From c749a717d02936b49f6213f8861e3c17b35abf67 Mon Sep 17 00:00:00 2001 From: Vernon Mauery Date: Mon, 27 Jan 2020 15:13:10 -0800 Subject: [PATCH] Initialize the BMC/host mailbox at reset time When the BMC comes out of reset, the mailbox registers need to be set so the communications with the host can start properly. Tested: boot the BMC and take note that the mailbox registers are no longer random garbage. Signed-off-by: Vernon Mauery --- board/aspeed/ast-g5/ast-g5-intel.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/board/aspeed/ast-g5/ast-g5-intel.c b/board/aspeed/ast-g5/ast-g5-intel.c index 4b017269f9..6c193d8afb 100644 --- a/board/aspeed/ast-g5/ast-g5-intel.c +++ b/board/aspeed/ast-g5/ast-g5-intel.c @@ -629,6 +629,33 @@ static void pwm_init(void) writel(val, PWM_BASE_ADDR + PWM_CONTROL); } +#define AST_MBX_COUNT 16 +#define MB_HINIT_BP_REG1 (0) +#define MB_HINIT_BP_REG2 (1) // reserved for future bit definition. +#define MB_FW_MJ_VER_REG (2) +#define MB_FW_MN_VER_REG (3) +#define MB_HINIT_ERR_REG (4) +#define MB_BOOTL_BP_REG1 (5) +#define MB_BOOTL_BP_REG2 (6) // tracks which image selected +#define MB_BOOTL_ERR_REG (7) +#define MB_RUNTM_BP_REG1 (8) +#define MB_RUNTM_BP_REG2 (9) // reserved for future bit definition. +#define MB_RUNTM_ERR_REG (10) +static void mailbox_init(void) +{ + /* clear out default mbox values */ + int i; + for (i = 0; i < AST_MBX_COUNT; i++) + { + writel(0, AST_MBX_BASE + 4 * i); + } + /* by the time this is called, all the hardware init is done + * so we can mark that as complete */ + writel(0xff, AST_MBX_BASE + 4 * MB_HINIT_BP_REG1); + /* mark progress up through booting linux */ + writel(0x1f, AST_MBX_BASE + 4 * MB_BOOTL_BP_REG1); +} + extern void espi_init(void); extern void kcs_init(void); void ast_g5_intel(void) @@ -638,6 +665,7 @@ void ast_g5_intel(void) SCU_MISC_UART_DEBUG_DIS, AST_SCU_MISC1_CTRL); uart_init(); + mailbox_init(); pwm_init(); gpio_init(gpio_table, ARRAY_SIZE(gpio_table)); espi_init();