From a7c85034b4a0a7e061930f27a6ec561d23d97cc6 Mon Sep 17 00:00:00 2001 From: Jae Hyun Yoo Date: Fri, 3 Jan 2020 15:14:09 -0800 Subject: [PATCH] AST2600: Adjust default GPIO settings - Disabled GPIOC3 to prevent unexpected host failures. - Fixed GPIOC5, GPIOD4, GPIOG6, GPIOI0~7, GPIOL6~7 and GPIO_S3 directions and default values. - Disabled internal pull-down of GPIOB6. - Disabled HBLED. Signed-off-by: Jae Hyun Yoo --- board/aspeed/ast2600_intel/intel.c | 74 ++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c index d1ac8651ac6c..14a20b27e178 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c @@ -162,6 +162,78 @@ static void sgpio_init(void) SCU_BASE | SCU_414); } +#define SCU_410 0x410 /* Multi-function Pin Control #4 */ +#define SCU_69C 0x69C /* Multi-function Pin Control #27 */ +#define SCU_69C_HBLED_EN BIT(31) +#define GPIO_000 0x000 /* GPIO A/B/C/D Value */ +#define GPIO_004 0x004 /* GPIO A/B/C/D Direction */ +#define GPIO_020 0x020 /* GPIO E/F/G/H Value */ +#define GPIO_024 0x024 /* GPIO E/F/G/H Direction */ +#define GPIO_070 0x070 /* GPIO I/J/K/L Value */ +#define GPIO_074 0x074 /* GPIO I/J/K/L Direction */ +#define GPIO_080 0x080 /* GPIO Q/R/S/T Value */ +#define GPIO_084 0x084 /* GPIO Q/R/S/T Direction */ + +static void set_gpio_default_state(void) +{ + /* Default setting of Y23 pad in AST2600 A1 is HBLED so disable it. */ + writel(readl(SCU_BASE | SCU_69C) & ~SCU_69C_HBLED_EN, + SCU_BASE | SCU_69C); + +#define SCU_410_RGMII3TXD1 BIT(19) +#define GPIO_C3 BIT(19) + + /* + * Set GPIOC3 as an output with value high explicitly since it doesn't + * have an external pull up. It uses direct register access because + * it's called from board_early_init_f(). + */ + writel(readl(SCU_BASE | SCU_410) & ~SCU_410_RGMII3TXD1, + SCU_BASE | SCU_410); + writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_C3, + AST_GPIO_BASE | GPIO_004); + writel(readl(AST_GPIO_BASE | GPIO_000) | GPIO_C3, + AST_GPIO_BASE | GPIO_000); + +#define SCU_610 0x610 /* Disable internal pull-down #0 */ +#define SCU_610_GPIOB6 BIT(14) + writel(readl(SCU_BASE | SCU_610) | SCU_610_GPIOB6, SCU_BASE | SCU_610); + + /* + * GPIO C5 has a connection between BMC(3.3v) and CPU(1.0v) so if we + * set it as an logic high output, it will be clipped by a protection + * circuit in the CPU and eventually the signal will be detected as + * logic low. So we leave this GPIO as an input so that the signal + * can be pulled up by a CPU internal resister. The signal will be + * 1.0v logic high resultingy. + */ +#define GPIO_C5 BIT(21) + writel(readl(AST_GPIO_BASE | GPIO_004) & ~GPIO_C5, + AST_GPIO_BASE | GPIO_004); + + /* + * Set GPIOD4 as an output with value low explicitly to set the + * default SPD mux path to CPU and DIMMs. + */ +#define GPIO_D4 BIT(28) + writel(readl(AST_GPIO_BASE | GPIO_004) | GPIO_D4, + AST_GPIO_BASE | GPIO_004); + writel(readl(AST_GPIO_BASE | GPIO_000) & ~GPIO_D4, + AST_GPIO_BASE | GPIO_000); + + /* GPIO G6 is also an open-drain output so set it as an input. */ +#define GPIO_G6 BIT(22) + writel(readl(AST_GPIO_BASE | GPIO_024) & ~GPIO_G6, + AST_GPIO_BASE | GPIO_024); + + /* Set GPIO S3 as push-pull output high */ +#define GPIO_S3 BIT(19) + writel(readl(AST_GPIO_BASE + GPIO_084) | GPIO_S3, + AST_GPIO_BASE + GPIO_084); + writel(readl(AST_GPIO_BASE + GPIO_080) | GPIO_S3, + AST_GPIO_BASE + GPIO_080); +} + static void timer_handler(void *regs) { printf("+"); @@ -175,6 +247,8 @@ int board_early_init_f(void) * I am not sure if it actually does anything... */ arch_interrupt_init_early(); + set_gpio_default_state(); + gpio_passthru_init(); port80h_snoop_init(); -- 2.17.1