From fd0768e6a63a25fdc87596036a5cbf82a88a1eb6 Mon Sep 17 00:00:00 2001 From: arun-pm Date: Fri, 29 Nov 2019 00:19:09 +0530 Subject: [PATCH] SPI Quad IO Mode This commit adds quad IO mode in SPI driver for AST2600. Note:- Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode. --- arch/arm/dts/ast2600-intel.dts | 6 ++---- drivers/mtd/spi/spi-nor-ids.c | 7 ++++++- drivers/spi/aspeed_spi.c | 18 +++++++++++++++++- 3 files changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts index 9a15e204f83b..1f14753056ee 100644 --- a/arch/arm/dts/ast2600-intel.dts +++ b/arch/arm/dts/ast2600-intel.dts @@ -120,16 +120,14 @@ &fmc { status = "okay"; -#if 0 pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fmcquad_default>; -#endif flash@0 { compatible = "spi-flash", "sst,w25q256"; status = "okay"; spi-max-frequency = <40000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; }; }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3b0a910d3fca..d6b949170570 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -164,7 +164,12 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, + /* Removed n25q00 Quad I/O support for the time being due to clock issue with chip 'Micron 8UA15 - rw182 (128MB)' + * while enabling Quad I/O mode. As this chip is default shipped in platforms, marking it + * as Not supported for the time being. Once all chips are replaced with the new model, this can be enabled + * back(Note:- Certain other chips having same name(n25q00) but different part number has no issues). + */ + { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, #endif diff --git a/drivers/spi/aspeed_spi.c b/drivers/spi/aspeed_spi.c index 18d4c2fa098e..6efb8c4e3c65 100644 --- a/drivers/spi/aspeed_spi.c +++ b/drivers/spi/aspeed_spi.c @@ -17,6 +17,9 @@ #define ASPEED_SPI_MAX_CS 3 #define FLASH_CALIBRATION_LEN 0x400 +#define AST2600A0 0x05000303 +#define AST2600A0_MAX_FREQ 40000000 +#define AST_MAX_FREQ 100000000 struct aspeed_spi_regs { u32 conf; /* 0x00 CE Type Setting */ @@ -1037,6 +1040,19 @@ static int aspeed_spi_bind(struct udevice *bus) return 0; } +static int aspeed_get_max_freq(void) +{ + u32 rev_id = readl(ASPEED_REVISION_ID); + + /*Limit max spi frequency less than 50MHz on AST2600-A0 due + * to FWSPICLK signal quality issue. + */ + if(rev_id == AST2600A0) + return AST2600A0_MAX_FREQ; + else + return AST_MAX_FREQ; +} + static int aspeed_spi_probe(struct udevice *bus) { struct resource res_regs, res_ahb; @@ -1067,7 +1083,7 @@ static int aspeed_spi_probe(struct udevice *bus) clk_free(&hclk); priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", - 100000000); + aspeed_get_max_freq()); priv->num_cs = dev_read_u32_default(bus, "num-cs", ASPEED_SPI_MAX_CS); -- 2.17.1