From f7671739c0d48994c3b6b90d08a75f0ba9e9a2ca Mon Sep 17 00:00:00 2001 From: Suryakanth Sekar Date: Thu, 18 Jun 2020 05:32:48 +0530 Subject: [PATCH] Apply WDT1-2 reset mask to reset needed controller Issue: BMC reset during BIOS serial port access causes BIOS hang. Root caused: BMC resetting the LPC controller during BMC warm reset. Which cause BIOS hang as BIOS cannot dump the BIOS serial data. Fix: WDT reset mask has been updated from default to proper value, such that controllers interacting with host will not be reset during wdt reset operation. This was missed earlier, causing BIOS to hang whenever BMC resets, as BIOS was accessing the serial port (LPC controller). De-coupling LPC controller will make sure BIOS serial port access is not disturbed. And also Reset mask is updated not to reset the following additionally on the default mask setting. eSPI controller reset causes system console lost connection, when BMC reset. 1. LPC controller 2. PWM controller 3. eSPI controller Quick Step to reproduce: Stop the BMC in uboot and add below bootcmd command setenv bootcmd "reset" Do the System power ON or System warm reset. For WDT2: boot the BMC and ran the /usr/bin/watch_dog_reset.sh Do the System Power ON or System warm reset. Tested: 1. Ran overnight continous BIOS and BMC warm reset on two SUTs. 2.Ran the TestApp which dump the BIOS serial port continously and do the BMC reset. 3.Stop the BMC in uboot and add below bootcmd command setenv bootcmd "reset" Do the System Power ON or System warm reset. 4.Ran Over night AC cycle test. Completed +1000 in two systems. 5.Stopped at u-boot. Issue protect off all command Issue erase all command. BMC should not hang and able to complete the "erase all" command Signed-off-by: Suryakanth Sekar Signed-off-by: Jae Hyun Yoo Signed-off-by: Kuiying Wang --- arch/arm/mach-aspeed/ast2600/platform.S | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S index 7e6787e5c6db..937ea0d7b9a0 100644 --- a/arch/arm/mach-aspeed/ast2600/platform.S +++ b/arch/arm/mach-aspeed/ast2600/platform.S @@ -64,6 +64,14 @@ #define AST_MAC2_BASE (0x1E680000) #define AST_MAC2_CTRL2 (AST_MAC2_BASE + 0x058) +#define AST_WDT1_BASE 0x1E785000 +#define AST_WDT1_RESET_MASK1 (AST_WDT1_BASE + 0x01C) +#define AST_WDT1_RESET_MASK2 (AST_WDT1_BASE + 0x020) + +#define AST_WDT2_BASE 0x1E785040 +#define AST_WDT2_RESET_MASK1 (AST_WDT2_BASE + 0x01C) +#define AST_WDT2_RESET_MASK2 (AST_WDT2_BASE + 0x020) + #define AST_GPIO_BASE (0x1E780000) #define AST_GPIOYZ_DATA_VALUE (AST_GPIO_BASE + 0x1E0) @@ -293,6 +301,20 @@ wait_lock: str r1, [r0] 2: + /* disable eSPI, LPC and PWM resets on WDT1 reset */ + ldr r0, =AST_WDT1_RESET_MASK2 + ldr r1, [r0] + ldr r2, =0x04002800 + bic r1, r2 + str r1, [r0] + + /* disable eSPI, LPC and PWM resets on WDT2 reset */ + ldr r0, =AST_WDT2_RESET_MASK2 + ldr r1, [r0] + ldr r2, =0x04002800 + bic r1, r2 + str r1, [r0] + /* PCIeRC/E2M8 power-on reset comes from SCU040 But SCU04018 default value is 0x0. It should be 0x1 to reset PCIeRC/E2M8.*/ -- 2.17.1