From 615d57c7c2a86df3ba19e0c1a201aa0d8042e38d Mon Sep 17 00:00:00 2001 From: Kuiying Wang Date: Thu, 25 Feb 2021 14:45:12 +0800 Subject: [PATCH] ast2600: Add Mailbox init function. Add Mailbox init function to make sure mailbox regs are clear when BMC reset. AST2600 A0 has 16 mailboxes. AST2600 A1 has 32 mailboxes. Tested: BMC could boot correctly and all the mailboxes clear ast# md 0x1e789200 1e789200: 00000000 00000000 00000000 00000000 ................ 1e789210: 00000000 00000000 00000000 00000000 ................ 1e789220: 00000000 00000000 00000000 00000000 ................ 1e789230: 00000000 00000000 00000000 00000000 ................ 1e789240: 00000000 00000000 00000000 00000000 ................ Signed-off-by: Vernon Mauery Signed-off-by: Kuiying Wang Signed-off-by: Jae Hyun Yoo --- board/aspeed/ast2600_intel/intel.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/board/aspeed/ast2600_intel/intel.c b/board/aspeed/ast2600_intel/intel.c index 17a21c746098..17d1b1952d4d 100644 --- a/board/aspeed/ast2600_intel/intel.c +++ b/board/aspeed/ast2600_intel/intel.c @@ -10,6 +10,9 @@ #define WATCHDOG_RESET_BIT BIT(20) #define BOOT_FAILURE_LIMIT 3 +#define SCU_014 0x014 /* Silicon Revision ID */ +#define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ + static int get_boot_failures(void) { return env_get_ulong("bootfailures", 10, 0); @@ -320,6 +323,25 @@ static void timer_callback(void *cookie) } } +#define AST_MBX_BASE 0x1e789200 +#define AST_MBX_COUNT_A0 16 +#define AST_MBX_COUNT 32 +static void mailbox_init(void) +{ + /* clear out default mbox values */ + int i, mbx_count; + + if (readl(SCU_BASE + SCU_014) == REV_ID_AST2600A0) + mbx_count = AST_MBX_COUNT_A0; + else + mbx_count = AST_MBX_COUNT; + + for (i = 0; i < mbx_count; i++) + { + writel(0, AST_MBX_BASE + 4 * i); + } +} + int board_early_init_f(void) { /* This is called before relocation; beware! */ @@ -333,6 +355,8 @@ int board_early_init_f(void) sgpio_init(); + mailbox_init(); + /* TODO: is it too late to enforce HW security registers? */ return 0; } @@ -469,8 +493,6 @@ extern void timer_enable(int n, u32 interval_us, interrupt_handler_t *handler, void *cookie); int board_late_init(void) { -#define SCU_014 0x014 /* Silicon Revision ID */ -#define REV_ID_AST2600A0 0x05000303 /* AST2600 A0 */ #define ONE_MSEC_IN_USEC 1000 char value[11]; u32 boot_failures; -- 2.17.1