From 89b5ebd26fc44b4bf820aa507bc88eec028ba218 Mon Sep 17 00:00:00 2001 From: Vernon Mauery Date: Wed, 16 May 2018 10:03:14 -0700 Subject: [PATCH] SGPIO DT and pinctrl fixup This commit fixes DT and pinctrl for SGPIO use. Signed-off-by: Vernon Mauery Signed-off-by: Jae Hyun Yoo --- arch/arm/boot/dts/aspeed-g4.dtsi | 56 +++++++++++------------------- arch/arm/boot/dts/aspeed-g5.dtsi | 3 +- arch/arm/boot/dts/aspeed-g6.dtsi | 15 ++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 48 ++++++++++++------------- 4 files changed, 60 insertions(+), 62 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index b875c0785833..e9fd66ab3099 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -254,6 +254,20 @@ #interrupt-cells = <2>; }; + sgpio: sgpio@1e780200 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2400-sgpio"; + reg = <0x1e780200 0x0100>; + interrupts = <40>; + interrupt-controller; + clocks = <&syscon ASPEED_CLK_APB>; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm_default>; + status = "disabled"; + }; + timer: timer@1e782000 { /* This timer is a Faraday FTTMR010 derivative */ compatible = "aspeed,ast2400-timer"; @@ -1227,44 +1241,14 @@ groups = "SD2"; }; - pinctrl_sgpmck_default: sgpmck_default { - function = "SGPMCK"; - groups = "SGPMCK"; - }; - - pinctrl_sgpmi_default: sgpmi_default { - function = "SGPMI"; - groups = "SGPMI"; - }; - - pinctrl_sgpmld_default: sgpmld_default { - function = "SGPMLD"; - groups = "SGPMLD"; - }; - - pinctrl_sgpmo_default: sgpmo_default { - function = "SGPMO"; - groups = "SGPMO"; - }; - - pinctrl_sgpsck_default: sgpsck_default { - function = "SGPSCK"; - groups = "SGPSCK"; - }; - - pinctrl_sgpsi0_default: sgpsi0_default { - function = "SGPSI0"; - groups = "SGPSI0"; - }; - - pinctrl_sgpsi1_default: sgpsi1_default { - function = "SGPSI1"; - groups = "SGPSI1"; + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; }; - pinctrl_sgpsld_default: sgpsld_default { - function = "SGPSLD"; - groups = "SGPSLD"; + pinctrl_sgps_default: sgps_default { + function = "SGPS"; + groups = "SGPS"; }; pinctrl_sioonctrl_default: sioonctrl_default { diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 452ec323534f..20b2eb8052b7 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -326,8 +326,7 @@ reg = <0x1e780200 0x0100>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; - ngpios = <8>; - bus-frequency = <12000000>; + bus-frequency = <1000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgpm_default>; status = "disabled"; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 54add29d8217..459070693aba 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -339,6 +339,21 @@ #interrupt-cells = <2>; }; + sgpio: sgpio@1e780500 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-sgpio"; + reg = <0x1e780500 0x0100>; + #interrupt-cells = <2>; + interrupts = ; + interrupt-controller; + bus-frequency = <1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgpm1_default>; + clocks = <&syscon ASPEED_CLK_APB1>; + status = "disabled"; + }; + rtc: rtc@1e781000 { compatible = "aspeed,ast2600-rtc"; reg = <0x1e781000 0x18>; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index bfed0e274643..10dadfd0e6e1 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -430,16 +430,22 @@ SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30)); SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31)); #define A14 48 -SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0)); +SIG_EXPR_LIST_DECL_SINGLE(A14, SGPSCK, SGPS, SIG_DESC_SET(SCU84, 0)); +PIN_DECL_1(A14, GPIOG0, SGPSCK); #define E13 49 -SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1)); +SIG_EXPR_LIST_DECL_SINGLE(E13, SGPSLD, SGPS, SIG_DESC_SET(SCU84, 1)); +PIN_DECL_1(E13, GPIOG1, SGPSLD); #define D13 50 -SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); +SIG_EXPR_LIST_DECL_SINGLE(D13, SGPSIO, SGPS, SIG_DESC_SET(SCU84, 2)); +PIN_DECL_1(D13, GPIOG2, SGPSIO); #define C13 51 -SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); +SIG_EXPR_LIST_DECL_SINGLE(C13, SGPSI1, SGPS, SIG_DESC_SET(SCU84, 3)); +PIN_DECL_1(C13, GPIOG3, SGPSI1); + +FUNC_GROUP_DECL(SGPS, A14, E13, D13, C13); #define B13 52 SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); @@ -613,16 +619,22 @@ FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20); FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20); #define J5 72 -SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8)); +SIG_EXPR_LIST_DECL_SINGLE(J5, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); +PIN_DECL_1(J5, GPIOJ0, SGPMCK); #define J4 73 -SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9)); +SIG_EXPR_LIST_DECL_SINGLE(J4, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); +PIN_DECL_1(J4, GPIOJ1, SGPMLD); #define K5 74 -SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10)); +SIG_EXPR_LIST_DECL_SINGLE(K5, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); +PIN_DECL_1(K5, GPIOJ2, SGPMO); #define J3 75 -SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11)); +SIG_EXPR_LIST_DECL_SINGLE(J3, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); +PIN_DECL_1(J3, GPIOJ3, SGPMI); + +FUNC_GROUP_DECL(SGPM, J5, J4, K5, J3); #define T4 76 SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12)); @@ -2234,14 +2246,8 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = { ASPEED_PINCTRL_GROUP(SALT4), ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD2), - ASPEED_PINCTRL_GROUP(SGPMCK), - ASPEED_PINCTRL_GROUP(SGPMI), - ASPEED_PINCTRL_GROUP(SGPMLD), - ASPEED_PINCTRL_GROUP(SGPMO), - ASPEED_PINCTRL_GROUP(SGPSCK), - ASPEED_PINCTRL_GROUP(SGPSI0), - ASPEED_PINCTRL_GROUP(SGPSI1), - ASPEED_PINCTRL_GROUP(SGPSLD), + ASPEED_PINCTRL_GROUP(SGPM), + ASPEED_PINCTRL_GROUP(SGPS), ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOPBI), ASPEED_PINCTRL_GROUP(SIOPBO), @@ -2389,14 +2395,8 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { ASPEED_PINCTRL_FUNC(SALT4), ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD2), - ASPEED_PINCTRL_FUNC(SGPMCK), - ASPEED_PINCTRL_FUNC(SGPMI), - ASPEED_PINCTRL_FUNC(SGPMLD), - ASPEED_PINCTRL_FUNC(SGPMO), - ASPEED_PINCTRL_FUNC(SGPSCK), - ASPEED_PINCTRL_FUNC(SGPSI0), - ASPEED_PINCTRL_FUNC(SGPSI1), - ASPEED_PINCTRL_FUNC(SGPSLD), + ASPEED_PINCTRL_FUNC(SGPM), + ASPEED_PINCTRL_FUNC(SGPS), ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOPBI), ASPEED_PINCTRL_FUNC(SIOPBO), -- 2.7.4