1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
|
From fc01155d6f78ab9940f1d1482b0df44addc5f313 Mon Sep 17 00:00:00 2001
From: Vikram Bodireddy <vikram.bodireddy@intel.com>
Date: Mon, 22 Feb 2021 17:22:16 +0530
Subject: [PATCH] ast2600-PFR-platform-EXTRST-reset-mask-selection
This commit will enable specific reset mask for EXTRST# signal.
On PFR platforms, EXTRST# signal is used by PFR CPLD to put BMC
in reset during firmware authentications, recovery and firmware
update flow, during which certain modules of BMC should be chosen
to be reset so that Host functionality would be intact.
Signed-off-by: Chalapathi Venkataramashetty <chalapathix.venkataramashetty@intel.com>
Signed-off-by: Vikram Bodireddy <vikram.bodireddy@intel.com>
---
arch/arm/mach-aspeed/ast2600/platform.S | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
index c65adff0d69a..3db7d993d3ca 100644
--- a/arch/arm/mach-aspeed/ast2600/platform.S
+++ b/arch/arm/mach-aspeed/ast2600/platform.S
@@ -39,6 +39,8 @@
#define AST_SCU_REV_ID (AST_SCU_BASE + 0x014)
#define AST_SCU_SYSRST_CTRL (AST_SCU_BASE + 0x040)
#define AST_SCU_SYSRST_CTRL_CLR (AST_SCU_BASE + 0x044)
+#define AST_SCU_EXTRST_SEL1 (AST_SCU_BASE + 0x060)
+#define AST_SCU_EXTRST_SEL2 (AST_SCU_BASE + 0x070)
#define AST_SCU_DEBUG_CTRL (AST_SCU_BASE + 0x0C8)
#define AST_SCU_DEBUG_CTRL2 (AST_SCU_BASE + 0x0D8)
#define AST_SCU_HPLL_PARAM (AST_SCU_BASE + 0x200)
@@ -304,6 +306,16 @@ wait_lock:
str r1, [r0]
2:
+ /* SCU060:EXTRST1# reset mask selection */
+ ldr r0, =AST_SCU_EXTRST_SEL1
+ ldr r1, =0x6FF1FF1
+ str r1, [r0]
+
+ /* SCU070:EXTRST2# reset mask selection */
+ ldr r0, =AST_SCU_EXTRST_SEL2
+ ldr r1, =0x3FFFFF3
+ str r1, [r0]
+
/* disable eSPI, LPC and PWM resets on WDT1 reset */
ldr r0, =AST_WDT1_RESET_MASK2
ldr r1, [r0]
--
2.17.1
|
