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From cd13ae4e64d57af84dc98ff6c8d5b31661bc450d Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Tue, 8 Jan 2019 13:33:15 -0800
Subject: [PATCH] Enable PCIe L1 support
This commit enables PCIe L1 support using magic registers.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
arch/arm/mach-aspeed/ast2600/platform.S | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
index 3db7d993d3ca..e2fcb732b6a6 100644
--- a/arch/arm/mach-aspeed/ast2600/platform.S
+++ b/arch/arm/mach-aspeed/ast2600/platform.S
@@ -349,6 +349,20 @@ wait_lock:
movt r1, #0x0000
str r1, [r0]
+ /* enable PCIe L1 support */
+ ldr r0, =0x1e6ed07c
+ ldr r1, =0xa8
+ str r1, [r0]
+ ldr r0, =0x1e6ed010
+ ldr r1, =0x27040fe1
+ str r1, [r0]
+ ldr r0, =0x1e6ed068
+ ldr r1, =0xc81f0a
+ str r1, [r0]
+ ldr r0, =0x1e6ed07c
+ mov r1, #0
+ str r1, [r0]
+
/* MMIO decode setting */
ldr r0, =AST_SCU_MMIO_DEC_SET
mov r1, #0x2000
--
2.17.1
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