1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
|
From 8534fb50dfe7c4e1c042843ded54c4ed23ee7bc2 Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Tue, 8 Jan 2019 13:33:15 -0800
Subject: [PATCH] Enable PCIe L1 support
This commit enables PCIe L1 support using magic registers.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
arch/arm/mach-aspeed/ast2600/platform.S | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S
index d7115c96f117..803ff94c4fc0 100644
--- a/arch/arm/mach-aspeed/ast2600/platform.S
+++ b/arch/arm/mach-aspeed/ast2600/platform.S
@@ -329,6 +329,20 @@ wait_lock:
bic r1, r2
str r1, [r0]
+ /* enable PCIe L1 support */
+ ldr r0, =0x1e6ed07c
+ ldr r1, =0xa8
+ str r1, [r0]
+ ldr r0, =0x1e6ed010
+ ldr r1, =0x27040fe1
+ str r1, [r0]
+ ldr r0, =0x1e6ed068
+ ldr r1, =0xc81f0a
+ str r1, [r0]
+ ldr r0, =0x1e6ed07c
+ mov r1, #0
+ str r1, [r0]
+
/* MMIO decode setting */
ldr r0, =AST_SCU_MMIO_DEC_SET
mov r1, #0x2000
--
2.17.1
|
