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From 5f2a7c03c877454eb78a406934abf6b7d05e40a6 Mon Sep 17 00:00:00 2001
From: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Date: Thu, 6 Dec 2018 18:49:04 -0800
Subject: [PATCH] Add support for Macronix and Micron 1Gbits SPI flash
Quick fix to support Macronix and Micron 1Gbits SPI.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
---
arch/arm/mach-aspeed/flash.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/mach-aspeed/flash.c b/arch/arm/mach-aspeed/flash.c
index f9f1345523d4..abc0420176a6 100644
--- a/arch/arm/mach-aspeed/flash.c
+++ b/arch/arm/mach-aspeed/flash.c
@@ -79,6 +79,8 @@ flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips info */
#define MX25L12805D 0x1820C2
#define MX25L25635E 0x1920C2
#define MX66L51235F 0x1A20C2
+#define MX66L1G45G 0x1B20C2
+#define MT25QL01GB 0x21BA20
#define SST25VF016B 0x4125bf
#define SST25VF064C 0x4b25bf
#define SST25VF040B 0x8d25bf
@@ -977,6 +979,36 @@ static ulong flash_get_size (ulong base, flash_info_t *info)
#endif
break;
+ case MT25QL01GB:
+ case MX66L1G45G:
+ erase_region_size = 0x10000;
+ info->readcmd = 0x0b;
+ info->dualport = 0;
+ info->dummybyte = 1;
+ info->buffersize = 256;
+ WriteClk = 50;
+ EraseClk = 20;
+ ReadClk = 50;
+#if 1
+ info->sector_count = 2048;
+ info->size = 0x4000000;
+ info->address32 = 1;
+#if defined(CONFIG_FLASH_SPIx2_Dummy)
+ info->readcmd = 0xbb;
+ info->dummybyte = 1;
+ info->dualport = 1;
+ info->iomode = IOMODEx2_dummy;
+#elif defined(CONFIG_FLASH_SPIx4_Dummy)
+ info->readcmd = 0xeb;
+ info->dummybyte = 3;
+ info->dualport = 0;
+ info->iomode = IOMODEx4_dummy;
+ info->quadport = 1;
+ info->dummydata = 0xaa;
+#endif
+#endif
+ break;
+
case MX25L12805D:
info->sector_count = 256;
info->size = 0x1000000;
--
2.7.4
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