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From 769b30d1b5463291ddffd46f6039321d42f80417 Mon Sep 17 00:00:00 2001
From: James Feist <james.feist@linux.intel.com>
Date: Mon, 5 Nov 2018 15:38:19 -0800
Subject: [PATCH 1/1] Leave GPIOE in passthrough after boot
This is a temporary patch that seems to leave exported
gpio in passthrough mode. It's hard to understand why this
works because all the macros are _very_ confusing, but
SIG_DESC_SET is equal to SIG_DESC_BIT(arg1, arg2, 1) so as
a test I used SIG_DESC_BIT set to 0 for SCU8C and I noticed
the correct result for exported gpios. As of today I'm unsure
why setting 0 results in the bit being 1 and vise versa, but
as this is only a short-term fix, I don't think we really care.
This is not a long term fix, but it was a quick and easy
change that can get us the correct result in the short term.
Signed-off-by: James Feist <james.feist@linux.intel.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 8 ++++----
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 0c89647f166f..386ae967835d 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -246,7 +246,7 @@ FUNC_GROUP_DECL(GPID6, G18, C21);
FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
-#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
+#define GPIE0_DESC SIG_DESC_BIT(SCU8C, 12, 0)
#define B20 32
SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
@@ -266,7 +266,7 @@ FUNC_GROUP_DECL(NDCD3, C20);
FUNC_GROUP_DECL(GPIE0, B20, C20);
-#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
+#define GPIE2_DESC SIG_DESC_BIT(SCU8C, 13, 0)
#define F18 34
SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
--
2.17.1
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