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From 01453aca6478379bef05095f64ed79509da3a5ca Mon Sep 17 00:00:00 2001
From: Nagaraju Mekala <nmekala@xilix.com>
Date: Mon, 18 Jul 2016 12:24:28 +0530
Subject: [PATCH 09/52] Add new bit-field instructions
This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged
Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
Conflicts:
opcodes/microblaze-dis.c
---
gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
opcodes/microblaze-dis.c | 20 +++++++++--
opcodes/microblaze-opc.h | 12 ++++++-
opcodes/microblaze-opcm.h | 6 +++-
4 files changed, 104 insertions(+), 5 deletions(-)
Index: gdb-9.2/opcodes/microblaze-dis.c
===================================================================
--- gdb-9.2.orig/opcodes/microblaze-dis.c
+++ gdb-9.2/opcodes/microblaze-dis.c
@@ -91,7 +91,19 @@ get_field_imm5_mbar (struct string_buf *
}
static char *
-get_field_rfsl (struct string_buf *buf, long instr)
+get_field_imm5width (struct string_buf *buf, long instr)
+{
+ char *p = strbuf (buf);
+
+ if (instr & 0x00004000)
+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
+ else
+ sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
+ return p;
+}
+
+static char *
+get_field_rfsl (struct string_buf *buf,long instr)
{
char *p = strbuf (buf);
@@ -425,7 +437,11 @@ print_insn_microblaze (bfd_vma memaddr,
/* For mbar 16 or sleep insn. */
case INST_TYPE_NONE:
break;
- /* For tuqula instruction */
+ /* For bit field insns. */
+ case INST_TYPE_RD_R1_IMM5_IMM5:
+ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
+ break;
+ /* For tuqula instruction */
case INST_TYPE_RD:
print_func (stream, "\t%s", get_field_rd (&buf, inst));
break;
Index: gdb-9.2/opcodes/microblaze-opc.h
===================================================================
--- gdb-9.2.orig/opcodes/microblaze-opc.h
+++ gdb-9.2/opcodes/microblaze-opc.h
@@ -59,6 +59,9 @@
/* For mbar. */
#define INST_TYPE_IMM5 20
+/* For bsefi and bsifi */
+#define INST_TYPE_RD_R1_IMM5_IMM5 21
+
#define INST_TYPE_NONE 25
@@ -89,7 +92,9 @@
#define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */
#define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */
#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */
+#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */
#define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */
+#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */
#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */
#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */
#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */
@@ -102,7 +107,7 @@
#define DELAY_SLOT 1
#define NO_DELAY_SLOT 0
-#define MAX_OPCODES 299
+#define MAX_OPCODES 301
struct op_code_struct
{
@@ -159,6 +164,8 @@ struct op_code_struct
{"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
{"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
{"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
+ {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+ {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
{"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
{"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
{"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
#define MIN_IMM5 ((int) 0x00000000)
#define MAX_IMM5 ((int) 0x0000001f)
+#define MIN_IMM_WIDTH ((int) 0x00000001)
+#define MAX_IMM_WIDTH ((int) 0x00000020)
+
#endif /* MICROBLAZE_OPC */
Index: gdb-9.2/opcodes/microblaze-opcm.h
===================================================================
--- gdb-9.2.orig/opcodes/microblaze-opcm.h
+++ gdb-9.2/opcodes/microblaze-opcm.h
@@ -29,7 +29,7 @@ enum microblaze_instr
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
- ncget, ncput, muli, bslli, bsrai, bsrli, mului,
+ ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
/* 'or/and/xor' are C++ keywords. */
microblaze_or, microblaze_and, microblaze_xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
@@ -129,6 +129,7 @@ enum microblaze_instr_type
#define RB_LOW 11 /* Low bit for RB. */
#define IMM_LOW 0 /* Low bit for immediate. */
#define IMM_MBAR 21 /* low bit for mbar instruction. */
+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
#define RD_MASK 0x03E00000
#define RA_MASK 0x001F0000
@@ -141,6 +142,9 @@ enum microblaze_instr_type
/* Imm mask for mbar. */
#define IMM5_MBAR_MASK 0x03E00000
+/* Imm mask for extract/insert width. */
+#define IMM5_WIDTH_MASK 0x000007C0
+
/* FSL imm mask for get, put instructions. */
#define RFSL_MASK 0x000000F
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