diff options
| author | Andrew Geissler <geissonator@yahoo.com> | 2023-03-31 17:57:23 +0300 |
|---|---|---|
| committer | Andrew Geissler <geissonator@yahoo.com> | 2023-03-31 18:06:58 +0300 |
| commit | 2daf84b2d486da0b21344da999553c8fa1228195 (patch) | |
| tree | 04a2402d258019103ad1a4c9da71d78301cd5d42 /meta-arm/meta-arm-bsp/recipes-bsp/u-boot | |
| parent | ced6278a187ae9eefe16fe59398f714857b7f76e (diff) | |
| download | openbmc-2daf84b2d486da0b21344da999553c8fa1228195.tar.xz | |
subtree updates: raspberrypi security arm
meta-arm: eb9c47a4e1..9b6c8c95e4:
Abdellatif El Khlifi (1):
CI: append classes to INHERIT in the common fvp.yml
Adam Johnston (1):
arm-bsp/linux-yocto: Update N1SDP PCI quirk patch
Jon Mason (10):
CI: add yml files for defaults
CI: add support for dev kernel, rt kernel, and poky-tiny
arm-bsp/fvp-base: update to u-boot 2023.01
arm-bsp/fvp-base-arm32: remove support
ci: add external-toolchain to qemuarm-secureboot
arm-bsp/optee: remove unused recipes
arm/optee: optee-os include cleanup
arm/optee-os: update to 3.20.0
arm/edk2: update version and relocate edk2-basetools to be with edk2
arm-bsp/fvp-base: Add edk2 build testing
Ross Burton (7):
arm-bsp/linux-arm64-ack: update Upstream-Status tags
CI: add CI_CLEAN_REPOS variable to allow cleaning the repo reference cache
arm/scp-firmware: fix up whitespace
arm/scp-firmware: enable verbose builds
arm/scp-firmware: remove textrel from INSANE_SKIP
arm/scp-firmware: improve debug packaging
CI: mask poky's llvm if we're using clang
Rui Miguel Silva (1):
arm-bsp/optee: bump corstone1000 to v3.20
Satish Kumar (1):
arm-bsp/corstone1000: new gpt based disk layout and fwu metadata
Xueliang Zhong (1):
arm-bsp/n1sdp: update to linux yocto kernel 6.1
meta-security: c06b9a18a6..a397a38ed9:
Armin Kuster (16):
openscap: update to 1.3.6
openscap: update to 1.3.7
openscap git: add DEFAULT_PREFERENCE
python3-fail2ban: update to 1.0.2
python3-privacyidea: update to 3.8.1
libhtp: update to 0.5.42
lkrg-modules: update to 0.9.6
chkrootkit: update to 0.57
fscrypt: update to 1.1.0
libmspack: update to 1.11
firejail: update 0.9.72
suricata: update to 6.0.10
apparmor: update to 3.1.3
krill: update 0.12.3
cryptmout: update to 6.2.0
packagegroup-core-security: refactor the inclusion of krill
Eero Aaltonen (1):
dm-verity-img.bbclass: fix syntax warning
Jose Quaresma (3):
meta-hardening/layer: lower the priority from 10 to 6
meta-security-compliance/layer: lower the priority from 10 to 6
meta-tpm/layer: lower the priority from 10 to 6
Kevin Hao (1):
dm-verity-img.bbclass: Fix the hash offset alignment issue
Mikko Rapeli (1):
ima-evm-utils: disable documentation from build
Paul Gortmaker (3):
dm-verity: update beaglebone wic to match meta-yocto
dm-verity: add basic non-arch/non-BSP yocto specific settings
dm-verity: document board specifics for Beaglebone Black
Peter Marko (1):
tpm2-tss: correct CVE product
meta-raspberrypi: e15b876155..3afdbbf782:
Carlos Alberto Lopez Perez (1):
mesa-demos: enable build with userland graphics drivers.
Khem Raj (6):
linux-raspberrypi: Add recipes for 6.1 kernel
psplash: Make psplash wait for the framebuffer to be ready
rpi-default-versions: Use 6.1 kernel as default
gstreamer1.0-plugins-bad: Drop gpl packageconfig
rpidistro-ffmpeg: Pin to use gcc always
rpidistro-vlc: Fix build with clang16
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: Ie6e60085306d31972098b87738eb550e5140b92a
Diffstat (limited to 'meta-arm/meta-arm-bsp/recipes-bsp/u-boot')
22 files changed, 1757 insertions, 303 deletions
diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0027-drivers-nvmxip-introduce-NVM-XIP-block-storage-emula.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0027-drivers-nvmxip-introduce-NVM-XIP-block-storage-emula.patch new file mode 100644 index 0000000000..30baf6826f --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0027-drivers-nvmxip-introduce-NVM-XIP-block-storage-emula.patch @@ -0,0 +1,595 @@ +From 1d277bc8c275fae8e8cd400344bdacbdce3a6b46 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Tue, 13 Dec 2022 19:47:49 +0000 +Subject: [PATCH 27/43] drivers/nvmxip: introduce NVM XIP block storage + emulation + +add block storage emulation for NVM XIP flash devices + +Some paltforms such as Corstone-1000 need to see NVM XIP raw flash +as a block storage device with read only capability. + +Here NVM flash devices are devices with addressable +memory (e.g: QSPI NOR flash). + +The implementation is generic and can be used by different platforms. + +Two drivers are provided as follows. + + nvmxip-blk : + + a generic block driver allowing to read from the XIP flash + + nvmxip_qspi : + + The driver probed with the DT and parent of the nvmxip-blk device. + nvmxip_qspi can be reused by other platforms. If the platform + has custom settings to apply before using the flash, then the platform + can provide its own parent driver belonging to UCLASS_NVMXIP and reuse + nvmxip-blk. The custom driver can be implmented like nvmxip_qspi in + addition to the platform custom settings. + +Platforms can use multiple NVM XIP devices at the same time by defining a +DT node for each one of them. + +For more details please refer to doc/develop/driver-model/nvmxip.rst + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + MAINTAINERS | 7 ++ + doc/develop/driver-model/index.rst | 1 + + doc/develop/driver-model/nvmxip.rst | 70 ++++++++++++ + doc/device-tree-bindings/nvmxip/nvmxip.txt | 56 +++++++++ + drivers/Kconfig | 2 + + drivers/Makefile | 1 + + drivers/block/blk-uclass.c | 1 + + drivers/nvmxip/Kconfig | 17 +++ + drivers/nvmxip/Makefile | 7 ++ + drivers/nvmxip/nvmxip-uclass.c | 13 +++ + drivers/nvmxip/nvmxip.c | 127 +++++++++++++++++++++ + drivers/nvmxip/nvmxip.h | 46 ++++++++ + drivers/nvmxip/nvmxip_qspi.c | 65 +++++++++++ + include/dm/uclass-id.h | 1 + + 14 files changed, 414 insertions(+) + create mode 100644 doc/develop/driver-model/nvmxip.rst + create mode 100644 doc/device-tree-bindings/nvmxip/nvmxip.txt + create mode 100644 drivers/nvmxip/Kconfig + create mode 100644 drivers/nvmxip/Makefile + create mode 100644 drivers/nvmxip/nvmxip-uclass.c + create mode 100644 drivers/nvmxip/nvmxip.c + create mode 100644 drivers/nvmxip/nvmxip.h + create mode 100644 drivers/nvmxip/nvmxip_qspi.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index 9feaf0502f5b..ba15dd02d58d 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1204,6 +1204,13 @@ F: cmd/nvme.c + F: include/nvme.h + F: doc/develop/driver-model/nvme.rst + ++NVMXIP ++M: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++S: Maintained ++F: doc/develop/driver-model/nvmxip.rst ++F: doc/device-tree-bindings/nvmxip/nvmxip.txt ++F: drivers/nvmxip/ ++ + NVMEM + M: Sean Anderson <seanga2@gmail.com> + S: Maintained +diff --git a/doc/develop/driver-model/index.rst b/doc/develop/driver-model/index.rst +index 7366ef818c5a..8e12bbd9366a 100644 +--- a/doc/develop/driver-model/index.rst ++++ b/doc/develop/driver-model/index.rst +@@ -20,6 +20,7 @@ subsystems + livetree + migration + nvme ++ nvmxip + of-plat + pci-info + pmic-framework +diff --git a/doc/develop/driver-model/nvmxip.rst b/doc/develop/driver-model/nvmxip.rst +new file mode 100644 +index 000000000000..91b24e4e50d2 +--- /dev/null ++++ b/doc/develop/driver-model/nvmxip.rst +@@ -0,0 +1,70 @@ ++.. SPDX-License-Identifier: GPL-2.0+ ++ ++NVM XIP Block Storage Emulation Driver ++======================================= ++ ++Summary ++------- ++ ++Non-Volatile Memory devices with addressable memory (e.g: QSPI NOR flash) could ++be used for block storage needs (e.g: parsing a GPT layout in a raw QSPI NOR flash). ++ ++The NVMXIP class provides this functionality and can be used for any 64-bit platform. ++ ++The NVMXIP class provides the following drivers: ++ ++ nvmxip-blk : ++ ++ A generic block driver allowing to read from the XIP flash. ++ The driver belongs to UCLASS_BLK. ++ The driver implemented by drivers/nvmxip/nvmxip.c ++ ++ nvmxip_qspi : ++ ++ The driver probed with the DT and parent of the nvmxip-blk device. ++ nvmxip_qspi can be reused by other platforms. If the platform ++ has custom settings to apply before using the flash, then the platform ++ can provide its own parent driver belonging to UCLASS_NVMXIP and reuse ++ nvmxip-blk. The custom driver can be implmented like nvmxip_qspi in ++ addition to the platform custom settings. ++ The nvmxip_qspi driver belongs to UCLASS_NVMXIP. ++ The driver implemented by drivers/nvmxip/nvmxip_qspi.c ++ ++ The implementation is generic and can be used by different platforms. ++ ++Supported hardware ++-------------------------------- ++ ++Any 64-bit plaform. ++ ++Configuration ++---------------------- ++ ++config NVMXIP ++ This option allows the emulation of a block storage device ++ on top of a direct access non volatile memory XIP flash devices. ++ This support provides the read operation. ++ This option provides the block storage driver nvmxip-blk which ++ handles the read operation. This driver is HW agnostic and can support ++ multiple flash devices at the same time. ++ ++config NVMXIP_QSPI ++ This option allows the emulation of a block storage device on top of a QSPI XIP flash. ++ Any platform that needs to emulate one or multiple XIP flash devices can turn this ++ option on to enable the functionality. NVMXIP config is selected automatically. ++ Platforms that need to add custom treatments before accessing to the flash, can ++ write their own driver (same as nvmxip_qspi in addition to the custom settings). ++ ++Device Tree nodes ++-------------------- ++ ++Multiple XIP flash devices can be used at the same time by describing them through DT ++nodes. ++ ++Please refer to the documentation of the DT binding at: ++ ++doc/device-tree-bindings/nvmxip/nvmxip.txt ++ ++Contributors ++------------ ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +diff --git a/doc/device-tree-bindings/nvmxip/nvmxip.txt b/doc/device-tree-bindings/nvmxip/nvmxip.txt +new file mode 100644 +index 000000000000..7c4b03f66b57 +--- /dev/null ++++ b/doc/device-tree-bindings/nvmxip/nvmxip.txt +@@ -0,0 +1,56 @@ ++Specifying NVMXIP information for devices ++====================================== ++ ++NVM XIP flash device nodes ++--------------------------- ++ ++Each flash device should have its own node. ++ ++Each node must specify the following fields: ++ ++1) ++ compatible = "nvmxip,qspi"; ++ ++This allows to bind the flash device with the nvmxip_qspi driver ++If a platform has its own driver, please provide your own compatible ++string. ++ ++2) ++ reg = <0x0 0x08000000 0x0 0x00200000>; ++ ++The start address and size of the flash device. The values give here are an ++example (when the cell size is 2). ++ ++When cell size is 1, the reg field looks like this: ++ ++ reg = <0x08000000 0x00200000>; ++ ++3) ++ ++ lba_shift = <9>; ++ ++The number of bit shifts used to calculate the size in bytes of one block. ++In this example the block size is 1 << 9 = 2 ^ 9 = 512 bytes ++ ++4) ++ ++ lba = <4096>; ++ ++The number of blocks. ++ ++Example of multiple flash devices ++---------------------------------------------------- ++ ++ nvmxip-qspi1@08000000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x0 0x08000000 0x0 0x00200000>; ++ lba_shift = <9>; ++ lba = <4096>; ++ }; ++ ++ nvmxip-qspi2@08200000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x0 0x08200000 0x0 0x00100000>; ++ lba_shift = <9>; ++ lba = <2048>; ++ }; +diff --git a/drivers/Kconfig b/drivers/Kconfig +index e51f0547c3da..d425ff1e76c7 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -78,6 +78,8 @@ source "drivers/net/Kconfig" + + source "drivers/nvme/Kconfig" + ++source "drivers/nvmxip/Kconfig" ++ + source "drivers/pci/Kconfig" + + source "drivers/pci_endpoint/Kconfig" +diff --git a/drivers/Makefile b/drivers/Makefile +index f0a7530295c5..fb1b62cbd6ff 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -89,6 +89,7 @@ obj-$(CONFIG_FWU_MDATA) += fwu-mdata/ + obj-y += misc/ + obj-$(CONFIG_MMC) += mmc/ + obj-$(CONFIG_NVME) += nvme/ ++obj-$(CONFIG_NVMXIP) += nvmxip/ + obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/ + obj-y += dfu/ + obj-$(CONFIG_PCH) += pch/ +diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c +index c69fc4d51829..e8ab576c3253 100644 +--- a/drivers/block/blk-uclass.c ++++ b/drivers/block/blk-uclass.c +@@ -28,6 +28,7 @@ static struct { + { UCLASS_AHCI, "sata" }, + { UCLASS_HOST, "host" }, + { UCLASS_NVME, "nvme" }, ++ { UCLASS_NVMXIP, "nvmxip" }, + { UCLASS_EFI_MEDIA, "efi" }, + { UCLASS_EFI_LOADER, "efiloader" }, + { UCLASS_VIRTIO, "virtio" }, +diff --git a/drivers/nvmxip/Kconfig b/drivers/nvmxip/Kconfig +new file mode 100644 +index 000000000000..6a23acaf1895 +--- /dev/null ++++ b/drivers/nvmxip/Kconfig +@@ -0,0 +1,17 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# Copyright (C) 2022, Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ ++config NVMXIP ++ bool "NVM XIP devices support" ++ select BLK ++ help ++ This option allows the emulation of a block storage device ++ on top of a direct access non volatile memory XIP flash devices. ++ This support provides the read operation. ++ ++config NVMXIP_QSPI ++ bool "QSPI XIP support" ++ select NVMXIP ++ help ++ This option allows the emulation of a block storage device on top of a QSPI XIP flash +diff --git a/drivers/nvmxip/Makefile b/drivers/nvmxip/Makefile +new file mode 100644 +index 000000000000..d8ad2a160b47 +--- /dev/null ++++ b/drivers/nvmxip/Makefile +@@ -0,0 +1,7 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2022 ++# Abdellatif El Khlifi, Arm Limited, abdellatif.elkhlifi@arm.com. ++ ++obj-y += nvmxip-uclass.o nvmxip.o ++obj-$(CONFIG_NVMXIP_QSPI) += nvmxip_qspi.o +diff --git a/drivers/nvmxip/nvmxip-uclass.c b/drivers/nvmxip/nvmxip-uclass.c +new file mode 100644 +index 000000000000..0f7e47b8af86 +--- /dev/null ++++ b/drivers/nvmxip/nvmxip-uclass.c +@@ -0,0 +1,13 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#include <common.h> ++#include <dm.h> ++ ++UCLASS_DRIVER(nvmxip) = { ++ .name = "nvmxip", ++ .id = UCLASS_NVMXIP, ++}; +diff --git a/drivers/nvmxip/nvmxip.c b/drivers/nvmxip/nvmxip.c +new file mode 100644 +index 000000000000..6ba48183c575 +--- /dev/null ++++ b/drivers/nvmxip/nvmxip.c +@@ -0,0 +1,127 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <dm/device-internal.h> ++#include "nvmxip.h" ++ ++static u32 nvmxip_bdev_max_devs; ++ ++static int nvmxip_mmio_rawread(const phys_addr_t address, u64 *value) ++{ ++ *value = readq(address); ++ return 0; ++} ++ ++static ulong nvmxip_blk_read(struct udevice *udev, lbaint_t blknr, lbaint_t blkcnt, void *buffer) ++{ ++ struct nvmxip_blk_priv *bpriv_data = dev_get_priv(udev); ++ struct blk_desc *desc = dev_get_uclass_plat(udev); ++ ++ /* size of 1 block */ ++ /* number of the u64 words to read */ ++ u32 qwords = (blkcnt * desc->blksz) / sizeof(u64); ++ /* physical address of the first block to read */ ++ phys_addr_t blkaddr = bpriv_data->pplat_data->phys_base + blknr * desc->blksz; ++ u64 *virt_blkaddr; ++ u64 *pdst = buffer; ++ u32 qdata_idx; ++ ++ if (!pdst) ++ return -EINVAL; ++ ++ pr_debug("[%s]: reading from blknr: %lu , blkcnt: %lu\n", udev->name, blknr, blkcnt); ++ ++ virt_blkaddr = map_sysmem(blkaddr, 0); ++ ++ /* assumption: the data is virtually contiguous */ ++ ++ for (qdata_idx = 0 ; qdata_idx < qwords ; qdata_idx++) ++ nvmxip_mmio_rawread((phys_addr_t)(virt_blkaddr + qdata_idx), pdst++); ++ ++ pr_debug("[%s]: src[0]: 0x%llx , dst[0]: 0x%llx , src[-1]: 0x%llx , dst[-1]: 0x%llx\n", ++ udev->name, ++ *virt_blkaddr, ++ *(u64 *)buffer, ++ *(u64 *)((u8 *)virt_blkaddr + desc->blksz * blkcnt - sizeof(u64)), ++ *(u64 *)((u8 *)buffer + desc->blksz * blkcnt - sizeof(u64))); ++ ++ unmap_sysmem(virt_blkaddr); ++ ++ return blkcnt; ++} ++ ++static int nvmxip_blk_probe(struct udevice *udev) ++{ ++ struct nvmxip_priv *ppriv_data = dev_get_priv(udev->parent); ++ struct blk_desc *desc = dev_get_uclass_plat(udev); ++ struct nvmxip_blk_priv *bpriv_data = dev_get_priv(udev); ++ ++ bpriv_data->bdev = udev; ++ bpriv_data->pplat_data = ppriv_data->plat_data; ++ desc->lba = bpriv_data->pplat_data->lba; ++ desc->log2blksz = bpriv_data->pplat_data->lba_shift; ++ desc->blksz = 1 << bpriv_data->pplat_data->lba_shift; ++ desc->bdev = bpriv_data->bdev; ++ ++ pr_debug("[%s]: block storage layout\n lbas: %lu , log2blksz: %d, blksz: %lu\n", ++ udev->name, desc->lba, desc->log2blksz, desc->blksz); ++ ++ return 0; ++} ++ ++int nvmxip_init(struct udevice *udev) ++{ ++ struct nvmxip_plat *plat_data = dev_get_plat(udev); ++ struct nvmxip_priv *priv_data = dev_get_priv(udev); ++ int ret; ++ struct udevice *bdev = NULL; ++ char bdev_name[NVMXIP_BLKDEV_NAME_SZ + 1] = {0}; ++ ++ priv_data->udev = udev; ++ priv_data->plat_data = plat_data; ++ ++ nvmxip_bdev_max_devs++; ++ ++ snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "nvmxip-blk#%d", nvmxip_bdev_max_devs); ++ ++ ret = blk_create_devicef(udev, NVMXIP_BLKDRV_NAME, bdev_name, UCLASS_NVMXIP, ++ nvmxip_bdev_max_devs, NVMXIP_DEFAULT_LBA_SZ, ++ NVMXIP_DEFAULT_LBA_COUNT, &bdev); ++ if (ret) { ++ pr_err("[%s]: failure during creation of the block device %s, error %d\n", ++ udev->name, bdev_name, ret); ++ goto blkdev_setup_error; ++ } ++ ++ ret = blk_probe_or_unbind(bdev); ++ if (ret) { ++ pr_err("[%s]: failure during probing the block device %s, error %d\n", ++ udev->name, bdev_name, ret); ++ goto blkdev_setup_error; ++ } ++ ++ pr_info("[%s]: the block device %s ready for use\n", udev->name, bdev_name); ++ ++ return 0; ++ ++blkdev_setup_error: ++ nvmxip_bdev_max_devs--; ++ return ret; ++} ++ ++static const struct blk_ops nvmxip_blk_ops = { ++ .read = nvmxip_blk_read, ++}; ++ ++U_BOOT_DRIVER(nvmxip_blk) = { ++ .name = NVMXIP_BLKDRV_NAME, ++ .id = UCLASS_BLK, ++ .probe = nvmxip_blk_probe, ++ .ops = &nvmxip_blk_ops, ++ .priv_auto = sizeof(struct nvmxip_blk_priv), ++}; +diff --git a/drivers/nvmxip/nvmxip.h b/drivers/nvmxip/nvmxip.h +new file mode 100644 +index 000000000000..393172cc2f86 +--- /dev/null ++++ b/drivers/nvmxip/nvmxip.h +@@ -0,0 +1,46 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#ifndef __DRIVER_NVMXIP_H__ ++#define __DRIVER_NVMXIP_H__ ++ ++#include <asm/io.h> ++#include <blk.h> ++#include <linux/bitops.h> ++#include <linux/compat.h> ++#include <mapmem.h> ++ ++#define NVMXIP_BLKDRV_NAME "nvmxip-blk" ++ ++#define NVMXIP_BLKDEV_NAME_SZ 20 ++ ++#define NVMXIP_DEFAULT_LBA_SHIFT 10 /* 1024 bytes per block */ ++#define NVMXIP_DEFAULT_LBA_COUNT 1024 /* block count */ ++ ++#define NVMXIP_DEFAULT_LBA_SZ BIT(NVMXIP_DEFAULT_LBA_SHIFT) ++ ++/* NVM XIP device platform data */ ++struct nvmxip_plat { ++ phys_addr_t phys_base; /* NVM XIP device base address */ ++ u32 lba_shift; /* block size shift count (read from device tree) */ ++ lbaint_t lba; /* number of blocks (read from device tree) */ ++}; ++ ++/* NVM XIP device private data */ ++struct nvmxip_priv { ++ struct udevice *udev; ++ struct nvmxip_plat *plat_data; ++}; ++ ++/* Private data of the block device associated with the NVM XIP device (the parent) */ ++struct nvmxip_blk_priv { ++ struct udevice *bdev; ++ struct nvmxip_plat *pplat_data; /* parent device platform data */ ++}; ++ ++int nvmxip_init(struct udevice *udev); ++ ++#endif /* __DRIVER_NVMXIP_H__ */ +diff --git a/drivers/nvmxip/nvmxip_qspi.c b/drivers/nvmxip/nvmxip_qspi.c +new file mode 100644 +index 000000000000..749625134acd +--- /dev/null ++++ b/drivers/nvmxip/nvmxip_qspi.c +@@ -0,0 +1,65 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#include <common.h> ++#include <dm.h> ++#include <fdt_support.h> ++#include "nvmxip.h" ++ ++#include <asm/global_data.h> ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi" ++ ++static int nvmxip_qspi_probe(struct udevice *dev) ++{ ++ pr_debug("[%s][%s]\n", __func__, dev->name); ++ return nvmxip_init(dev); ++} ++ ++static int nvmxip_qspi_of_to_plat(struct udevice *dev) ++{ ++ struct nvmxip_plat *plat_data = dev_get_plat(dev); ++ int ret; ++ ++ plat_data->phys_base = (phys_addr_t)dev_read_addr(dev); ++ if (plat_data->phys_base == FDT_ADDR_T_NONE) { ++ pr_err("[%s]: can not get base address from device tree\n", dev->name); ++ return -EINVAL; ++ } ++ ++ ret = dev_read_u32(dev, "lba_shift", &plat_data->lba_shift); ++ if (ret) { ++ pr_err("[%s]: can not get lba_shift from device tree\n", dev->name); ++ return -EINVAL; ++ } ++ ++ ret = dev_read_u32(dev, "lba", (u32 *)&plat_data->lba); ++ if (ret) { ++ pr_err("[%s]: can not get lba from device tree\n", dev->name); ++ return -EINVAL; ++ } ++ ++ pr_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n", ++ dev->name, plat_data->phys_base, plat_data->lba_shift, plat_data->lba); ++ ++ return 0; ++} ++ ++static const struct udevice_id nvmxip_qspi_ids[] = { ++ { .compatible = "nvmxip,qspi" }, ++ { /* sentinel */ } ++}; ++ ++U_BOOT_DRIVER(nvmxip_qspi) = { ++ .name = NVMXIP_QSPI_DRV_NAME, ++ .id = UCLASS_NVMXIP, ++ .of_match = nvmxip_qspi_ids, ++ .of_to_plat = nvmxip_qspi_of_to_plat, ++ .priv_auto = sizeof(struct nvmxip_priv), ++ .plat_auto = sizeof(struct nvmxip_plat), ++ .probe = nvmxip_qspi_probe, ++}; +diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h +index fa08a66ac8e0..f3564a49d912 100644 +--- a/include/dm/uclass-id.h ++++ b/include/dm/uclass-id.h +@@ -92,6 +92,7 @@ enum uclass_id { + UCLASS_NOP, /* No-op devices */ + UCLASS_NORTHBRIDGE, /* Intel Northbridge / SDRAM controller */ + UCLASS_NVME, /* NVM Express device */ ++ UCLASS_NVMXIP, /* NVM XIP devices */ + UCLASS_P2SB, /* (x86) Primary-to-Sideband Bus */ + UCLASS_PANEL, /* Display panel, such as an LCD */ + UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */ +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0028-sandbox64-fix-return-unsigned-long-in-readq.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0028-sandbox64-fix-return-unsigned-long-in-readq.patch new file mode 100644 index 0000000000..b0e83667da --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0028-sandbox64-fix-return-unsigned-long-in-readq.patch @@ -0,0 +1,46 @@ +From 3262ee6a5300221969e61eff7a8f18336a135a73 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Fri, 16 Dec 2022 17:20:58 +0000 +Subject: [PATCH 28/43] sandbox64: fix: return unsigned long in readq() + +make readq return unsigned long + +readq should return 64-bit data + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/sandbox/cpu/cpu.c | 2 +- + arch/sandbox/include/asm/io.h | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c +index 636d3545b954..248d17a85c82 100644 +--- a/arch/sandbox/cpu/cpu.c ++++ b/arch/sandbox/cpu/cpu.c +@@ -230,7 +230,7 @@ phys_addr_t map_to_sysmem(const void *ptr) + return mentry->tag; + } + +-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size) ++unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size) + { + struct sandbox_state *state = state_get_current(); + +diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h +index ad6c29a4e26c..31ab7289b4bd 100644 +--- a/arch/sandbox/include/asm/io.h ++++ b/arch/sandbox/include/asm/io.h +@@ -45,7 +45,7 @@ static inline void unmap_sysmem(const void *vaddr) + /* Map from a pointer to our RAM buffer */ + phys_addr_t map_to_sysmem(const void *ptr); + +-unsigned int sandbox_read(const void *addr, enum sandboxio_size_t size); ++unsigned long sandbox_read(const void *addr, enum sandboxio_size_t size); + void sandbox_write(void *addr, unsigned int val, enum sandboxio_size_t size); + + #define readb(addr) sandbox_read((const void *)addr, SB_SIZE_8) +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0029-sandbox64-add-support-for-NVMXIP-QSPI.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0029-sandbox64-add-support-for-NVMXIP-QSPI.patch new file mode 100644 index 0000000000..d6168b998e --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0029-sandbox64-add-support-for-NVMXIP-QSPI.patch @@ -0,0 +1,113 @@ +From 2b0606f603de13524ce9b63578f4c3358c3ac6df Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Thu, 22 Dec 2022 12:15:42 +0000 +Subject: [PATCH 29/43] sandbox64: add support for NVMXIP QSPI + +enable NVMXIP QSPI for sandbox 64-bit + +Adding two NVM XIP QSPI storage devices. + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/sandbox/dts/sandbox64.dts | 13 +++++++++++++ + arch/sandbox/dts/test.dts | 14 ++++++++++++++ + configs/sandbox_defconfig | 1 + + drivers/nvmxip/nvmxip.c | 4 ++++ + drivers/nvmxip/nvmxip.h | 3 +++ + 5 files changed, 35 insertions(+) + +diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts +index a9cd7908f83e..aed3801af8a9 100644 +--- a/arch/sandbox/dts/sandbox64.dts ++++ b/arch/sandbox/dts/sandbox64.dts +@@ -89,6 +89,19 @@ + cs-gpios = <0>, <&gpio_a 0>; + }; + ++ nvmxip-qspi1@08000000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x0 0x08000000 0x0 0x00200000>; ++ lba_shift = <9>; ++ lba = <4096>; ++ }; ++ ++ nvmxip-qspi2@08200000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x0 0x08200000 0x0 0x00100000>; ++ lba_shift = <9>; ++ lba = <2048>; ++ }; + }; + + #include "sandbox.dtsi" +diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts +index 2e580f980fc6..54f2b308e793 100644 +--- a/arch/sandbox/dts/test.dts ++++ b/arch/sandbox/dts/test.dts +@@ -1756,6 +1756,20 @@ + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&mmc0>; + }; ++ ++ nvmxip-qspi1@08000000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x08000000 0x00200000>; ++ lba_shift = <9>; ++ lba = <4096>; ++ }; ++ ++ nvmxip-qspi2@08200000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x08200000 0x00100000>; ++ lba_shift = <9>; ++ lba = <2048>; ++ }; + }; + + #include "sandbox_pmic.dtsi" +diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig +index e6ea96a6b924..f22230b5cce2 100644 +--- a/configs/sandbox_defconfig ++++ b/configs/sandbox_defconfig +@@ -138,6 +138,7 @@ CONFIG_NETCONSOLE=y + CONFIG_IP_DEFRAG=y + CONFIG_BOOTP_SERVERIP=y + CONFIG_IPV6=y ++CONFIG_NVMXIP_QSPI=y + CONFIG_DM_DMA=y + CONFIG_DEVRES=y + CONFIG_DEBUG_DEVRES=y +diff --git a/drivers/nvmxip/nvmxip.c b/drivers/nvmxip/nvmxip.c +index 6ba48183c575..af9c9a3b7270 100644 +--- a/drivers/nvmxip/nvmxip.c ++++ b/drivers/nvmxip/nvmxip.c +@@ -85,6 +85,10 @@ int nvmxip_init(struct udevice *udev) + priv_data->udev = udev; + priv_data->plat_data = plat_data; + ++#if CONFIG_IS_ENABLED(SANDBOX64) ++ sandbox_set_enable_memio(true); ++#endif ++ + nvmxip_bdev_max_devs++; + + snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "nvmxip-blk#%d", nvmxip_bdev_max_devs); +diff --git a/drivers/nvmxip/nvmxip.h b/drivers/nvmxip/nvmxip.h +index 393172cc2f86..0384ce2e2b47 100644 +--- a/drivers/nvmxip/nvmxip.h ++++ b/drivers/nvmxip/nvmxip.h +@@ -8,6 +8,9 @@ + #define __DRIVER_NVMXIP_H__ + + #include <asm/io.h> ++#if CONFIG_IS_ENABLED(SANDBOX64) ++#include <asm/test.h> ++#endif + #include <blk.h> + #include <linux/bitops.h> + #include <linux/compat.h> +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0030-corstone1000-add-NVM-XIP-QSPI-device-tree-node.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0030-corstone1000-add-NVM-XIP-QSPI-device-tree-node.patch new file mode 100644 index 0000000000..21ad2109cc --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0030-corstone1000-add-NVM-XIP-QSPI-device-tree-node.patch @@ -0,0 +1,35 @@ +From 3f72e390fc8e1a0d774d80c3ccd21be38c9af1db Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Mon, 19 Dec 2022 13:20:19 +0000 +Subject: [PATCH 30/43] corstone1000: add NVM XIP QSPI device tree node + +add QSPI flash device node for block storage access + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/arm/dts/corstone1000.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi +index 61e0c33247ce..faf4e12bab2a 100644 +--- a/arch/arm/dts/corstone1000.dtsi ++++ b/arch/arm/dts/corstone1000.dtsi +@@ -38,6 +38,13 @@ + reg = <0x88200000 0x77e00000>; + }; + ++ nvmxip-qspi@08000000 { ++ compatible = "nvmxip,qspi"; ++ reg = <0x08000000 0x2000000>; ++ lba_shift = <9>; ++ lba = <65536>; ++ }; ++ + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0031-corstone1000-enable-NVM-XIP-QSPI-flash.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0031-corstone1000-enable-NVM-XIP-QSPI-flash.patch new file mode 100644 index 0000000000..64bf97d1f3 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0031-corstone1000-enable-NVM-XIP-QSPI-flash.patch @@ -0,0 +1,29 @@ +From 0c3d61d499039ff0828376bb21b4fb1de071b8d2 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Mon, 19 Dec 2022 13:25:23 +0000 +Subject: [PATCH 31/43] corstone1000: enable NVM XIP QSPI flash + +add the QSPI flash device with block storage capability + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + configs/corstone1000_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index 1179bf5f3bfd..2986cc95932f 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -58,6 +58,7 @@ CONFIG_DM_SERIAL=y + CONFIG_USB=y + CONFIG_USB_ISP1760=y + CONFIG_ERRNO_STR=y ++CONFIG_NVMXIP_QSPI=y + CONFIG_EFI_MM_COMM_TEE=y + CONFIG_ARM_FFA_TRANSPORT=y + CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0032-sandbox64-add-a-test-case-for-UCLASS_NVMXIP.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0032-sandbox64-add-a-test-case-for-UCLASS_NVMXIP.patch new file mode 100644 index 0000000000..5724283494 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0032-sandbox64-add-a-test-case-for-UCLASS_NVMXIP.patch @@ -0,0 +1,174 @@ +From 3be91bde755c376a38c3affb9640b39df1acdd9c Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Thu, 22 Dec 2022 11:30:16 +0000 +Subject: [PATCH 32/43] sandbox64: add a test case for UCLASS_NVMXIP + +provide a test for NVM XIP devices + +The test case allows to make sure of the following: + +- The NVM XIP QSPI devices are probed +- The DT entries are read correctly +- the data read from the flash by the NVMXIP block driver is correct + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + MAINTAINERS | 1 + + test/dm/Makefile | 4 ++ + test/dm/nvmxip.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 120 insertions(+) + create mode 100644 test/dm/nvmxip.c + +diff --git a/MAINTAINERS b/MAINTAINERS +index ba15dd02d58d..82cb6075cb32 100644 +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -1210,6 +1210,7 @@ S: Maintained + F: doc/develop/driver-model/nvmxip.rst + F: doc/device-tree-bindings/nvmxip/nvmxip.txt + F: drivers/nvmxip/ ++F: test/dm/nvmxip.c + + NVMEM + M: Sean Anderson <seanga2@gmail.com> +diff --git a/test/dm/Makefile b/test/dm/Makefile +index 85e99e1c120e..bc8214da2da2 100644 +--- a/test/dm/Makefile ++++ b/test/dm/Makefile +@@ -18,6 +18,10 @@ obj-$(CONFIG_UT_DM) += test-uclass.o + obj-$(CONFIG_UT_DM) += core.o + obj-$(CONFIG_UT_DM) += read.o + obj-$(CONFIG_UT_DM) += phys2bus.o ++ifeq ($(CONFIG_NVMXIP_QSPI)$(CONFIG_SANDBOX64),yy) ++obj-y += nvmxip.o ++endif ++ + ifneq ($(CONFIG_SANDBOX),) + ifeq ($(CONFIG_ACPIGEN),y) + obj-y += acpi.o +diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c +new file mode 100644 +index 000000000000..484e6077b4a9 +--- /dev/null ++++ b/test/dm/nvmxip.c +@@ -0,0 +1,115 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Functional tests for UCLASS_FFA class ++ * ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#include <common.h> ++#include <console.h> ++#include <blk.h> ++#include <dm.h> ++#include <dm/test.h> ++#include "../../drivers/nvmxip/nvmxip.h" ++#include <test/test.h> ++#include <test/ut.h> ++ ++/* NVMXIP devices described in the device tree */ ++#define SANDBOX_NVMXIP_DEVICES 2 ++ ++/* reference device tree data for the probed devices */ ++static struct nvmxip_plat nvmqspi_refdata[SANDBOX_NVMXIP_DEVICES] = { ++ {0x08000000, 9, 4096}, {0x08200000, 9, 2048} ++}; ++ ++#define NVMXIP_BLK_START_PATTERN 0x1122334455667788ULL ++#define NVMXIP_BLK_END_PATTERN 0xa1a2a3a4a5a6a7a8ULL ++ ++static int dm_nvmxip_flash_sanity(u8 device_idx, void *buffer) ++{ ++ int i; ++ u64 *ptr = NULL; ++ u8 *base = NULL; ++ unsigned long blksz; ++ ++ blksz = 1 << nvmqspi_refdata[device_idx].lba_shift; ++ ++ /* if buffer not NULL, init the flash with the pattern data*/ ++ if (!buffer) ++ base = map_sysmem(nvmqspi_refdata[device_idx].phys_base, 0); ++ else ++ base = buffer; ++ ++ for (i = 0; i < nvmqspi_refdata[device_idx].lba ; i++) { ++ ptr = (u64 *)(base + i * blksz); ++ ++ /* write an 8 bytes pattern at the start of the current block*/ ++ if (!buffer) ++ *ptr = NVMXIP_BLK_START_PATTERN; ++ else if (*ptr != NVMXIP_BLK_START_PATTERN) ++ return -EINVAL; ++ ++ ptr = (u64 *)((u8 *)ptr + blksz - sizeof(u64)); ++ ++ /* write an 8 bytes pattern at the end of the current block*/ ++ if (!buffer) ++ *ptr = NVMXIP_BLK_END_PATTERN; ++ else if (*ptr != NVMXIP_BLK_END_PATTERN) ++ return -EINVAL; ++ } ++ ++ if (!buffer) ++ unmap_sysmem(base); ++ ++ return 0; ++} ++ ++static int dm_test_nvmxip(struct unit_test_state *uts) ++{ ++ struct nvmxip_plat *plat_data = NULL; ++ struct udevice *dev = NULL, *bdev = NULL; ++ u8 device_idx; ++ void *buffer = NULL; ++ unsigned long flashsz; ++ ++ /* set the flash content first for both devices */ ++ dm_nvmxip_flash_sanity(0, NULL); ++ dm_nvmxip_flash_sanity(1, NULL); ++ ++ /* probing all NVM XIP QSPI devices */ ++ for (device_idx = 0, uclass_first_device(UCLASS_NVMXIP, &dev); ++ dev; ++ uclass_next_device(&dev), device_idx++) { ++ plat_data = dev_get_plat(dev); ++ ++ /* device tree entries checks */ ++ ut_assertok(nvmqspi_refdata[device_idx].phys_base != plat_data->phys_base); ++ ut_assertok(nvmqspi_refdata[device_idx].lba_shift != plat_data->lba_shift); ++ ut_assertok(nvmqspi_refdata[device_idx].lba != plat_data->lba); ++ ++ /* before reading all the flash blocks, let's calculate the flash size */ ++ flashsz = plat_data->lba << plat_data->lba_shift; ++ ++ /* allocate the user buffer where to copy the blocks data to */ ++ buffer = calloc(flashsz, 1); ++ ut_assertok(!buffer); ++ ++ /* the block device is the child of the parent device probed with DT*/ ++ ut_assertok(device_find_first_child(dev, &bdev)); ++ ++ /* reading all the flash blocks*/ ++ ut_asserteq(plat_data->lba, blk_read(bdev, 0, plat_data->lba, buffer)); ++ ++ /* compare the data read from flash with the expected data */ ++ ut_assertok(dm_nvmxip_flash_sanity(device_idx, buffer)); ++ ++ free(buffer); ++ } ++ ++ ut_assertok(device_idx != SANDBOX_NVMXIP_DEVICES); ++ ++ return CMD_RET_SUCCESS; ++} ++ ++DM_TEST(dm_test_nvmxip, UT_TESTF_SCAN_FDT | UT_TESTF_CONSOLE_REC); +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-nvmxip-provide-a-u-boot-shell-test-command.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-nvmxip-provide-a-u-boot-shell-test-command.patch new file mode 100644 index 0000000000..e8adbc121a --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-nvmxip-provide-a-u-boot-shell-test-command.patch @@ -0,0 +1,135 @@ +From 560ebe3eb6197322b9d00c8e3cf30fb7e679d8b2 Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Thu, 22 Dec 2022 16:20:46 +0000 +Subject: [PATCH 33/43] nvmxip: provide a u-boot shell test command + +nvmxip command allows probing the NVM XIP devices manually + +The command is provided for test purposes only. + +Use: + +nvmxip probe + +Upstream-Status: Submitted +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + cmd/Kconfig | 7 +++++ + cmd/Makefile | 1 + + cmd/nvmxip.c | 47 ++++++++++++++++++++++++++++++++++ + configs/corstone1000_defconfig | 1 + + configs/sandbox_defconfig | 1 + + 5 files changed, 57 insertions(+) + create mode 100644 cmd/nvmxip.c + +diff --git a/cmd/Kconfig b/cmd/Kconfig +index 5e278ecb1597..b6a3e5908534 100644 +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -938,6 +938,13 @@ config CMD_ARMFFA + - Sending a data pattern to the specified partition + - Displaying the arm_ffa device info + ++config CMD_NVMXIP ++ bool "NVM XIP probe command" ++ depends on NVMXIP ++ help ++ Probes all NVM XIP devices. The command is for ++ test purposes only (not to be upstreamed) ++ + config CMD_ARMFLASH + #depends on FLASH_CFI_DRIVER + bool "armflash" +diff --git a/cmd/Makefile b/cmd/Makefile +index c757f1647da6..0a3d98100703 100644 +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -154,6 +154,7 @@ obj-$(CONFIG_CMD_RTC) += rtc.o + obj-$(CONFIG_SANDBOX) += host.o + obj-$(CONFIG_CMD_SATA) += sata.o + obj-$(CONFIG_CMD_NVME) += nvme.o ++obj-$(CONFIG_CMD_NVMXIP) += nvmxip.o + obj-$(CONFIG_SANDBOX) += sb.o + obj-$(CONFIG_CMD_SF) += sf.o + obj-$(CONFIG_CMD_SCSI) += scsi.o disk.o +diff --git a/cmd/nvmxip.c b/cmd/nvmxip.c +new file mode 100644 +index 000000000000..3eb0d84afc04 +--- /dev/null ++++ b/cmd/nvmxip.c +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <dm.h> ++ ++int do_nvmxip_probe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ struct udevice *dev = NULL; ++ for (uclass_first_device(UCLASS_NVMXIP, &dev); dev; uclass_next_device(&dev)); ++ ++ return 0; ++} ++ ++static struct cmd_tbl nvmxip_commands[] = { ++ U_BOOT_CMD_MKENT(probe, 1, 1, do_nvmxip_probe, "", ""), ++}; ++ ++static int do_nvmxip(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ++{ ++ struct cmd_tbl *nvmxip_cmd; ++ int ret; ++ ++ if (argc < 2) ++ return CMD_RET_USAGE; ++ ++ nvmxip_cmd = find_cmd_tbl(argv[1], nvmxip_commands, ARRAY_SIZE(nvmxip_commands)); ++ ++ argc -= 2; ++ argv += 2; ++ ++ if (!nvmxip_cmd || argc > nvmxip_cmd->maxargs) ++ return CMD_RET_USAGE; ++ ++ ret = nvmxip_cmd->cmd(nvmxip_cmd, flag, argc, argv); ++ ++ return cmd_process_error(nvmxip_cmd, ret); ++} ++ ++U_BOOT_CMD(nvmxip, 4, 1, do_nvmxip, ++ "NVM XIP probe command", ++ "probe\n" ++ " - probes all NVM XIP devices\n"); +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index 2986cc95932f..e009faee0252 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -59,6 +59,7 @@ CONFIG_USB=y + CONFIG_USB_ISP1760=y + CONFIG_ERRNO_STR=y + CONFIG_NVMXIP_QSPI=y ++CONFIG_CMD_NVMXIP=y + CONFIG_EFI_MM_COMM_TEE=y + CONFIG_ARM_FFA_TRANSPORT=y + CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig +index f22230b5cce2..3b895be9e4ba 100644 +--- a/configs/sandbox_defconfig ++++ b/configs/sandbox_defconfig +@@ -139,6 +139,7 @@ CONFIG_IP_DEFRAG=y + CONFIG_BOOTP_SERVERIP=y + CONFIG_IPV6=y + CONFIG_NVMXIP_QSPI=y ++CONFIG_CMD_NVMXIP=y + CONFIG_DM_DMA=y + CONFIG_DEVRES=y + CONFIG_DEBUG_DEVRES=y +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-add-fwu-metadata-store-info.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-add-fwu-metadata-store-info.patch new file mode 100644 index 0000000000..facd19b3c9 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-add-fwu-metadata-store-info.patch @@ -0,0 +1,42 @@ +From 9ef889ff89e6d2e2e40edecbd4ab7601c3d68052 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 15:58:07 +0000 +Subject: [PATCH 34/43] corstone1000: add fwu-metadata store info + +Add fwu-mdata node and handle for the reference +nvmxip-qspi. + +Upstream-Status: Submitted +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + arch/arm/dts/corstone1000.dtsi | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi +index faf4e12bab2a..b1d83b5ba861 100644 +--- a/arch/arm/dts/corstone1000.dtsi ++++ b/arch/arm/dts/corstone1000.dtsi +@@ -38,7 +38,7 @@ + reg = <0x88200000 0x77e00000>; + }; + +- nvmxip-qspi@08000000 { ++ nvmxip: nvmxip-qspi@08000000 { + compatible = "nvmxip,qspi"; + reg = <0x08000000 0x2000000>; + lba_shift = <9>; +@@ -106,6 +106,11 @@ + method = "smc"; + }; + ++ fwu-mdata { ++ compatible = "u-boot,fwu-mdata-gpt"; ++ fwu-mdata-store = <&nvmxip>; ++ }; ++ + soc { + compatible = "simple-bus"; + #address-cells = <1>; +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0035-nvmxip-shorter-block-device-name.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0035-nvmxip-shorter-block-device-name.patch new file mode 100644 index 0000000000..74e4ccb875 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0035-nvmxip-shorter-block-device-name.patch @@ -0,0 +1,44 @@ +From 83823733015998702e4dc0365764fe7dde4a321f Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 15:59:36 +0000 +Subject: [PATCH 35/43] nvmxip: shorter block device name + +Make the block device name shorter, so it will be set and presented +inside the array limits. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + drivers/nvmxip/nvmxip.c | 2 +- + drivers/nvmxip/nvmxip_qspi.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/nvmxip/nvmxip.c b/drivers/nvmxip/nvmxip.c +index af9c9a3b7270..91fe995f2d4d 100644 +--- a/drivers/nvmxip/nvmxip.c ++++ b/drivers/nvmxip/nvmxip.c +@@ -91,7 +91,7 @@ int nvmxip_init(struct udevice *udev) + + nvmxip_bdev_max_devs++; + +- snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "nvmxip-blk#%d", nvmxip_bdev_max_devs); ++ snprintf(bdev_name, NVMXIP_BLKDEV_NAME_SZ, "blk#%d", nvmxip_bdev_max_devs); + + ret = blk_create_devicef(udev, NVMXIP_BLKDRV_NAME, bdev_name, UCLASS_NVMXIP, + nvmxip_bdev_max_devs, NVMXIP_DEFAULT_LBA_SZ, +diff --git a/drivers/nvmxip/nvmxip_qspi.c b/drivers/nvmxip/nvmxip_qspi.c +index 749625134acd..f6f5435e6377 100644 +--- a/drivers/nvmxip/nvmxip_qspi.c ++++ b/drivers/nvmxip/nvmxip_qspi.c +@@ -43,7 +43,7 @@ static int nvmxip_qspi_of_to_plat(struct udevice *dev) + return -EINVAL; + } + +- pr_debug("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n", ++ log_err("[%s]: XIP device base addr: 0x%llx , lba_shift: %d , lbas: %lu\n", + dev->name, plat_data->phys_base, plat_data->lba_shift, plat_data->lba); + + return 0; +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0036-efi_boottime-allow-to-reset-a-path-after-boot.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0036-efi_boottime-allow-to-reset-a-path-after-boot.patch new file mode 100644 index 0000000000..59a60af668 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0036-efi_boottime-allow-to-reset-a-path-after-boot.patch @@ -0,0 +1,31 @@ +From 53d29d35cdbcf493f6a9046458947d3e91f01add Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 16:11:25 +0000 +Subject: [PATCH 36/43] efi_boottime: allow to reset a path after boot + +Allow to install multiple protocol interfaces in an +already installed root interface. +This may need to be fix in other way, but for now +looks like the get away fix. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + lib/efi_loader/efi_boottime.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c +index fea4eb7a342e..90f43ff9a62f 100644 +--- a/lib/efi_loader/efi_boottime.c ++++ b/lib/efi_loader/efi_boottime.c +@@ -2669,7 +2669,6 @@ efi_install_multiple_protocol_interfaces_int(efi_handle_t *handle, + EFI_PRINT("Path %pD already installed\n", + protocol_interface); + ret = EFI_ALREADY_STARTED; +- break; + } + } + ret = EFI_CALL(efi_install_protocol_interface(handle, protocol, +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-fwu_metadata-make-sure-structures-are-packed.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-fwu_metadata-make-sure-structures-are-packed.patch new file mode 100644 index 0000000000..7781a1edab --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0037-fwu_metadata-make-sure-structures-are-packed.patch @@ -0,0 +1,50 @@ +From a8142be9b32a769040b6238ff611c22cb31c8cb5 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 16:13:24 +0000 +Subject: [PATCH 37/43] fwu_metadata: make sure structures are packed + +The fwu metadata in the metadata partitions +should/are packed to guarantee that the info is +correct in all platforms. Also the size of them +are used to calculate the crc32 and that is important +to get it right. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + include/fwu_mdata.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h +index 8fda4f4ac225..c61221a91735 100644 +--- a/include/fwu_mdata.h ++++ b/include/fwu_mdata.h +@@ -22,7 +22,7 @@ struct fwu_image_bank_info { + efi_guid_t image_uuid; + uint32_t accepted; + uint32_t reserved; +-}; ++} __packed; + + /** + * struct fwu_image_entry - information for a particular type of image +@@ -38,7 +38,7 @@ struct fwu_image_entry { + efi_guid_t image_type_uuid; + efi_guid_t location_uuid; + struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS]; +-}; ++} __packed; + + /** + * struct fwu_mdata - FWU metadata structure for multi-bank updates +@@ -62,6 +62,6 @@ struct fwu_mdata { + uint32_t previous_active_index; + + struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; +-}; ++} __packed; + + #endif /* _FWU_MDATA_H_ */ +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-add-boot-index.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-add-boot-index.patch new file mode 100644 index 0000000000..afaf967348 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0038-corstone1000-add-boot-index.patch @@ -0,0 +1,33 @@ +From ceae4ec0d459b1ef12e544f4e36d6043a09d3b05 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 16:15:30 +0000 +Subject: [PATCH 38/43] corstone1000: add boot index + +it is expected that the firmware that runs before +u-boot somehow provide the information of the bank +(index) of it is booting. +We will need to extend tf-a to pass that info, +meanwhile just set it to the default bank. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + board/armltd/corstone1000/corstone1000.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +index d6ca6e896140..0a58ccd99cdd 100644 +--- a/board/armltd/corstone1000/corstone1000.c ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -106,6 +106,7 @@ int dram_init_banksize(void) + return 0; + } + +-void reset_cpu(ulong addr) ++void fwu_plat_get_bootidx(int *boot_idx) + { ++ *boot_idx = 0; + } +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-adjust-boot-bank-and-kernel-location.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-adjust-boot-bank-and-kernel-location.patch new file mode 100644 index 0000000000..a42b3a25ee --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0039-corstone1000-adjust-boot-bank-and-kernel-location.patch @@ -0,0 +1,36 @@ +From 80a2910370b0acc35f6fb2fbe3a7e56fecb1a08a Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 16:17:21 +0000 +Subject: [PATCH 39/43] corstone1000: adjust boot bank and kernel location + +Adjust in the env boot script the address of the +bootbank with the new gpt layout, and also the +kernel partition address. Please be aware that +this is hack and needs a proper fix, since the +offset of the kernel partition is not fixed, +but for the propose of PoC it is enough for testing. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + board/armltd/corstone1000/corstone1000.env | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/board/armltd/corstone1000/corstone1000.env b/board/armltd/corstone1000/corstone1000.env +index b24ff07fc6bd..a6ee4962211b 100644 +--- a/board/armltd/corstone1000/corstone1000.env ++++ b/board/armltd/corstone1000/corstone1000.env +@@ -1,8 +1,8 @@ + /* SPDX-License-Identifier: GPL-2.0+ */ + + usb_pgood_delay=250 +-boot_bank_flag=0x08002000 +-kernel_addr_bank_0=0x083EE000 ++boot_bank_flag=0x08005006 ++kernel_addr_bank_0=0x08280000 + kernel_addr_bank_1=0x0936E000 + retrieve_kernel_load_addr= + if itest.l *${boot_bank_flag} == 0; then +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0040-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0040-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch new file mode 100644 index 0000000000..d1fa8ffb25 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0040-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch @@ -0,0 +1,133 @@ +From 7c694af3fd5de372349f740b62cd3d909483fe2e Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Wed, 1 Feb 2023 16:19:40 +0000 +Subject: [PATCH 40/43] corstone1000: add nvmxip, fwu-mdata and gpt options + +Enable the newest features: nvmxip, fwu-metadata and +gpt. Commands to print the partition info, gpt info +and fwu metadata will be available. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + configs/corstone1000_defconfig | 31 +++++++++++++++++++------------ + fs/fs.c | 5 +++++ + 2 files changed, 24 insertions(+), 12 deletions(-) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index e009faee0252..711cf13592db 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -4,13 +4,15 @@ CONFIG_TARGET_CORSTONE1000=y + CONFIG_TEXT_BASE=0x80000000 + CONFIG_SYS_MALLOC_LEN=0x2000000 + CONFIG_NR_DRAM_BANKS=1 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 ++CONFIG_DM_GPIO=y + CONFIG_DEFAULT_DEVICE_TREE="corstone1000-mps3" + CONFIG_SYS_PROMPT="corstone1000# " + CONFIG_IDENT_STRING=" corstone1000 aarch64 " + CONFIG_SYS_LOAD_ADDR=0x82100000 ++CONFIG_FWU_NUM_IMAGES_PER_BANK=4 + CONFIG_DISTRO_DEFAULTS=y +-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 + CONFIG_FIT=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y +@@ -23,11 +25,16 @@ CONFIG_LOGLEVEL=7 + CONFIG_SYS_MAXARGS=64 + CONFIG_SYS_CBSIZE=512 + # CONFIG_CMD_CONSOLE is not set ++CONFIG_CMD_FWU_METADATA=y + CONFIG_CMD_BOOTZ=y + CONFIG_SYS_BOOTM_LEN=0x800000 + # CONFIG_CMD_XIMG is not set ++CONFIG_CMD_NVMXIP=y ++CONFIG_CMD_GPT=y ++# CONFIG_RANDOM_UUID is not set + CONFIG_CMD_LOADM=y + # CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MMC=y + CONFIG_CMD_USB=y + # CONFIG_CMD_SETEXPR is not set + # CONFIG_CMD_NFS is not set +@@ -39,29 +46,29 @@ CONFIG_OF_CONTROL=y + CONFIG_VERSION_VARIABLE=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_REGMAP=y +-CONFIG_MISC=y ++CONFIG_ARM_FFA_TRANSPORT=y + CONFIG_CLK=y +-CONFIG_CMD_MMC=y +-CONFIG_DM_MMC=y ++CONFIG_FWU_MDATA=y ++CONFIG_FWU_MDATA_GPT_BLK=y ++CONFIG_MISC=y + CONFIG_ARM_PL180_MMCI=y +-CONFIG_MMC_SDHCI_ADMA_HELPERS=y +-CONFIG_MMC_WRITE=y +-CONFIG_DM_GPIO=y + CONFIG_PHYLIB=y + CONFIG_PHY_SMSC=y + CONFIG_SMC911X=y ++CONFIG_NVMXIP_QSPI=y + CONFIG_PHY=y + CONFIG_RAM=y + CONFIG_DM_RTC=y + CONFIG_RTC_EMULATION=y + CONFIG_DM_SERIAL=y ++CONFIG_SYSRESET=y + CONFIG_USB=y + CONFIG_USB_ISP1760=y + CONFIG_ERRNO_STR=y +-CONFIG_NVMXIP_QSPI=y +-CONFIG_CMD_NVMXIP=y + CONFIG_EFI_MM_COMM_TEE=y +-CONFIG_ARM_FFA_TRANSPORT=y + CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y ++CONFIG_EFI_CAPSULE_ON_DISK=y ++CONFIG_EFI_IGNORE_OSINDICATIONS=y + CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +-CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y ++CONFIG_FWU_MULTI_BANK_UPDATE=y ++# CONFIG_TOOLS_MKEFICAPSULE is not set +diff --git a/fs/fs.c b/fs/fs.c +index 8324b4a22f20..f54955a2b7f6 100644 +--- a/fs/fs.c ++++ b/fs/fs.c +@@ -437,11 +437,13 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) + } + #endif + ++ log_err("RUI: fs_set_blk_dev fstype: %d\n", fstype); + part = part_get_info_by_dev_and_name_or_num(ifname, dev_part_str, &fs_dev_desc, + &fs_partition, 1); + if (part < 0) + return -1; + ++ log_err("RUI: fs_set_blk_dev 1\n"); + for (i = 0, info = fstypes; i < ARRAY_SIZE(fstypes); i++, info++) { + if (fstype != FS_TYPE_ANY && info->fstype != FS_TYPE_ANY && + fstype != info->fstype) +@@ -450,6 +452,8 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) + if (!fs_dev_desc && !info->null_dev_desc_ok) + continue; + ++ log_err("RUI: fs_set_blk_dev 2: info->fstype: %d part: %d\n", ++ info->fstype, part); + if (!info->probe(fs_dev_desc, &fs_partition)) { + fs_type = info->fstype; + fs_dev_part = part; +@@ -457,6 +461,7 @@ int fs_set_blk_dev(const char *ifname, const char *dev_part_str, int fstype) + } + } + ++ log_err("RUI: fs_set_blk_dev 3\n"); + return -1; + } + +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0041-nvmxip-move-header-to-include.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0041-nvmxip-move-header-to-include.patch new file mode 100644 index 0000000000..4e4ae17216 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0041-nvmxip-move-header-to-include.patch @@ -0,0 +1,42 @@ +From 37b3c73d9307d1de3b78e3ccba0ba6ba0867d6b8 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Thu, 23 Feb 2023 10:32:04 +0000 +Subject: [PATCH 41/43] nvmxip: move header to include + +Move header to include to allow external code +to get the internal bdev structures to access +block device operations. + +as at it, just add the UCLASS_NVMXIP string +so we get the correct output in partitions +listing. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + disk/part.c | 3 +++ + {drivers/nvmxip => include}/nvmxip.h | 0 + 2 files changed, 3 insertions(+) + rename {drivers/nvmxip => include}/nvmxip.h (100%) + +diff --git a/disk/part.c b/disk/part.c +index 5ee60a7fb591..593dd0004fa4 100644 +--- a/disk/part.c ++++ b/disk/part.c +@@ -270,6 +270,9 @@ static void print_part_header(const char *type, struct blk_desc *dev_desc) + case UCLASS_NVME: + puts ("NVMe"); + break; ++ case UCLASS_NVMXIP: ++ puts ("NVMXIP"); ++ break; + case UCLASS_PVBLOCK: + puts("PV BLOCK"); + break; +diff --git a/drivers/nvmxip/nvmxip.h b/include/nvmxip.h +similarity index 100% +rename from drivers/nvmxip/nvmxip.h +rename to include/nvmxip.h +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0042-corstone1000-set-kernel_addr-based-on-boot_idx.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0042-corstone1000-set-kernel_addr-based-on-boot_idx.patch new file mode 100644 index 0000000000..25e248b734 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0042-corstone1000-set-kernel_addr-based-on-boot_idx.patch @@ -0,0 +1,112 @@ +From e8272dc9390adfd0818d1093c83f3b5c07649a95 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Thu, 23 Feb 2023 10:35:00 +0000 +Subject: [PATCH 42/43] corstone1000: set kernel_addr based on boot_idx + +We need to distinguish between boot banks and from which +partition to load the kernel+initramfs to memory. + +For that, fetch the boot index, fetch the correspondent +partition, calculate the correct kernel address and +then set the env variable kernel_addr with that value. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + board/armltd/corstone1000/corstone1000.c | 55 +++++++++++++++++++++++- + configs/corstone1000_defconfig | 1 + + 2 files changed, 55 insertions(+), 1 deletion(-) + +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +index 0a58ccd99cdd..0923ca6e8c5b 100644 +--- a/board/armltd/corstone1000/corstone1000.c ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -5,13 +5,23 @@ + * Rui Miguel Silva <rui.silva@linaro.org> + */ + ++#include <blk.h> + #include <common.h> + #include <dm.h> ++#include <env.h> + #include <netdev.h> ++#include <nvmxip.h> ++#include <part.h> + #include <dm/platform_data/serial_pl01x.h> + #include <asm/armv8/mmu.h> + #include <asm/global_data.h> + ++#define CORSTONE1000_KERNEL_PARTS 2 ++#define CORSTONE1000_KERNEL_PRIMARY "kernel_primary" ++#define CORSTONE1000_KERNEL_SECONDARY "kernel_secondary" ++ ++static int corstone1000_boot_idx; ++ + static struct mm_region corstone1000_mem_map[] = { + { + /* CVM */ +@@ -108,5 +118,48 @@ int dram_init_banksize(void) + + void fwu_plat_get_bootidx(int *boot_idx) + { +- *boot_idx = 0; ++ *boot_idx = corstone1000_boot_idx; ++} ++ ++int board_late_init(void) ++{ ++ struct disk_partition part_info; ++ struct udevice *dev, *bdev; ++ struct nvmxip_plat *plat; ++ struct blk_desc *desc; ++ int ret; ++ ++ ret = uclass_first_device_err(UCLASS_NVMXIP, &dev); ++ if (ret < 0) { ++ log_err("Cannot find kernel device\n"); ++ return ret; ++ } ++ ++ plat = dev_get_plat(dev); ++ device_find_first_child(dev, &bdev); ++ desc = dev_get_uclass_plat(bdev); ++ ++ if (!corstone1000_boot_idx) ++ ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_PRIMARY, ++ &part_info); ++ else ++ ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_SECONDARY, ++ &part_info); ++ ++ if (ret < 0) { ++ log_err("failed to fetch kernel partition index: %d\n", ++ corstone1000_boot_idx); ++ return ret; ++ } ++ ++ ret = 0; ++ ++ ret |= env_set_hex("kernel_addr", plat->phys_base + ++ (part_info.start * part_info.blksz)); ++ ret |= env_set_hex("kernel_size", part_info.size * part_info.blksz); ++ ++ if (ret < 0) ++ log_err("failed to setup kernel addr and size\n"); ++ ++ return ret; + } +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index 711cf13592db..68054f755624 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -22,6 +22,7 @@ CONFIG_CONSOLE_RECORD=y + CONFIG_LOGLEVEL=7 + # CONFIG_DISPLAY_CPUINFO is not set + # CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_BOARD_LATE_INIT=y + CONFIG_SYS_MAXARGS=64 + CONFIG_SYS_CBSIZE=512 + # CONFIG_CMD_CONSOLE is not set +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0043-corstone1000-boot-index-from-active.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0043-corstone1000-boot-index-from-active.patch new file mode 100644 index 0000000000..9080ecb288 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0043-corstone1000-boot-index-from-active.patch @@ -0,0 +1,42 @@ +From b32aee10c66a9c2a3b6b948ad957deca3391c4bf Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva <rui.silva@linaro.org> +Date: Mon, 27 Feb 2023 14:40:13 +0000 +Subject: [PATCH 43/43] corstone1000: boot index from active + +In our platform, the Secure Enclave is the one who control +all the boot tries and status, so, every time we get here +we know that the we are booting from the active index. + +Upstream-Status: Pending +Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> +--- + board/armltd/corstone1000/corstone1000.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c +index 0923ca6e8c5b..e949edb79745 100644 +--- a/board/armltd/corstone1000/corstone1000.c ++++ b/board/armltd/corstone1000/corstone1000.c +@@ -118,7 +118,18 @@ int dram_init_banksize(void) + + void fwu_plat_get_bootidx(int *boot_idx) + { +- *boot_idx = corstone1000_boot_idx; ++ int ret; ++ ++ /* ++ * in our platform, the Secure Enclave is the one who control ++ * all the boot tries and status, so, every time we get here ++ * we know that the we are booting from the active index ++ */ ++ ret = fwu_get_active_index(boot_idx); ++ if (ret < 0) ++ log_err("corstone1000: failed to read active index\n"); ++ ++ return ret; + } + + int board_late_init(void) +-- +2.39.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0001-Add-vexpress_aemv8a_aarch32-variant.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0001-Add-vexpress_aemv8a_aarch32-variant.patch deleted file mode 100644 index 5138335eb4..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0001-Add-vexpress_aemv8a_aarch32-variant.patch +++ /dev/null @@ -1,184 +0,0 @@ -From 424d186ab0a0c4dd62dfb13ac87e8d1fd26c101e Mon Sep 17 00:00:00 2001 -From: Anders Dellien <anders.dellien@arm.com> -Date: Thu, 23 Jul 2020 17:32:55 +0100 -Subject: [PATCH 1/2] Add vexpress_aemv8a_aarch32 variant - -The ARM AEMv8 FVP model can be run in Aarch64 or Aarch32 mode. Aarch32 -support is enable per-CPU when launching the model, eg: - --C cluster0.cpu0.CONFIG64=0 - -This patch adds a new defconfig and some variant specific selections in -vexpress_armv8a.h. - -This patch is co-authored with Soby Mathew <Soby.Mathew@arm.com>. - -Upstream-Status: Denied - -For upstream discussion, please visit -https://www.mail-archive.com/u-boot@lists.denx.de/msg233429.html - -Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org> -Signed-off-by: Asha R <asha.r@arm.com> -Signed-off-by: Anders Dellien <anders.dellien@arm.com> ---- - arch/arm/Kconfig | 5 +++ - board/armltd/vexpress64/Kconfig | 2 +- - configs/vexpress_aemv8a_aarch32_defconfig | 40 ++++++++++++++++++ - include/configs/vexpress_aemv8.h | 50 +++++++++++++++-------- - 4 files changed, 80 insertions(+), 17 deletions(-) - create mode 100644 configs/vexpress_aemv8a_aarch32_defconfig - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index 4567c183fb84..99cc414d6760 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1250,6 +1250,11 @@ config TARGET_VEXPRESS64_BASE_FVP - select PL01X_SERIAL - select SEMIHOSTING - -+config TARGET_VEXPRESS64_BASE_FVP_AARCH32 -+ bool "Support Versatile Express ARMv8a 32-bit FVP BASE model" -+ select CPU_V7A -+ select SEMIHOSTING -+ - config TARGET_VEXPRESS64_JUNO - bool "Support Versatile Express Juno Development Platform" - select ARM64 -diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig -index 4aab3f092ecb..0a5e3fcc004a 100644 ---- a/board/armltd/vexpress64/Kconfig -+++ b/board/armltd/vexpress64/Kconfig -@@ -1,4 +1,4 @@ --if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO -+if TARGET_VEXPRESS64_BASE_FVP || TARGET_VEXPRESS64_JUNO || TARGET_VEXPRESS64_BASE_FVP_AARCH32 - - config SYS_BOARD - default "vexpress64" -diff --git a/configs/vexpress_aemv8a_aarch32_defconfig b/configs/vexpress_aemv8a_aarch32_defconfig -new file mode 100644 -index 000000000000..9c5c3367ec4d ---- /dev/null -+++ b/configs/vexpress_aemv8a_aarch32_defconfig -@@ -0,0 +1,40 @@ -+CONFIG_ARM=y -+CONFIG_SYS_ARCH_TIMER=y -+CONFIG_TARGET_VEXPRESS64_BASE_FVP_AARCH32=y -+CONFIG_SYS_TEXT_BASE=0x88000000 -+CONFIG_SYS_MALLOC_F_LEN=0x2000 -+CONFIG_NR_DRAM_BANKS=2 -+CONFIG_IDENT_STRING=" vexpress_aemv8a fvp aarch32" -+CONFIG_REMAKE_ELF=y -+CONFIG_SYS_LOAD_ADDR=0x90000000 -+CONFIG_BOOTDELAY=1 -+CONFIG_USE_BOOTARGS=y -+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 systemd.log_target=null root=/dev/vda1 rw androidboot.hardware=fvpbase rootwait loglevel=9" -+# CONFIG_DISPLAY_CPUINFO is not set -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_HUSH_PARSER=y -+CONFIG_SYS_PROMPT="fvp32# " -+# CONFIG_CMD_CONSOLE is not set -+CONFIG_CMD_BOOTZ=y -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_EDITENV is not set -+# CONFIG_CMD_ENV_EXISTS is not set -+CONFIG_CMD_MEMTEST=y -+CONFIG_CMD_ARMFLASH=y -+# CONFIG_CMD_LOADS is not set -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_DHCP=y -+# CONFIG_CMD_NFS is not set -+CONFIG_CMD_MII=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_FAT=y -+CONFIG_DM=y -+CONFIG_MTD_NOR_FLASH=y -+CONFIG_FLASH_CFI_DRIVER=y -+CONFIG_SYS_FLASH_CFI=y -+CONFIG_DM_SERIAL=y -+CONFIG_PL01X_SERIAL=y -+CONFIG_OF_LIBFDT=y -+CONFIG_REMAKE_ELF=y -diff --git a/include/configs/vexpress_aemv8.h b/include/configs/vexpress_aemv8.h -index f0c5ceb3849a..854fbb41bfc1 100644 ---- a/include/configs/vexpress_aemv8.h -+++ b/include/configs/vexpress_aemv8.h -@@ -86,7 +86,7 @@ - #endif - #endif /* !CONFIG_GICV3 */ - --#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH) -+#if (defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_AARCH32)) && !defined(CONFIG_DM_ETH) - /* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */ - #define CONFIG_SMC91111 1 - #define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000) -@@ -114,7 +114,7 @@ - #ifdef CONFIG_TARGET_VEXPRESS64_JUNO - #define PHYS_SDRAM_2 (0x880000000) - #define PHYS_SDRAM_2_SIZE 0x180000000 --#elif CONFIG_NR_DRAM_BANKS == 2 -+#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2 - #define PHYS_SDRAM_2 (0x880000000) - #define PHYS_SDRAM_2_SIZE 0x80000000 - #endif -@@ -171,23 +171,41 @@ - "fdt_addr_r=0x80000000\0" \ - BOOTENV - --#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP -+#elif defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) || \ -+ defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP_AARCH32) - --#define VEXPRESS_KERNEL_ADDR 0x80080000 --#define VEXPRESS_FDT_ADDR 0x8fc00000 --#define VEXPRESS_BOOT_ADDR 0x8fd00000 --#define VEXPRESS_RAMDISK_ADDR 0x8fe00000 -+#define VEXPRESS_KERNEL_ADDR 0x80080000 -+#define VEXPRESS_FDT_ADDR 0x8fc00000 -+#define VEXPRESS_BOOT_ADDR 0x8fd00000 -+#define VEXPRESS_RAMDISK_ADDR 0x8fe00000 - --#define CONFIG_EXTRA_ENV_SETTINGS \ -+#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ -- "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ -- "ramdisk_name=ramdisk.img\0" \ -- "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ -- "fdtfile=devtree.dtb\0" \ -- "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ -- "boot_name=boot.img\0" \ -- "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" -- -+ "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \ -+ "ramdisk_name=ramdisk.img\0" \ -+ "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \ -+ "fdtfile=devtree.dtb\0" \ -+ "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \ -+ "boot_name=boot.img\0" \ -+ "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0" -+ -+#ifndef CONFIG_BOOTCOMMAND -+#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr_r}; then " \ -+ " set bootargs; " \ -+ " abootimg addr ${boot_addr_r}; " \ -+ " abootimg get dtb --index=0 fdt_addr_r; " \ -+ " bootm ${boot_addr_r} ${boot_addr_r} " \ -+ " ${fdt_addr_r}; " \ -+ "else; " \ -+ " smhload ${kernel_name} ${kernel_addr_r}; " \ -+ " smhload ${fdtfile} ${fdt_addr_r}; " \ -+ " smhload ${ramdisk_name} ${initrd_addr_r} "\ -+ " initrd_end; " \ -+ " fdt addr ${fdt_addr_r}; fdt resize; " \ -+ " fdt chosen ${ramdisk_addr_r} ${initrd_end}; " \ -+ " bootz $kernel_addr_r - $fdt_addr_r; " \ -+ "fi" -+#endif - #endif - - /* Monitor Command Prompt */ --- -2.30.2 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0002-Revert-vexpress64-Enable-OF_CONTROL-and-OF_BOARD-for.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0002-Revert-vexpress64-Enable-OF_CONTROL-and-OF_BOARD-for.patch deleted file mode 100644 index d916d42061..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base-arm32/0002-Revert-vexpress64-Enable-OF_CONTROL-and-OF_BOARD-for.patch +++ /dev/null @@ -1,111 +0,0 @@ -From e896d48c57d272327410416887f34ac0db550390 Mon Sep 17 00:00:00 2001 -From: Jon Mason <jdmason@kudzu.us> -Date: Mon, 13 Jun 2022 10:59:53 -0400 -Subject: [PATCH 2/2] Revert "vexpress64: Enable OF_CONTROL and OF_BOARD for - VExpress64" - -This patch only works for aarch64 (as the 'x' registers are not -available for ARMv7). Since this platform is ARMv7 in the previous -patch, this either needs to be changed or removed. I opted to remove -it, as it doesn't seem to be necessary to boot the virtual hardware. -Given that the previous patch was rejected upstream, it is not -appropriate to fix this upstream. - -Upstream-Status: Inappropriate -Signed-off-by: Jon Mason <jon.mason@arm.com> - -This reverts commit 2661397464e47d45cd25bbc5e6b9de7594b3268d. ---- - board/armltd/vexpress64/Makefile | 2 +- - board/armltd/vexpress64/lowlevel_init.S | 12 ------------ - board/armltd/vexpress64/vexpress64.c | 26 ------------------------- - 3 files changed, 1 insertion(+), 39 deletions(-) - delete mode 100644 board/armltd/vexpress64/lowlevel_init.S - -diff --git a/board/armltd/vexpress64/Makefile b/board/armltd/vexpress64/Makefile -index 1878fbed4ec9..868dc4f629f2 100644 ---- a/board/armltd/vexpress64/Makefile -+++ b/board/armltd/vexpress64/Makefile -@@ -3,5 +3,5 @@ - # (C) Copyright 2000-2004 - # Wolfgang Denk, DENX Software Engineering, wd@denx.de. - --obj-y := vexpress64.o lowlevel_init.o -+obj-y := vexpress64.o - obj-$(CONFIG_TARGET_VEXPRESS64_JUNO) += pcie.o -diff --git a/board/armltd/vexpress64/lowlevel_init.S b/board/armltd/vexpress64/lowlevel_init.S -deleted file mode 100644 -index 3dcfb85d0e9a..000000000000 ---- a/board/armltd/vexpress64/lowlevel_init.S -+++ /dev/null -@@ -1,12 +0,0 @@ --/* SPDX-License-Identifier: GPL-2.0 */ --/* -- * (C) Copyright 2021 Arm Limited -- */ -- --.global save_boot_params --save_boot_params: -- -- adr x8, prior_stage_fdt_address -- str x0, [x8] -- -- b save_boot_params_ret -diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c -index 5e22e89824ee..cedab86d984b 100644 ---- a/board/armltd/vexpress64/vexpress64.c -+++ b/board/armltd/vexpress64/vexpress64.c -@@ -92,15 +92,7 @@ int dram_init_banksize(void) - return 0; - } - --/* Assigned in lowlevel_init.S -- * Push the variable into the .data section so that it -- * does not get cleared later. -- */ --unsigned long __section(".data") prior_stage_fdt_address; -- - #ifdef CONFIG_OF_BOARD -- --#ifdef CONFIG_TARGET_VEXPRESS64_JUNO - #define JUNO_FLASH_SEC_SIZE (256 * 1024) - static phys_addr_t find_dtb_in_nor_flash(const char *partname) - { -@@ -145,11 +137,9 @@ static phys_addr_t find_dtb_in_nor_flash(const char *partname) - - return ~0; - } --#endif - - void *board_fdt_blob_setup(int *err) - { --#ifdef CONFIG_TARGET_VEXPRESS64_JUNO - phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART); - - *err = 0; -@@ -159,22 +149,6 @@ void *board_fdt_blob_setup(int *err) - } - - return (void *)fdt_rom_addr; --#endif -- --#ifdef VEXPRESS_FDT_ADDR -- if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) { -- *err = 0; -- return (void *)VEXPRESS_FDT_ADDR; -- } --#endif -- -- if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) { -- *err = 0; -- return (void *)prior_stage_fdt_address; -- } -- -- *err = -ENXIO; -- return NULL; - } - #endif - --- -2.30.2 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/0001-Revert-vexpress64-pick-DRAM-size-from-DT.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/0001-Revert-vexpress64-pick-DRAM-size-from-DT.patch new file mode 100644 index 0000000000..d551622460 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/0001-Revert-vexpress64-pick-DRAM-size-from-DT.patch @@ -0,0 +1,44 @@ +From 4f649e0a3e0f9ed1f0d6efdff5b14cdc40d84201 Mon Sep 17 00:00:00 2001 +From: Jon Mason <jon.mason@arm.com +Date: Thu, 2 Mar 2023 15:22:08 +0000 +Subject: [PATCH] Revert "vexpress64: pick DRAM size from DT" + +This reverts commit 1a1143a45457161e90ea4cd5f3b0561d924ed8fe. + +DRAM is determined via dtb in recent versions. Since fvp isn't +reading and specifying a dtb, this fails and hangs u-boot. Remove this +and go back to the way things were. + +Signed-off-by: Jon Mason <jon.mason@arm.com> +Upstream-Status: Inappropriate +--- + board/armltd/vexpress64/vexpress64.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c +index af326dc6f453..e8ce88b22c5a 100644 +--- a/board/armltd/vexpress64/vexpress64.c ++++ b/board/armltd/vexpress64/vexpress64.c +@@ -88,12 +88,20 @@ int board_init(void) + + int dram_init(void) + { +- return fdtdec_setup_mem_size_base(); ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ return 0; + } + + int dram_init_banksize(void) + { +- return fdtdec_setup_memory_banksize(); ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++#ifdef PHYS_SDRAM_2 ++ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; ++ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; ++#endif ++ ++ return 0; + } + + /* Assigned in lowlevel_init.S diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/bootargs.cfg b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/bootargs.cfg index 716600f482..13f4cb4713 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/bootargs.cfg +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-base/bootargs.cfg @@ -1,3 +1,4 @@ CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda1 rw rootwait" +CONFIG_BOOTCOMMAND="booti $kernel_addr_r - $fdt_addr_r" # Our FVP support CRC instructions CONFIG_ARM64_CRC32=y diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index 9cc1bcd945..6e68a421c1 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -44,19 +44,31 @@ SRC_URI:append:corstone1000 = " \ file://0024-arm-corstone1000-esrt-support.patch \ file://0025-efi_setup-discover-FF-A-bus-before-raising-EFI-start.patch \ file://0026-corstone1000-enable-distro-booting-command.patch \ + file://0027-drivers-nvmxip-introduce-NVM-XIP-block-storage-emula.patch \ + file://0028-sandbox64-fix-return-unsigned-long-in-readq.patch \ + file://0029-sandbox64-add-support-for-NVMXIP-QSPI.patch \ + file://0030-corstone1000-add-NVM-XIP-QSPI-device-tree-node.patch \ + file://0031-corstone1000-enable-NVM-XIP-QSPI-flash.patch \ + file://0032-sandbox64-add-a-test-case-for-UCLASS_NVMXIP.patch \ + file://0033-nvmxip-provide-a-u-boot-shell-test-command.patch \ + file://0034-corstone1000-add-fwu-metadata-store-info.patch \ + file://0035-nvmxip-shorter-block-device-name.patch \ + file://0036-efi_boottime-allow-to-reset-a-path-after-boot.patch \ + file://0037-fwu_metadata-make-sure-structures-are-packed.patch \ + file://0038-corstone1000-add-boot-index.patch \ + file://0039-corstone1000-adjust-boot-bank-and-kernel-location.patch \ + file://0040-corstone1000-add-nvmxip-fwu-mdata-and-gpt-options.patch \ + file://0041-nvmxip-move-header-to-include.patch \ + file://0042-corstone1000-set-kernel_addr-based-on-boot_idx.patch \ + file://0043-corstone1000-boot-index-from-active.patch \ " # # FVP BASE # -SRC_URI:append:fvp-base = " file://bootargs.cfg" - -# -# FVP BASE ARM32 -# -SRC_URI:append:fvp-base-arm32 = " file://0001-Add-vexpress_aemv8a_aarch32-variant.patch \ - file://0002-Revert-vexpress64-Enable-OF_CONTROL-and-OF_BOARD-for.patch \ - " +SRC_URI:append:fvp-base = " file://bootargs.cfg \ + file://0001-Revert-vexpress64-pick-DRAM-size-from-DT.patch \ + " # # FVP BASER |