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| author | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2019-04-05 22:28:33 +0300 |
|---|---|---|
| committer | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2019-04-05 22:31:28 +0300 |
| commit | 193236933b0f4ab91b1625b64e2187e2db4e0e8f (patch) | |
| tree | e12769d7c76d8b0517d6de3d3c72189753d253ed /meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch | |
| parent | bd93df9478f2f56ffcbc8cb88f1709c735dcd85b (diff) | |
| download | openbmc-193236933b0f4ab91b1625b64e2187e2db4e0e8f.tar.xz | |
reset upstream subtrees to HEAD
Reset the following subtrees on HEAD:
poky: 8217b477a1(master)
meta-xilinx: 64aa3d35ae(master)
meta-openembedded: 0435c9e193(master)
meta-raspberrypi: 490a4441ac(master)
meta-security: cb6d1c85ee(master)
Squashed patches:
meta-phosphor: drop systemd 239 patches
meta-phosphor: mrw-api: use correct install path
Change-Id: I268e2646d9174ad305630c6bbd3fbc1a6105f43d
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Diffstat (limited to 'meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch')
| -rw-r--r-- | meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch b/meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch new file mode 100644 index 0000000000..865ad3287b --- /dev/null +++ b/meta-openembedded/meta-oe/recipes-dbs/postgresql/files/0001-Add-support-for-RISC-V.patch @@ -0,0 +1,41 @@ +From b06a228a5fd1589fc9bed654b3288b321fc21aa1 Mon Sep 17 00:00:00 2001 +From: "Richard W.M. Jones" <rjones@redhat.com> +Date: Sun, 20 Nov 2016 15:04:52 +0000 +Subject: [PATCH] Add support for RISC-V. + +The architecture is sufficiently similar to aarch64 that simply +extending the existing aarch64 macro works. +--- + src/include/storage/s_lock.h | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h +index 3fe29ce..7cd578f 100644 +--- a/src/include/storage/s_lock.h ++++ b/src/include/storage/s_lock.h +@@ -316,11 +316,12 @@ tas(volatile slock_t *lock) + + /* + * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available. ++ * On RISC-V, the same. + * + * We use the int-width variant of the builtin because it works on more chips + * than other widths. + */ +-#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) ++#if defined(__arm__) || defined(__arm) || defined(__aarch64__) || defined(__aarch64) || defined(__riscv) + #ifdef HAVE_GCC__SYNC_INT32_TAS + #define HAS_TEST_AND_SET + +@@ -337,7 +338,7 @@ tas(volatile slock_t *lock) + #define S_UNLOCK(lock) __sync_lock_release(lock) + + #endif /* HAVE_GCC__SYNC_INT32_TAS */ +-#endif /* __arm__ || __arm || __aarch64__ || __aarch64 */ ++#endif /* __arm__ || __arm || __aarch64__ || __aarch64 || __riscv */ + + + /* S/390 and S/390x Linux (32- and 64-bit zSeries) */ +-- +2.9.3 + |