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| author | Andrew Geissler <geissonator@yahoo.com> | 2020-12-12 01:25:29 +0300 |
|---|---|---|
| committer | Andrew Geissler <geissonator@yahoo.com> | 2020-12-12 01:25:34 +0300 |
| commit | 10fa14942b9cb27780f9496382107516639208b4 (patch) | |
| tree | f4b195505178e47c4b21ece7b3a898d9402b2daa /meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch | |
| parent | 6d8913e6c02e578d4e41b7fe88113f4e4822992d (diff) | |
| download | openbmc-10fa14942b9cb27780f9496382107516639208b4.tar.xz | |
meta-xilinx: subtree update:569f52f275..b3e37df5d9
Mark Hatle (11):
meta-microblaze: Move gcc patch that was missed in the prior work
Uprev standalone toolchain bbappends
pmu-firmware: Latest toolchain always treats 'assert' as a macro
binutils: update to early gatesgarth version
gdb: update to early gatesgarth version
gcc: update to early gatesgarth version
newlib: update to early gatesgarth version
machine/aarch64-tc.conf: Fix incorrect ilp32 pkgarch
libgcc.bbappend: Clear empty lib directory
newlib: Upstream now disabled builtin symbols
gdb: Fix on-target GDB compilation
Sai Hari Chandana Kalluri (5):
linux-xlnx_2020.2: Fix previous git cherry-pick
xrt: Remove stale patch to fix endian issues with latest version of boost
opencl-clhpp, ocl-icd: Remove recipes from meta-xilinx
esw.bbclass: Remove trailing / after S
Remove recipe bbappends pointing to older versions
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I18b028388a5b55a49ef135b98290228fa797e38d
Diffstat (limited to 'meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch')
| -rw-r--r-- | meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch new file mode 100644 index 0000000000..cce812bbc6 --- /dev/null +++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -0,0 +1,48 @@ +From 03429c91d1db134e1deda4c8e58bc0939d5fedf9 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 11/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added + ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os + optimization is used. lshrsi3_with_size_opt is being removed as it has + conflicts with unsigned int variables + +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index eba2776ae56..187ad522dcc 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1508,6 +1508,27 @@ + (set_attr "length" "4,4")] + ) + ++(define_insn "*ashrsi3_with_size_opt" ++ [(set (match_operand:SI 0 "register_operand" "=&d") ++ (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "immediate_operand" "I")))] ++ "(INTVAL (operands[2]) > 5 && optimize_size)" ++ { ++ operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("ori\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addik\t%3,%3,-1", operands); ++ output_asm_insn ("bneid\t%3,.-4", operands); ++ return "sra\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "20")] ++) ++ + (define_insn "*ashrsi_inline" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +-- +2.17.1 + |