diff options
| author | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2019-08-17 00:08:17 +0300 |
|---|---|---|
| committer | Brad Bishop <bradleyb@fuzziesquirrel.com> | 2019-08-17 00:10:30 +0300 |
| commit | 26bdd44576f25d63bf32632369b0cbdd94c93d7a (patch) | |
| tree | 506ed5dc7d2814cc3462a943f6222e02b4fb4146 /meta-xilinx | |
| parent | 30e7d8427b05d123ed1ca269e3c027b2425bd168 (diff) | |
| download | openbmc-26bdd44576f25d63bf32632369b0cbdd94c93d7a.tar.xz | |
subtree updates
meta-openembedded: 64974b8779..c95842cdca:
Adrian Bunk (46):
modemmanager: Remove the obsolete dependency on dbus-glib
gpsd: Remove the obsolete dependency on dbus-glib
eggdbus: Remove this obsolete package
sanity-meta-gnome: Remove obsolete class
gssdp: Merge inc
vlc: notify switched to GTK+3 some time ago
tremor: Upgrade 20150107 -> 20180319
vlc: Remove the obsolete dependency on dbus-glib
blueman: Enable thunar support by default but don't rdepend on it
gnome-bluetooth: Drop bluez4 support
networkmanager: Drop bluez4 support
packagegroup-meta-networking-connectivity: Correct a DISTRO_FEATURES check
packagegroup-tools-bluetooth: Remove bluez4 support
cpprest: Fix build failure with gcc 8
packagegroup-basic: Remove bluez4 support
packagegroup-meta-oe: Remove bogus bluez4 DISTRO_FEATURES checks
esound: Remove this obsolete package
gpsd: Remove obsolete musl patch
gpsd: Don't build without optimization
zeromq: Upgrade 4.3.1 -> 4.3.2
obex-data-server: Drop bluez4 support
openobex: Drop bluez4 support
gpsd: Drop bluez4 support
libao: Remove the non-default esound PACKAGECONFIG
gpsd: Disable manpage building by config option instead of patching
gpsd: Upgrade 3.18.1 -> 3.19
gnome-desktop3: Fix REQUIRED_DISTRO_FEATURES
meta-gnome: Remove GNOME_COMPRESS_TYPE = "xz" in recipes
jasper: Use the new upstream GitHub location instead of the defunct tarball URL
fluidsynth: Add PACKAGECONFIG for readline
meta-multimedia: Remove GNOME_COMPRESS_TYPE = "xz" in recipes
udisks: Remove this obsolete version
gpsd: Switch from python-scons-native to python3-scons-native
meta-gnome: Inherit gnomebase instead of gnome
meta-oe: Inherit gnomebase instead of gnome
libgsf: Drop the obsolete inherit gconf
gnome-system-monitor: Add DEPENDS on polkit
meta-oe: Change some ftp:// URIs to http(s)://
meta-oe: Use GNU_MIRROR in more recipes
wireshark: Use an upstream URL that stays valid longer
modemmanager: Use a simpler workaround for the clang build
network-manager-applet: Remove obsolete do_configure_append
network-manager-applet: Remove the obsolete DEPENDS on gconf
wv: Remove, abiword was the only user
gtkmathview: Remove, abiword was the last user
t1lib: Remove, gtkmathview was the last user
Alex Kiernan (6):
keyutils: Fix build with usrmerge
iwd: update to 0.18
libzip: Upgrade 1.5.1 -> 1.5.2
zstd: New recipe
zstd: Update 1.4.0 -> 1.4.2
iwd: Upgrade 0.18 -> 0.19
Alexander Kanavin (3):
python-matplotlib: remove the python 2.x version of the recipe
python-oauthlib: remove the 2.x version of the recipe
python-pandas: remove the python 2.x version of the recipe
Alistair Francis (3):
gpsd: Upgrade from 3.17 to 3.18.1
gpsd: Fix the systemd service run paths
python: pypi: Add python3-term
Anatol Belski (1):
gperftools: separate off libtcmalloc-minimal
Andreas Müller (2):
meta-xfce: Make Kai Kang layer maintainer
abiword: remove
Andrej Valek (2):
nodejs: 10.15.3 -> 10.16.0
nodejs: 10.16.0 -> 10.16.2
André Draszik (1):
layer.conf: ignore wireless-regdb->crda dep for siggen purposes
Ankit Navik (1):
safec: Remove aarch64 from COMPATIBLE_HOST
Anuj Mittal (2):
xterm: upgrade 330 -> 347
libsdl: import from OE-Core
Armin Kuster (5):
keyutils: update to 1.6
keyutils: improve ptests
keyutils: fix QA WARNING
keyutils: fix pulling in glibc when musl enabled
keyutils: fix library install path
Arturo Buzarra (1):
lvm2: Fix RDEPEND on lvm2 to lvm2-udevrules
Ayoub Zaki (1):
pegtl: Initial recipe
Bartosz Golaszewski (2):
bats: new package
libgpiod: bump version to v1.4.1
Beniamin Sandu (1):
unbound: create recipe for version 1.9.2
Callaghan, Dan (1):
unixodbc: mysql5 is not required but readline is
Changqing Li (15):
python-pygobject: fix install dir for python2
dlm: upgrade 4.0.7 -> 4.0.9
uthash: remove uthash-ptest dependencies
waf-samba: switch to python3
libtevent: upgrade 0.9.37 -> 0.10.0
libtdb: upgrade 1.3.17 -> 1.4.0
libtalloc: upgrade 2.1.14 -> 2.2.0
samba: upgrade 4.8.12 -> 4.10.5
libldb: upgrade 1.4.1 -> 1.5.4
volume-key: fix "Nothing RPROVIDES" when multilib enabled
isomd5sum: fix "Nothing RPROVIDES" when multilib enabled
satyr: fix "Nothing RPROVIDES" when multilib enabled
libtevent: fix do_package_qa issue
libtdb: fix do_package_qa issue
fio: Delete redundant tag
Chin Huat Ang (1):
opencv: 3.4.5 -> 4.1.0
Denys Dmytriyenko (1):
ufs-tool: add tool to access UFS (Universal Flash Storage) devices
Douglas Royds (2):
grpc: DEPENDS on googletest
packagegroup-meta-oe: RDEPENDS on googletest
Drew Moseley (1):
networkmanager: Use ALTERNATIVES for resolv-conf handling.
Erik Botö (1):
paho-mqtt-c: enable SSL
Fabian Klemp (1):
openvpn: respect pid file in init.d service start
Gianfranco Costamagna (3):
iniparser: add initial recipe
cpprest: update to 2.10.14
cpprest: Do not export Werror from build system instead of adding -Wno-error to the same build command
He Zhe (1):
drbd-utils: Fix netlink failure with nested attributes for kernel v5.2
Hongxu Jia (24):
packagegroup-xfce-extended: conditional runtime recommends on xfce-polkit
xfce-polkit: add required distro feature check to polkit
xfce4-session: optional support polkit
upower: remove polkit dependency
gvfs: add meson option admin and udisks2 to PACKAGECONFIG
mongodb: add to PNBLACKLIST
itstool: use libxml2 to instead of python3-lxml
meta-multimedia: add layer depends on meta-python
itstool: use libxml2 to instead of python3-lxml
python-six: remove duplicated recipe
libauthen-radius-perl: ptest requires meta-networking to be present
xfce4-panel: use lxdm to replace dm-tool
drop lxdm_%.bbappend
python3-pykickstart: 3.18 -> 3.20
python3-blivet: 3.1.2 -> 3.1.4
python-pyparted/python3-pyparted: 3.11.1 -> 3.11.2
libbytesize: 1.4 -> 2.0
libblockdev: 2.20 -> 2.22
network-manager-applet: 1.8.20 -> 1.8.22
thin-provisioning-tools: 0.7.6 -> 0.8.5
libreport: 2.9.7 -> 2.10.0
python3-blivetgui: fix blivet-gui broken
php: remove 5.6.40
lmsensors: support package lmsensors
Jackie Huang (1):
keyutils: add new recipe
Jason Wessel (1):
libbytesize: Add depends for gettext-native
Joshua Lock (3):
python-cffi: add missing RDEPENDS on pycparser
python-attrs: add native BBCLASSEXTEND
python-dateutil: add native BBCLASSEXTEND
Kai Kang (39):
mozjs: fix configure failure on CentOS 7.6
libvncserver: update to latest commit 1354f7f
libxfce4util: 4.13.3 -> 4.13.4
libxfce4ui: 4.13.5 -> 4.13.6
exo: 0.12.5 -> 0.12.6
xfconf: 4.13.7 -> 4.13.8
thunar: 1.8.6 -> 1.8.7
xfce4-session: 4.13.2 -> 4.13.3
xfwm4: 4.13.2 -> 4.13.3
xfdesktop: 4.13.4 -> 4.13.5
xfce4-power-manager: 1.6.2 -> 1.6.3
xfce4-panel: 4.13.5 -> 4.13.6
xfce4-dev-tools: 4.12.0 -> 4.13.0
thunar-volman: 0.9.2 -> 0.9.3
garcon: 0.6.2 -> 0.6.3
xfce4-settings: 4.12.4 -> 4.13.7
xfce4-pulseaudio-plugin: add dependency dbus-glib
xfce4-verve-plugin: 1.1.0 -> 2.0.0
net-snmp: update SRC_URI
xfwm4: fix assertion error
poppler: toggle gobject-introspection support
xfce4-settings: rrecommends xfce4-datetime-setter
xfce4-datetime-setter: add recipe
libxfce4util: 4.13.4 -> 4.14.0
xfconf: 4.13.8 -> 4.14.1
libxfce4ui: 4.13.6 -> 4.14.1
exo: 0.12.6 -> 0.12.8
garcon: 0.6.3 -> 0.6.4
thunar: 1.8.7 -> 1.8.9
thunar-volman: 0.9.3 -> 0.9.5
tumbler: 0.2.0 -> 0.2.7
xfce4-appfinder: 4.13.3 -> 4.14.0
xfce4-dev-tools: 4.13.0 -> 4.14.0
xfce4-panel: 4.13.6 -> 4.14.0
xfce4-power-manager: 1.6.3 -> 1.6.5
xfce4-session: 4.13.3 -> 4.14.0
xfce4-settings: 4.13.7 -> 4.14.0
xfdesktop: 4.13.5 -> 4.14.1
xfwm4: 4.13.3 -> 4.14.0
Khem Raj (44):
wvdial: Fix build with musl
librelp: Pass Wno-error to compiler
recipes: Use BPN instead of PN in SRC_URIs
cli11: Refresh patch to fix fuzz
sthttpd: Use git SRC_URI instead of github archive
arno-iptables-firewall: Switch to git fetcher
firewalld: Update to 0.6.3->0.6.4
python-matplotlib: Use git src_uri
mpv: Switch to using git fetcher
x11vnc: Switch to git fetcher
dumb-init: Switch to git fetcher
pam-plugin-ldapdb: Use git fetcher
libuv: Switch to using git fetcher
usbctl: Switch to git fetcher
pmdk: Fix libdir which is multi-lib aware
kexec-tools-klibc: Refresh patch with no code change
log4cplus: Fix build with gold linker
orage: Fix build with libical3
pegtl: Fix build with clang/libc++
postfix: Fix build failures with glibc 2.30
snort: Fix build with glibc 2.30
opensaf: Add configure time check to detect gettid API in libc
ypbind-mt: Fix build with glibc 2.30
openocd: Fix build with glibc 2.30
netkit-rusers: Add dep on rpcsvc-proto for rpc headers
collectd: Fix build with glibc 2.30
alsa-oss: Drop now not needed patch
klcc-cross: Recognise --unwindlib clang option
libsub-exporter-progressive-perl: Remove unneeded DEPENDS_PN
libedit: Delete
sjf2410-linux-native: Do not include sys/io.h
gradm: Upgrade to 3.1-201903191516 release
pmdk: Fix packaging errors when building on non-x86 host
klibc: Pass -fno-builtin-bcmp with musl/clang combo
graphviz: Fix build error that surfaced with latest pango
graphviz: Do not build tcl support for target
python-grpcio: Use gettid API from glibc 2.30+
grpc: Update to 1.22.0
android-tools: Fix build with glibc 2.30
iperf2: Upgrade to 2.0.13
netkit-rusers: Depend on rpcsvc-proto-native for rpcgen tool
kpatch: Pass ARCH from environment
python3-pillow: Provide python3-imaging
netkit-rusers: Fix cross-build after glibc dropped rpc
Laszlo Toth (1):
networkmanager: fix typo in nonarch_base_libdir
Liwei Song (2):
pm-graph: fix time format parse error
fio: fix first direct IO errored when ioengine is splice
Luca Boccassi (2):
python-pygobject: move python-setuptools from RDEPENDS to DEPENDS
python-pygobject: remove build-dependency on setuptools and add dependency on pkgutil
Luca Ceresoli (4):
fuse-exfat: moved to github
exfat-utils: moved to github
fuse-exfat: update 1.2.3 -> 1.3.0
exfat-utils: update 1.2.3 -> 1.3.0
Luca Palano (1):
Netdata upgrade: 1.8.0 -> 1.16.0
Maciej Pijanowski (8):
python3-websockets: upgrade to 8.0.2
python3-multidict: upgrade to 4.5.2
python-engineio: upgrade to 3.9.3
python-socketio: upgrade to 4.3.1
python-aiohttp.inc: add missing RDEPENDS
python-async-timeout: add asyncio to RDEPENDS
python-socketio.inc: add missing RDEPENDS
python3-aiofiles: add recipe
Mariano Lopez (1):
nftables: 0.9.0 > 0.9.1
Martin Jansa (8):
protobuf: fix build with gold
SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS add lsb and util-linux for phoronix-test-suite
oprofile: drop kernel-vmlinux from RRECOMMENDS
libdbi-perl: prevent native libdbi-perl depending on target perl
redis: backport a fix for stack trace generation on aarch64
ntop: fix missing return from non-void function
python3-twofish: Fix missing return statements in module stubs
kernel-selftest: skip -Werror=format-security and fortify
Max Krummenacher (1):
joe: update to 4.6
Mikko Rapeli (2):
protobuf: fix ptest compilation with hardening flags
stress-ng: delete recipe
Mingli Yu (7):
fio: Upgrade to 3.15
crash: Upgrade to 7.2.6
makedumpfile: Upgrade to 1.6.6
hwloc: Upgrade to 1.11.13
iperf3: Upgrade to 3.7
log4cplus: Upgrade to 2.0.4
log4cplus: remove gold linker setting
Oleksandr Kravchuk (22):
nghttp2: update to 1.39.1
drbd-utils: update to 9.10.0
drbd: update to 9.0.18-1
keepalived: update to 2.0.16
nano: update to 4.3
nuttcp: add systemd unit file
mbedtls: update to 2.16.2
dhcpcd: update to 7.2.2
freediameter: update to 1.2.1
sethdlc: set PV in filename
miniupnpd: update to 2.1.20190210
ipvsadm: update to 1.30
uftp: update to 4.9.11
libnftnl: update to 1.1.3
dhcpcd: update to 7.2.3
blueman: update to 2.1.1
uftp: update to 4.10
htpdate: update to 1.2.1
dhcpcd: update to 8.0.1
chrony: update to 3.5
wolfssl: update to 4.1.0
dhcpcd: update to 8.0.2
Ovidiu Panait (2):
python3-pillow: 5.4.1 -> 6.1
python3-pillow: Add python3-misc/logging/numbers to RDEPENDS
Paolo Valente (1):
s-suite: push SRCREV to version 3.5
Parthiban Nallathambi (1):
python3-matplotlib: add version 3.1.1
Pascal Bach (1):
protobuf: 1.3.1 -> 1.3.2
Paul Eggleton (3):
mraa: update to 2.0.0
upm: update to 2.0.0
picocom: update to 3.1
Pierre-Jean Texier (2):
stunnel: bump to version 5.55
cppzmq: bump to version 4.4.1
Piotr Tworek (1):
itstool: Don't use hardcoded, absolute path to python3 binary.
Qi.Chen@windriver.com (3):
turbostat: set PACKAGE_ARCH as MACHINE_ARCH
esmtp: use alternatives to manage /usr/lib/sendmail
postfix: use alternatives to manage /usr/lib/sendmail
Radovan Scasny (2):
dhcpcd: enable udev by default
dhcpcd: fix building with pkgconfig
Randy MacLeod (2):
poppler: update from 0.75.0 to 0.79.0
rsyslog: update from 8.1903.0 to 8.1907.0
Ricardo Ribalda Delgado (1):
fwts: Update to 19.06.00
Robert Joslyn (1):
cryptsetup: Don't enable udev for native build
Roman Stratiienko (1):
glmark2: Upgrade SRCREV to latest
Ross Burton (2):
gtk+: add (from oe-core)
gnome-themes-standard: add recipe for GTK+ 2 Adwaita
Ruslan Bilovol (2):
libnss-nisplus: Add recipe
kpatch: fix QA build errors for nativesdk
Saravanan Sekar (1):
liblightmodbus: Add version 2.0.2
Scott Ellis (1):
wireguard: Upgrade 20190406 to 20190702
Slater, Joseph (3):
drbd-utils: enable reproducible_build awareness
php: remove host specific info from header file
mozjs: do not expose intl api for mips64
Tim Orling (9):
libencode-perl: upgrade 2.94 -> 3.01; enable ptest
libdbi-perl: fix dependencies
libtest-nowarnings-perl: add recipe for 1.04
libdbd-sqlite-perl: upgrade 1.54 -> 1.62; enable ptest
libsub-uplevel-perl: add recipe for 0.36
libtest-warn-perl: add recipe for 0.36
libcgi-perl: upgrade 4.43 -> 4.44
libnet-ldap-perl: upgrade 0.65 -> 0.66; enable ptest
libunicode-linebreak-perl: upgrade 2017.004 -> 2019.001; enable ptest
Trevor Gamblin (2):
metacity; upgrade from 3.30.1 to 3.32.0
gvfs: upgrade from 1.40.0 to 1.40.2
Vincent Prince (1):
mongodb: add mongo shell as a PACKAGECONF option
William A. Kennington III via Openembedded-devel (5):
gtest: Googletest project is back under github.com/google/googletest
googletest: The gtest and gmock projects were combined under googletest in 2015
libtar: Enable libtar-native build
fmt: Init at 5.3.0
cli11: 1.7.1 -> 1.8.0
Windel Bouwman (3):
python-humanfriendly: Add recipe for the humanfriendly package.
Fix python-humanfriendly recipe for python2.
Add recipe for the coloredlogs python package.
Yi Zhao (7):
strongswan: upgrade 5.7.1 -> 5.8.0
snort: fix compile-host-path QA issue
cryptsetup: set the default luks format to LUKS1
libldb: upgrade 1.5.4 -> 1.5.5
samba: upgrade 4.10.5 -> 4.10.6
snort: upgrade 2.9.13 -> 2.9.14
snort: upgrade 2.9.14 -> 2.9.14.1
Yong, Jonathan (1):
icewm: add recipe
Yongxin Liu (3):
keyutils: move recipe and patches from meta-security to meta-oe
ndctl: v63 -> v65
pmdk: update from 1.4.2 to 1.6
Yuan Chao (9):
python-pycodestyle: upgrade 2.4.0 -> 2.5.0
python-lxml: upgrade 4.3.4 -> 4.4.0
python-configparser: upgrade 3.5.0 -> 3.7.4
protobuf: upgrade 3.9.0 -> 3.9.1
python-markupsafe: upgrade 1.0 -> 1.1.1
hostapd: upgrade 2.8 -> 2.9
python-configparser: upgrade 3.7.4 -> 3.8.1
python-lxml: upgrade 4.4.0 -> 4.4.1
python-pip: upgrade 19.2.1 -> 19.2.2
Zang Ruochen (47):
postgresql: upgrade 11.3 -> 11.4
wireshark: upgrade 3.0.1 -> 3.0.2
python-pygobject: upgrade 3.32.1 -> 3.32.2
python-alembic: upgrade 1.0.10 -> 1.0.11
logwatch: upgrade 7.4.3 -> 7.5.1
tcsh: upgrade 6.20.00 -> 6.21.00
python-cython: upgrade 0.29.10 -> 0.29.11
dialog: upgrade 1.3-20180621 -> 1.3-20190211
php: upgrade 7.3.6 -> 7.3.7
sessreg: upgrade 1.1.1 -> 1.1.2
python-typing: upgrade 3.6.6 -> 3.7.4
python-mako: upgrade 1.0.12 -> 1.0.13
python-pbr: upgrade 5.2.1 -> 5.4.0
python-cython: upgrade 0.29.11 -> 0.29.12
adcli: added new recipe.
python-pyflakes: upgrade 1.6.0 -> 2.1.1
python-protobuf: upgrade 3.8.0 -> 3.9.0
protobuf: upgrade 3.8.0 -> 3.9.0
setxkbmap: upgrade 1.3.1 -> 1.3.2
uftrace: upgrade 0.9.2 -> 0.9.3
wireshark: upgrade 3.0.2 -> 3.0.3
python-pbr: upgrade 5.4.0 -> 5.4.1
dstat: upgrade 0.7.3 -> 0.7.4
python-mako: upgrade 1.0.13 -> 1.0.14
xfsprogs: upgrade 5.0.0 -> 5.1.0
python-beautifulsoup4: upgrade 4.7.1 -> 4.8.0
xterm: upgrade 347 -> 348
python-pip: upgrade 19.1.1 -> 19.2.1
python-paste: upgrade 3.0.8 -> 3.1.0
syslog-ng: append syslog-ng.service
dialog: upgrade 1.3-20190211 -> 1.3-20190728
openldap: upgrade 2.4.47 -> 2.4.48
python-cython: upgrade 0.29.12 -> 0.29.13
libsodium: upgrade 1.0.17 -> 1.0.18
hwdata: upgrade 0.322 -> 0.326
python-jsonpatch: upgrade 1.23 -> 1.24
python-pyasn1: upgrade 0.4.5 -> 0.4.6
python-pyasn1-modules: upgrade 0.2.2 -> 0.2.6
python-pyparsing: upgrade 2.4.0 -> 2.4.2
python-pytest-runner: upgrade 4.2 -> 5.1
python-pytz: upgrade 2019.1 -> 2019.2
itstool: upgrade 2.0.5 -> 2.0.6
opensaf: upgrade 5.19.03 -> 5.19.07
libkcapi: upgrade 1.1.4 -> 1.1.5
mcelog: upgrade 162 -> 164
php: upgrade 7.3.7 -> 7.3.8
kpatch: upgrade 0.61 -> 0.71
Zheng Ruoqin (3):
python-mako: upgrade 1.0.14 -> 1.1.0
python-pbr: upgrade 5.4.1 -> 5.4.2
dnf-plugin-tui: new recipe
wouterlucas (1):
python-jsonref: add recipe
meta-phosphor: fbd01b6e08..fe8cee7488:
Brad Bishop (1):
meta-phosphor: sdk: react to upstream gtest rename
meta-xilinx: 64aa3d35ae..f3c8b1c9a8:
Alejandro Enedino Hernandez Samaniego (7):
opencl-clhpp: Allow empty packages to be built
opencl-headers: Allow empty packages to be built
gcc-8: rebase microblaze patches for gcc 8.2.0
gcc8: update microblaze patches
gcc: update microblaze patches
update gcc-8 patches
gcc: Remove xilinx.ld requirement
Jaewon Lee (6):
zc1254-zynqmp.conf: Add support for zc1254 evaluation board
zc1275-zynqmp.conf: Add support for zc1275 evaluation board
zcu102-zynqmp.conf: Changing qemu boot mode
Adding FPGA_MNGR_RECONFIG_ENABLE to control enabling fpga manager
gcc: Removing already upstreamed patch
Rebasing binutils patches from 2.31 to 2.32
Madhurkiran Harikrishnan (2):
kernel-module-mali: Fix errors associated with kernel upgrade to 4.19
xf86-video-armsoc: Remove the recipe for xf86-video-armsoc
Manjukumar Matha (10):
libmali-xlnx_git.bb: Fix the package arch for libmali
zcu111-zynqmp.conf: Add support for ZCU111 evaluation board
qemu-system-aarch64-multiarch: Enable plm argument in runqemu
arm-trusted-firmware.inc: Add support to build ATF for versal devices
linux-xlnx.inc: Add support to build kernel for versal devices
linux-xlnx.inc: Use KBUILD_DEFCONFIG in externalsrc mode if defined
kernel-simpleimage.bbclass: Use dts for simpleImage generation for Microblaze
kernel-simpleimage.bbclass: Deploy simpleImage unstrip file
kernel-simpleimage.bbclass: Deploy simpleImage strip
binutils%.bbappend: Update Microblaze binutils patches to v2.31
Min Ma (4):
ocl-icd_git.bb: Add recipe for OpenCL ICD loaders
opencl-clhpp_git.bb: Recipe for OpenCL Host API C++ bindings
zocl: Recipe for Xilinx runtime driver module
xrt: Xilinx Runtime User Space Libraries and headers
Sai Hari Chandana Kalluri (1):
xilinx-testimage.bbclass: Include IMAGE_AUTOLOGIN and IMAGE_FSTYPES values for runqemu
Sreeja Vadakattu (1):
machine-xilinx-default.inc: Make u-boot.elf as UBOOT_ELF for zynq
Vineeth Chowdary Karumanchi (1):
tune-zynq.inc: Build zImage in addition to uImage
meta-security: c28b72e91d..ecb526ffab:
Armin Kuster (34):
linux-bbappends: simplify
layers: set warrior only
security-test-image: add a testing image
runtime: clamav test cleanup
packagegroup-core-security: cleanup and remove ptest
test-image: add packagegroup-core-security-ptest
test-image: add a few more packages to image
ima-evm-utils: update to tip
runtime: tpm2 fix names in packagecheck
tpm2 images: create tpm2 image and fix packagegroup
tpm image: split out tpm2
tpm2-pkcs11/tpm2-pkcs11: update to tip
tpm2-tcti-uefi: update to tip
tpm2-tools: update to 3.2.0
tpm2-tss: update to 2.2.3
tpm2-totp: update to offical release v0.1.1
tpm2-tss-engine: update to 1.0.0
libmspack: update SRC_URI and package
clamav: minor recipe cleanup
lynis: update to 2.7.5
meta-security-compliance: update README
openscap_git: update to 1.3.0
openscap: add 1.3.1 recipes for upstream source
scap-security-guide: update to 0.1.44
meta-security-compliance: add meta-python
libldb: remove recipe
waf-cross-answers: remove files
samhain: update to 4.3.3
keyutils: remove from meta-security
linux-%: remove kernel fragments now in cache
meta-integrity: remove kernel fragments now in cache
linux-stable/5.2: add stable bbappend
linux-yocto: use 4.19 kernel cache now
linux-yocto-dev: update to use kernel cache
Dmitry Eremin-Solenikov (11):
packagegroup-security-tpm2: stop including tpm2-tcti-uefi
tpm2-tss: fix compilation when using updated AX_CODE_COVERAGE macro
tpm2-tcti-uefi: add autoconf-archive-native dependency
tpm2-tcti-uefi: fix configure arguments
tpm2-tcti-uefi: stop inserting host directories into build path
tpm2-tcti-uefi: build and install examples
meta-integrity: rename IMA_EVM_BASE to INTEGRITY_BASE
ima-evm-utils: bump to release 1.2.1
kernel-modsign.bbclass: add support for kernel modules signing
linux: add support for kernel modules signing
layer.conf: switch to keyutils from meta-oe
He Zhe (1):
kernel: Add conditional inclusion of fragments for linux-yocto-dev
Mark Asselstine (1):
openscap/scap-security-guide: use _git instead of versioned filenames
Yi Zhao (5):
openscap: update recipe
scap-security-guide: update recipe
openscap: cleanup DEPENDS
scap-security-guide: fix typo
xmlsec1: upgrade 1.2.27 -> 1.2.28
lumag (3):
layer.conf: add dependency on meta-security
ima-evm-utils: bump version
ima-evm-utils: refresh xattr patch
meta-raspberrypi: 8636b63752..b112816e95:
Andrei Gherzan (46):
rpi-base.inc: Include rpi4 dtb
raspberrypi3.conf: Clarify machine mode
linux-raspberrypi: Include configuration for RaspberryPi3 defconfig
linux-raspberrypi: Update 4.19 kernel to 4.19.56
rpi-base: Rename the rpi0w dtb
firmware: Update to 20190620
raspberrypi4.conf: Add initial machine 32 bit configuration
linux-firmware-rpidistro: Fix WiFi on RaspberryPi 4
rpi-base.inc: Include the "fake" KMS dtbo
raspberrypi4: Use vc4-fkms-v3d
linux-raspberrypi: Bump 4.19 revision to fix RPi 4 arm64 builds
raspberrypi4-64.conf: Introduce RPi arm64 machine
firmware: Rename firmware inc file to raspberrypi-firmware.inc
armstubs: Add support for compiling ARM stubs
rpi-config: Handle ARMSTUB
sdcard_image-rpi.bbclass: Include in the SD card image the armstub file
raspberrypi4-64.conf: Initial machine configuration
raspberrypi-tools: Update to remove Makefile patch
linux-raspberrypi: Fix defconfig for RPi4-64
linux-raspberrypi.inc: Explicitly set defconfig for raspberrypi4-64
sdcard_image-rpi.bbclass: Fix typo
linux-raspberrypi: Bump 4.19 revision to have proper coherent_pool set
raspberrypi4-64.conf: Define a machine feature for armstubs
sdcard_image-rpi.bbclass: Use armstub machine feature
linux-raspberrypi: Bump 4.19.57 revision
raspberrypi4.conf: Define uboot defconfig
raspberrypi4-64.conf: Uboot configuration and drop armstub
u-boot: Use a temporary fork for RPi4 support
raspberrypi-firmware: Update to 20190709
raspberrypi4.conf: The firmware uses kernel7l.img when LPAE is supported
linux-raspberrypi: Bump 4.19 to 4.19.58
linux-raspberrypi: Build dtbs with dtbs make target for all 64bit targets
linux-raspberrypi: Bump 4.19 revision
raspberrypi4-64.conf: Remove memory limitation
u-boot: Replace custom fork by patches
u-boot: Update patches for RPi4
rpi-config: Check for armstub based on machine feature
sdcard_image-rpi: Check for armstub based on machine feature
armstubs: Error out when ARMSTUBS is not defined
raspberrypi*: Define ARMSTUB for all machines
raspberrypi4-64.conf: Limit RAM to 3G
README.md: Use matrix chat room
raspberrypi-firmware.inc: Update to 20190718
linux-raspberrypi: Update 4.19 recipe to 4.19.66
mesa: Add v3d and kmsro driver as well
raspberrypi4-64: Remove the 3G RAM limitation
Carton (2):
bluez5: Fixed typo (RC_URI -> SRC_URI)
rpi-config: Check some config values against "1"
Francesco Giancane (1):
linux-raspberrypi: update to 4.14.114
Khem Raj (8):
linux-raspberrypi: Upgrade to 4.19.57
userland: Upgrade to latest
webkitgtk: Remove -DUSE_GSTREAMER_GL=OFF for vc4graphics
layer.conf: Add meta-networking to dynamic layers
drbd: Disable for rpi machines
packagegroup-rpi-test: Depend on wireless-regdb instead of crda
xorg-xserver: Adapt bbappend to latest OE-core
python-rtimu,python-sense-hat: Convert to py3 modules
Kirill Goncharov (1):
omxplayer: Bump revision
Martin Jansa (1):
sdcard_image-rpi.bbclass: use -v for all mcopy calls and add bbfatal in case mcopy fails
Riyaz (1):
rpi-base.inc: Enabling open-source vc4graphics driver for all RPI platforms
Change-Id: I9e37b5952a2e2e30745275fc89e4dd7c47b851e2
Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
Diffstat (limited to 'meta-xilinx')
130 files changed, 15039 insertions, 1174 deletions
diff --git a/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass index be70ffa387..348d0a733e 100644 --- a/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass +++ b/meta-xilinx/meta-xilinx-bsp/classes/kernel-simpleimage.bbclass @@ -15,8 +15,21 @@ do_prep_simpleimage () { for type in ${KERNEL_IMAGETYPES} ; do if [[ "${type}" =~ "simpleImage" ]] && [ ${ARCH} = "microblaze" ]; then ext="${type##*.}" - cp ${RECIPE_SYSROOT}/boot/devicetree/${ext}.dtb ${B}/arch/${ARCH}/boot/dts/ + # Microblaze simpleImage only works with dts file + cp ${RECIPE_SYSROOT}/boot/devicetree/${ext}.dts ${B}/arch/${ARCH}/boot/dts/ fi done } +do_deploy_append () { + for type in ${KERNEL_IMAGETYPES} ; do + if [[ "${type}" =~ "simpleImage" ]] && [ ${ARCH} = "microblaze" ]; then + base_name=${imageType}-${KERNEL_IMAGE_NAME} + install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.strip $deployDir/${base_name}.strip + install -m 0644 ${KERNEL_OUTPUT_DIR}/${type}.unstrip $deployDir/${base_name}.unstrip + symlink_name=${imageType}-${KERNEL_IMAGE_LINK_NAME} + ln -sf ${base_name}.strip $deployDir/${symlink_name}.strip + ln -sf ${base_name}.unstrip $deployDir/${symlink_name}.unstrip + fi + done +} diff --git a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass index d9086ec049..0126d8ba80 100644 --- a/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass +++ b/meta-xilinx/meta-xilinx-bsp/classes/xilinx-testimage.bbclass @@ -7,3 +7,5 @@ python do_testimage_prepend () { supported_fstypes.append('wic.qemu-sd') } +IMAGE_AUTOLOGIN = "0" +IMAGE_FSTYPES = "wic.qemu-sd" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc index 153a47fba4..3d927e76fa 100644 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/machine-xilinx-default.inc @@ -23,6 +23,7 @@ UBOOT_SUFFIX_microblaze ?= "bin" UBOOT_BINARY ?= "u-boot.${UBOOT_SUFFIX}" UBOOT_ELF ?= "u-boot" +UBOOT_ELF_zynq ?= "u-boot.elf" UBOOT_ELF_aarch64 ?= "u-boot.elf" #Hardware accelaration @@ -77,3 +78,4 @@ XSERVER_EXT_zynqmp ?= "xf86-video-armsoc" # For MicroBlaze default all microblaze machines to use GDB 7.7.1 (for gdbserver/gdb) PREFERRED_VERSION_gdb_microblaze = "7.7.1" +FPGA_MNGR_RECONFIG_ENABLE ?= "${@bb.utils.contains('IMAGE_FEATURES', 'fpga-manager', '1', '0', d)}" diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc index 270e2d937b..f7006026a1 100644 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/include/tune-zynq.inc @@ -12,6 +12,7 @@ require conf/machine/include/soc-family.inc # Linux Configuration KERNEL_IMAGETYPE ?= "uImage" +KERNEL_IMAGETYPES += "zImage" # Set default load address. # Override with KERNEL_EXTRA_ARGS_<board> += "..." in machine file if required diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf new file mode 100644 index 0000000000..51dd2a9d55 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1254-zynqmp.conf @@ -0,0 +1,38 @@ +#@TYPE: Machine +#@NAME: zc1254-zynqmp +#@DESCRIPTION: Machine support for ZC1254 Evaluation Board. +# + +SOC_VARIANT ?= "dr" + +require conf/machine/include/tune-zynqmp.inc +require conf/machine/include/machine-xilinx-overrides.inc +require conf/machine/include/machine-xilinx-default.inc + +MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" + +UBOOT_MACHINE = "xilinx_zynqmp_zc1254_revA_defconfig" +SPL_BINARY ?= "spl/boot.bin" + +SERIAL_CONSOLE ?= "115200 ttyPS0" + +SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}" + +KERNEL_DEVICETREE = "xilinx/zynqmp-zc1254-revA.dtb" + +PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx" +PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx" + +PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" +PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + arm-trusted-firmware \ + virtual/boot-bin \ + virtual/bootloader \ + " +IMAGE_BOOT_FILES += " \ + uEnv.txt \ + atf-uboot.ub \ + " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1275-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1275-zynqmp.conf new file mode 100644 index 0000000000..1e5cd0d7a0 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zc1275-zynqmp.conf @@ -0,0 +1,38 @@ +#@TYPE: Machine +#@NAME: zc1275-zynqmp +#@DESCRIPTION: Machine support for ZC1275 Evaluation Board. +# + +SOC_VARIANT ?= "dr" + +require conf/machine/include/tune-zynqmp.inc +require conf/machine/include/machine-xilinx-overrides.inc +require conf/machine/include/machine-xilinx-default.inc + +MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" + +UBOOT_MACHINE = "xilinx_zynqmp_zc1275_revB_defconfig" +SPL_BINARY ?= "spl/boot.bin" + +SERIAL_CONSOLE ?= "115200 ttyPS0" + +SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}" + +KERNEL_DEVICETREE = "xilinx/zynqmp-zc1275-revB.dtb" + +PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx" +PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx" + +PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" +PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + arm-trusted-firmware \ + virtual/boot-bin \ + virtual/bootloader \ + " +IMAGE_BOOT_FILES += " \ + uEnv.txt \ + atf-uboot.ub \ + " diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf index fba55a3ee2..281110d965 100644 --- a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu102-zynqmp.conf @@ -63,7 +63,7 @@ QB_OPT_APPEND_append_qemuboot-xilinx = " \ # Attach the rootfs disk image to the second SD interface of QEMU (which is SD0) QB_DEFAULT_FSTYPE_qemuboot-xilinx = "wic.qemu-sd" -QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=3" +QB_OPT_APPEND_append_qemuboot-xilinx = " -boot mode=5" QB_ROOTFS_OPT_qemuboot-xilinx = " -drive if=sd,index=1,file=@ROOTFS@,format=raw" # PMU instance args diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf new file mode 100644 index 0000000000..068e489036 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/zcu111-zynqmp.conf @@ -0,0 +1,38 @@ +#@TYPE: Machine +#@NAME: zcu111-zynqmp +#@DESCRIPTION: Machine support for ZCU111 Evaluation Board. +# + +SOC_VARIANT ?= "dr" + +require conf/machine/include/tune-zynqmp.inc +require conf/machine/include/machine-xilinx-overrides.inc +require conf/machine/include/machine-xilinx-default.inc + +MACHINE_FEATURES = "rtc ext2 ext3 vfat usbhost" + +UBOOT_MACHINE = "xilinx_zynqmp_zcu111_revA_defconfig" +SPL_BINARY ?= "spl/boot.bin" + +SERIAL_CONSOLE ?= "115200 ttyPS0" + +SERIAL_CONSOLES_CHECK = "${SERIAL_CONSOLES}" + +KERNEL_DEVICETREE = "xilinx/zynqmp-zcu111-revA.dtb" + +PREFERRED_PROVIDER_virtual/kernel ?= "linux-xlnx" +PREFERRED_PROVIDER_virtual/bootloader ?= "u-boot-xlnx" + +PMU_FIRMWARE_IMAGE_NAME ?= "pmu-firmware-zynqmp-pmu" +PMU_FIRMWARE_DEPLOY_DIR ?= "${TOPDIR}/pmutmp/deploy/images/zynqmp-pmu" + +EXTRA_IMAGEDEPENDS += " \ + u-boot-zynq-uenv \ + arm-trusted-firmware \ + virtual/boot-bin \ + virtual/bootloader \ + " +IMAGE_BOOT_FILES += " \ + uEnv.txt \ + atf-uboot.ub \ + " diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc index d64fad9cc6..1b4281952a 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc +++ b/meta-xilinx/meta-xilinx-bsp/recipes-bsp/arm-trusted-firmware/arm-trusted-firmware.inc @@ -25,9 +25,12 @@ SRC_URI = "${REPO};${BRANCHARG}" ATF_BASE_NAME ?= "${PN}-${PKGE}-${PKGV}-${PKGR}-${DATETIME}" ATF_BASE_NAME[vardepsexclude] = "DATETIME" -COMPATIBLE_MACHINE = "zynqmp" -PLATFORM_zynqmp = "zynqmp" +COMPATIBLE_MACHINE ?= "^$" +COMPATIBLE_MACHINE_zynqmp = ".*" +COMPATIBLE_MACHINE_versal = ".*" +PLATFORM_zynqmp = "zynqmp" +PLATFORM_versal = "versal" # requires CROSS_COMPILE set by hand as there is no configure script export CROSS_COMPILE="${TARGET_PREFIX}" @@ -40,9 +43,13 @@ LD[unexport] = "1" ATF_CONSOLE ?= "" ATF_CONSOLE_zynqmp = "cadence" +ATF_CONSOLE_versal ?= "pl011" DEBUG ?= "" +DEBUG_versal ?= "1" + EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" +EXTRA_OEMAKE_append_versal = "${@' VERSAL_CONSOLE=${ATF_CONSOLE}' if d.getVar('ATF_CONSOLE', True) != '' else ''}" EXTRA_OEMAKE_append = " ${@bb.utils.contains('DEBUG', '1', ' DEBUG=${DEBUG}', '', d)}" OUTPUT_DIR = "${@bb.utils.contains('DEBUG', '1', '${B}/${PLATFORM}/debug', '${B}/${PLATFORM}/release', d)}" @@ -53,6 +60,9 @@ ATF_MEM_SIZE ?= "" EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" EXTRA_OEMAKE_zynqmp_append = "${@' ZYNQMP_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" +EXTRA_OEMAKE_append_versal = "${@' VERSAL_ATF_MEM_BASE=${ATF_MEM_BASE}' if d.getVar('ATF_MEM_BASE', True) != '' else ''}" +EXTRA_OEMAKE_append_versal = "${@' VERSAL_ATF_MEM_SIZE=${ATF_MEM_SIZE}' if d.getVar('ATF_MEM_SIZE', True) != '' else ''}" + do_configure() { oe_runmake clean -C ${S} BUILD_BASE=${B} PLAT=${PLATFORM} } diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch index 2c92c686fb..ba0e274303 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-devtools/qemu/files/qemu-system-aarch64-multiarch @@ -13,15 +13,27 @@ mach_path = tempfile.mkdtemp() # Separate PMU and APU arguments APU_args = sys.argv[1:] -PMU_args = APU_args[APU_args.index('-pmu-args')+1] -APU_args.remove('-pmu-args') -APU_args.remove(PMU_args) -PMU_args = PMU_args.split() +mbtype='' -PMU_rom = PMU_args[PMU_args.index('-kernel')+1] -error_msg = None +if '-pmu-args' in APU_args: + MB_args = APU_args[APU_args.index('-pmu-args')+1] + APU_args.remove('-pmu-args') + APU_args.remove(MB_args) + MB_args = MB_args.split() + PMU_rom = MB_args[MB_args.index('-kernel')+1] + mbtype='PMU' +elif '-plm-args' in APU_args: + MB_args = APU_args[APU_args.index('-plm-args')+1] + APU_args.remove('-plm-args') + APU_args.remove(MB_args) + MB_args = MB_args.split() + mbtype='PLM' +else: + error_msg = '\nMultiarch not setup properly.' + sys.exit(error_msg) -if os.path.exists(PMU_rom): +error_msg = None +if (mbtype == 'PMU' and os.path.exists(PMU_rom)) or mbtype == 'PLM': # We need to switch tcp serial arguments (if they exist, e.g. qemurunner) to get the output correctly tcp_serial_ports = [i for i, s in enumerate(APU_args) if 'tcp:127.0.0.1:' in s] @@ -30,16 +42,16 @@ if os.path.exists(PMU_rom): if len(tcp_serial_ports) == 2: APU_args[tcp_serial_ports[0]],APU_args[tcp_serial_ports[1]] = APU_args[tcp_serial_ports[1]],APU_args[tcp_serial_ports[0]] - pmu_cmd = binpath + '/qemu-system-microblazeel ' + ' '.join(PMU_args) + ' -machine-path ' + mach_path + mb_cmd = binpath + '/qemu-system-microblazeel ' + ' '.join(MB_args) + ' -machine-path ' + mach_path apu_cmd = binpath + '/qemu-system-aarch64 ' + ' '.join(APU_args) + ' -machine-path ' + mach_path # Debug prints - print('\nPMU instance cmd: %s\n' % pmu_cmd) + print('\n%s instance cmd: %s\n' % (mbtype, mb_cmd)) print('APU instance cmd: %s\n' % apu_cmd) # Invoke QEMU pmu instance - process_pmu = subprocess.Popen(pmu_cmd, shell=True, stderr=subprocess.PIPE) + process_pmu = subprocess.Popen(mb_cmd, shell=True, stderr=subprocess.PIPE) # Invoke QEMU APU instance process_apu = subprocess.Popen(apu_cmd, shell=True, stderr=subprocess.PIPE) @@ -47,8 +59,9 @@ if os.path.exists(PMU_rom): error_msg = '\nQEMU APU instance failed:\n%s' % process_apu.stderr.read().decode() else: - error_msg = '\nError: Missing PMU ROM: %s' % PMU_rom - error_msg += '\nSee "meta-xilinx/README.qemu.md" for more information on accquiring the PMU ROM.\n' + if mbtype == 'PMU': + error_msg = '\nError: Missing PMU ROM: %s' % PMU_rom + error_msg += '\nSee "meta-xilinx/README.qemu.md" for more information on accquiring the PMU ROM.\n' shutil.rmtree(mach_path) sys.exit(error_msg) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb index 8c6ab3e9fd..113710e336 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/libgles/libmali-xlnx.bb @@ -37,7 +37,7 @@ COMPATIBLE_MACHINE = "^$" COMPATIBLE_MACHINE_zynqmpeg = "zynqmpeg" COMPATIBLE_MACHINE_zynqmpev = "zynqmpev" -PACKAGE_ARCH = "${SOC_FAMILY}${SOC_VARIANT}" +PACKAGE_ARCH = "${SOC_FAMILY}" S = "${WORKDIR}/mali-400" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb index 327f8f09e7..fe2fbdcf58 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali.bb @@ -21,6 +21,9 @@ SRC_URI = " \ file://0009-mali_memory_swap_alloc.c-Rename-global_page_state-wi.patch \ file://0010-common-mali_pm.c-Add-PM-runtime-barrier-after-removi.patch \ file://0011-linux-mali_kernel_linux.c-Enable-disable-clock-for-r.patch\ + file://0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch\ + file://0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch\ + file://0014-linux-mali_-timer-Get-rid-of-init_timer.patch\ " SRC_URI[md5sum] = "8f04ae86957fd56197ad5a9d017b84ff" SRC_URI[sha256sum] = "bfd14fa3f75a71d4ba313534e651ca1c58dc354e882c0b39867e335882a06350" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch new file mode 100644 index 0000000000..24f0a22c43 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0012-linux-mali_memory_os_alloc-Remove-__GFP_COLD.patch @@ -0,0 +1,33 @@ +From 779b1883d56804ecd08fe7f57d6c01e3db4e893b Mon Sep 17 00:00:00 2001 +From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Date: Wed, 5 Dec 2018 18:07:29 -0800 +Subject: [PATCH 1/3] linux: mali_memory_os_alloc: Remove __GFP_COLD + +The support for Cache hot and cold pages are removed from the kernel. +For more information refer kernel commit 453f85d43fa9ee243f0fc3ac4e1be45615301e3f + +Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> +Upstream Status: Pending +--- + driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c b/driver/src/devicedrv/mali/linux/mali_memory_os_alloc.c +index 1602371..830e8c6 100644 +--- linux/mali_memory_os_alloc.c ++++ b/linux/mali_memory_os_alloc.c +@@ -202,7 +202,9 @@ int mali_mem_os_alloc_pages(mali_mem_os_mem *os_mem, u32 size) + /* Allocate new pages, if needed. */ + for (i = 0; i < remaining; i++) { + dma_addr_t dma_addr; +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0) ++ gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN; ++#elif LINUX_VERSION_CODE == KERNEL_VERSION(4, 14, 0) + gfp_t flags = __GFP_ZERO | __GFP_RETRY_MAYFAIL | __GFP_NOWARN | __GFP_COLD; + #else + gfp_t flags = __GFP_ZERO | __GFP_REPEAT | __GFP_NOWARN | __GFP_COLD; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch new file mode 100644 index 0000000000..c28a83f478 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0013-linux-mali_memory_secure-Add-header-file-dma-direct..patch @@ -0,0 +1,34 @@ +From d20b6eb3e48e56558488dbdda98875b1aed0c29f Mon Sep 17 00:00:00 2001 +From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Date: Wed, 5 Dec 2018 18:13:28 -0800 +Subject: [PATCH 2/3] linux: mali_memory_secure: Add header file dma-direct.h + +Add dma-direct.h header, as API dma_to_phys is defined here. +refer kernel commit ea8c64ace86647260ec4255f483e5844d62af2df + +Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> +Upstream Status: Pending +--- + driver/src/devicedrv/mali/linux/mali_memory_secure.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/driver/src/devicedrv/mali/linux/mali_memory_secure.c b/driver/src/devicedrv/mali/linux/mali_memory_secure.c +index 2836b1b..4f55fa5 100644 +--- linux/mali_memory_secure.c ++++ b/linux/mali_memory_secure.c +@@ -13,7 +13,11 @@ + #include "mali_memory_secure.h" + #include "mali_osk.h" + #include <linux/mutex.h> ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0) ++#include <linux/dma-direct.h> ++#else + #include <linux/dma-mapping.h> ++#endif + #include <linux/dma-buf.h> + + _mali_osk_errcode_t mali_mem_secure_attach_dma_buf(mali_mem_secure *secure_mem, u32 size, int mem_fd) +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch new file mode 100644 index 0000000000..a7c1d5cc69 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/mali/kernel-module-mali/0014-linux-mali_-timer-Get-rid-of-init_timer.patch @@ -0,0 +1,156 @@ +From b6936450484b5aa9dd2438367a907af020341d1d Mon Sep 17 00:00:00 2001 +From: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Date: Thu, 6 Dec 2018 13:30:44 -0800 +Subject: [PATCH 3/3] linux: mali_*timer: Get rid of init_timer + +kernel 4.19 got rid of ancient init_timer. Hence, replace it with +timer_setup API. For more information refer kernel commit +7eeb6b893bd28c68b6d664de1d3120e49b855cdb + +Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> +Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> +Upstream Status: Pending +--- + driver/src/devicedrv/mali/common/mali_control_timer.c | 6 ++++++ + driver/src/devicedrv/mali/common/mali_group.c | 6 ++++++ + driver/src/devicedrv/mali/common/mali_osk.h | 15 ++++++++++++++- + driver/src/devicedrv/mali/linux/mali_osk_timers.c | 15 ++++++++++++++- + 4 files changed, 40 insertions(+), 2 deletions(-) + +diff --git a/driver/src/devicedrv/mali/common/mali_control_timer.c b/driver/src/devicedrv/mali/common/mali_control_timer.c +index 1296ffe..d24b934 100644 +--- common/mali_control_timer.c ++++ b/common/mali_control_timer.c +@@ -65,11 +65,17 @@ _mali_osk_errcode_t mali_control_timer_init(void) + } + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++ mali_control_timer = _mali_osk_timer_init(mali_control_timer_callback); ++#else + mali_control_timer = _mali_osk_timer_init(); ++#endif + if (NULL == mali_control_timer) { + return _MALI_OSK_ERR_FAULT; + } ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) + _mali_osk_timer_setcallback(mali_control_timer, mali_control_timer_callback, NULL); ++#endif + + return _MALI_OSK_ERR_OK; + } +diff --git a/driver/src/devicedrv/mali/common/mali_group.c b/driver/src/devicedrv/mali/common/mali_group.c +index 5c7b3f4..1702e9a 100644 +--- common/mali_group.c ++++ b/common/mali_group.c +@@ -65,9 +65,15 @@ struct mali_group *mali_group_create(struct mali_l2_cache_core *core, + + group = _mali_osk_calloc(1, sizeof(struct mali_group)); + if (NULL != group) { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++ group->timeout_timer = _mali_osk_timer_init(mali_group_timeout); ++#else + group->timeout_timer = _mali_osk_timer_init(); ++#endif + if (NULL != group->timeout_timer) { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) + _mali_osk_timer_setcallback(group->timeout_timer, mali_group_timeout, (void *)group); ++#endif + + group->l2_cache_core[0] = core; + _mali_osk_list_init(&group->group_list); +diff --git a/driver/src/devicedrv/mali/common/mali_osk.h b/driver/src/devicedrv/mali/common/mali_osk.h +index a501778..fe93d79 100644 +--- common/mali_osk.h ++++ b/common/mali_osk.h +@@ -947,7 +947,17 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_ + * asked for. + * + * @{ */ +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++/** @brief Initialize a timer ++ * ++ * Allocates resources for a new timer, and initializes them. This does not ++ * start the timer. ++ * ++ * @param callback Function to call when timer expires ++ * @return a pointer to the allocated timer object, or NULL on failure. ++ */ ++_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback); ++#else + /** @brief Initialize a timer + * + * Allocates resources for a new timer, and initializes them. This does not +@@ -956,6 +966,7 @@ _mali_osk_errcode_t _mali_osk_notification_queue_dequeue(_mali_osk_notification_ + * @return a pointer to the allocated timer object, or NULL on failure. + */ + _mali_osk_timer_t *_mali_osk_timer_init(void); ++#endif + + /** @brief Start a timer + * +@@ -1034,6 +1045,7 @@ void _mali_osk_timer_del_async(_mali_osk_timer_t *tim); + */ + mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim); + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) + /** @brief Set a timer's callback parameters. + * + * This must be called at least once before a timer is started/modified. +@@ -1047,6 +1059,7 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim); + * @param data Function-specific data to supply to the function on expiry. + */ + void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data); ++#endif + + /** @brief Terminate a timer, and deallocate resources. + * +diff --git a/driver/src/devicedrv/mali/linux/mali_osk_timers.c b/driver/src/devicedrv/mali/linux/mali_osk_timers.c +index e5d7238..f9b5a86 100644 +--- linux/mali_osk_timers.c ++++ b/linux/mali_osk_timers.c +@@ -21,13 +21,24 @@ + struct _mali_osk_timer_t_struct { + struct timer_list timer; + }; +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++typedef void (*timer_timeout_function_t)(struct timer_list *); ++#else + typedef void (*timer_timeout_function_t)(unsigned long); ++#endif + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++_mali_osk_timer_t *_mali_osk_timer_init(_mali_osk_timer_callback_t callback) ++#else + _mali_osk_timer_t *_mali_osk_timer_init(void) ++#endif + { + _mali_osk_timer_t *t = (_mali_osk_timer_t *)kmalloc(sizeof(_mali_osk_timer_t), GFP_KERNEL); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) ++ if (NULL != t) timer_setup(&t->timer, (timer_timeout_function_t)callback, 0); ++#else + if (NULL != t) init_timer(&t->timer); ++#endif + return t; + } + +@@ -62,12 +73,14 @@ mali_bool _mali_osk_timer_pending(_mali_osk_timer_t *tim) + return 1 == timer_pending(&(tim->timer)); + } + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0) + void _mali_osk_timer_setcallback(_mali_osk_timer_t *tim, _mali_osk_timer_callback_t callback, void *data) + { + MALI_DEBUG_ASSERT_POINTER(tim); + tim->timer.data = (unsigned long)data; + tim->timer.function = (timer_timeout_function_t)callback; + } ++#endif + + void _mali_osk_timer_term(_mali_osk_timer_t *tim) + { +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend new file mode 100644 index 0000000000..3ddcf0b819 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_%.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/xf86-video-armsoc:" + +SRC_URI_append = " file://0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb deleted file mode 100644 index 7a671fe01a..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-graphics/xorg-driver/xf86-video-armsoc_git.bb +++ /dev/null @@ -1,23 +0,0 @@ -require recipes-graphics/xorg-driver/xorg-driver-video.inc - -SUMMARY = "X.Org X server -- Xilinx ARM SOC display driver" -DESCRIPTION = "Xilinx ARM SOC display driver " - -LICENSE = "MIT-X & GPLv2+" -LIC_FILES_CHKSUM = "file://COPYING;md5=10ce5de3b111315ea652a5f74ec0c602" - -DEPENDS += "virtual/libx11 libdrm xf86driproto" -RDEPENDS_${PN} += "xserver-xorg-module-exa" - -PV = "1.4.1+git${SRCPV}" - -SRCREV = "8bbdb2ae3bb8ef649999a8da33ddbe11a04763b8" -SRC_URI = " \ - git://anongit.freedesktop.org/xorg/driver/xf86-video-armsoc \ - file://0001-src-drmmode_xilinx-Add-the-dumb-gem-support-for-Xili.patch \ - " - -S = "${WORKDIR}/git" - -EXTRA_OECONF = " --enable-maintainer-mode" -CFLAGS += " -I${STAGING_INCDIR}/xorg " diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc index ec056db4a0..5de6c9c234 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc +++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx.inc @@ -18,11 +18,19 @@ require linux-microblaze.inc DESCRIPTION = "Xilinx Kernel" +EXTKERNELSRC = "${@'1' if d.getVar('EXTERNALSRC') else ''}" + # Force the use of the KBUILD_DEFCONFIG even if some other defconfig was generated in the ${WORKDIR} do_kernel_metadata_prepend () { [ -n "${KBUILD_DEFCONFIG}" ] && [ -e ${WORKDIR}/defconfig ] && rm ${WORKDIR}/defconfig } +do_configure_prepend () { + if [ -n "${KBUILD_DEFCONFIG}" ] && [ -n "${EXTKERNELSRC}" ]; then + cp ${S}/arch/${ARCH}/configs/${KBUILD_DEFCONFIG} ${WORKDIR}/defconfig + fi +} + inherit kernel-simpleimage # Default to be only compatible with specific machines or soc families @@ -30,12 +38,14 @@ COMPATIBLE_MACHINE ?= "^$" COMPATIBLE_MACHINE_zynq = ".*" COMPATIBLE_MACHINE_zynqmp = ".*" COMPATIBLE_MACHINE_microblaze = ".*" +COMPATIBLE_MACHINE_versal = ".*" # Use DEFCONFIGs for configuring linux-xlnx kernels KCONFIG_MODE ?= "alldefconfig" KBUILD_DEFCONFIG_zynqmp = "xilinx_zynqmp_defconfig" KBUILD_DEFCONFIG_zynq = "xilinx_zynq_defconfig" KBUILD_DEFCONFIG_microblaze = "mmu_defconfig" +KBUILD_DEFCONFIG_versal = "xilinx_versal_defconfig" # Add meta-xilinx kmeta, used for MicroBlaze BSP fragments FILESEXTRAPATHS_prepend := "${THISDIR}:" @@ -46,5 +56,7 @@ KERNEL_FEATURES_append_kc705-microblazeel = " bsp/kc705-microblazeel/kc705-micro KERNEL_FEATURES_append_zynqmp = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' bsp/xilinx/xen.scc', '', d)}" -KERNEL_FEATURES_append_zynqmp = "${@bb.utils.contains('IMAGE_FEATURES', 'fpga-manager', ' features/overlay/overlay.scc', '', d)}" +KERNEL_FEATURES_append_zynqmp = "${@' features/overlay/overlay.scc' if d.getVar('FPGA_MNGR_RECONFIG_ENABLE') == '1' else ''}" + +KERNEL_FEATURES_append_versal = "${@bb.utils.contains('DISTRO_FEATURES', 'xen', ' bsp/xilinx/xen.scc', '', d)}" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend index 44709727c8..1a00c61c0e 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils%.bbappend @@ -1,15 +1,32 @@ -FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.31:" +FILESEXTRAPATHS_append_microblaze := "${THISDIR}/binutils-2.32:" SRC_URI_append_microblaze = " \ - file://0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \ - file://0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch \ - file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \ - file://0004-Fix-relaxation-of-assembler-resolved-references.patch \ - file://0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch \ - file://0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch \ - file://0007-Add-MicroBlaze-address-extension-instructions.patch \ - file://0008-Add-new-MicroBlaze-bit-field-instructions.patch \ - file://0009-Fixing-MicroBlaze-IMM-bug.patch \ - file://0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch \ - file://0011-Fixing-MicroBlaze-constant-range-check-issue.patch \ - file://0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch \ - " + file://0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \ + file://0002-Add-mlittle-endian-and-mbig-endian-flags.patch \ + file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \ + file://0004-Fix-relaxation-of-assembler-resolved-references.patch \ + file://0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch \ + file://0006-upstream-change-to-garbage-collection-sweep-causes-m.patch \ + file://0007-Fix-bug-in-TLSTPREL-Relocation.patch \ + file://0008-Added-Address-extension-instructions.patch \ + file://0009-fixing-the-MAX_OPCODES-to-correct-value.patch \ + file://0010-Add-new-bit-field-instructions.patch \ + file://0011-fixing-the-imm-bug.patch \ + file://0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch \ + file://0013-fixing-the-constant-range-check-issue.patch \ + file://0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch \ + file://0015-intial-commit-of-MB-64-bit.patch \ + file://0016-MB-X-initial-commit.patch \ + file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \ + file://0018-Added-relocations-for-MB-X.patch \ + file://0019-Fixed-MB-x-relocation-issues.patch \ + file://0020-Fixing-the-branch-related-issues.patch \ + file://0021-Fixed-address-computation-issues-with-64bit-address.patch \ + file://0022-Adding-new-relocation-to-support-64bit-rodata.patch \ + file://0023-fixing-the-.bss-relocation-issue.patch \ + file://0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \ + file://0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch \ + file://0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch \ + file://0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch \ + file://0030-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch \ + " diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0003-Disable-the-warning-message-for-eh_frame_hdr.patch deleted file mode 100644 index aee0c01ef9..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0003-Disable-the-warning-message-for-eh_frame_hdr.patch +++ /dev/null @@ -1,39 +0,0 @@ -From dac72d809be9faf9380b181df0c19a2c6d744c54 Mon Sep 17 00:00:00 2001 -From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> -Date: Mon, 28 Aug 2017 19:53:54 -0700 -Subject: [PATCH] Disable the warning message for eh_frame_hdr - -Upstream-Status: Inappropriate [workaround] - -Rebased to 2.31 - - Error hanlder changed - -Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com> -Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> - ---- - bfd/elf-eh-frame.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - -Index: git/bfd/elf-eh-frame.c -=================================================================== ---- git.orig/bfd/elf-eh-frame.c -+++ git/bfd/elf-eh-frame.c -@@ -1042,10 +1042,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, stru - goto success; - - free_no_table: -- _bfd_error_handler -+ /* FIXME: Remove the microblaze specifics when relaxing gets fixed. */ -+ if (bfd_get_arch(abfd) != bfd_arch_microblaze) { - /* xgettext:c-format */ -- (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), -- abfd, sec); -+ _bfd_error_handler -+ (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), -+ abfd, sec); -+ } - hdr_info->u.dwarf.table = FALSE; - if (sec_info) - free (sec_info); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch deleted file mode 100644 index e340c50693..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0012-MicroBlaze-fix-mask-for-barrel-shift-instructions.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 732b5a44a0a032da5ebb775b5df2ee2a36af988f Mon Sep 17 00:00:00 2001 -From: Nathan Rossi <nathan@nathanrossi.com> -Date: Sun, 5 Nov 2017 22:17:39 +1000 -Subject: [PATCH] MicroBlaze fix mask for barrel shift instructions - -As of v10.0 the bsi (bslli/bsrai/bsrli/bsefi/bsifi) instructions have -bits 16 and 17 defined as 'Insert' and 'Extract' respectively to support -bit field insert/extract operations. For the bslli/bsrai/bsrli -instructions these bits must be 0, as such update the opcode mask so -that the bslli/bsrai/bsrli instructions do not also match the bsefi and -bsifi instructions. - -Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Pending - ---- - opcodes/microblaze-opc.h | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - -diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h -index 4bc400a..9482d81 100644 ---- a/opcodes/microblaze-opc.h -+++ b/opcodes/microblaze-opc.h -@@ -161,9 +161,9 @@ struct op_code_struct - {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, - {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, - {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, -- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, -- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, -- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, -+ {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, -+ {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, -+ {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, - {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, - {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, - {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch index 878bb32136..5860848556 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0001-MicroBlaze-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch @@ -1,16 +1,14 @@ -From 91f39b692c48336117c092e4afd80899c97779e6 Mon Sep 17 00:00:00 2001 +From ad671256112cfee47871e91c6d390daea1b8fa2f Mon Sep 17 00:00:00 2001 From: David Holsgrove <david.holsgrove@xilinx.com> -Date: Mon, 28 Aug 2017 19:53:52 -0700 -Subject: [PATCH] MicroBlaze Add wdc.ext.clear and wdc.ext.flush insns +Date: Wed, 8 May 2013 11:03:36 +1000 +Subject: [PATCH] Add wdc.ext.clear and wdc.ext.flush insns Added two new instructions, wdc.ext.clear and wdc.ext.flush, to enable MicroBlaze to flush an external cache, which is used with the new coherency support for multiprocessing. -Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> --- opcodes/microblaze-opc.h | 5 ++++- @@ -18,7 +16,7 @@ Upstream-Status: Pending 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h -index ede8af8..773dc81 100644 +index 62ee3c9..865151f 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -91,6 +91,7 @@ @@ -49,7 +47,7 @@ index ede8af8..773dc81 100644 {"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst }, {"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst }, diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h -index 92f3f19..7338f6a 100644 +index 5a2d3b0..42f3dd3 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -33,8 +33,8 @@ enum microblaze_instr diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0002-Add-mlittle-endian-and-mbig-endian-flags.patch index edeecfd2f8..f0df4b8feb 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0002-MicroBlaze-add-mlittle-endian-and-mbig-endian-flags.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0002-Add-mlittle-endian-and-mbig-endian-flags.patch @@ -1,7 +1,7 @@ -From 8b733a61ab54ba4cedb234020562502d20eebcbb Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:53:53 -0700 -Subject: [PATCH] MicroBlaze add mlittle-endian and mbig-endian flags +From cd4e233a38df5eee833c77f4393e710ad5383ac0 Mon Sep 17 00:00:00 2001 +From: nagaraju <nmekala@xilix.com> +Date: Tue, 19 Mar 2013 17:18:23 +0530 +Subject: [PATCH] Add mlittle-endian and mbig-endian flags Added support in gas for mlittle-endian and mbig-endian flags as options. @@ -11,15 +11,13 @@ to include new entries. Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gas/config/tc-microblaze.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c -index 0194cd9..42dd7ae 100644 +index ab90c6b..c92e9ce 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c @@ -37,6 +37,8 @@ @@ -31,7 +29,7 @@ index 0194cd9..42dd7ae 100644 void microblaze_generate_symbol (char *sym); static bfd_boolean check_spl_reg (unsigned *); -@@ -1837,6 +1839,8 @@ struct option md_longopts[] = +@@ -1845,6 +1847,8 @@ struct option md_longopts[] = { {"EB", no_argument, NULL, OPTION_EB}, {"EL", no_argument, NULL, OPTION_EL}, @@ -40,7 +38,7 @@ index 0194cd9..42dd7ae 100644 { NULL, no_argument, NULL, 0} }; -@@ -2471,9 +2475,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) +@@ -2498,9 +2502,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) switch (c) { case OPTION_EB: @@ -52,7 +50,7 @@ index 0194cd9..42dd7ae 100644 target_big_endian = 0; break; default: -@@ -2488,6 +2494,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) +@@ -2515,6 +2521,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) /* fprintf(stream, _("\ MicroBlaze options:\n\ -noSmall Data in the comm and data sections do not go into the small data section\n")); */ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch new file mode 100644 index 0000000000..64d27d92bc --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0003-Disable-the-warning-message-for-eh_frame_hdr.patch @@ -0,0 +1,30 @@ +From a8cbf5f3e93150132f194cfa3008fe896457171f Mon Sep 17 00:00:00 2001 +From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> +Date: Fri, 22 Jun 2012 01:20:20 +0200 +Subject: [PATCH] Disable the warning message for eh_frame_hdr + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf-eh-frame.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c +index a13e81e..1824ba6 100644 +--- a/bfd/elf-eh-frame.c ++++ b/bfd/elf-eh-frame.c +@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info, + goto success; + + free_no_table: ++/* FIXME: Remove the microblaze specifics when relaxing gets fixed. */ ++if (bfd_get_arch(abfd) != bfd_arch_microblaze) { + _bfd_error_handler + /* xgettext:c-format */ + (_("error in %pB(%pA); no .eh_frame_hdr table will be created"), + abfd, sec); ++} + hdr_info->u.dwarf.table = FALSE; + if (sec_info) + free (sec_info); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0004-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0004-Fix-relaxation-of-assembler-resolved-references.patch index b543c54eea..4cae439ed0 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0004-Fix-relaxation-of-assembler-resolved-references.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0004-Fix-relaxation-of-assembler-resolved-references.patch @@ -1,27 +1,21 @@ -From 927ef228dfedf229dc915b273a308ab2c7bf9e19 Mon Sep 17 00:00:00 2001 +From 2b87c5c4ec4a7d6285c0991c202aae3cf8401d99 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> -Date: Mon, 28 Aug 2017 19:53:55 -0700 +Date: Tue, 14 Feb 2012 01:00:22 +0100 Subject: [PATCH] Fix relaxation of assembler resolved references -03/2018 -Rebased for binutils 2.30 - Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com> - -Upstream-Status: Pending +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> --- - bfd/elf32-microblaze.c | 39 +++++++++++++++++++++++++++++++++++++++ + bfd/elf32-microblaze.c | 38 ++++++++++++++++++++++++++++++++++++++ gas/config/tc-microblaze.c | 1 + - 2 files changed, 40 insertions(+) + 2 files changed, 39 insertions(+) diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c -index f1808bc..a1d810c 100644 +index e3c8027..359484d 100644 --- a/bfd/elf32-microblaze.c +++ b/bfd/elf32-microblaze.c -@@ -1887,6 +1887,45 @@ microblaze_elf_relax_section (bfd *abfd, +@@ -1973,6 +1973,44 @@ microblaze_elf_relax_section (bfd *abfd, irelscanend = irelocs + o->reloc_count; for (irelscan = irelocs; irelscan < irelscanend; irelscan++) { @@ -54,8 +48,7 @@ index f1808bc..a1d810c 100644 + elf_section_data (o)->this_hdr.contents = ocontents; + } + } -+ -+ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend + + isym->st_value, sec); + val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, @@ -68,10 +61,10 @@ index f1808bc..a1d810c 100644 { isym = isymbuf + ELF32_R_SYM (irelscan->r_info); diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c -index 42dd7ae..50dbfc7 100644 +index c92e9ce..3e72840 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c -@@ -2183,6 +2183,7 @@ md_apply_fix (fixS * fixP, +@@ -2205,6 +2205,7 @@ md_apply_fix (fixS * fixP, else fixP->fx_r_type = BFD_RELOC_NONE; fixP->fx_addsy = section_symbol (absolute_section); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch index 6cdd2cc2a4..a2954c91ea 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0005-Fixup-MicroBlaze-debug_loc-sections-after-linker-rel.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0005-LOCAL-Fixup-debug_loc-sections-after-linker-relaxati.patch @@ -1,42 +1,32 @@ -From 5bf68bc39976903929f730b6eed18686c3563c05 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:53:56 -0700 -Subject: [PATCH] Fixup MicroBlaze debug_loc sections after linker relaxation - -Fixup debug_loc sections after linker relaxation Adds a new reloctype -R_MICROBLAZE_32_NONE, used for passing reloc info from the assembler to -the linker when the linker manages to fully resolve a local symbol -reference. +From 68a91eb7ac94f0e0c6e9ebd7ad148c80cbc227df Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 6 Feb 2017 15:53:08 +0530 +Subject: [PATCH] Fixup debug_loc sections after linker relaxation Adds a new + reloctype R_MICROBLAZE_32_NONE, used for passing reloc info from the + assembler to the linker when the linker manages to fully resolve a local + symbol reference. This is a workaround for design flaws in the assembler to linker interface with regards to linker relaxation. -08/2018 -Rebased for binutils 2.31 - - Some RELOC_NUMBERs were added upstream, rebased to use 33 instead of 30 - Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Signed-off-by: Alejandro Enedino Hernandez Samaniego <alejandr@xilinx.com> - -Upstream-Status: Pending +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> --- - bfd/bfd-in2.h | 9 +++++++-- - bfd/elf32-microblaze.c | 45 ++++++++++++++++++++++++++++++++++++++------- + bfd/bfd-in2.h | 9 ++++++-- + bfd/elf32-microblaze.c | 53 ++++++++++++++++++++++++++++++++++------------ bfd/libbfd.h | 1 + bfd/reloc.c | 6 ++++++ binutils/readelf.c | 4 ++++ gas/config/tc-microblaze.c | 5 ++++- - include/elf/microblaze.h | 1 + - 7 files changed, 61 insertions(+), 10 deletions(-) + include/elf/microblaze.h | 2 ++ + 7 files changed, 64 insertions(+), 16 deletions(-) -Index: git/bfd/bfd-in2.h -=================================================================== ---- git.orig/bfd/bfd-in2.h -+++ git/bfd/bfd-in2.h -@@ -5791,10 +5791,15 @@ value relative to the read-write small d +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index e251d7e..fe6933a 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5867,10 +5867,15 @@ value relative to the read-write small data area anchor */ expressions of the form "Symbol Op Symbol" */ BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM, @@ -54,14 +44,15 @@ Index: git/bfd/bfd-in2.h /* This is a 64 bit reloc that stores the 32 bit pc relative value in two words (with an imm instruction). The relocation is -Index: git/bfd/elf32-microblaze.c -=================================================================== ---- git.orig/bfd/elf32-microblaze.c -+++ git/bfd/elf32-microblaze.c -@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_h +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 359484d..1c69c26 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -176,7 +176,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = 0x0000ffff, /* Dest Mask. */ FALSE), /* PC relative offset? */ +- /* This reloc does nothing. Used for relaxation. */ + HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ @@ -76,10 +67,11 @@ Index: git/bfd/elf32-microblaze.c + 0, /* Dest Mask. */ + FALSE), /* PC relative offset? */ + - /* This reloc does nothing. Used for relaxation. */ ++ /* This reloc does nothing. Used for relaxation. */ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ 0, /* Rightshift. */ -@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * + 3, /* Size (0 = byte, 1 = short, 2 = long). */ +@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, case BFD_RELOC_NONE: microblaze_reloc = R_MICROBLAZE_NONE; break; @@ -89,36 +81,41 @@ Index: git/bfd/elf32-microblaze.c case BFD_RELOC_MICROBLAZE_64_NONE: microblaze_reloc = R_MICROBLAZE_64_NONE; break; -@@ -1918,14 +1935,23 @@ microblaze_elf_relax_section (bfd *abfd, +@@ -1918,6 +1935,7 @@ microblaze_elf_relax_section (bfd *abfd, } break; case R_MICROBLAZE_NONE: -+ case R_MICROBLAZE_32_NONE: ++ case R_MICROBLAZE_32_NONE: { /* This was a PC-relative instruction that was completely resolved. */ - int sfix, efix; -+ unsigned int val; - bfd_vma target_address; +@@ -1926,12 +1944,18 @@ microblaze_elf_relax_section (bfd *abfd, target_address = irel->r_addend + irel->r_offset; sfix = calc_fixup (irel->r_offset, 0, sec); efix = calc_fixup (target_address, 0, sec); + -+ /* Validate the in-band val. */ -+ val = bfd_get_32 (abfd, contents + irel->r_offset); -+ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { -+ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); -+ } -+ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } irel->r_addend -= (efix - sfix); /* Should use HOWTO. */ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, -@@ -1973,12 +1999,16 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend); +- } +- break; ++ } ++ break; + case R_MICROBLAZE_64_NONE: + { + /* This was a PC-relative 64-bit instruction that was +@@ -1973,12 +1997,16 @@ microblaze_elf_relax_section (bfd *abfd, irelscanend = irelocs + o->reloc_count; for (irelscan = irelocs; irelscan < irelscanend; irelscan++) { - if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE) -+ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) { unsigned int val; @@ -131,19 +128,23 @@ Index: git/bfd/elf32-microblaze.c /* This was a PC-relative instruction that was completely resolved. */ if (ocontents == NULL) { -@@ -2003,15 +2033,16 @@ microblaze_elf_relax_section (bfd *abfd, - } - } - -- irelscan->r_addend -= calc_fixup (irelscan->r_addend +@@ -1999,18 +2027,17 @@ microblaze_elf_relax_section (bfd *abfd, + (file_ptr) 0, + o->rawsize)) + goto error_return; +- elf_section_data (o)->this_hdr.contents = ocontents; +- } +- } +- irelscan->r_addend -= calc_fixup (irelscan->r_addend - + isym->st_value, sec); ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); -+ + if (val != irelscan->r_addend) { + fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); + } + irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); -+ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, irelscan->r_addend); } @@ -153,7 +154,7 @@ Index: git/bfd/elf32-microblaze.c if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) { isym = isymbuf + ELF32_R_SYM (irelscan->r_info); -@@ -2071,7 +2102,7 @@ microblaze_elf_relax_section (bfd *abfd, +@@ -2070,7 +2097,7 @@ microblaze_elf_relax_section (bfd *abfd, elf_section_data (o)->this_hdr.contents = ocontents; } } @@ -162,11 +163,11 @@ Index: git/bfd/elf32-microblaze.c + isym->st_value, 0, sec); -Index: git/bfd/libbfd.h -=================================================================== ---- git.orig/bfd/libbfd.h -+++ git/bfd/libbfd.h -@@ -2862,6 +2862,7 @@ static const char *const bfd_reloc_code_ +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 36284d7..feb9fad 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2901,6 +2901,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_MICROBLAZE_32_ROSDA", "BFD_RELOC_MICROBLAZE_32_RWSDA", "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", @@ -174,11 +175,11 @@ Index: git/bfd/libbfd.h "BFD_RELOC_MICROBLAZE_64_NONE", "BFD_RELOC_MICROBLAZE_64_GOTPC", "BFD_RELOC_MICROBLAZE_64_GOT", -Index: git/bfd/reloc.c -=================================================================== ---- git.orig/bfd/reloc.c -+++ git/bfd/reloc.c -@@ -6865,6 +6865,12 @@ ENUMDOC +diff --git a/bfd/reloc.c b/bfd/reloc.c +index e6446a7..87753ae 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6796,6 +6796,12 @@ ENUMDOC This is a 32 bit reloc for the microblaze to handle expressions of the form "Symbol Op Symbol" ENUM @@ -191,25 +192,25 @@ Index: git/bfd/reloc.c BFD_RELOC_MICROBLAZE_64_NONE ENUMDOC This is a 64 bit reloc that stores the 32 bit pc relative -Index: git/binutils/readelf.c -=================================================================== ---- git.orig/binutils/readelf.c -+++ git/binutils/readelf.c -@@ -12908,6 +12908,10 @@ is_none_reloc (Filedata * filedata, unsi +diff --git a/binutils/readelf.c b/binutils/readelf.c +index 9df3742..1bbc2d1 100644 +--- a/binutils/readelf.c ++++ b/binutils/readelf.c +@@ -13020,6 +13020,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type) || reloc_type == 32 /* R_AVR_DIFF32. */); case EM_METAG: return reloc_type == 3; /* R_METAG_NONE. */ + case EM_MICROBLAZE: -+ return reloc_type == 33 /* R_MICROBLAZE_32_NONE. */ ++ return reloc_type == 30 /* R_MICROBLAZE_32_NONE. */ + || reloc_type == 0 /* R_MICROBLAZE_NONE. */ + || reloc_type == 9; /* R_MICROBLAZE_64_NONE. */ case EM_NDS32: return (reloc_type == 0 /* R_XTENSA_NONE. */ || reloc_type == 204 /* R_NDS32_DIFF8. */ -Index: git/gas/config/tc-microblaze.c -=================================================================== ---- git.orig/gas/config/tc-microblaze.c -+++ git/gas/config/tc-microblaze.c +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3e72840..fa665b4 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c @@ -2201,7 +2201,9 @@ md_apply_fix (fixS * fixP, /* This fixup has been resolved. Create a reloc in case the linker moves code around due to relaxing. */ @@ -221,7 +222,7 @@ Index: git/gas/config/tc-microblaze.c else fixP->fx_r_type = BFD_RELOC_NONE; fixP->fx_addsy = section_symbol (absolute_section); -@@ -2426,6 +2428,7 @@ tc_gen_reloc (asection * section ATTRIBU +@@ -2426,6 +2428,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) switch (fixp->fx_r_type) { case BFD_RELOC_NONE: @@ -229,15 +230,16 @@ Index: git/gas/config/tc-microblaze.c case BFD_RELOC_MICROBLAZE_64_NONE: case BFD_RELOC_32: case BFD_RELOC_MICROBLAZE_32_LO: -Index: git/include/elf/microblaze.h -=================================================================== ---- git.orig/include/elf/microblaze.h -+++ git/include/elf/microblaze.h -@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_relo +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index 830b5ad..6ee0966 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -61,6 +61,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30) /* PC-relative TEXT offset. */ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ + RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ END_RELOC_NUMBERS (R_MICROBLAZE_max) /* Global base address names. */ diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch new file mode 100644 index 0000000000..8c72ecf7d0 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0006-upstream-change-to-garbage-collection-sweep-causes-m.patch @@ -0,0 +1,38 @@ +From 0ee164f7e50d88e1cda4fdebd6f7bd182d0f27b3 Mon Sep 17 00:00:00 2001 +From: David Holsgrove <david.holsgrove@xilinx.com> +Date: Wed, 27 Feb 2013 13:56:11 +1000 +Subject: [PATCH] upstream change to garbage collection sweep causes mb + regression + +Upstream change for PR13177 now clears the def_regular during gc_sweep of a +section. (All other archs in binutils/bfd/elf32-*.c received an update +to a warning about unresolvable relocations - this warning is not present +in binutils/bfd/elf32-microblaze.c, but this warning check would not +prevent the error being seen) + +The visible issue with this change is when running a c++ application +in Petalinux which links libstdc++.so for exception handling it segfaults +on execution. + +This does not occur if static linking libstdc++.a, so its during the +relocations for a shared lib with garbage collection this occurs + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elflink.c | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/bfd/elflink.c b/bfd/elflink.c +index e50c0e4..09d43e3 100644 +--- a/bfd/elflink.c ++++ b/bfd/elflink.c +@@ -6187,7 +6187,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data) + + inf = (struct elf_gc_sweep_symbol_info *) data; + (*inf->hide_symbol) (inf->info, h, TRUE); +- h->def_regular = 0; + h->ref_regular = 0; + h->ref_regular_nonweak = 0; + } diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0007-Fix-bug-in-TLSTPREL-Relocation.patch index 8d3d5387be..472aa0cf80 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0006-Fix-bug-in-MicroBlaze-TLSTPREL-Relocation.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0007-Fix-bug-in-TLSTPREL-Relocation.patch @@ -1,7 +1,7 @@ -From ca0336a49c33ccb78962530f2affff8982027e8e Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:53:58 -0700 -Subject: [PATCH] Fix bug in MicroBlaze TLSTPREL Relocation +From 1367d2933de24720fa24032947f784b72b54e974 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 15 Jun 2015 16:50:30 +0530 +Subject: [PATCH] Fix bug in TLSTPREL Relocation Fixed the problem related to the fixup/relocations TLSTPREL. When the fixup is applied the addend is not added at the correct offset @@ -10,15 +10,13 @@ and it fails for Little endian. This patch allows support for both big & little-endian compilers Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- bfd/elf32-microblaze.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c -index 1dc56f7..d4e53de 100644 +index 1c69c26..d19a6dc 100644 --- a/bfd/elf32-microblaze.c +++ b/bfd/elf32-microblaze.c @@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *output_bfd, diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0007-Add-MicroBlaze-address-extension-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0008-Added-Address-extension-instructions.patch index 9672c51692..23d1793521 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0007-Add-MicroBlaze-address-extension-instructions.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0008-Added-Address-extension-instructions.patch @@ -1,38 +1,30 @@ -From 3895968b5c55321d203cadb7630a2baee8699e17 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:53:59 -0700 -Subject: [PATCH] Add MicroBlaze address extension instructions +From 57675e049d815f6fce100bd5effaea187abacf04 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 18 Jan 2016 12:28:21 +0530 +Subject: [PATCH] Added Address extension instructions This patch adds the support of new instructions which are required for supporting Address extension feature. -2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com> +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> - * microblaze-opc.h (op_code_struct): Added new instructions - * microblaze-opcm.h (microblaze_instr): Added new instructions +ChangeLog: + 2016-01-18 Nagaraju Mekala <nmekala@xilix.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze-opc.h (op_code_struct): Update + Added new instructions + *microblaze-opcm.h (microblaze_instr): Update + Added new instructions --- - opcodes/microblaze-opc.h | 13 ++++++++++++- + opcodes/microblaze-opc.h | 11 +++++++++++ opcodes/microblaze-opcm.h | 10 +++++----- - 2 files changed, 17 insertions(+), 6 deletions(-) + 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h -index 773dc81..4e69f76 100644 +index 865151f..330f104 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h -@@ -102,7 +102,7 @@ - #define DELAY_SLOT 1 - #define NO_DELAY_SLOT 0 - --#define MAX_OPCODES 291 -+#define MAX_OPCODES 299 - - struct op_code_struct - { @@ -178,8 +178,11 @@ struct op_code_struct {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst }, {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst }, @@ -80,7 +72,7 @@ index 773dc81..4e69f76 100644 {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, {"", 0, 0, 0, 0, 0, 0, 0, 0}, diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h -index 7338f6a..c75f10a 100644 +index 42f3dd3..1c39dbf 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -33,13 +33,13 @@ enum microblaze_instr diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch new file mode 100644 index 0000000000..0eaa699004 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0009-fixing-the-MAX_OPCODES-to-correct-value.patch @@ -0,0 +1,24 @@ +From 98b1a76e13ad32c979208a22e5b6b7cb260426b0 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 28 Jan 2016 14:07:34 +0530 +Subject: [PATCH] fixing the MAX_OPCODES to correct value + +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + opcodes/microblaze-opc.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 330f104..2a6b841 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -102,7 +102,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 291 ++#define MAX_OPCODES 299 + + struct op_code_struct + { diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0008-Add-new-MicroBlaze-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0010-Add-new-bit-field-instructions.patch index 0bc0117798..ea288aa159 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0008-Add-new-MicroBlaze-bit-field-instructions.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0010-Add-new-bit-field-instructions.patch @@ -1,19 +1,18 @@ -From 5c4dacaae2ba93569c1d37cda9859c57d6649dc0 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:54:01 -0700 -Subject: [PATCH] Add new MicroBlaze bit-field instructions +From 200359b776fbb19a1423ff4d0c46f5301af197c6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 18 Jul 2016 12:24:28 +0530 +Subject: [PATCH] Add new bit-field instructions -This patches adds new bsefi and bsifi instructions. BSEFI- The -instruction shall extract a bit field from a register and place it -right-adjusted in the destination register. The other bits in the -destination register shall be set to zero BSIFI- The instruction shall -insert a right-adjusted bit field from a register at another position in -the destination register. The rest of the bits in the destination -register shall be unchanged +This patches adds new bsefi and bsifi instructions. +BSEFI- The instruction shall extract a bit field from a +register and place it right-adjusted in the destination register. +The other bits in the destination register shall be set to zero +BSIFI- The instruction shall insert a right-adjusted bit field +from a register at another position in the destination register. +The rest of the bits in the destination register shall be unchanged + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++++++++++- opcodes/microblaze-dis.c | 16 +++++++++++ @@ -22,10 +21,10 @@ Upstream-Status: Pending 4 files changed, 102 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c -index e135547e62..34cb80fac2 100644 +index fa665b4..71bb888 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c -@@ -909,7 +909,7 @@ md_assemble (char * str) +@@ -917,7 +917,7 @@ md_assemble (char * str) unsigned reg2; unsigned reg3; unsigned isize; @@ -34,7 +33,7 @@ index e135547e62..34cb80fac2 100644 expressionS exp; char name[20]; -@@ -1164,7 +1164,76 @@ md_assemble (char * str) +@@ -1172,7 +1172,76 @@ md_assemble (char * str) inst |= (reg2 << RA_LOW) & RA_MASK; inst |= (immed << IMM_LOW) & IMM5_MASK; break; @@ -112,14 +111,13 @@ index e135547e62..34cb80fac2 100644 if (strcmp (op_end, "")) op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c -index 6a174b0eb9..80a47ad2fc 100644 +index f691740..f8aaf27 100644 --- a/opcodes/microblaze-dis.c +++ b/opcodes/microblaze-dis.c -@@ -73,6 +73,18 @@ get_field_imm5_mbar (long instr) - return(strdup(tmpstr)); +@@ -74,6 +74,18 @@ get_field_imm5_mbar (long instr) } -+static char * + static char * +get_field_imm5width (long instr) +{ + char tmpstr[25]; @@ -131,9 +129,10 @@ index 6a174b0eb9..80a47ad2fc 100644 + return (strdup (tmpstr)); +} + - static char * ++static char * get_field_rfsl (long instr) { + char tmpstr[25]; @@ -396,6 +408,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) /* For mbar 16 or sleep insn. */ case INST_TYPE_NONE: @@ -146,7 +145,7 @@ index 6a174b0eb9..80a47ad2fc 100644 case INST_TYPE_RD: print_func (stream, "\t%s", get_field_rd (inst)); diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h -index a64f8362da..afb34989d9 100644 +index 2a6b841..ce8ac35 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -59,6 +59,9 @@ @@ -197,7 +196,7 @@ index a64f8362da..afb34989d9 100644 #endif /* MICROBLAZE_OPC */ diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h -index 21a3dc8d76..dd6be7f65c 100644 +index 1c39dbf..2866269 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -29,7 +29,7 @@ enum microblaze_instr @@ -227,6 +226,3 @@ index 21a3dc8d76..dd6be7f65c 100644 /* FSL imm mask for get, put instructions. */ #define RFSL_MASK 0x000000F --- -2.15.0 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0009-Fixing-MicroBlaze-IMM-bug.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0011-fixing-the-imm-bug.patch index bb7e91ccbd..43d368c3b6 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0009-Fixing-MicroBlaze-IMM-bug.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0011-fixing-the-imm-bug.patch @@ -1,23 +1,20 @@ -From f649406ccaea992f3931e0d9ca9fbd6efb0c553b Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Mon, 28 Aug 2017 19:54:02 -0700 -Subject: [PATCH] Fixing MicroBlaze IMM bug - -Fixing the imm bug. with relax option imm -1 is also getting removed this is corrected now. +From cb65478b8ec240b372a9da7fe33875a59e89a1fe Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 10 Jul 2017 16:07:28 +0530 +Subject: [PATCH] fixing the imm bug. with relax option imm -1 is also getting + removed this is corrected now. Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- bfd/elf32-microblaze.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c -index a94799f..74b00d2 100644 +index d19a6dc..d001437 100644 --- a/bfd/elf32-microblaze.c +++ b/bfd/elf32-microblaze.c -@@ -1789,8 +1789,7 @@ microblaze_elf_relax_section (bfd *abfd, +@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd, else symval += irel->r_addend; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch index 077343e672..9abed968b4 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0010-Fixed-bug-in-GCC-so-that-it-will-support-.long-0U-an.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch @@ -1,19 +1,18 @@ -From e1bacaa7c1aa387f167afff74876c5acdffc39d9 Mon Sep 17 00:00:00 2001 +From 58271555959fcc3eadb1f23c8d31d793c979984b Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Wed, 15 Nov 2017 17:45:35 -0800 -Subject: [PATCH] Fixed bug in GCC so that it will support .long 0U and .long +Date: Fri, 29 Sep 2017 18:00:23 +0530 +Subject: [PATCH] fixed bug in GCC so that It will support .long 0U and .long 0u Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> --- gas/expr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gas/expr.c b/gas/expr.c -index 3e28af6..0b7cc76 100644 +index ee85bda..b502418 100644 --- a/gas/expr.c +++ b/gas/expr.c @@ -810,6 +810,15 @@ operand (expressionS *expressionP, enum expr_mode mode) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0011-Fixing-MicroBlaze-constant-range-check-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0013-fixing-the-constant-range-check-issue.patch index 244a7ade38..4aef7c9826 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.31/0011-Fixing-MicroBlaze-constant-range-check-issue.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0013-fixing-the-constant-range-check-issue.patch @@ -1,23 +1,20 @@ -From 9393a3e346d2ccbb86761117260c1dd89070a507 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Wed, 15 Nov 2017 17:45:34 -0800 -Subject: [PATCH] Fixing MicroBlaze constant range check issue - -Sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000 +From 70ba2154c2261d5a9d35a765c29acc5fdcdeea38 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 16 Oct 2017 15:44:23 +0530 +Subject: [PATCH] fixing the constant range check issue sample error: not in + range ffffffff80000000..7fffffff, not ffffffff70000000 Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gas/config/tc-microblaze.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c -index 21a5a0c..c614556 100644 +index 71bb888..16b10d0 100644 --- a/gas/config/tc-microblaze.c +++ b/gas/config/tc-microblaze.c -@@ -749,7 +749,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) +@@ -757,7 +757,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) if ((e->X_add_number >> 31) == 1) e->X_add_number |= -((addressT) (1U << 31)); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch new file mode 100644 index 0000000000..2118256942 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch @@ -0,0 +1,36 @@ +From 1b8f6099c5f85d77ef666becff1c4edd0aa724ab Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 21 Feb 2018 12:32:02 +0530 +Subject: [PATCH] Compiler will give error messages in more detail for + mxl-gp-opt flag.. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + ld/ldmain.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/ld/ldmain.c b/ld/ldmain.c +index 725512f..2ed413a 100644 +--- a/ld/ldmain.c ++++ b/ld/ldmain.c +@@ -1448,6 +1448,18 @@ reloc_overflow (struct bfd_link_info *info, + break; + case bfd_link_hash_defined: + case bfd_link_hash_defweak: ++ ++ if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) && entry->type == bfd_link_hash_defined) ++ { ++ einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: " ++ "%s against symbol `%T' defined in %A section in %B"), ++ reloc_name, entry->root.string, ++ entry->u.def.section, ++ entry->u.def.section == bfd_abs_section_ptr ++ ? info->output_bfd : entry->u.def.section->owner); ++ break; ++ } ++ + einfo (_(" relocation truncated to fit: " + "%s against symbol `%pT' defined in %pA section in %pB"), + reloc_name, entry->root.string, diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch new file mode 100644 index 0000000000..1afe8307e3 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0015-intial-commit-of-MB-64-bit.patch @@ -0,0 +1,4738 @@ +From e0a7cf883ed02a73fda5f7d3e131afc8f1ebe416 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 16:28:28 +0530 +Subject: [PATCH] intial commit of MB 64-bit + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/Makefile.am | 2 + + bfd/Makefile.in | 3 + + bfd/config.bfd | 4 + + bfd/configure | 2 + + bfd/configure.ac | 2 + + bfd/cpu-microblaze.c | 52 +- + bfd/elf64-microblaze.c | 3584 ++++++++++++++++++++++++++++++++++++ + bfd/targets.c | 6 + + gas/config/tc-microblaze.c | 274 ++- + gas/config/tc-microblaze.h | 4 +- + include/elf/common.h | 1 + + ld/Makefile.am | 8 + + ld/Makefile.in | 10 + + ld/configure.tgt | 3 + + ld/emulparams/elf64microblaze.sh | 23 + + ld/emulparams/elf64microblazeel.sh | 23 + + opcodes/microblaze-dis.c | 39 +- + opcodes/microblaze-opc.h | 162 +- + opcodes/microblaze-opcm.h | 20 +- + 19 files changed, 4181 insertions(+), 41 deletions(-) + create mode 100644 bfd/elf64-microblaze.c + create mode 100644 ld/emulparams/elf64microblaze.sh + create mode 100644 ld/emulparams/elf64microblazeel.sh + +diff --git a/bfd/Makefile.am b/bfd/Makefile.am +index a919155..c5fd250 100644 +--- a/bfd/Makefile.am ++++ b/bfd/Makefile.am +@@ -570,6 +570,7 @@ BFD64_BACKENDS = \ + elf64-riscv.lo \ + elfxx-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -603,6 +604,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +diff --git a/bfd/Makefile.in b/bfd/Makefile.in +index 896df52..fd457cb 100644 +--- a/bfd/Makefile.in ++++ b/bfd/Makefile.in +@@ -995,6 +995,7 @@ BFD64_BACKENDS = \ + elf64-riscv.lo \ + elfxx-riscv.lo \ + elf64-s390.lo \ ++ elf64-microblaze.lo \ + elf64-sparc.lo \ + elf64-tilegx.lo \ + elf64-x86-64.lo \ +@@ -1028,6 +1029,7 @@ BFD64_BACKENDS_CFILES = \ + elf64-nfp.c \ + elf64-ppc.c \ + elf64-s390.c \ ++ elf64-microblaze.c \ + elf64-sparc.c \ + elf64-tilegx.c \ + elf64-x86-64.c \ +@@ -1494,6 +1496,7 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@ +diff --git a/bfd/config.bfd b/bfd/config.bfd +index aef1448..8072c8a 100644 +--- a/bfd/config.bfd ++++ b/bfd/config.bfd +@@ -850,11 +850,15 @@ case "${targ}" in + microblazeel*-*) + targ_defvec=microblaze_elf32_le_vec + targ_selvecs=microblaze_elf32_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + microblaze*-*) + targ_defvec=microblaze_elf32_vec + targ_selvecs=microblaze_elf32_le_vec ++ targ64_selvecs=microblaze_elf64_vec ++ targ64_selvecs=microblaze_elf64_le_vec + ;; + + #ifdef BFD64 +diff --git a/bfd/configure b/bfd/configure +index e5bde48..5bf94d5 100755 +--- a/bfd/configure ++++ b/bfd/configure +@@ -15502,6 +15502,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/configure.ac b/bfd/configure.ac +index 7cdf9c8..998a651 100644 +--- a/bfd/configure.ac ++++ b/bfd/configure.ac +@@ -615,6 +615,8 @@ do + rx_elf32_linux_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;; + s390_elf32_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;; + s390_elf64_vec) tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; ++ microblaze_elf64_le_vec) tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;; + score_elf32_be_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + score_elf32_le_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;; + sh_coff_vec) tb="$tb coff-sh.lo $coff" ;; +diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c +index 9bc2eb3..c91ba46 100644 +--- a/bfd/cpu-microblaze.c ++++ b/bfd/cpu-microblaze.c +@@ -23,7 +23,24 @@ + #include "bfd.h" + #include "libbfd.h" + +-const bfd_arch_info_type bfd_microblaze_arch = ++const bfd_arch_info_type bfd_microblaze_arch[] = ++{ ++#if BFD_DEFAULT_TARGET_SIZE == 64 ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ FALSE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, + { + 32, /* 32 bits in a word. */ + 32, /* 32 bits in an address. */ +@@ -38,4 +55,37 @@ const bfd_arch_info_type bfd_microblaze_arch = + bfd_default_scan, /* String to architecture conversion. */ + bfd_arch_default_fill, /* Default fill. */ + NULL /* Next in list. */ ++} ++#else ++{ ++ 32, /* 32 bits in a word. */ ++ 32, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ TRUE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ &bfd_microblaze_arch[1] /* Next in list. */ ++}, ++{ ++ 64, /* 32 bits in a word. */ ++ 64, /* 32 bits in an address. */ ++ 8, /* 8 bits in a byte. */ ++ bfd_arch_microblaze, /* Architecture. */ ++ 0, /* Machine number - 0 for now. */ ++ "microblaze", /* Architecture name. */ ++ "MicroBlaze", /* Printable name. */ ++ 3, /* Section align power. */ ++ FALSE, /* Is this the default architecture ? */ ++ bfd_default_compatible, /* Architecture comparison function. */ ++ bfd_default_scan, /* String to architecture conversion. */ ++ bfd_arch_default_fill, /* Default fill. */ ++ NULL /* Next in list. */ ++} ++#endif + }; +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +new file mode 100644 +index 0000000..0f43ae6 +--- /dev/null ++++ b/bfd/elf64-microblaze.c +@@ -0,0 +1,3584 @@ ++/* Xilinx MicroBlaze-specific support for 32-bit ELF ++ ++ Copyright (C) 2009-2016 Free Software Foundation, Inc. ++ ++ This file is part of BFD, the Binary File Descriptor library. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the ++ Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, ++ Boston, MA 02110-1301, USA. */ ++ ++ ++int dbg1 = 0; ++ ++#include "sysdep.h" ++#include "bfd.h" ++#include "bfdlink.h" ++#include "libbfd.h" ++#include "elf-bfd.h" ++#include "elf/microblaze.h" ++#include <assert.h> ++ ++#define USE_RELA /* Only USE_REL is actually significant, but this is ++ here are a reminder... */ ++#define INST_WORD_SIZE 4 ++ ++static int ro_small_data_pointer = 0; ++static int rw_small_data_pointer = 0; ++ ++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max]; ++ ++static reloc_howto_type microblaze_elf_howto_raw[] = ++{ ++ /* This reloc does nothing. */ ++ HOWTO (R_MICROBLAZE_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 3, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_NONE", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A standard 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A standard PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_PCREL", /* Name. */ ++ TRUE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit PCREL relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_64_PCREL,/* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64_PCREL", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* The low half of a PCREL 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_PCREL_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_32_PCREL_LO", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* The low half of a 32 bit relocation. */ ++ HOWTO (R_MICROBLAZE_32_LO, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_signed, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_LO", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Read-only small data section relocation. */ ++ HOWTO (R_MICROBLAZE_SRO32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRO32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Read-write small data area relocation. */ ++ HOWTO (R_MICROBLAZE_SRW32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_SRW32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ HOWTO (R_MICROBLAZE_32_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_32_NONE",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* This reloc does nothing. Used for relaxation. */ ++ HOWTO (R_MICROBLAZE_64_NONE, /* Type. */ ++ 0, /* Rightshift. */ ++ 3, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_64_NONE",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Symbol Op Symbol relocation. */ ++ HOWTO (R_MICROBLAZE_32_SYM_OP_SYM, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 32, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_bitfield, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_32_SYM_OP_SYM", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0xffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable hierarchy. */ ++ HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ NULL, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTINHERIT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* GNU extension to record C++ vtable member usage. */ ++ HOWTO (R_MICROBLAZE_GNU_VTENTRY, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 0, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont,/* Complain on overflow. */ ++ _bfd_elf_rel_vtable_reloc_fn, /* Special Function. */ ++ "R_MICROBLAZE_GNU_VTENTRY", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOT_64",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 64 bit PLT relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_PLT_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_PLT_64",/* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_REL, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_REL", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_JUMP_SLOT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GLOB_DAT", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* A 32 bit GOT relative relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GOTOFF_32, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GOTOFF_32", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* COPY relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_COPY, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ FALSE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_COPY", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ ++ /* Marker relocs for TLS. */ ++ HOWTO (R_MICROBLAZE_TLS, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLS", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSGD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGD", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ HOWTO (R_MICROBLAZE_TLSLD, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSLD", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes the load module index of the load module that contains the ++ definition of its TLS sym. */ ++ HOWTO (R_MICROBLAZE_TLSDTPMOD32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPMOD32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. Used for initializing GOT */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a dtv-relative displacement, the difference between the value ++ of sym+add and the base address of the thread-local storage block that ++ contains the definition of sym, minus 0x8000. */ ++ HOWTO (R_MICROBLAZE_TLSDTPREL64, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSDTPREL64", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSGOTTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSGOTTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++ /* Computes a tp-relative displacement, the difference between the value of ++ sym+add and the value of the thread pointer (r13). */ ++ HOWTO (R_MICROBLAZE_TLSTPREL32, ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont, /* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_MICROBLAZE_TLSTPREL32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0x0000ffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ ++}; ++ ++#ifndef NUM_ELEM ++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) ++#endif ++ ++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done. */ ++ ++static void ++microblaze_elf_howto_init (void) ++{ ++ unsigned int i; ++ ++ for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;) ++ { ++ unsigned int type; ++ ++ type = microblaze_elf_howto_raw[i].type; ++ ++ BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table)); ++ ++ microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i]; ++ } ++} ++ ++static reloc_howto_type * ++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, ++ bfd_reloc_code_real_type code) ++{ ++ enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE; ++ ++ switch (code) ++ { ++ case BFD_RELOC_NONE: ++ microblaze_reloc = R_MICROBLAZE_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_NONE: ++ microblaze_reloc = R_MICROBLAZE_32_NONE; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_NONE: ++ microblaze_reloc = R_MICROBLAZE_64_NONE; ++ break; ++ case BFD_RELOC_32: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ /* RVA is treated the same as 32 */ ++ case BFD_RELOC_RVA: ++ microblaze_reloc = R_MICROBLAZE_32; ++ break; ++ case BFD_RELOC_32_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL; ++ break; ++ case BFD_RELOC_64_PCREL: ++ microblaze_reloc = R_MICROBLAZE_64_PCREL; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO_PCREL: ++ microblaze_reloc = R_MICROBLAZE_32_PCREL_LO; ++ break; ++ case BFD_RELOC_64: ++ microblaze_reloc = R_MICROBLAZE_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_LO: ++ microblaze_reloc = R_MICROBLAZE_32_LO; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_ROSDA: ++ microblaze_reloc = R_MICROBLAZE_SRO32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_RWSDA: ++ microblaze_reloc = R_MICROBLAZE_SRW32; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: ++ microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM; ++ break; ++ case BFD_RELOC_VTABLE_INHERIT: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT; ++ break; ++ case BFD_RELOC_VTABLE_ENTRY: ++ microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ microblaze_reloc = R_MICROBLAZE_GOTPC_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOT: ++ microblaze_reloc = R_MICROBLAZE_GOT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_PLT: ++ microblaze_reloc = R_MICROBLAZE_PLT_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_GOTOFF: ++ microblaze_reloc = R_MICROBLAZE_GOTOFF_32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGD: ++ microblaze_reloc = R_MICROBLAZE_TLSGD; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSLD: ++ microblaze_reloc = R_MICROBLAZE_TLSLD; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSDTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPREL64; ++ break; ++ case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD: ++ microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_64_TLSTPREL: ++ microblaze_reloc = R_MICROBLAZE_TLSTPREL32; ++ break; ++ case BFD_RELOC_MICROBLAZE_COPY: ++ microblaze_reloc = R_MICROBLAZE_COPY; ++ break; ++ default: ++ return (reloc_howto_type *) NULL; ++ } ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ return microblaze_elf_howto_table [(int) microblaze_reloc]; ++}; ++ ++static reloc_howto_type * ++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, ++ const char *r_name) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++) ++ if (microblaze_elf_howto_raw[i].name != NULL ++ && strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0) ++ return µblaze_elf_howto_raw[i]; ++ ++ return NULL; ++} ++ ++/* Set the howto pointer for a RCE ELF reloc. */ ++ ++static void ++microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED, ++ arelent * cache_ptr, ++ Elf_Internal_Rela * dst) ++{ ++ unsigned int r_type; ++ ++ if (!microblaze_elf_howto_table [R_MICROBLAZE_32]) ++ /* Initialize howto table if needed. */ ++ microblaze_elf_howto_init (); ++ ++ r_type = ELF64_R_TYPE (dst->r_info); ++ if (r_type >= R_MICROBLAZE_max) ++ { ++ (*_bfd_error_handler) (_("%B: unrecognised MicroBlaze reloc number: %d"), ++ abfd, r_type); ++ bfd_set_error (bfd_error_bad_value); ++ r_type = R_MICROBLAZE_NONE; ++ } ++ ++ cache_ptr->howto = microblaze_elf_howto_table [r_type]; ++} ++ ++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'. */ ++ ++static bfd_boolean ++microblaze_elf_is_local_label_name (bfd *abfd, const char *name) ++{ ++ if (name[0] == 'L' && name[1] == '.') ++ return TRUE; ++ ++ if (name[0] == '$' && name[1] == 'L') ++ return TRUE; ++ ++ /* With gcc, the labels go back to starting with '.', so we accept ++ the generic ELF local label syntax as well. */ ++ return _bfd_elf_is_local_label_name (abfd, name); ++} ++ ++/* The microblaze linker (like many others) needs to keep track of ++ the number of relocs that it decides to copy as dynamic relocs in ++ check_relocs for each symbol. This is so that it can later discard ++ them if they are found to be unnecessary. We store the information ++ in a field extending the regular ELF linker hash table. */ ++ ++struct elf64_mb_dyn_relocs ++{ ++ struct elf64_mb_dyn_relocs *next; ++ ++ /* The input section of the reloc. */ ++ asection *sec; ++ ++ /* Total number of relocs copied for the input section. */ ++ bfd_size_type count; ++ ++ /* Number of pc-relative relocs copied for the input section. */ ++ bfd_size_type pc_count; ++}; ++ ++/* ELF linker hash entry. */ ++ ++struct elf64_mb_link_hash_entry ++{ ++ struct elf_link_hash_entry elf; ++ ++ /* Track dynamic relocs copied for this symbol. */ ++ struct elf64_mb_dyn_relocs *dyn_relocs; ++ ++ /* TLS Reference Types for the symbol; Updated by check_relocs */ ++#define TLS_GD 1 /* GD reloc. */ ++#define TLS_LD 2 /* LD reloc. */ ++#define TLS_TPREL 4 /* TPREL reloc, => IE. */ ++#define TLS_DTPREL 8 /* DTPREL reloc, => LD. */ ++#define TLS_TLS 16 /* Any TLS reloc. */ ++ unsigned char tls_mask; ++ ++}; ++ ++#define IS_TLS_GD(x) (x == (TLS_TLS | TLS_GD)) ++#define IS_TLS_LD(x) (x == (TLS_TLS | TLS_LD)) ++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL)) ++#define IS_TLS_NONE(x) (x == 0) ++ ++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent)) ++ ++/* ELF linker hash table. */ ++ ++struct elf64_mb_link_hash_table ++{ ++ struct elf_link_hash_table elf; ++ ++ /* Short-cuts to get to dynamic linker sections. */ ++ asection *sgot; ++ asection *sgotplt; ++ asection *srelgot; ++ asection *splt; ++ asection *srelplt; ++ asection *sdynbss; ++ asection *srelbss; ++ ++ /* Small local sym to section mapping cache. */ ++ struct sym_cache sym_sec; ++ ++ /* TLS Local Dynamic GOT Entry */ ++ union { ++ bfd_signed_vma refcount; ++ bfd_vma offset; ++ } tlsld_got; ++}; ++ ++/* Nonzero if this section has TLS related relocations. */ ++#define has_tls_reloc sec_flg0 ++ ++/* Get the ELF linker hash table from a link_info structure. */ ++ ++#define elf64_mb_hash_table(p) \ ++ (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \ ++ == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL) ++ ++/* Create an entry in a microblaze ELF linker hash table. */ ++ ++static struct bfd_hash_entry * ++link_hash_newfunc (struct bfd_hash_entry *entry, ++ struct bfd_hash_table *table, ++ const char *string) ++{ ++ /* Allocate the structure if it has not already been allocated by a ++ subclass. */ ++ if (entry == NULL) ++ { ++ entry = bfd_hash_allocate (table, ++ sizeof (struct elf64_mb_link_hash_entry)); ++ if (entry == NULL) ++ return entry; ++ } ++ ++ /* Call the allocation method of the superclass. */ ++ entry = _bfd_elf_link_hash_newfunc (entry, table, string); ++ if (entry != NULL) ++ { ++ struct elf64_mb_link_hash_entry *eh; ++ ++ eh = (struct elf64_mb_link_hash_entry *) entry; ++ eh->dyn_relocs = NULL; ++ eh->tls_mask = 0; ++ } ++ ++ return entry; ++} ++ ++/* Create a mb ELF linker hash table. */ ++ ++static struct bfd_link_hash_table * ++microblaze_elf_link_hash_table_create (bfd *abfd) ++{ ++ struct elf64_mb_link_hash_table *ret; ++ bfd_size_type amt = sizeof (struct elf64_mb_link_hash_table); ++ ++ ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt); ++ if (ret == NULL) ++ return NULL; ++ ++ if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc, ++ sizeof (struct elf64_mb_link_hash_entry), ++ MICROBLAZE_ELF_DATA)) ++ { ++ free (ret); ++ return NULL; ++ } ++ ++ return &ret->elf.root; ++} ++ ++/* Set the values of the small data pointers. */ ++ ++static void ++microblaze_elf_final_sdp (struct bfd_link_info *info) ++{ ++ struct bfd_link_hash_entry *h; ++ ++ h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ ro_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++ ++ h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE); ++ if (h != (struct bfd_link_hash_entry *) NULL ++ && h->type == bfd_link_hash_defined) ++ rw_small_data_pointer = (h->u.def.value ++ + h->u.def.section->output_section->vma ++ + h->u.def.section->output_offset); ++} ++ ++static bfd_vma ++dtprel_base (struct bfd_link_info *info) ++{ ++ /* If tls_sec is NULL, we should have signalled an error already. */ ++ if (elf_hash_table (info)->tls_sec == NULL) ++ return 0; ++ return elf_hash_table (info)->tls_sec->vma; ++} ++ ++/* The size of the thread control block. */ ++#define TCB_SIZE 8 ++ ++/* Output a simple dynamic relocation into SRELOC. */ ++ ++static void ++microblaze_elf_output_dynamic_relocation (bfd *output_bfd, ++ asection *sreloc, ++ unsigned long reloc_index, ++ unsigned long indx, ++ int r_type, ++ bfd_vma offset, ++ bfd_vma addend) ++{ ++ ++ Elf_Internal_Rela rel; ++ ++ rel.r_info = ELF64_R_INFO (indx, r_type); ++ rel.r_offset = offset; ++ rel.r_addend = addend; ++ ++ bfd_elf64_swap_reloca_out (output_bfd, &rel, ++ (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela))); ++} ++ ++/* This code is taken from elf64-m32r.c ++ There is some attempt to make this function usable for many architectures, ++ both USE_REL and USE_RELA ['twould be nice if such a critter existed], ++ if only to serve as a learning tool. ++ ++ The RELOCATE_SECTION function is called by the new ELF backend linker ++ to handle the relocations for a section. ++ ++ The relocs are always passed as Rela structures; if the section ++ actually uses Rel structures, the r_addend field will always be ++ zero. ++ ++ This function is responsible for adjust the section contents as ++ necessary, and (if using Rela relocs and generating a ++ relocatable output file) adjusting the reloc addend as ++ necessary. ++ ++ This function does not have to worry about setting the reloc ++ address or the reloc symbol index. ++ ++ LOCAL_SYMS is a pointer to the swapped in local symbols. ++ ++ LOCAL_SECTIONS is an array giving the section in the input file ++ corresponding to the st_shndx field of each local symbol. ++ ++ The global hash table entry for the global symbols can be found ++ via elf_sym_hashes (input_bfd). ++ ++ When generating relocatable output, this function must handle ++ STB_LOCAL/STT_SECTION symbols specially. The output symbol is ++ going to be the section symbol corresponding to the output ++ section, which means that the addend must be adjusted ++ accordingly. */ ++ ++static bfd_boolean ++microblaze_elf_relocate_section (bfd *output_bfd, ++ struct bfd_link_info *info, ++ bfd *input_bfd, ++ asection *input_section, ++ bfd_byte *contents, ++ Elf_Internal_Rela *relocs, ++ Elf_Internal_Sym *local_syms, ++ asection **local_sections) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; ++ struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd); ++ Elf_Internal_Rela *rel, *relend; ++ int endian = (bfd_little_endian (output_bfd)) ? 0 : 2; ++ /* Assume success. */ ++ bfd_boolean ret = TRUE; ++ asection *sreloc; ++ bfd_vma *local_got_offsets; ++ unsigned int tls_type; ++ ++ if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1]) ++ microblaze_elf_howto_init (); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ local_got_offsets = elf_local_got_offsets (input_bfd); ++ ++ sreloc = elf_section_data (input_section)->sreloc; ++ ++ rel = relocs; ++ relend = relocs + input_section->reloc_count; ++ for (; rel < relend; rel++) ++ { ++ int r_type; ++ reloc_howto_type *howto; ++ unsigned long r_symndx; ++ bfd_vma addend = rel->r_addend; ++ bfd_vma offset = rel->r_offset; ++ struct elf_link_hash_entry *h; ++ Elf_Internal_Sym *sym; ++ asection *sec; ++ const char *sym_name; ++ bfd_reloc_status_type r = bfd_reloc_ok; ++ const char *errmsg = NULL; ++ bfd_boolean unresolved_reloc = FALSE; ++ ++ h = NULL; ++ r_type = ELF64_R_TYPE (rel->r_info); ++ tls_type = 0; ++ ++ if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max) ++ { ++ (*_bfd_error_handler) (_("%s: unknown relocation type %d"), ++ bfd_get_filename (input_bfd), (int) r_type); ++ bfd_set_error (bfd_error_bad_value); ++ ret = FALSE; ++ continue; ++ } ++ ++ howto = microblaze_elf_howto_table[r_type]; ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ ++ if (bfd_link_relocatable (info)) ++ { ++ /* This is a relocatable link. We don't have to change ++ anything, unless the reloc is against a section symbol, ++ in which case we have to adjust according to where the ++ section symbol winds up in the output section. */ ++ sec = NULL; ++ if (r_symndx >= symtab_hdr->sh_info) ++ /* External symbol. */ ++ continue; ++ ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sym_name = "<local symbol>"; ++ /* STT_SECTION: symbol is associated with a section. */ ++ if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) ++ /* Symbol isn't associated with a section. Nothing to do. */ ++ continue; ++ ++ sec = local_sections[r_symndx]; ++ addend += sec->output_offset + sym->st_value; ++#ifndef USE_REL ++ /* This can't be done for USE_REL because it doesn't mean anything ++ and elf_link_input_bfd asserts this stays zero. */ ++ /* rel->r_addend = addend; */ ++#endif ++ ++#ifndef USE_REL ++ /* Addends are stored with relocs. We're done. */ ++ continue; ++#else /* USE_REL */ ++ /* If partial_inplace, we need to store any additional addend ++ back in the section. */ ++ if (!howto->partial_inplace) ++ continue; ++ /* ??? Here is a nice place to call a special_function like handler. */ ++ r = _bfd_relocate_contents (howto, input_bfd, addend, ++ contents + offset); ++#endif /* USE_REL */ ++ } ++ else ++ { ++ bfd_vma relocation; ++ ++ /* This is a final link. */ ++ sym = NULL; ++ sec = NULL; ++ unresolved_reloc = FALSE; ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ { ++ /* Local symbol. */ ++ sym = local_syms + r_symndx; ++ sec = local_sections[r_symndx]; ++ if (sec == 0) ++ continue; ++ sym_name = "<local symbol>"; ++ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); ++ /* r_addend may have changed if the reference section was ++ a merge section. */ ++ addend = rel->r_addend; ++ } ++ else ++ { ++ /* External symbol. */ ++ bfd_boolean warned ATTRIBUTE_UNUSED; ++ bfd_boolean ignored ATTRIBUTE_UNUSED; ++ ++ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, ++ r_symndx, symtab_hdr, sym_hashes, ++ h, sec, relocation, ++ unresolved_reloc, warned, ignored); ++ sym_name = h->root.root.string; ++ } ++ ++ /* Sanity check the address. */ ++ if (offset > bfd_get_section_limit (input_bfd, input_section)) ++ { ++ r = bfd_reloc_outofrange; ++ goto check_reloc; ++ } ++ ++ switch ((int) r_type) ++ { ++ case (int) R_MICROBLAZE_SRO32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_get_section_name (sec->owner, sec); ++ ++ if (strcmp (name, ".sdata2") == 0 ++ || strcmp (name, ".sbss2") == 0) ++ { ++ if (ro_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (ro_small_data_pointer == 0) ++ { ++ ret = FALSE; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= ro_small_data_pointer; ++ /* Now it contains the offset from _SDA2_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), ++ bfd_get_filename (input_bfd), ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ bfd_get_section_name (sec->owner, sec)); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = FALSE; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_SRW32 : ++ { ++ const char *name; ++ ++ /* Only relocate if the symbol is defined. */ ++ if (sec) ++ { ++ name = bfd_get_section_name (sec->owner, sec); ++ ++ if (strcmp (name, ".sdata") == 0 ++ || strcmp (name, ".sbss") == 0) ++ { ++ if (rw_small_data_pointer == 0) ++ microblaze_elf_final_sdp (info); ++ if (rw_small_data_pointer == 0) ++ { ++ ret = FALSE; ++ r = bfd_reloc_undefined; ++ goto check_reloc; ++ } ++ ++ /* At this point `relocation' contains the object's ++ address. */ ++ relocation -= rw_small_data_pointer; ++ /* Now it contains the offset from _SDA_BASE_. */ ++ r = _bfd_final_link_relocate (howto, input_bfd, ++ input_section, ++ contents, offset, ++ relocation, addend); ++ } ++ else ++ { ++ (*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"), ++ bfd_get_filename (input_bfd), ++ sym_name, ++ microblaze_elf_howto_table[(int) r_type]->name, ++ bfd_get_section_name (sec->owner, sec)); ++ /*bfd_set_error (bfd_error_bad_value); ??? why? */ ++ ret = FALSE; ++ continue; ++ } ++ } ++ } ++ break; ++ ++ case (int) R_MICROBLAZE_32_SYM_OP_SYM: ++ break; /* Do nothing. */ ++ ++ case (int) R_MICROBLAZE_GOTPC_64: ++ relocation = htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ relocation += addend; ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ ++ case (int) R_MICROBLAZE_PLT_64: ++ { ++ bfd_vma immediate; ++ if (htab->splt != NULL && h != NULL ++ && h->plt.offset != (bfd_vma) -1) ++ { ++ relocation = (htab->splt->output_section->vma ++ + htab->splt->output_offset ++ + h->plt.offset); ++ unresolved_reloc = FALSE; ++ immediate = relocation - (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ else ++ { ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ immediate = relocation; ++ bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, immediate & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSGD: ++ tls_type = (TLS_TLS | TLS_GD); ++ goto dogot; ++ case (int) R_MICROBLAZE_TLSLD: ++ tls_type = (TLS_TLS | TLS_LD); ++ dogot: ++ case (int) R_MICROBLAZE_GOT_64: ++ { ++ bfd_vma *offp; ++ bfd_vma off, off2; ++ unsigned long indx; ++ bfd_vma static_value; ++ ++ bfd_boolean need_relocs = FALSE; ++ if (htab->sgot == NULL) ++ abort (); ++ ++ indx = 0; ++ offp = NULL; ++ ++ /* 1. Identify GOT Offset; ++ 2. Compute Static Values ++ 3. Process Module Id, Process Offset ++ 4. Fixup Relocation with GOT offset value. */ ++ ++ /* 1. Determine GOT Offset to use : TLS_LD, global, local */ ++ if (IS_TLS_LD (tls_type)) ++ offp = &htab->tlsld_got.offset; ++ else if (h != NULL) ++ { ++ if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1) ++ offp = &h->got.offset; ++ else ++ abort (); ++ } ++ else ++ { ++ if (local_got_offsets == NULL) ++ abort (); ++ offp = &local_got_offsets[r_symndx]; ++ } ++ ++ if (!offp) ++ abort (); ++ ++ off = (*offp) & ~1; ++ off2 = off; ++ ++ if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type)) ++ off2 = off + 4; ++ ++ /* Symbol index to use for relocs */ ++ if (h != NULL) ++ { ++ bfd_boolean dyn = ++ elf_hash_table (info)->dynamic_sections_created; ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, ++ bfd_link_pic (info), ++ h) ++ && (!bfd_link_pic (info) ++ || !SYMBOL_REFERENCES_LOCAL (info, h))) ++ indx = h->dynindx; ++ } ++ ++ /* Need to generate relocs ? */ ++ if ((bfd_link_pic (info) || indx != 0) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak)) ++ need_relocs = TRUE; ++ ++ /* 2. Compute/Emit Static value of r-expression */ ++ static_value = relocation + addend; ++ ++ /* 3. Process module-id and offset */ ++ if (! ((*offp) & 1) ) ++ { ++ bfd_vma got_offset; ++ ++ got_offset = (htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off); ++ ++ /* Process module-id */ ++ if (IS_TLS_LD(tls_type)) ++ { ++ if (! bfd_link_pic (info)) ++ { ++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, 0); ++ } ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ if (! need_relocs) ++ { ++ bfd_put_32 (output_bfd, 1, htab->sgot->contents + off); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, ++ htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32, ++ got_offset, indx ? 0 : static_value); ++ } ++ } ++ ++ /* Process Offset */ ++ if (htab->srelgot == NULL) ++ abort (); ++ ++ got_offset = (htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off2); ++ if (IS_TLS_LD(tls_type)) ++ { ++ /* For LD, offset should be 0 */ ++ *offp |= 1; ++ bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2); ++ } ++ else if (IS_TLS_GD(tls_type)) ++ { ++ *offp |= 1; ++ static_value -= dtprel_base(info); ++ if (need_relocs) ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32, ++ got_offset, indx ? 0 : static_value); ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->sgot->contents + off2); ++ } ++ } ++ else ++ { ++ bfd_put_32 (output_bfd, static_value, ++ htab->sgot->contents + off2); ++ ++ /* Relocs for dyn symbols generated by ++ finish_dynamic_symbols */ ++ if (bfd_link_pic (info) && h == NULL) ++ { ++ *offp |= 1; ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ htab->srelgot, htab->srelgot->reloc_count++, ++ /* symindex= */ indx, R_MICROBLAZE_REL, ++ got_offset, static_value); ++ } ++ } ++ } ++ ++ /* 4. Fixup Relocation with GOT offset value ++ Compute relative address of GOT entry for applying ++ the current relocation */ ++ relocation = htab->sgot->output_section->vma ++ + htab->sgot->output_offset ++ + off ++ - htab->sgotplt->output_section->vma ++ - htab->sgotplt->output_offset; ++ ++ /* Apply Current Relocation */ ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ ++ unresolved_reloc = FALSE; ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_64: ++ { ++ bfd_vma immediate; ++ unsigned short lo, high; ++ relocation += addend; ++ relocation -= htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ /* Write this value into correct location. */ ++ immediate = relocation; ++ lo = immediate & 0x0000ffff; ++ high = (immediate >> 16) & 0x0000ffff; ++ bfd_put_16 (input_bfd, high, contents + offset + endian); ++ bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_GOTOFF_32: ++ { ++ relocation += addend; ++ relocation -= htab->sgotplt->output_section->vma ++ + htab->sgotplt->output_offset; ++ /* Write this value into correct location. */ ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ break; ++ } ++ ++ case (int) R_MICROBLAZE_TLSDTPREL64: ++ relocation += addend; ++ relocation -= dtprel_base(info); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ break; ++ case (int) R_MICROBLAZE_64_PCREL : ++ case (int) R_MICROBLAZE_64: ++ case (int) R_MICROBLAZE_32: ++ { ++ /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols ++ from removed linkonce sections, or sections discarded by ++ a linker script. */ ++ if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ ++ if ((bfd_link_pic (info) ++ && (h == NULL ++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT ++ || h->root.type != bfd_link_hash_undefweak) ++ && (!howto->pc_relative ++ || (h != NULL ++ && h->dynindx != -1 ++ && (!info->symbolic ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && h != NULL ++ && h->dynindx != -1 ++ && !h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined))) ++ { ++ Elf_Internal_Rela outrel; ++ bfd_byte *loc; ++ bfd_boolean skip; ++ ++ /* When generating a shared object, these relocations ++ are copied into the output file to be resolved at run ++ time. */ ++ ++ BFD_ASSERT (sreloc != NULL); ++ ++ skip = FALSE; ++ ++ outrel.r_offset = ++ _bfd_elf_section_offset (output_bfd, info, input_section, ++ rel->r_offset); ++ if (outrel.r_offset == (bfd_vma) -1) ++ skip = TRUE; ++ else if (outrel.r_offset == (bfd_vma) -2) ++ skip = TRUE; ++ outrel.r_offset += (input_section->output_section->vma ++ + input_section->output_offset); ++ ++ if (skip) ++ memset (&outrel, 0, sizeof outrel); ++ /* h->dynindx may be -1 if the symbol was marked to ++ become local. */ ++ else if (h != NULL ++ && ((! info->symbolic && h->dynindx != -1) ++ || !h->def_regular)) ++ { ++ BFD_ASSERT (h->dynindx != -1); ++ outrel.r_info = ELF64_R_INFO (h->dynindx, r_type); ++ outrel.r_addend = addend; ++ } ++ else ++ { ++ if (r_type == R_MICROBLAZE_32) ++ { ++ outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); ++ outrel.r_addend = relocation + addend; ++ } ++ else ++ { ++ BFD_FAIL (); ++ (*_bfd_error_handler) ++ (_("%B: probably compiled without -fPIC?"), ++ input_bfd); ++ bfd_set_error (bfd_error_bad_value); ++ return FALSE; ++ } ++ } ++ ++ loc = sreloc->contents; ++ loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc); ++ break; ++ } ++ else ++ { ++ relocation += addend; ++ if (r_type == R_MICROBLAZE_32) ++ bfd_put_32 (input_bfd, relocation, contents + offset); ++ else ++ { ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); ++ bfd_put_16 (input_bfd, relocation & 0xffff, ++ contents + offset + endian + INST_WORD_SIZE); ++ } ++ break; ++ } ++ } ++ ++ default : ++ r = _bfd_final_link_relocate (howto, input_bfd, input_section, ++ contents, offset, ++ relocation, addend); ++ break; ++ } ++ } ++ ++ check_reloc: ++ ++ if (r != bfd_reloc_ok) ++ { ++ /* FIXME: This should be generic enough to go in a utility. */ ++ const char *name; ++ ++ if (h != NULL) ++ name = h->root.root.string; ++ else ++ { ++ name = (bfd_elf_string_from_elf_section ++ (input_bfd, symtab_hdr->sh_link, sym->st_name)); ++ if (name == NULL || *name == '\0') ++ name = bfd_section_name (input_bfd, sec); ++ } ++ ++ if (errmsg != NULL) ++ goto common_error; ++ ++ switch (r) ++ { ++ case bfd_reloc_overflow: ++ (*info->callbacks->reloc_overflow) ++ (info, (h ? &h->root : NULL), name, howto->name, ++ (bfd_vma) 0, input_bfd, input_section, offset); ++ break; ++ ++ case bfd_reloc_undefined: ++ (*info->callbacks->undefined_symbol) ++ (info, name, input_bfd, input_section, offset, TRUE); ++ break; ++ ++ case bfd_reloc_outofrange: ++ errmsg = _("internal error: out of range error"); ++ goto common_error; ++ ++ case bfd_reloc_notsupported: ++ errmsg = _("internal error: unsupported relocation error"); ++ goto common_error; ++ ++ case bfd_reloc_dangerous: ++ errmsg = _("internal error: dangerous error"); ++ goto common_error; ++ ++ default: ++ errmsg = _("internal error: unknown error"); ++ /* Fall through. */ ++ common_error: ++ (*info->callbacks->warning) (info, errmsg, name, input_bfd, ++ input_section, offset); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++/* Merge backend specific data from an object file to the output ++ object file when linking. ++ ++ Note: We only use this hook to catch endian mismatches. */ ++static bfd_boolean ++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd) ++{ ++ /* Check if we have the same endianess. */ ++ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) ++ return FALSE; ++ ++ return TRUE; ++} ++ ++ ++/* Calculate fixup value for reference. */ ++ ++static int ++calc_fixup (bfd_vma start, bfd_vma size, asection *sec) ++{ ++ bfd_vma end = start + size; ++ int i, fixup = 0; ++ ++ if (sec == NULL || sec->relax == NULL) ++ return 0; ++ ++ /* Look for addr in relax table, total fixup value. */ ++ for (i = 0; i < sec->relax_count; i++) ++ { ++ if (end <= sec->relax[i].addr) ++ break; ++ if ((end != start) && (start > sec->relax[i].addr)) ++ continue; ++ fixup += sec->relax[i].size; ++ } ++ return fixup; ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ a 32-bit instruction. */ ++static void ++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr = bfd_get_32 (abfd, bfd_addr); ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++} ++ ++/* Read-modify-write into the bfd, an immediate value into appropriate fields of ++ two consecutive 32-bit instructions. */ ++static void ++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) ++{ ++ unsigned long instr_hi; ++ unsigned long instr_lo; ++ ++ instr_hi = bfd_get_32 (abfd, bfd_addr); ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ ++ instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); ++ instr_lo &= ~0x0000ffff; ++ instr_lo |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE); ++} ++ ++static bfd_boolean ++microblaze_elf_relax_section (bfd *abfd, ++ asection *sec, ++ struct bfd_link_info *link_info, ++ bfd_boolean *again) ++{ ++ Elf_Internal_Shdr *symtab_hdr; ++ Elf_Internal_Rela *internal_relocs; ++ Elf_Internal_Rela *free_relocs = NULL; ++ Elf_Internal_Rela *irel, *irelend; ++ bfd_byte *contents = NULL; ++ bfd_byte *free_contents = NULL; ++ int rel_count; ++ unsigned int shndx; ++ int i, sym_index; ++ asection *o; ++ struct elf_link_hash_entry *sym_hash; ++ Elf_Internal_Sym *isymbuf, *isymend; ++ Elf_Internal_Sym *isym; ++ int symcount; ++ int offset; ++ bfd_vma src, dest; ++ ++ /* We only do this once per section. We may be able to delete some code ++ by running multiple passes, but it is not worth it. */ ++ *again = FALSE; ++ ++ /* Only do this for a text section. */ ++ if (bfd_link_relocatable (link_info) ++ || (sec->flags & SEC_RELOC) == 0 ++ || (sec->reloc_count == 0) ++ || (sec->flags & SEC_CODE) == 0) ++ return TRUE; ++ ++ BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0)); ++ ++ /* If this is the first time we have been called for this section, ++ initialize the cooked size. */ ++ if (sec->size == 0) ++ sec->size = sec->rawsize; ++ ++ /* Get symbols for this section. */ ++ symtab_hdr = &elf_tdata (abfd)->symtab_hdr; ++ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents; ++ symcount = symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (isymbuf == NULL) ++ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount, ++ 0, NULL, NULL, NULL); ++ BFD_ASSERT (isymbuf != NULL); ++ ++ internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory); ++ if (internal_relocs == NULL) ++ goto error_return; ++ if (! link_info->keep_memory) ++ free_relocs = internal_relocs; ++ ++ sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1) ++ * sizeof (struct relax_table)); ++ if (sec->relax == NULL) ++ goto error_return; ++ sec->relax_count = 0; ++ ++ irelend = internal_relocs + sec->reloc_count; ++ rel_count = 0; ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma symval; ++ if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL) ++ && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 )) ++ continue; /* Can't delete this reloc. */ ++ ++ /* Get the section contents. */ ++ if (contents == NULL) ++ { ++ if (elf_section_data (sec)->this_hdr.contents != NULL) ++ contents = elf_section_data (sec)->this_hdr.contents; ++ else ++ { ++ contents = (bfd_byte *) bfd_malloc (sec->size); ++ if (contents == NULL) ++ goto error_return; ++ free_contents = contents; ++ ++ if (!bfd_get_section_contents (abfd, sec, contents, ++ (file_ptr) 0, sec->size)) ++ goto error_return; ++ elf_section_data (sec)->this_hdr.contents = contents; ++ } ++ } ++ ++ /* Get the value of the symbol referred to by the reloc. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ /* A local symbol. */ ++ asection *sym_sec; ++ ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ if (isym->st_shndx == SHN_UNDEF) ++ sym_sec = bfd_und_section_ptr; ++ else if (isym->st_shndx == SHN_ABS) ++ sym_sec = bfd_abs_section_ptr; ++ else if (isym->st_shndx == SHN_COMMON) ++ sym_sec = bfd_com_section_ptr; ++ else ++ sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ ++ symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel); ++ } ++ else ++ { ++ unsigned long indx; ++ struct elf_link_hash_entry *h; ++ ++ indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info; ++ h = elf_sym_hashes (abfd)[indx]; ++ BFD_ASSERT (h != NULL); ++ ++ if (h->root.type != bfd_link_hash_defined ++ && h->root.type != bfd_link_hash_defweak) ++ /* This appears to be a reference to an undefined ++ symbol. Just ignore it--it will be caught by the ++ regular reloc processing. */ ++ continue; ++ ++ symval = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ } ++ ++ /* If this is a PC-relative reloc, subtract the instr offset from ++ the symbol value. */ ++ if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ symval = symval + irel->r_addend ++ - (irel->r_offset ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else ++ symval += irel->r_addend; ++ ++ if ((symval & 0xffff8000) == 0) ++ { ++ /* We can delete this instruction. */ ++ sec->relax[sec->relax_count].addr = irel->r_offset; ++ sec->relax[sec->relax_count].size = INST_WORD_SIZE; ++ sec->relax_count++; ++ ++ /* Rewrite relocation type. */ ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ case R_MICROBLAZE_64_PCREL: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_PCREL_LO); ++ break; ++ case R_MICROBLAZE_64: ++ irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info), ++ (int) R_MICROBLAZE_32_LO); ++ break; ++ default: ++ /* Cannot happen. */ ++ BFD_ASSERT (FALSE); ++ } ++ } ++ } /* Loop through all relocations. */ ++ ++ /* Loop through the relocs again, and see if anything needs to change. */ ++ if (sec->relax_count > 0) ++ { ++ shndx = _bfd_elf_section_from_bfd_section (abfd, sec); ++ rel_count = 0; ++ sec->relax[sec->relax_count].addr = sec->size; ++ ++ for (irel = internal_relocs; irel < irelend; irel++, rel_count++) ++ { ++ bfd_vma nraddr; ++ ++ /* Get the new reloc address. */ ++ nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec); ++ switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info)) ++ { ++ default: ++ break; ++ case R_MICROBLAZE_64_PCREL: ++ break; ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_32_LO: ++ /* If this reloc is against a symbol defined in this ++ section, we must check the addend to see it will put the value in ++ range to be adjusted, and hence must be changed. */ ++ if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info) ++ { ++ isym = isymbuf + ELF64_R_SYM (irel->r_info); ++ /* Only handle relocs against .text. */ ++ if (isym->st_shndx == shndx ++ && ELF64_ST_TYPE (isym->st_info) == STT_SECTION) ++ irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); ++ } ++ break; ++ case R_MICROBLAZE_NONE: ++ case R_MICROBLAZE_32_NONE: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; ++ case R_MICROBLAZE_64_NONE: ++ { ++ /* This was a PC-relative 64-bit instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE; ++ sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ irel->r_addend -= (efix - sfix); ++ microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset ++ + INST_WORD_SIZE, irel->r_addend); ++ } ++ break; ++ } ++ irel->r_offset = nraddr; ++ } /* Change all relocs in this section. */ ++ ++ /* Look through all other sections. */ ++ for (o = abfd->sections; o != NULL; o = o->next) ++ { ++ Elf_Internal_Rela *irelocs; ++ Elf_Internal_Rela *irelscan, *irelscanend; ++ bfd_byte *ocontents; ++ ++ if (o == sec ++ || (o->flags & SEC_RELOC) == 0 ++ || o->reloc_count == 0) ++ continue; ++ ++ /* We always cache the relocs. Perhaps, if info->keep_memory is ++ FALSE, we should free them, if we are permitted to. */ ++ ++ irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE); ++ if (irelocs == NULL) ++ goto error_return; ++ ++ ocontents = NULL; ++ irelscanend = irelocs + o->reloc_count; ++ for (irelscan = irelocs; irelscan < irelscanend; irelscan++) ++ { ++ if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE) ++ { ++ unsigned int val; ++ ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* hax: We only do the following fixup for debug location lists. */ ++ if (strcmp(".debug_loc", o->name)) ++ continue; ++ ++ /* This was a PC-relative instruction that was completely resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ val = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ if (val != irelscan->r_addend) { ++ fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend); ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec); ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ irelscan->r_addend -= calc_fixup (irelscan->r_addend ++ + isym->st_value, ++ 0, ++ sec); ++ } ++ } ++ else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO) ++ || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO)) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ ++ unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset); ++ immediate = instr & 0x0000ffff; ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, ++ irelscan->r_addend); ++ } ++ } ++ ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ offset = calc_fixup (irelscan->r_addend, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ } ++ } ++ else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL) ++ { ++ isym = isymbuf + ELF64_R_SYM (irelscan->r_info); ++ ++ /* Look at the reloc only if the value has been resolved. */ ++ if (isym->st_shndx == shndx ++ && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION)) ++ { ++ bfd_vma immediate; ++ bfd_vma target_address; ++ ++ if (ocontents == NULL) ++ { ++ if (elf_section_data (o)->this_hdr.contents != NULL) ++ ocontents = elf_section_data (o)->this_hdr.contents; ++ else ++ { ++ /* We always cache the section contents. ++ Perhaps, if info->keep_memory is FALSE, we ++ should free them, if we are permitted to. */ ++ if (o->rawsize == 0) ++ o->rawsize = o->size; ++ ocontents = (bfd_byte *) bfd_malloc (o->rawsize); ++ if (ocontents == NULL) ++ goto error_return; ++ if (!bfd_get_section_contents (abfd, o, ocontents, ++ (file_ptr) 0, ++ o->rawsize)) ++ goto error_return; ++ elf_section_data (o)->this_hdr.contents = ocontents; ++ } ++ } ++ unsigned long instr_hi = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset); ++ unsigned long instr_lo = bfd_get_32 (abfd, ocontents ++ + irelscan->r_offset ++ + INST_WORD_SIZE); ++ immediate = (instr_hi & 0x0000ffff) << 16; ++ immediate |= (instr_lo & 0x0000ffff); ++ target_address = immediate; ++ offset = calc_fixup (target_address, 0, sec); ++ immediate -= offset; ++ irelscan->r_addend -= offset; ++ microblaze_bfd_write_imm_value_64 (abfd, ocontents ++ + irelscan->r_offset, immediate); ++ } ++ } ++ } ++ } ++ ++ /* Adjust the local symbols defined in this section. */ ++ isymend = isymbuf + symtab_hdr->sh_info; ++ for (isym = isymbuf; isym < isymend; isym++) ++ { ++ if (isym->st_shndx == shndx) ++ { ++ isym->st_value -= calc_fixup (isym->st_value, 0, sec); ++ if (isym->st_size) ++ isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec); ++ } ++ } ++ ++ /* Now adjust the global symbols defined in this section. */ ++ isym = isymbuf + symtab_hdr->sh_info; ++ symcount = (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info; ++ for (sym_index = 0; sym_index < symcount; sym_index++) ++ { ++ sym_hash = elf_sym_hashes (abfd)[sym_index]; ++ if ((sym_hash->root.type == bfd_link_hash_defined ++ || sym_hash->root.type == bfd_link_hash_defweak) ++ && sym_hash->root.u.def.section == sec) ++ { ++ sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value, ++ 0, sec); ++ if (sym_hash->size) ++ sym_hash->size -= calc_fixup (sym_hash->root.u.def.value, ++ sym_hash->size, sec); ++ } ++ } ++ ++ /* Physically move the code and change the cooked size. */ ++ dest = sec->relax[0].addr; ++ for (i = 0; i < sec->relax_count; i++) ++ { ++ int len; ++ src = sec->relax[i].addr + sec->relax[i].size; ++ len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size; ++ ++ memmove (contents + dest, contents + src, len); ++ sec->size -= sec->relax[i].size; ++ dest += len; ++ } ++ ++ elf_section_data (sec)->relocs = internal_relocs; ++ free_relocs = NULL; ++ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ free_contents = NULL; ++ ++ symtab_hdr->contents = (bfd_byte *) isymbuf; ++ } ++ ++ if (free_relocs != NULL) ++ { ++ free (free_relocs); ++ free_relocs = NULL; ++ } ++ ++ if (free_contents != NULL) ++ { ++ if (!link_info->keep_memory) ++ free (free_contents); ++ else ++ /* Cache the section contents for elf_link_input_bfd. */ ++ elf_section_data (sec)->this_hdr.contents = contents; ++ free_contents = NULL; ++ } ++ ++ if (sec->relax_count == 0) ++ { ++ *again = FALSE; ++ free (sec->relax); ++ sec->relax = NULL; ++ } ++ else ++ *again = TRUE; ++ return TRUE; ++ ++ error_return: ++ if (free_relocs != NULL) ++ free (free_relocs); ++ if (free_contents != NULL) ++ free (free_contents); ++ if (sec->relax != NULL) ++ { ++ free (sec->relax); ++ sec->relax = NULL; ++ sec->relax_count = 0; ++ } ++ return FALSE; ++} ++ ++/* Return the section that should be marked against GC for a given ++ relocation. */ ++ ++static asection * ++microblaze_elf_gc_mark_hook (asection *sec, ++ struct bfd_link_info * info, ++ Elf_Internal_Rela * rel, ++ struct elf_link_hash_entry * h, ++ Elf_Internal_Sym * sym) ++{ ++ if (h != NULL) ++ switch (ELF64_R_TYPE (rel->r_info)) ++ { ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ case R_MICROBLAZE_GNU_VTENTRY: ++ return NULL; ++ } ++ ++ return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); ++} ++ ++/* Update the got entry reference counts for the section being removed. */ ++ ++static bfd_boolean ++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info * info ATTRIBUTE_UNUSED, ++ asection * sec ATTRIBUTE_UNUSED, ++ const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED) ++{ ++ return TRUE; ++} ++ ++/* PIC support. */ ++ ++#define PLT_ENTRY_SIZE 16 ++ ++#define PLT_ENTRY_WORD_0 0xb0000000 /* "imm 0". */ ++#define PLT_ENTRY_WORD_1 0xe9940000 /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT. */ ++#define PLT_ENTRY_WORD_1_NOPIC 0xe9800000 /* "lwi r12,r0,0" - non-PIC object. */ ++#define PLT_ENTRY_WORD_2 0x98186000 /* "brad r12". */ ++#define PLT_ENTRY_WORD_3 0x80000000 /* "nop". */ ++ ++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up ++ shortcuts to them in our hash table. */ ++ ++static bfd_boolean ++create_got_section (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ if (! _bfd_elf_create_got_section (dynobj, info)) ++ return FALSE; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ htab->sgot = bfd_get_linker_section (dynobj, ".got"); ++ htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt"); ++ if (!htab->sgot || !htab->sgotplt) ++ return FALSE; ++ ++ if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL) ++ htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got"); ++ if (htab->srelgot == NULL ++ || ! bfd_set_section_flags (dynobj, htab->srelgot, SEC_ALLOC ++ | SEC_LOAD ++ | SEC_HAS_CONTENTS ++ | SEC_IN_MEMORY ++ | SEC_LINKER_CREATED ++ | SEC_READONLY) ++ || ! bfd_set_section_alignment (dynobj, htab->srelgot, 2)) ++ return FALSE; ++ return TRUE; ++} ++ ++static bfd_boolean ++update_local_sym_info (bfd *abfd, ++ Elf_Internal_Shdr *symtab_hdr, ++ unsigned long r_symndx, ++ unsigned int tls_type) ++{ ++ bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd); ++ unsigned char *local_got_tls_masks; ++ ++ if (local_got_refcounts == NULL) ++ { ++ bfd_size_type size = symtab_hdr->sh_info; ++ ++ size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks)); ++ local_got_refcounts = bfd_zalloc (abfd, size); ++ if (local_got_refcounts == NULL) ++ return FALSE; ++ elf_local_got_refcounts (abfd) = local_got_refcounts; ++ } ++ ++ local_got_tls_masks = ++ (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info); ++ local_got_tls_masks[r_symndx] |= tls_type; ++ local_got_refcounts[r_symndx] += 1; ++ ++ return TRUE; ++} ++/* Look through the relocs for a section during the first phase. */ ++ ++static bfd_boolean ++microblaze_elf_check_relocs (bfd * abfd, ++ struct bfd_link_info * info, ++ asection * sec, ++ const Elf_Internal_Rela * relocs) ++{ ++ Elf_Internal_Shdr * symtab_hdr; ++ struct elf_link_hash_entry ** sym_hashes; ++ struct elf_link_hash_entry ** sym_hashes_end; ++ const Elf_Internal_Rela * rel; ++ const Elf_Internal_Rela * rel_end; ++ struct elf64_mb_link_hash_table *htab; ++ asection *sreloc = NULL; ++ ++ if (bfd_link_relocatable (info)) ++ return TRUE; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ symtab_hdr = & elf_tdata (abfd)->symtab_hdr; ++ sym_hashes = elf_sym_hashes (abfd); ++ sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym); ++ if (!elf_bad_symtab (abfd)) ++ sym_hashes_end -= symtab_hdr->sh_info; ++ ++ rel_end = relocs + sec->reloc_count; ++ ++ for (rel = relocs; rel < rel_end; rel++) ++ { ++ unsigned int r_type; ++ struct elf_link_hash_entry * h; ++ unsigned long r_symndx; ++ unsigned char tls_type = 0; ++ ++ r_symndx = ELF64_R_SYM (rel->r_info); ++ r_type = ELF64_R_TYPE (rel->r_info); ++ ++ if (r_symndx < symtab_hdr->sh_info) ++ h = NULL; ++ else ++ { ++ h = sym_hashes [r_symndx - symtab_hdr->sh_info]; ++ ++ /* PR15323, ref flags aren't set for references in the same ++ object. */ ++ h->root.non_ir_ref = 1; ++ } ++ ++ switch (r_type) ++ { ++ /* This relocation describes the C++ object vtable hierarchy. ++ Reconstruct it for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTINHERIT: ++ if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) ++ return FALSE; ++ break; ++ ++ /* This relocation describes which C++ vtable entries are actually ++ used. Record for later use during GC. */ ++ case R_MICROBLAZE_GNU_VTENTRY: ++ if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) ++ return FALSE; ++ break; ++ ++ /* This relocation requires .plt entry. */ ++ case R_MICROBLAZE_PLT_64: ++ if (h != NULL) ++ { ++ h->needs_plt = 1; ++ h->plt.refcount += 1; ++ } ++ break; ++ ++ /* This relocation requires .got entry. */ ++ case R_MICROBLAZE_TLSGD: ++ tls_type |= (TLS_TLS | TLS_GD); ++ goto dogottls; ++ case R_MICROBLAZE_TLSLD: ++ tls_type |= (TLS_TLS | TLS_LD); ++ dogottls: ++ sec->has_tls_reloc = 1; ++ case R_MICROBLAZE_GOT_64: ++ if (htab->sgot == NULL) ++ { ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ if (!create_got_section (htab->elf.dynobj, info)) ++ return FALSE; ++ } ++ if (h != NULL) ++ { ++ h->got.refcount += 1; ++ elf64_mb_hash_entry (h)->tls_mask |= tls_type; ++ } ++ else ++ { ++ if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) ) ++ return FALSE; ++ } ++ break; ++ ++ case R_MICROBLAZE_64: ++ case R_MICROBLAZE_64_PCREL: ++ case R_MICROBLAZE_32: ++ { ++ if (h != NULL && !bfd_link_pic (info)) ++ { ++ /* we may need a copy reloc. */ ++ h->non_got_ref = 1; ++ ++ /* we may also need a .plt entry. */ ++ h->plt.refcount += 1; ++ if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL) ++ h->pointer_equality_needed = 1; ++ } ++ ++ ++ /* If we are creating a shared library, and this is a reloc ++ against a global symbol, or a non PC relative reloc ++ against a local symbol, then we need to copy the reloc ++ into the shared library. However, if we are linking with ++ -Bsymbolic, we do not need to copy a reloc against a ++ global symbol which is defined in an object we are ++ including in the link (i.e., DEF_REGULAR is set). At ++ this point we have not seen all the input files, so it is ++ possible that DEF_REGULAR is not set now but will be set ++ later (it is never cleared). In case of a weak definition, ++ DEF_REGULAR may be cleared later by a strong definition in ++ a shared library. We account for that possibility below by ++ storing information in the relocs_copied field of the hash ++ table entry. A similar situation occurs when creating ++ shared libraries and symbol visibility changes render the ++ symbol local. ++ ++ If on the other hand, we are creating an executable, we ++ may need to keep relocations for symbols satisfied by a ++ dynamic library if we manage to avoid copy relocs for the ++ symbol. */ ++ ++ if ((bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && (r_type != R_MICROBLAZE_64_PCREL ++ || (h != NULL ++ && (! info->symbolic ++ || h->root.type == bfd_link_hash_defweak ++ || !h->def_regular)))) ++ || (!bfd_link_pic (info) ++ && (sec->flags & SEC_ALLOC) != 0 ++ && h != NULL ++ && (h->root.type == bfd_link_hash_defweak ++ || !h->def_regular))) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ struct elf64_mb_dyn_relocs **head; ++ ++ /* When creating a shared object, we must copy these ++ relocs into the output file. We create a reloc ++ section in dynobj and make room for the reloc. */ ++ ++ if (sreloc == NULL) ++ { ++ bfd *dynobj; ++ ++ if (htab->elf.dynobj == NULL) ++ htab->elf.dynobj = abfd; ++ dynobj = htab->elf.dynobj; ++ ++ sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj, ++ 2, abfd, 1); ++ if (sreloc == NULL) ++ return FALSE; ++ } ++ ++ /* If this is a global symbol, we count the number of ++ relocations we need for this symbol. */ ++ if (h != NULL) ++ head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs; ++ else ++ { ++ /* Track dynamic relocs needed for local syms too. ++ We really need local syms available to do this ++ easily. Oh well. */ ++ ++ asection *s; ++ Elf_Internal_Sym *isym; ++ void *vpp; ++ ++ isym = bfd_sym_from_r_symndx (&htab->sym_sec, ++ abfd, r_symndx); ++ if (isym == NULL) ++ return FALSE; ++ ++ s = bfd_section_from_elf_index (abfd, isym->st_shndx); ++ if (s == NULL) ++ return FALSE; ++ ++ vpp = &elf_section_data (s)->local_dynrel; ++ head = (struct elf64_mb_dyn_relocs **) vpp; ++ } ++ ++ p = *head; ++ if (p == NULL || p->sec != sec) ++ { ++ bfd_size_type amt = sizeof *p; ++ p = ((struct elf64_mb_dyn_relocs *) ++ bfd_alloc (htab->elf.dynobj, amt)); ++ if (p == NULL) ++ return FALSE; ++ p->next = *head; ++ *head = p; ++ p->sec = sec; ++ p->count = 0; ++ p->pc_count = 0; ++ } ++ ++ p->count += 1; ++ if (r_type == R_MICROBLAZE_64_PCREL) ++ p->pc_count += 1; ++ } ++ } ++ break; ++ } ++ } ++ ++ return TRUE; ++} ++ ++static bfd_boolean ++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (!htab->sgot && !create_got_section (dynobj, info)) ++ return FALSE; ++ ++ if (!_bfd_elf_create_dynamic_sections (dynobj, info)) ++ return FALSE; ++ ++ htab->splt = bfd_get_linker_section (dynobj, ".plt"); ++ htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt"); ++ htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss"); ++ if (!bfd_link_pic (info)) ++ htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss"); ++ ++ if (!htab->splt || !htab->srelplt || !htab->sdynbss ++ || (!bfd_link_pic (info) && !htab->srelbss)) ++ abort (); ++ ++ return TRUE; ++} ++ ++/* Copy the extra info we tack onto an elf_link_hash_entry. */ ++ ++static void ++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *dir, ++ struct elf_link_hash_entry *ind) ++{ ++ struct elf64_mb_link_hash_entry *edir, *eind; ++ ++ edir = (struct elf64_mb_link_hash_entry *) dir; ++ eind = (struct elf64_mb_link_hash_entry *) ind; ++ ++ if (eind->dyn_relocs != NULL) ++ { ++ if (edir->dyn_relocs != NULL) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (ind->root.type == bfd_link_hash_indirect) ++ abort (); ++ ++ /* Add reloc counts against the weak sym to the strong sym ++ list. Merge any entries against the same section. */ ++ for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ struct elf64_mb_dyn_relocs *q; ++ ++ for (q = edir->dyn_relocs; q != NULL; q = q->next) ++ if (q->sec == p->sec) ++ { ++ q->pc_count += p->pc_count; ++ q->count += p->count; ++ *pp = p->next; ++ break; ++ } ++ if (q == NULL) ++ pp = &p->next; ++ } ++ *pp = edir->dyn_relocs; ++ } ++ ++ edir->dyn_relocs = eind->dyn_relocs; ++ eind->dyn_relocs = NULL; ++ } ++ ++ edir->tls_mask |= eind->tls_mask; ++ ++ _bfd_elf_link_hash_copy_indirect (info, dir, ind); ++} ++ ++static bfd_boolean ++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, ++ struct elf_link_hash_entry *h) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry * eh; ++ struct elf64_mb_dyn_relocs *p; ++ asection *sdynbss, *s; ++ unsigned int power_of_two; ++ bfd *dynobj; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ /* If this is a function, put it in the procedure linkage table. We ++ will fill in the contents of the procedure linkage table later, ++ when we know the address of the .got section. */ ++ if (h->type == STT_FUNC ++ || h->needs_plt) ++ { ++ if (h->plt.refcount <= 0 ++ || SYMBOL_CALLS_LOCAL (info, h) ++ || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT ++ && h->root.type == bfd_link_hash_undefweak)) ++ { ++ /* This case can occur if we saw a PLT reloc in an input ++ file, but the symbol was never referred to by a dynamic ++ object, or if all references were garbage collected. In ++ such a case, we don't actually need to build a procedure ++ linkage table, and we can just do a PC32 reloc instead. */ ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ return TRUE; ++ } ++ else ++ /* It's possible that we incorrectly decided a .plt reloc was ++ needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in ++ check_relocs. We can't decide accurately between function and ++ non-function syms in check-relocs; Objects loaded later in ++ the link may change h->type. So fix it now. */ ++ h->plt.offset = (bfd_vma) -1; ++ ++ /* If this is a weak symbol, and there is a real definition, the ++ processor independent code will have arranged for us to see the ++ real definition first, and we can just use the same value. */ ++ if (h->u.weakdef != NULL) ++ { ++ BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined ++ || h->u.weakdef->root.type == bfd_link_hash_defweak); ++ h->root.u.def.section = h->u.weakdef->root.u.def.section; ++ h->root.u.def.value = h->u.weakdef->root.u.def.value; ++ return TRUE; ++ } ++ ++ /* This is a reference to a symbol defined by a dynamic object which ++ is not a function. */ ++ ++ /* If we are creating a shared library, we must presume that the ++ only references to the symbol are via the global offset table. ++ For such cases we need not do anything here; the relocations will ++ be handled correctly by relocate_section. */ ++ if (bfd_link_pic (info)) ++ return TRUE; ++ ++ /* If there are no references to this symbol that do not use the ++ GOT, we don't need to generate a copy reloc. */ ++ if (!h->non_got_ref) ++ return TRUE; ++ ++ /* If -z nocopyreloc was given, we won't generate them either. */ ++ if (info->nocopyreloc) ++ { ++ h->non_got_ref = 0; ++ return TRUE; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ s = p->sec->output_section; ++ if (s != NULL && (s->flags & SEC_READONLY) != 0) ++ break; ++ } ++ ++ /* If we didn't find any dynamic relocs in read-only sections, then ++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */ ++ if (p == NULL) ++ { ++ h->non_got_ref = 0; ++ return TRUE; ++ } ++ ++ /* We must allocate the symbol in our .dynbss section, which will ++ become part of the .bss section of the executable. There will be ++ an entry for this symbol in the .dynsym section. The dynamic ++ object will contain position independent code, so all references ++ from the dynamic object to this symbol will go through the global ++ offset table. The dynamic linker will use the .dynsym entry to ++ determine the address it must put in the global offset table, so ++ both the dynamic object and the regular object will refer to the ++ same memory location for the variable. */ ++ ++ /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker ++ to copy the initial value out of the dynamic object and into the ++ runtime process image. */ ++ dynobj = elf_hash_table (info)->dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ if ((h->root.u.def.section->flags & SEC_ALLOC) != 0) ++ { ++ htab->srelbss->size += sizeof (Elf64_External_Rela); ++ h->needs_copy = 1; ++ } ++ ++ /* We need to figure out the alignment required for this symbol. I ++ have no idea how ELF linkers handle this. */ ++ power_of_two = bfd_log2 (h->size); ++ if (power_of_two > 3) ++ power_of_two = 3; ++ ++ sdynbss = htab->sdynbss; ++ /* Apply the required alignment. */ ++ sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two)); ++ if (power_of_two > bfd_get_section_alignment (dynobj, sdynbss)) ++ { ++ if (! bfd_set_section_alignment (dynobj, sdynbss, power_of_two)) ++ return FALSE; ++ } ++ ++ /* Define the symbol as being at this point in the section. */ ++ h->root.u.def.section = sdynbss; ++ h->root.u.def.value = sdynbss->size; ++ ++ /* Increment the section size to make room for the symbol. */ ++ sdynbss->size += h->size; ++ return TRUE; ++} ++ ++/* Allocate space in .plt, .got and associated reloc sections for ++ dynamic relocs. */ ++ ++static bfd_boolean ++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat) ++{ ++ struct bfd_link_info *info; ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh; ++ struct elf64_mb_dyn_relocs *p; ++ ++ if (h->root.type == bfd_link_hash_indirect) ++ return TRUE; ++ ++ info = (struct bfd_link_info *) dat; ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (htab->elf.dynamic_sections_created ++ && h->plt.refcount > 0) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h)) ++ { ++ asection *s = htab->splt; ++ ++ /* The first entry in .plt is reserved. */ ++ if (s->size == 0) ++ s->size = PLT_ENTRY_SIZE; ++ ++ h->plt.offset = s->size; ++ ++ /* If this symbol is not defined in a regular file, and we are ++ not generating a shared library, then set the symbol to this ++ location in the .plt. This is required to make function ++ pointers compare as equal between the normal executable and ++ the shared library. */ ++ if (! bfd_link_pic (info) ++ && !h->def_regular) ++ { ++ h->root.u.def.section = s; ++ h->root.u.def.value = h->plt.offset; ++ } ++ ++ /* Make room for this entry. */ ++ s->size += PLT_ENTRY_SIZE; ++ ++ /* We also need to make an entry in the .got.plt section, which ++ will be placed in the .got section by the linker script. */ ++ htab->sgotplt->size += 4; ++ ++ /* We also need to make an entry in the .rel.plt section. */ ++ htab->srelplt->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ } ++ else ++ { ++ h->plt.offset = (bfd_vma) -1; ++ h->needs_plt = 0; ++ } ++ ++ eh = (struct elf64_mb_link_hash_entry *) h; ++ if (h->got.refcount > 0) ++ { ++ unsigned int need; ++ asection *s; ++ ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ need = 0; ++ if ((eh->tls_mask & TLS_TLS) != 0) ++ { ++ /* Handle TLS Symbol */ ++ if ((eh->tls_mask & TLS_LD) != 0) ++ { ++ if (!eh->elf.def_dynamic) ++ /* We'll just use htab->tlsld_got.offset. This should ++ always be the case. It's a little odd if we have ++ a local dynamic reloc against a non-local symbol. */ ++ htab->tlsld_got.refcount += 1; ++ else ++ need += 8; ++ } ++ if ((eh->tls_mask & TLS_GD) != 0) ++ need += 8; ++ } ++ else ++ { ++ /* Regular (non-TLS) symbol */ ++ need += 4; ++ } ++ if (need == 0) ++ { ++ h->got.offset = (bfd_vma) -1; ++ } ++ else ++ { ++ s = htab->sgot; ++ h->got.offset = s->size; ++ s->size += need; ++ htab->srelgot->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ h->got.offset = (bfd_vma) -1; ++ ++ if (eh->dyn_relocs == NULL) ++ return TRUE; ++ ++ /* In the shared -Bsymbolic case, discard space allocated for ++ dynamic pc-relative relocs against symbols which turn out to be ++ defined in regular objects. For the normal shared case, discard ++ space for pc-relative relocs that have become local due to symbol ++ visibility changes. */ ++ ++ if (bfd_link_pic (info)) ++ { ++ if (h->def_regular ++ && (h->forced_local ++ || info->symbolic)) ++ { ++ struct elf64_mb_dyn_relocs **pp; ++ ++ for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) ++ { ++ p->count -= p->pc_count; ++ p->pc_count = 0; ++ if (p->count == 0) ++ *pp = p->next; ++ else ++ pp = &p->next; ++ } ++ } ++ } ++ else ++ { ++ /* For the non-shared case, discard space for relocs against ++ symbols which turn out to need copy relocs or are not ++ dynamic. */ ++ ++ if (!h->non_got_ref ++ && ((h->def_dynamic ++ && !h->def_regular) ++ || (htab->elf.dynamic_sections_created ++ && (h->root.type == bfd_link_hash_undefweak ++ || h->root.type == bfd_link_hash_undefined)))) ++ { ++ /* Make sure this symbol is output as a dynamic symbol. ++ Undefined weak syms won't yet be marked as dynamic. */ ++ if (h->dynindx == -1 ++ && !h->forced_local) ++ { ++ if (! bfd_elf_link_record_dynamic_symbol (info, h)) ++ return FALSE; ++ } ++ ++ /* If that succeeded, we know we'll be keeping all the ++ relocs. */ ++ if (h->dynindx != -1) ++ goto keep; ++ } ++ ++ eh->dyn_relocs = NULL; ++ ++ keep: ; ++ } ++ ++ /* Finally, allocate space. */ ++ for (p = eh->dyn_relocs; p != NULL; p = p->next) ++ { ++ asection *sreloc = elf_section_data (p->sec)->sreloc; ++ sreloc->size += p->count * sizeof (Elf64_External_Rela); ++ } ++ ++ return TRUE; ++} ++ ++/* Set the sizes of the dynamic sections. */ ++ ++static bfd_boolean ++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, ++ struct bfd_link_info *info) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ bfd *dynobj; ++ asection *s; ++ bfd *ibfd; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ dynobj = htab->elf.dynobj; ++ BFD_ASSERT (dynobj != NULL); ++ ++ /* Set up .got offsets for local syms, and space for local dynamic ++ relocs. */ ++ for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) ++ { ++ bfd_signed_vma *local_got; ++ bfd_signed_vma *end_local_got; ++ bfd_size_type locsymcount; ++ Elf_Internal_Shdr *symtab_hdr; ++ unsigned char *lgot_masks; ++ asection *srel; ++ ++ if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) ++ continue; ++ ++ for (s = ibfd->sections; s != NULL; s = s->next) ++ { ++ struct elf64_mb_dyn_relocs *p; ++ ++ for (p = ((struct elf64_mb_dyn_relocs *) ++ elf_section_data (s)->local_dynrel); ++ p != NULL; ++ p = p->next) ++ { ++ if (!bfd_is_abs_section (p->sec) ++ && bfd_is_abs_section (p->sec->output_section)) ++ { ++ /* Input section has been discarded, either because ++ it is a copy of a linkonce section or due to ++ linker script /DISCARD/, so we'll be discarding ++ the relocs too. */ ++ } ++ else if (p->count != 0) ++ { ++ srel = elf_section_data (p->sec)->sreloc; ++ srel->size += p->count * sizeof (Elf64_External_Rela); ++ if ((p->sec->output_section->flags & SEC_READONLY) != 0) ++ info->flags |= DF_TEXTREL; ++ } ++ } ++ } ++ ++ local_got = elf_local_got_refcounts (ibfd); ++ if (!local_got) ++ continue; ++ ++ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; ++ locsymcount = symtab_hdr->sh_info; ++ end_local_got = local_got + locsymcount; ++ lgot_masks = (unsigned char *) end_local_got; ++ s = htab->sgot; ++ srel = htab->srelgot; ++ ++ for (; local_got < end_local_got; ++local_got, ++lgot_masks) ++ { ++ if (*local_got > 0) ++ { ++ unsigned int need = 0; ++ if ((*lgot_masks & TLS_TLS) != 0) ++ { ++ if ((*lgot_masks & TLS_GD) != 0) ++ need += 8; ++ if ((*lgot_masks & TLS_LD) != 0) ++ htab->tlsld_got.refcount += 1; ++ } ++ else ++ need += 4; ++ ++ if (need == 0) ++ { ++ *local_got = (bfd_vma) -1; ++ } ++ else ++ { ++ *local_got = s->size; ++ s->size += need; ++ if (bfd_link_pic (info)) ++ srel->size += need * (sizeof (Elf64_External_Rela) / 4); ++ } ++ } ++ else ++ *local_got = (bfd_vma) -1; ++ } ++ } ++ ++ /* Allocate global sym .plt and .got entries, and space for global ++ sym dynamic relocs. */ ++ elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info); ++ ++ if (htab->tlsld_got.refcount > 0) ++ { ++ htab->tlsld_got.offset = htab->sgot->size; ++ htab->sgot->size += 8; ++ if (bfd_link_pic (info)) ++ htab->srelgot->size += sizeof (Elf64_External_Rela); ++ } ++ else ++ htab->tlsld_got.offset = (bfd_vma) -1; ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Make space for the trailing nop in .plt. */ ++ if (htab->splt->size > 0) ++ htab->splt->size += 4; ++ } ++ ++ /* The check_relocs and adjust_dynamic_symbol entry points have ++ determined the sizes of the various dynamic sections. Allocate ++ memory for them. */ ++ for (s = dynobj->sections; s != NULL; s = s->next) ++ { ++ const char *name; ++ bfd_boolean strip = FALSE; ++ ++ if ((s->flags & SEC_LINKER_CREATED) == 0) ++ continue; ++ ++ /* It's OK to base decisions on the section name, because none ++ of the dynobj section names depend upon the input files. */ ++ name = bfd_get_section_name (dynobj, s); ++ ++ if (strncmp (name, ".rela", 5) == 0) ++ { ++ if (s->size == 0) ++ { ++ /* If we don't need this section, strip it from the ++ output file. This is to handle .rela.bss and ++ .rela.plt. We must create it in ++ create_dynamic_sections, because it must be created ++ before the linker maps input sections to output ++ sections. The linker does that before ++ adjust_dynamic_symbol is called, and it is that ++ function which decides whether anything needs to go ++ into these sections. */ ++ strip = TRUE; ++ } ++ else ++ { ++ /* We use the reloc_count field as a counter if we need ++ to copy relocs into the output file. */ ++ s->reloc_count = 0; ++ } ++ } ++ else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt) ++ { ++ /* It's not one of our sections, so don't allocate space. */ ++ continue; ++ } ++ ++ if (strip) ++ { ++ s->flags |= SEC_EXCLUDE; ++ continue; ++ } ++ ++ /* Allocate memory for the section contents. */ ++ /* FIXME: This should be a call to bfd_alloc not bfd_zalloc. ++ Unused entries should be reclaimed before the section's contents ++ are written out, but at the moment this does not happen. Thus in ++ order to prevent writing out garbage, we initialise the section's ++ contents to zero. */ ++ s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); ++ if (s->contents == NULL && s->size != 0) ++ return FALSE; ++ } ++ ++ if (elf_hash_table (info)->dynamic_sections_created) ++ { ++ /* Add some entries to the .dynamic section. We fill in the ++ values later, in microblaze_elf_finish_dynamic_sections, but we ++ must add the entries now so that we get the correct size for ++ the .dynamic section. The DT_DEBUG entry is filled in by the ++ dynamic linker and used by the debugger. */ ++#define add_dynamic_entry(TAG, VAL) \ ++ _bfd_elf_add_dynamic_entry (info, TAG, VAL) ++ ++ if (bfd_link_executable (info)) ++ { ++ if (!add_dynamic_entry (DT_DEBUG, 0)) ++ return FALSE; ++ } ++ ++ if (!add_dynamic_entry (DT_RELA, 0) ++ || !add_dynamic_entry (DT_RELASZ, 0) ++ || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela))) ++ return FALSE; ++ ++ if (htab->splt->size != 0) ++ { ++ if (!add_dynamic_entry (DT_PLTGOT, 0) ++ || !add_dynamic_entry (DT_PLTRELSZ, 0) ++ || !add_dynamic_entry (DT_PLTREL, DT_RELA) ++ || !add_dynamic_entry (DT_JMPREL, 0) ++ || !add_dynamic_entry (DT_BIND_NOW, 1)) ++ return FALSE; ++ } ++ ++ if (info->flags & DF_TEXTREL) ++ { ++ if (!add_dynamic_entry (DT_TEXTREL, 0)) ++ return FALSE; ++ } ++ } ++#undef add_dynamic_entry ++ return TRUE; ++} ++ ++/* Finish up dynamic symbol handling. We set the contents of various ++ dynamic sections here. */ ++ ++static bfd_boolean ++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd, ++ struct bfd_link_info *info, ++ struct elf_link_hash_entry *h, ++ Elf_Internal_Sym *sym) ++{ ++ struct elf64_mb_link_hash_table *htab; ++ struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h); ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ if (h->plt.offset != (bfd_vma) -1) ++ { ++ asection *splt; ++ asection *srela; ++ asection *sgotplt; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ bfd_vma plt_index; ++ bfd_vma got_offset; ++ bfd_vma got_addr; ++ ++ /* This symbol has an entry in the procedure linkage table. Set ++ it up. */ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ splt = htab->splt; ++ srela = htab->srelplt; ++ sgotplt = htab->sgotplt; ++ BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL); ++ ++ plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved. */ ++ got_offset = (plt_index + 3) * 4; /* 3 reserved ??? */ ++ got_addr = got_offset; ++ ++ /* For non-PIC objects we need absolute address of the GOT entry. */ ++ if (!bfd_link_pic (info)) ++ got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset; ++ ++ /* Fill in the entry in the procedure linkage table. */ ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff), ++ splt->contents + h->plt.offset); ++ if (bfd_link_pic (info)) ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ else ++ bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff), ++ splt->contents + h->plt.offset + 4); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2, ++ splt->contents + h->plt.offset + 8); ++ bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3, ++ splt->contents + h->plt.offset + 12); ++ ++ /* Any additions to the .got section??? */ ++ /* bfd_put_32 (output_bfd, ++ splt->output_section->vma + splt->output_offset + h->plt.offset + 4, ++ sgotplt->contents + got_offset); */ ++ ++ /* Fill in the entry in the .rela.plt section. */ ++ rela.r_offset = (sgotplt->output_section->vma ++ + sgotplt->output_offset ++ + got_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT); ++ rela.r_addend = 0; ++ loc = srela->contents; ++ loc += plt_index * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ ++ if (!h->def_regular) ++ { ++ /* Mark the symbol as undefined, rather than as defined in ++ the .plt section. Zero the value. */ ++ sym->st_shndx = SHN_UNDEF; ++ sym->st_value = 0; ++ } ++ } ++ ++ /* h->got.refcount to be checked ? */ ++ if (h->got.offset != (bfd_vma) -1 && ++ ! ((h->got.offset & 1) || ++ IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask))) ++ { ++ asection *sgot; ++ asection *srela; ++ bfd_vma offset; ++ ++ /* This symbol has an entry in the global offset table. Set it ++ up. */ ++ ++ sgot = htab->sgot; ++ srela = htab->srelgot; ++ BFD_ASSERT (sgot != NULL && srela != NULL); ++ ++ offset = (sgot->output_section->vma + sgot->output_offset ++ + (h->got.offset &~ (bfd_vma) 1)); ++ ++ /* If this is a -Bsymbolic link, and the symbol is defined ++ locally, we just want to emit a RELATIVE reloc. Likewise if ++ the symbol was forced to be local because of a version file. ++ The entry in the global offset table will already have been ++ initialized in the relocate_section function. */ ++ if (bfd_link_pic (info) ++ && ((info->symbolic && h->def_regular) ++ || h->dynindx == -1)) ++ { ++ asection *sec = h->root.u.def.section; ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ /* symindex= */ 0, ++ R_MICROBLAZE_REL, offset, ++ h->root.u.def.value ++ + sec->output_section->vma ++ + sec->output_offset); ++ } ++ else ++ { ++ microblaze_elf_output_dynamic_relocation (output_bfd, ++ srela, srela->reloc_count++, ++ h->dynindx, ++ R_MICROBLAZE_GLOB_DAT, ++ offset, 0); ++ } ++ ++ bfd_put_32 (output_bfd, (bfd_vma) 0, ++ sgot->contents + (h->got.offset &~ (bfd_vma) 1)); ++ } ++ ++ if (h->needs_copy) ++ { ++ asection *s; ++ Elf_Internal_Rela rela; ++ bfd_byte *loc; ++ ++ /* This symbols needs a copy reloc. Set it up. */ ++ ++ BFD_ASSERT (h->dynindx != -1); ++ ++ s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss"); ++ BFD_ASSERT (s != NULL); ++ ++ rela.r_offset = (h->root.u.def.value ++ + h->root.u.def.section->output_section->vma ++ + h->root.u.def.section->output_offset); ++ rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY); ++ rela.r_addend = 0; ++ loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela); ++ bfd_elf64_swap_reloca_out (output_bfd, &rela, loc); ++ } ++ ++ /* Mark some specially defined symbols as absolute. */ ++ if (h == htab->elf.hdynamic ++ || h == htab->elf.hgot ++ || h == htab->elf.hplt) ++ sym->st_shndx = SHN_ABS; ++ ++ return TRUE; ++} ++ ++ ++/* Finish up the dynamic sections. */ ++ ++static bfd_boolean ++microblaze_elf_finish_dynamic_sections (bfd *output_bfd, ++ struct bfd_link_info *info) ++{ ++ bfd *dynobj; ++ asection *sdyn, *sgot; ++ struct elf64_mb_link_hash_table *htab; ++ ++ htab = elf64_mb_hash_table (info); ++ if (htab == NULL) ++ return FALSE; ++ ++ dynobj = htab->elf.dynobj; ++ ++ sdyn = bfd_get_linker_section (dynobj, ".dynamic"); ++ ++ if (htab->elf.dynamic_sections_created) ++ { ++ asection *splt; ++ Elf64_External_Dyn *dyncon, *dynconend; ++ ++ splt = bfd_get_linker_section (dynobj, ".plt"); ++ BFD_ASSERT (splt != NULL && sdyn != NULL); ++ ++ dyncon = (Elf64_External_Dyn *) sdyn->contents; ++ dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size); ++ for (; dyncon < dynconend; dyncon++) ++ { ++ Elf_Internal_Dyn dyn; ++ const char *name; ++ bfd_boolean size; ++ ++ bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn); ++ ++ switch (dyn.d_tag) ++ { ++ case DT_PLTGOT: name = ".got.plt"; size = FALSE; break; ++ case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break; ++ case DT_JMPREL: name = ".rela.plt"; size = FALSE; break; ++ case DT_RELA: name = ".rela.dyn"; size = FALSE; break; ++ case DT_RELASZ: name = ".rela.dyn"; size = TRUE; break; ++ default: name = NULL; size = FALSE; break; ++ } ++ ++ if (name != NULL) ++ { ++ asection *s; ++ ++ s = bfd_get_section_by_name (output_bfd, name); ++ if (s == NULL) ++ dyn.d_un.d_val = 0; ++ else ++ { ++ if (! size) ++ dyn.d_un.d_ptr = s->vma; ++ else ++ dyn.d_un.d_val = s->size; ++ } ++ bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon); ++ } ++ } ++ ++ /* Clear the first entry in the procedure linkage table, ++ and put a nop in the last four bytes. */ ++ if (splt->size > 0) ++ { ++ memset (splt->contents, 0, PLT_ENTRY_SIZE); ++ bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop. */, ++ splt->contents + splt->size - 4); ++ } ++ ++ elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ /* Set the first entry in the global offset table to the address of ++ the dynamic section. */ ++ sgot = bfd_get_linker_section (dynobj, ".got.plt"); ++ if (sgot && sgot->size > 0) ++ { ++ if (sdyn == NULL) ++ bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents); ++ else ++ bfd_put_32 (output_bfd, ++ sdyn->output_section->vma + sdyn->output_offset, ++ sgot->contents); ++ elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4; ++ } ++ ++ if (htab->sgot && htab->sgot->size > 0) ++ elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4; ++ ++ return TRUE; ++} ++ ++/* Hook called by the linker routine which adds symbols from an object ++ file. We use it to put .comm items in .sbss, and not .bss. */ ++ ++static bfd_boolean ++microblaze_elf_add_symbol_hook (bfd *abfd, ++ struct bfd_link_info *info, ++ Elf_Internal_Sym *sym, ++ const char **namep ATTRIBUTE_UNUSED, ++ flagword *flagsp ATTRIBUTE_UNUSED, ++ asection **secp, ++ bfd_vma *valp) ++{ ++ if (sym->st_shndx == SHN_COMMON ++ && !bfd_link_relocatable (info) ++ && sym->st_size <= elf_gp_size (abfd)) ++ { ++ /* Common symbols less than or equal to -G nn bytes are automatically ++ put into .sbss. */ ++ *secp = bfd_make_section_old_way (abfd, ".sbss"); ++ if (*secp == NULL ++ || ! bfd_set_section_flags (abfd, *secp, SEC_IS_COMMON)) ++ return FALSE; ++ ++ *valp = sym->st_size; ++ } ++ ++ return TRUE; ++} ++ ++#define TARGET_LITTLE_SYM microblaze_elf64_le_vec ++#define TARGET_LITTLE_NAME "elf64-microblazeel" ++ ++#define TARGET_BIG_SYM microblaze_elf64_vec ++#define TARGET_BIG_NAME "elf64-microblaze" ++ ++#define ELF_ARCH bfd_arch_microblaze ++#define ELF_TARGET_ID MICROBLAZE_ELF_DATA ++#define ELF_MACHINE_CODE EM_MICROBLAZE ++#define ELF_MACHINE_ALT1 EM_MICROBLAZE_OLD ++#define ELF_MAXPAGESIZE 0x1000 ++#define elf_info_to_howto microblaze_elf_info_to_howto ++#define elf_info_to_howto_rel NULL ++ ++#define bfd_elf64_bfd_reloc_type_lookup microblaze_elf_reloc_type_lookup ++#define bfd_elf64_bfd_is_local_label_name microblaze_elf_is_local_label_name ++#define elf_backend_relocate_section microblaze_elf_relocate_section ++#define bfd_elf64_bfd_relax_section microblaze_elf_relax_section ++#define bfd_elf64_bfd_merge_private_bfd_data microblaze_elf_merge_private_bfd_data ++#define bfd_elf64_bfd_reloc_name_lookup microblaze_elf_reloc_name_lookup ++ ++#define elf_backend_gc_mark_hook microblaze_elf_gc_mark_hook ++#define elf_backend_gc_sweep_hook microblaze_elf_gc_sweep_hook ++#define elf_backend_check_relocs microblaze_elf_check_relocs ++#define elf_backend_copy_indirect_symbol microblaze_elf_copy_indirect_symbol ++#define bfd_elf64_bfd_link_hash_table_create microblaze_elf_link_hash_table_create ++#define elf_backend_can_gc_sections 1 ++#define elf_backend_can_refcount 1 ++#define elf_backend_want_got_plt 1 ++#define elf_backend_plt_readonly 1 ++#define elf_backend_got_header_size 12 ++#define elf_backend_rela_normal 1 ++ ++#define elf_backend_adjust_dynamic_symbol microblaze_elf_adjust_dynamic_symbol ++#define elf_backend_create_dynamic_sections microblaze_elf_create_dynamic_sections ++#define elf_backend_finish_dynamic_sections microblaze_elf_finish_dynamic_sections ++#define elf_backend_finish_dynamic_symbol microblaze_elf_finish_dynamic_symbol ++#define elf_backend_size_dynamic_sections microblaze_elf_size_dynamic_sections ++#define elf_backend_add_symbol_hook microblaze_elf_add_symbol_hook ++ ++#include "elf64-target.h" +diff --git a/bfd/targets.c b/bfd/targets.c +index 158168c..ef567a3 100644 +--- a/bfd/targets.c ++++ b/bfd/targets.c +@@ -706,6 +706,8 @@ extern const bfd_target mep_elf32_le_vec; + extern const bfd_target metag_elf32_vec; + extern const bfd_target microblaze_elf32_vec; + extern const bfd_target microblaze_elf32_le_vec; ++extern const bfd_target microblaze_elf64_vec; ++extern const bfd_target microblaze_elf64_le_vec; + extern const bfd_target mips_ecoff_be_vec; + extern const bfd_target mips_ecoff_le_vec; + extern const bfd_target mips_ecoff_bele_vec; +@@ -1073,6 +1075,10 @@ static const bfd_target * const _bfd_target_vector[] = + + &metag_elf32_vec, + ++#ifdef BFD64 ++ µblaze_elf64_vec, ++ µblaze_elf64_le_vec, ++#endif + µblaze_elf32_vec, + + &mips_ecoff_be_vec, +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 16b10d0..c794347 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -35,10 +35,13 @@ + #define streq(a,b) (strcmp (a, b) == 0) + #endif + ++static int microblaze_arch_size = 0; ++ + #define OPTION_EB (OPTION_MD_BASE + 0) + #define OPTION_EL (OPTION_MD_BASE + 1) + #define OPTION_LITTLE (OPTION_MD_BASE + 2) + #define OPTION_BIG (OPTION_MD_BASE + 3) ++#define OPTION_M64 (OPTION_MD_BASE + 4) + + void microblaze_generate_symbol (char *sym); + static bfd_boolean check_spl_reg (unsigned *); +@@ -773,6 +776,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + return new_pointer; + } + ++ static char * ++parse_imml (char * s, expressionS * e, long min, long max) ++{ ++ char *new_pointer; ++ char *atp; ++ int itype, ilen; ++ ++ ilen = 0; ++ ++ /* Find the start of "@GOT" or "@PLT" suffix (if any) */ ++ for (atp = s; *atp != '@'; atp++) ++ if (is_end_of_line[(unsigned char) *atp]) ++ break; ++ ++ if (*atp == '@') ++ { ++ itype = match_imm (atp + 1, &ilen); ++ if (itype != 0) ++ { ++ *atp = 0; ++ e->X_md = itype; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ ilen = 0; ++ } ++ *atp = 0; ++ } ++ else ++ { ++ atp = NULL; ++ e->X_md = 0; ++ } ++ ++ if (atp && !GOT_symbol) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ new_pointer = parse_exp (s, e); ++ ++ if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20)) ++ { ++ GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME); ++ } ++ ++ if (e->X_op == O_absent) ++ ; /* An error message has already been emitted. */ ++ else if ((e->X_op != O_constant && e->X_op != O_symbol) ) ++ as_fatal (_("operand must be a constant or a label")); ++ else if ((e->X_op == O_constant) && ((long) e->X_add_number < min ++ || (long) e->X_add_number > max)) ++ { ++ as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), ++ min, max, (long) e->X_add_number); ++ } ++ ++ if (atp) ++ { ++ *atp = '@'; /* restore back (needed?) */ ++ if (new_pointer >= atp) ++ new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */ ++ } ++ return new_pointer; ++} ++ + static char * + check_got (int * got_type, int * got_len) + { +@@ -920,6 +991,7 @@ md_assemble (char * str) + unsigned int immed, immed2, temp; + expressionS exp; + char name[20]; ++ long immedl; + + /* Drop leading whitespace. */ + while (ISSPACE (* str)) +@@ -1129,7 +1201,7 @@ md_assemble (char * str) + } + break; + +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1163,16 +1235,22 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + +- if (immed != (immed % 32)) ++ if ((immed != (immed % 32)) && ++ (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli)) + { + as_warn (_("Shift value > 32. using <value %% 32>")); + immed = immed % 32; + } ++ else if (immed != (immed % 64)) ++ { ++ as_warn (_("Shift value > 64. using <value %% 64>")); ++ immed = immed % 64; ++ } + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM5_MASK; ++ inst |= (immed << IMM_LOW) & IMM6_MASK; + break; +- case INST_TYPE_RD_R1_IMM5_IMM5: ++ case INST_TYPE_RD_R1_IMMW_IMMS: + if (strcmp (op_end, "")) + op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ + else +@@ -1196,7 +1274,7 @@ md_assemble (char * str) + + /* Width immediate value. */ + if (strcmp (op_end, "")) +- op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH); ++ op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM); + else + as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +@@ -1208,6 +1286,8 @@ md_assemble (char * str) + immed = exp.X_add_number; + if (opcode->instr == bsefi && immed > 31) + as_fatal (_("Width value must be less than 32")); ++ else if (opcode->instr == bslefi && immed > 63) ++ as_fatal (_("Width value must be less than 64")); + + /* Shift immediate value. */ + if (strcmp (op_end, "")) +@@ -1215,32 +1295,40 @@ md_assemble (char * str) + else + as_fatal (_("Error in statement syntax")); + if (exp.X_op != O_constant) +- { ++ { + as_warn (_("Symbol used as immediate shift value for bit field instruction")); + immed2 = 0; + } + else +- { ++ { + output = frag_more (isize); + immed2 = exp.X_add_number; +- } +- if (immed2 != (immed2 % 32)) +- { +- as_warn (_("Shift value greater than 32. using <value %% 32>")); ++ } ++ if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi)) ++ { ++ ++ as_warn (_("Shift value greater than 32. using <value %% 32>")); + immed2 = immed2 % 32; + } ++ else if (immed2 != (immed2 % 64)) ++ { ++ as_warn (_("Shift value greater than 64. using <value %% 64>")); ++ immed2 = immed2 % 64; ++ } + + /* Check combined value. */ +- if (immed + immed2 > 32) ++ if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi)) + as_fatal (_("Width value + shift value must not be greater than 32")); + ++ else if (immed + immed2 > 64) ++ as_fatal (_("Width value + shift value must not be greater than 64")); + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (reg2 << RA_LOW) & RA_MASK; +- if (opcode->instr == bsefi) +- inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */ ++ if (opcode->instr == bsefi || opcode->instr == bslefi) ++ inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */ + else +- inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */ +- inst |= (immed2 << IMM_LOW) & IMM5_MASK; ++ inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */ ++ inst |= (immed2 << IMM_LOW) & IMM6_MASK; + break; + case INST_TYPE_R1_R2: + if (strcmp (op_end, "")) +@@ -1808,6 +1896,142 @@ md_assemble (char * str) + } + inst |= (immed << IMM_MBAR); + break; ++ /* For 64-bit instructions */ ++ case INST_TYPE_RD_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®2); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg2 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (& reg1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ if (check_spl_reg (& reg2)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_R1_IMML: ++ if (strcmp (op_end, "")) ++ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */ ++ else ++ { ++ as_fatal (_("Error in statement syntax")); ++ reg1 = 0; ++ } ++ if (strcmp (op_end, "")) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ else ++ as_fatal (_("Error in statement syntax")); ++ ++ /* Check for spl registers. */ ++ if (check_spl_reg (®1)) ++ as_fatal (_("Cannot use special register with this instruction")); ++ ++ if (exp.X_op != O_constant) ++ { ++ char *opc = NULL; ++ relax_substateT subtype; ++ ++ if (exp.X_md != 0) ++ subtype = get_imm_otype(exp.X_md); ++ else ++ subtype = opcode->inst_offset_type; ++ ++ output = frag_var (rs_machine_dependent, ++ isize * 2, /* maxm of 2 words. */ ++ isize * 2, /* minm of 2 words. */ ++ subtype, /* PC-relative or not. */ ++ exp.X_add_symbol, ++ exp.X_add_number, ++ opc); ++ immedl = 0L; ++ } ++ else ++ { ++ output = frag_more (isize); ++ immedl = exp.X_add_number; ++ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ ++ inst |= (reg1 << RA_LOW) & RA_MASK; ++ inst |= (immedl << IMM_LOW) & IMM_MASK; ++ break; ++ ++ case INST_TYPE_IMML: ++ as_fatal (_("An IMML instruction should not be present in the .s file")); ++ break; + + default: + as_fatal (_("unimplemented opcode \"%s\""), name); +@@ -1918,6 +2142,7 @@ struct option md_longopts[] = + {"EL", no_argument, NULL, OPTION_EL}, + {"mlittle-endian", no_argument, NULL, OPTION_LITTLE}, + {"mbig-endian", no_argument, NULL, OPTION_BIG}, ++ {"m64", no_argument, NULL, OPTION_M64}, + { NULL, no_argument, NULL, 0} + }; + +@@ -2569,6 +2794,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + return rel; + } + ++/* Called by TARGET_FORMAT. */ ++const char * ++microblaze_target_format (void) ++{ ++ ++ if (microblaze_arch_size == 64) ++ return "elf64-microblazeel"; ++ else ++ return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel"; ++} ++ ++ + int + md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + { +@@ -2582,6 +2819,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_LITTLE: + target_big_endian = 0; + break; ++ case OPTION_M64: ++ //if (arg != NULL && strcmp (arg, "64") == 0) ++ microblaze_arch_size = 64; ++ break; + default: + return 0; + } +@@ -2597,6 +2838,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED) + fprintf (stream, _(" MicroBlaze specific assembler options:\n")); + fprintf (stream, " -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu")); + fprintf (stream, " -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu")); ++ fprintf (stream, " -%-23s%s\n", "m64", N_("generate 64-bit elf")); + } + + +diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h +index ca9dbb8..9d38d2c 100644 +--- a/gas/config/tc-microblaze.h ++++ b/gas/config/tc-microblaze.h +@@ -78,7 +78,9 @@ extern const struct relax_type md_relax_table[]; + + #ifdef OBJ_ELF + +-#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") ++#define TARGET_FORMAT microblaze_target_format() ++extern const char *microblaze_target_format (void); ++//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel") + + #define ELF_TC_SPECIAL_SECTIONS \ + { ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, \ +diff --git a/include/elf/common.h b/include/elf/common.h +index 996acf9..2f1e5be 100644 +--- a/include/elf/common.h ++++ b/include/elf/common.h +@@ -339,6 +339,7 @@ + #define EM_RISCV 243 /* RISC-V */ + #define EM_LANAI 244 /* Lanai 32-bit processor. */ + #define EM_BPF 247 /* Linux BPF – in-kernel virtual machine. */ ++#define EM_MB_64 248 /* Xilinx MicroBlaze 32-bit RISC soft processor core */ + #define EM_NFP 250 /* Netronome Flow Processor. */ + #define EM_CSKY 252 /* C-SKY processor family. */ + +diff --git a/ld/Makefile.am b/ld/Makefile.am +index d7faf19..f7b3b97 100644 +--- a/ld/Makefile.am ++++ b/ld/Makefile.am +@@ -422,6 +422,8 @@ ALL_64_EMULATION_SOURCES = \ + eelf32ltsmipn32.c \ + eelf32ltsmipn32_fbsd.c \ + eelf32mipswindiss.c \ ++ eelf64microblazeel.c \ ++ eelf64microblaze.c \ + eelf64_aix.c \ + eelf64_ia64.c \ + eelf64_ia64_fbsd.c \ +@@ -1702,6 +1704,12 @@ eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ++eelf64microblazeel.c: $(srcdir)/emulparams/elf64microblazeel.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ ++eelf64microblaze.c: $(srcdir)/emulparams/elf64microblaze.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ + eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +diff --git a/ld/Makefile.in b/ld/Makefile.in +index 8b14f52..ffc9a3e 100644 +--- a/ld/Makefile.in ++++ b/ld/Makefile.in +@@ -907,6 +907,8 @@ ALL_64_EMULATION_SOURCES = \ + eelf32ltsmipn32.c \ + eelf32ltsmipn32_fbsd.c \ + eelf32mipswindiss.c \ ++ eelf64microblazeel.c \ ++ eelf64microblaze.c \ + eelf64_aix.c \ + eelf64_ia64.c \ + eelf64_ia64_fbsd.c \ +@@ -1355,6 +1357,8 @@ distclean-compile: + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xc16xs.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Po@am__quote@ + @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Po@am__quote@ +@@ -3306,6 +3310,12 @@ eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_X86_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ++eelf64microblazeel.c: $(srcdir)/emulparams/elf64microblazeel.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ ++eelf64microblaze.c: $(srcdir)/emulparams/elf64microblaze.sh \ ++ $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} ++ + eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +diff --git a/ld/configure.tgt b/ld/configure.tgt +index 1e37d74..42f106d 100644 +--- a/ld/configure.tgt ++++ b/ld/configure.tgt +@@ -424,6 +424,9 @@ microblaze*-linux*) targ_emul="elf32mb_linux" + microblazeel*) targ_emul=elf32microblazeel + targ_extra_emuls=elf32microblaze + ;; ++microblazeel64*) targ_emul=elf64microblazeel ++ targ_extra_emuls=elf64microblaze ++ ;; + microblaze*) targ_emul=elf32microblaze + targ_extra_emuls=elf32microblazeel + ;; +diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh +new file mode 100644 +index 0000000..9c7b0eb +--- /dev/null ++++ b/ld/emulparams/elf64microblaze.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh +new file mode 100644 +index 0000000..9c7b0eb +--- /dev/null ++++ b/ld/emulparams/elf64microblazeel.sh +@@ -0,0 +1,23 @@ ++SCRIPT_NAME=elfmicroblaze ++OUTPUT_FORMAT="elf64-microblazeel" ++#BIG_OUTPUT_FORMAT="elf64-microblaze" ++LITTLE_OUTPUT_FORMAT="elf64-microblazeel" ++#TEXT_START_ADDR=0 ++NONPAGED_TEXT_START_ADDR=0x28 ++ALIGNMENT=4 ++MAXPAGESIZE=4 ++ARCH=microblaze ++EMBEDDED=yes ++ ++NOP=0x80000000 ++ ++# Hmmm, there's got to be a better way. This sets the stack to the ++# top of the simulator memory (2^19 bytes). ++#PAGE_SIZE=0x1000 ++#DATA_ADDR=0x10000 ++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }' ++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@} ++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);' ++ ++TEMPLATE_NAME=elf32 ++#GENERATE_SHLIB_SCRIPT=yes +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index f8aaf27..20ea6a8 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -33,6 +33,7 @@ + #define get_field_r1(instr) get_field (instr, RA_MASK, RA_LOW) + #define get_field_r2(instr) get_field (instr, RB_MASK, RB_LOW) + #define get_int_field_imm(instr) ((instr & IMM_MASK) >> IMM_LOW) ++#define get_int_field_imml(instr) ((instr & IMML_MASK) >> IMM_LOW) + #define get_int_field_r1(instr) ((instr & RA_MASK) >> RA_LOW) + + +@@ -56,11 +57,20 @@ get_field_imm (long instr) + } + + static char * +-get_field_imm5 (long instr) ++get_field_imml (long instr) + { + char tmpstr[25]; + +- sprintf (tmpstr, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW)); ++ sprintf (tmpstr, "%d", (short)((instr & IMML_MASK) >> IMM_LOW)); ++ return (strdup (tmpstr)); ++} ++ ++static char * ++get_field_imms (long instr) ++{ ++ char tmpstr[25]; ++ ++ sprintf (tmpstr, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); + } + +@@ -74,14 +84,14 @@ get_field_imm5_mbar (long instr) + } + + static char * +-get_field_imm5width (long instr) ++get_field_immw (long instr) + { + char tmpstr[25]; + + if (instr & 0x00004000) +- sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ ++ sprintf (tmpstr, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ + else +- sprintf (tmpstr, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ ++ sprintf (tmpstr, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */ + return (strdup (tmpstr)); + } + +@@ -286,9 +296,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; +- case INST_TYPE_RD_R1_IMM5: ++ case INST_TYPE_RD_R1_IMML: ++ print_func (stream, "\t%s, %s, %s", get_field_rd (inst), ++ get_field_r1(inst), get_field_imm (inst)); ++ /* TODO: Also print symbol */ ++ case INST_TYPE_RD_R1_IMMS: + print_func (stream, "\t%s, %s, %s", get_field_rd (inst), +- get_field_r1(inst), get_field_imm5 (inst)); ++ get_field_r1(inst), get_field_imms (inst)); + break; + case INST_TYPE_RD_RFSL: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_rfsl (inst)); +@@ -386,6 +400,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + } + } + break; ++ case INST_TYPE_IMML: ++ print_func (stream, "\t%s", get_field_imml (inst)); ++ /* TODO: Also print symbol */ ++ break; + case INST_TYPE_RD_R2: + print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst)); + break; +@@ -409,9 +427,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) + case INST_TYPE_NONE: + break; + /* For bit field insns. */ +- case INST_TYPE_RD_R1_IMM5_IMM5: +- print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst),get_field_r1(inst),get_field_imm5width (inst), get_field_imm5 (inst)); +- break; ++ case INST_TYPE_RD_R1_IMMW_IMMS: ++ print_func (stream, "\t%s, %s, %s, %s", get_field_rd (inst), get_field_r1(inst), ++ get_field_immw (inst), get_field_imms (inst)); ++ break; + /* For tuqula instruction */ + case INST_TYPE_RD: + print_func (stream, "\t%s", get_field_rd (inst)); +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index ce8ac35..985834b 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -40,7 +40,7 @@ + #define INST_TYPE_RD_SPECIAL 11 + #define INST_TYPE_R1 12 + /* New instn type for barrel shift imms. */ +-#define INST_TYPE_RD_R1_IMM5 13 ++#define INST_TYPE_RD_R1_IMMS 13 + #define INST_TYPE_RD_RFSL 14 + #define INST_TYPE_R1_RFSL 15 + +@@ -60,7 +60,13 @@ + #define INST_TYPE_IMM5 20 + + /* For bsefi and bsifi */ +-#define INST_TYPE_RD_R1_IMM5_IMM5 21 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 ++ ++/* For 64-bit instructions */ ++#define INST_TYPE_IMML 22 ++#define INST_TYPE_RD_R1_IMML 23 ++#define INST_TYPE_R1_IMML 24 ++#define INST_TYPE_RD_R1_IMMW_IMMS 21 + + #define INST_TYPE_NONE 25 + +@@ -91,13 +97,14 @@ + #define OPCODE_MASK_H24 0xFC1F07FF /* High 6, bits 20-16 and low 11 bits. */ + #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ + #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ +-#define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ +-#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */ ++#define OPCODE_MASK_H3 0xFC000700 /* High 6 bits and bits 21, 22, 23. */ ++#define OPCODE_MASK_H3B 0xFC00E600 /* High 6 bits and bits 16, 17, 18, 21, 22. */ + #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ +-#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */ ++#define OPCODE_MASK_H32B 0xFC00E000 /* High 6 bits and bit 16, 17, 18. */ + #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ + #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ + #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ ++#define OPCODE_MASK_H8 0xFF000000 /* High 8 bits only. */ + + /* New Mask for msrset, msrclr insns. */ + #define OPCODE_MASK_H23N 0xFC1F8000 /* High 6 and bits 11 - 16. */ +@@ -107,7 +114,7 @@ + #define DELAY_SLOT 1 + #define NO_DELAY_SLOT 0 + +-#define MAX_OPCODES 301 ++#define MAX_OPCODES 412 + + struct op_code_struct + { +@@ -125,6 +132,7 @@ struct op_code_struct + /* More info about output format here. */ + } opcodes[MAX_OPCODES] = + { ++ /* 32-bit instructions */ + {"add", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst }, + {"rsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst }, + {"addc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst }, +@@ -161,11 +169,11 @@ struct op_code_struct + {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst }, + {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst }, + {"muli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst }, +- {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, +- {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, +- {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, +- {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, +- {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, ++ {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst }, ++ {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst }, ++ {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst }, ++ {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, ++ {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, + {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, + {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, + {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, +@@ -425,6 +433,129 @@ struct op_code_struct + {"suspend", INST_TYPE_NONE, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN, invalid_inst, special_inst }, /* translates to mbar 24. */ + {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst }, + {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst }, ++ ++ /* 64-bit instructions */ ++ {"addl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst }, ++ {"rsubl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst }, ++ {"addlc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst }, ++ {"rsublc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst }, ++ {"addlk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst }, ++ {"rsublk", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst }, ++ {"addlkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst }, ++ {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst }, ++ {"cmpl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst }, ++ {"cmplu", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst }, ++ {"addli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsubli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* Identical to 32-bit */ ++ {"mull", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst }, ++ {"bslll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst }, ++ {"bslra", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst }, ++ {"bslrl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst }, ++ {"bsllli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst }, ++ {"bslrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst }, ++ {"bslrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst }, ++ {"bslefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst }, ++ {"bslifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst }, ++ {"orl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst }, ++ {"andl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst }, ++ {"xorl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst }, ++ {"andnl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst }, ++ {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst }, ++ {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst }, ++ {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst }, ++ {"srla", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst }, ++ {"srlc", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst }, ++ {"srll", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst }, ++ {"sextl8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst }, ++ {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst }, ++ {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst }, ++ {"brea", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst }, ++ {"bread", INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst }, ++ {"breald", INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst }, ++ {"beaeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst }, ++ {"bealeq", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst }, ++ {"beaeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst }, ++ {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst }, ++ {"beane", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst }, ++ {"bealne", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst }, ++ {"beaned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst }, ++ {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst }, ++ {"bealt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst }, ++ {"beallt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst }, ++ {"bealtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst }, ++ {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst }, ++ {"beale", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst }, ++ {"bealle", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst }, ++ {"bealed", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst }, ++ {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst }, ++ {"beagt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst }, ++ {"bealgt", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst }, ++ {"beagtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst }, ++ {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst }, ++ {"beage", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst }, ++ {"bealge", INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst }, ++ {"beaged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst }, ++ {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst }, ++ {"orli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"xorli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"andnli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst }, /* Identical to 32-bit */ ++ {"imml", INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst }, ++ {"breai", INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst }, ++ {"breaid", INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst }, ++ {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst }, ++ {"beaeqi", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst }, ++ {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */ ++ {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst }, ++ {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqid */ ++ {"beanei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst }, ++ {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */ ++ {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst }, ++ {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaneid */ ++ {"bealti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst }, ++ {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */ ++ {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst }, ++ {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealtid */ ++ {"bealei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst }, ++ {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */ ++ {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst }, ++ {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealeid */ ++ {"beagti", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst }, ++ {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */ ++ {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst }, ++ {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagtid */ ++ {"beagei", INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst }, ++ {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */ ++ {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst }, ++ {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beageid */ ++ {"ll", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst }, ++ {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, ++ {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, ++ {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, ++ {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ ++ {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, ++ {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, ++ {"dmul", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst }, ++ {"ddiv", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst }, ++ {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst }, ++ {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst }, ++ {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst }, ++ {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst }, ++ {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst }, ++ {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst }, ++ {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst }, ++ {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, ++ {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, ++ {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ + {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; + +@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM5 ((int) 0x00000000) + #define MAX_IMM5 ((int) 0x0000001f) + ++#define MIN_IMM6 ((int) 0x00000000) ++#define MAX_IMM6 ((int) 0x0000003f) ++ + #define MIN_IMM_WIDTH ((int) 0x00000001) + #define MAX_IMM_WIDTH ((int) 0x00000020) + ++#define MIN_IMM6_WIDTH ((int) 0x00000001) ++#define MAX_IMM6_WIDTH ((int) 0x00000040) ++ ++#define MIN_IMML ((long) 0xffffff8000000000L) ++#define MAX_IMML ((long) 0x0000007fffffffffL) ++ + #endif /* MICROBLAZE_OPC */ + +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 2866269..076dbcd 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -25,6 +25,7 @@ + + enum microblaze_instr + { ++ /* 32-bit instructions */ + add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu, + addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, + mulh, mulhu, mulhsu,swapb,swaph, +@@ -58,6 +59,18 @@ enum microblaze_instr + aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd, + eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd, + eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd, ++ ++ /* 64-bit instructions */ ++ addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull, ++ bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl, ++ andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32, ++ brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned, ++ bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt, ++ bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid, ++ beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti, ++ beagtid, beagei, beageid, imml, ll, llr, sl, slr, ++ dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge, ++ dcmp_un, dbl, dlong, dsqrt, + invalid_inst + }; + +@@ -135,15 +148,18 @@ enum microblaze_instr_type + #define RA_MASK 0x001F0000 + #define RB_MASK 0x0000F800 + #define IMM_MASK 0x0000FFFF ++#define IMML_MASK 0x00FFFFFF + +-/* Imm mask for barrel shifts. */ ++/* Imm masks for barrel shifts. */ + #define IMM5_MASK 0x0000001F ++#define IMM6_MASK 0x0000003F + + /* Imm mask for mbar. */ + #define IMM5_MBAR_MASK 0x03E00000 + +-/* Imm mask for extract/insert width. */ ++/* Imm masks for extract/insert width. */ + #define IMM5_WIDTH_MASK 0x000007C0 ++#define IMM6_WIDTH_MASK 0x00000FC0 + + /* FSL imm mask for get, put instructions. */ + #define RFSL_MASK 0x000000F diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch new file mode 100644 index 0000000000..406d7bf2cd --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0016-MB-X-initial-commit.patch @@ -0,0 +1,692 @@ +From 549bf1fafb7dfa2718e172a94ff68acb14320ed8 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 16:31:26 +0530 +Subject: [PATCH] MB-X initial commit code cleanup is needed. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/bfd-in2.h | 10 +++ + bfd/elf32-microblaze.c | 65 +++++++++++++++++-- + bfd/elf64-microblaze.c | 61 +++++++++++++++++- + bfd/libbfd.h | 2 + + bfd/reloc.c | 12 ++++ + gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++++++++++++-------- + include/elf/microblaze.h | 2 + + opcodes/microblaze-opc.h | 4 +- + opcodes/microblaze-opcm.h | 4 +- + 9 files changed, 277 insertions(+), 35 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index fe6933a..90645d1 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5878,11 +5878,21 @@ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, + + /* This is a 64 bit reloc that stores the 32 bit pc relative ++value in two words (with an imml instruction). The relocation is ++PC-relative GOT offset */ ++ BFD_RELOC_MICROBLAZE_64_GPC, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOT, +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index d001437..035e71f 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ ++ + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ +@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1467,7 +1502,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1933,6 +1968,28 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; + case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { +@@ -2037,9 +2094,9 @@ microblaze_elf_relax_section (bfd *abfd, + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, + irelscan->r_addend); + } +- if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) +- { +- isym = isymbuf + ELF32_R_SYM (irelscan->r_info); ++ if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)// || ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) ++ { ++ isym = isymbuf + ELF32_R_SYM (irelscan->r_info); + + /* Look at the reloc only if the value has been resolved. */ + if (isym->st_shndx == shndx +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 0f43ae6..56a45f2 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -117,6 +117,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + TRUE), /* PC relative offset? */ + + /* A 64 bit relocation. Table entry not really used. */ ++ HOWTO (R_MICROBLAZE_IMML_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 4, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 64, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc,/* Special Function. */ ++ "R_MICROBLAZE_IMML_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ ++ /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ + 0, /* Rightshift. */ + 2, /* Size (0 = byte, 1 = short, 2 = long). */ +@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0x0000ffff, /* Dest Mask. */ + TRUE), /* PC relative offset? */ + ++ /* A 64 bit GOTPC relocation. Table-entry not really used. */ ++ HOWTO (R_MICROBLAZE_GPC_64, /* Type. */ ++ 0, /* Rightshift. */ ++ 2, /* Size (0 = byte, 1 = short, 2 = long). */ ++ 16, /* Bitsize. */ ++ TRUE, /* PC_relative. */ ++ 0, /* Bitpos. */ ++ complain_overflow_dont, /* Complain on overflow. */ ++ bfd_elf_generic_reloc, /* Special Function. */ ++ "R_MICROBLAZE_GPC_64", /* Name. */ ++ FALSE, /* Partial Inplace. */ ++ 0, /* Source Mask. */ ++ 0x0000ffff, /* Dest Mask. */ ++ TRUE), /* PC relative offset? */ ++ + /* A 64 bit GOT relocation. Table-entry not really used. */ + HOWTO (R_MICROBLAZE_GOT_64, /* Type. */ + 0, /* Rightshift. */ +@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; ++ case BFD_RELOC_MICROBLAZE_64: ++ microblaze_reloc = R_MICROBLAZE_IMML_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: + microblaze_reloc = R_MICROBLAZE_GOTPC_64; + break; ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ microblaze_reloc = R_MICROBLAZE_GPC_64; ++ break; + case BFD_RELOC_MICROBLAZE_64_GOT: + microblaze_reloc = R_MICROBLAZE_GOT_64; + break; +@@ -1161,6 +1197,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + break; /* Do nothing. */ + + case (int) R_MICROBLAZE_GOTPC_64: ++ case (int) R_MICROBLAZE_GPC_64: + relocation = htab->sgotplt->output_section->vma + + htab->sgotplt->output_offset; + relocation -= (input_section->output_section->vma +@@ -1431,7 +1468,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0) + { + relocation += addend; +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); + else + { +@@ -1876,6 +1913,28 @@ microblaze_elf_relax_section (bfd *abfd, + irel->r_addend -= calc_fixup (irel->r_addend, 0, sec); + } + break; ++ case R_MICROBLAZE_IMML_64: ++ { ++ /* This was a PC-relative instruction that was ++ completely resolved. */ ++ int sfix, efix; ++ unsigned int val; ++ bfd_vma target_address; ++ target_address = irel->r_addend + irel->r_offset; ++ sfix = calc_fixup (irel->r_offset, 0, sec); ++ efix = calc_fixup (target_address, 0, sec); ++ ++ /* Validate the in-band val. */ ++ val = bfd_get_32 (abfd, contents + irel->r_offset); ++ if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { ++ fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); ++ } ++ irel->r_addend -= (efix - sfix); ++ /* Should use HOWTO. */ ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); ++ } ++ break; + case R_MICROBLAZE_NONE: + case R_MICROBLAZE_32_NONE: + { +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index feb9fad..450653f 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2903,7 +2903,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", ++ "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", ++ "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index 87753ae..ccf29f5 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6804,6 +6804,12 @@ ENUMDOC + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64 ++ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing +@@ -6811,6 +6817,12 @@ ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++ BFD_RELOC_MICROBLAZE_64_GPC ++ENUMDOC ++ This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset + ENUM +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c794347..3f90b7c 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -94,6 +94,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; + #define TLSTPREL_OFFSET 16 + #define TEXT_OFFSET 17 + #define TEXT_PC_OFFSET 18 ++#define DEFINED_64_OFFSET 19 + + /* Initialize the relax table. */ + const relax_typeS md_relax_table[] = +@@ -117,6 +118,8 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++// { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 17: DEFINED_64_OFFSET. */ + }; + + static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ +@@ -396,7 +399,8 @@ const pseudo_typeS md_pseudo_table[] = + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ +- {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ ++ {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ ++ {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -405,6 +409,7 @@ const pseudo_typeS md_pseudo_table[] = + {"sbss", microblaze_s_bss, 1}, + {"text", microblaze_s_text, 0}, + {"word", cons, 4}, ++ {"dword", cons, 8}, + {"frame", s_ignore, 0}, + {"mask", s_ignore, 0}, /* Emitted by gcc. */ + {NULL, NULL, 0} +@@ -898,7 +903,7 @@ check_got (int * got_type, int * got_len) + extern bfd_reloc_code_real_type + parse_cons_expression_microblaze (expressionS *exp, int size) + { +- if (size == 4) ++ if (size == 4 || (microblaze_arch_size == 64 && size == 8)) + { + /* Handle @GOTOFF et.al. */ + char *save, *gotfree_copy; +@@ -930,6 +935,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size) + + static const char * str_microblaze_ro_anchor = "RO"; + static const char * str_microblaze_rw_anchor = "RW"; ++static const char * str_microblaze_64 = "64"; + + static bfd_boolean + check_spl_reg (unsigned * reg) +@@ -1174,6 +1180,33 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } ++#if 0 //revisit ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFFFFFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++#endif + else + { + temp = immed & 0xFFFF8000; +@@ -1926,6 +1959,7 @@ md_assemble (char * str) + if (exp.X_op != O_constant) + { + char *opc = NULL; ++ //char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -1939,7 +1973,7 @@ md_assemble (char * str) + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, +- opc); ++ (char *) opc); + immedl = 0L; + } + else +@@ -1977,7 +2011,7 @@ md_assemble (char * str) + reg1 = 0; + } + if (strcmp (op_end, "")) +- op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); + else + as_fatal (_("Error in statement syntax")); + +@@ -1987,7 +2021,8 @@ md_assemble (char * str) + + if (exp.X_op != O_constant) + { +- char *opc = NULL; ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -2001,14 +2036,13 @@ md_assemble (char * str) + subtype, /* PC-relative or not. */ + exp.X_add_symbol, + exp.X_add_number, +- opc); ++ (char *) opc); + immedl = 0L; + } + else + { + output = frag_more (isize); + immedl = exp.X_add_number; +- + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { +@@ -2187,13 +2221,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_OFFSET: ++ if (fragP->fr_symbol == GOT_symbol) ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC); ++ else ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_ABS_SEGMENT: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, FALSE, BFD_RELOC_64); ++ fragP->fr_offset, TRUE, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2416,22 +2460,38 @@ md_apply_fix (fixS * fixP, + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: ++ case BFD_RELOC_MICROBLAZE_64: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + +- /* Generate the imm instruction. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +- ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ } ++ else ++ { ++ /* Generate the imm instruction. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; ++ } + buf[0] = INST_BYTE0 (inst1); + buf[1] = INST_BYTE1 (inst1); + buf[2] = INST_BYTE2 (inst1); +@@ -2460,6 +2520,7 @@ md_apply_fix (fixS * fixP, + /* Fall through. */ + + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2467,12 +2528,16 @@ md_apply_fix (fixS * fixP, + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- +- /* Generate the imm instruction. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ else ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ else ++ as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } + +@@ -2496,6 +2561,8 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2539,6 +2606,32 @@ md_estimate_size_before_relax (fragS * fragP, + as_bad (_("Absolute PC-relative value in relaxation code. Assembler error.....")); + abort (); + } ++ else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type ++ && !S_IS_WEAK (fragP->fr_symbol)) ++ { ++ if (fragP->fr_opcode != NULL) { ++ if(streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++ else ++ { ++ fragP->fr_subtype = DEFINED_PC_OFFSET; ++ /* Don't know now whether we need an imm instruction. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } ++ } ++ #if 0 + else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && + !S_IS_WEAK (fragP->fr_symbol)) + { +@@ -2546,6 +2639,7 @@ md_estimate_size_before_relax (fragS * fragP, + /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } ++#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2648,6 +2742,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSLD_OFFSET: + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: ++ case DEFINED_64_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2701,7 +2796,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2734,6 +2829,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_RWSDA: + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: ++ case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: +@@ -2876,7 +2973,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- r = BFD_RELOC_64; ++ if (microblaze_arch_size == 64) ++ r = BFD_RELOC_32; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h +index 6ee0966..16b2736 100644 +--- a/include/elf/microblaze.h ++++ b/include/elf/microblaze.h +@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type) + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31) /* TEXT Entry offset 64-bit. */ + RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit. */ + RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33) ++ RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34) ++ RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35) /* GOT entry offset. */ + + END_RELOC_NUMBERS (R_MICROBLAZE_max) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 985834b..9b6264b 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -538,8 +538,8 @@ struct op_code_struct + {"llr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst }, + {"sl", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst }, + {"slr", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst }, +- {"lli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ +- {"sli", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ ++ {"lli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, /* Identical to 32-bit */ ++ {"sli", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */ + {"lla", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* lla translates to addlik */ + {"dadd", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst }, + {"drsub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst }, +diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h +index 076dbcd..5f2e190 100644 +--- a/opcodes/microblaze-opcm.h ++++ b/opcodes/microblaze-opcm.h +@@ -40,8 +40,8 @@ enum microblaze_instr + imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid, + brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti, + bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx, +- sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, +- sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, ++ sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli, ++ sbi, shi, sli, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv, + fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt, + fint, fsqrt, + tget, tcget, tnget, tncget, tput, tcput, tnput, tncput, diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch new file mode 100644 index 0000000000..062ee364cc --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch @@ -0,0 +1,36 @@ +From 3735a1bb6174f15bde23dd2767675b49c9e8712f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 11 Sep 2018 13:48:33 +0530 +Subject: [PATCH] negl instruction is overriding rsubl,fixed it by changing the + instruction order... + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + opcodes/microblaze-opc.h | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 9b6264b..824afc0 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -275,9 +275,7 @@ struct op_code_struct + {"la", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik. */ + {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42. */ + {"not", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1. */ +- {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ + {"rtb", INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4. */ +- {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + {"lmi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst }, + {"smi", INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, + {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst }, +@@ -555,6 +553,8 @@ struct op_code_struct + {"dbl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl, arithmetic_inst }, + {"dlong", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst }, + {"dsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst }, ++ {"neg", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0. */ ++ {"sub", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra. */ + + {"", 0, 0, 0, 0, 0, 0, 0, 0}, + }; diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch new file mode 100644 index 0000000000..b98db228d1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0018-Added-relocations-for-MB-X.patch @@ -0,0 +1,348 @@ +From 6b6c4a67212ced3fe1593fb173cfc4bce8d7f922 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 11 Sep 2018 17:30:17 +0530 +Subject: [PATCH] Added relocations for MB-X + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/bfd-in2.h | 11 ++++-- + bfd/libbfd.h | 4 +-- + bfd/reloc.c | 26 +++++++------- + gas/config/tc-microblaze.c | 90 ++++++++++++++++++++-------------------------- + 4 files changed, 62 insertions(+), 69 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index 90645d1..f74aac1 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5873,16 +5873,21 @@ done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_32_NONE, + + /* This is a 64 bit reloc that stores the 32 bit pc relative +- * +value in two words (with an imm instruction). No relocation is ++ * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ +- BFD_RELOC_MICROBLAZE_64_NONE, ++ BFD_RELOC_MICROBLAZE_64_PCREL, + +-/* This is a 64 bit reloc that stores the 32 bit pc relative ++/* This is a 64 bit reloc that stores the 32 bit relative + * +value in two words (with an imml instruction). No relocation is + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64, + + /* This is a 64 bit reloc that stores the 32 bit pc relative ++ * +value in two words (with an imm instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_64_NONE, ++ ++/* This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset */ + BFD_RELOC_MICROBLAZE_64_GOTPC, +diff --git a/bfd/libbfd.h b/bfd/libbfd.h +index 450653f..d87a183 100644 +--- a/bfd/libbfd.h ++++ b/bfd/libbfd.h +@@ -2903,14 +2903,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", + "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM", + "BFD_RELOC_MICROBLAZE_32_NONE", + "BFD_RELOC_MICROBLAZE_64_NONE", +- "BFD_RELOC_MICROBLAZE_64", + "BFD_RELOC_MICROBLAZE_64_GOTPC", +- "BFD_RELOC_MICROBLAZE_64_GPC", + "BFD_RELOC_MICROBLAZE_64_GOT", + "BFD_RELOC_MICROBLAZE_64_PLT", + "BFD_RELOC_MICROBLAZE_64_GOTOFF", + "BFD_RELOC_MICROBLAZE_32_GOTOFF", + "BFD_RELOC_MICROBLAZE_COPY", ++ "BFD_RELOC_MICROBLAZE_64", ++ "BFD_RELOC_MICROBLAZE_64_PCREL", + "BFD_RELOC_MICROBLAZE_64_TLS", + "BFD_RELOC_MICROBLAZE_64_TLSGD", + "BFD_RELOC_MICROBLAZE_64_TLSLD", +diff --git a/bfd/reloc.c b/bfd/reloc.c +index ccf29f5..861f2d4 100644 +--- a/bfd/reloc.c ++++ b/bfd/reloc.c +@@ -6804,12 +6804,6 @@ ENUMDOC + ENUM + BFD_RELOC_MICROBLAZE_64_NONE + ENUMDOC +- This is a 32 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64 +-ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). No relocation is + done here - only used for relaxing +@@ -6817,12 +6811,6 @@ ENUM + BFD_RELOC_MICROBLAZE_64_GOTPC + ENUMDOC + This is a 64 bit reloc that stores the 32 bit pc relative +- value in two words (with an imml instruction). No relocation is +- done here - only used for relaxing +-ENUM +- BFD_RELOC_MICROBLAZE_64_GPC +-ENUMDOC +- This is a 64 bit reloc that stores the 32 bit pc relative + value in two words (with an imm instruction). The relocation is + PC-relative GOT offset + ENUM +@@ -6906,6 +6894,20 @@ ENUMDOC + value in two words (with an imm instruction). The relocation is + relative offset from start of TEXT. + ++ This is a 64 bit reloc that stores 64-bit thread pointer relative offset ++ to two words (uses imml instruction). ++ENUM ++BFD_RELOC_MICROBLAZE_64, ++ENUMDOC ++ This is a 64 bit reloc that stores the 64 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing ++ENUM ++BFD_RELOC_MICROBLAZE_64_PCREL, ++ENUMDOC ++ This is a 32 bit reloc that stores the 32 bit pc relative ++ value in two words (with an imml instruction). No relocation is ++ done here - only used for relaxing + ENUM + BFD_RELOC_AARCH64_RELOC_START + ENUMDOC +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 3f90b7c..587a4d5 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -95,6 +95,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP"; + #define TEXT_OFFSET 17 + #define TEXT_PC_OFFSET 18 + #define DEFINED_64_OFFSET 19 ++#define DEFINED_64_PC_OFFSET 20 + + /* Initialize the relax table. */ + const relax_typeS md_relax_table[] = +@@ -119,7 +120,8 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ + // { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ +- { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 17: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 19: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; + + static struct hash_control * opcode_hash_control; /* Opcode mnemonics. */ +@@ -1180,33 +1182,6 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +-#if 0 //revisit +- else if (streq (name, "lli") || streq (name, "sli")) +- { +- temp = immed & 0xFFFFFFFFFFFF8000; +- if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imml"); +- return; +- } +- +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } +-#endif + else + { + temp = immed & 0xFFFF8000; +@@ -1958,8 +1933,8 @@ md_assemble (char * str) + + if (exp.X_op != O_constant) + { +- char *opc = NULL; +- //char *opc = str_microblaze_64; ++ //char *opc = NULL; ++ char *opc = str_microblaze_64; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -2221,13 +2196,19 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; ++ case DEFINED_64_PC_OFFSET: ++ fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, ++ fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL); ++ fragP->fr_fix += INST_WORD_SIZE * 2; ++ fragP->fr_var = 0; ++ break; + case DEFINED_64_OFFSET: + if (fragP->fr_symbol == GOT_symbol) + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC); ++ fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64); ++ fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2237,7 +2218,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, + fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC); + else + fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol, +- fragP->fr_offset, TRUE, BFD_RELOC_64); ++ fragP->fr_offset, FALSE, BFD_RELOC_64); + fragP->fr_fix += INST_WORD_SIZE * 2; + fragP->fr_var = 0; + break; +@@ -2457,14 +2438,17 @@ md_apply_fix (fixS * fixP, + } + } + break; ++ + case BFD_RELOC_64_PCREL: + case BFD_RELOC_64: + case BFD_RELOC_MICROBLAZE_64_TEXTREL: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + /* Add an imm instruction. First save the current instruction. */ + for (i = 0; i < INST_WORD_SIZE; i++) + buf[i + INST_WORD_SIZE] = buf[i]; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64 ++ || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + { + /* Generate the imm instruction. */ + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); +@@ -2477,6 +2461,10 @@ md_apply_fix (fixS * fixP, + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ fixP->fx_r_type = BFD_RELOC_64; ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) ++ fixP->fx_r_type = BFD_RELOC_64_PCREL; + } + else + { +@@ -2487,7 +2475,7 @@ md_apply_fix (fixS * fixP, + as_bad (_("unknown opcode \"%s\""), "imm"); + return; + } +- ++ + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK; +@@ -2534,7 +2522,7 @@ md_apply_fix (fixS * fixP, + opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); + if (opcode1 == NULL) + { +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) ++ if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) + as_bad (_("unknown opcode \"%s\""), "imml"); + else + as_bad (_("unknown opcode \"%s\""), "imm"); +@@ -2561,8 +2549,6 @@ md_apply_fix (fixS * fixP, + moves code around due to relaxing. */ + if (fixP->fx_r_type == BFD_RELOC_64_PCREL) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; +- if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) +- fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; + else +@@ -2613,33 +2599,24 @@ md_estimate_size_before_relax (fragS * fragP, + if(streq (fragP->fr_opcode, str_microblaze_64)) + { + /* Used as an absolute value. */ +- fragP->fr_subtype = DEFINED_64_OFFSET; ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; + /* Variable part does not change. */ +- fragP->fr_var = INST_WORD_SIZE; ++ fragP->fr_var = INST_WORD_SIZE*2; + } + else + { + fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ ++ /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } + } + else + { + fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ ++ /* Don't know now whether we need an imm instruction. */ + fragP->fr_var = INST_WORD_SIZE; + } + } +- #if 0 +- else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type && +- !S_IS_WEAK (fragP->fr_symbol)) +- { +- fragP->fr_subtype = DEFINED_PC_OFFSET; +- /* Don't know now whether we need an imm instruction. */ +- fragP->fr_var = INST_WORD_SIZE; +- } +-#endif + else if (S_IS_DEFINED (fragP->fr_symbol) + && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0)) + { +@@ -2669,6 +2646,13 @@ md_estimate_size_before_relax (fragS * fragP, + /* Variable part does not change. */ + fragP->fr_var = INST_WORD_SIZE*2; + } ++ else if (streq (fragP->fr_opcode, str_microblaze_64)) ++ { ++ /* Used as an absolute value. */ ++ fragP->fr_subtype = DEFINED_64_OFFSET; ++ /* Variable part does not change. */ ++ fragP->fr_var = INST_WORD_SIZE; ++ } + else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor)) + { + /* It is accessed using the small data read only anchor. */ +@@ -2743,6 +2727,7 @@ md_estimate_size_before_relax (fragS * fragP, + case TLSTPREL_OFFSET: + case TLSDTPREL_OFFSET: + case DEFINED_64_OFFSET: ++ case DEFINED_64_PC_OFFSET: + fragP->fr_var = INST_WORD_SIZE*2; + break; + case DEFINED_RO_SEGMENT: +@@ -2796,7 +2781,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED) + else + { + /* The case where we are going to resolve things... */ +- if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64) ++ if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) + return fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE; + else + return fixp->fx_where + fixp->fx_frag->fr_address; +@@ -2831,6 +2816,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: + case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: + case BFD_RELOC_MICROBLAZE_64_PLT: + case BFD_RELOC_MICROBLAZE_64_GOTOFF: diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch new file mode 100644 index 0000000000..55319ee2cf --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0019-Fixed-MB-x-relocation-issues.patch @@ -0,0 +1,373 @@ +From 616031595c692c2181c3b1ce8c08678b68b2fe4e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 28 Sep 2018 12:04:55 +0530 +Subject: [PATCH] -Fixed MB-x relocation issues -Added imml for required MB-x + instructions + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf64-microblaze.c | 68 ++++++++++++++++---- + gas/config/tc-microblaze.c | 152 ++++++++++++++++++++++++++++++++------------- + gas/tc.h | 2 +- + 3 files changed, 167 insertions(+), 55 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 56a45f2..54a2461 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1476,8 +1476,17 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation -= (input_section->output_section->vma + + input_section->output_offset + + offset + INST_WORD_SIZE); +- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, + contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + endian + INST_WORD_SIZE); + } +@@ -1567,11 +1576,28 @@ microblaze_elf_relocate_section (bfd *output_bfd, + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +- relocation -= (input_section->output_section->vma +- + input_section->output_offset +- + offset + INST_WORD_SIZE); +- bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ { ++ if (!input_section->output_section->vma && ++ !input_section->output_offset && !offset) ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset); ++ else ++ relocation -= (input_section->output_section->vma ++ + input_section->output_offset ++ + offset + INST_WORD_SIZE); ++ } ++ unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); ++ if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ { ++ insn &= ~0x00ffffff; ++ insn |= (relocation >> 16) & 0xffffff; ++ bfd_put_32 (input_bfd, insn, + contents + offset + endian); ++ } ++ else ++ bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff, ++ contents + offset + endian); + bfd_put_16 (input_bfd, relocation & 0xffff, + contents + offset + endian + INST_WORD_SIZE); + } +@@ -1690,9 +1716,19 @@ static void + microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + { + unsigned long instr = bfd_get_32 (abfd, bfd_addr); +- instr &= ~0x0000ffff; +- instr |= (val & 0x0000ffff); +- bfd_put_32 (abfd, instr, bfd_addr); ++ ++ if (instr == 0xb2000000 || instr == 0xb2ffffff) ++ { ++ instr &= ~0x00ffffff; ++ instr |= (val & 0xffffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } ++ else ++ { ++ instr &= ~0x0000ffff; ++ instr |= (val & 0x0000ffff); ++ bfd_put_32 (abfd, instr, bfd_addr); ++ } + } + + /* Read-modify-write into the bfd, an immediate value into appropriate fields of +@@ -1704,10 +1740,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + unsigned long instr_lo; + + instr_hi = bfd_get_32 (abfd, bfd_addr); +- instr_hi &= ~0x0000ffff; +- instr_hi |= ((val >> 16) & 0x0000ffff); +- bfd_put_32 (abfd, instr_hi, bfd_addr); +- ++ if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff) ++ { ++ instr_hi &= ~0x00ffffff; ++ instr_hi |= (val >> 16) & 0xffffff; ++ bfd_put_32 (abfd, instr_hi,bfd_addr); ++ } ++ else ++ { ++ instr_hi &= ~0x0000ffff; ++ instr_hi |= ((val >> 16) & 0x0000ffff); ++ bfd_put_32 (abfd, instr_hi, bfd_addr); ++ } + instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE); + instr_lo &= ~0x0000ffff; + instr_lo |= (val & 0x0000ffff); +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 587a4d5..fa437b6 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -392,7 +392,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED) + Integer arg to pass to the function. */ + /* If the pseudo-op is not found in this table, it searches in the obj-elf.c, + and then in the read.c table. */ +-const pseudo_typeS md_pseudo_table[] = ++pseudo_typeS md_pseudo_table[] = + { + {"lcomm", microblaze_s_lcomm, 1}, + {"data", microblaze_s_data, 0}, +@@ -401,7 +401,7 @@ const pseudo_typeS md_pseudo_table[] = + {"data32", cons, 4}, /* Same as word. */ + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ +- {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ ++ {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ + {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, +@@ -996,7 +996,7 @@ md_assemble (char * str) + unsigned reg2; + unsigned reg3; + unsigned isize; +- unsigned int immed, immed2, temp; ++ unsigned long immed, immed2, temp; + expressionS exp; + char name[20]; + long immedl; +@@ -1118,8 +1118,9 @@ md_assemble (char * str) + as_fatal (_("lmi pseudo instruction should not use a label in imm field")); + else if (streq (name, "smi")) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); +- +- if (reg2 == REG_ROSDP) ++ if(streq (name, "lli") || streq (name, "sli")) ++ opc = str_microblaze_64; ++ else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) + opc = str_microblaze_rw_anchor; +@@ -1182,31 +1183,55 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else +- { +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { ++ else if (streq (name, "lli") || streq (name, "sli")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { + /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); + if (opcode1 == NULL) + { +- as_bad (_("unknown opcode \"%s\""), "imm"); ++ as_bad (_("unknown opcode \"%s\""), "imml"); + return; + } +- + inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; + output[0] = INST_BYTE0 (inst1); + output[1] = INST_BYTE1 (inst1); + output[2] = INST_BYTE2 (inst1); + output[3] = INST_BYTE3 (inst1); + output = frag_more (isize); +- } +- inst |= (reg1 << RD_LOW) & RD_MASK; +- inst |= (reg2 << RA_LOW) & RA_MASK; +- inst |= (immed << IMM_LOW) & IMM_MASK; +- } ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } ++ ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (reg2 << RA_LOW) & RA_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_RD_R1_IMMS: +@@ -1832,12 +1857,20 @@ md_assemble (char * str) + case INST_TYPE_IMM: + if (streq (name, "imm")) + as_fatal (_("An IMM instruction should not be present in the .s file")); +- +- op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); ++ if (microblaze_arch_size == 64) ++ op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML); ++ else ++ op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM); + + if (exp.X_op != O_constant) + { +- char *opc = NULL; ++ char *opc; ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ opc = str_microblaze_64; ++ else ++ opc = NULL; + relax_substateT subtype; + + if (exp.X_md != 0) +@@ -1860,27 +1893,54 @@ md_assemble (char * str) + immed = exp.X_add_number; + } + ++ if (microblaze_arch_size == 64 && (streq (name, "breai") || ++ streq (name, "breaid") || ++ streq (name, "brai") || streq (name, "braid"))) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } + +- temp = immed & 0xFFFF8000; +- if ((temp != 0) && (temp != 0xFFFF8000)) +- { +- /* Needs an immediate inst. */ +- opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); +- if (opcode1 == NULL) +- { +- as_bad (_("unknown opcode \"%s\""), "imm"); +- return; ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); + } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { ++ temp = immed & 0xFFFF8000; ++ if ((temp != 0) && (temp != 0xFFFF8000)) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imm"); ++ return; ++ } + +- inst1 = opcode1->bit_sequence; +- inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; +- output[0] = INST_BYTE0 (inst1); +- output[1] = INST_BYTE1 (inst1); +- output[2] = INST_BYTE2 (inst1); +- output[3] = INST_BYTE3 (inst1); +- output = frag_more (isize); +- } +- inst |= (immed << IMM_LOW) & IMM_MASK; ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_NONE: +@@ -2460,7 +2520,7 @@ md_apply_fix (fixS * fixP, + + inst1 = opcode1->bit_sequence; + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) +- inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64) + fixP->fx_r_type = BFD_RELOC_64; + if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL) +@@ -2628,7 +2688,14 @@ md_estimate_size_before_relax (fragS * fragP, + } + else + { +- fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ if (fragP->fr_opcode != NULL) { ++ if (streq (fragP->fr_opcode, str_microblaze_64)) ++ fragP->fr_subtype = DEFINED_64_PC_OFFSET; ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; ++ } ++ else ++ fragP->fr_subtype = UNDEFINED_PC_OFFSET; + fragP->fr_var = INST_WORD_SIZE*2; + } + break; +@@ -2905,6 +2972,7 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED) + case OPTION_M64: + //if (arg != NULL && strcmp (arg, "64") == 0) + microblaze_arch_size = 64; ++ md_pseudo_table[7].poc_val = 8; + break; + default: + return 0; +diff --git a/gas/tc.h b/gas/tc.h +index 0a50a69..529a73b 100644 +--- a/gas/tc.h ++++ b/gas/tc.h +@@ -22,7 +22,7 @@ + /* In theory (mine, at least!) the machine dependent part of the assembler + should only have to include one file. This one. -- JF */ + +-extern const pseudo_typeS md_pseudo_table[]; ++extern pseudo_typeS md_pseudo_table[]; + + const char * md_atof (int, char *, int *); + int md_parse_option (int, const char *); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch new file mode 100644 index 0000000000..43a06d894e --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0020-Fixing-the-branch-related-issues.patch @@ -0,0 +1,25 @@ +From 05cac23e0cdb94705c87cf9d94ffe00e7cba53f6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sun, 30 Sep 2018 17:06:58 +0530 +Subject: [PATCH] Fixing the branch related issues + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf64-microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 54a2461..e9b3cf3 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2532,7 +2532,7 @@ microblaze_elf_check_relocs (bfd * abfd, + + /* PR15323, ref flags aren't set for references in the same + object. */ +- h->root.non_ir_ref = 1; ++ h->root.non_ir_ref_regular = 1; + } + + switch (r_type) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch new file mode 100644 index 0000000000..b3aebb7452 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0021-Fixed-address-computation-issues-with-64bit-address.patch @@ -0,0 +1,217 @@ +From 8b98898add56667d28b7d6242c86603bb2f5946e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 9 Oct 2018 10:14:22 +0530 +Subject: [PATCH] - Fixed address computation issues with 64bit address - Fixed + imml dissassamble issue + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/bfd-in2.h | 5 ++++ + bfd/elf64-microblaze.c | 14 ++++----- + gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++++++++++----- + opcodes/microblaze-dis.c | 2 +- + 4 files changed, 79 insertions(+), 16 deletions(-) + +diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h +index f74aac1..434b41c 100644 +--- a/bfd/bfd-in2.h ++++ b/bfd/bfd-in2.h +@@ -5882,6 +5882,11 @@ done here - only used for relaxing */ + * +done here - only used for relaxing */ + BFD_RELOC_MICROBLAZE_64, + ++/* This is a 64 bit reloc that stores the 32 bit relative ++ * +value in two words (with an imml instruction). No relocation is ++ * +done here - only used for relaxing */ ++ BFD_RELOC_MICROBLAZE_EA64, ++ + /* This is a 64 bit reloc that stores the 32 bit pc relative + * +value in two words (with an imm instruction). No relocation is + * +done here - only used for relaxing */ +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index e9b3cf3..40f10aa 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] = + 0, /* Rightshift. */ + 4, /* Size (0 = byte, 1 = short, 2 = long). */ + 64, /* Bitsize. */ +- TRUE, /* PC_relative. */ ++ FALSE, /* PC_relative. */ + 0, /* Bitpos. */ + complain_overflow_dont, /* Complain on overflow. */ + bfd_elf_generic_reloc,/* Special Function. */ + "R_MICROBLAZE_IMML_64", /* Name. */ + FALSE, /* Partial Inplace. */ + 0, /* Source Mask. */ +- 0x0000ffff, /* Dest Mask. */ +- TRUE), /* PC relative offset? */ ++ 0xffffffffffffff, /* Dest Mask. */ ++ FALSE), /* PC relative offset? */ + + /* A 64 bit relocation. Table entry not really used. */ + HOWTO (R_MICROBLAZE_64, /* Type. */ +@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_32: + microblaze_reloc = R_MICROBLAZE_32; + break; +- /* RVA is treated the same as 32 */ ++ /* RVA is treated the same as 64 */ + case BFD_RELOC_RVA: +- microblaze_reloc = R_MICROBLAZE_32; ++ microblaze_reloc = R_MICROBLAZE_IMML_64; + break; + case BFD_RELOC_32_PCREL: + microblaze_reloc = R_MICROBLAZE_32_PCREL; +@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + case BFD_RELOC_VTABLE_ENTRY: + microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY; + break; +- case BFD_RELOC_MICROBLAZE_64: ++ case BFD_RELOC_MICROBLAZE_EA64: + microblaze_reloc = R_MICROBLAZE_IMML_64; + break; + case BFD_RELOC_MICROBLAZE_64_GOTPC: +@@ -1969,7 +1969,7 @@ microblaze_elf_relax_section (bfd *abfd, + efix = calc_fixup (target_address, 0, sec); + + /* Validate the in-band val. */ +- val = bfd_get_32 (abfd, contents + irel->r_offset); ++ val = bfd_get_64 (abfd, contents + irel->r_offset); + if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) { + fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend); + } +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index fa437b6..46df32e 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -402,7 +402,6 @@ pseudo_typeS md_pseudo_table[] = + {"ent", s_func, 0}, /* Treat ent as function entry point. */ + {"end", microblaze_s_func, 1}, /* Treat end as function end point. */ + {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section. */ +- {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section. */ + {"weakext", microblaze_s_weakext, 0}, + {"rodata", microblaze_s_rdata, 0}, + {"sdata2", microblaze_s_rdata, 1}, +@@ -2482,15 +2481,71 @@ md_apply_fix (fixS * fixP, + /* Don't do anything if the symbol is not defined. */ + if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) + { ++ if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64)) ++ { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); ++ } ++ else ++ { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ else { ++ if (target_big_endian) ++ { ++ buf[0] |= ((val >> 24) & 0xff); ++ buf[1] |= ((val >> 16) & 0xff); ++ buf[2] |= ((val >> 8) & 0xff); ++ buf[3] |= (val & 0xff); ++ } ++ else ++ { ++ buf[3] |= ((val >> 24) & 0xff); ++ buf[2] |= ((val >> 16) & 0xff); ++ buf[1] |= ((val >> 8) & 0xff); ++ buf[0] |= (val & 0xff); ++ } ++ } ++ } ++ break; ++ ++ case BFD_RELOC_MICROBLAZE_EA64: ++ /* Don't do anything if the symbol is not defined. */ ++ if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy)) ++ { + if (target_big_endian) + { +- buf[0] |= ((val >> 24) & 0xff); +- buf[1] |= ((val >> 16) & 0xff); +- buf[2] |= ((val >> 8) & 0xff); +- buf[3] |= (val & 0xff); ++ buf[0] |= ((val >> 56) & 0xff); ++ buf[1] |= ((val >> 48) & 0xff); ++ buf[2] |= ((val >> 40) & 0xff); ++ buf[3] |= ((val >> 32) & 0xff); ++ buf[4] |= ((val >> 24) & 0xff); ++ buf[5] |= ((val >> 16) & 0xff); ++ buf[6] |= ((val >> 8) & 0xff); ++ buf[7] |= (val & 0xff); + } + else + { ++ buf[7] |= ((val >> 56) & 0xff); ++ buf[6] |= ((val >> 48) & 0xff); ++ buf[5] |= ((val >> 40) & 0xff); ++ buf[4] |= ((val >> 32) & 0xff); + buf[3] |= ((val >> 24) & 0xff); + buf[2] |= ((val >> 16) & 0xff); + buf[1] |= ((val >> 8) & 0xff); +@@ -2611,6 +2666,8 @@ md_apply_fix (fixS * fixP, + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE; + else if (fixP->fx_r_type == BFD_RELOC_32) + fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE; ++ else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64) ++ fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64; + else + fixP->fx_r_type = BFD_RELOC_NONE; + fixP->fx_addsy = section_symbol (absolute_section); +@@ -2882,6 +2939,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp) + case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM: + case BFD_RELOC_MICROBLAZE_64_GOTPC: + case BFD_RELOC_MICROBLAZE_64_GPC: ++ case BFD_RELOC_MICROBLAZE_EA64: + case BFD_RELOC_MICROBLAZE_64: + case BFD_RELOC_MICROBLAZE_64_PCREL: + case BFD_RELOC_MICROBLAZE_64_GOT: +@@ -3027,10 +3085,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- if (microblaze_arch_size == 64) ++ /*if (microblaze_arch_size == 64) + r = BFD_RELOC_32; +- else +- r = BFD_RELOC_64; ++ else*/ ++ r = BFD_RELOC_MICROBLAZE_EA64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); +diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c +index 20ea6a8..f679a43 100644 +--- a/opcodes/microblaze-dis.c ++++ b/opcodes/microblaze-dis.c +@@ -61,7 +61,7 @@ get_field_imml (long instr) + { + char tmpstr[25]; + +- sprintf (tmpstr, "%d", (short)((instr & IMML_MASK) >> IMM_LOW)); ++ sprintf (tmpstr, "%d", (int)((instr & IMML_MASK) >> IMM_LOW)); + return (strdup (tmpstr)); + } + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch new file mode 100644 index 0000000000..aec793d9c3 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0022-Adding-new-relocation-to-support-64bit-rodata.patch @@ -0,0 +1,166 @@ +From 3eb0c068ad5a698007341b32c82d9e7ac6cabc49 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sat, 13 Oct 2018 21:17:01 +0530 +Subject: [PATCH] Adding new relocation to support 64bit rodata + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf64-microblaze.c | 11 +++++++++-- + gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++++++++++---- + 2 files changed, 54 insertions(+), 6 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 40f10aa..4d9b906 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1461,6 +1461,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + case (int) R_MICROBLAZE_64_PCREL : + case (int) R_MICROBLAZE_64: + case (int) R_MICROBLAZE_32: ++ case (int) R_MICROBLAZE_IMML_64: + { + /* r_symndx will be STN_UNDEF (zero) only for relocs against symbols + from removed linkonce sections, or sections discarded by +@@ -1470,6 +1471,8 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation += addend; + if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64) + bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +@@ -1547,7 +1550,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + } + else + { +- if (r_type == R_MICROBLAZE_32) ++ if (r_type == R_MICROBLAZE_32 || r_type == R_MICROBLAZE_IMML_64) + { + outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL); + outrel.r_addend = relocation + addend; +@@ -1573,6 +1576,8 @@ microblaze_elf_relocate_section (bfd *output_bfd, + relocation += addend; + if (r_type == R_MICROBLAZE_32) + bfd_put_32 (input_bfd, relocation, contents + offset); ++ else if (r_type == R_MICROBLAZE_IMML_64) ++ bfd_put_64 (input_bfd, relocation, contents + offset + endian); + else + { + if (r_type == R_MICROBLAZE_64_PCREL) +@@ -2085,7 +2090,8 @@ microblaze_elf_relax_section (bfd *abfd, + microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset, + irelscan->r_addend); + } +- if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ++ if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32 ++ || ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_IMML_64) + { + isym = isymbuf + ELF64_R_SYM (irelscan->r_info); + +@@ -2591,6 +2597,7 @@ microblaze_elf_check_relocs (bfd * abfd, + case R_MICROBLAZE_64: + case R_MICROBLAZE_64_PCREL: + case R_MICROBLAZE_32: ++ case R_MICROBLAZE_IMML_64: + { + if (h != NULL && !bfd_link_pic (info)) + { +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index 46df32e..c6d2e4c 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -1119,6 +1119,13 @@ md_assemble (char * str) + as_fatal (_("smi pseudo instruction should not use a label in imm field")); + if(streq (name, "lli") || streq (name, "sli")) + opc = str_microblaze_64; ++ else if ((microblaze_arch_size == 64) && ((streq (name, "lbui") ++ || streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else if (reg2 == REG_ROSDP) + opc = str_microblaze_ro_anchor; + else if (reg2 == REG_RWSDP) +@@ -1182,7 +1189,10 @@ md_assemble (char * str) + inst |= (immed << IMM_LOW) & IMM_MASK; + } + } +- else if (streq (name, "lli") || streq (name, "sli")) ++ else if (streq (name, "lli") || streq (name, "sli") || ((microblaze_arch_size == 64) ++ && ((streq (name, "lbui")) || streq (name, "lhui") ++ || streq (name, "lwi") || streq (name, "sbi") ++ || streq (name, "shi") || streq (name, "swi")))) + { + temp = immed & 0xFFFFFF8000; + if (temp != 0 && temp != 0xFFFFFF8000) +@@ -1794,6 +1804,11 @@ md_assemble (char * str) + + if (exp.X_md != 0) + subtype = get_imm_otype(exp.X_md); ++ else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ opc = str_microblaze_64; ++ subtype = opcode->inst_offset_type; ++ } + else + subtype = opcode->inst_offset_type; + +@@ -1811,6 +1826,31 @@ md_assemble (char * str) + output = frag_more (isize); + immed = exp.X_add_number; + } ++ if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai")) ++ { ++ temp = immed & 0xFFFFFF8000; ++ if (temp != 0 && temp != 0xFFFFFF8000) ++ { ++ /* Needs an immediate inst. */ ++ opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml"); ++ if (opcode1 == NULL) ++ { ++ as_bad (_("unknown opcode \"%s\""), "imml"); ++ return; ++ } ++ inst1 = opcode1->bit_sequence; ++ inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK; ++ output[0] = INST_BYTE0 (inst1); ++ output[1] = INST_BYTE1 (inst1); ++ output[2] = INST_BYTE2 (inst1); ++ output[3] = INST_BYTE3 (inst1); ++ output = frag_more (isize); ++ } ++ inst |= (reg1 << RD_LOW) & RD_MASK; ++ inst |= (immed << IMM_LOW) & IMM_MASK; ++ } ++ else ++ { + + temp = immed & 0xFFFF8000; + if ((temp != 0) && (temp != 0xFFFF8000)) +@@ -1834,6 +1874,7 @@ md_assemble (char * str) + + inst |= (reg1 << RD_LOW) & RD_MASK; + inst |= (immed << IMM_LOW) & IMM_MASK; ++ } + break; + + case INST_TYPE_R2: +@@ -3085,10 +3126,10 @@ cons_fix_new_microblaze (fragS * frag, + r = BFD_RELOC_32; + break; + case 8: +- /*if (microblaze_arch_size == 64) +- r = BFD_RELOC_32; +- else*/ ++ if (microblaze_arch_size == 64) + r = BFD_RELOC_MICROBLAZE_EA64; ++ else ++ r = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %u"), size); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch new file mode 100644 index 0000000000..cd54cae46c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0023-fixing-the-.bss-relocation-issue.patch @@ -0,0 +1,76 @@ +From 52f6c56353aad424dfdaf713e0192f8fc9c874f4 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 24 Oct 2018 12:34:37 +0530 +Subject: [PATCH] fixing the .bss relocation issue + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf64-microblaze.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 4d9b906..184b7d5 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -1480,7 +1480,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + + input_section->output_offset + + offset + INST_WORD_SIZE); + unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); +- if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ if ((insn & 0xff000000) == 0xb2000000) + { + insn &= ~0x00ffffff; + insn |= (relocation >> 16) & 0xffffff; +@@ -1593,7 +1593,7 @@ microblaze_elf_relocate_section (bfd *output_bfd, + + offset + INST_WORD_SIZE); + } + unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian); +- if (insn == 0xb2000000 || insn == 0xb2ffffff) ++ if ((insn & 0xff000000) == 0xb2000000) + { + insn &= ~0x00ffffff; + insn |= (relocation >> 16) & 0xffffff; +@@ -1722,7 +1722,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + { + unsigned long instr = bfd_get_32 (abfd, bfd_addr); + +- if (instr == 0xb2000000 || instr == 0xb2ffffff) ++ if ((instr & 0xff000000) == 0xb2000000) + { + instr &= ~0x00ffffff; + instr |= (val & 0xffffff); +@@ -1745,7 +1745,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val) + unsigned long instr_lo; + + instr_hi = bfd_get_32 (abfd, bfd_addr); +- if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff) ++ if ((instr_hi & 0xff000000) == 0xb2000000) + { + instr_hi &= ~0x00ffffff; + instr_hi |= (val >> 16) & 0xffffff; +@@ -2238,7 +2238,10 @@ microblaze_elf_relax_section (bfd *abfd, + unsigned long instr_lo = bfd_get_32 (abfd, ocontents + + irelscan->r_offset + + INST_WORD_SIZE); +- immediate = (instr_hi & 0x0000ffff) << 16; ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; + immediate |= (instr_lo & 0x0000ffff); + offset = calc_fixup (irelscan->r_addend, 0, sec); + immediate -= offset; +@@ -2282,7 +2285,10 @@ microblaze_elf_relax_section (bfd *abfd, + unsigned long instr_lo = bfd_get_32 (abfd, ocontents + + irelscan->r_offset + + INST_WORD_SIZE); +- immediate = (instr_hi & 0x0000ffff) << 16; ++ if ((instr_hi & 0xff000000) == 0xb2000000) ++ immediate = (instr_hi & 0x00ffffff) << 24; ++ else ++ immediate = (instr_hi & 0x0000ffff) << 16; + immediate |= (instr_lo & 0x0000ffff); + target_address = immediate; + offset = calc_fixup (target_address, 0, sec); diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch new file mode 100644 index 0000000000..a4f8257d2a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0024-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch @@ -0,0 +1,44 @@ +From ed3e6fad3e2a626fc987e9c7477f51d03d2b4512 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 28 Nov 2018 14:00:29 +0530 +Subject: [PATCH] Fixed the bug in the R_MICROBLAZE_64_NONE relocation. It was + adjusting only lower 16bits. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf32-microblaze.c | 4 ++-- + bfd/elf64-microblaze.c | 4 ++-- + 2 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 035e71f..2d8c062 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -2022,8 +2022,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index 184b7d5..ef6a870 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2017,8 +2017,8 @@ microblaze_elf_relax_section (bfd *abfd, + sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec); + efix = calc_fixup (target_address, 0, sec); + irel->r_addend -= (efix - sfix); +- microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset +- + INST_WORD_SIZE, irel->r_addend); ++ microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset, ++ irel->r_addend); + } + break; + } diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch new file mode 100644 index 0000000000..fec19b6b6c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0025-Patch-MicroBlaze-fixed-Build-issue-which-are-due-to-.patch @@ -0,0 +1,67 @@ +From b8bd638f71649980e114548d8eeecba34683af42 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Sun, 2 Dec 2018 14:49:14 +0530 +Subject: [PATCH] fixed Build issue which are due to conflicts in patches. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf32-microblaze.c | 1 + + bfd/elf64-microblaze.c | 12 ++++++------ + gas/config/tc-microblaze.c | 4 ++-- + 3 files changed, 9 insertions(+), 8 deletions(-) + +diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c +index 2d8c062..6a795c5 100644 +--- a/bfd/elf32-microblaze.c ++++ b/bfd/elf32-microblaze.c +@@ -1996,6 +1996,7 @@ microblaze_elf_relax_section (bfd *abfd, + /* This was a PC-relative instruction that was + completely resolved. */ + int sfix, efix; ++ unsigned int val; + bfd_vma target_address; + target_address = irel->r_addend + irel->r_offset; + sfix = calc_fixup (irel->r_offset, 0, sec); +diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c +index ef6a870..bed534e 100644 +--- a/bfd/elf64-microblaze.c ++++ b/bfd/elf64-microblaze.c +@@ -2854,14 +2854,14 @@ microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ +- if (h->u.weakdef != NULL) ++ if (h->is_weakalias) + { +- BFD_ASSERT (h->u.weakdef->root.type == bfd_link_hash_defined +- || h->u.weakdef->root.type == bfd_link_hash_defweak); +- h->root.u.def.section = h->u.weakdef->root.u.def.section; +- h->root.u.def.value = h->u.weakdef->root.u.def.value; ++ struct elf_link_hash_entry *def = weakdef (h); ++ BFD_ASSERT (def->root.type == bfd_link_hash_defined); ++ h->root.u.def.section = def->root.u.def.section; ++ h->root.u.def.value = def->root.u.def.value; + return TRUE; +- } ++ } + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index c6d2e4c..b3e49f0 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -118,9 +118,9 @@ const relax_typeS md_relax_table[] = + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 15: TLSGOTTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 16: TLSTPREL_OFFSET. */ + { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 17: TEXT_OFFSET. */ +- { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 18: TEXT_PC_OFFSET. */ ++ { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }, /* 18: TEXT_PC_OFFSET. */ + // { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 } /* 16: TLSTPREL_OFFSET. */ +- { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 } /* 19: DEFINED_64_OFFSET. */ ++ { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }, /* 19: DEFINED_64_OFFSET. */ + { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 } /* 20: DEFINED_64_PC_OFFSET. */ + }; + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch new file mode 100644 index 0000000000..cd6965d70e --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0026-Patch-Microblaze-changes-of-PR22458-failure-to-choos.patch @@ -0,0 +1,31 @@ +From cbe98e5a0cbc2337bf25d6b3f9dabcae38b95952 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 26 Feb 2019 17:31:41 +0530 +Subject: [PATCH] changes of "PR22458, failure to choose a matching ELF target" + is causing "Multiple Prevailing definition errors",added check for best_match + elf. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/format.c | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/bfd/format.c b/bfd/format.c +index 97a9229..3a74cc4 100644 +--- a/bfd/format.c ++++ b/bfd/format.c +@@ -292,7 +292,12 @@ bfd_check_format_matches (bfd *abfd, bfd_format format, char ***matching) + + /* Don't check the default target twice. */ + if (*target == &binary_vec ++#if !BFD_SUPPORTS_PLUGINS + || (!abfd->target_defaulted && *target == save_targ)) ++#else ++ || (!abfd->target_defaulted && *target == save_targ) ++ || (*target)->match_priority > best_match) ++#endif + continue; + + /* If we already tried a match, the bfd is modified and may diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch new file mode 100644 index 0000000000..f293f5cf6f --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0029-Patch-Microblaze-Binutils-security-check-is-causing-.patch @@ -0,0 +1,33 @@ +From b1e425aed65150d7ce9ddb119f4b94969fe4043e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 11 Mar 2019 14:23:58 +0530 +Subject: [PATCH] Binutils security check is causing build error for windows + builds.commenting for now. + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + bfd/elf-attrs.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c +index bfe135e..feb5cb3 100644 +--- a/bfd/elf-attrs.c ++++ b/bfd/elf-attrs.c +@@ -440,6 +440,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr) + /* PR 17512: file: 2844a11d. */ + if (hdr->sh_size == 0) + return; ++ #if 0 + if (hdr->sh_size > bfd_get_file_size (abfd)) + { + /* xgettext:c-format */ +@@ -448,6 +449,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr) + bfd_set_error (bfd_error_invalid_operation); + return; + } ++ #endif + + contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1); + if (!contents) diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 0000000000..7e3accad02 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0030-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,57 @@ +From 1eec84c155aeaeead673310f83293853f01b578d Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 29 Nov 2018 17:59:25 +0530 +Subject: [PATCH] fixing the long & long long mingw toolchain issue + +Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + gas/config/tc-microblaze.c | 10 +++++----- + opcodes/microblaze-opc.h | 4 ++-- + 2 files changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c +index b3e49f0..5b506d3 100644 +--- a/gas/config/tc-microblaze.c ++++ b/gas/config/tc-microblaze.c +@@ -783,7 +783,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max) + } + + static char * +-parse_imml (char * s, expressionS * e, long min, long max) ++parse_imml (char * s, expressionS * e, long long min, long long max) + { + char *new_pointer; + char *atp; +@@ -834,11 +834,11 @@ parse_imml (char * s, expressionS * e, long min, long max) + ; /* An error message has already been emitted. */ + else if ((e->X_op != O_constant && e->X_op != O_symbol) ) + as_fatal (_("operand must be a constant or a label")); +- else if ((e->X_op == O_constant) && ((long) e->X_add_number < min +- || (long) e->X_add_number > max)) ++ else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min ++ || (long long) e->X_add_number > max)) + { +- as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"), +- min, max, (long) e->X_add_number); ++ as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"), ++ min, max, (long long) e->X_add_number); + } + + if (atp) +diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h +index 824afc0..d59ee0a 100644 +--- a/opcodes/microblaze-opc.h ++++ b/opcodes/microblaze-opc.h +@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr"; + #define MIN_IMM6_WIDTH ((int) 0x00000001) + #define MAX_IMM6_WIDTH ((int) 0x00000040) + +-#define MIN_IMML ((long) 0xffffff8000000000L) +-#define MAX_IMML ((long) 0x0000007fffffffffL) ++#define MIN_IMML ((long long) 0xffffff8000000000L) ++#define MAX_IMML ((long long) 0x0000007fffffffffL) + + #endif /* MICROBLAZE_OPC */ + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch new file mode 100644 index 0000000000..8c54f761ee --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/binutils/binutils-2.32/0031-fixing-the-_STACK_SIZE-issue-with-the-flto-flag.patch @@ -0,0 +1,55 @@ +From e28b33db95e6b71afe2eaca9d7090b3bfc20f08e Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Wed, 20 Mar 2019 11:42:07 +0530 +Subject: [PATCH] fixing the _STACK_SIZE issue with the flto flag + +Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> + +--- + ld/scripttempl/elfmicroblaze.sc | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/ld/scripttempl/elfmicroblaze.sc b/ld/scripttempl/elfmicroblaze.sc +index 30b9c28..6be0f4e 100644 +--- a/ld/scripttempl/elfmicroblaze.sc ++++ b/ld/scripttempl/elfmicroblaze.sc +@@ -63,9 +63,9 @@ ${RELOCATING+${LIB_SEARCH_DIRS}} + + ${RELOCATING+ENTRY (${ENTRY})} + +-${RELOCATING+_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50; +-_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0; +-_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;} ++${RELOCATING+_DEF_TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x50; ++_DEF_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x0; ++_DEF_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x400;} + + SECTIONS + { +@@ -75,7 +75,7 @@ SECTIONS + .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0 + .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0 + +- ${RELOCATING+. = _TEXT_START_ADDR;} ++ ${RELOCATING+. = _DEF_TEXT_START_ADDR;} + + ${RELOCATING+ _ftext = .;} + .text : { +@@ -207,7 +207,7 @@ SECTIONS + .heap : { + ${RELOCATING+ _heap = .;} + ${RELOCATING+ _heap_start = .;} +- ${RELOCATING+ . += _HEAP_SIZE;} ++ ${RELOCATING+ . += _DEF_HEAP_SIZE;} + ${RELOCATING+ _heap_end = .;} + } + +@@ -215,7 +215,7 @@ SECTIONS + + .stack : { + ${RELOCATING+ _stack_end = .;} +- ${RELOCATING+ . += _STACK_SIZE;} ++ ${RELOCATING+ . += _DEF_STACK_SIZE;} + ${RELOCATING+ . = ALIGN(. != 0 ? 8 : 1);} + ${RELOCATING+ _stack = .;} + ${RELOCATING+ _end = .;} diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch deleted file mode 100644 index 93af6514b7..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0001-Revert.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 12cd383fbef719cc1a84cc80ff171073409a8557 Mon Sep 17 00:00:00 2001 -From: eager <eager@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Sat, 27 May 2017 18:29:40 +0000 -Subject: [PATCH] Revert: 2016-01-21 Ajit Agarwal - <ajitkum@xilinx.com> - - See https://gcc.gnu.org/ml/gcc/2017-05/msg00221.html. - - * config/microblaze/microblaze.h - (FIXED_REGISTERS): Update in macro. - (CALL_USED_REGISTERS): Update in macro. - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@248540 138bc75d-0d04-0410-961f-82ee72b054a4 -Upstream-Status: Backport [from post gcc-7] ---- - gcc/config/microblaze/microblaze.h | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 66e4ef5c3d..2c9ece1d6c 100644 ---- a/gcc/config/microblaze/microblaze.h -+++ b/gcc/config/microblaze/microblaze.h -@@ -269,14 +269,14 @@ extern enum pipeline_type microblaze_pipe; - #define FIXED_REGISTERS \ - { \ - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ -- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - - #define CALL_USED_REGISTERS \ - { \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - #define GP_REG_FIRST 0 --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch deleted file mode 100644 index 42bfd3c146..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0003-PR-target-83013.patch +++ /dev/null @@ -1,32 +0,0 @@ -From f17cdebf4e0defaefce927176ddeb9717de073d2 Mon Sep 17 00:00:00 2001 -From: law <law@138bc75d-0d04-0410-961f-82ee72b054a4> -Date: Mon, 15 Jan 2018 06:02:19 +0000 -Subject: [PATCH] PR target/83013 - - * config/microblaze/microblaze.c (microblaze_asm_output_ident): - Use .pushsection/.popsection. - -git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@256681 138bc75d-0d04-0410-961f-82ee72b054a4 -Upstream-Status: Backport [backport from trunk pre-release v8] ---- - gcc/config/microblaze/microblaze.c | 4 +++- - 1 file changed, 3 insertions(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index d0f86fd460..a98aca1235 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3371,7 +3371,9 @@ microblaze_asm_output_ident (const char *string) - else - section_asm_op = READONLY_DATA_SECTION_ASM_OP; - -- buf = ACONCAT ((section_asm_op, "\n\t.ascii \"", string, "\\0\"\n", NULL)); -+ buf = ACONCAT (("\t.pushsection", section_asm_op, -+ "\n\t.ascii \"", string, "\\0\"\n", -+ "\t.popsection\n", NULL)); - symtab->finalize_toplevel_asm (build_string (strlen (buf), buf)); - } - --- -2.15.1 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch deleted file mode 100644 index c0a427eac4..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch +++ /dev/null @@ -1,36 +0,0 @@ -From ab2cb6320138c173b20fee8ce6e8d4afa4696384 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:16 -0700 -Subject: [PATCH] dejagnu static testing on qemu, suppress warnings - -For dejagnu static testing on qemu, suppress warnings about multiple -definitions from the test function and libc in line with method used by -powerpc. Dynamic linking and using a qemu binary which understands -sysroot resolves all test failures with builtins - -Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ++++ - 1 file changed, 4 insertions(+) - -diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -index ba16b09c41..ada149912b 100644 ---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp -@@ -48,6 +48,10 @@ if { [istarget *-*-eabi*] - lappend additional_flags "-Wl,--allow-multiple-definition" - } - -+if [istarget "microblaze*-*-linux*"] { -+ lappend additional_flags "-Wl,-zmuldefs" -+} -+ - foreach src [lsort [find $srcdir/$subdir *.c]] { - if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { - c-torture-execute [list $src \ --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch deleted file mode 100644 index 464f59e3a3..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 1a9dcdb578452ecd53e0aec65fe6279233218778 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:26 -0700 -Subject: [PATCH] Fix the Microblaze crash with msmall-divides flag - -Fix the Microblaze crash with msmall-divides flag Compiler is crashing -when we use msmall-divides and mxl-barrel-shift flag. This is because -when use above flags microblaze_expand_divide function will be called -for division operation. In microblaze_expand_divide function we are -using sub_reg but MicroBlaze doesn't have subreg register due to this -compiler was crashing. Changed the logic to avoid sub_reg call - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index bba6983b65..15080db539 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3527,8 +3527,7 @@ microblaze_expand_divide (rtx operands[]) - mem_rtx = gen_rtx_MEM (QImode, - gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); - -- insn = emit_insn (gen_movqi (regqi, mem_rtx)); -- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); -+ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); - JUMP_LABEL (jump) = div_end_label; - LABEL_NUSES (div_end_label) = 1; --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch deleted file mode 100644 index 4041e11fb8..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 25b161dd222311cca0e6ab46b7f3be444bd4bbe8 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:32 -0700 -Subject: [PATCH] Disable fivopts by default Turn off ivopts by default. - Interferes with cse. - -Changelog - -2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com> - - * gcc/common/config/microblaze/microblaze-common.c - (microblaze_option_optimization_table): Disable fivopts by default. - -Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> -Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/common/config/microblaze/microblaze-common.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c -index 4975663305..8ddc4c3cbe 100644 ---- a/gcc/common/config/microblaze/microblaze-common.c -+++ b/gcc/common/config/microblaze/microblaze-common.c -@@ -27,6 +27,8 @@ - /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ - static const struct default_options microblaze_option_optimization_table[] = - { -+ /* Turn off ivopts by default. It messes up cse. */ -+ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, - { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, - { OPT_LEVELS_NONE, 0, NULL, 0 } - }; --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch deleted file mode 100644 index 00e79b93fe..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0020-Modified-MicroBlaze-trap-instruction.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1b9bd76840fc1e67770a23c58bf18a24a25eb2b9 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:36 -0700 -Subject: [PATCH] Modified MicroBlaze trap instruction - -Modified trap instruction The instruction was wrongly written to brki -r0,-1 it should be bri r0. Modified with the correct instruction - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index abbe97c15f..a3954a24b6 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2343,7 +2343,7 @@ - (define_insn "trap" - [(trap_if (const_int 1) (const_int 0))] - "" -- "brki\tr0,-1" -+ "bri\t0" - [(set_attr "type" "trap")] - ) - --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch deleted file mode 100644 index 6de1702433..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0022-Inline-Expansion-of-fsqrt-builtin.patch +++ /dev/null @@ -1,64 +0,0 @@ -From cf85f09a0fade1e7827828a3dc9a526c212f3be7 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:39 -0700 -Subject: [PATCH] Inline Expansion of fsqrt builtin - -Inline Expansion of fsqrt builtin. The changes are made in the patch for -the inline expansion of the fsqrt builtin with fqrt instruction. The -sqrt math function takes double as argument and return double as -argument. The pattern is selected while expanding the unary op through -expand_unop which passes DFmode and the DFmode pattern was not there -returning zero. Thus the sqrt math function is not inlined and expanded. -The pattern with DFmode argument is added. Also the source and -destination argument is not same the DF through two different -consecutive registers with lower 32 bit is the argument passed to sqrt -and the higher 32 bit is zero. If the source and destinations are -different the DFmode 64 bits registers is not set properly giving the -problem in runtime. Such changes are taken care in the implementation of -the pattern for DFmode for inline expansion of the sqrt. - -ChangeLog: - -2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> - Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * config/microblaze/microblaze.md (sqrtdf2): New - pattern. - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index a3954a24b6..13f8803428 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -449,6 +449,20 @@ - (set_attr "mode" "SF") - (set_attr "length" "4")]) - -+(define_insn "sqrtdf2" -+ [(set (match_operand:DF 0 "register_operand" "=d") -+ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] -+ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" -+ { -+ if (REGNO (operands[0]) == REGNO (operands[1])) -+ return "fsqrt\t%0,%1"; -+ else -+ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; -+ } -+ [(set_attr "type" "fsqrt") -+ (set_attr "mode" "SF") -+ (set_attr "length" "4")]) -+ - (define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (match_operand:SF 1 "register_operand" "d")))] --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch deleted file mode 100644 index ff8e610750..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch +++ /dev/null @@ -1,72 +0,0 @@ -From fabd23a354496701b4a9ebf6931485b0d61c7bbe Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:45 -0700 -Subject: [PATCH] MicroBlaze correct the const high double immediate value - -With this patch the loading of the DI mode immediate values will be -using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE -functions, as CONST_DOUBLE_HIGH was returning the sign extension value -even of the unsigned long long constants also - -ChangeLog: - -2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE & - REAL_VALUE_TO_TARGET_DOUBLE - * long.c (new): Added new testcase - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 6 ++++-- - gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++ - 2 files changed, 14 insertions(+), 2 deletions(-) - create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index e7697bf30d..96bf6e1cab 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -2493,14 +2493,16 @@ print_operand (FILE * file, rtx op, int letter) - else if (letter == 'h' || letter == 'j') - { - long val[2]; -+ long l[2]; - if (code == CONST_DOUBLE) - { - if (GET_MODE (op) == DFmode) - REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); - else - { -- val[0] = CONST_DOUBLE_HIGH (op); -- val[1] = CONST_DOUBLE_LOW (op); -+ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); -+ val[1] = l[WORDS_BIG_ENDIAN == 0]; -+ val[0] = l[WORDS_BIG_ENDIAN != 0]; - } - } - else if (code == CONST_INT) -diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c -new file mode 100644 -index 0000000000..4d4518619d ---- /dev/null -+++ b/gcc/testsuite/gcc.target/microblaze/long.c -@@ -0,0 +1,10 @@ -+/* { dg-options "-O0" } */ -+#define BASEADDR 0xF0000000ULL -+int main () -+{ -+ unsigned long long start; -+ start = (unsigned long long) BASEADDR; -+ return 0; -+} -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ -+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch deleted file mode 100644 index 7ea28ee806..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0026-Fix-internal-compiler-error-with-msmall-divides.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 2149d85f1f7375dd97bf961b2bdb693d6d931c13 Mon Sep 17 00:00:00 2001 -From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:46 -0700 -Subject: [PATCH] Fix internal compiler error with msmall-divides - -This patch will fix the internal error microblaze_expand_divide function -which comes because of rtx PLUS where the mem_rtx is of type SI and the -operand is of type QImode. This patch modifies the mem_rtx as QImode and -Plus as QImode to fix the error. - -ChangeLog: - -2016-02-23 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.c (microblaze_expand_divide): Update - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 96bf6e1cab..a41121264e 100644 ---- a/gcc/config/microblaze/microblaze.c -+++ b/gcc/config/microblaze/microblaze.c -@@ -3719,7 +3719,7 @@ microblaze_expand_divide (rtx operands[]) - emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); - emit_insn (gen_addsi3 (regt1, regt1, operands[2])); - mem_rtx = gen_rtx_MEM (QImode, -- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); -+ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); - - insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); - jump = emit_jump_insn_after (gen_jump (div_end_label), insn); --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch deleted file mode 100644 index eaae566794..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch +++ /dev/null @@ -1,51 +0,0 @@ -From e2a7a582945d24ede55393462a3360f377f45478 Mon Sep 17 00:00:00 2001 -From: Nathan Rossi <nathan@nathanrossi.com> -Date: Sun, 5 Nov 2017 23:03:54 +1000 -Subject: [PATCH] MicroBlaze fix signed bit fields with bit field instructions - -The 'extv' definition is expected to sign extended the result based on -the width of the bit field. - - https://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html#index-extvm-instruction-pattern - -The MicroBlaze 'bsefi' instruction does not sign extended, it zero -extends. There is no option for the instruction to sign extended the -result and no simple instruction or expression to implement a variant -length sign extend (only sext8/sext16 instructions exist). - -As such these definitions needs to be changed to the zero extended -variant of 'extv' which is 'extzv'. This change updates the existing -definitions to allow for signed bit fields to function correctly and be -sign extended. - -Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Pending ---- - gcc/config/microblaze/microblaze.md | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index ef53c3069e..b52be42d6e 100644 ---- a/gcc/config/microblaze/microblaze.md -+++ b/gcc/config/microblaze/microblaze.md -@@ -2476,7 +2476,7 @@ - DONE; - }") - --(define_expand "extvsi" -+(define_expand "extzvsi" - [(set (match_operand:SI 0 "register_operand" "r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "I") -@@ -2485,7 +2485,7 @@ - "" - ) - --(define_insn "extv_32" -+(define_insn "extzv_32" - [(set (match_operand:SI 0 "register_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "immediate_operand" "I") --- -2.14.2 - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch new file mode 100644 index 0000000000..5d29531d2c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch @@ -0,0 +1,35 @@ +From 7fbf19ba660c72a1d4817780cad5c4ae52cbe0b5 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 13:13:57 +0530 +Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic + Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> + +Conflicts: + + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index 9f0b24a..1cb4f97 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + ++<<<<<<< HEAD ++======= ++if [istarget "microblaze*-*-linux*"] { ++ lappend additional_flags "-Wl,-zmuldefs" ++ lappend additional_flags "-fPIC" ++} ++ ++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch new file mode 100644 index 0000000000..503b1ecf98 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch @@ -0,0 +1,31 @@ +From 4b675eeabceea22ec51abfa7c37e11a631e58659 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 14:31:10 +0530 +Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This + particular testcase fails with a timeout. Instead, fail it at compile-time + for microblaze. This speeds up the testsuite without removing it from the + FAIL reports. + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +--- + gcc/testsuite/g++.dg/opt/memcpy1.C | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/testsuite/g++.dg/opt/memcpy1.C b/gcc/testsuite/g++.dg/opt/memcpy1.C +index 66411cd..d951fee 100644 +--- a/gcc/testsuite/g++.dg/opt/memcpy1.C ++++ b/gcc/testsuite/g++.dg/opt/memcpy1.C +@@ -4,6 +4,10 @@ + // { dg-do compile } + // { dg-options "-O" } + ++#if defined (__MICROBLAZE__) ++#error "too slow on mb. Investigate." ++#endif ++ + typedef unsigned char uint8_t; + typedef uint8_t uint8; + __extension__ typedef __SIZE_TYPE__ size_t; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch new file mode 100644 index 0000000000..3905849688 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch @@ -0,0 +1,116 @@ +From 03d4d7335be2b2f72c199ab5177685b6dfd1a9d6 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 15:28:38 +0530 +Subject: [PATCH 03/54] [LOCAL]: Testsuite - explicitly add -fivopts for tests + that depend on it (test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt + exist in 4.6 branch) + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> +--- + gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C | 2 +- + gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-2.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-4.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/loop-5.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/pr19590.c | 2 +- + gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +- + 8 files changed, 8 insertions(+), 8 deletions(-) + +diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C +index 438db88..ede883e 100644 +--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C ++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C +@@ -1,5 +1,5 @@ + /* { dg-do compile { target { i?86-*-* x86_64-*-* } } } */ +-/* { dg-options "-O2 -fdump-tree-ivopts-details" } */ ++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */ + + void test (int *b, int *e, int stride) + { +diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C +index 07ff1b7..a09710c 100644 +--- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C ++++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C +@@ -1,5 +1,5 @@ + // { dg-do compile } +-// { dg-options "-O2 -fdump-tree-ivopts-details" } ++// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } + + class MinimalVec3 + { +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c +index bda2516..22c8a5d 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c +@@ -1,7 +1,7 @@ + /* A test for strength reduction and induction variable elimination. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + /* { dg-require-effective-target size32plus } */ + + /* Size of this structure should be sufficiently weird so that no memory +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c +index f0770ab..65d74c8 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c +@@ -1,7 +1,7 @@ + /* A test for strength reduction and induction variable elimination. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + /* { dg-require-effective-target size32plus } */ + + /* Size of this structure should be sufficiently weird so that no memory +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c +index 5f42857..9bc86ee 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c +@@ -1,7 +1,7 @@ + /* A test for induction variable merging. */ + + /* { dg-do compile } */ +-/* { dg-options "-O1 -fdump-tree-optimized" } */ ++/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */ + + void foo(long); + +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c +index 0fa5600..94caa44 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ ++/* { dg-options "-O2 -fivopts -fopt-info-loop-missed -Wunsafe-loop-optimizations" } */ + extern void g(void); + + void +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c +index 2c6cfc6..648e6e6 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-O2 -fdump-tree-ivopts" } */ ++/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */ + + void vnum_test8(int *data) + { +diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c +index e911bfc..5d3e7e0 100644 +--- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c ++++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c +@@ -1,5 +1,5 @@ + /* { dg-do compile } */ +-/* { dg-options "-Os -fdump-tree-optimized" } */ ++/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */ + + /* Slightly changed testcase from PR middle-end/40815. */ + void bar(char*, char*, int); +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch new file mode 100644 index 0000000000..e16528b6bb --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch @@ -0,0 +1,35 @@ +From a4c99f7f7775f105eb6f1dfbdf304e6b7e498e2e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 11 Jan 2017 15:46:28 +0530 +Subject: [PATCH 04/54] [LOCAL]: For dejagnu static testing on qemu, suppress + warnings about multiple definitions from the test function and libc in line + with method used by powerpc. Dynamic linking and using a qemu binary which + understands sysroot resolves all test failures with builtins + +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +index 1cb4f97..bdfa08a 100644 +--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp ++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp +@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*] + lappend additional_flags "-Wl,--allow-multiple-definition" + } + +-<<<<<<< HEAD +-======= + if [istarget "microblaze*-*-linux*"] { + lappend additional_flags "-Wl,-zmuldefs" +- lappend additional_flags "-fPIC" + } + +->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic + foreach src [lsort [find $srcdir/$subdir *.c]] { + if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} { + c-torture-execute [list $src \ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch index 6fad8bf754..33688f1438 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch @@ -1,7 +1,8 @@ -From 8bcdd551f7fe585126ea3173ece976fbc646c34a Mon Sep 17 00:00:00 2001 +From 6b0de6811796b6834d426263eaa855b65c9b3389 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:20 -0700 -Subject: [PATCH] Add MicroBlaze to target-supports for atomic builtin tests +Date: Wed, 11 Jan 2017 15:50:35 +0530 +Subject: [PATCH 05/54] [Patch, testsuite]: Add MicroBlaze to target-supports + for atomic buil. .tin tests MicroBlaze added to supported targets for atomic builtin tests. @@ -13,18 +14,15 @@ Changelog/testsuite check_effective_target_sync_int_long. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/lib/target-supports.exp | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index 342af270ab..b0f510e596 100644 +index c591acd..94353cc 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp -@@ -6715,6 +6715,7 @@ proc check_effective_target_sync_int_long { } { +@@ -7428,6 +7428,7 @@ proc check_effective_target_sync_int_long { } { && [check_effective_target_arm_acq_rel]) || [istarget bfin*-*linux*] || [istarget hppa*-*linux*] @@ -33,5 +31,5 @@ index 342af270ab..b0f510e596 100644 || [istarget powerpc*-*-*] || [istarget crisv32-*-*] || [istarget cris-*-*] -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch index b428d121cd..b428d121cd 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch index 069329fcf8..3e2368f273 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch @@ -1,8 +1,8 @@ -From 4622988b62335af6ef17d58bf10940419fd0f99f Mon Sep 17 00:00:00 2001 +From 0d2cca275f3e85ae42dac7888d862975d65ffb36 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:21 -0700 -Subject: [PATCH] Update MicroBlaze strings test for new scan-assembly output - resulting in use of $LC label +Date: Wed, 11 Jan 2017 16:20:01 +0530 +Subject: [PATCH 06/54] [Patch, testsuite]: Update MicroBlaze strings test for + new scan-assembly output resulting in use of $LC label ChangeLog/testsuite @@ -12,15 +12,12 @@ ChangeLog/testsuite to include $LC label. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c -index 7a63faf79f..0403b7bdca 100644 +index 7a63faf..0403b7b 100644 --- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c +++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c @@ -1,13 +1,15 @@ @@ -42,5 +39,5 @@ index 7a63faf79f..0403b7bdca 100644 somefunc (string2); } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch index dbfeb52b9e..bcd5dbade5 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch @@ -1,11 +1,9 @@ -From 037809e91bfed9c501ecd5272ff6d3ce96edf76c Mon Sep 17 00:00:00 2001 +From b6f828da3caa827d8ccc08bbf260a2a01b2b2613 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:22 -0700 -Subject: [PATCH] Allow MicroBlaze .weakext pattern in testsuite - -Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to -include optional ext at the end of .weak to match the MicroBlaze weak -label .weakext +Date: Thu, 12 Jan 2017 16:14:15 +0530 +Subject: [PATCH 07/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern + in regex match Extend regex pattern to include optional ext at the end of + .weak to match the MicroBlaze weak label .weakext ChangeLog/testsuite @@ -16,9 +14,10 @@ ChangeLog/testsuite * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + +Conflicts: + + gcc/testsuite/g++.dg/abi/rtti3.C --- gcc/testsuite/g++.dg/abi/rtti3.C | 4 ++-- gcc/testsuite/g++.dg/abi/thunk3.C | 2 +- @@ -26,13 +25,13 @@ Upstream-Status: Pending 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C -index 0316bcb5de..5a39a0811f 100644 +index 0cc7d3e..f284cd9 100644 --- a/gcc/testsuite/g++.dg/abi/rtti3.C +++ b/gcc/testsuite/g++.dg/abi/rtti3.C @@ -3,8 +3,8 @@ // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } -// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } } -// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } } +// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } } @@ -41,7 +40,7 @@ index 0316bcb5de..5a39a0811f 100644 // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } } diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C -index f2347f79ec..dcec8a771a 100644 +index f2347f7..dcec8a7 100644 --- a/gcc/testsuite/g++.dg/abi/thunk3.C +++ b/gcc/testsuite/g++.dg/abi/thunk3.C @@ -1,5 +1,5 @@ @@ -52,17 +51,17 @@ index f2347f79ec..dcec8a771a 100644 struct Base diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C -index fa5fbd4327..79cb311cab 100644 +index 6e8f124..d1d34fe 100644 --- a/gcc/testsuite/g++.dg/abi/thunk4.C +++ b/gcc/testsuite/g++.dg/abi/thunk4.C @@ -1,6 +1,6 @@ // { dg-require-weak "" } - // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } { "*" } { "" } } + // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } } -// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } +// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } } // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } } struct Base -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch index 6b9dd9913f..6232535d28 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch @@ -1,25 +1,21 @@ -From 23a04c06c2a689fed151eeb94c45ea9b512036ae Mon Sep 17 00:00:00 2001 +From d27a2545486da9c6a4d3d5ca06b4affb83f8d0a1 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:23 -0700 -Subject: [PATCH] Add MicroBlaze to check_profiling_available Testsuite - -Add MicroBlaze to check_profiling_available Testsuite, add -microblaze*-*-* target in check_profiling_available inline with other -archs setting profiling_available_saved to 0 +Date: Thu, 12 Jan 2017 16:34:27 +0530 +Subject: [PATCH 08/54] [Patch, testsuite]: Add MicroBlaze to + check_profiling_available Testsuite, add microblaze*-*-* target in + check_profiling_available inline with other archs setting + profiling_available_saved to 0 Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/testsuite/lib/target-supports.exp | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp -index b0f510e596..fffb690e49 100644 +index 94353cc..ecfbe4d 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp -@@ -625,6 +625,7 @@ proc check_profiling_available { test_what } { +@@ -676,6 +676,7 @@ proc check_profiling_available { test_what } { || [istarget m68k-*-elf] || [istarget m68k-*-uclinux*] || [istarget mips*-*-elf*] @@ -28,5 +24,5 @@ index b0f510e596..fffb690e49 100644 || [istarget mn10300-*-elf*] || [istarget moxie-*-elf*] -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch index c21ca816f6..db730f438f 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0010-Fix-atomic-side-effects.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0009-Patch-microblaze-Fix-atomic-side-effects.patch @@ -1,25 +1,21 @@ -From c1e8a1419e8f5d18e7135fb4fe3bf21941125008 Mon Sep 17 00:00:00 2001 +From 8711bdfe27bce04d35ba93a1d18ccccd61371829 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:24 -0700 -Subject: [PATCH] Fix atomic side effects. - -In atomic_compare_and_swapsi, add side effects to prevent incorrect -assumptions during optimization. Previously, the outputs were considered -unused; this generated assembly code with undefined side effects after -invocation of the atomic. +Date: Thu, 12 Jan 2017 16:41:43 +0530 +Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic side effects. In + atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions + during optimization. Previously, the outputs were considered unused; this + generated assembly code with undefined side effects after invocation of the + atomic. Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.md | 3 +++ gcc/config/microblaze/sync.md | 21 +++++++++++++-------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 8a372d7ebb..59d629b559 100644 +index f698e54..93f5fa2 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -41,6 +41,9 @@ @@ -33,7 +29,7 @@ index 8a372d7ebb..59d629b559 100644 (define_c_enum "unspec" [ diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index 8125bd8d63..edf4bdd811 100644 +index b34bd54..8e694e9 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -18,14 +18,19 @@ @@ -65,5 +61,5 @@ index 8125bd8d63..edf4bdd811 100644 "" { -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch index f4bc16e81f..5058529ad5 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0011-Fix-atomic-boolean-return-value.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch @@ -1,22 +1,18 @@ -From a5957bdf7acfde0a65eeba90bae11f5619bf96af Mon Sep 17 00:00:00 2001 +From 92015c19e5d1baabd62067bf1cfc4522e85d1b25 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:25 -0700 -Subject: [PATCH] Fix atomic boolean return value. - -In atomic_compare_and_swapsi, fix boolean return value. Previously, it -contained zero if successful and non-zero if unsuccessful. +Date: Thu, 12 Jan 2017 16:45:45 +0530 +Subject: [PATCH 10/54] [Patch, microblaze]: Fix atomic boolean return value. + In atomic_compare_and_swapsi, fix boolean return value. Previously, it + contained zero if successful and non-zero if unsuccessful. Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/sync.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md -index edf4bdd811..aadb414728 100644 +index 8e694e9..8ddb10d 100644 --- a/gcc/config/microblaze/sync.md +++ b/gcc/config/microblaze/sync.md @@ -34,15 +34,16 @@ @@ -40,5 +36,5 @@ index edf4bdd811..aadb414728 100644 } ) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch new file mode 100644 index 0000000000..2451c93851 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch @@ -0,0 +1,33 @@ +From 658476aef537c0c2d031eb1c7a001f00c1d9bf7b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 12 Jan 2017 16:50:17 +0530 +Subject: [PATCH 11/54] [Patch, microblaze]: Fix the Microblaze crash with + msmall-divides flag Compiler is crashing when we use msmall-divides and + mxl-barrel-shift flag. This is because when use above flags + microblaze_expand_divide function will be called for division operation. In + microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't + have subreg register due to this compiler was crashing. Changed the logic to + avoid sub_reg call + +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 9a4a287..cbe8cb7 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3575,8 +3575,7 @@ microblaze_expand_divide (rtx operands[]) + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); + +- insn = emit_insn (gen_movqi (regqi, mem_rtx)); +- insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0))); ++ insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch index 6005e216e3..b58df87319 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch @@ -1,26 +1,21 @@ -From c32df2ec3d269d19b631a17cea2b6d19bbb98c27 Mon Sep 17 00:00:00 2001 +From 64f1a238641616c9cca5823d7ca99e76a7c2a490 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:27 -0700 -Subject: [PATCH] Add MicroBlaze ashrsi_3_with_size_opt +Date: Thu, 12 Jan 2017 16:52:56 +0530 +Subject: [PATCH 12/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added + ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os + optimization is used. lshrsi3_with_size_opt is being removed as it has + conflicts with unsigned int variables -Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to -optimize the sra instructions when the -Os optimization is used. -lshrsi3_with_size_opt is being removed as it has conflicts with unsigned -int variables - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 59d629b559..8c0a97e032 100644 +index 93f5fa2..fe90a14 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -1505,6 +1505,27 @@ +@@ -1506,6 +1506,27 @@ (set_attr "length" "4,4")] ) @@ -49,5 +44,5 @@ index 59d629b559..8c0a97e032 100644 [(set (match_operand:SI 0 "register_operand" "=&d") (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch index e75bebebd7..6af0f10e2b 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch @@ -1,12 +1,10 @@ -From 79ea36649467aea6045a49c7d016f8f9245efb8c Mon Sep 17 00:00:00 2001 +From ed23e22fb25a2d3dc357c0743f51b2735fc46a6a Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:29 -0700 -Subject: [PATCH] MicroBlaze fixed missing save of r18 in fast_interrupt - -Fixed missing save of r18 in fast_interrupt. Register 18 is used as a -clobber register, and must be stored when entering a fast_interrupt. -Before this fix, register 18 was only saved if it was used directly in -the interrupt function. +Date: Thu, 12 Jan 2017 17:50:03 +0530 +Subject: [PATCH 13/54] [Patch, microblaze]: Fixed missing save of r18 in + fast_interrupt. Register 18 is used as a clobber register, and must be stored + when entering a fast_interrupt. Before this fix, register 18 was only saved + if it was used directly in the interrupt function. However, if the fast_interrupt function called a function that used r18, the register would not be saved, and thus be mangled @@ -21,18 +19,15 @@ Changelog Signed-off-by: Klaus Petersen <klauspetersen@gmail.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 15080db539..558796cad9 100644 +index cbe8cb7..6f0b4f4 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1943,7 +1943,7 @@ microblaze_must_save_register (int regno) +@@ -1967,7 +1967,7 @@ microblaze_must_save_register (int regno) { if (df_regs_ever_live_p (regno) || regno == MB_ABI_MSR_SAVE_REG @@ -42,5 +37,5 @@ index 15080db539..558796cad9 100644 || regno == MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM))) return 1; -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch index f5de718ee1..f47265b07e 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0016-MicroBlaze-use-bralid-for-profiler-calls.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch @@ -1,21 +1,18 @@ -From 6ed57ee8219e5d09a294b329dd7c531a1868dc8a Mon Sep 17 00:00:00 2001 +From 582558f3c18d096885ab24e645899f310b148b5c Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:31 -0700 -Subject: [PATCH] MicroBlaze use bralid for profiler calls +Date: Tue, 17 Jan 2017 10:57:19 +0530 +Subject: [PATCH 14/54] [Patch, microblaze]: Use bralid for profiler calls + Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index ccd77e8b4d..0dd8b853e2 100644 +index 0d3718f..88e0351 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h -@@ -519,7 +519,7 @@ typedef struct microblaze_args +@@ -486,7 +486,7 @@ typedef struct microblaze_args #define FUNCTION_PROFILER(FILE, LABELNO) { \ { \ @@ -25,5 +22,5 @@ index ccd77e8b4d..0dd8b853e2 100644 } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch new file mode 100644 index 0000000000..acfa083f27 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0015-Patch-microblaze-Disable-fivopts-by-default.patch @@ -0,0 +1,42 @@ +From b60068cbdd3c830e541fbd35f2ed119245911461 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 11:10:21 +0530 +Subject: [PATCH 15/54] [Patch, microblaze]: Disable fivopts by default Turn + off ivopts by default. Interferes with cse. + +Changelog + +2013-03-18 Edgar E. Iglesias <edgar.iglesias@xilinx.com> + + * gcc/common/config/microblaze/microblaze-common.c + (microblaze_option_optimization_table): Disable fivopts by default. + +Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> +Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> +--- + gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c +index 3e75675..fe45f2e 100644 +--- a/gcc/common/config/microblaze/microblaze-common.c ++++ b/gcc/common/config/microblaze/microblaze-common.c +@@ -24,6 +24,15 @@ + #include "common/common-target.h" + #include "common/common-target-def.h" + ++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ ++static const struct default_options microblaze_option_optimization_table[] = ++ { ++ /* Turn off ivopts by default. It messes up cse. */ ++ { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, ++ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, ++ { OPT_LEVELS_NONE, 0, NULL, 0 } ++ }; ++ + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch index b019571875..dbd7b2e2c9 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0014-Removed-MicroBlaze-moddi3-routinue.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0016-Patch-microblaze-Removed-moddi3-routinue.patch @@ -1,30 +1,25 @@ -From a68e94fc57bcf60cb730894e49dde55d081397f5 Mon Sep 17 00:00:00 2001 +From 640628680ff6f028ad6d5fef2e41da29664f036f Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:28 -0700 -Subject: [PATCH] Removed MicroBlaze moddi3 routinue +Date: Thu, 12 Jan 2017 17:36:16 +0530 +Subject: [PATCH 16/54] [Patch, microblaze]: Removed moddi3 routinue Using the + default moddi3 function as the existing implementation has many bugs -Removed moddi3 routinue Using the default moddi3 function as the -existing implementation has many bugs - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by:Nagaraju <nmekala@xilix.com> --- - libgcc/config/microblaze/moddi3.S | 115 ---------------------------------- + libgcc/config/microblaze/moddi3.S | 121 ---------------------------------- libgcc/config/microblaze/t-microblaze | 3 +- - 2 files changed, 1 insertion(+), 117 deletions(-) + 2 files changed, 1 insertion(+), 123 deletions(-) delete mode 100644 libgcc/config/microblaze/moddi3.S diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S deleted file mode 100644 -index bcea079476..0000000000 +index a8f17d7..0000000 --- a/libgcc/config/microblaze/moddi3.S +++ /dev/null -@@ -1,115 +0,0 @@ +@@ -1,121 +0,0 @@ -################################### -# --# Copyright (C) 2009-2017 Free Software Foundation, Inc. +-# Copyright (C) 2009-2018 Free Software Foundation, Inc. -# -# Contributed by Michael Eager <eager@eagercon.com>. -# @@ -54,6 +49,12 @@ index bcea079476..0000000000 -####################################### - - +-/* An executable stack is *not* required for these functions. */ +-#ifdef __linux__ +-.section .note.GNU-stack,"",%progbits +-.previous +-#endif +- - .globl __moddi3 - .ent __moddi3 -__moddi3: @@ -138,7 +139,7 @@ index bcea079476..0000000000 - .end __moddi3 - diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze -index 96959f0292..8d954a4957 100644 +index 96959f0..8d954a4 100644 --- a/libgcc/config/microblaze/t-microblaze +++ b/libgcc/config/microblaze/t-microblaze @@ -1,8 +1,7 @@ @@ -152,5 +153,5 @@ index 96959f0292..8d954a4957 100644 $(srcdir)/config/microblaze/muldi3_hard.S \ $(srcdir)/config/microblaze/mulsi3.S \ -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch index 5239d2bdcb..6fb1b32fea 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch @@ -1,8 +1,8 @@ -From 02d8afd50a868e827ac8b6b6243c69922cd694ed Mon Sep 17 00:00:00 2001 +From c0e74b79cc1db2f68dd560154225da1e5ddfd920 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:34 -0700 -Subject: [PATCH] Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and - TARGET_ASM_DESTRUCTOR macros. +Date: Tue, 17 Jan 2017 14:41:58 +0530 +Subject: [PATCH 17/54] [Patch, microblaze]: Add INIT_PRIORITY support Added + TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. These macros allows users to control the order of initialization of objects defined at namespace scope with the init_priority @@ -19,20 +19,17 @@ Changelog microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR. -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> +Signed-off-by:nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 558796cad9..c1b0172bcf 100644 +index 6f0b4f4..53b44df 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2530,6 +2530,53 @@ print_operand_address (FILE * file, rtx addr) +@@ -2554,6 +2554,53 @@ print_operand_address (FILE * file, rtx addr) } } @@ -86,7 +83,7 @@ index 558796cad9..c1b0172bcf 100644 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol is used, so that we don't emit an .extern for it in microblaze_asm_file_end. */ -@@ -3775,6 +3822,12 @@ microblaze_machine_dependent_reorg (void) +@@ -3841,6 +3888,12 @@ microblaze_starting_frame_offset (void) #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE microblaze_attribute_table @@ -100,5 +97,5 @@ index 558796cad9..c1b0172bcf 100644 #define TARGET_IN_SMALL_DATA_P microblaze_elf_in_small_data_p -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch index 049ce3fe2e..ab2473a374 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0018-Patch-microblaze-Add-optimized-lshrsi3.patch @@ -1,12 +1,9 @@ -From 0b2061ac7706df97da3e8b3c01c6a5cfc504c16e Mon Sep 17 00:00:00 2001 +From 2cba68c3e27ffaea77cc5469233cf4dcb9383142 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:35 -0700 -Subject: [PATCH] MicroBlaze add optimized lshrsi3 When barrel shifter is not - present - -Add optimized lshrsi3 When barrel shifter is not present, the immediate -value is greater than #5 and optimization is -OS, the compiler will -generate shift operation using loop. +Date: Tue, 17 Jan 2017 15:23:57 +0530 +Subject: [PATCH 18/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel + shifter is not present, the immediate value is greater than #5 and + optimization is -OS, the compiler will generate shift operation using loop. Changelog @@ -20,11 +17,8 @@ ChangeLog/testsuite * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> +Signed-off-by:Nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++ .../gcc.target/microblaze/others/lshrsi_Os_1.c | 13 +++++++++++++ @@ -32,10 +26,10 @@ Upstream-Status: Pending create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 8c0a97e032..abbe97c15f 100644 +index fe90a14..c063ffc 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -1615,6 +1615,27 @@ +@@ -1616,6 +1616,27 @@ (set_attr "length" "4,4")] ) @@ -65,7 +59,7 @@ index 8c0a97e032..abbe97c15f 100644 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c new file mode 100644 -index 0000000000..32a3be7c76 +index 0000000..32a3be7 --- /dev/null +++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c @@ -0,0 +1,13 @@ @@ -83,5 +77,5 @@ index 0000000000..32a3be7c76 +/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */ +/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */ -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch new file mode 100644 index 0000000000..5afcff434a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0019-Patch-microblaze-Modified-trap-instruction.patch @@ -0,0 +1,29 @@ +From e8b05b5105655d276c93864ab90e15bfbe46cf74 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 15:42:15 +0530 +Subject: [PATCH 19/54] [Patch, microblaze]: Modified trap instruction The + instruction was wrongly written to brki r0,-1 it should be bri r0. Modified + with the correct instruction + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> +--- + gcc/config/microblaze/microblaze.md | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index c063ffc..7bbdbe1 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2344,7 +2344,7 @@ + (define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" +- "brki\tr0,-1" ++ "bri\t0" + [(set_attr "type" "trap")] + ) + +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch index ead929ab68..6e07ac4fcc 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch @@ -1,26 +1,20 @@ -From f5416ee7ddc6e4853e57ed15fb2bf630de2c3b12 Mon Sep 17 00:00:00 2001 +From 0cc6aabbd3f7b331c3995f11efec545499297358 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:37 -0700 -Subject: [PATCH] Reducing Stack space for arguments Currently in Microblaze - target stack space +Date: Tue, 17 Jan 2017 16:42:44 +0530 +Subject: [PATCH 20/54] [Patch, microblaze]: Reducing Stack space for arguments + Currently in Microblaze target stack space for arguments in register is being + allocated even if there are no arguments in the function. This patch will + optimize the extra 24 bytes that are being allocated. -Reducing Stack space for arguments Currently in Microblaze target stack -space for arguments in register is being allocated even if there are no -arguments in the function. This patch will optimize the extra 24 bytes -that are being allocated. +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: -2015-04-17 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> +2015-04-17 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> - * microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New - * microblaze.c (REG_PARM_STACK_SPACE): Modify - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New + *microblaze.c (REG_PARM_STACK_SPACE): Modify --- gcc/config/microblaze/microblaze-protos.h | 1 + gcc/config/microblaze/microblaze.c | 134 +++++++++++++++++++++++++++++- @@ -28,10 +22,10 @@ Upstream-Status: Pending 3 files changed, 136 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h -index b56e052ae4..a1408629cc 100644 +index 4cbba0c..f8a56f7 100644 --- a/gcc/config/microblaze/microblaze-protos.h +++ b/gcc/config/microblaze/microblaze-protos.h -@@ -57,6 +57,7 @@ extern int symbol_mentioned_p (rtx); +@@ -58,6 +58,7 @@ extern int symbol_mentioned_p (rtx); extern int label_mentioned_p (rtx); extern bool microblaze_cannot_force_const_mem (machine_mode, rtx); extern void microblaze_eh_return (rtx op0); @@ -40,10 +34,10 @@ index b56e052ae4..a1408629cc 100644 /* Declare functions in microblaze-c.c. */ diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index c1b0172bcf..f46dffff0d 100644 +index 53b44df..0dec362 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1965,6 +1965,138 @@ microblaze_must_save_register (int regno) +@@ -1989,6 +1989,138 @@ microblaze_must_save_register (int regno) return 0; } @@ -182,7 +176,7 @@ index c1b0172bcf..f46dffff0d 100644 /* Return the bytes needed to compute the frame pointer from the current stack pointer. -@@ -3275,7 +3407,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, +@@ -3298,7 +3430,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, emit_insn (gen_indirect_jump (temp2)); /* Run just enough of rest_of_compilation. This sequence was @@ -192,10 +186,10 @@ index c1b0172bcf..f46dffff0d 100644 shorten_branches (insn); final_start_function (insn, file, 1); diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 0dd8b853e2..82e7e890be 100644 +index 88e0351..9f74ec8 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h -@@ -467,9 +467,9 @@ extern struct microblaze_frame_info current_frame_info; +@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info; #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 @@ -208,5 +202,5 @@ index 0dd8b853e2..82e7e890be 100644 #define STACK_BOUNDARY 32 -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch new file mode 100644 index 0000000000..b04ee58023 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0021-Patch-microblaze-Add-cbranchsi4_reg.patch @@ -0,0 +1,159 @@ +From f846bd900d5277dd9defb5fe0625f97e3417ee61 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:04:37 +0530 +Subject: [PATCH 21/54] [Patch, microblaze]: Add cbranchsi4_reg This patch + optimizes the generation of pcmpne/pcmpeq instruction if the compare + instruction has no immediate values.For the immediate values the xor + instruction is generated + +Signed-off-by: Nagaraju Mekala <nmekala@xilix.com> +Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> + +ChangeLog: +2015-01-13 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.md (cbranchsi4_reg): New + *microblaze.c (microblaze_expand_conditional_branch_reg): New + +Conflicts: + + gcc/config/microblaze/microblaze-protos.h +--- + gcc/config/microblaze/microblaze-protos.h | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c | 2 +- + gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c | 14 +++++++------- + gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------ + gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c | 2 +- + 8 files changed, 19 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index f8a56f7..c39e2e9 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -32,7 +32,7 @@ extern int microblaze_expand_shift (rtx *); + extern bool microblaze_expand_move (machine_mode, rtx *); + extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx); + extern void microblaze_expand_divide (rtx *); +-extern void microblaze_expand_conditional_branch (machine_mode, rtx *); ++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); + extern int microblaze_can_use_return_insn (void); +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +index 4041a24..ccc6a46 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 <= f3) +- print ("le"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +index 3902b83..1dd5fe6 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 < f3) +- print ("lt"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +index 8555974..d6f80fb 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c +@@ -6,5 +6,5 @@ void float_func () + { + /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if (f2 == f3) +- print ("eq"); ++ f1 = f2 + f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +index 79cc5f9..d117724 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c +@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3) + /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */ + if(f1==f2 && f1<=f3) +- print ("f1 eq f2 && f1 le f3"); ++ f2 = f3; + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +index ebfb170..7582297 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c +@@ -5,17 +5,17 @@ volatile float f1, f2, f3; + void float_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ +- if (f2 <= f3) +- print ("le"); ++ if (f2 <= f3) ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +index 1d6ba80..532c035 100644 +--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c ++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c +@@ -74,16 +74,16 @@ void float_cmp_func () + { + /* { dg-final { scan-assembler-not "fcmp" } } */ + if (f2 <= f3) +- print ("le"); ++ f1 = f3; + else if (f2 == f3) +- print ("eq"); ++ f1 = f3; + else if (f2 < f3) +- print ("lt"); ++ f1 = f3; + else if (f2 > f3) +- print ("gt"); ++ f1 = f3; + else if (f2 >= f3) +- print ("ge"); ++ f1 = f3; + else if (f2 != f3) +- print ("ne"); ++ f1 = f3; + + } +diff --git a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c +index fdcde1f..580b4db 100644 +--- a/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c ++++ b/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c +@@ -5,4 +5,4 @@ void trap () + __builtin_trap (); + } + +-/* { dg-final { scan-assembler "brki\tr0,-1" } } */ +\ No newline at end of file ++/* { dg-final { scan-assembler "bri\t0" } } */ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch new file mode 100644 index 0000000000..beeb80fdaa --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch @@ -0,0 +1,58 @@ +From 7d70a287544dd915b66a5658a3857ebecb8b3583 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:11:04 +0530 +Subject: [PATCH 22/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin. + The changes are made in the patch for the inline expansion of the fsqrt + builtin with fqrt instruction. The sqrt math function takes double as + argument and return double as argument. The pattern is selected while + expanding the unary op through expand_unop which passes DFmode and the DFmode + pattern was not there returning zero. Thus the sqrt math function is not + inlined and expanded. The pattern with DFmode argument is added. Also the + source and destination argument is not same the DF through two different + consecutive registers with lower 32 bit is the argument passed to sqrt and + the higher 32 bit is zero. If the source and destinations are different the + DFmode 64 bits registers is not set properly giving the problem in runtime. + Such changes are taken care in the implementation of the pattern for DFmode + for inline expansion of the sqrt. + +ChangeLog: +2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> + Nagaraju Mekala <nmekala@xilinx.com> + + * config/microblaze/microblaze.md (sqrtdf2): New + pattern. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/config/microblaze/microblaze.md | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 7bbdbe1..3a53e24 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -449,6 +449,20 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" ++ { ++ if (REGNO (operands[0]) == REGNO (operands[1])) ++ return "fsqrt\t%0,%1"; ++ else ++ return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; ++ } ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch new file mode 100644 index 0000000000..8f5bed52a6 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch @@ -0,0 +1,47 @@ +From a28768eec0a9d5137196bed8e8c6d284cf4c3cbc Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 17:33:31 +0530 +Subject: [PATCH 23/54] [Patch] OPT: Update heuristics for loop-invariant for + address arithme. .tic. + +The changes are made in the patch to update the heuristics +for loop invariant for address arithmetic. The heuristics is +changed to calculate the estimated register pressure cost when +ira based register pressure is not enabled. The estimated +register pressure cost modifies the existing calculation cost +associated to perform the Loop invariant code motion for address +arithmetic. + +ChangeLog: +2015-06-17 Ajit Agarwal <ajitkum@xilinx.com> + Nagaraju Mekala <nmekala@xilinx.com> + + * loop-invariant.c (gain_for_invariant): update the + heuristics for estimate_reg_pressure_cost. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com + Nagaraju Mekala nmekala@xilinx.com +--- + gcc/loop-invariant.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c +index bd31a51..8e22ca0 100644 +--- a/gcc/loop-invariant.c ++++ b/gcc/loop-invariant.c +@@ -1466,10 +1466,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, + + if (! flag_ira_loop_pressure) + { +- size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0], +- regs_used, speed, call_p) +- - estimate_reg_pressure_cost (new_regs[0], +- regs_used, speed, call_p)); ++ size_cost = estimate_reg_pressure_cost (regs_needed[0], ++ regs_used, speed, call_p); + } + else if (ret < 0) + return -1; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch index 03ea8b197f..85a749e58b 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch @@ -1,16 +1,14 @@ -From 2d90c10cf4d95999f68f474305828c7dfc51af18 Mon Sep 17 00:00:00 2001 -From: Nathan Rossi <nathan@nathanrossi.com> -Date: Thu, 12 Nov 2015 16:09:31 +1000 -Subject: [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions - -Change adddi3 to handle DI immediates as the second operand, this -requires modification to the output template however reduces the need to -specify seperate templates for 16-bit positive/negative immediate -operands. The use of 32-bit immediates for the addi and addic -instructions is handled by the assembler, which will emit the imm -instructions when required. This conveniently handles the optimizable -cases where the immediate constant value does not need the higher half -words of the operands upper/lower words. +From be9c512be09fa4ef67870ab0456eb3781394dac3 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 17 Jan 2017 18:07:24 +0530 +Subject: [PATCH 24/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3' + insn definitions Change adddi3 to handle DI immediates as the second operand, + this requires modification to the output template however reduces the need to + specify seperate templates for 16-bit positive/negative immediate operands. + The use of 32-bit immediates for the addi and addic instructions is handled + by the assembler, which will emit the imm instructions when required. This + conveniently handles the optimizable cases where the immediate constant value + does not need the higher half words of the operands upper/lower words. Change the constraints of the subdi3 instruction definition such that it does not match the second operand as an immediate value. This is because @@ -20,16 +18,15 @@ instruction to perform a forward arithmetic subtraction (it only provides reverse 'rD = IMM - rA'). Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> -Upstream-Status: Unsubmitted --- gcc/config/microblaze/microblaze.md | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b3a0011fd7..8a372d7ebb 100644 +index 3a53e24..949e103 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -483,17 +483,16 @@ +@@ -500,17 +500,16 @@ ;; Adding 2 DI operands in register or reg/imm (define_insn "adddi3" @@ -52,7 +49,7 @@ index b3a0011fd7..8a372d7ebb 100644 ;;---------------------------------------------------------------- ;; Subtraction -@@ -530,7 +529,7 @@ +@@ -547,7 +546,7 @@ (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=&d") (minus:DI (match_operand:DI 1 "register_operand" "d") @@ -62,5 +59,5 @@ index b3a0011fd7..8a372d7ebb 100644 "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" [(set_attr "type" "darith") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch index d8eb76955f..17f254488d 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch @@ -1,42 +1,36 @@ -From f269f552e1abf182dc3749e0f29b1529fc82644a Mon Sep 17 00:00:00 2001 +From c8ee051fa3e0ad05b19eb6141a7cb72245b412b7 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:42 -0700 -Subject: [PATCH] Update MicroBlaze ashlsi3 & movsf patterns +Date: Tue, 17 Jan 2017 18:18:41 +0530 +Subject: [PATCH 25/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns + This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand + of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal + patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our + instruction doesn't support so using gen_int_mode function -This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in -print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and -movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating -64-bit value which our instruction doesn't support so using gen_int_mode -function +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + :Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: +2016-01-07 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> -2016-01-07 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> - - * microblaze.md (ashlsi3_with_mul_nodelay, + *microblaze.md (ashlsi3_with_mul_nodelay, ashlsi3_with_mul_delay, movsf_internal): Updated the patterns to use gen_int_mode function - * microblaze.c (print_operand): - updated the 'F' case to use "unsinged int" instead - of HOST_WIDE_INT_PRINT_HEX - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.c (print_operand): + updated the 'F' case to use "unsinged int" instead + of HOST_WIDE_INT_PRINT_HEX --- gcc/config/microblaze/microblaze.c | 2 +- gcc/config/microblaze/microblaze.md | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index f46dffff0d..663b20a022 100644 +index 0dec362..daf0269 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2507,7 +2507,7 @@ print_operand (FILE * file, rtx op, int letter) +@@ -2531,7 +2531,7 @@ print_operand (FILE * file, rtx op, int letter) unsigned long value_long; REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), value_long); @@ -46,7 +40,7 @@ index f46dffff0d..663b20a022 100644 else { diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 13f8803428..b9c62b6d0f 100644 +index 949e103..bc675ca 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -1366,7 +1366,10 @@ @@ -74,5 +68,5 @@ index 13f8803428..b9c62b6d0f 100644 [(set_attr "type" "no_delay_arith") (set_attr "mode" "SI") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch index 6faa625128..506714bd3e 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0024-8-stage-pipeline-for-microblaze.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch @@ -1,27 +1,25 @@ -From 17353cc4ba521f5ad928a1ede61cf03110e366ae Mon Sep 17 00:00:00 2001 +From 64e76f3be6ad78044ea2b89b555a07758c2b2950 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:43 -0700 -Subject: [PATCH] 8-stage pipeline for microblaze +Date: Tue, 17 Jan 2017 19:50:34 +0530 +Subject: [PATCH 26/54] [Patch, microblaze]: 8-stage pipeline for microblaze + This patch adds the support for the 8-stage pipeline. The new 8-stage + pipeline reduces the latencies of float & integer division drastically -This patch adds the support for the 8-stage pipeline. The new 8-stage -pipeline reduces the latencies of float & integer division drastically +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> ChangeLog: +2016-01-18 Nagaraju Mekala <nmekala@xilix.com> -2016-01-18 Nagaraju Mekala <nagaraju.mekala@xilinx.com> + *microblaze.md (define_automaton mbpipe_8): New - * microblaze.md (define_automaton mbpipe_8): New - * microblaze.c (microblaze_option_override): Update - Updated the logic to generate only when MB version is 10.0 - * microblaze.h (pipeline_type): Update - Update the enum with MICROBLAZE_PIPE_8 - * microblaze.opt (mxl-frequency): New - New flag added for 8-stage pipeline + *microblaze.c (microblaze_option_override): Update + Updated the logic to generate only when MB version is 10.0 -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.h (pipeline_type): Update + Update the enum with MICROBLAZE_PIPE_8 + + *microblaze.opt (mxl-frequency): New + New flag added for 8-stage pipeline --- gcc/config/microblaze/microblaze.c | 13 ++++++ gcc/config/microblaze/microblaze.h | 3 +- @@ -30,10 +28,10 @@ Upstream-Status: Pending 4 files changed, 96 insertions(+), 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 663b20a022..e7697bf30d 100644 +index daf0269..3832d16 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -1773,6 +1773,19 @@ microblaze_option_override (void) +@@ -1772,6 +1772,19 @@ microblaze_option_override (void) warning (0, "-mxl-reorder requires -mxl-pattern-compare for -mcpu=v8.30.a"); TARGET_REORDER = 0; } @@ -54,7 +52,7 @@ index 663b20a022..e7697bf30d 100644 if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL) error ("-mxl-multiply-high requires -mno-xl-soft-mul"); diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 82e7e890be..3f48e48f10 100644 +index 9f74ec8..2ac5aeec 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -27,7 +27,8 @@ @@ -68,7 +66,7 @@ index 82e7e890be..3f48e48f10 100644 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001 diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index b9c62b6d0f..61d6412dac 100644 +index bc675ca..6395533 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -35,6 +35,7 @@ @@ -179,7 +177,7 @@ index b9c62b6d0f..61d6412dac 100644 (set_attr "length" "4")]) diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt -index 8847c3daf8..85a9929d74 100644 +index 8242998..c8e6f00 100644 --- a/gcc/config/microblaze/microblaze.opt +++ b/gcc/config/microblaze/microblaze.opt @@ -129,3 +129,7 @@ Use hardware prefetch instruction @@ -191,5 +189,5 @@ index 8847c3daf8..85a9929d74 100644 +Target Mask(AREA_OPTIMIZED_2) +Use 8 stage pipeline (frequency optimization) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch new file mode 100644 index 0000000000..95b9b2aa3d --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch @@ -0,0 +1,142 @@ +From 5147c831c6a78d9b95138b679bb2ca7624abc3a1 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:08:40 +0530 +Subject: [PATCH 27/54] [Patch,rtl Optimization]: Better register pressure + estimate for loop . .invariant code motion + +Calculate the loop liveness used for regs for calculating the register pressure +in the cost estimation. Loop liveness is based on the following properties. +We only need to find the set of objects that are live at the birth or the header +of the loop. We don't need to calculate the live through the loop by considering +live in and live out of all the basic blocks of the loop. This is based on the +point that the set of objects that are live-in at the birth or header of the loop +will be live-in at every node in the loop. + +If a v live is out at the header of the loop then the variable is live-in at every node +in the loop. To prove this, consider a loop L with header h such that the variable v +defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i +from the dominance property, i.e. h is strictly dominated by d. Furthermore, there +exists a path from h to a use of v which does not go through d. For every node p in +the loop, since the loop is strongly connected and node is a component of the CFG, +there exists a path, consisting only of nodes of L from p to h. Concatenating these +two paths proves that v is live-in and live-out of p. + +Calculate the live-out and live-in for the exit edge of the loop. This patch considers +liveness for not only the loop latch but also the liveness outside the loops. + +ChangeLog: +2016-01-22 Ajit Agarwal <ajitkum@xilinx.com> + + * loop-invariant.c + (find_invariants_to_move): Add the logic of regs_used based + on liveness. + * cfgloopanal.c + (estimate_reg_pressure_cost): Update the heuristics in presence + of call_p. + +Signed-off-by:Ajit Agarwal ajitkum@xilinx.com. +--- + gcc/cfgloopanal.c | 4 +++- + gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++++++++------------- + 2 files changed, 50 insertions(+), 17 deletions(-) + +diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c +index 3af0b2d..123dc6b 100644 +--- a/gcc/cfgloopanal.c ++++ b/gcc/cfgloopanal.c +@@ -411,7 +411,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed, + if (regs_needed + target_res_regs <= available_regs) + return 0; + +- if (regs_needed <= available_regs) ++ if ((regs_needed <= available_regs) ++ || (call_p && (regs_needed <= ++ (available_regs + target_clobbered_regs)))) + /* If we are close to running out of registers, try to preserve + them. */ + cost = target_reg_cost [speed] * n_new; +diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c +index 8e22ca0..c9ec8df 100644 +--- a/gcc/loop-invariant.c ++++ b/gcc/loop-invariant.c +@@ -1520,7 +1520,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed, + size_cost = 0; + } + +- return comp_cost - size_cost; ++ return comp_cost - size_cost + 1; + } + + /* Finds invariant with best gain for moving. Returns the gain, stores +@@ -1614,22 +1614,53 @@ find_invariants_to_move (bool speed, bool call_p) + /* REGS_USED is actually never used when the flag is on. */ + regs_used = 0; + else +- /* We do not really do a good job in estimating number of +- registers used; we put some initial bound here to stand for +- induction variables etc. that we do not detect. */ ++ /* The logic used in estimating the number of regs_used is changed. ++ Now it will be based on liveness of the loop. */ + { +- unsigned int n_regs = DF_REG_SIZE (df); +- +- regs_used = 2; +- +- for (i = 0; i < n_regs; i++) +- { +- if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i)) +- { +- /* This is a value that is used but not changed inside loop. */ +- regs_used++; +- } +- } ++ int i; ++ edge e; ++ vec<edge> edges; ++ bitmap_head regs_live; ++ ++ bitmap_initialize (®s_live, ®_obstack); ++ edges = get_loop_exit_edges (curr_loop); ++ ++ /* Loop liveness is based on the following properties. ++ We only need to find the set of objects that are live at the ++ birth or the header of the loop. ++ We don't need to calculate the live through the loop considering ++ live-in and live-out of all the basic blocks of the loop. This is ++ based on the point that the set of objects that are live-in at the ++ birth or header of the loop will be live-in at every block in the ++ loop. ++ ++ If a v live out at the header of the loop then the variable is ++ live-in at every node in the Loop. To prove this, consider a loop ++ L with header h such that the variable v defined at d is live-in ++ at h. Since v is live at h, d is not part of L. This follows from ++ the dominance property, i.e. h is strictly dominated by d. Furthermore, ++ there exists a path from h to a use of v which does not go through d. ++ For every node of the loop, p, since the loop is strongly connected ++ component of the CFG, there exists a path, consisting only of nodes ++ of L from p to h. Concatenating these two paths prove that v is ++ live-in and live-out of p. */ ++ ++ bitmap_ior_into (®s_live, DF_LR_IN (curr_loop->header)); ++ bitmap_ior_into (®s_live, DF_LR_OUT (curr_loop->header)); ++ ++ /* Calculate the live-out and live-in for the exit edge of the loop. ++ This considers liveness for not only the loop latch but also the ++ liveness outside the loops. */ ++ ++ FOR_EACH_VEC_ELT (edges, i, e) ++ { ++ bitmap_ior_into (®s_live, DF_LR_OUT (e->src)); ++ bitmap_ior_into (®s_live, DF_LR_IN (e->dest)); ++ } ++ ++ regs_used = bitmap_count_bits (®s_live) + 2; ++ bitmap_clear (®s_live); ++ edges.release (); + } + + if (! flag_ira_loop_pressure) +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch new file mode 100644 index 0000000000..3643ff19d1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0028-Patch-microblaze-Correct-the-const-high-double-immed.patch @@ -0,0 +1,69 @@ +From 2715b235b3db423bf35b9304a2ba5daa86b1680e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:25:48 +0530 +Subject: [PATCH 28/54] [Patch, microblaze]: Correct the const high double + immediate value With this patch the loading of the DI mode immediate values + will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE + functions, as CONST_DOUBLE_HIGH was returning the sign extension value even + of the unsigned long long constants also + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + +ChangeLog: +2016-02-03 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE & + REAL_VALUE_TO_TARGET_DOUBLE + *long.c (new): Added new testcase +--- + gcc/config/microblaze/microblaze.c | 8 ++++++-- + gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++ + 2 files changed, 16 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 3832d16..29cd54f 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2517,14 +2517,18 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ long l[2]; + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- val[0] = CONST_DOUBLE_HIGH (op); +- val[1] = CONST_DOUBLE_LOW (op); ++ REAL_VALUE_TYPE rv; ++ REAL_VALUE_FROM_CONST_DOUBLE (rv, op); ++ REAL_VALUE_TO_TARGET_DOUBLE (rv, l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c +new file mode 100644 +index 0000000..4d45186 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/microblaze/long.c +@@ -0,0 +1,10 @@ ++/* { dg-options "-O0" } */ ++#define BASEADDR 0xF0000000ULL ++int main () ++{ ++ unsigned long long start; ++ start = (unsigned long long) BASEADDR; ++ return 0; ++} ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */ ++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch new file mode 100644 index 0000000000..b4b9d2ecbb --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch @@ -0,0 +1,36 @@ +From 7e025a0b22eee87bf9597267918bd16fc87c85c2 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 11:49:58 +0530 +Subject: [PATCH 29/54] [Fix, microblaze]: Fix internal compiler error with + msmall-divides This patch will fix the internal error + microblaze_expand_divide function which comes because of rtx PLUS where the + mem_rtx is of type SI and the operand is of type QImode. This patch modifies + the mem_rtx as QImode and Plus as QImode to fix the error. + +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> +ChangeLog: + 2016-02-23 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> + + *microblaze.c (microblaze_expand_divide): Update +--- + gcc/config/microblaze/microblaze.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 29cd54f..f8a417c 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3769,7 +3769,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_addsi3 (regt1, regt1, operands[2])); + mem_rtx = gen_rtx_MEM (QImode, +- gen_rtx_PLUS (Pmode, regt1, div_table_rtx)); ++ gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); + jump = emit_jump_insn_after (gen_jump (div_end_label), insn); +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch index 97422aeaf8..52fd4beab8 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch @@ -1,7 +1,8 @@ -From 34049c9fcaa256befad032cbcd8aa74beecf13dc Mon Sep 17 00:00:00 2001 +From 27a69d1873221747121360d0a1dffc4336a1d0cc Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:47 -0700 -Subject: [PATCH] Fix the calculation of high word in a long long 64-bit +Date: Wed, 18 Jan 2017 12:03:39 +0530 +Subject: [PATCH 30/54] [patch,microblaze]: Fix the calculation of high word in + a long long 6. .4-bit This patch will change the calculation of high word in a long long 64-bit. Earlier to this patch the high word of long long word (0xF0000000ULL) is @@ -11,29 +12,25 @@ removes the condition of checking high word = 0 & low word < 0. This check is not required for the correctness of calculating 32-bit high and low words in a 64-bit long long. -ChangeLog: - -2016-03-01 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - Ajit Agarwal <ajitkum@xilinx.com> +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> - * config/microblaze/microblaze.c (print_operand): Remove the - condition of checking high word = 0 & low word < 0. - * testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. +ChangeLog: +2016-03-01 Nagaraju Mekala <nmekala@xilix.com> + Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *config/microblaze/microblaze.c (print_operand): Remove the condition of checking + high word = 0 & low word < 0. + *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option. --- gcc/config/microblaze/microblaze.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index a41121264e..2ed64971fb 100644 +index f8a417c..70d8d03 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -2509,9 +2509,6 @@ print_operand (FILE * file, rtx op, int letter) +@@ -2535,9 +2535,6 @@ print_operand (FILE * file, rtx op, int letter) { val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; val[1] = INTVAL (op) & 0x00000000ffffffffLL; @@ -44,5 +41,5 @@ index a41121264e..2ed64971fb 100644 fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); } -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch index 02940e2fba..571445237d 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0028-Add-new-bit-field-instructions.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0031-Patch-microblaze-Add-new-bit-field-instructions.patch @@ -1,32 +1,26 @@ -From 90b6f833bd59f89d4192a3dc787fc2c9115b9c00 Mon Sep 17 00:00:00 2001 +From 35569bb20a5bb881f7f275d901a0be3408b16622 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:48 -0700 -Subject: [PATCH] Add new bit-field instructions +Date: Wed, 18 Jan 2017 12:14:51 +0530 +Subject: [PATCH 31/54] [Patch, microblaze]: Add new bit-field instructions + This patches adds new bsefi and bsifi instructions. BSEFI- The instruction + shall extract a bit field from a register and place it right-adjusted in the + destination register. The other bits in the destination register shall be set + to zero BSIFI- The instruction shall insert a right-adjusted bit field from a + register at another position in the destination register. The rest of the + bits in the destination register shall be unchanged -This patches adds new bsefi and bsifi instructions. BSEFI- The -instruction shall extract a bit field from a register and place it -right-adjusted in the destination register. The other bits in the -destination register shall be set to zero BSIFI- The instruction shall -insert a right-adjusted bit field from a register at another position in -the destination register. The rest of the bits in the destination -register shall be unchanged +Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> ChangeLog: + 2016-02-03 Nagaraju Mekala <nmekala@xilix.com> -2016-02-03 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * microblaze.md (Update): Added new patterns - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending + *microblaze.md (Update): Added new patterns --- gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 61d6412dac..7a00629922 100644 +index 6395533..5a2dd13 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -980,6 +980,8 @@ @@ -122,5 +116,5 @@ index 61d6412dac..7a00629922 100644 + (include "sync.md") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch index c3e4bc9ea6..dce1bc58b7 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0029-Fix-bug-in-MB-version-calculation.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch @@ -1,24 +1,21 @@ -From 3eada9d81437d378ef24f11a8bd046fee5b3505a Mon Sep 17 00:00:00 2001 +From 3db8f0c3124d3001d3c10e6d400943f3ec57616b Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:49 -0700 -Subject: [PATCH] Fix bug in MB version calculation +Date: Wed, 18 Jan 2017 12:42:10 +0530 +Subject: [PATCH 32/54] [Patch, microblaze]: Fix bug in MB version calculation + This patch fixes the bug in microblaze_version_to_int function. Earlier the + conversion of vXX.YY.Z to int has a bug which is fixed now. -This patch fixes the bug in microblaze_version_to_int function. Earlier -the conversion of vXX.YY.Z to int has a bug which is fixed now. - -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com> + Nagaraju Mekala <nmekala@xilix.com> --- gcc/config/microblaze/microblaze.c | 147 ++++++++++++++++++------------------- 1 file changed, 70 insertions(+), 77 deletions(-) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 2ed64971fb..55dba83882 100644 +index 70d8d03..30a0fcf 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -239,6 +239,63 @@ section *sdata2_section; +@@ -238,6 +238,63 @@ section *sdata2_section; #define TARGET_HAVE_TLS true #endif @@ -82,7 +79,7 @@ index 2ed64971fb..55dba83882 100644 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */ static bool microblaze_const_double_ok (rtx op, machine_mode mode) -@@ -1267,8 +1324,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, +@@ -1266,8 +1323,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, { if (TARGET_BARREL_SHIFT) { @@ -92,7 +89,7 @@ index 2ed64971fb..55dba83882 100644 *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (2); -@@ -1329,8 +1385,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, +@@ -1328,8 +1384,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, } else if (!TARGET_SOFT_MUL) { @@ -102,7 +99,7 @@ index 2ed64971fb..55dba83882 100644 *total = COSTS_N_INSNS (1); else *total = COSTS_N_INSNS (3); -@@ -1610,72 +1665,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, +@@ -1609,72 +1664,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode, return 0; } @@ -176,7 +173,7 @@ index 2ed64971fb..55dba83882 100644 microblaze_section_threshold = (global_options_set.x_g_switch_value ? g_switch_value -@@ -1696,13 +1692,13 @@ microblaze_option_override (void) +@@ -1695,13 +1691,13 @@ microblaze_option_override (void) /* Check the MicroBlaze CPU version for any special action to be done. */ if (microblaze_select_cpu == NULL) microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU; @@ -193,7 +190,7 @@ index 2ed64971fb..55dba83882 100644 if (ver < 0) { /* No hardware exceptions in earlier versions. So no worries. */ -@@ -1713,8 +1709,7 @@ microblaze_option_override (void) +@@ -1712,8 +1708,7 @@ microblaze_option_override (void) microblaze_pipe = MICROBLAZE_PIPE_3; } else if (ver == 0 @@ -203,7 +200,7 @@ index 2ed64971fb..55dba83882 100644 { #if 0 microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY); -@@ -1731,11 +1726,9 @@ microblaze_option_override (void) +@@ -1730,11 +1725,9 @@ microblaze_option_override (void) #endif microblaze_no_unsafe_delay = 0; microblaze_pipe = MICROBLAZE_PIPE_5; @@ -218,7 +215,7 @@ index 2ed64971fb..55dba83882 100644 { /* Pattern compares are to be turned on by default only when compiling for MB v5.00.'z'. */ -@@ -1743,7 +1736,7 @@ microblaze_option_override (void) +@@ -1742,7 +1735,7 @@ microblaze_option_override (void) } } @@ -227,7 +224,7 @@ index 2ed64971fb..55dba83882 100644 if (ver < 0) { if (TARGET_MULTIPLY_HIGH) -@@ -1751,7 +1744,7 @@ microblaze_option_override (void) +@@ -1750,7 +1743,7 @@ microblaze_option_override (void) "-mxl-multiply-high can be used only with -mcpu=v6.00.a or greater"); } @@ -236,7 +233,7 @@ index 2ed64971fb..55dba83882 100644 microblaze_has_clz = 1; if (ver < 0) { -@@ -1760,7 +1753,7 @@ microblaze_option_override (void) +@@ -1759,7 +1752,7 @@ microblaze_option_override (void) } /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified. */ @@ -246,5 +243,5 @@ index 2ed64971fb..55dba83882 100644 { if (TARGET_REORDER == 1) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch index 1d877be687..15111477a2 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0033-Fixing-the-bug-in-the-bit-field-instruction.patch @@ -1,23 +1,19 @@ -From 0c740ddd203433ef8d979348c085269f8b97cbfc Mon Sep 17 00:00:00 2001 +From f3e259923788176ebb323155cc089e68c6de0895 Mon Sep 17 00:00:00 2001 From: Mahesh Bodapati <mbodapat@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:50 -0700 -Subject: [PATCH] MicroBlaze fixing the bug in the bit-field instruction. +Date: Wed, 18 Jan 2017 13:57:48 +0530 +Subject: [PATCH 33/54] Fixing the bug in the bit-field instruction. Bit field + instruction should be generated only if mcpu >10.0 -Bit field instruction should be generated only if mcpu >10.0 - -Signed-off-by: Mahesh Bodapati <mbodapat@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- gcc/config/microblaze/microblaze.c | 3 +++ gcc/config/microblaze/microblaze.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c -index 55dba83882..4f6d399bba 100644 +index 30a0fcf..835e906 100644 --- a/gcc/config/microblaze/microblaze.c +++ b/gcc/config/microblaze/microblaze.c -@@ -159,6 +159,9 @@ int microblaze_no_unsafe_delay; +@@ -163,6 +163,9 @@ int microblaze_no_unsafe_delay; /* Set to one if the targeted core has the CLZ insn. */ int microblaze_has_clz = 0; @@ -28,7 +24,7 @@ index 55dba83882..4f6d399bba 100644 version having only a particular type of pipeline. There can still be options on the CPU to scale pipeline features up or down. :( diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h -index 3f48e48f10..712525f856 100644 +index 2ac5aeec..991d0f7 100644 --- a/gcc/config/microblaze/microblaze.h +++ b/gcc/config/microblaze/microblaze.h @@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[]; @@ -48,5 +44,5 @@ index 3f48e48f10..712525f856 100644 /* The default is to support PIC. */ #define TARGET_SUPPORTS_PIC 1 -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch new file mode 100644 index 0000000000..f22f2f3fb2 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch @@ -0,0 +1,32 @@ +From 52cf8e91f06ce9259d4d94bb8ea5cb327825b806 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 18 Jan 2017 20:57:10 +0530 +Subject: [PATCH 34/54] [Patch, microblaze]: Macros used in Xilinx internal + patches has been removed in gcc 6.2 version so modified the code accordingly. + +--- + gcc/config/microblaze/microblaze.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 835e906..2e3b4c9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2520,11 +2520,9 @@ print_operand (FILE * file, rtx op, int letter) + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); + else + { +- REAL_VALUE_TYPE rv; +- REAL_VALUE_FROM_CONST_DOUBLE (rv, op); +- REAL_VALUE_TO_TARGET_DOUBLE (rv, l); +- val[1] = l[WORDS_BIG_ENDIAN == 0]; +- val[0] = l[WORDS_BIG_ENDIAN != 0]; ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); ++ val[1] = l[WORDS_BIG_ENDIAN == 0]; ++ val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } + else if (code == CONST_INT) +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch index 3786a71a08..00d67bcf63 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0035-Fixing-the-issue-with-the-builtin_alloc.patch @@ -1,21 +1,17 @@ -From fdb99f97b41f7cd06b81e668b88463d0fc2cbe87 Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:54 -0700 -Subject: [PATCH] Fixing the issue with MicroBlaze builtin_alloc +From 727b0f7ae03279177559f5d85d8920352bd853b2 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 23 Feb 2017 17:09:04 +0530 +Subject: [PATCH 35/54] Fixing the issue with the builtin_alloc. register r18 + was not properly handling the stack pattern which was resolved by using free + available register -Fixing the issue with the builtin_alloc. Register r18 was not properly -handling the stack pattern which was resolved by using free available -register - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending +signed-off-by:nagaraju mekala <nmekala@xilinx.com> --- gcc/config/microblaze/microblaze.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 7a00629922..68c3b22bd4 100644 +index 5a2dd13..8072ffc 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -2076,10 +2076,10 @@ @@ -44,5 +40,5 @@ index 7a00629922..68c3b22bd4 100644 } ) -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch new file mode 100644 index 0000000000..54ccd9a0c7 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch @@ -0,0 +1,49 @@ +From 7156e379a67fa47a5fb9ede1448c0d528dbda65b Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Thu, 2 Mar 2017 19:02:31 +0530 +Subject: [PATCH 36/54] [Patch,Microblaze]:reverting the cost check before + propagating constants. + +--- + gcc/cprop.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/gcc/cprop.c b/gcc/cprop.c +index e4df509..deb706b 100644 +--- a/gcc/cprop.c ++++ b/gcc/cprop.c +@@ -733,6 +733,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + int success = 0; + rtx set = single_set (insn); + ++#if 0 + bool check_rtx_costs = true; + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); + int old_cost = set ? set_rtx_cost (set, speed) : 0; +@@ -744,6 +745,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + && (GET_CODE (XEXP (note, 0)) == CONST + || CONSTANT_P (XEXP (note, 0))))) + check_rtx_costs = false; ++#endif + + /* Usually we substitute easy stuff, so we won't copy everything. + We however need to take care to not duplicate non-trivial CONST +@@ -752,6 +754,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + + validate_replace_src_group (from, to, insn); + ++#if 0 + /* If TO is a constant, check the cost of the set after propagation + to the cost of the set before the propagation. If the cost is + higher, then do not replace FROM with TO. */ +@@ -764,6 +767,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + return false; + } + ++#endif + + if (num_changes_pending () && apply_change_group ()) + success = 1; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch index 29bc752eae..26b685a580 100644 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-7/0032-MicroBlaze-remove-bitfield-instructions-macros.patch +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch @@ -1,30 +1,25 @@ -From 646fe1dbaca06f2fe2df4c0da3fa20e0aff0a4ec Mon Sep 17 00:00:00 2001 -From: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Date: Sat, 26 Aug 2017 19:21:56 -0700 -Subject: [PATCH] MicroBlaze remove bitfield instructions macros +From 149cf4619622d27641a2886cd8bf38a49ad88f87 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 19 Feb 2018 18:06:16 +0530 +Subject: [PATCH 37/54] [Patch,Microblaze]: update in constraints for bitfield + insert and extract instructions. -Remove the conditions in the bit field expand macros to generate the -instructions in structure bit-field usecases - -ChangeLog: - -2018-08-16 Nagaraju Mekala <nagaraju.mekala@xilinx.com> - - * gcc/config/microblaze/microblaze.md: - remove the expand constraints - -Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com> -Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> -Upstream-Status: Pending --- - gcc/config/microblaze/microblaze.md | 40 +++++-------------------------------- - 1 file changed, 5 insertions(+), 35 deletions(-) + gcc/config/microblaze/microblaze.md | 43 ++++++------------------------------- + 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md -index 68c3b22bd4..ef53c3069e 100644 +index 8072ffc..9bb87ec 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md -@@ -2482,25 +2482,8 @@ +@@ -2476,33 +2476,17 @@ + DONE; + }") + +-(define_expand "extvsi" ++(define_expand "extzvsi" + [(set (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "I") (match_operand:SI 3 "immediate_operand" "I")))] "TARGET_HAS_BITFIELD" @@ -50,13 +45,16 @@ index 68c3b22bd4..ef53c3069e 100644 +"" +) - (define_insn "extv_32" +-(define_insn "extv_32" ++ ++(define_insn "extzv_32" [(set (match_operand:SI 0 "register_operand" "=r") -@@ -2518,22 +2501,9 @@ - (match_operand:SI 1 "immediate_operand" "I") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") +@@ -2519,21 +2503,8 @@ (match_operand:SI 2 "immediate_operand" "I")) (match_operand:SI 3 "register_operand" "r"))] -- "TARGET_HAS_BITFIELD" + "TARGET_HAS_BITFIELD" - " -{ - unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); @@ -72,12 +70,11 @@ index 68c3b22bd4..ef53c3069e 100644 - operands[2], operands[3])); - DONE; -}") -+"TARGET_HAS_BITFIELD" +"" +) (define_insn "insv_32" [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") -- -2.14.2 +2.7.4 diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch new file mode 100644 index 0000000000..d8ae6c1557 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch @@ -0,0 +1,38 @@ +From 5494699756f8e1dba6848fcf09780a031139c232 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Mon, 4 Jun 2018 10:10:18 +0530 +Subject: [PATCH 38/54] [Patch,Microblaze] : Removed fsqrt generation for + double values. + +--- + gcc/config/microblaze/microblaze.md | 14 -------------- + 1 file changed, 14 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 9bb87ec..a93ddd0 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -524,20 +524,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +-(define_insn "sqrtdf2" +- [(set (match_operand:DF 0 "register_operand" "=d") +- (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT" +- { +- if (REGNO (operands[0]) == REGNO (operands[1])) +- return "fsqrt\t%0,%1"; +- else +- return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0"; +- } +- [(set_attr "type" "fsqrt") +- (set_attr "mode" "SF") +- (set_attr "length" "4")]) +- + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch new file mode 100644 index 0000000000..88497a8ef4 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0039-Intial-commit-of-64-bit-Microblaze.patch @@ -0,0 +1,810 @@ +From 6e8b37bf54646c38fb4071d542a60ea92715df9b Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 3 Apr 2018 16:48:39 +0530 +Subject: [PATCH 39/54] Intial commit of 64-bit Microblaze + +--- + gcc/config/microblaze/microblaze-protos.h | 1 + + gcc/config/microblaze/microblaze.c | 109 +++++++-- + gcc/config/microblaze/microblaze.h | 4 +- + gcc/config/microblaze/microblaze.md | 370 +++++++++++++++++++++++++++++- + gcc/config/microblaze/microblaze.opt | 9 +- + gcc/config/microblaze/t-microblaze | 7 +- + 6 files changed, 461 insertions(+), 39 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h +index c39e2e9..a5ed62e 100644 +--- a/gcc/config/microblaze/microblaze-protos.h ++++ b/gcc/config/microblaze/microblaze-protos.h +@@ -35,6 +35,7 @@ extern void microblaze_expand_divide (rtx *); + extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *); + extern void microblaze_expand_conditional_branch_sf (rtx *); ++extern void microblaze_expand_conditional_branch_df (rtx *); + extern int microblaze_can_use_return_insn (void); + extern void print_operand (FILE *, rtx, int); + extern void print_operand_address (FILE *, rtx); +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 2e3b4c9..2079ae9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3457,11 +3457,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + op0 = operands[0]; + op1 = operands[1]; + +- if (!register_operand (op0, SImode) +- && !register_operand (op1, SImode) ++ if (!register_operand (op0, mode) ++ && !register_operand (op1, mode) + && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0)) + { +- rtx temp = force_reg (SImode, op1); ++ rtx temp = force_reg (mode, op1); + emit_move_insn (op0, temp); + return true; + } +@@ -3499,12 +3499,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[]) + && (flag_pic == 2 || microblaze_tls_symbol_p (p0) + || !SMALL_INT (p1))))) + { +- rtx temp = force_reg (SImode, p0); ++ rtx temp = force_reg (mode, p0); + rtx temp2 = p1; + + if (flag_pic && reload_in_progress) + df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); +- emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2)); ++ emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2)); + return true; + } + } +@@ -3635,7 +3635,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG)); +@@ -3644,23 +3644,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + if (cmp_op1 == const0_rtx) + { + comp_reg = cmp_op0; +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + + else if (code == EQ || code == NE) + { + /* Use xor for equal/not-equal comparison. */ +- emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); +- condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1)); ++ else ++ emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); ++ condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1)); ++ else ++ emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1)); + } + } + +@@ -3671,7 +3684,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + rtx cmp_op0 = operands[1]; + rtx cmp_op1 = operands[2]; + rtx label1 = operands[3]; +- rtx comp_reg = gen_reg_rtx (SImode); ++ rtx comp_reg = gen_reg_rtx (mode); + rtx condition; + + gcc_assert ((GET_CODE (cmp_op0) == REG) +@@ -3682,30 +3695,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), +- SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else if (code == EQ) + { +- emit_insn (gen_seq_internal_pat (comp_reg, +- cmp_op0, cmp_op1)); +- condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); ++ + } + else if (code == NE) + { +- emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, +- cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, label1)); ++ if (mode == SImode) ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ else ++ { ++ emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0, ++ cmp_op1)); ++ } ++ condition = gen_rtx_NE (mode, comp_reg, const0_rtx); ++ if (mode == SImode) ++ emit_jump_insn (gen_condjump (condition, label1)); ++ else ++ emit_jump_insn (gen_long_condjump (condition, label1)); + } + else + { + /* Generate compare and branch in single instruction. */ + cmp_op1 = force_reg (mode, cmp_op1); + condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); +- emit_jump_insn (gen_branch_compare (condition, cmp_op0, +- cmp_op1, label1)); ++ if (mode == SImode) ++ emit_jump_insn (gen_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ else ++ { ++ emit_jump_insn (gen_long_branch_compare (condition, cmp_op0, ++ cmp_op1, label1)); ++ } ++ + } + } + +@@ -3722,6 +3768,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + emit_jump_insn (gen_condjump (condition, operands[3])); + } + ++void ++microblaze_expand_conditional_branch_df (rtx operands[]) ++{ ++ rtx condition; ++ rtx cmp_op0 = XEXP (operands[0], 0); ++ rtx cmp_op1 = XEXP (operands[0], 1); ++ rtx comp_reg = gen_reg_rtx (DImode); ++ ++ emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); ++ condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ emit_jump_insn (gen_long_condjump (condition, operands[3])); ++} ++ + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ + + static bool +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 991d0f7..72fbee5 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe; + #define ASM_SPEC "\ + %(target_asm_spec) \ + %{mbig-endian:-EB} \ ++%{m64:-m64} \ + %{mlittle-endian:-EL}" + + /* Extra switches sometimes passed to the linker. */ +@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe; + #define LINK_SPEC "%{shared:-shared} -N -relax \ + %{mbig-endian:-EB --oformat=elf32-microblaze} \ + %{mlittle-endian:-EL --oformat=elf32-microblazeel} \ ++ %{m64:-EL --oformat=elf64-microblazeel} \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ +@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe; + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 32 ++#define LONG_TYPE_SIZE 64 + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index a93ddd0..6976b37 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -495,7 +495,6 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + +- + (define_insn "divsf3" + [(set (match_operand:SF 0 "register_operand" "=d") + (div:SF (match_operand:SF 1 "register_operand" "d") +@@ -506,6 +505,7 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++ + (define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=d") + (sqrt:SF (match_operand:SF 1 "register_operand" "d")))] +@@ -560,6 +560,18 @@ + + ;; Adding 2 DI operands in register or reg/imm + ++(define_insn "adddi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (match_operand:DI 2 "arith_plus_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ addlk\t%0,%z1,%2 ++ addlik\t%0,%z1,%2" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "adddi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") +@@ -604,6 +616,18 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + ++(define_insn "subdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "register_operand" "d,n")))] ++ "TARGET_MB_64" ++ "@ ++ rsubl\t%0,%2,%1 ++ addlik\t%0,%z1,-%2" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "subdi3" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") +@@ -793,6 +817,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negdi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (neg:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "rsubl\t%0,%1,r0" ++ [(set_attr "type" "darith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -812,6 +845,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "one_cmpldi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "xorli\t%0,%1,-1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ + (define_insn "*one_cmpldi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -838,6 +880,20 @@ + ;; Logical + ;;---------------------------------------------------------------- + ++(define_insn "anddi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ andl\t%0,%1,%2 ++ andli\t%0,%1,%2 #andl1" ++ ;; andli\t%0,%1,%2 #andl3 ++ ;; andli\t%0,%1,%2 #andl2 ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -853,6 +909,18 @@ + (set_attr "length" "4,8,8,8")]) + + ++(define_insn "iordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ior:DI (match_operand:DI 1 "arith_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ orl\t%0,%1,%2 ++ orli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ + (define_insn "iorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") + (ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d") +@@ -867,6 +935,19 @@ + (set_attr "mode" "SI,SI,SI,SI") + (set_attr "length" "4,8,8,8")]) + ++(define_insn "xordi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (xor:DI (match_operand:DI 1 "arith_operand" "%d,d") ++ (match_operand:DI 2 "arith_operand" "d,K")))] ++ "TARGET_MB_64" ++ "@ ++ xorl\t%0,%1,%2 ++ xorli\t%0,%1,%2 #andl1" ++ [(set_attr "type" "arith,arith") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")]) ++ ++ + (define_insn "xorsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d") +@@ -935,6 +1016,26 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++;;(define_expand "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] ++;; "TARGET_MB_64" ++;; { ++;; if (GET_CODE (operands[1]) != REG) ++;; FAIL; ++;; } ++;;) ++ ++ ++;;(define_insn "extendqidi2" ++;; [(set (match_operand:DI 0 "register_operand" "=d") ++;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] ++;; "TARGET_MB_64" ++;; "sextl8\t%0,%1" ++;; [(set_attr "type" "arith") ++;; (set_attr "mode" "DI") ++;; (set_attr "length" "4")]) ++ + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -944,6 +1045,16 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "extendhidi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "sextl16\t%0,%1" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++ + ;; Those for integer source operand are ordered + ;; widest source type first. + +@@ -1009,7 +1120,6 @@ + ) + + +- + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +@@ -1421,6 +1531,36 @@ + (set_attr "length" "4,4")] + ) + ++;; Barrel shift left ++(define_expand "ashldi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashldi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bsllli\t%0,%1,%2 ++ bslll\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++) + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1546,6 +1686,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "ashrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "ashrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrai\t%0,%1,%2 ++ bslra\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -1655,6 +1825,36 @@ + ;;---------------------------------------------------------------- + ;; 32-bit right shifts (logical) + ;;---------------------------------------------------------------- ++;; Barrel shift left ++(define_expand "lshrdi3" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "arith_operand" "")))] ++"TARGET_MB_64" ++{ ++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++ { ++ emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else ++ FAIL; ++} ++) ++ ++(define_insn "lshrdi3_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") ++ (match_operand:DI 2 "arith_operand" "I,d")))] ++ "TARGET_MB_64" ++ "@ ++ bslrli\t%0,%1,%2 ++ bslrl\t%0,%1,%2" ++ [(set_attr "type" "bshift,bshift") ++ (set_attr "mode" "DI,DI") ++ (set_attr "length" "4,4")] ++ ) + + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") +@@ -1801,6 +2001,8 @@ + (set_attr "length" "4")] + ) + ++ ++ + ;;---------------------------------------------------------------- + ;; Setting a register from an floating point comparison. + ;;---------------------------------------------------------------- +@@ -1816,6 +2018,18 @@ + (set_attr "length" "4")] + ) + ++(define_insn "cstoredf4" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (match_operator:DI 1 "ordered_comparison_operator" ++ [(match_operand:DF 2 "register_operand" "r") ++ (match_operand:DF 3 "register_operand" "r")]))] ++ "TARGET_MB_64" ++ "dcmp.%C1\t%0,%3,%2" ++ [(set_attr "type" "fcmp") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")] ++) ++ + ;;---------------------------------------------------------------- + ;; Conditional branches + ;;---------------------------------------------------------------- +@@ -1928,6 +2142,115 @@ + (set_attr "length" "12")] + ) + ++ ++(define_expand "cbranchdi4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "arith_operand" "I,i")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdi4_reg" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand") ++ (match_operand:DI 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_reg (DImode, operands); ++ DONE; ++}) ++ ++(define_expand "cbranchdf4" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand:DF 1 "register_operand") ++ (match_operand:DF 2 "register_operand")]) ++ (label_ref (match_operand 3 "")) ++ (pc)))] ++ "TARGET_MB_64" ++{ ++ microblaze_expand_conditional_branch_df (operands); ++ DONE; ++ ++}) ++ ++;; Used to implement comparison instructions ++(define_expand "long_condjump" ++ [(set (pc) ++ (if_then_else (match_operand 0) ++ (label_ref (match_operand 1)) ++ (pc)))]) ++ ++(define_insn "long_branch_zero" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "beal%C0i%?\t%z1,%2"; ++ else ++ return "beal%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +@@ -2462,17 +2785,33 @@ + DONE; + }") + +-(define_expand "extzvsi" ++(define_expand "extvsi" + [(set (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") + (match_operand:SI 3 "immediate_operand" "I")))] + "TARGET_HAS_BITFIELD" +-"" +-) +- ++" ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[2]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]); ++ ++ if ((len == 0) || (pos + len > 32) ) ++ FAIL; ++ ++ ;;if (!register_operand (operands[1], VOIDmode)) ++ ;; FAIL; ++ if (operands[0] == operands[1]) ++ FAIL; ++ if (GET_CODE (operands[1]) == ASHIFT) ++ FAIL; ++;; operands[2] = GEN_INT(INTVAL(operands[2])+1 ); ++ emit_insn (gen_extv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") + +-(define_insn "extzv_32" ++(define_insn "extv_32" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "I") +@@ -2489,8 +2828,21 @@ + (match_operand:SI 2 "immediate_operand" "I")) + (match_operand:SI 3 "register_operand" "r"))] + "TARGET_HAS_BITFIELD" +-"" +-) ++ " ++{ ++ unsigned HOST_WIDE_INT len = UINTVAL (operands[1]); ++ unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]); ++ ++ if (len <= 0 || pos + len > 32) ++ FAIL; ++ ++ ;;if (!register_operand (operands[0], VOIDmode)) ++ ;; FAIL; ++ ++ emit_insn (gen_insv_32 (operands[0], operands[1], ++ operands[2], operands[3])); ++ DONE; ++}") + + (define_insn "insv_32" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") +diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt +index c8e6f00..cdcae00 100644 +--- a/gcc/config/microblaze/microblaze.opt ++++ b/gcc/config/microblaze/microblaze.opt +@@ -125,11 +125,16 @@ Description for mxl-mode-novectors. + + mxl-prefetch + Target Mask(PREFETCH) +-Use hardware prefetch instruction ++Use hardware prefetch instruction. + + mxl-mode-xilkernel + Target + + mxl-frequency + Target Mask(AREA_OPTIMIZED_2) +-Use 8 stage pipeline (frequency optimization) ++Use 8 stage pipeline (frequency optimization). ++ ++m64 ++Target Mask(MB_64) ++MicroBlaze 64-bit mode. ++ +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 41fa9a9..e9a1921 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,8 +1,11 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian +-MULTILIB_DIRNAMES = bs m mh le ++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 ++MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch new file mode 100644 index 0000000000..1157a82fc3 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch @@ -0,0 +1,83 @@ +From 5526d87787d61990be3187b230fae4d0591d0651 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 4 Apr 2018 16:41:41 +0530 +Subject: [PATCH 40/54] Added load store pattern movdi and also adding missing + files + +--- + gcc/config/microblaze/constraints.md | 5 +++++ + gcc/config/microblaze/microblaze.md | 26 ++++++++++++++++++++++++++ + gcc/config/microblaze/t-microblaze | 4 ++-- + 3 files changed, 33 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index ae14944..a06b4d8 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -52,6 +52,11 @@ + (and (match_code "const_int") + (match_test "ival > 0 && ival < 0x10000"))) + ++(define_constraint "K" ++ "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." ++ (and (match_code "const_int") ++ (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ + ;; Define floating point constraints + + (define_constraint "G" +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 6976b37..0cd0441 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1120,6 +1120,32 @@ + ) + + ++(define_insn "*movdi_internal_64" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") ++ (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] ++ "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1"; ++ case 1: ++ return "addlik\t%0,r0,%1"; ++ case 2: ++ return "addlk\t%0,r0,r0"; ++ case 3: ++ case 4: ++ return "lli\t%0,%1"; ++ case 5: ++ case 6: ++ return "sli\t%1,%0"; ++ } ++ return "unreachable"; ++ } ++ [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "8,8,8,8,12,8,12")]) ++ + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index e9a1921..7671f63 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -4,8 +4,8 @@ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch new file mode 100644 index 0000000000..411958e748 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0041-Intial-commit-for-64bit-MB-sources.patch @@ -0,0 +1,2463 @@ +From eee9b7f7423823b133d6a5e5382863502433bdc6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 27 Jul 2018 15:23:41 +0530 +Subject: [PATCH 41/54] Intial commit for 64bit-MB sources. Need to cleanup the + code later. + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze-c.c | 6 + + gcc/config/microblaze/microblaze.c | 218 ++++++++---- + gcc/config/microblaze/microblaze.h | 63 ++-- + gcc/config/microblaze/microblaze.md | 606 ++++++++++++++++++++++++-------- + gcc/config/microblaze/t-microblaze | 7 +- + libgcc/config/microblaze/crti.S | 4 +- + libgcc/config/microblaze/crtn.S | 4 +- + libgcc/config/microblaze/divdi3.S | 98 ++++++ + libgcc/config/microblaze/divdi3_table.c | 62 ++++ + libgcc/config/microblaze/moddi3.S | 97 +++++ + libgcc/config/microblaze/muldi3.S | 73 ++++ + libgcc/config/microblaze/t-microblaze | 11 +- + libgcc/config/microblaze/udivdi3.S | 107 ++++++ + libgcc/config/microblaze/umoddi3.S | 110 ++++++ + 15 files changed, 1232 insertions(+), 236 deletions(-) + create mode 100644 libgcc/config/microblaze/divdi3.S + create mode 100644 libgcc/config/microblaze/divdi3_table.c + create mode 100644 libgcc/config/microblaze/moddi3.S + create mode 100644 libgcc/config/microblaze/muldi3.S + create mode 100644 libgcc/config/microblaze/udivdi3.S + create mode 100644 libgcc/config/microblaze/umoddi3.S + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index a06b4d8..867a7b5 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL"))) ++ (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) + + ;; Define floating point constraints + +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index 7b020b5..d8a1d13 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile) + builtin_define ("HAVE_HW_FPU_SQRT"); + builtin_define ("__HAVE_HW_FPU_SQRT__"); + } ++ if (TARGET_MB_64) ++ { ++ builtin_define ("__arch64__"); ++ builtin_define ("__microblaze64__"); ++ builtin_define ("__MICROBLAZE64__"); ++ } + } +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 2079ae9..ba7ade4 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -382,10 +382,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) + { + return 1; + } +- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) ++ /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG) + { + return 1; +- } ++ }*/ + else + return 0; + +@@ -433,7 +433,7 @@ double_memory_operand (rtx op, machine_mode mode) + return 1; + + return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT +- ? E_SImode : E_SFmode), ++ ? Pmode : E_SFmode), + plus_constant (Pmode, addr, 4)); + } + +@@ -680,7 +680,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg) + /* Load the addend. */ + addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)), + UNSPEC_TLS); +- addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); ++ addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend)); + dest = gen_rtx_PLUS (Pmode, dest, addend); + break; + +@@ -698,7 +698,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x) + + if (XINT (x, 1) == UNSPEC_GOTOFF) + { +- info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM); ++ info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); + info->type = ADDRESS_GOTOFF; + } + else if (XINT (x, 1) == UNSPEC_PLT) +@@ -1230,8 +1230,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length) + emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES)); + + /* Emit the test & branch. */ +- emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src), ++ ++ if (TARGET_MB_64) { ++ emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src), ++ src_reg, final_src, label)); ++ } ++ else { ++ emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src), + src_reg, final_src, label)); ++ ++ } + + /* Mop up any left-over bytes. */ + if (leftover) +@@ -1561,14 +1569,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v, + break; + + case E_DFmode: +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + if (!cum->gp_reg_found && cum->arg_number <= 2) + cum->fp_code += 2 << ((cum->arg_number - 1) * 2); + break; + + case E_DImode: + cum->gp_reg_found = 1; +- cum->arg_words += 2; ++ if (TARGET_MB_64) ++ cum->arg_words++; ++ else ++ cum->arg_words += 2; + break; + + case E_QImode: +@@ -2219,7 +2233,7 @@ compute_frame_size (HOST_WIDE_INT size) + + if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM) + /* Don't account for link register. It is accounted specially below. */ +- gp_reg_size += GET_MODE_SIZE (SImode); ++ gp_reg_size += GET_MODE_SIZE (Pmode); + + mask |= (1L << (regno - GP_REG_FIRST)); + } +@@ -2487,7 +2501,7 @@ print_operand (FILE * file, rtx op, int letter) + + if ((letter == 'M' && !WORDS_BIG_ENDIAN) + || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D') +- regnum++; ++ regnum++; + + fprintf (file, "%s", reg_names[regnum]); + } +@@ -2513,6 +2527,7 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; ++ int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2525,12 +2540,12 @@ print_operand (FILE * file, rtx op, int letter) + val[0] = l[WORDS_BIG_ENDIAN != 0]; + } + } +- else if (code == CONST_INT) ++ else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val1[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); + } + else if (code == CONST_DOUBLE) + { +@@ -2713,7 +2728,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2736,7 +2754,10 @@ microblaze_asm_destructor (rtx symbol, int priority) + + switch_to_section (get_section (section, 0, NULL)); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -2802,7 +2823,7 @@ save_restore_insns (int prologue) + /* For interrupt_handlers, need to save/restore the MSR. */ + if (microblaze_is_interrupt_variant ()) + { +- isr_mem_rtx = gen_rtx_MEM (SImode, ++ isr_mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, base_reg_rtx, + GEN_INT (current_frame_info. + gp_offset - +@@ -2810,8 +2831,8 @@ save_restore_insns (int prologue) + + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (isr_mem_rtx) = 1; +- isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG); +- isr_msr_rtx = gen_rtx_REG (SImode, ST_REG); ++ isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG); ++ isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG); + } + + if (microblaze_is_interrupt_variant () && !prologue) +@@ -2819,8 +2840,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_reg_rtx, isr_mem_rtx); + emit_move_insn (isr_msr_rtx, isr_reg_rtx); + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) +@@ -2831,9 +2852,9 @@ save_restore_insns (int prologue) + /* Don't handle here. Already handled as the first register. */ + continue; + +- reg_rtx = gen_rtx_REG (SImode, regno); ++ reg_rtx = gen_rtx_REG (Pmode, regno); + insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset)); +- mem_rtx = gen_rtx_MEM (SImode, insn); ++ mem_rtx = gen_rtx_MEM (Pmode, insn); + if (microblaze_is_interrupt_variant () || save_volatiles) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +@@ -2848,7 +2869,7 @@ save_restore_insns (int prologue) + insn = emit_move_insn (reg_rtx, mem_rtx); + } + +- gp_offset += GET_MODE_SIZE (SImode); ++ gp_offset += GET_MODE_SIZE (Pmode); + } + } + +@@ -2858,8 +2879,8 @@ save_restore_insns (int prologue) + emit_move_insn (isr_mem_rtx, isr_reg_rtx); + + /* Do not optimize in flow analysis. */ +- emit_insn (gen_rtx_USE (SImode, isr_reg_rtx)); +- emit_insn (gen_rtx_USE (SImode, isr_msr_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx)); ++ emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx)); + } + + /* Done saving and restoring */ +@@ -2949,7 +2970,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor) + + switch_to_section (s); + assemble_align (POINTER_SIZE); +- fputs ("\t.word\t", asm_out_file); ++ if (TARGET_MB_64) ++ fputs ("\t.dword\t", asm_out_file); ++ else ++ fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, symbol); + fputs ("\n", asm_out_file); + } +@@ -3095,10 +3119,10 @@ microblaze_expand_prologue (void) + { + if (offset != 0) + ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); +- emit_move_insn (gen_rtx_MEM (SImode, ptr), +- gen_rtx_REG (SImode, regno)); ++ emit_move_insn (gen_rtx_MEM (Pmode, ptr), ++ gen_rtx_REG (Pmode, regno)); + +- offset += GET_MODE_SIZE (SImode); ++ offset += GET_MODE_SIZE (Pmode); + } + + } +@@ -3108,15 +3132,23 @@ microblaze_expand_prologue (void) + rtx fsiz_rtx = GEN_INT (fsiz); + + rtx_insn *insn = NULL; +- insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ if (TARGET_MB_64) ++ { ++ ++ insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, + fsiz_rtx)); ++ } ++ else { ++ insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, ++ fsiz_rtx)); ++ } + if (insn) + RTX_FRAME_RELATED_P (insn) = 1; + + /* Handle SUB_RETURN_ADDR_REGNUM specially at first. */ + if (!crtl->is_leaf || interrupt_handler) + { +- mem_rtx = gen_rtx_MEM (SImode, ++ mem_rtx = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, + const0_rtx)); + +@@ -3124,7 +3156,7 @@ microblaze_expand_prologue (void) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; + +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + insn = emit_move_insn (mem_rtx, reg_rtx); + RTX_FRAME_RELATED_P (insn) = 1; + } +@@ -3224,12 +3256,12 @@ microblaze_expand_epilogue (void) + if (!crtl->is_leaf || interrupt_handler) + { + mem_rtx = +- gen_rtx_MEM (SImode, ++ gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx)); + if (interrupt_handler) + /* Do not optimize in flow analysis. */ + MEM_VOLATILE_P (mem_rtx) = 1; +- reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM); + emit_move_insn (reg_rtx, mem_rtx); + } + +@@ -3245,15 +3277,25 @@ microblaze_expand_epilogue (void) + /* _restore_ registers for epilogue. */ + save_restore_insns (0); + emit_insn (gen_blockage ()); +- emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); ++ else ++ emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx)); + } + + if (crtl->calls_eh_return) +- emit_insn (gen_addsi3 (stack_pointer_rtx, ++ if (TARGET_MB_64) { ++ emit_insn (gen_adddi3 (stack_pointer_rtx, + stack_pointer_rtx, +- gen_raw_REG (SImode, ++ gen_raw_REG (Pmode, + MB_EH_STACKADJ_REGNUM))); +- ++ } ++ else { ++ emit_insn (gen_addsi3 (stack_pointer_rtx, ++ stack_pointer_rtx, ++ gen_raw_REG (Pmode, ++ MB_EH_STACKADJ_REGNUM))); ++ } + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST + + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + } +@@ -3402,9 +3444,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + else + this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM); + +- /* Apply the constant offset, if required. */ ++ /* Apply the constant offset, if required. */ + if (delta) +- emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ { ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta))); ++ } + + /* Apply the offset from the vtable, if required. */ + if (vcall_offset) +@@ -3417,7 +3464,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, + rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx); + emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc)); + +- emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); ++ if (TARGET_MB_64) ++ emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1)); ++ else ++ emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1)); + } + + /* Generate a tail call to the target function. */ +@@ -3564,7 +3614,7 @@ microblaze_eh_return (rtx op0) + /* Queue an .ident string in the queue of top-level asm statements. + If the string size is below the threshold, put it into .sdata2. + If the front-end is done, we must be being called from toplev.c. +- In that case, do nothing. */ ++ In that case, do nothing. */ + void + microblaze_asm_output_ident (const char *string) + { +@@ -3619,9 +3669,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) + emit_block_move (m_tramp, assemble_trampoline_template (), + GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL); + +- mem = adjust_address (m_tramp, SImode, 16); ++ mem = adjust_address (m_tramp, Pmode, 16); + emit_move_insn (mem, chain_value); +- mem = adjust_address (m_tramp, SImode, 20); ++ mem = adjust_address (m_tramp, Pmode, 20); + emit_move_insn (mem, fnaddr); + } + +@@ -3645,7 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) ++ if (mode == Pmode) + emit_jump_insn (gen_condjump (condition, label1)); + else + emit_jump_insn (gen_long_condjump (condition, label1)); +@@ -3764,7 +3814,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[]) + rtx comp_reg = gen_reg_rtx (SImode); + + emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[3])); + } + +@@ -3774,10 +3824,10 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + rtx condition; + rtx cmp_op0 = XEXP (operands[0], 0); + rtx cmp_op1 = XEXP (operands[0], 1); +- rtx comp_reg = gen_reg_rtx (DImode); ++ rtx comp_reg = gen_reg_rtx (Pmode); + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); +- condition = gen_rtx_NE (DImode, comp_reg, const0_rtx); ++ condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); + emit_jump_insn (gen_long_condjump (condition, operands[3])); + } + +@@ -3798,8 +3848,8 @@ microblaze_expand_divide (rtx operands[]) + { + /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15). */ + +- rtx regt1 = gen_reg_rtx (SImode); +- rtx reg18 = gen_rtx_REG (SImode, R_TMP); ++ rtx regt1 = gen_reg_rtx (Pmode); ++ rtx reg18 = gen_rtx_REG (Pmode, R_TMP); + rtx regqi = gen_reg_rtx (QImode); + rtx_code_label *div_label = gen_label_rtx (); + rtx_code_label *div_end_label = gen_label_rtx (); +@@ -3807,17 +3857,31 @@ microblaze_expand_divide (rtx operands[]) + rtx mem_rtx; + rtx ret; + rtx_insn *jump, *cjump, *insn; +- +- insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); +- cjump = emit_jump_insn_after (gen_cbranchsi4 ( +- gen_rtx_GTU (SImode, regt1, GEN_INT (15)), ++ ++ if (TARGET_MB_64) { ++ insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchdi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), ++ regt1, GEN_INT (15), div_label), insn); ++ } ++ else { ++ insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2])); ++ cjump = emit_jump_insn_after (gen_cbranchsi4 ( ++ gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), + regt1, GEN_INT (15), div_label), insn); ++ } + LABEL_NUSES (div_label) = 1; + JUMP_LABEL (cjump) = div_label; +- emit_insn (gen_rtx_CLOBBER (SImode, reg18)); ++ emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + +- emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); +- emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ if (TARGET_MB_64) { ++ emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_adddi3 (regt1, regt1, operands[2])); ++ } ++ else { ++ emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_addsi3 (regt1, regt1, operands[2])); ++ } + mem_rtx = gen_rtx_MEM (QImode, + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + +@@ -3964,7 +4028,7 @@ insert_wic_for_ilb_runout (rtx_insn *first) + { + insn = + emit_insn_before (gen_iprefetch +- (gen_int_mode (addr_offset, SImode)), ++ (gen_int_mode (addr_offset, Pmode)), + before_4); + recog_memoized (insn); + INSN_LOCATION (insn) = INSN_LOCATION (before_4); +@@ -3974,7 +4038,27 @@ insert_wic_for_ilb_runout (rtx_insn *first) + } + } + } +- ++ ++/* Set the names for various arithmetic operations according to the ++ * MICROBLAZE ABI. */ ++static void ++microblaze_init_libfuncs (void) ++{ ++ set_optab_libfunc (smod_optab, SImode, "__modsi3"); ++ set_optab_libfunc (sdiv_optab, SImode, "__divsi3"); ++ set_optab_libfunc (smul_optab, SImode, "__mulsi3"); ++ set_optab_libfunc (umod_optab, SImode, "__umodsi3"); ++ set_optab_libfunc (udiv_optab, SImode, "__udivsi3"); ++ ++ if (TARGET_MB_64) ++ { ++ set_optab_libfunc (smod_optab, DImode, "__moddi3"); ++ set_optab_libfunc (sdiv_optab, DImode, "__divdi3"); ++ set_optab_libfunc (smul_optab, DImode, "__muldi3"); ++ set_optab_libfunc (umod_optab, DImode, "__umoddi3"); ++ set_optab_libfunc (udiv_optab, DImode, "__udivdi3"); ++ } ++} + /* Insert instruction prefetch instruction at the fall + through path of the function call. */ + +@@ -4127,6 +4211,17 @@ microblaze_starting_frame_offset (void) + #undef TARGET_LRA_P + #define TARGET_LRA_P hook_bool_void_false + ++#ifdef TARGET_MB_64 ++#undef TARGET_ASM_ALIGNED_DI_OP ++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" ++ ++#undef TARGET_ASM_ALIGNED_HI_OP ++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" ++ ++#undef TARGET_ASM_ALIGNED_SI_OP ++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" ++#endif ++ + #undef TARGET_FRAME_POINTER_REQUIRED + #define TARGET_FRAME_POINTER_REQUIRED microblaze_frame_pointer_required + +@@ -4136,6 +4231,9 @@ microblaze_starting_frame_offset (void) + #undef TARGET_TRAMPOLINE_INIT + #define TARGET_TRAMPOLINE_INIT microblaze_trampoline_init + ++#undef TARGET_INIT_LIBFUNCS ++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs ++ + #undef TARGET_PROMOTE_FUNCTION_MODE + #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 72fbee5..1e60513 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe; + + /* Generate DWARF exception handling info. */ + #define DWARF2_UNWIND_INFO 1 +- + /* Don't generate .loc operations. */ + #define DWARF2_ASM_LINE_DEBUG_INFO 0 + +@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe; + ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr) + + /* Use DWARF 2 debugging information by default. */ +-#define DWARF2_DEBUGGING_INFO ++#define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG ++#define DWARF2_ADDR_SIZE 4 + + /* Target machine storage layout */ + + #define BITS_BIG_ENDIAN 0 + #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) + #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) +-#define BITS_PER_WORD 32 +-#define UNITS_PER_WORD 4 ++//#define BITS_PER_WORD 64 ++//Revisit ++#define MAX_BITS_PER_WORD 64 ++#define UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define MIN_UNITS_PER_WORD (TARGET_MB_64 ? 8 : 4) ++//#define UNITS_PER_WORD 4 + #define MIN_UNITS_PER_WORD 4 + #define INT_TYPE_SIZE 32 + #define SHORT_TYPE_SIZE 16 +-#define LONG_TYPE_SIZE 64 ++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32) + #define LONG_LONG_TYPE_SIZE 64 + #define FLOAT_TYPE_SIZE 32 + #define DOUBLE_TYPE_SIZE 64 + #define LONG_DOUBLE_TYPE_SIZE 64 +-#define POINTER_SIZE 32 +-#define PARM_BOUNDARY 32 +-#define FUNCTION_BOUNDARY 32 +-#define EMPTY_FIELD_BOUNDARY 32 ++#define POINTER_SIZE (TARGET_MB_64 ? 64 : 32) ++//#define WIDEST_HARDWARE_FP_SIZE 64 ++//#define POINTERS_EXTEND_UNSIGNED 1 ++#define PARM_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define FUNCTION_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++#define EMPTY_FIELD_BOUNDARY (TARGET_MB_64 ? 64 : 32) + #define STRUCTURE_SIZE_BOUNDARY 8 +-#define BIGGEST_ALIGNMENT 32 ++#define BIGGEST_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + #define STRICT_ALIGNMENT 1 + #define PCC_BITFIELD_TYPE_MATTERS 1 + ++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode) + #undef SIZE_TYPE +-#define SIZE_TYPE "unsigned int" ++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #undef PTRDIFF_TYPE +-#define PTRDIFF_TYPE "int" ++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int") ++ ++/*#undef INTPTR_TYPE ++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/ ++#undef UINTPTR_TYPE ++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int") + + #define DATA_ALIGNMENT(TYPE, ALIGN) \ + ((((ALIGN) < BITS_PER_WORD) \ +@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +- ++/* + #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < 4) \ +- (MODE) = SImode; +- ++ && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ ++ (MODE) = TARGET_MB_64 ? DImode : SImode; ++*/ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info; + #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD) + + #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 ++#define DWARF_CIE_DATA_ALIGNMENT -1 + + #define REG_PARM_STACK_SPACE(FNDECL) microblaze_reg_parm_stack_space(FNDECL) + + #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 + +-#define STACK_BOUNDARY 32 ++#define STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) + ++#define PREFERRED_STACK_BOUNDARY (TARGET_MB_64 ? 64 : 32) ++ + #define NUM_OF_ARGS 6 + + #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM) +@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info; + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + + #define LIBCALL_VALUE(MODE) \ ++ gen_rtx_REG (MODE,GP_RETURN) ++ ++/*#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +- ++*/ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -500,7 +518,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 32 ++#define TRAMPOLINE_ALIGNMENT 64 + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +@@ -533,13 +551,13 @@ typedef struct microblaze_args + addresses which require two reload registers. */ + #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X) + +-#define CASE_VECTOR_MODE (SImode) ++#define CASE_VECTOR_MODE (TARGET_MB_64? DImode:SImode) + + #ifndef DEFAULT_SIGNED_CHAR + #define DEFAULT_SIGNED_CHAR 1 + #endif + +-#define MOVE_MAX 4 ++#define MOVE_MAX (TARGET_MB_64 ? 8 : 4) + #define MAX_MOVE_MAX 8 + + #define SLOW_BYTE_ACCESS 1 +@@ -549,7 +567,7 @@ typedef struct microblaze_args + + #define SHIFT_COUNT_TRUNCATED 1 + +-#define Pmode SImode ++#define Pmode (TARGET_MB_64? DImode:SImode) + + #define FUNCTION_MODE SImode + +@@ -711,6 +729,7 @@ do { \ + + #undef TARGET_ASM_OUTPUT_IDENT + #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident ++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive + + /* Default to -G 8 */ + #ifndef MICROBLAZE_DEFAULT_GVALUE +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0cd0441..0f41ac6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -26,6 +26,7 @@ + ;; Constants + ;;---------------------------------------------------- + (define_constants [ ++ (R_Z 0) ;; For reg r0 + (R_SP 1) ;; Stack pointer reg + (R_SR 15) ;; Sub-routine return addr reg + (R_IR 14) ;; Interrupt return addr reg +@@ -539,6 +540,7 @@ + + ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ] + ;; Leave carry as is ++ + (define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d") + (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ") +@@ -560,23 +562,38 @@ + + ;; Adding 2 DI operands in register or reg/imm + +-(define_insn "adddi3_long" ++(define_expand "adddi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (plus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_plus_operand" "")))] ++"" ++{ ++ if (TARGET_MB_64) ++ { ++ if (GET_CODE (operands[2]) == CONST_INT && ++ INTVAL(operands[2]) < (long)-549755813888 && ++ INTVAL(operands[2]) > (long)549755813887) ++ FAIL; ++ } ++}) ++ ++(define_insn "*adddi3_long" + [(set (match_operand:DI 0 "register_operand" "=d,d") +- (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ") ++ (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_plus_operand" "d,K")))] + "TARGET_MB_64" + "@ +- addlk\t%0,%z1,%2 +- addlik\t%0,%z1,%2" +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") ++ addlk\t%0,%1,%2 ++ addlik\t%0,%1,%2 #N10" ++ [(set_attr "type" "darith,no_delay_arith") ++ (set_attr "mode" "DI") + (set_attr "length" "4,4")]) + +-(define_insn "adddi3" ++(define_insn "*adddi3_all" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (plus:DI (match_operand:DI 1 "register_operand" "%d,d") + (match_operand:DI 2 "arith_operand" "d,i")))] +- "" ++ "!TARGET_MB_64" + "@ + add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2 + addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2" +@@ -603,7 +620,7 @@ + (define_insn "iprefetch" + [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH) + (clobber (mem:BLK (scratch)))] +- "TARGET_PREFETCH" ++ "TARGET_PREFETCH && !TARGET_MB_64" + { + operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + return "mfs\t%2,rpc\n\twic\t%2,r0"; +@@ -616,23 +633,33 @@ + ;; Double Precision Subtraction + ;;---------------------------------------------------------------- + +-(define_insn "subdi3_long" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (minus:DI (match_operand:DI 1 "register_operand" "d,d") +- (match_operand:DI 2 "register_operand" "d,n")))] ++(define_expand "subdi3" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (minus:DI (match_operand:DI 1 "register_operand" "") ++ (match_operand:DI 2 "arith_operand" "")))] ++"" ++" ++{ ++}") ++ ++(define_insn "subsidi3" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (minus:DI (match_operand:DI 1 "register_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,n")))] + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addlik\t%0,%z1,-%2" +- [(set_attr "type" "darith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ addik\t%0,%z1,-%2 ++ addik\t%0,%z1,-%2" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,4")]) + +-(define_insn "subdi3" ++(define_insn "subdi3_small" + [(set (match_operand:DI 0 "register_operand" "=&d") + (minus:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "" ++ "!TARGET_MB_64" + "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1" + [(set_attr "type" "darith") + (set_attr "mode" "DI") +@@ -661,7 +688,7 @@ + (mult:DI + (sign_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -672,7 +699,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -683,7 +710,7 @@ + (mult:DI + (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) + (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))] +- "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH" ++ "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64" + "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1" + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -787,7 +814,7 @@ + (match_operand:SI 4 "arith_operand")]) + (label_ref (match_operand 5)) + (pc)))] +- "TARGET_HARD_FLOAT" ++ "TARGET_HARD_FLOAT && !TARGET_MB_64" + [(set (match_dup 1) (match_dup 3))] + + { +@@ -817,6 +844,15 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + ++(define_insn "negsi_long" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (neg:SI (match_operand:DI 1 "register_operand" "d")))] ++ "" ++ "rsubk\t%0,%1,r0" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")]) ++ + (define_insn "negdi2_long" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (match_operand:DI 1 "register_operand" "d")))] +@@ -845,16 +881,24 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_insn "one_cmpldi2_long" ++(define_expand "one_cmpldi2" ++ [(set (match_operand:DI 0 "register_operand" "") ++ (not:DI (match_operand:DI 1 "register_operand" "")))] ++ "" ++ " ++{ ++}") ++ ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") +- (not:DI (match_operand:DI 1 "register_operand" "d")))] ++ (not:DI (match_operand:DI 1 "arith_operand" "d")))] + "TARGET_MB_64" + "xorli\t%0,%1,-1" +- [(set_attr "type" "arith") ++ [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4")]) + +-(define_insn "*one_cmpldi2" ++(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d") + (not:DI (match_operand:DI 1 "register_operand" "d")))] + "" +@@ -869,7 +913,8 @@ + (not:DI (match_operand:DI 1 "register_operand" "")))] + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) +- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))" ++ && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) ++ && !TARGET_MB_64" + + [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0))) + (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))] +@@ -881,18 +926,17 @@ + ;;---------------------------------------------------------------- + + (define_insn "anddi3" +- [(set (match_operand:DI 0 "register_operand" "=d,d") +- (and:DI (match_operand:DI 1 "arith_operand" "d,d") +- (match_operand:DI 2 "arith_operand" "d,K")))] ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (and:DI (match_operand:DI 1 "arith_operand" "d,d,d") ++ (match_operand:DI 2 "arith_operand" "d,K,I")))] + "TARGET_MB_64" + "@ + andl\t%0,%1,%2 +- andli\t%0,%1,%2 #andl1" +- ;; andli\t%0,%1,%2 #andl3 +- ;; andli\t%0,%1,%2 #andl2 +- [(set_attr "type" "arith,arith") +- (set_attr "mode" "DI,DI") +- (set_attr "length" "4,4")]) ++ andli\t%0,%1,%2 #andl2 ++ andli\t%0,%1,%2 #andl3" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI,DI,DI") ++ (set_attr "length" "4,4,4")]) + + (define_insn "andsi3" + [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") +@@ -917,7 +961,7 @@ + "@ + orl\t%0,%1,%2 + orli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -943,7 +987,7 @@ + "@ + xorl\t%0,%1,%2 + xorli\t%0,%1,%2 #andl1" +- [(set_attr "type" "arith,arith") ++ [(set_attr "type" "arith,no_delay_arith") + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")]) + +@@ -1016,26 +1060,6 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-;;(define_expand "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))] +-;; "TARGET_MB_64" +-;; { +-;; if (GET_CODE (operands[1]) != REG) +-;; FAIL; +-;; } +-;;) +- +- +-;;(define_insn "extendqidi2" +-;; [(set (match_operand:DI 0 "register_operand" "=d") +-;; (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))] +-;; "TARGET_MB_64" +-;; "sextl8\t%0,%1" +-;; [(set_attr "type" "arith") +-;; (set_attr "mode" "DI") +-;; (set_attr "length" "4")]) +- + (define_insn "extendhisi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (sign_extend:SI (match_operand:HI 1 "register_operand" "d")))] +@@ -1058,6 +1082,27 @@ + ;; Those for integer source operand are ordered + ;; widest source type first. + ++(define_insn "extendsidi2_long" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,d") ++ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "sextl32\t%0,%1"; ++ case 1: ++ case 2: ++ { ++ output_asm_insn ("ll%i1\t%0,%1", operands); ++ return "sextl32\t%0,%0"; ++ } ++ } ++ } ++ [(set_attr "type" "multi,multi,multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,8,8")]) ++ + (define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=d,d,d") + (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))] +@@ -1088,68 +1133,117 @@ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. ++;; //} + + (define_expand "movdi" + [(set (match_operand:DI 0 "nonimmediate_operand" "") + (match_operand:DI 1 "general_operand" ""))] + "" + { +- /* If operands[1] is a constant address illegal for pic, then we need to +- handle it just like microblaze_legitimize_address does. */ +- if (flag_pic && pic_address_needs_scratch (operands[1])) ++ if (TARGET_MB_64) ++ { ++ if (microblaze_expand_move (DImode, operands)) DONE; ++ } ++ else + { ++ /* If operands[1] is a constant address illegal for pic, then we need to ++ handle it just like microblaze_legitimize_address does. */ ++ if (flag_pic && pic_address_needs_scratch (operands[1])) ++ { + rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0)); + rtx temp2 = XEXP (XEXP (operands[1], 0), 1); + emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2)); + DONE; +- } +- +- +- if ((reload_in_progress | reload_completed) == 0 +- && !register_operand (operands[0], DImode) +- && !register_operand (operands[1], DImode) +- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) +- && operands[1] != CONST0_RTX (DImode)))) +- { ++ } + +- rtx temp = force_reg (DImode, operands[1]); +- emit_move_insn (operands[0], temp); +- DONE; ++ if ((reload_in_progress | reload_completed) == 0 ++ && !register_operand (operands[0], DImode) ++ && !register_operand (operands[1], DImode) ++ && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0) ++ && operands[1] != CONST0_RTX (DImode)))) ++ { ++ rtx temp = force_reg (DImode, operands[1]); ++ emit_move_insn (operands[0], temp); ++ DONE; ++ } + } + } + ) + ++;; Added for status registers ++(define_insn "movdi_status" ++ [(set (match_operand:DI 0 "register_operand" "=d,d,z") ++ (match_operand:DI 1 "register_operand" "z,d,d"))] ++ "microblaze_is_interrupt_variant () && TARGET_MB_64" ++ "@ ++ mfs\t%0,%1 #mfs ++ addlk\t%0,%1,r0 #add movdi ++ mts\t%0,%1 #mts" ++ [(set_attr "type" "move") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) + +-(define_insn "*movdi_internal_64" +- [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") +- (match_operand:DI 1 "general_operand" " d,K,J,R,o,d,d"))] +- "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)" ++;; This move will be not be moved to delay slot. ++(define_insn "*movdi_internal3" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d") ++ (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] ++ "TARGET_MB_64 && (register_operand (operands[0], DImode) && ++ (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ "@ ++ addlk\t%0,r0,r0\t ++ addlik\t%0,r0,%1\t #N1 %X1 ++ addlik\t%0,r0,%1\t #N2 %X1" ++ [(set_attr "type" "arith,no_delay_arith,no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++;; This move may be used for PLT label operand ++(define_insn "*movdi_internal5_pltop" ++ [(set (match_operand:DI 0 "register_operand" "=d,d") ++ (match_operand:DI 1 "call_insn_operand" ""))] ++ "TARGET_MB_64 && (register_operand (operands[0], Pmode) && ++ PLT_ADDR_P (operands[1]))" ++ { ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "load") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")]) ++ ++(define_insn "*movdi_internal2" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64" + { + switch (which_alternative) + { + case 0: +- return "addlk\t%0,%1"; +- case 1: +- return "addlik\t%0,r0,%1"; +- case 2: +- return "addlk\t%0,r0,r0"; +- case 3: +- case 4: +- return "lli\t%0,%1"; +- case 5: +- case 6: +- return "sli\t%1,%0"; +- } +- return "unreachable"; +- } +- [(set_attr "type" "no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") + (set_attr "mode" "DI") +- (set_attr "length" "8,8,8,8,12,8,12")]) ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + + (define_insn "*movdi_internal" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o") + (match_operand:DI 1 "general_operand" " d,i,J,R,o,d,d"))] +- "" ++ "!TARGET_MB_64" + { + switch (which_alternative) + { +@@ -1181,7 +1275,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))" ++ && (REGNO(operands[0]) == (REGNO(operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] +@@ -1193,12 +1288,22 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !(TARGET_MB_64)" + + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") + ++(define_insn "movdi_long_int" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d") ++ (match_operand:DI 1 "general_operand" "i"))] ++ "" ++ "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "12")]) ++ + ;; Unlike most other insns, the move insns can't be split with + ;; different predicates, because register spilling and other parts of + ;; the compiler, have memoized the insn number already. +@@ -1270,6 +1375,8 @@ + (set_attr "length" "4,4,8,4,8,4,8")]) + + ++ ++ + ;; 16-bit Integer moves + + ;; Unlike most other insns, the move insns can't be split with +@@ -1302,8 +1409,8 @@ + "@ + addik\t%0,r0,%1\t# %X1 + addk\t%0,%1,r0 +- lhui\t%0,%1 +- lhui\t%0,%1 ++ lhu%i1\t%0,%1 ++ lhu%i1\t%0,%1 + sh%i0\t%z1,%0 + sh%i0\t%z1,%0" + [(set_attr "type" "arith,move,load,no_delay_load,store,no_delay_store") +@@ -1346,7 +1453,7 @@ + lbu%i1\t%0,%1 + lbu%i1\t%0,%1 + sb%i0\t%z1,%0 +- sbi\t%z1,%0" ++ sb%i0\t%z1,%0" + [(set_attr "type" "arith,arith,move,load,no_delay_load,store,no_delay_store") + (set_attr "mode" "QI") + (set_attr "length" "4,4,8,4,8,4,8")]) +@@ -1419,7 +1526,7 @@ + addik\t%0,r0,%F1 + lw%i1\t%0,%1 + sw%i0\t%z1,%0 +- swi\t%z1,%0" ++ sw%i0\t%z1,%0" + [(set_attr "type" "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store") + (set_attr "mode" "SF") + (set_attr "length" "4,4,4,4,4,4,4")]) +@@ -1458,6 +1565,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o") + (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))] +@@ -1492,7 +1626,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) == (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4)) + (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))] + "") +@@ -1503,7 +1638,8 @@ + "reload_completed + && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) +- && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))" ++ && (REGNO (operands[0]) != (REGNO (operands[1]) + 1)) ++ && !TARGET_MB_64" + [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0)) + (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))] + "") +@@ -2003,6 +2139,31 @@ else + " + ) + ++ ++(define_insn "seq_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (eq:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmpleq\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "sne_internal_pat_long" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (ne:DI ++ (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "pcmplne\t%0,%1,%2" ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4")] ++) ++ + (define_insn "seq_internal_pat" + [(set (match_operand:SI 0 "register_operand" "=d") + (eq:SI +@@ -2063,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "arith_operand" "I,i")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +@@ -2076,13 +2237,13 @@ else + (define_expand "cbranchsi4_reg" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand:SI 1 "register_operand") +- (match_operand:SI 2 "register_operand")]) ++ [(match_operand 1 "register_operand") ++ (match_operand 2 "register_operand")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" + { +- microblaze_expand_conditional_branch_reg (SImode, operands); ++ microblaze_expand_conditional_branch_reg (Pmode, operands); + DONE; + }) + +@@ -2107,6 +2268,26 @@ else + (label_ref (match_operand 1)) + (pc)))]) + ++(define_insn "branch_zero64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "ordered_comparison_operator" ++ [(match_operand 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ + (define_insn "branch_zero" + [(set (pc) + (if_then_else (match_operator:SI 0 "ordered_comparison_operator" +@@ -2127,6 +2308,47 @@ else + (set_attr "length" "4")] + ) + ++(define_insn "branch_compare64" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:SI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmp\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmpu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmp\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmpu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx); ++ return "bea%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2310,7 +2532,7 @@ else + ;; Indirect jumps. Jump to register values. Assuming absolute jumps + + (define_insn "indirect_jump_internal1" +- [(set (pc) (match_operand:SI 0 "register_operand" "d"))] ++ [(set (pc) (match_operand 0 "register_operand" "d"))] + "" + "bra%?\t%0" + [(set_attr "type" "jump") +@@ -2323,7 +2545,7 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- gcc_assert (GET_MODE (operands[0]) == Pmode); ++ //gcc_assert (GET_MODE (operands[0]) == Pmode); + + if (!flag_pic) + emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +@@ -2335,7 +2557,7 @@ else + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand:SI 0 "register_operand" "d")) ++ (match_operand 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2345,9 +2567,9 @@ else + + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus:SI (match_operand:SI 0 "register_operand" "d") +- (label_ref:SI (match_operand:SI 1 "" "")))) +- (use (label_ref:SI (match_dup 1)))])] ++ (plus (match_operand 0 "register_operand" "d") ++ (label_ref (match_operand:SI 1 "" "")))) ++ (use (label_ref (match_dup 1)))])] + "" + "" + ) +@@ -2408,7 +2630,7 @@ else + (minus (reg 1) (match_operand 1 "register_operand" ""))) + (set (reg 1) + (minus (reg 1) (match_dup 1)))] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx reg = gen_reg_rtx (Pmode); +@@ -2433,7 +2655,7 @@ else + (define_expand "save_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + emit_move_insn (operands[0], operands[1]); + DONE; +@@ -2443,7 +2665,7 @@ else + (define_expand "restore_stack_block" + [(match_operand 0 "register_operand" "") + (match_operand 1 "register_operand" "")] +- "" ++ "!TARGET_MB_64" + { + rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx); + rtx rtmp = gen_rtx_REG (SImode, R_TMP); +@@ -2490,7 +2712,7 @@ else + + (define_insn "<optab>_internal" + [(any_return) +- (use (match_operand:SI 0 "register_operand" ""))] ++ (use (match_operand 0 "register_operand" ""))] + "" + { + if (microblaze_is_break_handler ()) +@@ -2523,7 +2745,7 @@ else + (define_expand "call" + [(parallel [(call (match_operand 0 "memory_operand" "m") + (match_operand 1 "" "i")) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 2 "" "")) + (use (match_operand 3 "" ""))])] + "" +@@ -2543,12 +2765,12 @@ else + + if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC) + emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_internal0 (operands[0], operands[1], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2558,7 +2780,7 @@ else + (define_expand "call_internal0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" ""))])] ++ (clobber (match_operand 2 "" ""))])] + "" + { + } +@@ -2567,18 +2789,34 @@ else + (define_expand "call_internal_plt0" + [(parallel [(call (match_operand 0 "" "") + (match_operand 1 "" "")) +- (clobber (match_operand:SI 2 "" "")) +- (use (match_operand:SI 3 "" ""))])] ++ (clobber (match_operand 2 "" "")) ++ (use (match_operand 3 "" ""))])] + "" + { + } + ) + ++(define_insn "call_internal_plt_64" ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal_plt" +- [(call (mem (match_operand:SI 0 "call_insn_plt_operand" "")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR)) +- (use (reg:SI R_GOT))] ++ [(call (mem (match_operand 0 "call_insn_plt_operand" "")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR)) ++ (use (reg R_GOT))] + "flag_pic" + { + register rtx target2 = gen_rtx_REG (Pmode, +@@ -2590,10 +2828,41 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_internal1_64" ++ [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[0]; ++ register rtx target2 = gen_rtx_REG (Pmode, ++ GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ if (GET_CODE (target) == SYMBOL_REF) { ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "breaki\tr16,%0\;%#"; ++ } ++ else { ++ gen_rtx_CLOBBER (VOIDmode, target2); ++ return "brealid\tr15,%0\;%#"; ++ } ++ } else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%0\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%0\;%#"; ++ else { ++ fprintf (stderr,"Unsupported call insn\n"); ++ return NULL; ++ } ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_internal1" + [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri")) +- (match_operand:SI 1 "" "i")) +- (clobber (reg:SI R_SR))] ++ (match_operand 1 "" "i")) ++ (clobber (reg R_SR))] + "" + { + register rtx target = operands[0]; +@@ -2627,7 +2896,7 @@ else + [(parallel [(set (match_operand 0 "register_operand" "=d") + (call (match_operand 1 "memory_operand" "m") + (match_operand 2 "" "i"))) +- (clobber (reg:SI R_SR)) ++ (clobber (reg R_SR)) + (use (match_operand 3 "" ""))])] ;; next_arg_reg + "" + { +@@ -2647,13 +2916,13 @@ else + if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC) + emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM), + pic_offset_table_rtx)); + else + emit_call_insn (gen_call_value_internal (operands[0], operands[1], + operands[2], +- gen_rtx_REG (SImode, ++ gen_rtx_REG (Pmode, + GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM))); + + DONE; +@@ -2665,7 +2934,7 @@ else + [(parallel [(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) ++ (clobber (match_operand 3 "" "")) + ])] + "" + {} +@@ -2675,18 +2944,35 @@ else + [(parallel[(set (match_operand 0 "" "") + (call (match_operand 1 "" "") + (match_operand 2 "" ""))) +- (clobber (match_operand:SI 3 "" "")) +- (use (match_operand:SI 4 "" ""))])] ++ (clobber (match_operand 3 "" "")) ++ (use (match_operand 4 "" ""))])] + "flag_pic" + {} + ) + ++(define_insn "call_value_intern_plt_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] ++ "flag_pic && TARGET_MB_64" ++ { ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ return "brealid\tr15,%1\;%#"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern_plt" + [(set (match_operand:VOID 0 "register_operand" "=d") +- (call (mem (match_operand:SI 1 "call_insn_plt_operand" "")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d")) +- (use (match_operand:SI 4 "register_operand"))] ++ (call (mem (match_operand 1 "call_insn_plt_operand" "")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d")) ++ (use (match_operand 4 "register_operand"))] + "flag_pic" + { + register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); +@@ -2698,11 +2984,46 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "call_value_intern_64" ++ [(set (match_operand:VOID 0 "register_operand" "=d") ++ (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] ++ "TARGET_MB_64" ++ { ++ register rtx target = operands[1]; ++ register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM); ++ ++ if (GET_CODE (target) == SYMBOL_REF) ++ { ++ gen_rtx_CLOBBER (VOIDmode,target2); ++ if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) ++ return "breaki\tr16,%1\;%#"; ++ else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION) ++ { ++ return "brealid\tr15,%1\;%#"; ++ } ++ else ++ { ++ return "bralid\tr15,%1\;%#"; ++ } ++ } ++ else if (GET_CODE (target) == CONST_INT) ++ return "la\t%@,r0,%1\;brald\tr15,%@\;%#"; ++ else if (GET_CODE (target) == REG) ++ return "brald\tr15,%1\;%#"; ++ else ++ return "Unsupported call insn\n"; ++ } ++ [(set_attr "type" "call") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "call_value_intern" + [(set (match_operand:VOID 0 "register_operand" "=d") + (call (mem (match_operand:VOID 1 "call_insn_operand" "ri")) +- (match_operand:SI 2 "" "i"))) +- (clobber (match_operand:SI 3 "register_operand" "=d"))] ++ (match_operand 2 "" "i"))) ++ (clobber (match_operand 3 "register_operand" "=d"))] + "" + { + register rtx target = operands[1]; +@@ -2864,7 +3185,6 @@ else + + ;;if (!register_operand (operands[0], VOIDmode)) + ;; FAIL; +- + emit_insn (gen_insv_32 (operands[0], operands[1], + operands[2], operands[3])); + DONE; +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 7671f63..9fc80b1 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en + MULTILIB_DIRNAMES = bs m mh le m64 + MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high + MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 ++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 2e15be4..3386520 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -40,7 +40,7 @@ + + .align 2 + __init: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 + la r11, r0, _stack + mts rshr, r11 +@@ -51,5 +51,5 @@ __init: + .global __fini + .align 2 + __fini: +- addik r1, r1, -8 ++ addik r1, r1, -16 + sw r15, r0, r1 +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index cd5fd9e..04e73d7 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -33,9 +33,9 @@ + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 + + .section .fini, "ax" + lw r15, r0, r1 + rtsd r15, 8 +- addik r1, r1, 8 ++ addik r1, r1, 16 +diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S +new file mode 100644 +index 0000000..d37bf51 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3.S +@@ -0,0 +1,98 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# divdi3.S ++# ++# Divide operation for 32 bit integers. ++# Input : Dividend in Reg r5 ++# Divisor in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __divdi3 ++ .ent __divdi3 ++ .type __divdi3,@function ++__divdi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ XORL r28,r5,r6 # Get the sign of the result ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r30,r0,0 # Clear mod ++ ADDLIK r3,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ RSUBLI r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ nop ++.end __divdi3 ++ .size __divdi3, . - __divdi3 ++#endif +diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c +new file mode 100644 +index 0000000..8096259 +--- /dev/null ++++ b/libgcc/config/microblaze/divdi3_table.c +@@ -0,0 +1,62 @@ ++/* Table for software lookup divide for Xilinx MicroBlaze. ++ ++ Copyright (C) 2009-2017 Free Software Foundation, Inc. ++ ++ Contributed by Michael Eager <eager@eagercon.com>. ++ ++ This file is free software; you can redistribute it and/or modify it ++ under the terms of the GNU General Public License as published by the ++ Free Software Foundation; either version 3, or (at your option) any ++ later version. ++ ++ GCC is distributed in the hope that it will be useful, but WITHOUT ++ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++ License for more details. ++ ++ Under Section 7 of GPL version 3, you are granted additional ++ permissions described in the GCC Runtime Library Exception, version ++ 3.1, as published by the Free Software Foundation. ++ ++ You should have received a copy of the GNU General Public License and ++ a copy of the GCC Runtime Library Exception along with this program; ++ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++ <http://www.gnu.org/licenses/>. */ ++ ++ ++unsigned char _divdi3_table[] = ++{ ++ 0, 0/1, 0/2, 0/3, 0/4, 0/5, 0/6, 0/7, ++ 0/8, 0/9, 0/10, 0/11, 0/12, 0/13, 0/14, 0/15, ++ 0, 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ++ 1/8, 1/9, 1/10, 1/11, 1/12, 1/13, 1/14, 1/15, ++ 0, 2/1, 2/2, 2/3, 2/4, 2/5, 2/6, 2/7, ++ 2/8, 2/9, 2/10, 2/11, 2/12, 2/13, 2/14, 2/15, ++ 0, 3/1, 3/2, 3/3, 3/4, 3/5, 3/6, 3/7, ++ 3/8, 3/9, 3/10, 3/11, 3/12, 3/13, 3/14, 3/15, ++ 0, 4/1, 4/2, 4/3, 4/4, 4/5, 4/6, 4/7, ++ 4/8, 4/9, 4/10, 4/11, 4/12, 4/13, 4/14, 4/15, ++ 0, 5/1, 5/2, 5/3, 5/4, 5/5, 5/6, 5/7, ++ 5/8, 5/9, 5/10, 5/11, 5/12, 5/13, 5/14, 5/15, ++ 0, 6/1, 6/2, 6/3, 6/4, 6/5, 6/6, 6/7, ++ 6/8, 6/9, 6/10, 6/11, 6/12, 6/13, 6/14, 6/15, ++ 0, 7/1, 7/2, 7/3, 7/4, 7/5, 7/6, 7/7, ++ 7/8, 7/9, 7/10, 7/11, 7/12, 7/13, 7/14, 7/15, ++ 0, 8/1, 8/2, 8/3, 8/4, 8/5, 8/6, 8/7, ++ 8/8, 8/9, 8/10, 8/11, 8/12, 8/13, 8/14, 8/15, ++ 0, 9/1, 9/2, 9/3, 9/4, 9/5, 9/6, 9/7, ++ 9/8, 9/9, 9/10, 9/11, 9/12, 9/13, 9/14, 9/15, ++ 0, 10/1, 10/2, 10/3, 10/4, 10/5, 10/6, 10/7, ++ 10/8, 10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15, ++ 0, 11/1, 11/2, 11/3, 11/4, 11/5, 11/6, 11/7, ++ 11/8, 11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15, ++ 0, 12/1, 12/2, 12/3, 12/4, 12/5, 12/6, 12/7, ++ 12/8, 12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15, ++ 0, 13/1, 13/2, 13/3, 13/4, 13/5, 13/6, 13/7, ++ 13/8, 13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15, ++ 0, 14/1, 14/2, 14/3, 14/4, 14/5, 14/6, 14/7, ++ 14/8, 14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15, ++ 0, 15/1, 15/2, 15/3, 15/4, 15/5, 15/6, 15/7, ++ 15/8, 15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15, ++}; ++ +diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S +new file mode 100644 +index 0000000..5d3f7c0 +--- /dev/null ++++ b/libgcc/config/microblaze/moddi3.S +@@ -0,0 +1,97 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# moddi3.S ++# ++# modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __moddi3 ++ .ent __moddi3 ++ .type __moddi3,@function ++__moddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,32 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDL r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] ++ BEALGEI r5,$LaR5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$LaR5_Pos: ++ BEALGEI r6,$LaR6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$LaR6_Pos: ++ ADDLIK r3,r0,0 # Clear mod ++ ADDLIK r30,r0,0 # clear div ++ ADDLIK r29,r0,64 # Initialize the loop count ++ BEALLTI r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++ # First part try to find the first '1' in the r5 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r30 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEALGEI r28,$LaRETURN_HERE ++ rsubli r3,r3,0 # Negate the result ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addlik r1,r1,32 ++ rtsd r15,8 ++ nop ++ .end __moddi3 ++ .size __moddi3, . - __moddi3 ++#endif +diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S +new file mode 100644 +index 0000000..5677841 +--- /dev/null ++++ b/libgcc/config/microblaze/muldi3.S +@@ -0,0 +1,73 @@ ++/*###################################-*-asm*- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# muldi3.S ++# ++# Multiply operation for 32 bit integers. ++# Input : Operand1 in Reg r5 ++# Operand2 in Reg r6 ++# Output: Result [op1 * op2] in Reg r3 ++# ++#######################################*/ ++ ++#ifdef __arch64__ ++ .globl __muldi3 ++ .ent __muldi3 ++ .type __muldi3,@function ++__muldi3: ++ .frame r1,0,r15 ++ addl r3,r0,r0 ++ BEALEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEALEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ XORL r4,r5,r6 # Get the sign of the result ++ BEALGEI r5,$L_R5_Pos ++ RSUBLI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEALGEI r6,$L_R6_Pos ++ RSUBLI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ addl r5,r5,r5 ++$L1: ++ srll r6,r6 ++ addlc r7,r0,r0 ++ bealeqi r7,$L2 ++ addl r3,r3,r5 ++ bealnei r6,$L2 ++ beallti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rsubl r3,r3,r0 ++ rtsd r15,8 ++ nop ++$L_Result_Is_Zero: ++ addli r3,r0,0 ++ rtsd r15,8 ++ nop ++ .end __muldi3 ++ .size __muldi3, . - __muldi3 ++#endif +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 8d954a4..35021b2 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,11 +1,16 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ ++ _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ ++ $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/muldi3_hard.S \ ++ $(srcdir)/config/microblaze/moddi3.S \ + $(srcdir)/config/microblaze/mulsi3.S \ ++ $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ ++ $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c ++ $(srcdir)/config/microblaze/umoddi3.S \ ++ $(srcdir)/config/microblaze/divsi3_table.c \ +diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S +new file mode 100644 +index 0000000..c210fbc +--- /dev/null ++++ b/libgcc/config/microblaze/udivdi3.S +@@ -0,0 +1,107 @@ ++###################################- ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# udivdi3.S ++# ++# Unsigned divide operation. ++# Input : Divisor in Reg r5 ++# Dividend in Reg r6 ++# Output: Result in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __udivdi3 ++ .ent __udivdi3 ++ .type __udivdi3,@function ++__udivdi3: ++ .frame r1,0,r15 ++ ++ ADDlIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r30,r0,0 # Clear mod ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++ # Check if r6 and r5 are equal # if yes, return 1 ++ RSUBL r18,r5,r6 ++ ADDLIK r3,r0,1 ++ BEALEQI r18,$LaRETURN_HERE ++ ++ # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 ++ XORL r18,r5,r6 ++ ADDL r3,r0,r0 # We would anyways clear r3 ++ BEALGEI r18,$LRSUBL ++ BEALLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++$LRSUBL: ++ RSUBL r18,r6,r5 # MICROBLAZEcmp ++ BEALLTI r18,$LaRETURN_HERE ++ ++ # If r6 [bit 31] is set, then return result as 1 ++$LCheckr6: ++ BEALGTI r6,$LaDIV0 ++ ADDLIK r3,r0,1 ++ BREAI $LaRETURN_HERE ++ ++ # First part try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGTI r5,$LaDIV1 ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r30,r30,r30 # Move that bit into the Mod register ++ RSUBL r31,r6,r30 # Try to subtract (r30 a r6) ++ BEALLTI r31,$LaMOD_TOO_SMALL ++ ORL r30,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r3,r3,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ ORL r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDLIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++ .end __udivdi3 ++ .size __udivdi3, . - __udivdi3 ++#endif +diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S +new file mode 100644 +index 0000000..7f5cd23 +--- /dev/null ++++ b/libgcc/config/microblaze/umoddi3.S +@@ -0,0 +1,110 @@ ++################################### ++# ++# Copyright (C) 2009-2017 Free Software Foundation, Inc. ++# ++# Contributed by Michael Eager <eager@eagercon.com>. ++# ++# This file is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License as published by the ++# Free Software Foundation; either version 3, or (at your option) any ++# later version. ++# ++# GCC is distributed in the hope that it will be useful, but WITHOUT ++# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY ++# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public ++# License for more details. ++# ++# Under Section 7 of GPL version 3, you are granted additional ++# permissions described in the GCC Runtime Library Exception, version ++# 3.1, as published by the Free Software Foundation. ++# ++# You should have received a copy of the GNU General Public License and ++# a copy of the GCC Runtime Library Exception along with this program; ++# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see ++# <http://www.gnu.org/licenses/>. ++# ++# umoddi3.S ++# ++# Unsigned modulo operation for 32 bit integers. ++# Input : op1 in Reg r5 ++# op2 in Reg r6 ++# Output: op1 mod op2 in Reg r3 ++# ++####################################### ++ ++#ifdef __arch64__ ++ .globl __umoddi3 ++ .ent __umoddi3 ++ .type __umoddi3,@function ++__umoddi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-24 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 ++ ++ BEALEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ ADDLIK r3,r0,0 # Clear div ++ BEALEQI r5,$LaResult_Is_Zero # Result is Zero ++ ADDLIK r30,r0,0 # clear mod ++ ADDLIK r29,r0,64 # Initialize the loop count ++ ++# Check if r6 and r5 are equal # if yes, return 0 ++ rsubl r18,r5,r6 ++ bealeqi r18,$LaRETURN_HERE ++ ++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 ++ xorl r18,r5,r6 ++ addlik r3,r5,0 ++ bealgei r18,$LRSUB ++ beallti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++$LRSUB: ++ rsubl r18,r5,r6 # MICROBLAZEcmp ++ bealgti r18,$LaRETURN_HERE ++ ++# If r6 [bit 31] is set, then return result as r5-r6 ++$LCheckr6: ++ addlik r3,r0,0 ++ bealgti r6,$LaDIV0 ++ addlik r18,r0,0x7fffffff ++ andl r5,r5,r18 ++ andl r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsubl r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALLTI r5,$LaDIV2 ++$LaDIV1: ++ ADDL r5,r5,r5 # left shift logical r5 ++ ADDLIK r29,r29,-1 ++ BEALGEI r5,$LaDIV1 # ++$LaDIV2: ++ ADDL r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDLC r3,r3,r3 # Move that bit into the Mod register ++ rSUBL r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALLTi r31,$LaMOD_TOO_SMALL ++ ORL r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDLIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDLIK r29,r29,-1 ++ BEALEQi r29,$LaLOOP_END ++ ADDL r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ orl r3,r0,r0 # set result to 0 ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++.end __umoddi3 ++ .size __umoddi3, . - __umoddi3 ++#endif +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch new file mode 100644 index 0000000000..c33b247bfd --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0042-re-arrangement-of-the-compare-branches.patch @@ -0,0 +1,268 @@ +From 9e45ca7bd65fe327e01e93d3c539c9d8cf049b79 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 3 Aug 2018 15:41:39 +0530 +Subject: [PATCH 42/54] re-arrangement of the compare branches + +--- + gcc/config/microblaze/microblaze.c | 28 ++----- + gcc/config/microblaze/microblaze.md | 141 +++++++++++++++++------------------- + 2 files changed, 73 insertions(+), 96 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index ba7ade4..fab79d9 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3695,11 +3695,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + { + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == Pmode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); +- ++ emit_jump_insn (gen_condjump (condition, label1)); + } + + else if (code == EQ || code == NE) +@@ -3710,10 +3706,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[]) + else + emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1)); + condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3746,10 +3739,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + comp_reg = cmp_op0; + condition = gen_rtx_fmt_ee (signed_condition (code), + mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else if (code == EQ) + { +@@ -3764,10 +3754,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_EQ (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + + } + else if (code == NE) +@@ -3783,10 +3770,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[]) + cmp_op1)); + } + condition = gen_rtx_NE (mode, comp_reg, const0_rtx); +- if (mode == SImode) +- emit_jump_insn (gen_condjump (condition, label1)); +- else +- emit_jump_insn (gen_long_condjump (condition, label1)); ++ emit_jump_insn (gen_condjump (condition, label1)); + } + else + { +@@ -3828,7 +3812,7 @@ microblaze_expand_conditional_branch_df (rtx operands[]) + + emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1)); + condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx); +- emit_jump_insn (gen_long_condjump (condition, operands[3])); ++ emit_jump_insn (gen_condjump (condition, operands[3])); + } + + /* Implement TARGET_FRAME_POINTER_REQUIRED. */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 0f41ac6..2213d6e 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2268,7 +2268,27 @@ else + (label_ref (match_operand 1)) + (pc)))]) + +-(define_insn "branch_zero64" ++(define_insn "branch_zero_64" ++ [(set (pc) ++ (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ [(match_operand:SI 1 "register_operand" "d") ++ (const_int 0)]) ++ (match_operand:SI 2 "pc_or_label_operand" "") ++ (match_operand:SI 3 "pc_or_label_operand" ""))) ++ ] ++ "TARGET_MB_64" ++ { ++ if (operands[3] == pc_rtx) ++ return "bea%C0i%?\t%z1,%2"; ++ else ++ return "bea%N0i%?\t%z1,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")] ++) ++ ++(define_insn "long_branch_zero" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand 1 "register_operand" "d") +@@ -2279,9 +2299,9 @@ else + "TARGET_MB_64" + { + if (operands[3] == pc_rtx) +- return "bea%C0i%?\t%z1,%2"; ++ return "beal%C0i%?\t%z1,%2"; + else +- return "bea%N0i%?\t%z1,%3"; ++ return "beal%N0i%?\t%z1,%3"; + } + [(set_attr "type" "branch") + (set_attr "mode" "none") +@@ -2310,9 +2330,9 @@ else + + (define_insn "branch_compare64" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:SI 0 "cmp_op" ++ [(match_operand:SI 1 "register_operand" "d") ++ (match_operand:SI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2349,6 +2369,47 @@ else + (set_attr "length" "12")] + ) + ++(define_insn "long_branch_compare" ++ [(set (pc) ++ (if_then_else (match_operator 0 "cmp_op" ++ [(match_operand 1 "register_operand" "d") ++ (match_operand 2 "register_operand" "d") ++ ]) ++ (label_ref (match_operand 3)) ++ (pc))) ++ (clobber(reg:DI R_TMP))] ++ "TARGET_MB_64" ++ { ++ operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ enum rtx_code code = GET_CODE (operands[0]); ++ ++ if (code == GT || code == LE) ++ { ++ output_asm_insn ("cmpl\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GTU || code == LEU) ++ { ++ output_asm_insn ("cmplu\tr18,%z1,%z2", operands); ++ code = swap_condition (code); ++ } ++ else if (code == GE || code == LT) ++ { ++ output_asm_insn ("cmpl\tr18,%z2,%z1", operands); ++ } ++ else if (code == GEU || code == LTU) ++ { ++ output_asm_insn ("cmplu\tr18,%z2,%z1", operands); ++ } ++ ++ operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); ++ return "beal%C0i%?\tr18,%3"; ++ } ++ [(set_attr "type" "branch") ++ (set_attr "mode" "none") ++ (set_attr "length" "12")] ++) ++ + (define_insn "branch_compare" + [(set (pc) + (if_then_else (match_operator:SI 0 "cmp_op" +@@ -2431,74 +2492,6 @@ else + + }) + +-;; Used to implement comparison instructions +-(define_expand "long_condjump" +- [(set (pc) +- (if_then_else (match_operand 0) +- (label_ref (match_operand 1)) +- (pc)))]) +- +-(define_insn "long_branch_zero" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "ordered_comparison_operator" +- [(match_operand:DI 1 "register_operand" "d") +- (const_int 0)]) +- (match_operand:DI 2 "pc_or_label_operand" "") +- (match_operand:DI 3 "pc_or_label_operand" ""))) +- ] +- "TARGET_MB_64" +- { +- if (operands[3] == pc_rtx) +- return "beal%C0i%?\t%z1,%2"; +- else +- return "beal%N0i%?\t%z1,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "4")] +-) +- +-(define_insn "long_branch_compare" +- [(set (pc) +- (if_then_else (match_operator:DI 0 "cmp_op" +- [(match_operand:DI 1 "register_operand" "d") +- (match_operand:DI 2 "register_operand" "d") +- ]) +- (label_ref (match_operand 3)) +- (pc))) +- (clobber(reg:DI R_TMP))] +- "TARGET_MB_64" +- { +- operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); +- enum rtx_code code = GET_CODE (operands[0]); +- +- if (code == GT || code == LE) +- { +- output_asm_insn ("cmpl\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GTU || code == LEU) +- { +- output_asm_insn ("cmplu\tr18,%z1,%z2", operands); +- code = swap_condition (code); +- } +- else if (code == GE || code == LT) +- { +- output_asm_insn ("cmpl\tr18,%z2,%z1", operands); +- } +- else if (code == GEU || code == LTU) +- { +- output_asm_insn ("cmplu\tr18,%z2,%z1", operands); +- } +- +- operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx); +- return "beal%C0i%?\tr18,%3"; +- } +- [(set_attr "type" "branch") +- (set_attr "mode" "none") +- (set_attr "length" "12")] +-) +- + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch new file mode 100644 index 0000000000..d1cf457986 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch @@ -0,0 +1,28 @@ +From 0c132e74714d217108d65fca630ab497a0d8821a Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 8 Aug 2018 17:37:26 +0530 +Subject: [PATCH 43/54] [Patch,Microblaze] : previous commit broke the + handling of SI Branch compare for Microblaze 32-bit.. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 2213d6e..53ea401 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2224,8 +2224,8 @@ else + (define_expand "cbranchsi4" + [(set (pc) + (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand") +- (match_operand 2 "arith_operand" "I,i")]) ++ [(match_operand:SI 1 "register_operand") ++ (match_operand:SI 2 "arith_operand" "I,i")]) + (label_ref (match_operand 3 "")) + (pc)))] + "" +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch new file mode 100644 index 0000000000..68791cb24e --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch @@ -0,0 +1,73 @@ +From 259ed1ee33625964f5bc394ae660103b6c35510f Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 11 Sep 2018 13:43:48 +0530 +Subject: [PATCH 44/54] [Patch, Microblaze] : Support of multilibs with m64 ... + +--- + gcc/config/microblaze/microblaze-c.c | 1 + + gcc/config/microblaze/t-microblaze | 15 ++++++--------- + libgcc/config/microblaze/t-microblaze | 11 +++-------- + 3 files changed, 10 insertions(+), 17 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c +index d8a1d13..6586575 100644 +--- a/gcc/config/microblaze/microblaze-c.c ++++ b/gcc/config/microblaze/microblaze-c.c +@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile) + } + if (TARGET_MB_64) + { ++ builtin_define ("__microblaze64"); + builtin_define ("__arch64__"); + builtin_define ("__microblaze64__"); + builtin_define ("__MICROBLAZE64__"); +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 9fc80b1..35ab965 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,12 +1,9 @@ +-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64 +-MULTILIB_DIRNAMES = bs m mh le m64 +-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64 +-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high +-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian +-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64 +-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64 ++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high ++MULTILIB_DIRNAMES = m64 bs le m mh ++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high + + # Extra files + microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \ +diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze +index 35021b2..8d954a4 100644 +--- a/libgcc/config/microblaze/t-microblaze ++++ b/libgcc/config/microblaze/t-microblaze +@@ -1,16 +1,11 @@ +-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \ +- _divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 ++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 + + LIB2ADD += \ + $(srcdir)/config/microblaze/divsi3.S \ +- $(srcdir)/config/microblaze/divdi3.S \ + $(srcdir)/config/microblaze/modsi3.S \ +- $(srcdir)/config/microblaze/moddi3.S \ ++ $(srcdir)/config/microblaze/muldi3_hard.S \ + $(srcdir)/config/microblaze/mulsi3.S \ +- $(srcdir)/config/microblaze/muldi3.S \ + $(srcdir)/config/microblaze/stack_overflow_exit.S \ + $(srcdir)/config/microblaze/udivsi3.S \ +- $(srcdir)/config/microblaze/udivdi3.S \ + $(srcdir)/config/microblaze/umodsi3.S \ +- $(srcdir)/config/microblaze/umoddi3.S \ +- $(srcdir)/config/microblaze/divsi3_table.c \ ++ $(srcdir)/config/microblaze/divsi3_table.c +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch new file mode 100644 index 0000000000..8c0bde713a --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0045-Fixed-issues-like.patch @@ -0,0 +1,70 @@ +From 654582846ebf847b52e769eb6e015c8e486461d6 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 11 Sep 2018 14:58:00 +0530 +Subject: [PATCH 45/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign + extension issue + +--- + gcc/config/microblaze/microblaze.c | 16 ++++++++++------ + gcc/config/microblaze/microblaze.md | 2 +- + 2 files changed, 11 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index fab79d9..6b6ca61 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2241,9 +2241,14 @@ compute_frame_size (HOST_WIDE_INT size) + + total_size += gp_reg_size; + +- /* Add 4 bytes for MSR. */ ++ /* Add 4/8 bytes for MSR. */ + if (microblaze_is_interrupt_variant ()) +- total_size += 4; ++ { ++ if (TARGET_MB_64) ++ total_size += 8; ++ else ++ total_size += 4; ++ } + + /* No space to be allocated for link register in leaf functions with no other + stack requirements. */ +@@ -2527,7 +2532,6 @@ print_operand (FILE * file, rtx op, int letter) + else if (letter == 'h' || letter == 'j') + { + long val[2]; +- int val1[2]; + long l[2]; + if (code == CONST_DOUBLE) + { +@@ -2542,10 +2546,10 @@ print_operand (FILE * file, rtx op, int letter) + } + else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF) + { +- val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; +- val1[1] = INTVAL (op) & 0x00000000ffffffffLL; ++ val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32; ++ val[1] = INTVAL (op) & 0x00000000ffffffffLL; + } +- fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]); ++ fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]); + } + else if (code == CONST_DOUBLE) + { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 53ea401..3a6943b 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -1094,7 +1094,7 @@ + case 1: + case 2: + { +- output_asm_insn ("ll%i1\t%0,%1", operands); ++ output_asm_insn ("lw%i1\t%0,%1", operands); + return "sextl32\t%0,%0"; + } + } +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch new file mode 100644 index 0000000000..22bb5b2f9c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0046-Fixed-below-issues.patch @@ -0,0 +1,306 @@ +From 48f9f9a1c6809b14e7cfdd2343df92c0de18d730 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 28 Sep 2018 11:59:12 +0530 +Subject: [PATCH 46/54] Fixed below issues: - Floating point print issues in + 64bit mode - Dejagnu Jump related issues - Added dbl instruction + +--- + gcc/config/microblaze/microblaze.c | 12 ++++- + gcc/config/microblaze/microblaze.h | 7 +++ + gcc/config/microblaze/microblaze.md | 89 ++++++++++++++++++++++++++++++------- + libgcc/config/microblaze/crti.S | 24 +++++++++- + libgcc/config/microblaze/crtn.S | 13 ++++++ + 5 files changed, 127 insertions(+), 18 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 6b6ca61..33d183e 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -2536,7 +2536,12 @@ print_operand (FILE * file, rtx op, int letter) + if (code == CONST_DOUBLE) + { + if (GET_MODE (op) == DFmode) +- REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ { ++ if (TARGET_MB_64) ++ REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ else ++ REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val); ++ } + else + { + REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l); +@@ -3874,7 +3879,10 @@ microblaze_expand_divide (rtx operands[]) + gen_rtx_PLUS (QImode, regt1, div_table_rtx)); + + insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx)); +- jump = emit_jump_insn_after (gen_jump (div_end_label), insn); ++ if (TARGET_MB_64) ++ jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn); ++ else ++ jump = emit_jump_insn_after (gen_jump (div_end_label), insn); + JUMP_LABEL (jump) = div_end_label; + LABEL_NUSES (div_end_label) = 1; + emit_barrier (); +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 1e60513..e34f549 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -892,10 +892,17 @@ do { \ + /* We do this to save a few 10s of code space that would be taken up + by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION + definition in crtstuff.c. */ ++#ifdef __arch64__ ++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ ++ asm ( SECTION_OP "\n" \ ++ "\tbrealid r15, " #FUNC "\n\t nop\n" \ ++ TEXT_SECTION_ASM_OP); ++#else + #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm ( SECTION_OP "\n" \ + "\tbrlid r15, " #FUNC "\n\t nop\n" \ + TEXT_SECTION_ASM_OP); ++#endif + + /* We need to group -lm as well, since some Newlib math functions + reference __errno! */ +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 3a6943b..2669a28 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -525,6 +525,15 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "floatdidf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (float:DF (match_operand:DI 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dbl\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "fix_truncsfsi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (fix:SI (match_operand:SF 1 "register_operand" "d")))] +@@ -1298,7 +1307,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "" ++ "TARGET_MB_64" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1581,7 +1590,7 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo"; ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -2371,9 +2380,9 @@ else + + (define_insn "long_branch_compare" + [(set (pc) +- (if_then_else (match_operator 0 "cmp_op" +- [(match_operand 1 "register_operand" "d") +- (match_operand 2 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "cmp_op" ++ [(match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d") + ]) + (label_ref (match_operand 3)) + (pc))) +@@ -2495,6 +2504,20 @@ else + ;;---------------------------------------------------------------- + ;; Unconditional branches + ;;---------------------------------------------------------------- ++(define_insn "jump_64" ++ [(set (pc) ++ (label_ref (match_operand 0 "" "")))] ++ "TARGET_MB_64" ++ { ++ if (GET_CODE (operands[0]) == REG) ++ return "brea%?\t%0"; ++ else ++ return "breai%?\t%l0"; ++ } ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] +@@ -2538,19 +2561,28 @@ else + (use (label_ref (match_operand 1 "" "")))] + "" + { +- //gcc_assert (GET_MODE (operands[0]) == Pmode); +- ++ gcc_assert (GET_MODE (operands[0]) == Pmode); ++ + if (!flag_pic) +- emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); +- else +- emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1])); ++ } ++ else { ++ if (!TARGET_MB_64) ++ emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1])); ++ else ++ emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1])); ++ } + DONE; + } + ) + + (define_insn "tablejump_internal1" + [(set (pc) +- (match_operand 0 "register_operand" "d")) ++ (match_operand:SI 0 "register_operand" "d")) + (use (label_ref (match_operand 1 "" "")))] + "" + "bra%?\t%0 " +@@ -2558,11 +2590,21 @@ else + (set_attr "mode" "none") + (set_attr "length" "4")]) + ++(define_insn "tablejump_internal2" ++ [(set (pc) ++ (match_operand:DI 0 "register_operand" "d")) ++ (use (label_ref (match_operand 1 "" "")))] ++ "TARGET_MB_64" ++ "bra%?\t%0 " ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ + (define_expand "tablejump_internal3" + [(parallel [(set (pc) +- (plus (match_operand 0 "register_operand" "d") +- (label_ref (match_operand:SI 1 "" "")))) +- (use (label_ref (match_dup 1)))])] ++ (plus:SI (match_operand:SI 0 "register_operand" "d") ++ (label_ref:SI (match_operand:SI 1 "" "")))) ++ (use (label_ref:SI (match_dup 1)))])] + "" + "" + ) +@@ -2593,6 +2635,23 @@ else + "" + ) + ++(define_insn "" ++ [(set (pc) ++ (plus:DI (match_operand:DI 0 "register_operand" "d") ++ (label_ref:DI (match_operand 1 "" "")))) ++ (use (label_ref:DI (match_dup 1)))] ++ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0 ++ && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC ++ && flag_pic" ++ { ++ output_asm_insn ("addlk\t%0,%0,r20",operands); ++ return "bra%?\t%0"; ++} ++ [(set_attr "type" "jump") ++ (set_attr "mode" "none") ++ (set_attr "length" "4")]) ++ ++ + ;;---------------------------------------------------------------- + ;; Function prologue/epilogue and stack allocation + ;;---------------------------------------------------------------- +@@ -3097,7 +3156,7 @@ else + ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference + ;; between "mfs" and "addik" instructions. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand 0 "register_operand" "=r") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))] + "" + "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8" +diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S +index 3386520..3d4cde2 100644 +--- a/libgcc/config/microblaze/crti.S ++++ b/libgcc/config/microblaze/crti.S +@@ -33,11 +33,32 @@ + .section .init, "ax" + .global __init + ++#ifdef __arch64__ + .weak _stack +- .set _stack, 0xffffffff ++ .set _stack, 0xffffffffffffffff + .weak _stack_end + .set _stack_end, 0 + ++ .align 3 ++__init: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++ addlik r11, r0, _stack ++ mts rshr, r11 ++ addlik r11, r0, _stack_end ++ mts rslr, r11 ++ ++ .section .fini, "ax" ++ .global __fini ++ .align 3 ++__fini: ++ addlik r1, r1, -32 ++ sl r15, r0, r1 ++#else ++ .weak _stack ++ .set _stack, 0xffffffff ++ .weak _stack_end ++ .set _stack_end, 0 + .align 2 + __init: + addik r1, r1, -16 +@@ -53,3 +74,4 @@ __init: + __fini: + addik r1, r1, -16 + sw r15, r0, r1 ++#endif +diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S +index 04e73d7..c262ce0 100644 +--- a/libgcc/config/microblaze/crtn.S ++++ b/libgcc/config/microblaze/crtn.S +@@ -29,7 +29,19 @@ + .section .note.GNU-stack,"",%progbits + .previous + #endif ++#ifdef __arch64__ ++ .section .init, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop + ++ .section .fini, "ax" ++ ll r15, r0, r1 ++ addlik r1, r1, 32 ++ rtsd r15, 8 ++ nop ++#else + .section .init, "ax" + lw r15, r0, r1 + rtsd r15, 8 +@@ -39,3 +51,4 @@ + lw r15, r0, r1 + rtsd r15, 8 + addik r1, r1, 16 ++#endif +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch new file mode 100644 index 0000000000..f28d9f5166 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0047-Added-double-arith-instructions.patch @@ -0,0 +1,135 @@ +From b09721c830dd0831f50084e2e64920f83618e3f4 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 9 Oct 2018 10:07:08 +0530 +Subject: [PATCH 47/54] -Added double arith instructions -Fixed prologue stack + pointer decrement issue + +--- + gcc/config/microblaze/microblaze.md | 78 ++++++++++++++++++++++++++++++++----- + gcc/config/microblaze/t-microblaze | 7 ++++ + 2 files changed, 76 insertions(+), 9 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 2669a28..dca61d6 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -525,6 +525,66 @@ + (set_attr "mode" "SF") + (set_attr "length" "4")]) + ++(define_insn "fix_truncsfsi2" ++ [(set (match_operand:SI 0 "register_operand" "=d") ++ (fix:SI (match_operand:SF 1 "register_operand" "d")))] ++ "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" ++ "fint\t%0,%1" ++ [(set_attr "type" "fint") ++ (set_attr "mode" "SF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "adddf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (plus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dadd\t%0,%1,%2" ++ [(set_attr "type" "fadd") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "subdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (minus:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "drsub\t%0,%2,%1" ++ [(set_attr "type" "frsub") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "muldf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (mult:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dmul\t%0,%1,%2" ++ [(set_attr "type" "fmul") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++(define_insn "divdf3" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (div:DF (match_operand:DF 1 "register_operand" "d") ++ (match_operand:DF 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "ddiv\t%0,%2,%1" ++ [(set_attr "type" "fdiv") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ ++ ++(define_insn "sqrtdf2" ++ [(set (match_operand:DF 0 "register_operand" "=d") ++ (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dsqrt\t%0,%1" ++ [(set_attr "type" "fsqrt") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4")]) ++ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +@@ -534,13 +594,13 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "fix_truncsfsi2" +- [(set (match_operand:SI 0 "register_operand" "=d") +- (fix:SI (match_operand:SF 1 "register_operand" "d")))] +- "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" +- "fint\t%0,%1" +- [(set_attr "type" "fint") +- (set_attr "mode" "SF") ++(define_insn "floatdfdi2" ++ [(set (match_operand:DI 0 "register_operand" "=d") ++ (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ "TARGET_MB_64" ++ "dlong\t%0,%1" ++ [(set_attr "type" "fcvt") ++ (set_attr "mode" "DI") + (set_attr "length" "4")]) + + ;;---------------------------------------------------------------- +@@ -658,8 +718,8 @@ + "TARGET_MB_64" + "@ + rsubl\t%0,%2,%1 +- addik\t%0,%z1,-%2 +- addik\t%0,%z1,-%2" ++ addlik\t%0,%z1,-%2 ++ addlik\t%0,%z1,-%2" + [(set_attr "type" "arith,no_delay_arith,no_delay_arith") + (set_attr "mode" "DI") + (set_attr "length" "4,4,4")]) +diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze +index 35ab965..dfef45c 100644 +--- a/gcc/config/microblaze/t-microblaze ++++ b/gcc/config/microblaze/t-microblaze +@@ -1,6 +1,13 @@ + MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high + MULTILIB_DIRNAMES = m64 bs le m mh + MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64 ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul ++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high ++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high + MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high + MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch new file mode 100644 index 0000000000..9a214d55a7 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch @@ -0,0 +1,37 @@ +From 1ed548dd5993b8c3e58ef393467bdeea49c437be Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 12 Oct 2018 16:07:36 +0530 +Subject: [PATCH 48/54] Fixed the issue in the delay slot with swap + instructions + +--- + gcc/config/microblaze/microblaze.md | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index dca61d6..d037843 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -441,6 +441,9 @@ + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_REORDER" + "swapb %0, %1" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "4")] + ) + + (define_insn "bswaphi2" +@@ -449,6 +452,9 @@ + "TARGET_REORDER" + "swapb %0, %1 + swaph %0, %0" ++ [(set_attr "type" "no_delay_arith") ++ (set_attr "mode" "SI") ++ (set_attr "length" "8")] + ) + + ;;---------------------------------------------------------------- +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch new file mode 100644 index 0000000000..a682bc19df --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch @@ -0,0 +1,256 @@ +From 1c889b64454f63f164f34d79d891d91b0bb4731f Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Sat, 13 Oct 2018 21:12:43 +0530 +Subject: [PATCH 49/54] Fixed the load store issue with the 32bit arith + libraries + +--- + libgcc/config/microblaze/divsi3.S | 25 ++++++++++++++++++++++++- + libgcc/config/microblaze/modsi3.S | 26 +++++++++++++++++++++++++- + libgcc/config/microblaze/mulsi3.S | 3 +++ + libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++- + libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++- + 5 files changed, 98 insertions(+), 4 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 663d398..7e7d875 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -41,6 +41,17 @@ + .globl __divsi3 + .ent __divsi3 + .type __divsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__divsi3: ++ .frame r1,0,r15 ++ ++ ADDIK r1,r1,-32 ++ SLI r28,r1,0 ++ SLI r29,r1,8 ++ SLI r30,r1,16 ++ SLI r31,r1,24 ++#else + __divsi3: + .frame r1,0,r15 + +@@ -49,7 +60,7 @@ __divsi3: + SWI r29,r1,4 + SWI r30,r1,8 + SWI r31,r1,12 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEID r5,$LaR5_Pos +@@ -89,6 +100,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r28,r1,0 ++ LLI r29,r1,8 ++ LLI r30,r1,16 ++ LLI r31,r1,24 ++ ADDLIK r1,r1,32 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r28,r1,0 +@@ -97,6 +119,7 @@ $LaRETURN_HERE: + LWI r31,r1,12 + RTSD r15,8 + ADDIK r1,r1,16 ++#endif + .end __divsi3 + .size __divsi3, . - __divsi3 + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 71b56e30..7e85064 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -41,6 +41,17 @@ + .globl __modsi3 + .ent __modsi3 + .type __modsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__modsi3: ++ .frame r1,0,r15 ++ ++ addlik r1,r1,-32 ++ sli r28,r1,0 ++ sli r29,r1,8 ++ sli r30,r1,16 ++ sli r31,r1,24 ++#else + __modsi3: + .frame r1,0,r15 + +@@ -49,6 +60,7 @@ __modsi3: + swi r29,r1,4 + swi r30,r1,8 + swi r31,r1,12 ++#endif + + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero +@@ -88,6 +100,18 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 [Both mod as well as div are 0] ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r28,r1,0 ++ lli r29,r1,8 ++ lli r30,r1,16 ++ lli r31,r1,24 ++ addik r1,r1,32 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r28,r1,0 +@@ -95,7 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 +- addik r1,r1,16 ++#endif + .end __modsi3 + .size __modsi3, . - __modsi3 + +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 40b0b15..31a73c2 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -41,6 +41,9 @@ + .globl __mulsi3 + .ent __mulsi3 + .type __mulsi3,@function ++#ifdef __arch64__ ++ .align 3 ++#endif + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 2aef8ed..94adb6a 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -41,6 +41,16 @@ + .globl __udivsi3 + .ent __udivsi3 + .type __udivsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__udivsi3: ++ .frame r1,0,r15 ++ ++ ADDLIK r1,r1,-24 ++ SLI r29,r1,0 ++ SLI r30,r1,8 ++ SLI r31,r1,16 ++#else + __udivsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __udivsi3: + SWI r29,r1,0 + SWI r30,r1,4 + SWI r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero + ADDIK r30,r0,0 # Clear mod +@@ -98,6 +108,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++ # Restore values of CSRs and that of r3 and the divisor and the dividend ++ LLI r29,r1,0 ++ LLI r30,r1,8 ++ LLI r31,r1,16 ++ ADDIK r1,r1,24 ++ RTSD r15,8 ++ NOP ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + LWI r29,r1,0 +@@ -105,5 +126,6 @@ $LaRETURN_HERE: + LWI r31,r1,8 + RTSD r15,8 + ADDIK r1,r1,12 ++#endif + .end __udivsi3 + .size __udivsi3, . - __udivsi3 +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index a2582d0..00b3bdf 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -41,6 +41,16 @@ + .globl __umodsi3 + .ent __umodsi3 + .type __umodsi3,@function ++#ifdef __arch64__ ++ .align 3 ++__umodsi3: ++ .frame r1,0,r15 ++ ++ addik r1,r1,-24 ++ swi r29,r1,0 ++ swi r30,r1,8 ++ swi r31,r1,16 ++#else + __umodsi3: + .frame r1,0,r15 + +@@ -48,7 +58,7 @@ __umodsi3: + swi r29,r1,0 + swi r30,r1,4 + swi r31,r1,8 +- ++#endif + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero + ADDIK r3,r0,0 # Clear div +@@ -101,6 +111,17 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 ++ ++#ifdef __arch64__ ++$LaRETURN_HERE: ++# Restore values of CSRs and that of r3 and the divisor and the dividend ++ lli r29,r1,0 ++ lli r30,r1,8 ++ lli r31,r1,16 ++ addlik r1,r1,24 ++ rtsd r15,8 ++ nop ++#else + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend + lwi r29,r1,0 +@@ -108,5 +129,6 @@ $LaRETURN_HERE: + lwi r31,r1,8 + rtsd r15,8 + addik r1,r1,12 ++#endif + .end __umodsi3 + .size __umodsi3, . - __umodsi3 +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch new file mode 100644 index 0000000000..95a26db2c0 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch @@ -0,0 +1,25 @@ +From 751a01ce1eeaffcd41c504b9bf44868345b45da0 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Mon, 15 Oct 2018 12:00:10 +0530 +Subject: [PATCH 50/54] extending the Dwarf support to 64bit Microblaze + +--- + gcc/config/microblaze/microblaze.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index e34f549..0a5ff0a 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe; + /* Use DWARF 2 debugging information by default. */ + #define DWARF2_DEBUGGING_INFO 1 + #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +-#define DWARF2_ADDR_SIZE 4 ++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4) + + /* Target machine storage layout */ + +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch new file mode 100644 index 0000000000..574037ecf1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0051-fixing-the-typo-errors-in-umodsi3-file.patch @@ -0,0 +1,29 @@ +From 295046d0a63148fb5a685ae2bd7a06489274c72a Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Tue, 16 Oct 2018 07:55:46 +0530 +Subject: [PATCH 51/54] fixing the typo errors in umodsi3 file + +--- + libgcc/config/microblaze/umodsi3.S | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 00b3bdf..9bf65c3 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -47,9 +47,9 @@ __umodsi3: + .frame r1,0,r15 + + addik r1,r1,-24 +- swi r29,r1,0 +- swi r30,r1,8 +- swi r31,r1,16 ++ sli r29,r1,0 ++ sli r30,r1,8 ++ sli r31,r1,16 + #else + __umodsi3: + .frame r1,0,r15 +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch new file mode 100644 index 0000000000..95d39bb284 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0052-fixing-the-32bit-LTO-related-issue9-1014024.patch @@ -0,0 +1,68 @@ +From d55eff09f175ddbc66e4e800fa5650ce9e2f599e Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Wed, 17 Oct 2018 16:56:14 +0530 +Subject: [PATCH 52/54] fixing the 32bit LTO related issue9(1014024) + +--- + gcc/config/microblaze/microblaze.h | 24 ++++++++++++++---------- + 1 file changed, 14 insertions(+), 10 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 0a5ff0a..740b8d9 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe; + #define WORD_REGISTER_OPERATIONS 1 + + #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND +-/* +-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ +- if (GET_MODE_CLASS (MODE) == MODE_INT \ +- && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \ +- (MODE) = TARGET_MB_64 ? DImode : SImode; +-*/ ++ ++#ifndef __arch64__ ++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ ++ if (GET_MODE_CLASS (MODE) == MODE_INT \ ++ && GET_MODE_SIZE (MODE) < 4) \ ++ (MODE) = SImode; ++#endif ++ + /* Standard register usage. */ + + /* On the MicroBlaze, we have 32 integer registers */ +@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info; + + #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS + ++#ifdef __aarch64__ + #define LIBCALL_VALUE(MODE) \ + gen_rtx_REG (MODE,GP_RETURN) +- +-/*#define LIBCALL_VALUE(MODE) \ ++#else ++#define LIBCALL_VALUE(MODE) \ + gen_rtx_REG ( \ + ((GET_MODE_CLASS (MODE) != MODE_INT \ + || GET_MODE_SIZE (MODE) >= 4) \ + ? (MODE) \ + : SImode), GP_RETURN) +-*/ ++#endif ++ + /* 1 if N is a possible register number for a function value. + On the MicroBlaze, R2 R3 are the only register thus used. + Currently, R2 are only implemented here (C has no complex type) */ +@@ -518,7 +522,7 @@ typedef struct microblaze_args + /* 4 insns + 2 words of data. */ + #define TRAMPOLINE_SIZE (6 * 4) + +-#define TRAMPOLINE_ALIGNMENT 64 ++#define TRAMPOLINE_ALIGNMENT (TARGET_MB_64 ? 64 : 32) + + #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1) + +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch new file mode 100644 index 0000000000..e992075b95 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch @@ -0,0 +1,25 @@ +From 3e7161218dc8b4dd84ad8d31f6dbaa7c256e7a82 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Fri, 19 Oct 2018 14:26:25 +0530 +Subject: [PATCH 53/54] Fixed the missing stack adjustment in prologue of + modsi3 function + +--- + libgcc/config/microblaze/modsi3.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 7e85064..46ff34a 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -119,6 +119,7 @@ $LaRETURN_HERE: + lwi r30,r1,8 + lwi r31,r1,12 + rtsd r15,8 ++ addik r1,r1,16 + #endif + .end __modsi3 + .size __modsi3, . - __modsi3 +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch new file mode 100644 index 0000000000..afb88d3506 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch @@ -0,0 +1,29 @@ +From a89b3e6902d7835129ad178f6af896eba15c5d5e Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 24 Oct 2018 18:31:04 +0530 +Subject: [PATCH 54/54] [Patch,Microblaze] : corrected SPN for dlong + instruction mapping. + +--- + gcc/config/microblaze/microblaze.md | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index d037843..cbd7e77 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -600,9 +600,9 @@ + (set_attr "mode" "DF") + (set_attr "length" "4")]) + +-(define_insn "floatdfdi2" ++(define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") +- (float:DI (match_operand:DF 1 "register_operand" "d")))] ++ (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] + "TARGET_MB_64" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch new file mode 100644 index 0000000000..4c694723d9 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-fixing-the-long-long-long-mingw-toolchain-issue.patch @@ -0,0 +1,59 @@ +From 76e231f92afd8fda13d6ae18ef3aef0ea6096489 Mon Sep 17 00:00:00 2001 +From: Nagaraju Mekala <nmekala@xilix.com> +Date: Thu, 29 Nov 2018 17:55:08 +0530 +Subject: [PATCH 55/57] fixing the long & long long mingw toolchain issue + +--- + gcc/config/microblaze/constraints.md | 2 +- + gcc/config/microblaze/microblaze.md | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md +index 867a7b5..27c6bfc 100644 +--- a/gcc/config/microblaze/constraints.md ++++ b/gcc/config/microblaze/constraints.md +@@ -55,7 +55,7 @@ + (define_constraint "K" + "A constant in the range 0xffffff8000000000L to 0x0000007fffffffffL (inclusive)." + (and (match_code "const_int") +- (match_test "ival > (long)-549755813888 && ival < (long)549755813887"))) ++ (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887"))) + + ;; Define floating point constraints + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index cbd7e77..e03b835 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -646,8 +646,8 @@ + if (TARGET_MB_64) + { + if (GET_CODE (operands[2]) == CONST_INT && +- INTVAL(operands[2]) < (long)-549755813888 && +- INTVAL(operands[2]) > (long)549755813887) ++ INTVAL(operands[2]) < (long long)-549755813888 && ++ INTVAL(operands[2]) > (long long)549755813887) + FAIL; + } + }) +@@ -1264,7 +1264,7 @@ + (match_operand:DI 1 "immediate_operand" "J,I,Mnis"))] + "TARGET_MB_64 && (register_operand (operands[0], DImode) && + (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))" ++ (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))" + "@ + addlk\t%0,r0,r0\t + addlik\t%0,r0,%1\t #N1 %X1 +@@ -1298,7 +1298,7 @@ + case 1: + case 2: + if (GET_CODE (operands[1]) == CONST_INT && +- (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888)) ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) + return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + else + return "addlik\t%0,r0,%1"; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch new file mode 100644 index 0000000000..c009c92d20 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0055-microblaze_linker_script_xilinx_ld.patch @@ -0,0 +1,16 @@ +diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h +index 740b8d9..4bda9c2 100644 +--- a/gcc/config/microblaze/microblaze.h ++++ b/gcc/config/microblaze/microblaze.h +@@ -114,8 +114,9 @@ extern enum pipeline_type microblaze_pipe; + %{m64:-EL --oformat=elf64-microblazeel} \ + %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ + %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \ +- %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \ +- %{!T*: -dT xilinx.ld%s}" ++ %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0}" ++ ++// %{!T*: -dT xilinx.ld%s}" + + /* Specs for the compiler proper */ + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch new file mode 100644 index 0000000000..a5a2039d99 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch @@ -0,0 +1,47 @@ +From 6c58973f1cc1e37773aeab583aa3ac6331489106 Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Thu, 14 Mar 2019 18:11:04 +0530 +Subject: [PATCH 57/57] Fix the MB-64 bug of handling QI objects + +--- + gcc/config/microblaze/microblaze.md | 14 +++++++------- + 1 file changed, 7 insertions(+), 7 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index e03b835..88aee9e 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -2345,11 +2345,11 @@ else + + (define_insn "branch_zero_64" + [(set (pc) +- (if_then_else (match_operator:SI 0 "ordered_comparison_operator" ++ (if_then_else (match_operator 0 "ordered_comparison_operator" + [(match_operand:SI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand:SI 2 "pc_or_label_operand" "") +- (match_operand:SI 3 "pc_or_label_operand" ""))) ++ (match_operand 2 "pc_or_label_operand" "") ++ (match_operand 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +@@ -2365,11 +2365,11 @@ else + + (define_insn "long_branch_zero" + [(set (pc) +- (if_then_else (match_operator 0 "ordered_comparison_operator" +- [(match_operand 1 "register_operand" "d") ++ (if_then_else (match_operator:DI 0 "ordered_comparison_operator" ++ [(match_operand:DI 1 "register_operand" "d") + (const_int 0)]) +- (match_operand 2 "pc_or_label_operand" "") +- (match_operand 3 "pc_or_label_operand" ""))) ++ (match_operand:DI 2 "pc_or_label_operand" "") ++ (match_operand:DI 3 "pc_or_label_operand" ""))) + ] + "TARGET_MB_64" + { +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch new file mode 100644 index 0000000000..8bc47a430c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch @@ -0,0 +1,87 @@ +From bcbfd9f69d858306a080aa7213e96ca6eca66106 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Fri, 29 Mar 2019 12:08:39 +0530 +Subject: [PATCH 58/61] [Patch,Microblaze] : We will check the possibility of + peephole2 optimization,if we can then we will fix the compiler issue. + +--- + gcc/config/microblaze/microblaze.md | 63 ++++++++++++++++++++++--------------- + 1 file changed, 38 insertions(+), 25 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 88aee9e..8bd175f 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -880,31 +880,44 @@ + (set_attr "mode" "SI") + (set_attr "length" "4")]) + +-(define_peephole2 +- [(set (match_operand:SI 0 "register_operand") +- (fix:SI (match_operand:SF 1 "register_operand"))) +- (set (pc) +- (if_then_else (match_operator 2 "ordered_comparison_operator" +- [(match_operand:SI 3 "register_operand") +- (match_operand:SI 4 "arith_operand")]) +- (label_ref (match_operand 5)) +- (pc)))] +- "TARGET_HARD_FLOAT && !TARGET_MB_64" +- [(set (match_dup 1) (match_dup 3))] +- +- { +- rtx condition; +- rtx cmp_op0 = operands[3]; +- rtx cmp_op1 = operands[4]; +- rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); +- +- emit_insn (gen_cstoresf4 (comp_reg, operands[2], +- gen_rtx_REG (SFmode, REGNO (cmp_op0)), +- gen_rtx_REG (SFmode, REGNO (cmp_op1)))); +- condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); +- emit_jump_insn (gen_condjump (condition, operands[5])); +- } +-) ++;; peephole2 optimization will be done only if fint and if-then-else ++;; are dependent.added condition for the same. ++;; if they are dependent then gcc is giving "flow control insn inside a basic block" ++;; testcase: ++;; volatile float vec = 1.0; ++;; volatile int ci = 2; ++;; register int cj = (int)(vec); ++;;// ci=cj; ++;;// if (ci <0) { ++;; if (cj < 0) { ++;; ci = 0; ++;; } ++;; commenting for now.we will check the possibility of this optimization later ++ ++;;(define_peephole2 ++;; [(set (match_operand:SI 0 "register_operand") ++;; (fix:SI (match_operand:SF 1 "register_operand"))) ++;; (set (pc) ++;; (if_then_else (match_operator 2 "ordered_comparison_operator" ++;; [(match_operand:SI 3 "register_operand") ++;; (match_operand:SI 4 "arith_operand")]) ++;; (label_ref (match_operand 5)) ++;; (pc)))] ++;; "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))" ++;; [(set (match_dup 1) (match_dup 3))] ++;; { ++;; rtx condition; ++;; rtx cmp_op0 = operands[3]; ++;; rtx cmp_op1 = operands[4]; ++;; rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); ++;; ++;; emit_insn (gen_cstoresf4 (comp_reg, operands[2], ++;; gen_rtx_REG (SFmode, REGNO (cmp_op0)), ++;; gen_rtx_REG (SFmode, REGNO (cmp_op1)))); ++;; condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); ++;; emit_jump_insn (gen_condjump (condition, operands[5])); ++;; } ++;;) + + ;;---------------------------------------------------------------- + ;; Negation and one's complement +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch new file mode 100644 index 0000000000..be4dfad5c4 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch @@ -0,0 +1,51 @@ +From 2f22090a7e8216f7a9f7e958b77ac83006a7ce89 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Tue, 16 Apr 2019 17:20:24 +0530 +Subject: [PATCH 59/61] Reverting the patch as kernel boot is not working with + this patch CR-1026413 Revert "[Patch,Microblaze]:reverting the cost check + before propagating constants." + +This reverts commit 7156e379a67fa47a5fb9ede1448c0d528dbda65b. +--- + gcc/cprop.c | 4 ---- + 1 file changed, 4 deletions(-) + +diff --git a/gcc/cprop.c b/gcc/cprop.c +index deb706b..e4df509 100644 +--- a/gcc/cprop.c ++++ b/gcc/cprop.c +@@ -733,7 +733,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + int success = 0; + rtx set = single_set (insn); + +-#if 0 + bool check_rtx_costs = true; + bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); + int old_cost = set ? set_rtx_cost (set, speed) : 0; +@@ -745,7 +744,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + && (GET_CODE (XEXP (note, 0)) == CONST + || CONSTANT_P (XEXP (note, 0))))) + check_rtx_costs = false; +-#endif + + /* Usually we substitute easy stuff, so we won't copy everything. + We however need to take care to not duplicate non-trivial CONST +@@ -754,7 +752,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + + validate_replace_src_group (from, to, insn); + +-#if 0 + /* If TO is a constant, check the cost of the set after propagation + to the cost of the set before the propagation. If the cost is + higher, then do not replace FROM with TO. */ +@@ -767,7 +764,6 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn) + return false; + } + +-#endif + + if (num_changes_pending () && apply_change_group ()) + success = 1; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch new file mode 100644 index 0000000000..1548faada1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch @@ -0,0 +1,466 @@ +From 80919b0f43b275e70521e4f85cd28bcd0ece3b80 Mon Sep 17 00:00:00 2001 +From: Mahesh Bodapati <mbodapat@xilinx.com> +Date: Wed, 17 Apr 2019 12:36:16 +0530 +Subject: [PATCH 60/61] [Patch,MicroBlaze]: fixed typos in mul,div and mod + assembly files. + +--- + libgcc/config/microblaze/divsi3.S | 47 ++++++++++++++++++++++++++---- + libgcc/config/microblaze/modsi3.S | 40 +++++++++++++++++++++++--- + libgcc/config/microblaze/mulsi3.S | 33 +++++++++++++++++++++- + libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++++++++---- + libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++++++++++--- + 5 files changed, 212 insertions(+), 20 deletions(-) + +diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S +index 7e7d875..cfb4c05 100644 +--- a/libgcc/config/microblaze/divsi3.S ++++ b/libgcc/config/microblaze/divsi3.S +@@ -46,7 +46,7 @@ + __divsi3: + .frame r1,0,r15 + +- ADDIK r1,r1,-32 ++ ADDLIK r1,r1,-32 + SLI r28,r1,0 + SLI r29,r1,8 + SLI r30,r1,16 +@@ -61,13 +61,23 @@ __divsi3: + SWI r30,r1,8 + SWI r31,r1,12 + #endif +- BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error +- BEQI r5,$LaResult_Is_Zero # Result is Zero +- BGEID r5,$LaR5_Pos ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEID r5,$LaR5_Pos ++#else ++ BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEQI r5,$LaResult_Is_Zero # Result is Zero ++ BGEID r5,$LaR5_Pos ++#endif + XOR r28,r5,r6 # Get the sign of the result + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r30,r0,0 # Clear mod +@@ -76,26 +86,51 @@ $LaR6_Pos: + + # First part try to find the first '1' in the r5 + $LaDIV0: +- BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#else ++ BLTI r5,$LaDIV2 # This traps r5 == 0x80000000 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++#else + BEQi r29,$LaLOOP_END ++#endif + ADD r3,r3,r3 # Shift in the '1' into div ++#ifdef __arch64__ ++ BREAI $LaDIV2 # Div2 ++#else + BRI $LaDIV2 # Div2 ++#endif + $LaLOOP_END: ++#ifdef __arch64__ ++ BEAGEI r28,$LaRETURN_HERE ++ BREAID $LaRETURN_HERE ++#else + BGEI r28,$LaRETURN_HERE + BRID $LaRETURN_HERE ++#endif + RSUBI r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S +index 46ff34a..49618dd 100644 +--- a/libgcc/config/microblaze/modsi3.S ++++ b/libgcc/config/microblaze/modsi3.S +@@ -62,40 +62,72 @@ __modsi3: + swi r31,r1,12 + #endif + ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQI r5,$LaResult_Is_Zero # Result is Zero ++ BEAGEId r5,$LaR5_Pos ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQI r5,$LaResult_Is_Zero # Result is Zero + BGEId r5,$LaR5_Pos ++#endif + ADD r28,r5,r0 # Get the sign of the result [ Depends only on the first arg] + RSUBI r5,r5,0 # Make r5 positive + $LaR5_Pos: +- BGEI r6,$LaR6_Pos ++#ifdef __arch64__ ++ BEAGEI r6,$LaR6_Pos ++#else ++ BGEI r6,$LaR6_Pos ++#endif + RSUBI r6,r6,0 # Make r6 positive + $LaR6_Pos: + ADDIK r3,r0,0 # Clear mod + ADDIK r30,r0,0 # clear div +- BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++#ifdef __arch64__ ++ BEALTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip + # the first bit search. ++#else ++ BLTId r5,$LaDIV2 # If r5 is still negative (0x80000000), skip ++ # the first bit search. ++#endif + ADDIK r29,r0,32 # Initialize the loop count + # First part try to find the first '1' in the r5 + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 +- BGEID r5,$LaDIV1 # ++#ifdef __arch64__ ++ BEAGEID r5,$LaDIV1 # ++#else ++ BGEID r5,$LaDIV1 # ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r3,r3,r3 # Move that bit into the Mod register + rSUB r31,r6,r3 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTi r31,$LaMOD_TOO_SMALL ++#else + BLTi r31,$LaMOD_TOO_SMALL ++#endif + OR r3,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r30,r30,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BEAGEI r28,$LaRETURN_HERE ++ BREAId $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r30,r30,r30 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BGEI r28,$LaRETURN_HERE + BRId $LaRETURN_HERE ++#endif + rsubi r3,r3,0 # Negate the result + $LaDiv_By_Zero: + $LaResult_Is_Zero: +@@ -108,7 +140,7 @@ $LaRETURN_HERE: + lli r29,r1,8 + lli r30,r1,16 + lli r31,r1,24 +- addik r1,r1,32 ++ addlik r1,r1,32 + rtsd r15,8 + nop + #else +diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S +index 31a73c2..39951be 100644 +--- a/libgcc/config/microblaze/mulsi3.S ++++ b/libgcc/config/microblaze/mulsi3.S +@@ -43,7 +43,37 @@ + .type __mulsi3,@function + #ifdef __arch64__ + .align 3 +-#endif ++__mulsi3: ++ .frame r1,0,r15 ++ add r3,r0,r0 ++ BEAEQI r5,$L_Result_Is_Zero # Multiply by Zero ++ BEAEQI r6,$L_Result_Is_Zero # Multiply by Zero ++ BEAGEId r5,$L_R5_Pos ++ XOR r4,r5,r6 # Get the sign of the result ++ RSUBI r5,r5,0 # Make r5 positive ++$L_R5_Pos: ++ BEAGEI r6,$L_R6_Pos ++ RSUBI r6,r6,0 # Make r6 positive ++$L_R6_Pos: ++ breai $L1 ++$L2: ++ add r5,r5,r5 ++$L1: ++ srl r6,r6 ++ addc r7,r0,r0 ++ beaeqi r7,$L2 ++ beaneid r6,$L2 ++ add r3,r3,r5 ++ bealti r4,$L_NegateResult ++ rtsd r15,8 ++ nop ++$L_NegateResult: ++ rtsd r15,8 ++ rsub r3,r3,r0 ++$L_Result_Is_Zero: ++ rtsd r15,8 ++ addi r3,r0,0 ++#else + __mulsi3: + .frame r1,0,r15 + add r3,r0,r0 +@@ -74,5 +104,6 @@ $L_NegateResult: + $L_Result_Is_Zero: + rtsd r15,8 + addi r3,r0,0 ++#endif + .end __mulsi3 + .size __mulsi3, . - __mulsi3 +diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S +index 94adb6a..d4fe285 100644 +--- a/libgcc/config/microblaze/udivsi3.S ++++ b/libgcc/config/microblaze/udivsi3.S +@@ -59,52 +59,96 @@ __udivsi3: + SWI r30,r1,4 + SWI r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQID r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQID r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r30,r0,0 # Clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 1 + RSUB r18,r5,r6 ++#ifdef __arch64__ ++ BEAEQID r18,$LaRETURN_HERE ++#else + BEQID r18,$LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0 + XOR r18,r5,r6 +- BGEID r18,16 ++#ifdef __arch64__ ++ BEAGEID r18,16 ++#else ++ BGEID r18,16 ++#endif + ADD r3,r0,r0 # We would anyways clear r3 ++#ifdef __arch64__ ++ BEALTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater ++ BREAI $LCheckr6 ++ RSUB r18,r6,r5 # MICROBLAZEcmp ++ BEALTI r18,$LaRETURN_HERE ++#else + BLTI r6,$LaRETURN_HERE # r6[bit 31 = 1] hence is greater + BRI $LCheckr6 + RSUB r18,r6,r5 # MICROBLAZEcmp + BLTI r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as 1 + $LCheckr6: +- BGTI r6,$LaDIV0 +- BRID $LaRETURN_HERE ++#ifdef __arch64__ ++ BEAGTI r6,$LaDIV0 ++ BREAID $LaRETURN_HERE ++#else ++ BGTI r6,$LaDIV0 ++ BRID $LaRETURN_HERE ++#endif + ADDIK r3,r0,1 + + # First part try to find the first '1' in the r5 + $LaDIV0: ++#ifdef __arch64__ ++ BEALTI r5,$LaDIV2 ++#else + BLTI r5,$LaDIV2 ++#endif + $LaDIV1: + ADD r5,r5,r5 # left shift logical r5 ++#ifdef __arch64__ ++ BEAGTID r5,$LaDIV1 ++#else + BGTID r5,$LaDIV1 ++#endif + ADDIK r29,r29,-1 + $LaDIV2: + ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry + ADDC r30,r30,r30 # Move that bit into the Mod register + RSUB r31,r6,r30 # Try to subtract (r30 a r6) ++#ifdef __arch64__ ++ BEALTI r31,$LaMOD_TOO_SMALL ++#else + BLTI r31,$LaMOD_TOO_SMALL ++#endif + OR r30,r0,r31 # Move the r31 to mod since the result was positive + ADDIK r3,r3,1 + $LaMOD_TOO_SMALL: + ADDIK r29,r29,-1 ++#ifdef __arch64__ ++ BEAEQi r29,$LaLOOP_END ++ ADD r3,r3,r3 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++#else + BEQi r29,$LaLOOP_END + ADD r3,r3,r3 # Shift in the '1' into div + BRI $LaDIV2 # Div2 + $LaLOOP_END: + BRI $LaRETURN_HERE ++#endif + $LaDiv_By_Zero: + $LaResult_Is_Zero: + OR r3,r0,r0 # set result to 0 +@@ -115,7 +159,7 @@ $LaRETURN_HERE: + LLI r29,r1,0 + LLI r30,r1,8 + LLI r31,r1,16 +- ADDIK r1,r1,24 ++ ADDLIK r1,r1,24 + RTSD r15,8 + NOP + #else +diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S +index 9bf65c3..3bd5d48 100644 +--- a/libgcc/config/microblaze/umodsi3.S ++++ b/libgcc/config/microblaze/umodsi3.S +@@ -46,7 +46,7 @@ + __umodsi3: + .frame r1,0,r15 + +- addik r1,r1,-24 ++ addlik r1,r1,-24 + sli r29,r1,0 + sli r30,r1,8 + sli r31,r1,16 +@@ -59,27 +59,77 @@ __umodsi3: + swi r30,r1,4 + swi r31,r1,8 + #endif ++#ifdef __arch64__ ++ BEAEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error ++ BEAEQId r5,$LaResult_Is_Zero # Result is Zero ++#else + BEQI r6,$LaDiv_By_Zero # Div_by_Zero # Division Error + BEQId r5,$LaResult_Is_Zero # Result is Zero ++#endif + ADDIK r3,r0,0 # Clear div + ADDIK r30,r0,0 # clear mod + ADDIK r29,r0,32 # Initialize the loop count + + # Check if r6 and r5 are equal # if yes, return 0 + rsub r18,r5,r6 +- beqi r18,$LaRETURN_HERE + ++#ifdef __arch64__ ++ beaeqi r18,$LaRETURN_HERE ++#else ++ beqi r18,$LaRETURN_HERE ++#endif + # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5 + xor r18,r5,r6 ++#ifdef __arch64__ ++ beageid r18,16 ++ addik r3,r5,0 ++ bealti r6,$LaRETURN_HERE ++ breai $LCheckr6 ++ rsub r18,r5,r6 # MICROBLAZEcmp ++ beagti r18,$LaRETURN_HERE ++#else + bgeid r18,16 + addik r3,r5,0 + blti r6,$LaRETURN_HERE + bri $LCheckr6 + rsub r18,r5,r6 # MICROBLAZEcmp + bgti r18,$LaRETURN_HERE +- ++#endif + # If r6 [bit 31] is set, then return result as r5-r6 + $LCheckr6: ++#ifdef __arch64__ ++ beagtid r6,$LaDIV0 ++ addik r3,r0,0 ++ addik r18,r0,0x7fffffff ++ and r5,r5,r18 ++ and r6,r6,r18 ++ breaid $LaRETURN_HERE ++ rsub r3,r6,r5 ++# First part: try to find the first '1' in the r5 ++$LaDIV0: ++ BEALTI r5,$LaDIV2 ++$LaDIV1: ++ ADD r5,r5,r5 # left shift logical r5 ++ BEAGEID r5,$LaDIV1 # ++ ADDIK r29,r29,-1 ++$LaDIV2: ++ ADD r5,r5,r5 # left shift logical r5 get the '1' into the Carry ++ ADDC r3,r3,r3 # Move that bit into the Mod register ++ rSUB r31,r6,r3 # Try to subtract (r3 a r6) ++ BEALTi r31,$LaMOD_TOO_SMALL ++ OR r3,r0,r31 # Move the r31 to mod since the result was positive ++ ADDIK r30,r30,1 ++$LaMOD_TOO_SMALL: ++ ADDIK r29,r29,-1 ++ BEAEQi r29,$LaLOOP_END ++ ADD r30,r30,r30 # Shift in the '1' into div ++ BREAI $LaDIV2 # Div2 ++$LaLOOP_END: ++ BREAI $LaRETURN_HERE ++$LaDiv_By_Zero: ++$LaResult_Is_Zero: ++ or r3,r0,r0 # set result to 0 ++#else + bgtid r6,$LaDIV0 + addik r3,r0,0 + addik r18,r0,0x7fffffff +@@ -111,7 +161,7 @@ $LaLOOP_END: + $LaDiv_By_Zero: + $LaResult_Is_Zero: + or r3,r0,r0 # set result to 0 +- ++#endif + #ifdef __arch64__ + $LaRETURN_HERE: + # Restore values of CSRs and that of r3 and the divisor and the dividend +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch new file mode 100644 index 0000000000..690bc72737 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0061-Author-Nagaraju-nmekala-xilinx.com.patch @@ -0,0 +1,479 @@ +From e1b8cfe6c0b4a0bd90ecbd3e85ae7114df21b6cc Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Thu, 18 Apr 2019 16:00:37 +0530 +Subject: [PATCH 61/62] Author: Nagaraju <nmekala@xilinx.com> Date: Wed Apr + 17 14:11:00 2019 +0530 + + [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default + By default MB-64 is generatting barrel-shift instructions. It has been + removed from default. Barrel-shift instructions will be generated only if + barrel-shifter is enabled. Similarly to double instructions as well. + + Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> +--- + gcc/config/microblaze/microblaze.c | 2 +- + gcc/config/microblaze/microblaze.md | 269 +++++++++++++++++++++++++++++++++--- + 2 files changed, 252 insertions(+), 19 deletions(-) + +diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c +index 33d183e..c321b03 100644 +--- a/gcc/config/microblaze/microblaze.c ++++ b/gcc/config/microblaze/microblaze.c +@@ -3868,7 +3868,7 @@ microblaze_expand_divide (rtx operands[]) + emit_insn (gen_rtx_CLOBBER (Pmode, reg18)); + + if (TARGET_MB_64) { +- emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4))); ++ emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4))); + emit_insn (gen_adddi3 (regt1, regt1, operands[2])); + } + else { +diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md +index 8bd175f..b5b60fb 100644 +--- a/gcc/config/microblaze/microblaze.md ++++ b/gcc/config/microblaze/microblaze.md +@@ -545,7 +545,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (plus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dadd\t%0,%1,%2" + [(set_attr "type" "fadd") + (set_attr "mode" "DF") +@@ -555,7 +555,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (minus:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "drsub\t%0,%2,%1" + [(set_attr "type" "frsub") + (set_attr "mode" "DF") +@@ -565,7 +565,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (mult:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dmul\t%0,%1,%2" + [(set_attr "type" "fmul") + (set_attr "mode" "DF") +@@ -575,7 +575,7 @@ + [(set (match_operand:DF 0 "register_operand" "=d") + (div:DF (match_operand:DF 1 "register_operand" "d") + (match_operand:DF 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "ddiv\t%0,%2,%1" + [(set_attr "type" "fdiv") + (set_attr "mode" "DF") +@@ -585,7 +585,7 @@ + (define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (sqrt:DF (match_operand:DF 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dsqrt\t%0,%1" + [(set_attr "type" "fsqrt") + (set_attr "mode" "DF") +@@ -594,7 +594,7 @@ + (define_insn "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "=d") + (float:DF (match_operand:DI 1 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dbl\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DF") +@@ -603,7 +603,7 @@ + (define_insn "fix_truncdfdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT" + "dlong\t%0,%1" + [(set_attr "type" "fcvt") + (set_attr "mode" "DI") +@@ -1299,6 +1299,34 @@ + (set_attr "mode" "DI") + (set_attr "length" "4")]) + ++(define_insn "*movdi_internal2_bshift" ++ [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") ++ (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ case 2: ++ if (GET_CODE (operands[1]) == CONST_INT && ++ (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) ++ return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ else ++ return "addlik\t%0,r0,%1"; ++ case 3: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 5: ++ case 6: ++ return "sl%i0\t%z1,%0"; ++ } ++ } ++ [(set_attr "type" "load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store") ++ (set_attr "mode" "DI") ++ (set_attr "length" "4,4,12,4,8,4,8")]) ++ + (define_insn "*movdi_internal2" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d, d,d,R,m") + (match_operand:DI 1 "move_src_operand" " d,I,Mnis,R,m,dJ,dJ"))] +@@ -1312,7 +1340,15 @@ + case 2: + if (GET_CODE (operands[1]) == CONST_INT && + (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888)) +- return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; ++ { ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; ++ } + else + return "addlik\t%0,r0,%1"; + case 3: +@@ -1386,7 +1422,7 @@ + (define_insn "movdi_long_int" + [(set (match_operand:DI 0 "nonimmediate_operand" "=d") + (match_operand:DI 1 "general_operand" "i"))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la"; + [(set_attr "type" "no_delay_arith") + (set_attr "mode" "DI") +@@ -1653,6 +1689,33 @@ + ;; movdf_internal + ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT + ;; ++(define_insn "*movdf_internal_64_bshift" ++ [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") ++ (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" ++ { ++ switch (which_alternative) ++ { ++ case 0: ++ return "addlk\t%0,%1,r0"; ++ case 1: ++ return "addlk\t%0,r0,r0"; ++ case 2: ++ case 4: ++ return "ll%i1\t%0,%1"; ++ case 3: ++ { ++ return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ } ++ case 5: ++ return "sl%i0\t%1,%0"; ++ } ++ gcc_unreachable (); ++ } ++ [(set_attr "type" "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store") ++ (set_attr "mode" "DF") ++ (set_attr "length" "4,4,4,16,4,4")]) ++ + (define_insn "*movdf_internal_64" + [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m") + (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))] +@@ -1669,7 +1732,13 @@ + return "ll%i1\t%0,%1"; + case 3: + { +- return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo"; ++ operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("addlik\t%0,r0,%h1", operands); ++ output_asm_insn ("addlik\t%2,r0,32", operands); ++ output_asm_insn ("addlik\t%2,%2,-1", operands); ++ output_asm_insn ("beaneid\t%2,.-8", operands); ++ output_asm_insn ("addlk\t%0,%0,%0", operands); ++ return "addlik\t%0,%0,%j1 #li => la"; + } + case 5: + return "sl%i0\t%1,%0"; +@@ -1789,11 +1858,21 @@ + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1803,7 +1882,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashift:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bsllli\t%0,%1,%2 + bslll\t%0,%1,%2" +@@ -1811,6 +1890,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashldi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashldi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashift:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "addlk\t%0,%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + ;; The following patterns apply when there is no barrel shifter present + + (define_insn "*ashlsi3_with_mul_delay" +@@ -1944,11 +2068,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -1958,7 +2092,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrai\t%0,%1,%2 + bslra\t%0,%1,%2" +@@ -1966,6 +2100,51 @@ else + (set_attr "mode" "DI,DI") + (set_attr "length" "4,4")] + ) ++ ++(define_insn "ashrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "arith") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "ashrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srla\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "ashrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (ashiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2083,11 +2262,21 @@ else + "TARGET_MB_64" + { + ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) +-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65) ++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT) + { + emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2])); + DONE; + } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2])) ++ { ++ emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2])); ++ DONE; ++ } ++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && GET_CODE (operands[2]) == REG) ++ { ++ emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2])); ++ DONE; ++ } + else + FAIL; + } +@@ -2097,7 +2286,7 @@ else + [(set (match_operand:DI 0 "register_operand" "=d,d") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") + (match_operand:DI 2 "arith_operand" "I,d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_BARREL_SHIFT" + "@ + bslrli\t%0,%1,%2 + bslrl\t%0,%1,%2" +@@ -2106,6 +2295,50 @@ else + (set_attr "length" "4,4")] + ) + ++(define_insn "lshrdi3_const" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "immediate_operand" "I")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ ++ output_asm_insn ("orli\t%3,r0,%2", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,%1,r0", operands); ++ ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "DI") ++ (set_attr "length" "20")] ++) ++ ++(define_insn "lshrdi3_reg" ++ [(set (match_operand:DI 0 "register_operand" "=&d") ++ (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") ++ (match_operand:DI 2 "register_operand" "d")))] ++ "TARGET_MB_64" ++ { ++ operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM); ++ output_asm_insn ("andli\t%3,%2,31", operands); ++ if (REGNO (operands[0]) != REGNO (operands[1])) ++ output_asm_insn ("addlk\t%0,r0,%1", operands); ++ /* Exit the loop if zero shift. */ ++ output_asm_insn ("beaeqid\t%3,.+24", operands); ++ /* Emit the loop. */ ++ output_asm_insn ("addlk\t%0,%0,r0", operands); ++ output_asm_insn ("addlik\t%3,%3,-1", operands); ++ output_asm_insn ("beaneid\t%3,.-8", operands); ++ return "srll\t%0,%0"; ++ } ++ [(set_attr "type" "multi") ++ (set_attr "mode" "SI") ++ (set_attr "length" "28")] ++) ++ + (define_expand "lshrsi3" + [(set (match_operand:SI 0 "register_operand" "=&d") + (lshiftrt:SI (match_operand:SI 1 "register_operand" "d") +@@ -2233,7 +2466,7 @@ else + (eq:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmpleq\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +@@ -2245,7 +2478,7 @@ else + (ne:DI + (match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")))] +- "TARGET_MB_64" ++ "TARGET_MB_64 && TARGET_PATTERN_COMPARE" + "pcmplne\t%0,%1,%2" + [(set_attr "type" "arith") + (set_attr "mode" "DI") +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch new file mode 100644 index 0000000000..e7dfa89c15 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-8/0062-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch @@ -0,0 +1,41 @@ +From 612e6579116e6714417ea21e6c13b0968bb6aac2 Mon Sep 17 00:00:00 2001 +From: Nagaraju <nmekala@xilinx.com> +Date: Wed, 8 May 2019 14:12:03 +0530 +Subject: [PATCH 62/62] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and + disable fivopts by default + +Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. + + * gcc/common/config/microblaze/microblaze-common.c + (microblaze_option_optimization_table): Disable fivopts by default. + +Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com> +--- + gcc/common/config/microblaze/microblaze-common.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c +index fe45f2e..2873d4b 100644 +--- a/gcc/common/config/microblaze/microblaze-common.c ++++ b/gcc/common/config/microblaze/microblaze-common.c +@@ -27,13 +27,15 @@ + /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */ + static const struct default_options microblaze_option_optimization_table[] = + { +- /* Turn off ivopts by default. It messes up cse. */ ++ /* Turn off ivopts by default. It messes up cse. ++ { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */ + { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 }, +- { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, + { OPT_LEVELS_NONE, 0, NULL, 0 } + }; + + #undef TARGET_DEFAULT_TARGET_FLAGS + #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT + ++#undef TARGET_OPTION_OPTIMIZATION_TABLE ++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table + struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER; +-- +2.7.4 + diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend deleted file mode 100644 index 9770af6110..0000000000 --- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_7.%.bbappend +++ /dev/null @@ -1,38 +0,0 @@ -# Add MicroBlaze Patches (only when using MicroBlaze) -FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-7:" -SRC_URI_append_microblaze = " \ - file://0001-Revert.patch \ - file://0002-microblaze.md-Improve-adddi3-and-subdi3-insn-definit.patch \ - file://0003-PR-target-83013.patch \ - file://0004-dejagnu-static-testing-on-qemu-suppress-warnings.patch \ - file://0005-Testsuite-explicitly-add-fivopts-for-tests-that-depe.patch \ - file://0006-Add-MicroBlaze-to-target-supports-for-atomic-builtin.patch \ - file://0007-Update-MicroBlaze-strings-test-for-new-scan-assembly.patch \ - file://0008-Allow-MicroBlaze-.weakext-pattern-in-testsuite.patch \ - file://0009-Add-MicroBlaze-to-check_profiling_available-Testsuit.patch \ - file://0010-Fix-atomic-side-effects.patch \ - file://0011-Fix-atomic-boolean-return-value.patch \ - file://0012-Fix-the-Microblaze-crash-with-msmall-divides-flag.patch \ - file://0013-Add-MicroBlaze-ashrsi_3_with_size_opt.patch \ - file://0014-Removed-MicroBlaze-moddi3-routinue.patch \ - file://0015-MicroBlaze-fixed-missing-save-of-r18-in-fast_interru.patch \ - file://0016-MicroBlaze-use-bralid-for-profiler-calls.patch \ - file://0017-Disable-fivopts-by-default-Turn-off-ivopts-by-defaul.patch \ - file://0018-Add-INIT_PRIORITY-support-Added-TARGET_ASM_CONSTRUCT.patch \ - file://0019-MicroBlaze-add-optimized-lshrsi3-When-barrel-shifter.patch \ - file://0020-Modified-MicroBlaze-trap-instruction.patch \ - file://0021-Reducing-Stack-space-for-arguments-Currently-in-Micr.patch \ - file://0022-Inline-Expansion-of-fsqrt-builtin.patch \ - file://0023-Update-MicroBlaze-ashlsi3-movsf-patterns.patch \ - file://0024-8-stage-pipeline-for-microblaze.patch \ - file://0025-MicroBlaze-correct-the-const-high-double-immediate-v.patch \ - file://0026-Fix-internal-compiler-error-with-msmall-divides.patch \ - file://0027-Fix-the-calculation-of-high-word-in-a-long-long-64-b.patch \ - file://0028-Add-new-bit-field-instructions.patch \ - file://0029-Fix-bug-in-MB-version-calculation.patch \ - file://0030-MicroBlaze-fixing-the-bug-in-the-bit-field-instructi.patch \ - file://0031-Fixing-the-issue-with-MicroBlaze-builtin_alloc.patch \ - file://0032-MicroBlaze-remove-bitfield-instructions-macros.patch \ - file://0033-MicroBlaze-fix-signed-bit-fields-with-bit-field-inst.patch \ - " - diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend new file mode 100644 index 0000000000..d6a819126c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-source_8.%.bbappend @@ -0,0 +1,65 @@ +# Add MicroBlaze Patches (only when using MicroBlaze) +FILESEXTRAPATHS_append_microblaze := "${THISDIR}/gcc-8:" +SRC_URI_append_microblaze = " \ +file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \ + file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \ + file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \ + file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \ + file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \ + file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \ + file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \ + file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \ + file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \ + file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \ + file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \ + file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \ + file://0013-Patch-microblaze-Fixed-missing-save-of-r18-in-fast_i.patch \ + file://0014-Patch-microblaze-Use-bralid-for-profiler-calls.patch \ + file://0015-Patch-microblaze-Disable-fivopts-by-default.patch \ + file://0016-Patch-microblaze-Removed-moddi3-routinue.patch \ + file://0017-Patch-microblaze-Add-INIT_PRIORITY-support.patch \ + file://0018-Patch-microblaze-Add-optimized-lshrsi3.patch \ + file://0019-Patch-microblaze-Modified-trap-instruction.patch \ + file://0020-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \ + file://0021-Patch-microblaze-Add-cbranchsi4_reg.patch \ + file://0022-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \ + file://0023-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \ + file://0024-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \ + file://0025-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \ + file://0026-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \ + file://0027-Patch-rtl-Optimization-Better-register-pressure-esti.patch \ + file://0028-Patch-microblaze-Correct-the-const-high-double-immed.patch \ + file://0029-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \ + file://0030-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \ + file://0031-Patch-microblaze-Add-new-bit-field-instructions.patch \ + file://0032-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \ + file://0033-Fixing-the-bug-in-the-bit-field-instruction.patch \ + file://0034-Patch-microblaze-Macros-used-in-Xilinx-internal-patc.patch \ + file://0035-Fixing-the-issue-with-the-builtin_alloc.patch \ + file://0036-Patch-Microblaze-reverting-the-cost-check-before-pro.patch \ + file://0037-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \ + file://0038-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \ + file://0039-Intial-commit-of-64-bit-Microblaze.patch \ + file://0040-Added-load-store-pattern-movdi-and-also-adding-missi.patch \ + file://0041-Intial-commit-for-64bit-MB-sources.patch \ + file://0042-re-arrangement-of-the-compare-branches.patch \ + file://0043-Patch-Microblaze-previous-commit-broke-the-handling-.patch \ + file://0044-Patch-Microblaze-Support-of-multilibs-with-m64.patch \ + file://0045-Fixed-issues-like.patch \ + file://0046-Fixed-below-issues.patch \ + file://0047-Added-double-arith-instructions.patch \ + file://0048-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \ + file://0049-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \ + file://0050-extending-the-Dwarf-support-to-64bit-Microblaze.patch \ + file://0051-fixing-the-typo-errors-in-umodsi3-file.patch \ + file://0052-fixing-the-32bit-LTO-related-issue9-1014024.patch \ + file://0053-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \ + file://0054-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \ + file://0055-fixing-the-long-long-long-mingw-toolchain-issue.patch \ + file://0057-Fix-the-MB-64-bug-of-handling-QI-objects.patch \ + file://0058-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \ + file://0059-Reverting-the-patch-as-kernel-boot-is-not-working-wi.patch \ + file://0060-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \ + file://0061-Author-Nagaraju-nmekala-xilinx.com.patch \ + file://0055-microblaze_linker_script_xilinx_ld.patch \ +" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb new file mode 100644 index 0000000000..d14ec53e3d --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb @@ -0,0 +1,19 @@ +SUMMARY = "OpenCL ICD library" +DESCRIPTION = "Open Source alternative to vendor specific OpenCL ICD loaders." + +# The LICENSE is BSD 2-Clause "Simplified" License +LICENSE = "BSD-2-Clause" +LIC_FILES_CHKSUM = "file://COPYING;md5=232257bbf7320320725ca9529d3782ab" + +SRC_URI = "git://github.com/OCL-dev/ocl-icd.git;protocol=https" + +PV = "2.2.12+git${SRCPV}" +SRCREV = "af79aebe4649f30dbd711c1bf6fc661eac6e5f01" + +S = "${WORKDIR}/git" + +inherit autotools + +DEPENDS = "ruby-native" + +BBCLASSEXTEND = "native" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb new file mode 100644 index 0000000000..9af4442da1 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb @@ -0,0 +1,29 @@ +SUMMARY = "Host API C++ bindings" +DESCRIPTION = "OpenCL compute API headers C++ bindings from Khronos Group" +LICENSE = "Khronos" +LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=7e4a01f0c56b39419aa287361a82df00" +SECTION = "base" + +SRC_URI = "git://github.com/KhronosGroup/OpenCL-CLHPP.git;protocol=https" + +PV = "2.0.10+git${SRCPV}" +SRCREV = "acd6972bc65845aa28bd9f670dec84cbf8b760f3" + +S = "${WORKDIR}/git" + +do_configure () { +: +} + +# Only cl2.hpp is necessary. +# Base on the repo, Directly input_cl2.hpp copied as cl2.hpp +do_compile () { +: +} + +do_install () { + install -d ${D}${includedir}/CL/ + install -m 0644 ${S}/input_cl2.hpp ${D}${includedir}/CL/cl2.hpp +} + +ALLOW_EMPTY_${PN} = "1" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend new file mode 100644 index 0000000000..afe3e9cda0 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-headers/opencl-headers_%.bbappend @@ -0,0 +1 @@ +ALLOW_EMPTY_${PN} = "1" diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb new file mode 100644 index 0000000000..d91f3b8f3c --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb @@ -0,0 +1,28 @@ +SUMMARY = "Xilinx Runtime(XRT) libraries" +DESCRIPTION = "Xilinx Runtime User Space Libraries and headers" + +LICENSE = "GPLv2 & Apache-2.0" +LIC_FILES_CHKSUM = "file://${WORKDIR}/git/LICENSE;md5=fa343562af4b9b922b8d7fe7b0b6d000 \ + file://runtime_src/driver/xclng/drm/xocl/LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263 \ + file://runtime_src/driver/xclng/xrt/user_gem/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57 \ + file://runtime_src/driver/xclng/tools/xbutil/LICENSE;md5=d273d63619c9aeaf15cdaf76422c4f87" + +SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https" + +PV = "2.2.0+git${SRCPV}" +SRCREV = "69a7e181d8d53c3b5dde9e8f17ace790141eaa01" + +S = "${WORKDIR}/git/src" + +inherit cmake + +BBCLASSEXTEND = "native nativesdk" + +# util-linux is for libuuid-dev. +DEPENDS = "libdrm opencl-headers ocl-icd opencl-clhpp boost util-linux git-replacement-native" +RDEPENDS_${PN} = "bash ocl-icd boost-system boost-filesystem" + +EXTRA_OECMAKE += " \ + -DCMAKE_BUILD_TYPE=Release \ + -DCMAKE_EXPORT_COMPILE_COMANDS=ON \ + " diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb new file mode 100644 index 0000000000..de437a1e23 --- /dev/null +++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/zocl/zocl_git.bb @@ -0,0 +1,14 @@ +SUMMARY = "Xilinx Runtime(XRT) driver module" +DESCRIPTION = "Xilinx Runtime driver module provides memory management and compute unit schedule" + +LICENSE = "GPLv2" +LIC_FILES_CHKSUM = "file://LICENSE;md5=b234ee4d69f5fce4486a80fdaf4a4263" + +SRC_URI = "git://github.com/Xilinx/XRT.git;protocol=https" + +PV = "2.2.0+git${SRCPV}" +SRCREV = "69a7e181d8d53c3b5dde9e8f17ace790141eaa01" + +S = "${WORKDIR}/git/src/runtime_src/driver/zynq/drm/zocl" + +inherit module |