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| author | Andrew Geissler <geissonator@yahoo.com> | 2020-04-13 21:39:40 +0300 |
|---|---|---|
| committer | Andrew Geissler <geissonator@yahoo.com> | 2020-05-05 16:30:44 +0300 |
| commit | 82c905dc58a36aeae40b1b273a12f63fb1973cf4 (patch) | |
| tree | 38caf00263451b5036435cdc36e035b25d32e623 /poky/meta/conf/machine/include/riscv/tune-riscv.inc | |
| parent | 83ecb75644b3d677c274188f9ac0b2374d6f6925 (diff) | |
| download | openbmc-82c905dc58a36aeae40b1b273a12f63fb1973cf4.tar.xz | |
meta-openembedded and poky: subtree updates
Squash of the following due to dependencies among them
and OpenBMC changes:
meta-openembedded: subtree update:d0748372d2..9201611135
meta-openembedded: subtree update:9201611135..17fd382f34
poky: subtree update:9052e5b32a..2e11d97b6c
poky: subtree update:2e11d97b6c..a8544811d7
The change log was too large for the jenkins plugin
to handle therefore it has been removed. Here is
the first and last commit of each subtree:
meta-openembedded:d0748372d2
cppzmq: bump to version 4.6.0
meta-openembedded:17fd382f34
mpv: Remove X11 dependency
poky:9052e5b32a
package_ipk: Remove pointless comment to trigger rebuild
poky:a8544811d7
pbzip2: Fix license warning
Change-Id: If0fc6c37629642ee207a4ca2f7aa501a2c673cd6
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Diffstat (limited to 'poky/meta/conf/machine/include/riscv/tune-riscv.inc')
| -rw-r--r-- | poky/meta/conf/machine/include/riscv/tune-riscv.inc | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/poky/meta/conf/machine/include/riscv/tune-riscv.inc b/poky/meta/conf/machine/include/riscv/tune-riscv.inc index 25d0463492..741eeb34db 100644 --- a/poky/meta/conf/machine/include/riscv/tune-riscv.inc +++ b/poky/meta/conf/machine/include/riscv/tune-riscv.inc @@ -3,10 +3,14 @@ require conf/machine/include/riscv/arch-riscv.inc TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations" TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations" +TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point" +TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point" + TUNEVALID[bigendian] = "Big endian mode" -AVAILTUNES += "riscv64 riscv32" +AVAILTUNES += "riscv64 riscv32 riscv64nf riscv32nf" +# Default TUNE_FEATURES_tune-riscv64 = "riscv64" TUNE_ARCH_tune-riscv64 = "riscv64" TUNE_PKGARCH_tune-riscv64 = "riscv64" @@ -17,3 +21,13 @@ TUNE_ARCH_tune-riscv32 = "riscv32" TUNE_PKGARCH_tune-riscv32 = "riscv32" PACKAGE_EXTRA_ARCHS_tune-riscv32 = "riscv32" +# No float +TUNE_FEATURES_tune-riscv64nf = "${TUNE_FEATURES_tune-riscv64} riscv64nf" +TUNE_ARCH_tune-riscv64nf = "riscv64" +TUNE_PKGARCH_tune-riscv64nf = "riscv64" +PACKAGE_EXTRA_ARCHS_tune-riscv64nf = "riscv64nf" + +TUNE_FEATURES_tune-riscv32nf = "${TUNE_FEATURES_tune-riscv32} riscv32nf" +TUNE_ARCH_tune-riscv32nf = "riscv32" +TUNE_PKGARCH_tune-riscv32nf = "riscv32" +PACKAGE_EXTRA_ARCHS_tune-riscv32nf = "riscv32nf" |