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| author | Jayanth Othayoth <ojayanth@in.ibm.com> | 2022-07-07 15:09:42 +0300 |
|---|---|---|
| committer | Andrew Geissler <andrew@geissonator.com> | 2022-07-12 14:59:53 +0300 |
| commit | 61298cff8d4df10e749715e7fe7d312ea0fd3db7 (patch) | |
| tree | a10512d5dad93fb4be2c52ea699874121c52ea7d /setup | |
| parent | 6d3702a269117a2dd28ad7a483dbe82661b8f104 (diff) | |
| download | openbmc-61298cff8d4df10e749715e7fe7d312ea0fd3db7.tar.xz | |
openpower: ipl: srcrev bump 49e7026d98..8fc1c2d6e3
Jayanth Othayoth (12):
libphal: deconfigureTgt skip primary processor deconfig
libphal: Add sbe halt state handling for threadStopProc chipop
libphal: SBE chip-op failure debug data support
ipl: changed clang-format file location
ipl: clang-format: disabled SortIncludes
ipl: enabled clang-format based source formatting
libphal: Added input target type check in isPrimaryProc api
libphal: deconfigureTgt api updates
ipl:: Added clock redundant mode check helper function
libipl:p10: redundant mode clock error handling support
libipl: ATTR_SYS_CLOCK_DECONFIG_STATE based clock state update
libipl: ATTR_SYS_CLOCK_DECONFIG_STATE size update
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I8e3aa976c79e55404e165770b044a389347a1c22
Diffstat (limited to 'setup')
0 files changed, 0 insertions, 0 deletions