diff options
Diffstat (limited to 'meta-arm/meta-arm-bsp/recipes-bsp/u-boot')
15 files changed, 94 insertions, 537 deletions
diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch index 63c42c70b7..9fd5b33b70 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch @@ -1,29 +1,29 @@ -From df23489adcba1cdcbcb4fefbed0896fc1f408700 Mon Sep 17 00:00:00 2001 -From: Emekcan Aras <emekcan.aras@arm.com> -Date: Wed, 2 Aug 2023 17:07:05 +0100 -Subject: [PATCH] Increase the unzipped Kernel size +From b57e05e95735b9b58e81b7a67f483b645c56811e Mon Sep 17 00:00:00 2001 +From: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> +Date: Fri, 11 Aug 2023 10:41:19 +0100 +Subject: [PATCH] corstone1000: detect inflated kernel size -Increases the unzipped kernel size for corstone1000. +use filesize variable set by unzip command Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Emekcan Aras <emekcan.aras@arm.com> +Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> --- configs/corstone1000_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig -index a0af413de8..54a5bca354 100644 +index b6b1ccdd78..8a10bca069 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig -@@ -15,7 +15,7 @@ CONFIG_DISTRO_DEFAULTS=y +@@ -17,7 +17,7 @@ CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" -CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" -+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xfb0000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" ++CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" CONFIG_CONSOLE_RECORD=y CONFIG_LOGLEVEL=7 # CONFIG_DISPLAY_CPUINFO is not set -- -2.17.1 +2.25.1 diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch new file mode 100644 index 0000000000..197a06950a --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch @@ -0,0 +1,47 @@ +From 98b33cc6b3a56f56224e0a6fe6c3564de7b1341a Mon Sep 17 00:00:00 2001 +From: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com> +Date: Tue, 8 Aug 2023 10:24:39 +0000 +Subject: [PATCH] corstone1000: ESRT: add unique firmware GUID + +Add unique Corstone-1000 firmware GUID + +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Anusmita Dutta Mazumder <anusmita.duttamazumder@arm.com> +--- + lib/efi_loader/efi_firmware.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c +index 6135f8ed1c..c9117ae2b2 100644 +--- a/lib/efi_loader/efi_firmware.c ++++ b/lib/efi_loader/efi_firmware.c +@@ -20,12 +20,12 @@ + #define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1') + + #if CONFIG_IS_ENABLED(TARGET_CORSTONE1000) +-#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \ +- EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \ +- 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f) ++/* Firmware GUID */ ++#define EFI_CORSTONE1000_FIRMWARE_GUID \ ++ EFI_GUID(0x989f3a4e, 0x46e0, 0x4cd0, 0x98, 0x77, \ ++ 0xa2, 0x5c, 0x70, 0xc0, 0x13, 0x29) + +- const efi_guid_t efi_firmware_image_type_uboot_raw = +- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID; ++efi_guid_t corstone1000_firmware_guid = EFI_CORSTONE1000_FIRMWARE_GUID; + + static efi_status_t efi_corstone1000_img_info_get ( + efi_uintn_t *image_info_size, +@@ -353,7 +353,7 @@ efi_status_t EFIAPI efi_firmware_get_image_info( + descriptor_version, descriptor_count, + descriptor_size, + package_version, package_version_name, +- &efi_firmware_image_type_uboot_raw); ++ &corstone1000_firmware_guid); + #else + ret = efi_fill_image_desc_array(image_info_size, image_info, + descriptor_version, descriptor_count, +-- +2.38.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch deleted file mode 100644 index 1d28631a21..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch +++ /dev/null @@ -1,139 +0,0 @@ -From 2bb9fb8414b8ad35ed5fc6c91a34c21cef285a01 Mon Sep 17 00:00:00 2001 -From: Rui Miguel Silva <rui.silva@linaro.org> -Date: Wed, 18 Dec 2019 21:52:34 +0000 -Subject: [PATCH 1/2] armv7: adding generic timer access through MMIO - -Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> - -This driver enables the ARMv7 generic timer. - -The access to the timer registers is through memory mapping (MMIO). - -This driver can be used by u-boot to access to the timer through MMIO -when arch_timer is not available in the core (access using system -instructions not possible), for example, in case of Cortex-A5. - -This driver configures and enables the generic timer at -the u-boot initcall level (timer_init) before u-boot relocation. - -Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> -Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> - - -Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> ---- - arch/arm/cpu/armv7/Makefile | 1 + - arch/arm/cpu/armv7/mmio_timer.c | 75 +++++++++++++++++++++++++++++++++ - scripts/config_whitelist.txt | 1 + - 3 files changed, 77 insertions(+) - create mode 100644 arch/arm/cpu/armv7/mmio_timer.c - -diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile -index bfbd85ae64ef..1a0a24e53110 100644 ---- a/arch/arm/cpu/armv7/Makefile -+++ b/arch/arm/cpu/armv7/Makefile -@@ -28,6 +28,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o - obj-$(CONFIG_IPROC) += iproc-common/ - obj-$(CONFIG_KONA) += kona-common/ - obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o -+obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o - - ifneq (,$(filter s5pc1xx exynos,$(SOC))) - obj-y += s5p-common/ -diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c -new file mode 100644 -index 000000000000..edd806e06e42 ---- /dev/null -+++ b/arch/arm/cpu/armv7/mmio_timer.c -@@ -0,0 +1,75 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (c) 2019, Arm Limited. All rights reserved. -+ * -+ */ -+ -+#include <common.h> -+#include <asm/io.h> -+#include <div64.h> -+#include <bootstage.h> -+#include <asm/global_data.h> -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+#define CNTCTLBASE 0x1a020000UL -+#define CNTREADBASE 0x1a030000UL -+#define CNTEN (1 << 0) -+#define CNTFCREQ (1 << 8) -+ -+static inline uint32_t mmio_read32(uintptr_t addr) -+{ -+ return *(volatile uint32_t*)addr; -+} -+ -+static inline void mmio_write32(uintptr_t addr, uint32_t data) -+{ -+ *(volatile uint32_t*)addr = data; -+} -+ -+int timer_init(void) -+{ -+ /* calculate the frequency in ms */ -+ gd->arch.timer_rate_hz = COUNTER_FREQUENCY / CONFIG_SYS_HZ; -+ -+ /* configure CNTFID0 register: set the base frequency */ -+ mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY); -+ -+ /* -+ * configure CNTCR register: -+ * enable the generic counter and; -+ * select the first frequency entry -+ */ -+ mmio_write32(CNTCTLBASE, CNTFCREQ | CNTEN); -+ -+ return 0; -+} -+ -+unsigned long long get_ticks(void) -+{ -+ return (((u64)(mmio_read32(CNTREADBASE + 0x4)) << 32) | -+ mmio_read32(CNTREADBASE)); -+} -+ -+ulong get_timer(ulong base) -+{ -+ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; -+} -+ -+void __udelay(unsigned long usec) -+{ -+ unsigned long endtime; -+ -+ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, -+ 1000UL); -+ -+ endtime += get_ticks(); -+ -+ while (get_ticks() < endtime) -+ ; -+} -+ -+ulong get_tbclk(void) -+{ -+ return gd->arch.timer_rate_hz; -+} -diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt -index ea71f9d23449..1496d9b88233 100644 ---- a/scripts/config_whitelist.txt -+++ b/scripts/config_whitelist.txt -@@ -610,6 +610,7 @@ CONFIG_SYS_MMC_U_BOOT_DST - CONFIG_SYS_MMC_U_BOOT_OFFS - CONFIG_SYS_MMC_U_BOOT_SIZE - CONFIG_SYS_MMC_U_BOOT_START -+CONFIG_SYS_MMIO_TIMER - CONFIG_SYS_MOR_VAL - CONFIG_SYS_MRAM_BASE - CONFIG_SYS_NAND_AMASK --- -2.39.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch deleted file mode 100644 index 5aec24cc47..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch +++ /dev/null @@ -1,299 +0,0 @@ -From 376e7cc533e27f943191d44c112e3812885b8fd1 Mon Sep 17 00:00:00 2001 -From: Rui Miguel Silva <rui.silva@linaro.org> -Date: Wed, 8 Jan 2020 09:48:11 +0000 -Subject: [PATCH 2/2] board: arm: add corstone500 board - -Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> - -Add support for the Arm corstone500 platform, with a cortex-a5 -chip, add the default configuration, initialization and -makefile for this system. - -Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> ---- - arch/arm/Kconfig | 10 +++ - board/armltd/corstone500/Kconfig | 12 +++ - board/armltd/corstone500/Makefile | 8 ++ - board/armltd/corstone500/corstone500.c | 48 ++++++++++++ - configs/corstone500_defconfig | 41 ++++++++++ - include/configs/corstone500.h | 102 +++++++++++++++++++++++++ - 6 files changed, 221 insertions(+) - create mode 100644 board/armltd/corstone500/Kconfig - create mode 100644 board/armltd/corstone500/Makefile - create mode 100644 board/armltd/corstone500/corstone500.c - create mode 100644 configs/corstone500_defconfig - create mode 100644 include/configs/corstone500.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index cac4fa09fd32..b875c1ef3d32 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1309,6 +1309,15 @@ config TARGET_CORSTONE1000 - select PL01X_SERIAL - select DM - -+config TARGET_CORSTONE500 -+ bool "Support Corstone500" -+ select CPU_V7A -+ select SEMIHOSTING -+ select PL01X_SERIAL -+ help -+ This enables support for Corstone500 ARM which is a -+ Cortex-A5 system -+ - config TARGET_TOTAL_COMPUTE - bool "Support Total Compute Platform" - select ARM64 -@@ -2264,6 +2273,7 @@ source "board/bosch/shc/Kconfig" - source "board/bosch/guardian/Kconfig" - source "board/Marvell/octeontx/Kconfig" - source "board/Marvell/octeontx2/Kconfig" -+source "board/armltd/corstone500/Kconfig" - source "board/armltd/vexpress/Kconfig" - source "board/armltd/vexpress64/Kconfig" - source "board/cortina/presidio-asic/Kconfig" -diff --git a/board/armltd/corstone500/Kconfig b/board/armltd/corstone500/Kconfig -new file mode 100644 -index 000000000000..8e689bd1fdc8 ---- /dev/null -+++ b/board/armltd/corstone500/Kconfig -@@ -0,0 +1,12 @@ -+if TARGET_CORSTONE500 -+ -+config SYS_BOARD -+ default "corstone500" -+ -+config SYS_VENDOR -+ default "armltd" -+ -+config SYS_CONFIG_NAME -+ default "corstone500" -+ -+endif -diff --git a/board/armltd/corstone500/Makefile b/board/armltd/corstone500/Makefile -new file mode 100644 -index 000000000000..6598fdd3ae0d ---- /dev/null -+++ b/board/armltd/corstone500/Makefile -@@ -0,0 +1,8 @@ -+# SPDX-License-Identifier: GPL-2.0+ -+# -+# (C) Copyright 2022 ARM Limited -+# (C) Copyright 2022 Linaro -+# Rui Miguel Silva <rui.silva@linaro.org> -+# -+ -+obj-y := corstone500.o -diff --git a/board/armltd/corstone500/corstone500.c b/board/armltd/corstone500/corstone500.c -new file mode 100644 -index 000000000000..e878f5c6a521 ---- /dev/null -+++ b/board/armltd/corstone500/corstone500.c -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * (C) Copyright 2022 ARM Limited -+ * (C) Copyright 2022 Linaro -+ * Rui Miguel Silva <rui.silva@linaro.org> -+ */ -+ -+#include <common.h> -+#include <dm.h> -+#include <dm/platform_data/serial_pl01x.h> -+#include <malloc.h> -+#include <asm/global_data.h> -+ -+static const struct pl01x_serial_plat serial_platdata = { -+ .base = V2M_UART0, -+ .type = TYPE_PL011, -+ .clock = CONFIG_PL011_CLOCK, -+}; -+ -+U_BOOT_DRVINFO(corstone500_serials) = { -+ .name = "serial_pl01x", -+ .plat = &serial_platdata, -+}; -+ -+int board_init(void) -+{ -+ return 0; -+} -+ -+int dram_init(void) -+{ -+ gd->ram_size = PHYS_SDRAM_1_SIZE; -+ -+ return 0; -+} -+ -+int dram_init_banksize(void) -+{ -+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; -+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -+ -+ return 0; -+} -+ -+void reset_cpu(ulong addr) -+{ -+} -+ -diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig -new file mode 100644 -index 000000000000..91661beb8d8d ---- /dev/null -+++ b/configs/corstone500_defconfig -@@ -0,0 +1,41 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_TARGET_CORSTONE500=y -+CONFIG_TEXT_BASE=0x88000000 -+CONFIG_SYS_MALLOC_LEN=0x840000 -+CONFIG_NR_DRAM_BANKS=1 -+CONFIG_ENV_SIZE=0x40000 -+CONFIG_SYS_PROMPT="corstone500# " -+CONFIG_IDENT_STRING=" corstone500 aarch32" -+CONFIG_SYS_LOAD_ADDR=0x90000000 -+CONFIG_SYS_MEMTEST_START=0x80000000 -+CONFIG_SYS_MEMTEST_END=0xff000000 -+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 -+CONFIG_SUPPORT_RAW_INITRD=y -+CONFIG_BOOTDELAY=1 -+CONFIG_USE_BOOTARGS=y -+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9" -+# CONFIG_DISPLAY_CPUINFO is not set -+# CONFIG_DISPLAY_BOARDINFO is not set -+CONFIG_HUSH_PARSER=y -+# CONFIG_CMD_CONSOLE is not set -+CONFIG_CMD_BOOTZ=y -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_EDITENV is not set -+# CONFIG_CMD_ENV_EXISTS is not set -+CONFIG_CMD_MEMTEST=y -+CONFIG_CMD_ARMFLASH=y -+# CONFIG_CMD_LOADS is not set -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_DHCP=y -+# CONFIG_CMD_NFS is not set -+CONFIG_CMD_MII=y -+CONFIG_CMD_PING=y -+CONFIG_CMD_CACHE=y -+CONFIG_CMD_FAT=y -+CONFIG_DM=y -+CONFIG_MTD_NOR_FLASH=y -+CONFIG_DM_SERIAL=y -+CONFIG_OF_LIBFDT=y -diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h -new file mode 100644 -index 000000000000..416f5fa4399d ---- /dev/null -+++ b/include/configs/corstone500.h -@@ -0,0 +1,102 @@ -+/* SPDX-License-Identifier: GPL-2.0+ */ -+/* -+ * (C) Copyright 2022 ARM Limited -+ * (C) Copyright 2022 Linaro -+ * Rui Miguel Silva <rui.silva@linaro.org> -+ * -+ * Configuration for Cortex-A5 Corstone500. Parts were derived from other ARM -+ * configurations. -+ */ -+ -+#ifndef __CORSTONE500_H -+#define __CORSTONE500_H -+ -+/* Generic Timer Definitions */ -+#define CONFIG_SYS_HZ_CLOCK 7500000 -+#define CONFIG_SYS_HZ 1000 -+#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK -+ -+#ifdef CONFIG_CORSTONE500_MEMORY_MAP_EXTENDED -+#define V2M_SRAM0 0x00010000 -+#define V2M_SRAM1 0x02200000 -+#define V2M_QSPI 0x0a800000 -+#else -+#define V2M_SRAM0 0x00000000 -+#define V2M_SRAM1 0x02000000 -+#define V2M_QSPI 0x08000000 -+#endif -+ -+#define V2M_DEBUG 0x10000000 -+#define V2M_BASE_PERIPH 0x1a000000 -+#define V2M_A5_PERIPH 0x1c000000 -+#define V2M_L2CC_PERIPH 0x1c010000 -+ -+#define V2M_MASTER_EXPANSION0 0x40000000 -+#define V2M_MASTER_EXPANSION1 0x60000000 -+ -+#define V2M_BASE 0x80000000 -+ -+#define V2M_PERIPH_OFFSET(x) (x << 16) -+ -+#define V2M_SYSID (V2M_BASE_PERIPH) -+#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) -+#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2)) -+#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3)) -+#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4)) -+#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5)) -+ -+#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16)) -+#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17)) -+ -+#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) -+#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) -+ -+#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) -+#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) -+ -+/* PL011 Serial Configuration */ -+#define CONFIG_CONS_INDEX 0 -+#define CONFIG_PL011_CLOCK 7500000 -+ -+/* Physical Memory Map */ -+#define PHYS_SDRAM_1 (V2M_BASE) -+ -+/* Top 16MB reserved for secure world use */ -+#define DRAM_SEC_SIZE 0x01000000 -+#define PHYS_SDRAM_1_SIZE (0x80000000 - DRAM_SEC_SIZE) -+ -+/* Miscellaneous configurable options */ -+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -+ -+#define CONFIG_SYS_MMIO_TIMER -+ -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ "kernel_name=Image\0" \ -+ "kernel_addr=0x80f00000\0" \ -+ "initrd_name=ramdisk.img\0" \ -+ "initrd_addr=0x84000000\0" \ -+ "fdt_name=devtree.dtb\0" \ -+ "fdt_addr=0x83000000\0" \ -+ "fdt_high=0xffffffff\0" \ -+ "initrd_high=0xffffffff\0" -+ -+#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \ -+ "cp.b 0x80100000 $kernel_addr 0xb00000; " \ -+ "cp.b 0x80d00000 $initrd_addr 0x800000; " \ -+ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr" -+ -+/* Monitor Command Prompt */ -+#define CONFIG_SYS_FLASH_BASE 0x80000000 -+/* Store environment at top of flash */ -+#define CONFIG_ENV_ADDR 0x0a7c0000 -+#define CONFIG_ENV_SECT_SIZE 0x0040000 -+ -+#define CONFIG_SYS_FLASH_CFI 1 -+#define CONFIG_FLASH_CFI_DRIVER 1 -+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -+#define CONFIG_SYS_MAX_FLASH_BANKS 1 -+ -+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ -+#define FLASH_MAX_SECTOR_SI 0x00040000 -+#define CONFIG_ENV_IS_IN_FLASH 1 -+#endif --- -2.39.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch index dd6b77d3a5..45db74e133 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch @@ -1,7 +1,7 @@ -From e90aa7853ae32cb03c86249a6c572ec88cdebaa2 Mon Sep 17 00:00:00 2001 +From 401a88bf6019941d4095476de76af5893686d6f6 Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Wed, 26 May 2021 17:41:10 +0100 -Subject: [PATCH 1/9] armv8: Add ARMv8 MPU configuration logic +Subject: [PATCH] armv8: Add ARMv8 MPU configuration logic Detect whether an MMU is present at the current exception level. If not, initialize the MPU instead of the MMU during init, and clear the @@ -19,6 +19,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17 + --- arch/arm/cpu/armv8/cache_v8.c | 101 ++++++++++++++++++++++++++++++- arch/arm/include/asm/armv8/mpu.h | 59 ++++++++++++++++++ @@ -27,7 +28,7 @@ Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17 create mode 100644 arch/arm/include/asm/armv8/mpu.h diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c -index e4736e5643..798aed8058 100644 +index 2a226fd063..8611a35eb3 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -15,6 +15,7 @@ @@ -145,8 +146,8 @@ index e4736e5643..798aed8058 100644 + } } - set_sctlr(get_sctlr() | CR_C); -@@ -519,7 +610,11 @@ void dcache_disable(void) + /* Set up page tables only once (it is done also by mmu_setup()) */ +@@ -523,7 +614,11 @@ void dcache_disable(void) set_sctlr(sctlr & ~(CR_C|CR_M)); flush_dcache_all(); @@ -254,6 +255,3 @@ index 87d1c77e8b..4510db98a2 100644 /* * ID_AA64PFR0_EL1 bits definitions */ --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch index b8cab45e40..103e48479c 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch @@ -1,7 +1,7 @@ -From 181f5efb401ffaa5ab0898b07a976796f75e502a Mon Sep 17 00:00:00 2001 +From 5b42322cb57692dbea7d2c39fd8769b6f0f6b7af Mon Sep 17 00:00:00 2001 From: Qi Feng <qi.feng@arm.com> Date: Tue, 26 Jul 2022 18:13:23 +0800 -Subject: [PATCH 2/9] vexpress64: add MPU memory map for the BASER_FVP +Subject: [PATCH] vexpress64: add MPU memory map for the BASER_FVP The previous patch added support for initializing an Armv8 MPU. There is only an MPU at S-EL2 on the BASER_FVP, so add a platform-specific MPU memory map. @@ -12,6 +12,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Signed-off-by: Qi Feng <qi.feng@arm.com> + --- board/armltd/vexpress64/vexpress64.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) @@ -56,6 +57,3 @@ index af326dc6f4..2310d18eb7 100644 static struct mm_region vexpress64_mem_map[] = { { .virt = V2M_PA_BASE, --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch index caabf804b2..5953abc652 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch @@ -1,8 +1,7 @@ -From 07cc3e4af3def76d92faf39712d4fd8717b21d2b Mon Sep 17 00:00:00 2001 +From ffb0f72a67926c3053308cf03420bc0c36675d42 Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Fri, 10 Dec 2021 11:41:19 +0000 -Subject: [PATCH 3/9] armv8: Allow disabling exception vectors on non-SPL - builds +Subject: [PATCH] armv8: Allow disabling exception vectors on non-SPL builds On the BASER_FVP, U-Boot shares EL2 with another bootloader, so we do not wish to overide the exception vector, but we are also not using an @@ -19,6 +18,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Change-Id: I0cf0fc6d7ef4d45791411cf1f67c65e198cc8b2b + --- arch/arm/cpu/armv8/Kconfig | 10 ++++++++-- arch/arm/cpu/armv8/Makefile | 6 ++---- @@ -72,7 +72,7 @@ index 2e4bf9e038..001a31cae7 100644 endif obj-y += tlb.o diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S -index 28f0df13f0..f831e77af3 100644 +index f3ea858577..7fad901336 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -104,7 +104,7 @@ pie_skip_reloc: @@ -102,6 +102,3 @@ index 495eb1dee3..683d983c36 100644 # CONFIG_MMC is not set CONFIG_VIRTIO_MMIO=y +CONFIG_ARMV8_EXCEPTION_VECTORS=n --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch index 81758fce71..157a15d7df 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch @@ -1,7 +1,7 @@ -From 30405f59881c73946b6b0ffdbf25804f9fbf1585 Mon Sep 17 00:00:00 2001 +From 14e204ffca5870d6bfd238627937a2028c88589d Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Wed, 14 Jul 2021 12:44:27 +0100 -Subject: [PATCH 4/9] armv8: ARMV8_SWITCH_TO_EL1 improvements +Subject: [PATCH] armv8: ARMV8_SWITCH_TO_EL1 improvements Convert CONFIG_ARMV8_SWITCH_TO_EL1 to a Kconfig variable. @@ -16,6 +16,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Change-Id: If98478148d6d8d1f732acac5439276700614815f + --- arch/arm/cpu/armv8/exception_level.c | 21 ++++++++++++++-- arch/arm/lib/bootm.c | 36 ++++++++++++++++------------ @@ -66,7 +67,7 @@ index b11936548f..4aad1550f4 100644 } } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c -index 9f086f3b90..b044aeca88 100644 +index e414ef8267..9a86c17d2a 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -270,7 +270,6 @@ __weak void update_os_arch_secondary_cores(uint8_t os_arch) @@ -84,8 +85,8 @@ index 9f086f3b90..b044aeca88 100644 -#endif /* Subcommand: GO */ - static void boot_jump_linux(bootm_headers_t *images, int flag) -@@ -312,21 +310,29 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) + static void boot_jump_linux(struct bootm_headers *images, int flag) +@@ -312,21 +310,29 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) update_os_arch_secondary_cores(images->os.arch); @@ -137,6 +138,3 @@ index 683d983c36..6044f82b00 100644 CONFIG_VIRTIO_MMIO=y CONFIG_ARMV8_EXCEPTION_VECTORS=n +CONFIG_ARMV8_SWITCH_TO_EL1=y --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch index f64db3bf46..82926cc36e 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch @@ -1,8 +1,7 @@ -From a6daca56b77d7f1b26483f10eb33ebdd6e157d3e Mon Sep 17 00:00:00 2001 +From e3d24bc1fd0b09915b5181de1282f7008bbf776f Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Fri, 10 Dec 2021 16:37:26 +0000 -Subject: [PATCH 5/9] armv8: Make disabling HVC configurable when switching to - EL1 +Subject: [PATCH] armv8: Make disabling HVC configurable when switching to EL1 On the BASER_FVP there is no EL3, so HVC is used to provide PSCI services. Therefore we cannot disable hypercalls. @@ -15,6 +14,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Change-Id: I463d82f1db8a3cafcab40a9c0c208753569cc300 + --- arch/arm/cpu/armv8/Kconfig | 9 +++++++++ arch/arm/include/asm/macro.h | 10 ++++++++-- @@ -78,6 +78,3 @@ index 6044f82b00..6226f6b2c1 100644 CONFIG_ARMV8_EXCEPTION_VECTORS=n CONFIG_ARMV8_SWITCH_TO_EL1=y +CONFIG_ARMV8_DISABLE_HVC=n --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch index ebbc939c05..eb2273e565 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch @@ -1,7 +1,7 @@ -From 862d3f1ac66a75cdf48adbdebd8adbaf671a9366 Mon Sep 17 00:00:00 2001 +From 571f44d5292cfead6f68bf4c6c9519872337bfd0 Mon Sep 17 00:00:00 2001 From: Qi Feng <qi.feng@arm.com> Date: Thu, 28 Jul 2022 17:47:18 +0800 -Subject: [PATCH 6/9] vexpress64: Do not set COUNTER_FREQUENCY +Subject: [PATCH] vexpress64: Do not set COUNTER_FREQUENCY VExpress boards normally run as a second-stage bootloader so should not need to modify CNTFRQ_EL0. On the BASER_FVP, U-Boot can modify it if @@ -13,6 +13,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Signed-off-by: Qi Feng <qi.feng@arm.com> + --- configs/vexpress_aemv8r_defconfig | 1 - 1 file changed, 1 deletion(-) @@ -27,6 +28,3 @@ index 6226f6b2c1..b902a6a7d9 100644 CONFIG_ARCH_VEXPRESS64=y CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="arm_fvp" --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch index 8c09ed2b74..6f5bfa38c4 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch @@ -1,7 +1,7 @@ -From 32beea722c1167c9b33f1ecfdc28d360cabd6823 Mon Sep 17 00:00:00 2001 +From df01346bb63c821cf8e73202e2894ceda9cb692b Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Tue, 22 Feb 2022 15:32:51 +0000 -Subject: [PATCH 7/9] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r +Subject: [PATCH] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r defconfig Issue-Id: SCM-3874 @@ -9,6 +9,7 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Change-Id: Ide0532cf2de89f1bca9c8d4bd2ed0c1a1c57599f + --- configs/vexpress_aemv8r_defconfig | 1 + 1 file changed, 1 insertion(+) @@ -22,6 +23,3 @@ index b902a6a7d9..a58a9db385 100644 CONFIG_ARMV8_SWITCH_TO_EL1=y CONFIG_ARMV8_DISABLE_HVC=n +CONFIG_OF_LIBFDT_OVERLAY=y --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch index 8be14ee85a..61bdf928f4 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch @@ -1,7 +1,7 @@ -From 01490ab8deb0f0b61eeb55a02ee5ea430cfe7eee Mon Sep 17 00:00:00 2001 +From 665ab8253a0e3e17db54a1682bbee0f5659939a2 Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Wed, 18 May 2022 15:24:19 +0100 -Subject: [PATCH 8/9] armv8: Allow PRBAR MPU attributes to be configured +Subject: [PATCH] armv8: Allow PRBAR MPU attributes to be configured In a previous patch, support was added to initialize an S-EL2 MPU on armv8r64 machines. This implementation allowed the PRLAR attribute @@ -21,6 +21,7 @@ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Upstream-Status: Inappropriate [other] Implementation pending further discussion Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984 + --- arch/arm/cpu/armv8/cache_v8.c | 12 ++++++++---- arch/arm/include/asm/armv8/mpu.h | 3 ++- @@ -28,7 +29,7 @@ Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c -index 798aed8058..e336339281 100644 +index 8611a35eb3..f7de952187 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -390,7 +390,9 @@ static void mpu_clear_regions(void) @@ -100,6 +101,3 @@ index 2310d18eb7..531fa4d618 100644 }, { /* List terminator */ 0, --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch index 0e0a248136..a4bc746e30 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch @@ -1,7 +1,7 @@ -From 0f15f6b02825b042ddc1d753f62cf87f30b1fe12 Mon Sep 17 00:00:00 2001 +From c7301588a3aec9ebf36749da601d0d6e3d807bfc Mon Sep 17 00:00:00 2001 From: Peter Hoyes <Peter.Hoyes@arm.com> Date: Thu, 19 May 2022 09:02:32 +0100 -Subject: [PATCH 9/9] armv8: Enable icache when switching exception levels in +Subject: [PATCH] armv8: Enable icache when switching exception levels in bootefi bootefi calls the function switch_to_non_secure_mode before calling the @@ -26,6 +26,7 @@ Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com> Upstream-Status: Inappropriate [other] Implementation pending further discussion Change-Id: I678cd5ba39b56e124ab7854608289cd14651ce65 + --- arch/arm/cpu/armv8/exception_level.c | 3 +++ 1 file changed, 3 insertions(+) @@ -58,6 +59,3 @@ index 4aad1550f4..0a3e5428e7 100644 /* Move into EL1 and keep running there */ armv8_switch_to_el1((uintptr_t)&non_secure_jmp, 0, 0, 0, (uintptr_t)entry_non_secure, ES_TO_AARCH64); --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index 6c0d49046a..d1dcd74557 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -1,13 +1,6 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" # -# Corstone-500 MACHINE -# -SRC_URI:append:corstone500 = " \ - file://0001-armv7-adding-generic-timer-access-through-MMIO.patch \ - file://0002-board-arm-add-corstone500-board.patch" - -# # Corstone1000 64-bit machines # DEPENDS:append:corstone1000 = " gnutls-native" @@ -50,7 +43,8 @@ SRC_URI:append:corstone1000 = " \ file://0030-corstone1000-boot-index-from-active.patch \ file://0031-corstone1000-enable-PSCI-reset.patch \ file://0032-Enable-EFI-set-get-time-services.patch \ - file://0033-Increase-the-unzipped-Kernel-size.patch \ + file://0033-corstone1000-detect-inflated-kernel-size.patch \ + file://0034-corstone1000-ESRT-add-unique-firmware-GUID.patch \ " # diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb deleted file mode 100644 index 905ae552a7..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb +++ /dev/null @@ -1,26 +0,0 @@ -HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome" -DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \ -ARM, MIPS and several other processors, which can be installed in a boot \ -ROM and used to initialize and test the hardware or to download and run \ -application code." -SECTION = "bootloaders" -DEPENDS += "flex-native bison-native" - -LICENSE = "GPL-2.0-or-later" -LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1" -PE = "1" - -# We use the revision in order to avoid having to fetch it from the -# repo during parse -SRCREV = "4debc57a3da6c3f4d3f89a637e99206f4cea0a96" - -SRC_URI = "git://git.denx.de/u-boot.git;branch=master \ - " - -S = "${WORKDIR}/git" -B = "${WORKDIR}/build" -do_configure[cleandirs] = "${B}" - -require recipes-bsp/u-boot/u-boot.inc - -DEPENDS += "bc-native dtc-native gnutls-native" |