diff options
Diffstat (limited to 'meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os')
4 files changed, 341 insertions, 0 deletions
diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0001-core-arm-add-MPIDR-affinity-shift-and-mask-for-32-bi.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0001-core-arm-add-MPIDR-affinity-shift-and-mask-for-32-bi.patch new file mode 100644 index 0000000000..f249e526a8 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0001-core-arm-add-MPIDR-affinity-shift-and-mask-for-32-bi.patch @@ -0,0 +1,29 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +From cf84c933bb7b8a95742d1e723950cb2cde2d5320 Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath <vishnu.banavath@arm.com> +Date: Wed, 20 Jul 2022 16:37:10 +0100 +Subject: [PATCH] core: arm: add MPIDR affinity shift and mask for 32-bit + +This change is to add MPIDR affinity shift and mask for +32-bit + +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +diff --git a/core/arch/arm/include/arm.h b/core/arch/arm/include/arm.h +index f59478af..2f6f82e7 100644 +--- a/core/arch/arm/include/arm.h ++++ b/core/arch/arm/include/arm.h +@@ -63,6 +63,8 @@ + #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) + #define MPIDR_AFF2_SHIFT U(16) + #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) ++#define MPIDR_AFF3_SHIFT U(32) ++#define MPIDR_AFF3_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) + + #define MPIDR_MT_SHIFT U(24) + #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) +-- +2.17.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0002-plat-n1sdp-add-N1SDP-platform-support.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0002-plat-n1sdp-add-N1SDP-platform-support.patch new file mode 100644 index 0000000000..db195ab337 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0002-plat-n1sdp-add-N1SDP-platform-support.patch @@ -0,0 +1,233 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +From 22ba7c7789082dbc179921962cdcadece4499c89 Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath <vishnu.banavath@arm.com> +Date: Thu, 30 Jun 2022 18:36:26 +0100 +Subject: [PATCH] plat-n1sdp: add N1SDP platform support + +These changes are to add N1SDP platform to optee-os + +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +diff --git a/core/arch/arm/plat-n1sdp/conf.mk b/core/arch/arm/plat-n1sdp/conf.mk +new file mode 100644 +index 00000000..06b4975a +--- /dev/null ++++ b/core/arch/arm/plat-n1sdp/conf.mk +@@ -0,0 +1,41 @@ ++include core/arch/arm/cpu/cortex-armv8-0.mk ++ ++CFG_DEBUG_INFO = y ++CFG_TEE_CORE_LOG_LEVEL = 4 ++ ++# Workaround 808870: Unconditional VLDM instructions might cause an ++# alignment fault even though the address is aligned ++# Either hard float must be disabled for AArch32 or strict alignment checks ++# must be disabled ++ifeq ($(CFG_SCTLR_ALIGNMENT_CHECK),y) ++$(call force,CFG_TA_ARM32_NO_HARD_FLOAT_SUPPORT,y) ++else ++$(call force,CFG_SCTLR_ALIGNMENT_CHECK,n) ++endif ++ ++CFG_ARM64_core ?= y ++ ++CFG_ARM_GICV3 = y ++ ++# ARM debugger needs this ++platform-cflags-debug-info = -gdwarf-4 ++platform-aflags-debug-info = -gdwarf-4 ++ ++CFG_CORE_SEL1_SPMC = y ++CFG_WITH_ARM_TRUSTED_FW = y ++ ++$(call force,CFG_GIC,y) ++$(call force,CFG_PL011,y) ++$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) ++ ++CFG_CORE_HEAP_SIZE = 0x32000 # 200kb ++ ++CFG_TEE_CORE_NB_CORE = 4 ++CFG_TZDRAM_START ?= 0x08000000 ++CFG_TZDRAM_SIZE ?= 0x02008000 ++ ++CFG_SHMEM_START ?= 0x83000000 ++CFG_SHMEM_SIZE ?= 0x00210000 ++# DRAM1 is defined above 4G ++$(call force,CFG_CORE_LARGE_PHYS_ADDR,y) ++$(call force,CFG_CORE_ARM64_PA_BITS,36) +diff --git a/core/arch/arm/plat-n1sdp/main.c b/core/arch/arm/plat-n1sdp/main.c +new file mode 100644 +index 00000000..cfb7f19b +--- /dev/null ++++ b/core/arch/arm/plat-n1sdp/main.c +@@ -0,0 +1,63 @@ ++// SPDX-License-Identifier: BSD-2-Clause ++/* ++ * Copyright (c) 2022, Arm Limited. ++ */ ++ ++#include <arm.h> ++#include <console.h> ++#include <drivers/gic.h> ++#include <drivers/pl011.h> ++#include <drivers/tpm2_mmio.h> ++#include <drivers/tpm2_ptp_fifo.h> ++#include <drivers/tzc400.h> ++#include <initcall.h> ++#include <keep.h> ++#include <kernel/boot.h> ++#include <kernel/interrupt.h> ++#include <kernel/misc.h> ++#include <kernel/notif.h> ++#include <kernel/panic.h> ++#include <kernel/spinlock.h> ++#include <kernel/tee_time.h> ++#include <mm/core_memprot.h> ++#include <mm/core_mmu.h> ++#include <platform_config.h> ++#include <sm/psci.h> ++#include <stdint.h> ++#include <string.h> ++#include <trace.h> ++ ++static struct gic_data gic_data __nex_bss; ++static struct pl011_data console_data __nex_bss; ++ ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); ++ ++register_ddr(DRAM0_BASE, DRAM0_SIZE); ++ ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); ++register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE); ++ ++void main_init_gic(void) ++{ ++ gic_init_base_addr(&gic_data, GICC_BASE, ++ GICD_BASE); ++ itr_init(&gic_data.chip); ++} ++ ++void main_secondary_init_gic(void) ++{ ++ gic_cpu_init(&gic_data); ++} ++ ++void itr_core_handler(void) ++{ ++ gic_it_handle(&gic_data); ++} ++ ++void console_init(void) ++{ ++ pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, ++ CONSOLE_BAUDRATE); ++ register_serial_console(&console_data.chip); ++} +diff --git a/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S +new file mode 100644 +index 00000000..439d4e67 +--- /dev/null ++++ b/core/arch/arm/plat-n1sdp/n1sdp_core_pos.S +@@ -0,0 +1,32 @@ ++/* SPDX-License-Identifier: BSD-2-Clause */ ++/* ++ * Copyright (c) 2022, Arm Limited ++ */ ++ ++#include <asm.S> ++#include <arm.h> ++#include "platform_config.h" ++ ++FUNC get_core_pos_mpidr , : ++ mov x4, x0 ++ ++ /* ++ * The MT bit in MPIDR is always set for n1sdp and the ++ * affinity level 0 corresponds to thread affinity level. ++ */ ++ ++ /* Extract individual affinity fields from MPIDR */ ++ ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS ++ ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS ++ ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS ++ ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS ++ ++ /* Compute linear position */ ++ mov x4, #N1SDP_MAX_CLUSTERS_PER_CHIP ++ madd x2, x3, x4, x2 ++ mov x4, #N1SDP_MAX_CPUS_PER_CLUSTER ++ madd x1, x2, x4, x1 ++ mov x4, #N1SDP_MAX_PE_PER_CPU ++ madd x0, x1, x4, x0 ++ ret ++END_FUNC get_core_pos_mpidr +diff --git a/core/arch/arm/plat-n1sdp/platform_config.h b/core/arch/arm/plat-n1sdp/platform_config.h +new file mode 100644 +index 00000000..81b99409 +--- /dev/null ++++ b/core/arch/arm/plat-n1sdp/platform_config.h +@@ -0,0 +1,49 @@ ++/* SPDX-License-Identifier: BSD-2-Clause */ ++/* ++ * Copyright (c) 2022, Arm Limited ++ */ ++ ++#ifndef PLATFORM_CONFIG_H ++#define PLATFORM_CONFIG_H ++ ++#include <mm/generic_ram_layout.h> ++#include <stdint.h> ++ ++/* Make stacks aligned to data cache line length */ ++#define STACK_ALIGNMENT 64 ++ ++ /* N1SDP topology related constants */ ++#define N1SDP_MAX_CPUS_PER_CLUSTER U(2) ++#define PLAT_ARM_CLUSTER_COUNT U(2) ++#define PLAT_N1SDP_CHIP_COUNT U(2) ++#define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) ++#define N1SDP_MAX_PE_PER_CPU U(1) ++ ++#define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ ++ PLAT_ARM_CLUSTER_COUNT * \ ++ N1SDP_MAX_CPUS_PER_CLUSTER * \ ++ N1SDP_MAX_PE_PER_CPU) ++ ++#define GIC_BASE 0x2c010000 ++ ++#define UART1_BASE 0x1C0A0000 ++#define UART1_CLK_IN_HZ 24000000 /*24MHz*/ ++ ++#define CONSOLE_UART_BASE UART1_BASE ++#define CONSOLE_UART_CLK_IN_HZ UART1_CLK_IN_HZ ++ ++#define DRAM0_BASE 0x80000000 ++#define DRAM0_SIZE 0x80000000 ++ ++#define GICD_BASE 0x30000000 ++#define GICC_BASE 0x2C000000 ++#define GICR_BASE 0x300C0000 ++ ++#ifndef UART_BAUDRATE ++#define UART_BAUDRATE 115200 ++#endif ++#ifndef CONSOLE_BAUDRATE ++#define CONSOLE_BAUDRATE UART_BAUDRATE ++#endif ++ ++#endif /*PLATFORM_CONFIG_H*/ +diff --git a/core/arch/arm/plat-n1sdp/sub.mk b/core/arch/arm/plat-n1sdp/sub.mk +new file mode 100644 +index 00000000..a0b49da1 +--- /dev/null ++++ b/core/arch/arm/plat-n1sdp/sub.mk +@@ -0,0 +1,3 @@ ++global-incdirs-y += . ++srcs-y += main.c ++srcs-y += n1sdp_core_pos.S +-- +2.17.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0003-HACK-disable-instruction-cache-and-data-cache.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0003-HACK-disable-instruction-cache-and-data-cache.patch new file mode 100644 index 0000000000..e8f4cc44dc --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0003-HACK-disable-instruction-cache-and-data-cache.patch @@ -0,0 +1,46 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +From 0c3ce4c09cd7d2ff4cd2e62acab899dd88dc9514 Mon Sep 17 00:00:00 2001 +From: Vishnu Banavath <vishnu.banavath@arm.com> +Date: Wed, 20 Jul 2022 16:45:59 +0100 +Subject: [PATCH] HACK: disable instruction cache and data cache. + +For some reason, n1sdp fails to boot with instruction cache and +data cache enabled. This is a temporary change to disable I cache +and D cache until a proper fix is found. + +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +%% original patch: 0003-HACK-disable-instruction-cache-and-data-cache.patch + +diff --git a/core/arch/arm/kernel/entry_a64.S b/core/arch/arm/kernel/entry_a64.S +index 875b6e69..594d6928 100644 +--- a/core/arch/arm/kernel/entry_a64.S ++++ b/core/arch/arm/kernel/entry_a64.S +@@ -52,7 +52,7 @@ + + .macro set_sctlr_el1 + mrs x0, sctlr_el1 +- orr x0, x0, #SCTLR_I ++ bic x0, x0, #SCTLR_I + orr x0, x0, #SCTLR_SA + orr x0, x0, #SCTLR_SPAN + #if defined(CFG_CORE_RWDATA_NOEXEC) +@@ -490,11 +490,11 @@ LOCAL_FUNC enable_mmu , : , .identity_map + isb + + /* Enable I and D cache */ +- mrs x1, sctlr_el1 ++ /* mrs x1, sctlr_el1 + orr x1, x1, #SCTLR_I + orr x1, x1, #SCTLR_C + msr sctlr_el1, x1 +- isb ++ isb */ + + /* Adjust stack pointers and return address */ + msr spsel, #1 +-- +2.17.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0004-Handle-logging-syscall.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0004-Handle-logging-syscall.patch new file mode 100644 index 0000000000..356be9e04f --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/n1sdp/0004-Handle-logging-syscall.patch @@ -0,0 +1,33 @@ +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com> + +From b3fde6c2e1a950214f760ab9f194f3a6572292a8 Mon Sep 17 00:00:00 2001 +From: Balint Dobszay <balint.dobszay@arm.com> +Date: Fri, 15 Jul 2022 13:45:54 +0200 +Subject: [PATCH] Handle logging syscall + +Signed-off-by: Balint Dobszay <balint.dobszay@arm.com> +Change-Id: Ib8151cc9c66aea8bcc8fe8b1ecdc3f9f9c5f14e4 + +%% original patch: 0004-Handle-logging-syscall.patch + +diff --git a/core/arch/arm/kernel/spmc_sp_handler.c b/core/arch/arm/kernel/spmc_sp_handler.c +index e0fa0aa6..c7a45387 100644 +--- a/core/arch/arm/kernel/spmc_sp_handler.c ++++ b/core/arch/arm/kernel/spmc_sp_handler.c +@@ -1004,6 +1004,12 @@ void spmc_sp_msg_handler(struct thread_smc_args *args, + ffa_mem_reclaim(args, caller_sp); + sp_enter(args, caller_sp); + break; ++ case 0xdeadbeef: ++ ts_push_current_session(&caller_sp->ts_sess); ++ IMSG("%s", (char *)args->a1); ++ ts_pop_current_session(); ++ sp_enter(args, caller_sp); ++ break; + default: + EMSG("Unhandled FFA function ID %#"PRIx32, + (uint32_t)args->a0); +-- +2.17.1 + |