From d08a2a08a454b0861f973df7e42b32d78c6ec166 Mon Sep 17 00:00:00 2001 From: eportnov Date: Fri, 8 Jul 2022 10:57:50 +0300 Subject: Add new field to bmcweb --- .../0003-Add-new-fields-to-cpu.patch | 70 +++++++++++ .../dbus/phosphor-dbus-interfaces_%.bbappend | 1 + .../bmcweb/0003-add-new-cpu-fields.patch | 133 +++++++++++++++++++++ .../recipes-phosphor/interfaces/bmcweb_%.bbappend | 1 + .../phosphor-inventory-manager-cpu/cpu0.yaml | 12 ++ .../phosphor-inventory-manager-cpu/cpu1.yaml | 12 ++ .../recipes-phosphor/interfaces/bmcweb_git.bb | 4 - 7 files changed, 229 insertions(+), 4 deletions(-) create mode 100644 meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0003-Add-new-fields-to-cpu.patch create mode 100644 meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb/0003-add-new-cpu-fields.patch diff --git a/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0003-Add-new-fields-to-cpu.patch b/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0003-Add-new-fields-to-cpu.patch new file mode 100644 index 0000000000..f10da21652 --- /dev/null +++ b/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces/0003-Add-new-fields-to-cpu.patch @@ -0,0 +1,70 @@ +From 4b2a14e510495ef42d638584a62ab3c9ccf24056 Mon Sep 17 00:00:00 2001 +From: eportnov +Date: Thu, 7 Jul 2022 17:52:12 +0300 +Subject: [PATCH] Add new fields to cpu + +--- + .../Inventory/Item/Cpu.interface.yaml | 36 ++++++++++++++++++- + 1 file changed, 35 insertions(+), 1 deletion(-) + +diff --git a/yaml/xyz/openbmc_project/Inventory/Item/Cpu.interface.yaml b/yaml/xyz/openbmc_project/Inventory/Item/Cpu.interface.yaml +index 211673d..174a80e 100644 +--- a/yaml/xyz/openbmc_project/Inventory/Item/Cpu.interface.yaml ++++ b/yaml/xyz/openbmc_project/Inventory/Item/Cpu.interface.yaml +@@ -37,6 +37,10 @@ properties: + type: uint32 + description: > + Max Speed in megahertz the CPU can support. ++ - name: MinSpeedMHz ++ type: uint32 ++ description: > ++ Min Speed in megahertz the CPU can support. + - name: Characteristics + type: array[enum[self.Capability]] + description: > +@@ -72,6 +76,12 @@ properties: + The set of boolean flags for processor's capability, such as + 64-bit Capable, Multi-Core, Hardware Thread, Execute Protection, + Enhanced Virtualization, Power/Performance Control etc. ++ - name: ProcessorArchitecture ++ type: enum[self.ProcessorArchitecture] ++ description: > ++ The set of boolean flags for processor's capability, such as ++ 64-bit Capable, Multi-Core, Hardware Thread, Execute Protection, ++ Enhanced Virtualization, Power/Performance Control etc. + + enumerations: + - name: Capability +@@ -130,7 +140,31 @@ enumerations: + - name: x86_64 + description: > + Support power/performance control. +- ++ ++ - name: ProcessorArchitecture ++ description: > ++ Contain the string that identifies the architecture ++ of the processor contained in this socket ++ values: ++ - name: ARM ++ description: > ++ ARM. ++ - name: IA_64 ++ description: > ++ Intel Itanium. ++ - name: MIPS ++ description: > ++ MIPS. ++ - name: OEM ++ description: > ++ OEM-defined. ++ - name: Power ++ description: > ++ Power. ++ - name: x86 ++ description: > ++ x86 or x86-64. ++ + associations: + - name: associated_pcie_slots + description: > diff --git a/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend b/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend index 614db6e4d2..34fb790278 100644 --- a/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend +++ b/meta-ibs/meta-common/recipes-phosphor/dbus/phosphor-dbus-interfaces_%.bbappend @@ -21,4 +21,5 @@ SRC_URI += "file://0007-ipmi-set-BIOS-id.patch \ file://0034-Add-username-property-to-SessionInfo-interface.patch \ file://0035-Remove-read-only-flag-from-NTPServers.patch \ file://0036-add-fields.patch \ + file://0003-Add-new-fields-to-cpu.patch \ " diff --git a/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb/0003-add-new-cpu-fields.patch b/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb/0003-add-new-cpu-fields.patch new file mode 100644 index 0000000000..1e4f2efd7a --- /dev/null +++ b/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb/0003-add-new-cpu-fields.patch @@ -0,0 +1,133 @@ +From 644dc71f3ff13fbc620d6ea8bff89736dc7cc691 Mon Sep 17 00:00:00 2001 +From: eportnov +Date: Fri, 8 Jul 2022 10:31:14 +0300 +Subject: [PATCH] add new cpu fields + +--- + redfish-core/lib/processor.hpp | 106 +++++++++++++++++++++++++++++++++ + 1 file changed, 106 insertions(+) + +diff --git a/redfish-core/lib/processor.hpp b/redfish-core/lib/processor.hpp +index 2a0e028..a83211a 100644 +--- a/redfish-core/lib/processor.hpp ++++ b/redfish-core/lib/processor.hpp +@@ -66,6 +66,77 @@ inline void getProcessorUUID(std::shared_ptr aResp, + }); + } + ++inline std::string translateInstructionSetTypeToRedfish(const std::string& instructionSetType) ++{ ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.ARM_A32") ++ { ++ return "ARM-A32"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.ARM_A64") ++ { ++ return "ARM-A64"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.IA_64") ++ { ++ return "IA-64"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.MIPS32") ++ { ++ return "MIPS32"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.MIPS64") ++ { ++ return "MIPS64"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.OEM") ++ { ++ return "OEM"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.PowerISA") ++ { ++ return "PowerISA"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.x86") ++ { ++ return "x86"; ++ } ++ if (instructionSetType == "xyz.openbmc_project.Inventory.Item.Cpu.Instruction.x86_64") ++ { ++ return "x86-64"; ++ } ++ return ""; ++} ++ ++inline std::string translateProcessorArchTypeToRedfish(const std::string& processorArchType) ++{ ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.ARM") ++ { ++ return "ARM"; ++ } ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.IA_64") ++ { ++ return "IA-64"; ++ } ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.MIPS") ++ { ++ return "MIPS"; ++ } ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.OEM") ++ { ++ return "OEM"; ++ } ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.Power") ++ { ++ return "Power"; ++ } ++ if (processorArchType == "xyz.openbmc_project.Inventory.Item.Cpu.ProcessorArchitecture.x86") ++ { ++ return "x86"; ++ } ++ return ""; ++} ++ ++ + inline void getCpuDataByInterface( + const std::shared_ptr& aResp, + const dbus::utility::DBusInteracesMap& cpuInterfacesProperties) +@@ -144,6 +215,41 @@ inline void getCpuDataByInterface( + aResp->res.jsonValue["TotalThreads"] = *value; + } + } ++ else if (property.first == "InstructionSet") ++ { ++ const std::string* value = ++ std::get_if(&property.second); ++ if (value != nullptr) ++ { ++ aResp->res.jsonValue["InstructionSet"] = translateInstructionSetTypeToRedfish(*value); ++ } ++ } ++ else if (property.first == "Version") ++ { ++ const std::string* value = ++ std::get_if(&property.second); ++ if (value != nullptr) ++ { ++ aResp->res.jsonValue["Version"] = *value; ++ } ++ } ++ else if (property.first == "ProcessorArchitecture") ++ { ++ const std::string* value = ++ std::get_if(&property.second); ++ if (value != nullptr) ++ { ++ aResp->res.jsonValue["ProcessorArchitecture"] = translateProcessorArchTypeToRedfish(*value); ++ } ++ } ++ else if (property.first == "MinSpeedMHz") ++ { ++ const uint32_t* value = std::get_if(&property.second); ++ if (value != nullptr) ++ { ++ aResp->res.jsonValue["MinSpeedMHz"] = *value; ++ } ++ } + else if (property.first == "EffectiveFamily") + { + const uint16_t* value = std::get_if(&property.second); diff --git a/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend b/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend index e349ee7674..9ce95cfe84 100644 --- a/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend +++ b/meta-ibs/meta-common/recipes-phosphor/interfaces/bmcweb_%.bbappend @@ -5,6 +5,7 @@ SRCREV = "550a6bf85f81c1725b6c320a5ee419335cff2cf6" SRC_URI += "\ file://0001-Enable-vm-nbdproxy-option.patch \ file://0002-Add-http-ftp-nfs-protocols-to-un-filter-them-FT-58-T.patch \ + file://0003-add-new-cpu-fields.patch \ " EXTRA_OEMESON += "\ diff --git a/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu0.yaml b/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu0.yaml index d2863b548d..9c70596b00 100644 --- a/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu0.yaml +++ b/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu0.yaml @@ -14,6 +14,9 @@ events: Family: value: "XeonCPU-3" type: string + Version: + value: "1.22" + type: string - name: createObjects objs: @@ -143,6 +146,15 @@ events: type: uint32 value: 111 + - name: setProperty + interface: xyz.openbmc_project.Inventory.Item.Cpu + property: MinSpeedMHz + paths: + - /system/chassis/motherboard/cpu0 + value: + type: uint32 + value: 2000 + diff --git a/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu1.yaml b/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu1.yaml index 35a8d5abb5..4c85a72551 100644 --- a/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu1.yaml +++ b/meta-ibs/meta-cp2-5422/recipes-phosphor/inventory/phosphor-inventory-manager-cpu/cpu1.yaml @@ -14,6 +14,9 @@ events: Family: value: "XeonCPU-3" type: string + Version: + value: "1.22" + type: string - name: createObjects objs: @@ -143,6 +146,15 @@ events: type: uint32 value: 111 + - name: setProperty + interface: xyz.openbmc_project.Inventory.Item.Cpu + property: MinSpeedMHz + paths: + - /system/chassis/motherboard/cpu1 + value: + type: uint32 + value: 2000 + diff --git a/meta-phosphor/recipes-phosphor/interfaces/bmcweb_git.bb b/meta-phosphor/recipes-phosphor/interfaces/bmcweb_git.bb index 9034936e29..d86041f1b0 100644 --- a/meta-phosphor/recipes-phosphor/interfaces/bmcweb_git.bb +++ b/meta-phosphor/recipes-phosphor/interfaces/bmcweb_git.bb @@ -19,10 +19,6 @@ S = "${WORKDIR}/git" inherit pkgconfig meson ptest -SRC_URI += " \ - file://run-ptest \ -" - DEPENDS = " \ openssl \ zlib \ -- cgit v1.2.3