From 8dd68484e26c2924fcc0eeda4d024b0116115009 Mon Sep 17 00:00:00 2001 From: Patrick Williams Date: Tue, 4 Oct 2022 07:57:18 -0500 Subject: subtree updates meta-openembedded: 0782ea454a..ce0b93fc12: Alex Kiernan (5): faad2: Upgrade 2.8.8 -> 2.10.0 onig: Upgrade 6.9.4 -> 6.9.8 jansson: Honour multilib paths jansson: Backport linker flag fixes jansson: Default to shared builds Beniamin Sandu (1): libnet: update to v1.2 release Daniel Gomez (4): gst-instruments: Update 0.2.3 -> 0.3.1+cb8977a libftdi: Add ftdi-eeprom support xf86-video-ati: Update 19.1.0 -> 19.1.0+7a6a34af v4l-utils: Update 1.22.1 -> 1.23.0+fd544473 Gianluigi Spagnuolo (1): bpftool: add aarch64 to COMPATIBLE_HOST Hitomi Hasegawa (1): libsdl: add CVE-2019-14906 to allowlist Khem Raj (2): python3-gevent: Avoid building internal version of libev xterm: Add _GNU_SOURCE via CFLAGS Lukas Rusak (2): libwebsockets: add optional support for sd-event loop libwebsockets: add error check if PACKAGECONFIG contains systemd but DISTRO_FEATURES doesn't Ming Liu (1): plymouth: uprev to 22.02.122 William A. Kennington III (2): gerbera: upgrade 1.9.2 -> 1.11.0 fmt: upgrade 8.1.1 -> 9.1.0 Yi Zhao (4): freeradius: fix daemon startup warnings frr: upgrade 8.2.2 -> 8.3.1 libnftnl: upgrade 1.2.2 -> 1.2.3 nftables: upgrade 1.0.4 -> 1.0.5 onkelpit (1): tio: added tio version 2.0 and 1.47 wangmy (1): xterm: upgrade 372 -> 373 meta-arm: 52f07a4b0b..0164b4ca7a: Abdellatif El Khlifi (12): arm-bsp/u-boot: corstone1000: update initramfs bundle size arm-bsp/u-boot: corstone1000: upgrade FF-A support arm-bsp/optee-os: corstone1000: upgrade to v3.18 arm-bsp/optee-spdevkit: corstone1000: drop the support arm-bsp/corstone1000-initramfs-image: remove obsolete packages arm-bsp/trusted-services: corstone1000: add secure partitions support arm-bsp/machine: corstone1000: disable pulling the kernel into the initramfs arm-bsp/trusted-services: corstone1000: add MHU-driver arm-bsp/corstone1000-initramfs-image: add TS PSA API tests packages arm-bsp/linux: corstone1000: use arm-ffa machine feature arm/secure-partitions: drop use of the recipe arm/ffa-debugfs: drop use of the kernel module Adam Johnston (3): arm-bsp/edk2-firmware: Update edk2/edk2-platforms versions for N1SDP arm-bsp/edk2-firmware: Add edk2-platforms patches for N1SDP arm-bsp/trusted-firmware-a: Update TF-A version for N1SDP Andrei Gherzan (1): edk2-firmware: Fix configure sed typo Anton Antonov (1): Temporary use qemu 7.0.0 for TS CI pipelines Davidson K (6): arm-bsp/tc: upgrade version of trusted-firmware-a arm-bsp/tc: upgrade version of hafnium arm-bsp/tc: upgrade version of optee arm-bsp/u-boot: add gnutls-native as dependency arm-bsp/trusted-firmware-a: add firmware update support for TC arm-bsp/hafnium: enable Virtual Host Extension for TC Denys Dmytriyenko (1): arm-toolchain/gcc,external-arm-toolchain: resolve conflict with gcc headers Emekcan (8): arm-bsp/u-boot: Add external system driver to u-boot device tree arm-bsp/kernel: Add external device driver arm-bsp/u-boot: Add external system MHUs to u-boot device tree arm-bsp/kernel: Add rpmsg_arm_mailbox to corstone1000 arm-bsp/test: Adding a test app for external system arm-bsp/images: Adding external system test to initramfs image arm-bsp/test: Changing the test app repository arm-bsp/external-system: Changing the RTX repo Jiacheng Tang (1): arm/fvp-base-r-aem: upgrade to version 11.19.14 Joe Slater (1): arm/packagegroup-ts-tests: fix parse error Jon Mason (17): arm-bsp/optee-os: add 3.10 recipe for corstone1000 arm-bsp/optee: rename corstone1000 files arm/optee-spdevkit: add version to file name arm/optee-os: add ARMv7 changes to clang patch and update patches arm/qemuarm-secureboot: remove optee-os version pin arm/optee: remove old versions arm/optee-client: move the 3.14 recipe to meta-arm-bsp arm/hafnium: update to 2.7 arm-bsp/n1sdp: update linux-yocto patches arm/edk2-firmware: Work around clang issue arm-bsp/tc: remove hafnium clang patch layers: convert to langdale compatibility CI: Remove uniquely zephyr machines arm-bsp/fvp: move the fvp include file to the include directory ci: move features only needed by testimage from base CI: apply a patch so that meta-zephyr is compatible with langdale Revert "CI: apply a patch so that meta-zephyr is compatible with langdale" Khem Raj (6): optee-os: Extend clang pragma fixes to core_mmu_v7.c for 3.18 trusted-services: Pin to use gcc ffa-debugfs-mod: Exclude from world builds linux-yocto: Add bbappend for 5.19 hafnium: Add a fix for clang-15 errors hafnium: Exclude from world builds Mohamed Omar Asaker (1): arm-bsp/n1sdp-board-firmware: upgrade to N1SDP-2022.06.22 Peter Hoyes (4): arm/lib: Specify the FVP environment variables explicitly arm-bsp/trusted-firmware-m: Make branch names configurable arm/classes: Migrate TF-M image signing to bbclass arm-bsp/corstone1000: Refactor image signing to use new bbclass Ross Burton (3): gem5/linux-yocto: upgrade to 5.4.205 and fix buildpaths in binaries Revert "Temporary use qemu 7.0.0 for TS CI pipelines" runfvp: pass-through environment variables need for GUI applications Rui Miguel Silva (1): arm-bsp: trusted-services: fix openamp build Vishnu Banavath (2): arm-bsp/ffa-debugfs: update git SHA for v2.1.0 arm-bsp/external-system:corstone1000: build and install external-system Xueliang Zhong (1): arm-bsp/n1sdp: upgrade scp-firmware version Signed-off-by: Patrick Williams Change-Id: I7a07eab9e4aa0bdbdb50602050c3c4caf062acbf --- ...M-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch | 475 +++++++++++++++++++++ ...Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch | 48 +++ ...M-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch | 67 +++ .../files/edk2-platforms/add-nt-fw-config.patch | 474 -------------------- 4 files changed, 590 insertions(+), 474 deletions(-) create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/add-nt-fw-config.patch (limited to 'meta-arm/meta-arm-bsp/recipes-bsp/uefi/files') diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch new file mode 100644 index 0000000000..e5526dd66e --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch @@ -0,0 +1,475 @@ +From fa3fd24ffbc987e952a2e5610a7b02556afd2087 Mon Sep 17 00:00:00 2001 +From: sahil +Date: Thu, 17 Mar 2022 16:28:05 +0530 +Subject: [PATCH 1/3] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG + +NT_FW_CONFIG DTB contains platform information passed by +Tf-A boot stage. +This information is used for Virtual memory map generation +during PEI phase and passed on to DXE phase as a HOB, where +it is used in ConfigurationManagerDxe. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: Ib82571280bf1ca5febe5766e618de09e7b70bb02 + +--- + .../ConfigurationManager.c | 24 ++-- + .../ConfigurationManagerDxe.inf | 3 +- + .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +-- + .../Library/PlatformLib/AArch64/Helper.S | 4 +- + .../Library/PlatformLib/PlatformLib.c | 12 +- + .../Library/PlatformLib/PlatformLib.inf | 8 +- + .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++- + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +- + 8 files changed, 152 insertions(+), 25 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index f50623ae..e023d47c 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -1,7 +1,7 @@ + /** @file + Configuration Manager Dxe + +- Copyright (c) 2021, ARM Limited. All rights reserved.
++ Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ + #include "Platform.h" + + extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat; ++static NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + + /** The platform configuration repository information. + */ +@@ -1242,13 +1244,11 @@ InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo + ) + { +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 Dram2Size; + UINT64 RemoteDdrSize; + + RemoteDdrSize = 0; + +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB); + + PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; +@@ -1512,7 +1512,6 @@ GetGicCInfo ( + ) + { + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + +@@ -1523,7 +1522,6 @@ GetGicCInfo ( + } + + PlatformRepo = This->PlatRepoInfo; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + + if (PlatInfo->MultichipMode == 1) { + TotalObjCount = PLAT_CPU_COUNT * 2; +@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject ( + { + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 AcpiTableCount; + + if ((This == NULL) || (CmObject == NULL)) { +@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject ( + + Status = EFI_NOT_FOUND; + PlatformRepo = This->PlatRepoInfo; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; ++ + AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList); + if (PlatInfo->MultichipMode == 0) + AcpiTableCount -= 1; +@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject ( + { + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; +@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject ( + Status = EFI_NOT_FOUND; + PlatformRepo = This->PlatRepoInfo; + +- // Probe for multi chip information +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->MultichipMode == 1) { + GicRedistCount = 2; + GicCpuCount = PLAT_CPU_COUNT * 2; +@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize ( + IN EFI_SYSTEM_TABLE * SystemTable + ) + { ++ VOID *PlatInfoHob; + EFI_STATUS Status; + ++ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid); ++ ++ if (PlatInfoHob == NULL) { ++ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); ++ return EFI_NOT_FOUND; ++ } ++ ++ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob); ++ + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status = InitializePlatformRepository ( +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +index 4f8e7f13..fb59c295 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +@@ -1,7 +1,7 @@ + ## @file + # Configuration Manager Dxe + # +-# Copyright (c) 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -42,6 +42,7 @@ + + [LibraryClasses] + ArmPlatformLib ++ HobLib + PrintLib + UefiBootServicesTableLib + UefiDriverEntryPoint +diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +index 097160c7..63cebaf0 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h ++++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +@@ -1,6 +1,6 @@ + /** @file + * +-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. ++* Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +@@ -41,11 +41,6 @@ + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + +-// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is +-// pre-populated by a earlier boot stage +-#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ +- 0x00008000) +- + /* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure +@@ -55,12 +50,17 @@ + typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 MultichipMode; +- /*! Slave count in C2C mode */ +- UINT8 SlaveCount; ++ /*! Secondary chip count in C2C mode */ ++ UINT8 SecondaryChipCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; + } NEOVERSEN1SOC_PLAT_INFO; + ++// NT_FW_CONFIG DT structure ++typedef struct { ++ UINT64 NtFwConfigDtAddr; ++} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI; ++ + #endif +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S +index 8d2069de..88ed640d 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S +@@ -1,6 +1,6 @@ + /** @file + * +-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. ++* Copyright (c) 2019 - 2022, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + // the UEFI firmware through the CPU registers. + // + ASM_PFX(ArmPlatformPeiBootAction): ++ adr x10, NtFwConfigDtBlob ++ str x0, [x10] + ret + + // +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +index c0effd37..fabe902c 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +@@ -1,6 +1,6 @@ + /** @file + +- Copyright (c) 2018-2021, ARM Limited. All rights reserved.
++ Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -8,8 +8,12 @@ + + #include + #include ++#include + #include + ++UINT64 NtFwConfigDtBlob; ++STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi; ++ + STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 +@@ -46,6 +50,7 @@ ArmPlatformInitialize ( + IN UINTN MpId + ) + { ++ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob; + return RETURN_SUCCESS; + } + +@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi ++ }, ++ { ++ EFI_PEI_PPI_DESCRIPTOR_PPI, ++ &gNtFwConfigDtInfoPpiGuid, ++ &mNtFwConfigDtInfoPpi + } + }; + +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +index 96e590cd..6f9c9d5a 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +@@ -1,7 +1,7 @@ + ## @file + # Platform Library for N1Sdp. + # +-# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -18,10 +18,14 @@ + [Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec ++ EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + ++[LibraryClasses] ++ FdtLib ++ + [Sources.common] + PlatformLibMem.c + PlatformLib.c +@@ -59,7 +63,9 @@ + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + [Guids] ++ gArmNeoverseN1SocPlatformInfoDescriptorGuid + gEfiHobListGuid ## CONSUMES ## SystemTable + + [Ppis] + gArmMpCoreInfoPpiGuid ++ gNtFwConfigDtInfoPpiGuid +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +index 339fa07b..b58bda4b 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +@@ -1,6 +1,6 @@ + /** @file + +- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++ Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -10,11 +10,95 @@ + #include + #include + #include ++#include ++#include + #include + + // The total number of descriptors, including the final "end-of-table" descriptor. + #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 + ++/** A helper function to locate the NtFwConfig PPI and get the base address of ++ NT_FW_CONFIG DT from which values are obtained using FDT helper functions. ++ ++ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB ++ ++ @retval EFI_SUCCESS Success. ++ returns EFI_INVALID_PARAMETER A parameter is invalid. ++**/ ++EFI_STATUS ++GetNeoverseN1SocPlatInfo ( ++ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info ++ ) ++{ ++ CONST UINT32 *Property; ++ INT32 Offset; ++ CONST VOID *NtFwCfgDtBlob; ++ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi; ++ EFI_STATUS Status; ++ ++ Status = PeiServicesLocatePpi ( ++ &gNtFwConfigDtInfoPpiGuid, ++ 0, ++ NULL, ++ (VOID **)&NtFwConfigInfoPpi ++ ); ++ ++ if (EFI_ERROR (Status)) { ++ DEBUG (( ++ DEBUG_ERROR, ++ "PeiServicesLocatePpi failed with error %r\n", ++ Status ++ )); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr; ++ if (fdt_check_header (NtFwCfgDtBlob) != 0) { ++ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob)); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info"); ++ if (Offset == -FDT_ERR_NOTFOUND) { ++ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->LocalDdrSize = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->MultichipMode = fdt32_to_cpu (*Property); ++ ++ return EFI_SUCCESS; ++} ++ + /** + Returns the Virtual Memory Map of the platform. + +@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap ( + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + UINT64 RemoteDdrSize; ++ EFI_STATUS Status; + + Index = 0; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; ++ ++ // Create platform info HOB ++ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob ( ++ &gArmNeoverseN1SocPlatformInfoDescriptorGuid, ++ sizeof (NEOVERSEN1SOC_PLAT_INFO) ++ ); ++ ++ if (PlatInfo == NULL) { ++ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); ++ ASSERT (FALSE); ++ return; ++ } ++ ++ Status = GetNeoverseN1SocPlatInfo (PlatInfo); ++ ASSERT (Status == 0); + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * + (UINT64)SIZE_1GB); +diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +index d59f25a5..4dea8fe1 100644 +--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec ++++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +@@ -1,7 +1,7 @@ + ## @file + # Describes the entire platform configuration. + # +-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -22,6 +22,8 @@ + Include # Root include for the package + + [Guids.common] ++ # ARM NeoverseN1Soc Platform Info descriptor ++ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } } + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + + [PcdsFixedAtBuild] +@@ -83,3 +85,6 @@ + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050 + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051 ++ ++[Ppis] ++ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } } +-- +2.37.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch new file mode 100644 index 0000000000..1c097fcc7e --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch @@ -0,0 +1,48 @@ +From 73aab76042ae34fa4b07414c1830129e572dcd65 Mon Sep 17 00:00:00 2001 +From: sahil +Date: Wed, 20 Apr 2022 12:24:41 +0530 +Subject: [PATCH 2/3] Platform/ARM/N1Sdp: Fix RemoteDdrSize cast + +RemoteDdrSize calculation wraps around when booting N1Sdp in +multichip mode. Casting it to UINT64 to fix the issue. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: I2c2a70c2ab046337236fba92d25dec5905ccd117 + +--- + .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index e023d47c..36b5fc9e 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -1254,7 +1254,7 @@ InitializePlatformRepository ( + PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; + + if (PlatInfo->MultichipMode == 1) { +- RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); ++ RemoteDdrSize = ((UINT64)(PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); + + // Update Remote DDR Region1 + PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1].ProximityDomain = 1; +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +index b58bda4b..fbc9b05e 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +@@ -157,7 +157,7 @@ ArmPlatformGetVirtualMemoryMap ( + DramBlock2Size); + + if (PlatInfo->MultichipMode == 1) { +- RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); ++ RemoteDdrSize = ((UINT64)(PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, +-- +2.37.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch new file mode 100644 index 0000000000..f0de02eb66 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch @@ -0,0 +1,67 @@ +From adc66d99663f71ec97313c40b0d00a908f292c30 Mon Sep 17 00:00:00 2001 +From: Himanshu Sharma +Date: Mon, 30 May 2022 10:53:30 +0000 +Subject: [PATCH 3/3] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and + routing it to IOFPGA UART1 + +In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the +IPI0 trigger method to "level", which prevented SGI0 to be enabled +again after a CPU offline/online cycle. + +This patch fixes the above issue by assigning a reserved IRQ ID +for the Debug UART, other than 0 and also routing it to use IOFPGA +UART1 by unsharing it from currently using serial terminal. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: Himanshu Sharma +Change-Id: I6640c3c8f77afd233304ce9cb06dcf80a8659c16 + +--- + .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- + Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index 36b5fc9e..e8873200 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress +- 0, // Interrupt -unused ++ 250, // Interrupt (reserved) + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +index 865dd04d..878c8f2f 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +@@ -4,7 +4,7 @@ + # This provides platform specific component descriptions and libraries that + # conform to EFI/Framework standards. + # +-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -136,9 +136,9 @@ + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) +- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase +- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate +- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 +-- +2.37.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/add-nt-fw-config.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/add-nt-fw-config.patch deleted file mode 100644 index f6f1895116..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/add-nt-fw-config.patch +++ /dev/null @@ -1,474 +0,0 @@ -From cc58709b32d74273736886ccfc08e4723a436ea4 Mon Sep 17 00:00:00 2001 -From: sahil -Date: Thu, 17 Mar 2022 16:28:05 +0530 -Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG - -NT_FW_CONFIG DTB contains platform information passed by -Tf-A boot stage. -This information is used for Virtual memory map generation -during PEI phase and passed on to DXE phase as a HOB, where -it is used in ConfigurationManagerDxe. - -Upstream-Status: Pending -Signed-off-by: Adam Johnston -Signed-off-by: sahil -Change-Id: Ib82571280bf1ca5febe5766e618de09e7b70bb02 - ---- - .../ConfigurationManager.c | 24 ++-- - .../ConfigurationManagerDxe.inf | 3 +- - .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +-- - .../Library/PlatformLib/AArch64/Helper.S | 4 +- - .../Library/PlatformLib/PlatformLib.c | 12 +- - .../Library/PlatformLib/PlatformLib.inf | 8 +- - .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++- - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +- - 8 files changed, 152 insertions(+), 25 deletions(-) - -diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -index f50623ae3f..e023d47cfd 100644 ---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -@@ -1,7 +1,7 @@ - /** @file - Configuration Manager Dxe - -- Copyright (c) 2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -28,6 +29,7 @@ - #include "Platform.h" - - extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat; -+static NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - - /** The platform configuration repository information. - */ -@@ -1242,13 +1244,11 @@ InitializePlatformRepository ( - IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo - ) - { -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT64 Dram2Size; - UINT64 RemoteDdrSize; - - RemoteDdrSize = 0; - -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB); - - PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; -@@ -1512,7 +1512,6 @@ GetGicCInfo ( - ) - { - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 TotalObjCount; - UINT32 ObjIndex; - -@@ -1523,7 +1522,6 @@ GetGicCInfo ( - } - - PlatformRepo = This->PlatRepoInfo; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - - if (PlatInfo->MultichipMode == 1) { - TotalObjCount = PLAT_CPU_COUNT * 2; -@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject ( - { - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 AcpiTableCount; - - if ((This == NULL) || (CmObject == NULL)) { -@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject ( - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; -+ - AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList); - if (PlatInfo->MultichipMode == 0) - AcpiTableCount -= 1; -@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject ( - { - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 GicRedistCount; - UINT32 GicCpuCount; - UINT32 ProcHierarchyInfoCount; -@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject ( - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - -- // Probe for multi chip information -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - if (PlatInfo->MultichipMode == 1) { - GicRedistCount = 2; - GicCpuCount = PLAT_CPU_COUNT * 2; -@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize ( - IN EFI_SYSTEM_TABLE * SystemTable - ) - { -+ VOID *PlatInfoHob; - EFI_STATUS Status; - -+ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid); -+ -+ if (PlatInfoHob == NULL) { -+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); -+ return EFI_NOT_FOUND; -+ } -+ -+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob); -+ - // Initialize the Platform Configuration Repository before installing the - // Configuration Manager Protocol - Status = InitializePlatformRepository ( -diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -index 4f8e7f1302..fb59c29501 100644 ---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -@@ -1,7 +1,7 @@ - ## @file - # Configuration Manager Dxe - # --# Copyright (c) 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2021 - 2022, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -42,6 +42,7 @@ - - [LibraryClasses] - ArmPlatformLib -+ HobLib - PrintLib - UefiBootServicesTableLib - UefiDriverEntryPoint -diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -index 097160c7e2..63cebaf0e0 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -@@ -1,6 +1,6 @@ - /** @file - * --* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -+* Copyright (c) 2018 - 2022, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * -@@ -41,11 +41,6 @@ - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 - --// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is --// pre-populated by a earlier boot stage --#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ -- 0x00008000) -- - /* - * Platform information structure stored in Non-secure SRAM. Platform - * information are passed from the trusted firmware with the below structure -@@ -55,12 +50,17 @@ - typedef struct { - /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ - UINT8 MultichipMode; -- /*! Slave count in C2C mode */ -- UINT8 SlaveCount; -+ /*! Secondary chip count in C2C mode */ -+ UINT8 SecondaryChipCount; - /*! Local DDR memory size in GigaBytes */ - UINT8 LocalDdrSize; - /*! Remote DDR memory size in GigaBytes */ - UINT8 RemoteDdrSize; - } NEOVERSEN1SOC_PLAT_INFO; - -+// NT_FW_CONFIG DT structure -+typedef struct { -+ UINT64 NtFwConfigDtAddr; -+} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI; -+ - #endif -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -index 8d2069dea8..88ed640d29 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -@@ -1,6 +1,6 @@ - /** @file - * --* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. -+* Copyright (c) 2019 - 2022, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * -@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) - // the UEFI firmware through the CPU registers. - // - ASM_PFX(ArmPlatformPeiBootAction): -+ adr x10, NtFwConfigDtBlob -+ str x0, [x10] - ret - - // -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -index c0effd37f3..fabe902cd0 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -@@ -1,6 +1,6 @@ - /** @file - -- Copyright (c) 2018-2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -8,8 +8,12 @@ - - #include - #include -+#include - #include - -+UINT64 NtFwConfigDtBlob; -+STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi; -+ - STATIC ARM_CORE_INFO mCoreInfoTable[] = { - { 0x0, 0x0 }, // Cluster 0, Core 0 - { 0x0, 0x1 }, // Cluster 0, Core 1 -@@ -46,6 +50,7 @@ ArmPlatformInitialize ( - IN UINTN MpId - ) - { -+ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob; - return RETURN_SUCCESS; - } - -@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi -+ }, -+ { -+ EFI_PEI_PPI_DESCRIPTOR_PPI, -+ &gNtFwConfigDtInfoPpiGuid, -+ &mNtFwConfigDtInfoPpi - } - }; - -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -index 96e590cdd8..6f9c9d5ab6 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -@@ -1,7 +1,7 @@ - ## @file - # Platform Library for N1Sdp. - # --# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -18,10 +18,14 @@ - [Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec -+ EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec - -+[LibraryClasses] -+ FdtLib -+ - [Sources.common] - PlatformLibMem.c - PlatformLib.c -@@ -59,7 +63,9 @@ - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Guids] -+ gArmNeoverseN1SocPlatformInfoDescriptorGuid - gEfiHobListGuid ## CONSUMES ## SystemTable - - [Ppis] - gArmMpCoreInfoPpiGuid -+ gNtFwConfigDtInfoPpiGuid -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -index 339fa07b32..b58bda4b76 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -@@ -1,6 +1,6 @@ - /** @file - -- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -10,11 +10,95 @@ - #include - #include - #include -+#include -+#include - #include - - // The total number of descriptors, including the final "end-of-table" descriptor. - #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 - -+/** A helper function to locate the NtFwConfig PPI and get the base address of -+ NT_FW_CONFIG DT from which values are obtained using FDT helper functions. -+ -+ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB -+ -+ @retval EFI_SUCCESS Success. -+ returns EFI_INVALID_PARAMETER A parameter is invalid. -+**/ -+EFI_STATUS -+GetNeoverseN1SocPlatInfo ( -+ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info -+ ) -+{ -+ CONST UINT32 *Property; -+ INT32 Offset; -+ CONST VOID *NtFwCfgDtBlob; -+ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi; -+ EFI_STATUS Status; -+ -+ Status = PeiServicesLocatePpi ( -+ &gNtFwConfigDtInfoPpiGuid, -+ 0, -+ NULL, -+ (VOID **)&NtFwConfigInfoPpi -+ ); -+ -+ if (EFI_ERROR (Status)) { -+ DEBUG (( -+ DEBUG_ERROR, -+ "PeiServicesLocatePpi failed with error %r\n", -+ Status -+ )); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr; -+ if (fdt_check_header (NtFwCfgDtBlob) != 0) { -+ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob)); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info"); -+ if (Offset == -FDT_ERR_NOTFOUND) { -+ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->LocalDdrSize = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->MultichipMode = fdt32_to_cpu (*Property); -+ -+ return EFI_SUCCESS; -+} -+ - /** - Returns the Virtual Memory Map of the platform. - -@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap ( - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT64 DramBlock2Size; - UINT64 RemoteDdrSize; -+ EFI_STATUS Status; - - Index = 0; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; -+ -+ // Create platform info HOB -+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob ( -+ &gArmNeoverseN1SocPlatformInfoDescriptorGuid, -+ sizeof (NEOVERSEN1SOC_PLAT_INFO) -+ ); -+ -+ if (PlatInfo == NULL) { -+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); -+ ASSERT (FALSE); -+ return; -+ } -+ -+ Status = GetNeoverseN1SocPlatInfo (PlatInfo); -+ ASSERT (Status == 0); - DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - - NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * - (UINT64)SIZE_1GB); -diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -index d59f25a5b9..4dea8fe1e8 100644 ---- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -@@ -1,7 +1,7 @@ - ## @file - # Describes the entire platform configuration. - # --# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2022, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -22,6 +22,8 @@ - Include # Root include for the package - - [Guids.common] -+ # ARM NeoverseN1Soc Platform Info descriptor -+ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } } - gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } - - [PcdsFixedAtBuild] -@@ -83,3 +85,6 @@ - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050 - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051 -+ -+[Ppis] -+ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } } --- -2.17.1 - -- cgit v1.2.3