From 80d41842d41c701edac5b2c768da574f260fa6a3 Mon Sep 17 00:00:00 2001 From: Andrew Geissler Date: Mon, 11 Sep 2023 08:36:15 -0400 Subject: Revert "subtree updates" Needs to go through CI This reverts commit fc7e7973f3119e2bad511209aa336537dc5ffbed. --- .../conf/machine/corstone1000-fvp.conf | 7 - .../meta-arm-bsp/conf/machine/corstone500.conf | 49 + .../conf/machine/fvp-baser-aemv8r64.conf | 2 +- .../conf/machine/include/corstone1000.inc | 6 +- meta-arm/meta-arm-bsp/conf/machine/include/tc.inc | 7 +- meta-arm/meta-arm-bsp/conf/machine/n1sdp.conf | 2 +- meta-arm/meta-arm-bsp/documentation/corstone500.md | 28 + .../external-system/external-system_0.1.0.bb | 5 +- ...odule_code-atomically-rewrite-the-generat.patch | 67 - .../recipes-bsp/external-system/files/race.patch | 66 + ...e-cntp-timer-register-accesses-using-cnth.patch | 25 +- ...able-vhe-and-disable-branch-protection-fo.patch | 32 - .../files/tc/0001-tc-increase-heap-pages.patch | 27 + ...late-interrupt-controller-register-access.patch | 17 +- ...able-vhe-and-disable-branch-protection-fo.patch | 31 + ...isable-alignment-check-for-EL0-partitions.patch | 318 +++ ...t-STAGE1_NS-while-mapping-memory-from-NWd.patch | 41 - ...t-STAGE1_NS-while-mapping-memory-from-NWd.patch | 41 + .../recipes-bsp/hafnium/hafnium-tc.inc | 12 +- .../images/n1sdp-board-firmware_2022.06.22.bb | 2 +- .../scp-firmware/scp-firmware-n1sdp.inc | 3 - .../0001-Fix-FF-A-version-in-SPMC-manifest.patch | 11 +- ...stone1000-bl2-loads-fip-based-on-metadata.patch | 24 +- ...ix-corstone1000-add-cpuhelper-to-makefile.patch | 28 - .../trusted-firmware-a/files/rwx-segments.patch | 38 - .../files/tf-a-tests-no-warn-rwx-segments.patch | 26 - .../trusted-firmware-a/fiptool-native_2.8.6.bb | 33 - .../trusted-firmware-a/tf-a-tests_%.bbappend | 4 - .../trusted-firmware-a/tf-a-tests_2.8.0.bb | 54 - .../trusted-firmware-a/tf-a-tests_2.8.0.bbappend | 4 + .../trusted-firmware-a-corstone1000.inc | 16 +- .../trusted-firmware-a-corstone500.inc | 17 + .../trusted-firmware-a-n1sdp.inc | 4 - .../trusted-firmware-a_%.bbappend | 13 - .../trusted-firmware-a_2.8.%.bbappend | 14 + .../trusted-firmware-a/trusted-firmware-a_2.8.6.bb | 15 - ...orm-corstone1000-add-unique-firmware-GUID.patch | 35 - .../trusted-firmware-m-corstone1000.inc | 1 - .../0033-Increase-the-unzipped-Kernel-size.patch | 29 + ...-corstone1000-detect-inflated-kernel-size.patch | 29 - ...orstone1000-ESRT-add-unique-firmware-GUID.patch | 47 - ...-adding-generic-timer-access-through-MMIO.patch | 139 ++ .../0002-board-arm-add-corstone500-board.patch | 299 +++ ...1-armv8-Add-ARMv8-MPU-configuration-logic.patch | 14 +- ...ss64-add-MPU-memory-map-for-the-BASER_FVP.patch | 8 +- ...-disabling-exception-vectors-on-non-SPL-b.patch | 11 +- ...04-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch | 14 +- ...disabling-HVC-configurable-when-switching.patch | 9 +- ...6-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch | 8 +- ...Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch | 8 +- ...low-PRBAR-MPU-attributes-to-be-configured.patch | 10 +- ...e-icache-when-switching-exception-levels-.patch | 8 +- .../recipes-bsp/u-boot/u-boot_%.bbappend | 10 +- .../recipes-bsp/u-boot/u-boot_2022.10.bb | 26 + .../recipes-bsp/uefi/edk2-firmware-n1sdp.inc | 18 +- ...M-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch | 471 ++++ ...Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch | 44 + ...M-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch | 63 + ...-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch | 57 + ...orm-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch | 119 + ...-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch | 2538 ++++++++++++++++++++ ...rm-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch | 88 + ...M-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch | 50 + ...M-N1Sdp-manually-poll-QSPI-status-bit-aft.patch | 197 ++ ...M-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch | 471 ---- ...M-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch | 63 - ...-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch | 57 - ...orm-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch | 119 - ...-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch | 2538 -------------------- ...rm-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch | 88 - ...M-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch | 50 - ...M-N1Sdp-manually-poll-QSPI-status-bit-aft.patch | 197 -- ...pdate-cache-properties-for-Arm-Ltd-platfo.patch | 138 ++ ...2-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch | 35 + ...vp-Add-information-about-L1-and-L2-caches.patch | 146 ++ ...xpress-align-LED-node-names-with-dtschema.patch | 81 + .../recipes-kernel/linux/linux-arm-platforms.inc | 13 + .../optee-os/tc/0001-WIP-Enable-managed-exit.patch | 24 +- ...at-totalcompute-fix-TZDRAM-start-and-size.patch | 44 +- .../optee/optee-client/tee-supplicant.service | 1 - .../optee/optee-os-corstone1000-common.inc | 6 + .../recipes-security/optee/optee-os-generic-tc.inc | 14 + .../recipes-security/optee/optee-os-n1sdp.inc | 2 - .../optee/optee-os-tadevkit_3.18.0.bbappend | 2 +- .../recipes-security/optee/optee-os-tc.inc | 12 +- .../optee/optee-os_3.20.0.bbappend | 2 +- .../optee/optee-os_3.22.0.bbappend | 6 - ...ssion_1000-remove-unneeded-stat.h-include.patch | 34 - ...d-arm_ffa_user-driver-compatibility-check.patch | 160 -- ...003-Update-arm_ffa_user-driver-dependency.patch | 36 - .../Update-arm_ffa_user-driver-dependency.patch | 39 + ...d-arm_ffa_user-driver-compatibility-check.patch | 163 ++ .../optee/optee-test/musl-workaround.patch | 24 + .../recipes-security/optee/optee-test_3.18.0.bb | 2 +- .../optee/optee-test_3.18.0.bbappend | 1 + .../recipes-security/optee/optee-test_3.20.0.bb | 6 +- .../optee/optee-test_3.20.0.bbappend | 6 - ...t-corstone1000-change-ns-interrupt-action.patch | 31 - .../trusted-services/ts-arm-platforms.inc | 1 - .../corstone1000-external-sys-tests_1.0.bb | 2 +- .../wic/core-image-minimal.corstone500.wks | 12 + 101 files changed, 5585 insertions(+), 4480 deletions(-) create mode 100644 meta-arm/meta-arm-bsp/conf/machine/corstone500.conf create mode 100644 meta-arm/meta-arm-bsp/documentation/corstone500.md delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/0001-tools-gen_module_code-atomically-rewrite-the-generat.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/race.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-tc-increase-heap-pages.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-disable-alignment-check-for-EL0-partitions.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0004-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-add-cpuhelper-to-makefile.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/rwx-segments.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tf-a-tests-no-warn-rwx-segments.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/fiptool-native_2.8.6.bb delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bbappend create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone500.inc delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.%.bbappend delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.6.bb delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-Platform-corstone1000-add-unique-firmware-GUID.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0004-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0005-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0006-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-generic-tc.inc delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.22.0.bbappend delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0002-ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0003-Update-arm_ffa_user-driver-dependency.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/Update-arm_ffa_user-driver-dependency.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch create mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/musl-workaround.patch delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bbappend delete mode 100644 meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/0008-plat-corstone1000-change-ns-interrupt-action.patch create mode 100644 meta-arm/meta-arm-bsp/wic/core-image-minimal.corstone500.wks (limited to 'meta-arm/meta-arm-bsp') diff --git a/meta-arm/meta-arm-bsp/conf/machine/corstone1000-fvp.conf b/meta-arm/meta-arm-bsp/conf/machine/corstone1000-fvp.conf index ebfba5b93f..9636ffe4a0 100644 --- a/meta-arm/meta-arm-bsp/conf/machine/corstone1000-fvp.conf +++ b/meta-arm/meta-arm-bsp/conf/machine/corstone1000-fvp.conf @@ -49,10 +49,3 @@ FVP_CONFIG[board.msd_mmc.p_fast_access] ?= "0" FVP_CONFIG[board.msd_mmc.diagnostics] ?= "2" FVP_CONFIG[board.msd_mmc.p_max_block_count] ?= "0xFFFF" FVP_CONFIG[board.msd_config.pl180_fifo_depth] ?= "16" - -# MMC2 card configuration -FVP_CONFIG[board.msd_mmc_2.card_type] ?= "SDHC" -FVP_CONFIG[board.msd_mmc_2.p_fast_access] ?= "0" -FVP_CONFIG[board.msd_mmc_2.diagnostics] ?= "2" -FVP_CONFIG[board.msd_mmc_2.p_max_block_count] ?= "0xFFFF" -FVP_CONFIG[board.msd_config_2.pl180_fifo_depth] ?= "16" \ No newline at end of file diff --git a/meta-arm/meta-arm-bsp/conf/machine/corstone500.conf b/meta-arm/meta-arm-bsp/conf/machine/corstone500.conf new file mode 100644 index 0000000000..6d2294c273 --- /dev/null +++ b/meta-arm/meta-arm-bsp/conf/machine/corstone500.conf @@ -0,0 +1,49 @@ +#@TYPE: Machine +#@NAME: Corstone-500 machine +#@DESCRIPTION: Machine configuration for the Corstone-500 platform + +require conf/machine/include/arm/armv7a/tune-cortexa5.inc + +# Corstone-500 is built against poky-tiny distro. +# poky-tiny sets PREFERRED_PROVIDER_virtual/kernel to linux-yocto-tiny. +# Since distro config is evaluated after the machine config, we need to +# use the strongest override possible (forcevariable) so the +# PREFERRED_PROVIDER_virtual/kernel specified in the machine config will +# apply. +# +PREFERRED_PROVIDER_virtual/kernel:forcevariable = "linux-yocto" +PREFERRED_VERSION_linux-yocto ?= "6.1%" + +EXTRA_IMAGEDEPENDS += "trusted-firmware-a u-boot" + +IMAGE_CLASSES += "wic_nopt" +IMAGE_FSTYPES:forcevariable = "cpio.gz squashfs wic wic.nopt" + +SERIAL_CONSOLES = "115200;ttyAMA0" + +# Corstone-500 u-boot configuration +UBOOT_MACHINE = "corstone500_defconfig" +UBOOT_IMAGE_ENTRYPOINT = "0x84000000" +UBOOT_IMAGE_LOADADDRESS = "0x84000000" +PREFERRED_VERSION_u-boot ?= "2023.01" + +# making sure EXTRA_IMAGEDEPENDS will be used while creating the image +WKS_FILE_DEPENDS:append = " ${EXTRA_IMAGEDEPENDS}" + +WKS_FILE ?= "core-image-minimal.corstone500.wks" + +TEST_TARGET = "OEFVPTarget" +TEST_SUITES = "fvp_boot" + +FVP_PROVIDER ?= "fvp-corstone500-native" +FVP_EXE ?= "FVP_Corstone-500" +FVP_CONFIG[board.flashloader0.fname] ?= "bl1.bin" +FVP_DATA ?= "css.cluster.cpu0=${IMAGE_NAME}.wic.nopt@0x80000000" +FVP_CONSOLE ?= "terminal_0" +FVP_TERMINALS[css.terminal_0] ?= "console" +FVP_TERMINALS[css.terminal_1] ?= "" + +# Disable openssl in kmod to shink the initramfs size +PACKAGECONFIG:remove:pn-kmod = "openssl" + +IMAGE_NAME_SUFFIX = "" diff --git a/meta-arm/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf b/meta-arm/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf index 7d2eaf9b94..25ba3c840f 100644 --- a/meta-arm/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf +++ b/meta-arm/meta-arm-bsp/conf/machine/fvp-baser-aemv8r64.conf @@ -9,7 +9,7 @@ require conf/machine/include/arm/armv8r/arch-armv8r64.inc EXTRA_IMAGEDEPENDS += "boot-wrapper-aarch64" PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" -PREFERRED_VERSION_u-boot ?= "2023.01" +PREFERRED_VERSION_u-boot ?= "2022.10" KERNEL_IMAGETYPE = "Image" KERNEL_DEVICETREE = "arm/fvp-baser-aemv8r64.dtb" diff --git a/meta-arm/meta-arm-bsp/conf/machine/include/corstone1000.inc b/meta-arm/meta-arm-bsp/conf/machine/include/corstone1000.inc index 72c0af518d..aeb1411ab9 100644 --- a/meta-arm/meta-arm-bsp/conf/machine/include/corstone1000.inc +++ b/meta-arm/meta-arm-bsp/conf/machine/include/corstone1000.inc @@ -5,8 +5,6 @@ MACHINEOVERRIDES =. "corstone1000:" # TF-A TFA_PLATFORM = "corstone1000" EXTRA_IMAGEDEPENDS += "trusted-firmware-a" -PREFERRED_VERSION_trusted-firmware-a ?= "2.9.%" -PREFERRED_VERSION_tf-a-tests ?= "2.8.%" TFA_BL2_BINARY = "bl2-corstone1000.bin" TFA_FIP_BINARY = "fip-corstone1000.bin" @@ -36,8 +34,8 @@ UBOOT_ARCH = "arm" UBOOT_EXTLINUX = "0" #optee -PREFERRED_VERSION_optee-os ?= "3.22%" -PREFERRED_VERSION_optee-client ?= "3.22%" +PREFERRED_VERSION_optee-os ?= "3.20.%" +PREFERRED_VERSION_optee-client ?= "3.18.%" EXTRA_IMAGEDEPENDS += "optee-os" OPTEE_ARCH = "arm64" OPTEE_BINARY = "tee-pager_v2.bin" diff --git a/meta-arm/meta-arm-bsp/conf/machine/include/tc.inc b/meta-arm/meta-arm-bsp/conf/machine/include/tc.inc index 872f58cbfe..f6674ba481 100644 --- a/meta-arm/meta-arm-bsp/conf/machine/include/tc.inc +++ b/meta-arm/meta-arm-bsp/conf/machine/include/tc.inc @@ -14,9 +14,9 @@ UBOOT_ENTRYPOINT = "0x80080000" PREFERRED_PROVIDER_virtual/kernel ?= "linux-yocto" # OP-TEE -PREFERRED_VERSION_optee-os ?= "3.20%" -PREFERRED_VERSION_optee-client ?= "3.20%" -PREFERRED_VERSION_optee-test ?= "3.20%" +PREFERRED_VERSION_optee-os ?= "3.18%" +PREFERRED_VERSION_optee-client ?= "3.18%" +PREFERRED_VERSION_optee-test ?= "3.18%" # Cannot use the default zImage on arm64 KERNEL_IMAGETYPE = "Image" @@ -30,7 +30,6 @@ IMAGE_NAME_SUFFIX = "" SERIAL_CONSOLES = "115200;ttyAMA0" EXTRA_IMAGEDEPENDS += "trusted-firmware-a optee-os" -PREFERRED_VERSION_trusted-firmware-a ?= "2.8.%" # FIXME - there is signed image dependency/race with testimage. # This should be fixed in oe-core TESTIMAGEDEPENDS:append = " virtual/kernel:do_deploy" diff --git a/meta-arm/meta-arm-bsp/conf/machine/n1sdp.conf b/meta-arm/meta-arm-bsp/conf/machine/n1sdp.conf index c25a32dcff..16b409861b 100644 --- a/meta-arm/meta-arm-bsp/conf/machine/n1sdp.conf +++ b/meta-arm/meta-arm-bsp/conf/machine/n1sdp.conf @@ -29,7 +29,7 @@ EXTRA_IMAGEDEPENDS += "virtual/control-processor-firmware" #UEFI EDK2 firmware EXTRA_IMAGEDEPENDS += "edk2-firmware" -PREFERRED_VERSION_edk2-firmware ?= "202305" +PREFERRED_VERSION_edk2-firmware ?= "202211" #optee PREFERRED_VERSION_optee-os ?= "3.20.%" diff --git a/meta-arm/meta-arm-bsp/documentation/corstone500.md b/meta-arm/meta-arm-bsp/documentation/corstone500.md new file mode 100644 index 0000000000..0f019611b7 --- /dev/null +++ b/meta-arm/meta-arm-bsp/documentation/corstone500.md @@ -0,0 +1,28 @@ +# Corstone-500 Platform Support in meta-arm-bsp + +## Howto Build and Run + +### Configuration: + +Use the kas + +### Build: + +``bash$ kas build kas/corstone500.yml + +### Run: + +Building using kas should have fetch the Fixed Virtual Platform for this +platform and installed at: + +build/tmp/sysroots-components/x86_64/fvp-corstone500-native/usr/bin/./FVP_Corstone-500 + +with this in place is possible to launch the FVP using the runfvp inside the +scripts directory: + +cd scripts + +./runfvp ../build/tmp/deploy/images/corstone500/core-image-minimal-corstone500.fvpconf --console + +this will output the console in the launching terminal + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/external-system/external-system_0.1.0.bb b/meta-arm/meta-arm-bsp/recipes-bsp/external-system/external-system_0.1.0.bb index 18649ceeaf..8b09ab0d07 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/external-system/external-system_0.1.0.bb +++ b/meta-arm/meta-arm-bsp/recipes-bsp/external-system/external-system_0.1.0.bb @@ -9,12 +9,11 @@ LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0 \ file://cmsis/LICENSE.txt;md5=e3fc50a88d0a364313df4b21ef20c29e" SRC_URI = "gitsm://git.gitlab.arm.com/arm-reference-solutions/corstone1000/external_system/rtx.git;protocol=https;branch=master \ - file://0001-tools-gen_module_code-atomically-rewrite-the-generat.patch" + file://race.patch" SRCREV = "8c9dca74b104ff6c9722fb0738ba93dd3719c080" -PV .= "+git" +PV .= "+git${SRCPV}" COMPATIBLE_MACHINE = "(corstone1000)" -PACKAGE_ARCH = "${MACHINE_ARCH}" # PRODUCT is passed to the Makefile to specify the platform to be used. PRODUCT = "corstone-1000" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/0001-tools-gen_module_code-atomically-rewrite-the-generat.patch b/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/0001-tools-gen_module_code-atomically-rewrite-the-generat.patch deleted file mode 100644 index 70087ff2e2..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/0001-tools-gen_module_code-atomically-rewrite-the-generat.patch +++ /dev/null @@ -1,67 +0,0 @@ -From fa5ed6204f9188134a87ac9dd569e1496759a7f6 Mon Sep 17 00:00:00 2001 -From: Ross Burton -Date: Tue, 8 Sep 2020 11:49:08 +0100 -Subject: [PATCH] tools/gen_module_code: atomically rewrite the generated files - -Upstream-Status: Submitted [https://gitlab.arm.com/arm-reference-solutions/corstone1000/external_system/rtx/-/issues/1] -Signed-off-by: Ross Burton - -The gen_module rule in rules.mk is marked as .PHONY, so make will -execute it whenever it is mentioned. This results in gen_module_code -being executed 64 times for a Juno build. - -However in heavily parallel builds there's a good chance that -gen_module_code is writing a file whilst the compiler is reading it -because make also doesn't know what files are generated by -gen_module_code. - -The correct fix is to adjust the Makefiles so that the dependencies are -correct but this isn't trivial, so band-aid the problem by atomically -writing the generated files. - -Change-Id: I82d44f9ea6537a91002e1f80de8861d208571630 -Signed-off-by: Ross Burton - ---- - tools/gen_module_code.py | 19 ++++++++++++++----- - 1 file changed, 14 insertions(+), 5 deletions(-) - -diff --git a/tools/gen_module_code.py b/tools/gen_module_code.py -index 6bf50e0..92623a7 100755 ---- a/tools/gen_module_code.py -+++ b/tools/gen_module_code.py -@@ -17,6 +17,7 @@ - import argparse - import os - import sys -+import tempfile - - DEFAULT_PATH = 'build/' - -@@ -55,13 +56,21 @@ TEMPLATE_C = "/* This file was auto generated using {} */\n" \ - - def generate_file(path, filename, content): - full_filename = os.path.join(path, filename) -- with open(full_filename, 'a+') as f: -- f.seek(0) -- if f.read() != content: -+ -+ try: -+ with open(full_filename) as f: -+ rewrite = f.read() != content -+ except FileNotFoundError: -+ rewrite = True -+ -+ if rewrite: -+ with tempfile.NamedTemporaryFile(prefix="gen-module-code", -+ dir=path, -+ delete=False, -+ mode="wt") as f: - print("[GEN] {}...".format(full_filename)) -- f.seek(0) -- f.truncate() - f.write(content) -+ os.replace(f.name, full_filename) - - - def generate_header(path, modules): diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/race.patch b/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/race.patch new file mode 100644 index 0000000000..c6bc4f2234 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/external-system/files/race.patch @@ -0,0 +1,66 @@ +Upstream-Status: Submitted [https://gitlab.arm.com/arm-reference-solutions/corstone1000/external_system/rtx/-/issues/1] +Signed-off-by: Ross Burton + +From 34e1c04534607f5605255f39fb46e26261fc9c4e Mon Sep 17 00:00:00 2001 +From: Ross Burton +Date: Tue, 8 Sep 2020 11:49:08 +0100 +Subject: [PATCH] tools/gen_module_code: atomically rewrite the generated files + +The gen_module rule in rules.mk is marked as .PHONY, so make will +execute it whenever it is mentioned. This results in gen_module_code +being executed 64 times for a Juno build. + +However in heavily parallel builds there's a good chance that +gen_module_code is writing a file whilst the compiler is reading it +because make also doesn't know what files are generated by +gen_module_code. + +The correct fix is to adjust the Makefiles so that the dependencies are +correct but this isn't trivial, so band-aid the problem by atomically +writing the generated files. + +Change-Id: I82d44f9ea6537a91002e1f80de8861d208571630 +Signed-off-by: Ross Burton +--- + tools/gen_module_code.py | 19 ++++++++++++++----- + 1 file changed, 14 insertions(+), 5 deletions(-) + +diff --git a/tools/gen_module_code.py b/tools/gen_module_code.py +index 7b3953845..ee099b713 100755 +--- a/tools/gen_module_code.py ++++ b/tools/gen_module_code.py +@@ -17,6 +17,7 @@ + import argparse + import os + import sys ++import tempfile + + DEFAULT_PATH = 'build/' + +@@ -53,13 +54,21 @@ + + def generate_file(path, filename, content): + full_filename = os.path.join(path, filename) +- with open(full_filename, 'a+') as f: +- f.seek(0) +- if f.read() != content: ++ ++ try: ++ with open(full_filename) as f: ++ rewrite = f.read() != content ++ except FileNotFoundError: ++ rewrite = True ++ ++ if rewrite: ++ with tempfile.NamedTemporaryFile(prefix="gen-module-code", ++ dir=path, ++ delete=False, ++ mode="wt") as f: + print("[GEN] {}...".format(full_filename)) +- f.seek(0) +- f.truncate() + f.write(content) ++ os.replace(f.name, full_filename) + + + def generate_header(path, modules): diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch index 9ae4b39f85..a9a839ea8d 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch @@ -1,4 +1,4 @@ -From 3bc797e097ef2b29acf36560e4d2bfeec31f8d81 Mon Sep 17 00:00:00 2001 +From f526797b83113cc64e3e658c22d8a5d269896a2a Mon Sep 17 00:00:00 2001 From: Ben Horgan Date: Fri, 4 Mar 2022 16:48:14 +0000 Subject: [PATCH] feat: emulate cntp timer register accesses using cnthps @@ -19,7 +19,7 @@ Change-Id: I67508203273baf3bd8e6be2d99717028db945715 create mode 100644 src/arch/aarch64/hypervisor/timer_el1.h diff --git a/Makefile b/Makefile -index 95cab9a56bfd..21cca938531d 100644 +index 95cab9a5..21cca938 100644 --- a/Makefile +++ b/Makefile @@ -60,7 +60,8 @@ CHECKPATCH := $(CURDIR)/third_party/linux/scripts/checkpatch.pl \ @@ -33,7 +33,7 @@ index 95cab9a56bfd..21cca938531d 100644 OUT ?= out/$(PROJECT) OUT_DIR = out/$(PROJECT) diff --git a/src/arch/aarch64/hypervisor/BUILD.gn b/src/arch/aarch64/hypervisor/BUILD.gn -index 6068d1e8f075..de1a414dac68 100644 +index 6068d1e8..de1a414d 100644 --- a/src/arch/aarch64/hypervisor/BUILD.gn +++ b/src/arch/aarch64/hypervisor/BUILD.gn @@ -45,6 +45,7 @@ source_set("hypervisor") { @@ -45,7 +45,7 @@ index 6068d1e8f075..de1a414dac68 100644 ] diff --git a/src/arch/aarch64/hypervisor/cpu.c b/src/arch/aarch64/hypervisor/cpu.c -index 5e025b596674..edd5df134cfc 100644 +index bcf5ffce..d2df77d8 100644 --- a/src/arch/aarch64/hypervisor/cpu.c +++ b/src/arch/aarch64/hypervisor/cpu.c @@ -98,13 +98,20 @@ void arch_regs_reset(struct vcpu *vcpu) @@ -72,7 +72,7 @@ index 5e025b596674..edd5df134cfc 100644 } diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c -index 3422ff7b8265..c495df40f3f5 100644 +index 4bd8a3b4..4c1b6e48 100644 --- a/src/arch/aarch64/hypervisor/handler.c +++ b/src/arch/aarch64/hypervisor/handler.c @@ -34,6 +34,7 @@ @@ -83,8 +83,8 @@ index 3422ff7b8265..c495df40f3f5 100644 /** * Hypervisor Fault Address Register Non-Secure. -@@ -1295,6 +1296,11 @@ void handle_system_register_access(uintreg_t esr_el2) - inject_el1_sysreg_trap_exception(vcpu, esr_el2); +@@ -1277,6 +1278,11 @@ void handle_system_register_access(uintreg_t esr_el2) + inject_el1_unknown_exception(vcpu, esr_el2); return; } + } else if (timer_el1_is_register_access(esr_el2)) { @@ -93,11 +93,11 @@ index 3422ff7b8265..c495df40f3f5 100644 + return; + } } else { - inject_el1_sysreg_trap_exception(vcpu, esr_el2); + inject_el1_unknown_exception(vcpu, esr_el2); return; diff --git a/src/arch/aarch64/hypervisor/timer_el1.c b/src/arch/aarch64/hypervisor/timer_el1.c new file mode 100644 -index 000000000000..c30e5543f436 +index 00000000..c30e5543 --- /dev/null +++ b/src/arch/aarch64/hypervisor/timer_el1.c @@ -0,0 +1,104 @@ @@ -207,7 +207,7 @@ index 000000000000..c30e5543f436 +} diff --git a/src/arch/aarch64/hypervisor/timer_el1.h b/src/arch/aarch64/hypervisor/timer_el1.h new file mode 100644 -index 000000000000..04a43b6ca335 +index 00000000..04a43b6c --- /dev/null +++ b/src/arch/aarch64/hypervisor/timer_el1.h @@ -0,0 +1,20 @@ @@ -232,10 +232,10 @@ index 000000000000..04a43b6ca335 +bool timer_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id, + uintreg_t esr); diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h -index 6edc39f2af48..bf1a66d1d4c5 100644 +index cd6778b4..55e78330 100644 --- a/src/arch/aarch64/msr.h +++ b/src/arch/aarch64/msr.h -@@ -131,3 +131,11 @@ +@@ -126,3 +126,11 @@ #define MSR_ELR_EL12 S3_5_C4_C0_1 #endif @@ -247,3 +247,4 @@ index 6edc39f2af48..bf1a66d1d4c5 100644 +#define MSR_CNTHPS_CTL_EL2 S3_4_C14_C5_1 +#define MSR_CNTHPS_CVAL_EL2 S3_4_C14_C5_2 +#define MSR_CNTHPS_TVAL_EL2 S3_4_C14_C5_0 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch deleted file mode 100644 index 9627a765f1..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 1fef5bd2504ce3a203c56a3b66dba773cd4893c6 Mon Sep 17 00:00:00 2001 -From: Davidson K -Date: Thu, 8 Sep 2022 10:47:10 +0530 -Subject: [PATCH] feat(vhe): enable vhe and disable branch protection for TC - -Signed-off-by: Davidson K -Change-Id: I60cd607d9f2bf0114b482980e7ca68e24aaf4d1f -Upstream-Status: Pending [Not submitted to upstream yet] ---- - BUILD.gn | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/BUILD.gn b/BUILD.gn -index cc6a78f4fdb8..acd1f9d1634b 100644 ---- a/BUILD.gn -+++ b/BUILD.gn -@@ -245,7 +245,6 @@ aarch64_toolchains("secure_tc") { - heap_pages = 180 - max_cpus = 8 - max_vms = 16 -- branch_protection = "standard" - toolchain_args = { - plat_ffa = "//src/arch/aarch64/plat/ffa:spmc" - plat_psci = "//src/arch/aarch64/plat/psci:spmc" -@@ -254,6 +253,7 @@ aarch64_toolchains("secure_tc") { - secure_world = "1" - pl011_base_address = "0x7ff80000" - enable_mte = "1" -+ enable_vhe = "1" - plat_log_level = "LOG_LEVEL_INFO" - } - } diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-tc-increase-heap-pages.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-tc-increase-heap-pages.patch new file mode 100644 index 0000000000..fa35efc112 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0001-tc-increase-heap-pages.patch @@ -0,0 +1,27 @@ +From 613dea068fa546956717ce0b60328e39d451f661 Mon Sep 17 00:00:00 2001 +From: Arunachalam Ganapathy +Date: Fri, 29 Apr 2022 20:07:50 +0100 +Subject: [PATCH] tc: increase heap pages + +Upstream-Status: Pending +Signed-off-by: Arunachalam Ganapathy +--- + BUILD.gn | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/BUILD.gn b/BUILD.gn +index 6b9b383..62ba763 100644 +--- a/BUILD.gn ++++ b/BUILD.gn +@@ -235,7 +235,7 @@ aarch64_toolchains("secure_tc") { + gicd_base_address = "0x30000000" + gicr_base_address = "0x30080000" + gicr_frames = 8 +- heap_pages = 60 ++ heap_pages = 120 + max_cpus = 8 + max_vms = 16 + branch_protection = "standard" +-- +2.30.2 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-emulate-interrupt-controller-register-access.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-emulate-interrupt-controller-register-access.patch index 3e6761519a..d9ec6e2a99 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-emulate-interrupt-controller-register-access.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-emulate-interrupt-controller-register-access.patch @@ -1,4 +1,4 @@ -From 9f5b07e30c82713b9598ea60d9f802bd419b560f Mon Sep 17 00:00:00 2001 +From 97a8ca1835f5d9512dacda497540d5523e56c7dd Mon Sep 17 00:00:00 2001 From: Arunachalam Ganapathy Date: Tue, 26 Apr 2022 14:43:58 +0100 Subject: [PATCH] feat: emulate interrupt controller register access @@ -16,10 +16,10 @@ Upstream-Status: Inappropriate [Experimental feature] 4 files changed, 97 insertions(+) diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c -index c495df40f3f5..13578fc99670 100644 +index 4c1b6e48..cd5146bd 100644 --- a/src/arch/aarch64/hypervisor/handler.c +++ b/src/arch/aarch64/hypervisor/handler.c -@@ -1301,6 +1301,11 @@ void handle_system_register_access(uintreg_t esr_el2) +@@ -1283,6 +1283,11 @@ void handle_system_register_access(uintreg_t esr_el2) inject_el1_unknown_exception(vcpu, esr_el2); return; } @@ -29,10 +29,10 @@ index c495df40f3f5..13578fc99670 100644 + return; + } } else { - inject_el1_sysreg_trap_exception(vcpu, esr_el2); + inject_el1_unknown_exception(vcpu, esr_el2); return; diff --git a/src/arch/aarch64/hypervisor/perfmon.c b/src/arch/aarch64/hypervisor/perfmon.c -index f13b035480d8..05e216c84c2e 100644 +index f13b0354..05e216c8 100644 --- a/src/arch/aarch64/hypervisor/perfmon.c +++ b/src/arch/aarch64/hypervisor/perfmon.c @@ -116,6 +116,10 @@ @@ -131,7 +131,7 @@ index f13b035480d8..05e216c84c2e 100644 + return true; +} diff --git a/src/arch/aarch64/hypervisor/perfmon.h b/src/arch/aarch64/hypervisor/perfmon.h -index 81669ba1c401..c90d45bfc239 100644 +index 81669ba1..c90d45bf 100644 --- a/src/arch/aarch64/hypervisor/perfmon.h +++ b/src/arch/aarch64/hypervisor/perfmon.h @@ -70,3 +70,8 @@ bool perfmon_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id, @@ -144,13 +144,14 @@ index 81669ba1c401..c90d45bfc239 100644 +bool intr_ctrl_el1_process_access(struct vcpu *vcpu, ffa_vm_id_t vm_id, + uintreg_t esr); diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h -index bf1a66d1d4c5..b88a14b52f68 100644 +index 55e78330..82aa8846 100644 --- a/src/arch/aarch64/msr.h +++ b/src/arch/aarch64/msr.h -@@ -139,3 +139,6 @@ +@@ -134,3 +134,6 @@ #define MSR_CNTHPS_CTL_EL2 S3_4_C14_C5_1 #define MSR_CNTHPS_CVAL_EL2 S3_4_C14_C5_2 #define MSR_CNTHPS_TVAL_EL2 S3_4_C14_C5_0 + +#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 +#define ICC_SGI1R_EL1 S3_0_C12_C11_5 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch new file mode 100644 index 0000000000..9960f65dcf --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0002-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch @@ -0,0 +1,31 @@ +From 1fef5bd2504ce3a203c56a3b66dba773cd4893c6 Mon Sep 17 00:00:00 2001 +From: Davidson K +Date: Thu, 8 Sep 2022 10:47:10 +0530 +Subject: [PATCH] feat(vhe): enable vhe and disable branch protection for TC + +Signed-off-by: Davidson K +Change-Id: I60cd607d9f2bf0114b482980e7ca68e24aaf4d1f +Upstream-Status: Pending [Not submitted to upstream yet] +--- + BUILD.gn | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/BUILD.gn b/BUILD.gn +index 62ba763..f26ce03 100644 +--- a/BUILD.gn ++++ b/BUILD.gn +@@ -238,7 +238,6 @@ aarch64_toolchains("secure_tc") { + heap_pages = 120 + max_cpus = 8 + max_vms = 16 +- branch_protection = "standard" + toolchain_args = { + plat_ffa = "//src/arch/aarch64/plat/ffa:spmc" + plat_psci = "//src/arch/aarch64/plat/psci:spmc" +@@ -247,5 +246,6 @@ aarch64_toolchains("secure_tc") { + secure_world = "1" + pl011_base_address = "0x7ff80000" + enable_mte = "1" ++ enable_vhe = "1" + } + } diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-disable-alignment-check-for-EL0-partitions.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-disable-alignment-check-for-EL0-partitions.patch new file mode 100644 index 0000000000..5e620cf318 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-disable-alignment-check-for-EL0-partitions.patch @@ -0,0 +1,318 @@ +From 1c4d28493faed6cf189c75fa91d19131e6a34e04 Mon Sep 17 00:00:00 2001 +From: Olivier Deprez +Date: Mon, 8 Aug 2022 19:14:23 +0200 +Subject: [PATCH] feat: disable alignment check for EL0 partitions + +Relax hw alignment check specifically for (S-)EL0 partitions when +Hafnium runs with VHE enabled. EL1 partitions have a specific control +for EL1 and EL0 with respect to alignment check. +Create a hyp_state structure (from already defined flying registers) +within the vCPU context to hold the Hypervisor EL2 static configuration +applied when a vCPU runs. This state is switched back and forth when +running the Hypervisor or the VM. +Add SCTLR_EL2 to this context. An EL0 partition context is initialized +with SCTLR_EL2.A=0 such that alignment check is disabled when EL0 runs +in the EL2&0 translation regime. SCTLR_EL2.A is set back when returning +to the Hypervisor such that Hypervisor execution runs with aligment +check enabled at EL2. +Remove HCR_EL2 saving from vCPU exit path provided this register state +is static and doesn't change while a vCPU runs. +The rationale for such change is to permit running upstream SW stacks +such as the EDKII/StandaloneMm [1] for which default build assumes +unaligned accesses are permitted. Similar query exists for running +Trusted Services on top of Hafnium [2]. + +[1] https://github.com/tianocore/edk2/tree/master/StandaloneMmPkg +[2] https://trusted-services.readthedocs.io/en/integration/ + +Signed-off-by: Olivier Deprez +Change-Id: I2906f4c712425fcfb31adbf89e2e3b9ca293f181 +Upstream-Status: Submitted [https://review.trustedfirmware.org/c/hafnium/hafnium/+/16195] +--- + src/arch/aarch64/hypervisor/cpu.c | 9 ++++--- + src/arch/aarch64/hypervisor/exceptions.S | 32 ++++++++++++++++-------- + src/arch/aarch64/hypervisor/feature_id.c | 6 ++--- + src/arch/aarch64/hypervisor/handler.c | 18 +++++++------ + src/arch/aarch64/inc/hf/arch/types.h | 9 +++++-- + src/arch/aarch64/mm.c | 2 +- + src/arch/aarch64/sysregs.c | 11 ++++++-- + src/arch/aarch64/sysregs.h | 2 +- + 8 files changed, 59 insertions(+), 30 deletions(-) + +diff --git a/src/arch/aarch64/hypervisor/cpu.c b/src/arch/aarch64/hypervisor/cpu.c +index d2df77d8..a000159b 100644 +--- a/src/arch/aarch64/hypervisor/cpu.c ++++ b/src/arch/aarch64/hypervisor/cpu.c +@@ -115,7 +115,9 @@ void arch_regs_reset(struct vcpu *vcpu) + } + } + +- r->hcr_el2 = get_hcr_el2_value(vm_id, vcpu->vm->el0_partition); ++ r->hyp_state.hcr_el2 = ++ get_hcr_el2_value(vm_id, vcpu->vm->el0_partition); ++ r->hyp_state.sctlr_el2 = get_sctlr_el2_value(vcpu->vm->el0_partition); + r->lazy.cnthctl_el2 = cnthctl; + if (vcpu->vm->el0_partition) { + CHECK(has_vhe_support()); +@@ -125,10 +127,11 @@ void arch_regs_reset(struct vcpu *vcpu) + * are ignored and treated as 0. There is no need to mask the + * VMID (used as asid) to only 8 bits. + */ +- r->ttbr0_el2 = pa_addr(table) | ((uint64_t)vm_id << 48); ++ r->hyp_state.ttbr0_el2 = ++ pa_addr(table) | ((uint64_t)vm_id << 48); + r->spsr = PSR_PE_MODE_EL0T; + } else { +- r->ttbr0_el2 = read_msr(ttbr0_el2); ++ r->hyp_state.ttbr0_el2 = read_msr(ttbr0_el2); + r->lazy.vtcr_el2 = arch_mm_get_vtcr_el2(); + r->lazy.vttbr_el2 = pa_addr(table) | ((uint64_t)vm_id << 48); + #if SECURE_WORLD == 1 +diff --git a/src/arch/aarch64/hypervisor/exceptions.S b/src/arch/aarch64/hypervisor/exceptions.S +index 539e196d..d3732f86 100644 +--- a/src/arch/aarch64/hypervisor/exceptions.S ++++ b/src/arch/aarch64/hypervisor/exceptions.S +@@ -20,6 +20,9 @@ + #define ID_AA64PFR0_SVE_SHIFT (32) + #define ID_AA64PFR0_SVE_LENGTH (4) + ++#define SCTLR_EL2_A_SHIFT (1) ++#define HCR_EL2_TGE_SHIFT (27) ++ + /** + * Saves the volatile registers into the register buffer of the current vCPU. + */ +@@ -51,8 +54,6 @@ + mrs x1, elr_el2 + mrs x2, spsr_el2 + stp x1, x2, [x18, #VCPU_REGS + 8 * 31] +- mrs x1, hcr_el2 +- str x1, [x18, #VCPU_REGS + 8 * 33] + .endm + + /** +@@ -871,12 +872,13 @@ vcpu_restore_volatile_and_run: + msr elr_el2, x1 + msr spsr_el2, x2 + +- ldr x1, [x0, #VCPU_REGS + 8 * 33] ++ ldp x1, x2, [x0, #VCPU_REGS + 8 * 33] + msr hcr_el2, x1 ++ msr ttbr0_el2, x2 + isb + +- ldr x1, [x0, #VCPU_REGS + 8 * 34] +- msr ttbr0_el2, x1 ++ ldr x1, [x0, #VCPU_REGS + 8 * 35] ++ msr sctlr_el2, x1 + isb + + /* Restore x0..x3, which we have used as scratch before. */ +@@ -886,15 +888,17 @@ vcpu_restore_volatile_and_run: + + #if ENABLE_VHE + enable_vhe_tge: ++ mrs x0, id_aa64mmfr1_el1 ++ tst x0, #0xf00 ++ b.eq 1f ++ + /** + * Switch to host mode ({E2H, TGE} = {1,1}) when VHE is enabled. + * Note that E2H is always set when VHE is enabled. + */ +- mrs x0, id_aa64mmfr1_el1 +- tst x0, #0xf00 +- b.eq 1f +- orr x1, x1, #(1 << 27) +- msr hcr_el2, x1 ++ mrs x0, hcr_el2 ++ orr x0, x0, #(1 << HCR_EL2_TGE_SHIFT) ++ msr hcr_el2, x0 + isb + + /** +@@ -905,6 +909,14 @@ enable_vhe_tge: + ldr x0, [x0] + msr ttbr0_el2, x0 + isb ++ ++ /** ++ * Enable alignment check while Hypervisor runs. ++ */ ++ mrs x0, sctlr_el2 ++ orr x0, x0, #(1 << SCTLR_EL2_A_SHIFT) ++ msr sctlr_el2, x0 ++ isb + 1: + ret + #endif +diff --git a/src/arch/aarch64/hypervisor/feature_id.c b/src/arch/aarch64/hypervisor/feature_id.c +index ed3bf8f1..57f32627 100644 +--- a/src/arch/aarch64/hypervisor/feature_id.c ++++ b/src/arch/aarch64/hypervisor/feature_id.c +@@ -175,7 +175,7 @@ void feature_set_traps(struct vm *vm, struct arch_regs *regs) + ~(ID_AA64MMFR1_EL1_VH_MASK << ID_AA64MMFR1_EL1_VH_SHIFT); + + if (features & HF_FEATURE_RAS) { +- regs->hcr_el2 |= HCR_EL2_TERR; ++ regs->hyp_state.hcr_el2 |= HCR_EL2_TERR; + vm->arch.tid3_masks.id_aa64mmfr1_el1 &= + ~ID_AA64MMFR1_EL1_SPEC_SEI; + vm->arch.tid3_masks.id_aa64pfr0_el1 &= ~ID_AA64PFR0_EL1_RAS; +@@ -221,14 +221,14 @@ void feature_set_traps(struct vm *vm, struct arch_regs *regs) + } + + if (features & HF_FEATURE_LOR) { +- regs->hcr_el2 |= HCR_EL2_TLOR; ++ regs->hyp_state.hcr_el2 |= HCR_EL2_TLOR; + + vm->arch.tid3_masks.id_aa64mmfr1_el1 &= ~ID_AA64MMFR1_EL1_LO; + } + + if (features & HF_FEATURE_PAUTH) { + /* APK and API bits *enable* trapping when cleared. */ +- regs->hcr_el2 &= ~(HCR_EL2_APK | HCR_EL2_API); ++ regs->hyp_state.hcr_el2 &= ~(HCR_EL2_APK | HCR_EL2_API); + + vm->arch.tid3_masks.id_aa64isar1_el1 &= ~ID_AA64ISAR1_EL1_GPI; + vm->arch.tid3_masks.id_aa64isar1_el1 &= ~ID_AA64ISAR1_EL1_GPA; +diff --git a/src/arch/aarch64/hypervisor/handler.c b/src/arch/aarch64/hypervisor/handler.c +index cd5146bd..8a3d6289 100644 +--- a/src/arch/aarch64/hypervisor/handler.c ++++ b/src/arch/aarch64/hypervisor/handler.c +@@ -272,9 +272,9 @@ noreturn void sync_current_exception_noreturn(uintreg_t elr, uintreg_t spsr) + static void set_virtual_irq(struct arch_regs *r, bool enable) + { + if (enable) { +- r->hcr_el2 |= HCR_EL2_VI; ++ r->hyp_state.hcr_el2 |= HCR_EL2_VI; + } else { +- r->hcr_el2 &= ~HCR_EL2_VI; ++ r->hyp_state.hcr_el2 &= ~HCR_EL2_VI; + } + } + +@@ -283,14 +283,15 @@ static void set_virtual_irq(struct arch_regs *r, bool enable) + */ + static void set_virtual_irq_current(bool enable) + { +- uintreg_t hcr_el2 = current()->regs.hcr_el2; ++ struct vcpu *vcpu = current(); ++ uintreg_t hcr_el2 = vcpu->regs.hyp_state.hcr_el2; + + if (enable) { + hcr_el2 |= HCR_EL2_VI; + } else { + hcr_el2 &= ~HCR_EL2_VI; + } +- current()->regs.hcr_el2 = hcr_el2; ++ vcpu->regs.hyp_state.hcr_el2 = hcr_el2; + } + + /** +@@ -300,9 +301,9 @@ static void set_virtual_irq_current(bool enable) + static void set_virtual_fiq(struct arch_regs *r, bool enable) + { + if (enable) { +- r->hcr_el2 |= HCR_EL2_VF; ++ r->hyp_state.hcr_el2 |= HCR_EL2_VF; + } else { +- r->hcr_el2 &= ~HCR_EL2_VF; ++ r->hyp_state.hcr_el2 &= ~HCR_EL2_VF; + } + } + +@@ -311,14 +312,15 @@ static void set_virtual_fiq(struct arch_regs *r, bool enable) + */ + static void set_virtual_fiq_current(bool enable) + { +- uintreg_t hcr_el2 = current()->regs.hcr_el2; ++ struct vcpu *vcpu = current(); ++ uintreg_t hcr_el2 = vcpu->regs.hyp_state.hcr_el2; + + if (enable) { + hcr_el2 |= HCR_EL2_VF; + } else { + hcr_el2 &= ~HCR_EL2_VF; + } +- current()->regs.hcr_el2 = hcr_el2; ++ vcpu->regs.hyp_state.hcr_el2 = hcr_el2; + } + + #if SECURE_WORLD == 1 +diff --git a/src/arch/aarch64/inc/hf/arch/types.h b/src/arch/aarch64/inc/hf/arch/types.h +index 6379d73e..6b8b24f1 100644 +--- a/src/arch/aarch64/inc/hf/arch/types.h ++++ b/src/arch/aarch64/inc/hf/arch/types.h +@@ -79,8 +79,13 @@ struct arch_regs { + uintreg_t r[NUM_GP_REGS]; + uintreg_t pc; + uintreg_t spsr; +- uintreg_t hcr_el2; +- uintreg_t ttbr0_el2; ++ ++ /* Hypervisor configuration while a vCPU runs. */ ++ struct { ++ uintreg_t hcr_el2; ++ uintreg_t ttbr0_el2; ++ uintreg_t sctlr_el2; ++ } hyp_state; + + /* + * System registers. +diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c +index 8ee65ca0..487ae353 100644 +--- a/src/arch/aarch64/mm.c ++++ b/src/arch/aarch64/mm.c +@@ -886,7 +886,7 @@ bool arch_mm_init(paddr_t table) + #endif + (0xff << (8 * STAGE1_NORMALINDX)), + +- .sctlr_el2 = get_sctlr_el2_value(), ++ .sctlr_el2 = get_sctlr_el2_value(false), + .vstcr_el2 = (1U << 31) | /* RES1. */ + (0 << 30) | /* SA. */ + (0 << 29) | /* SW. */ +diff --git a/src/arch/aarch64/sysregs.c b/src/arch/aarch64/sysregs.c +index e8c154b1..087ba4ed 100644 +--- a/src/arch/aarch64/sysregs.c ++++ b/src/arch/aarch64/sysregs.c +@@ -159,7 +159,7 @@ uintreg_t get_cptr_el2_value(void) + /** + * Returns the value for SCTLR_EL2 for the CPU. + */ +-uintreg_t get_sctlr_el2_value(void) ++uintreg_t get_sctlr_el2_value(bool is_el0_partition) + { + uintreg_t sctlr_el2_value = 0; + +@@ -173,7 +173,14 @@ uintreg_t get_sctlr_el2_value(void) + + /* MMU-related bits. */ + sctlr_el2_value |= SCTLR_EL2_M; +- sctlr_el2_value |= SCTLR_EL2_A; ++ ++ /* ++ * Alignment check enabled, but in the case of an EL0 partition ++ * with VHE enabled. ++ */ ++ if (!(has_vhe_support() && is_el0_partition)) { ++ sctlr_el2_value |= SCTLR_EL2_A; ++ } + sctlr_el2_value |= SCTLR_EL2_C; + sctlr_el2_value |= SCTLR_EL2_SA; + sctlr_el2_value |= SCTLR_EL2_I; +diff --git a/src/arch/aarch64/sysregs.h b/src/arch/aarch64/sysregs.h +index babd2375..6fdab58e 100644 +--- a/src/arch/aarch64/sysregs.h ++++ b/src/arch/aarch64/sysregs.h +@@ -668,7 +668,7 @@ uintreg_t get_mdcr_el2_value(void); + + uintreg_t get_cptr_el2_value(void); + +-uintreg_t get_sctlr_el2_value(void); ++uintreg_t get_sctlr_el2_value(bool is_el0_partition); + + /** + * Branch Target Identification mechanism support in AArch64 state. + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch deleted file mode 100644 index cd19f632c5..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch +++ /dev/null @@ -1,41 +0,0 @@ -From 41f3ff2f011da69ff81234769353955e51c7e588 Mon Sep 17 00:00:00 2001 -From: Davidson K -Date: Thu, 7 Oct 2021 12:20:08 +0530 -Subject: [PATCH] feat(vhe): set STAGE1_NS while mapping memory from NWd to SWd - -If the memory is shared by a VM executing in non secure world, attribute -MM_MODE_NS had to be set while mapping that in a S-EL0 SP executing in -secure world. It will not be needed for a S-EL1 SP since the NS bit is -available only for the stage 1 translations and the stage 1 translations -for a S-EL1 SP will be handled by a trusted OS running in S-EL1. - -Signed-off-by: Davidson K -Change-Id: I074e2d5a50a659bd3c097d797c4901f08d210b1b -Upstream-Status: Pending [Not submitted to upstream yet] ---- - src/ffa_memory.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/src/ffa_memory.c b/src/ffa_memory.c -index 5826cb2fdd4b..bae677633dea 100644 ---- a/src/ffa_memory.c -+++ b/src/ffa_memory.c -@@ -2618,6 +2618,18 @@ struct ffa_value ffa_memory_retrieve(struct vm_locked to_locked, - - memory_to_attributes = ffa_memory_permissions_to_mode( - permissions, share_state->sender_orig_mode); -+ -+ if (to_locked.vm->el0_partition) { -+ /* -+ * Get extra mapping attributes for the given VM ID. -+ * If the memory is shared by a VM executing in non secure -+ * world, attribute MM_MODE_NS had to be set while mapping -+ * that in a SP executing in secure world. -+ */ -+ memory_to_attributes |= arch_mm_extra_attributes_from_vm( -+ retrieve_request->sender); -+ } -+ - ret = ffa_retrieve_check_update( - to_locked, memory_region->sender, share_state->fragments, - share_state->fragment_constituent_counts, diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0004-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0004-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch new file mode 100644 index 0000000000..cfa7cfb73d --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/files/tc/0004-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch @@ -0,0 +1,41 @@ +From 4b59905d2fec01cc17038b1c167b4e57e7835adf Mon Sep 17 00:00:00 2001 +From: Davidson K +Date: Thu, 7 Oct 2021 12:20:08 +0530 +Subject: [PATCH] feat(vhe): set STAGE1_NS while mapping memory from NWd to SWd + +If the memory is shared by a VM executing in non secure world, attribute +MM_MODE_NS had to be set while mapping that in a S-EL0 SP executing in +secure world. It will not be needed for a S-EL1 SP since the NS bit is +available only for the stage 1 translations and the stage 1 translations +for a S-EL1 SP will be handled by a trusted OS running in S-EL1. + +Signed-off-by: Davidson K +Change-Id: I074e2d5a50a659bd3c097d797c4901f08d210b1b +Upstream-Status: Pending [Not submitted to upstream yet] +--- + src/ffa_memory.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/src/ffa_memory.c b/src/ffa_memory.c +index 048cca9c..8910cc79 100644 +--- a/src/ffa_memory.c ++++ b/src/ffa_memory.c +@@ -2483,6 +2483,18 @@ struct ffa_value ffa_memory_retrieve(struct vm_locked to_locked, + + memory_to_attributes = ffa_memory_permissions_to_mode( + permissions, share_state->sender_orig_mode); ++ ++ if (to_locked.vm->el0_partition) { ++ /* ++ * Get extra mapping attributes for the given VM ID. ++ * If the memory is shared by a VM executing in non secure ++ * world, attribute MM_MODE_NS had to be set while mapping ++ * that in a SP executing in secure world. ++ */ ++ memory_to_attributes |= arch_mm_extra_attributes_from_vm( ++ retrieve_request->sender); ++ } ++ + ret = ffa_retrieve_check_update( + to_locked, memory_region->sender, share_state->fragments, + share_state->fragment_constituent_counts, diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/hafnium-tc.inc b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/hafnium-tc.inc index 09de6f1e5a..433d56129e 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/hafnium-tc.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/hafnium/hafnium-tc.inc @@ -3,13 +3,21 @@ COMPATIBLE_MACHINE = "(tc?)" HAFNIUM_PLATFORM = "secure_tc" +# Intermediate SHA with 2.7 baseline version +SRCREV = "dd0561820946fe23bcd57cc129140437f72102a5" +PV = "2.7+git${SRCPV}" + FILESEXTRAPATHS:prepend:tc := "${THISDIR}/files/tc:" +SRC_URI:remove = "file://0003-Fix-build-with-clang-15.patch" + SRC_URI:append = " \ file://0001-feat-emulate-cntp-timer-register-accesses-using-cnth.patch \ file://0002-feat-emulate-interrupt-controller-register-access.patch \ - file://0003-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch \ - file://0001-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch;patchdir=project/reference \ + file://0003-feat-disable-alignment-check-for-EL0-partitions.patch \ + file://0004-feat-vhe-set-STAGE1_NS-while-mapping-memory-from-NWd.patch \ + file://0001-tc-increase-heap-pages.patch;patchdir=project/reference \ + file://0002-feat-vhe-enable-vhe-and-disable-branch-protection-fo.patch;patchdir=project/reference \ " do_compile() { diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2022.06.22.bb b/meta-arm/meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2022.06.22.bb index 1b502e5297..6a27f02ef0 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2022.06.22.bb +++ b/meta-arm/meta-arm-bsp/recipes-bsp/images/n1sdp-board-firmware_2022.06.22.bb @@ -14,7 +14,7 @@ COMPATIBLE_MACHINE = "n1sdp" SRC_URI = "git://git.gitlab.arm.com/arm-reference-solutions/board-firmware.git;protocol=https;branch=n1sdp" SRCREV = "70ba494265eee76747faff38264860c19e214540" -PV .= "+git" +PV .= "+git${SRCPV}" S = "${WORKDIR}/git" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc b/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc index 41d8f4484e..c89b132ce4 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/scp-firmware/scp-firmware-n1sdp.inc @@ -13,9 +13,6 @@ DEPENDS += "n1sdp-board-firmware" EXTRA_OECMAKE:append = " \ -DSCP_N1SDP_SENSOR_LIB_PATH=${RECIPE_SYSROOT}/n1sdp-board-firmware_source/LIB/sensor.a \ " -# scp-firmware version aligning to Arm Reference Solutions N1SDP-2023.06.22 Release -SRCREV = "543ae8ca3c9e38da3058311118fa3ceef1da47f7" -PV .= "+git" do_install:append() { fiptool \ diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Fix-FF-A-version-in-SPMC-manifest.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Fix-FF-A-version-in-SPMC-manifest.patch index 6d5114e1c1..016de8d3de 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Fix-FF-A-version-in-SPMC-manifest.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0001-Fix-FF-A-version-in-SPMC-manifest.patch @@ -1,4 +1,7 @@ -From adaa22bc2f529bb34e9d4fe89ff5c65f0c83ca0c Mon Sep 17 00:00:00 2001 +Upstream-Status: Inappropriate +Signed-off-by: Emekcan Aras + +From a31aee0988ef64724ec5866f10709f51f8cb3237 Mon Sep 17 00:00:00 2001 From: emeara01 Date: Wed, 11 May 2022 14:37:06 +0100 Subject: [PATCH] Fix FF-A version in SPMC manifest @@ -8,14 +11,13 @@ This commit corrects the FF-A version in corstone1000_spmc_manifest.dts. This patch will not be upstreamed and will be dropped once OPTEE version is updated for Corstone1000. -Upstream-Status: Inappropriate Signed-off-by: Emekcan Aras --- .../corstone1000/common/fdts/corstone1000_spmc_manifest.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts -index 8e49ab83f76a..5baa1b115b2e 100644 +index 8e49ab83f..5baa1b115 100644 --- a/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts +++ b/plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts @@ -20,7 +20,7 @@ @@ -27,3 +29,6 @@ index 8e49ab83f76a..5baa1b115b2e 100644 exec_state = <0x0>; load_address = <0x0 0x2002000>; entrypoint = <0x0 0x2002000>; +-- +2.17.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch index e26fd34e86..d834e95bd7 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch @@ -1,4 +1,4 @@ -From fa7ab9b40babee29d2aadb267dfce7a96f8989d4 Mon Sep 17 00:00:00 2001 +From 360aa32846a97e775750e06865d462c6258179fa Mon Sep 17 00:00:00 2001 From: Mohamed Omar Asaker Date: Mon, 9 Jan 2023 13:59:06 +0000 Subject: [PATCH] feat(corstone1000): bl2 loads fip based on metadata @@ -15,6 +15,7 @@ image starts at fip partition + fip signature area size. Upstream-Status: Pending Signed-off-by: Mohamed Omar Asaker + --- bl2/bl2_main.c | 4 +++ .../corstone1000/common/corstone1000_plat.c | 32 ++++++------------- @@ -24,10 +25,10 @@ Signed-off-by: Mohamed Omar Asaker 5 files changed, 24 insertions(+), 32 deletions(-) diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c -index ce83692e0ebc..1a9febc007b2 100644 +index 5da803795..f25dc3029 100644 --- a/bl2/bl2_main.c +++ b/bl2/bl2_main.c -@@ -87,6 +87,10 @@ void bl2_main(void) +@@ -86,6 +86,10 @@ void bl2_main(void) /* Perform remaining generic architectural setup in S-EL1 */ bl2_arch_setup(); @@ -39,7 +40,7 @@ index ce83692e0ebc..1a9febc007b2 100644 fwu_init(); #endif /* PSA_FWU_SUPPORT */ diff --git a/plat/arm/board/corstone1000/common/corstone1000_plat.c b/plat/arm/board/corstone1000/common/corstone1000_plat.c -index 0235f8b8474c..7f9708a82489 100644 +index 0235f8b84..7f9708a82 100644 --- a/plat/arm/board/corstone1000/common/corstone1000_plat.c +++ b/plat/arm/board/corstone1000/common/corstone1000_plat.c @@ -33,36 +33,17 @@ const mmap_region_t plat_arm_mmap[] = { @@ -97,7 +98,7 @@ index 0235f8b8474c..7f9708a82489 100644 * is no power control present */ diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h -index 584d485f3ea7..0bfab05a482b 100644 +index 584d485f3..0bfab05a4 100644 --- a/plat/arm/board/corstone1000/common/include/platform_def.h +++ b/plat/arm/board/corstone1000/common/include/platform_def.h @@ -173,16 +173,16 @@ @@ -124,10 +125,10 @@ index 584d485f3ea7..0bfab05a482b 100644 /* * Some data must be aligned on the biggest cache line size in the platform. diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile -index 042e844626bd..45b76a022f91 100644 +index ca548b836..32b5486a0 100644 --- a/tools/cert_create/Makefile +++ b/tools/cert_create/Makefile -@@ -78,8 +78,8 @@ INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include +@@ -69,8 +69,8 @@ INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include # directory. However, for a local build of OpenSSL, the built binaries are # located under the main project directory (i.e.: ${OPENSSL_DIR}, not # ${OPENSSL_DIR}/lib/). @@ -139,10 +140,10 @@ index 042e844626bd..45b76a022f91 100644 HOSTCC ?= gcc diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile -index 2ebee33931ba..dcfd314bee89 100644 +index e6aeba95b..7c047479e 100644 --- a/tools/fiptool/Makefile +++ b/tools/fiptool/Makefile -@@ -39,7 +39,7 @@ HOSTCCFLAGS += -DUSING_OPENSSL3=$(USING_OPENSSL3) +@@ -29,7 +29,7 @@ endif # directory. However, for a local build of OpenSSL, the built binaries are # located under the main project directory (i.e.: ${OPENSSL_DIR}, not # ${OPENSSL_DIR}/lib/). @@ -151,7 +152,7 @@ index 2ebee33931ba..dcfd314bee89 100644 ifeq (${V},0) Q := @ -@@ -47,7 +47,7 @@ else +@@ -37,7 +37,7 @@ else Q := endif @@ -160,3 +161,6 @@ index 2ebee33931ba..dcfd314bee89 100644 HOSTCC ?= gcc +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-add-cpuhelper-to-makefile.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-add-cpuhelper-to-makefile.patch deleted file mode 100644 index 6ddde10e4f..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/corstone1000/0004-fix-corstone1000-add-cpuhelper-to-makefile.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 33078d8ef143e8c79f06399de46dd26e1d53a220 Mon Sep 17 00:00:00 2001 -From: Gauri Sahnan -Date: Tue, 8 Aug 2023 17:16:51 +0100 -Subject: fix(corstone1000): add cpuhelpers to makefile - -Adds cpu_helpers.S to the Makefile to align with the changes in new -trusted-firmware-a version. - -Signed-off-by: Gauri Sahnan -Upstream-Status: Pending [Not submitted to upstream yet] ---- - plat/arm/board/corstone1000/platform.mk | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/plat/arm/board/corstone1000/platform.mk b/plat/arm/board/corstone1000/platform.mk -index 3edffe087..079e9d6c1 100644 ---- a/plat/arm/board/corstone1000/platform.mk -+++ b/plat/arm/board/corstone1000/platform.mk -@@ -43,6 +43,7 @@ BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \ - plat/arm/board/corstone1000/common/corstone1000_err.c \ - plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \ - lib/utils/mem_region.c \ -+ lib/cpus/aarch64/cpu_helpers.S \ - plat/arm/board/corstone1000/common/corstone1000_helpers.S \ - plat/arm/board/corstone1000/common/corstone1000_plat.c \ - plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \ --- -2.25.1 diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/rwx-segments.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/rwx-segments.patch deleted file mode 100644 index a4518ec6b0..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/rwx-segments.patch +++ /dev/null @@ -1,38 +0,0 @@ -Binutils 2.39 now warns when a segment has RXW permissions[1]: - -aarch64-none-elf-ld.bfd: warning: bl31.elf has a LOAD segment with RWX -permissions - -However, TF-A passes --fatal-warnings to LD, so this is a build failure. - -There is a ticket filed upstream[2], so until that is resolved just -remove --fatal-warnings. - -[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107 -[2] https://developer.trustedfirmware.org/T996 - -Upstream-Status: Inappropriate -Signed-off-by: Ross Burton - -diff --git a/Makefile b/Makefile -index 3941f8698..13bbac348 100644 ---- a/Makefile -+++ b/Makefile -@@ -418,7 +418,7 @@ TF_LDFLAGS += $(TF_LDFLAGS_$(ARCH)) - # LD = gcc (used when GCC LTO is enabled) - else ifneq ($(findstring gcc,$(notdir $(LD))),) - # Pass ld options with Wl or Xlinker switches --TF_LDFLAGS += -Wl,--fatal-warnings -O1 -+TF_LDFLAGS += -O1 - TF_LDFLAGS += -Wl,--gc-sections - ifeq ($(ENABLE_LTO),1) - ifeq (${ARCH},aarch64) -@@ -435,7 +435,7 @@ TF_LDFLAGS += $(subst --,-Xlinker --,$(TF_LDFLAGS_$(ARCH))) - - # LD = gcc-ld (ld) or llvm-ld (ld.lld) or other - else --TF_LDFLAGS += --fatal-warnings -O1 -+TF_LDFLAGS += -O1 - TF_LDFLAGS += --gc-sections - # ld.lld doesn't recognize the errata flags, - # therefore don't add those in that case diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tf-a-tests-no-warn-rwx-segments.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tf-a-tests-no-warn-rwx-segments.patch deleted file mode 100644 index 5d02e35317..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/files/tf-a-tests-no-warn-rwx-segments.patch +++ /dev/null @@ -1,26 +0,0 @@ -Binutils 2.39 now warns when a segment has RXW permissions[1]: - -aarch64-poky-linux-musl-ld: tftf.elf has a LOAD segment with RWX permissions - -There is a ticket filed upstream[2], so until that is resolved just -disable the warning - -[1] https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ba951afb99912da01a6e8434126b8fac7aa75107 -[2] https://developer.trustedfirmware.org/T996 - -Upstream-Status: Inappropriate -Signed-off-by: Anton Antonov - -diff --git a/Makefile b/Makefile -index 6d0774e1..be3f84ce 100644 ---- a/Makefile -+++ b/Makefile -@@ -238,7 +238,7 @@ TFTF_SOURCES := ${FRAMEWORK_SOURCES} ${TESTS_SOURCES} ${PLAT_SOURCES} ${LIBC_SR - TFTF_INCLUDES += ${PLAT_INCLUDES} - TFTF_CFLAGS += ${COMMON_CFLAGS} - TFTF_ASFLAGS += ${COMMON_ASFLAGS} --TFTF_LDFLAGS += ${COMMON_LDFLAGS} -+TFTF_LDFLAGS += ${COMMON_LDFLAGS} --no-warn-rwx-segments - TFTF_EXTRA_OBJS := - - ifneq (${BP_OPTION},none) diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/fiptool-native_2.8.6.bb b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/fiptool-native_2.8.6.bb deleted file mode 100644 index 02f3387396..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/fiptool-native_2.8.6.bb +++ /dev/null @@ -1,33 +0,0 @@ -# Firmware Image Package (FIP) -# It is a packaging format used by TF-A to package the -# firmware images in a single binary. - -DESCRIPTION = "fiptool - Trusted Firmware tool for packaging" -LICENSE = "BSD-3-Clause" - -SRC_URI_TRUSTED_FIRMWARE_A ?= "git://git.trustedfirmware.org/TF-A/trusted-firmware-a.git;protocol=https" -SRC_URI = "${SRC_URI_TRUSTED_FIRMWARE_A};destsuffix=fiptool-${PV};branch=${SRCBRANCH}" -LIC_FILES_CHKSUM = "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde" - -# Use fiptool from TF-A v2.8.6 -SRCREV = "ff0bd5f9bb2ba2f31fb9cec96df917747af9e92d" -SRCBRANCH = "lts-v2.8" - -DEPENDS += "openssl-native" - -inherit native - -EXTRA_OEMAKE = "V=1 HOSTCC='${BUILD_CC}' OPENSSL_DIR=${STAGING_DIR_NATIVE}/${prefix_native}" - -do_compile () { - # This is still needed to have the native fiptool executing properly by - # setting the RPATH - sed -i '/^LDLIBS/ s,$, \$\{BUILD_LDFLAGS},' ${S}/tools/fiptool/Makefile - sed -i '/^INCLUDE_PATHS/ s,$, \$\{BUILD_CFLAGS},' ${S}/tools/fiptool/Makefile - - oe_runmake fiptool -} - -do_install () { - install -D -p -m 0755 tools/fiptool/fiptool ${D}${bindir}/fiptool -} diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend deleted file mode 100644 index 392c6090e1..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_%.bbappend +++ /dev/null @@ -1,4 +0,0 @@ -# Machine specific TFAs - -COMPATIBLE_MACHINE:corstone1000 = "corstone1000" -SRCREV:corstone1000 = "5f591f67738a1bbe6b262c53d9dad46ed8bbcd67" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb deleted file mode 100644 index ed3b349950..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bb +++ /dev/null @@ -1,54 +0,0 @@ -DESCRIPTION = "Trusted Firmware-A tests(aka TFTF)" -LICENSE = "BSD-3-Clause & NCSA" - -LIC_FILES_CHKSUM += "file://docs/license.rst;md5=6175cc0aa2e63b6d21a32aa0ee7d1b4a" - -inherit deploy - -COMPATIBLE_MACHINE ?= "invalid" - -SRC_URI_TRUSTED_FIRMWARE_A_TESTS ?= "git://git.trustedfirmware.org/TF-A/tf-a-tests.git;protocol=https" -SRC_URI = "${SRC_URI_TRUSTED_FIRMWARE_A_TESTS};branch=${SRCBRANCH} \ - file://tf-a-tests-no-warn-rwx-segments.patch" -SRCBRANCH = "lts-v2.8" -SRCREV = "85442d2943440718c2c2c9c5c690202b4b4f5725" - -DEPENDS += "optee-os" - -EXTRA_OEMAKE += "USE_NVM=0" -EXTRA_OEMAKE += "SHELL_COLOR=1" -EXTRA_OEMAKE += "DEBUG=1" - -# Platform must be set for each machine -TFA_PLATFORM ?= "invalid" - -EXTRA_OEMAKE += "ARCH=aarch64" -EXTRA_OEMAKE += "LOG_LEVEL=50" - -S = "${WORKDIR}/git" -B = "${WORKDIR}/build" - -# Add platform parameter -EXTRA_OEMAKE += "BUILD_BASE=${B} PLAT=${TFA_PLATFORM}" - -# Requires CROSS_COMPILE set by hand as there is no configure script -export CROSS_COMPILE="${TARGET_PREFIX}" - -do_compile() { - oe_runmake -C ${S} tftf -} - -do_compile[cleandirs] = "${B}" - -FILES:${PN} = "/firmware/tftf.bin" -SYSROOT_DIRS += "/firmware" - -do_install() { - install -d -m 755 ${D}/firmware - install -m 0644 ${B}/${TFA_PLATFORM}/debug/tftf.bin ${D}/firmware/tftf.bin -} - -do_deploy() { - cp -rf ${D}/firmware/* ${DEPLOYDIR}/ -} -addtask deploy after do_install diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bbappend new file mode 100644 index 0000000000..392c6090e1 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/tf-a-tests_2.8.0.bbappend @@ -0,0 +1,4 @@ +# Machine specific TFAs + +COMPATIBLE_MACHINE:corstone1000 = "corstone1000" +SRCREV:corstone1000 = "5f591f67738a1bbe6b262c53d9dad46ed8bbcd67" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc index 3f66bed55a..06be28ee62 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone1000.inc @@ -3,12 +3,16 @@ COMPATIBLE_MACHINE = "(corstone1000)" FILESEXTRAPATHS:prepend := "${THISDIR}/files/corstone1000:" -SRC_URI:append = " \ + +SRC_URI:append = " \ file://0001-Fix-FF-A-version-in-SPMC-manifest.patch \ - file://0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch \ - file://0003-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \ - file://0004-fix-corstone1000-add-cpuhelper-to-makefile.patch \ - " + file://0002-feat-corstone1000-bl2-loads-fip-based-on-metadata.patch \ + file://0003-psci-SMCCC_ARCH_FEATURES-discovery-through-PSCI_FEATURES.patch \ + " + +#Sets TF-A version to 2.8.0 +SRCREV_tfa = "9881bb93a3bc0a3ea37e9f093e09ab4b360a9e48" +PV = "2.8.0" TFA_DEBUG = "1" TFA_UBOOT ?= "1" @@ -29,7 +33,7 @@ EXTRA_OEMAKE:append = " \ TARGET_PLATFORM=${TFA_TARGET_PLATFORM} \ ENABLE_STACK_PROTECTOR=strong \ ENABLE_PIE=1 \ - RESET_TO_BL2=1 \ + BL2_AT_EL3=1 \ CREATE_KEYS=1 \ GENERATE_COT=1 \ TRUSTED_BOARD_BOOT=1 \ diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone500.inc b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone500.inc new file mode 100644 index 0000000000..acd9e3dbfb --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-corstone500.inc @@ -0,0 +1,17 @@ +# Corstone-500 specific TFA support + +COMPATIBLE_MACHINE = "corstone500" +TFA_PLATFORM = "a5ds" +TFA_DEBUG = "1" +TFA_UBOOT = "1" +TFA_BUILD_TARGET = "all fip" +TFA_INSTALL_TARGET = "bl1.bin fip.bin" + +EXTRA_OEMAKE:append = " \ + ARCH=aarch32 \ + FVP_HW_CONFIG_DTS=fdts/a5ds.dts \ + ARM_ARCH_MAJOR=7 \ + AARCH32_SP=sp_min \ + ARM_CORTEX_A5=yes \ + ARM_XLAT_TABLES_LIB_V1=1 \ + " diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc index c2fa223cf5..654e43270f 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a-n1sdp.inc @@ -1,9 +1,5 @@ # N1SDP specific TFA support -# Align with N1SDP-2023.06.22 Manifest -SRCREV_tfa = "31f60a968347497562b0129134928d7ac4767710" -PV .= "+git" - COMPATIBLE_MACHINE = "n1sdp" TFA_PLATFORM = "n1sdp" TFA_BUILD_TARGET = "all fip" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend deleted file mode 100644 index 7fbcd3aba0..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_%.bbappend +++ /dev/null @@ -1,13 +0,0 @@ -FILESEXTRAPATHS:prepend := "${THISDIR}/files/:" - -# Machine specific TFAs - -MACHINE_TFA_REQUIRE ?= "" -MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc" -MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc" -MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc" -MACHINE_TFA_REQUIRE:n1sdp = "trusted-firmware-a-n1sdp.inc" -MACHINE_TFA_REQUIRE:sgi575 = "trusted-firmware-a-sgi575.inc" -MACHINE_TFA_REQUIRE:tc = "trusted-firmware-a-tc.inc" - -require ${MACHINE_TFA_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.%.bbappend new file mode 100644 index 0000000000..220dd6e33e --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.%.bbappend @@ -0,0 +1,14 @@ +FILESEXTRAPATHS:prepend := "${THISDIR}/files/:" + +# Machine specific TFAs + +MACHINE_TFA_REQUIRE ?= "" +MACHINE_TFA_REQUIRE:corstone500 = "trusted-firmware-a-corstone500.inc" +MACHINE_TFA_REQUIRE:corstone1000 = "trusted-firmware-a-corstone1000.inc" +MACHINE_TFA_REQUIRE:fvp-base = "trusted-firmware-a-fvp.inc" +MACHINE_TFA_REQUIRE:juno = "trusted-firmware-a-juno.inc" +MACHINE_TFA_REQUIRE:n1sdp = "trusted-firmware-a-n1sdp.inc" +MACHINE_TFA_REQUIRE:sgi575 = "trusted-firmware-a-sgi575.inc" +MACHINE_TFA_REQUIRE:tc = "trusted-firmware-a-tc.inc" + +require ${MACHINE_TFA_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.6.bb b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.6.bb deleted file mode 100644 index cffc6db17c..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-a/trusted-firmware-a_2.8.6.bb +++ /dev/null @@ -1,15 +0,0 @@ -require recipes-bsp/trusted-firmware-a/trusted-firmware-a.inc - -# TF-A v2.8.6 -SRCREV_tfa = "ff0bd5f9bb2ba2f31fb9cec96df917747af9e92d" -SRCBRANCH = "lts-v2.8" - -SRC_URI += "file://rwx-segments.patch" - -LIC_FILES_CHKSUM += "file://docs/license.rst;md5=b2c740efedc159745b9b31f88ff03dde" - -# mbed TLS v2.28.2 -SRC_URI_MBEDTLS = "git://github.com/ARMmbed/mbedtls.git;name=mbedtls;protocol=https;destsuffix=git/mbedtls;branch=mbedtls-2.28" -SRCREV_mbedtls = "89f040a5c938985c5f30728baed21e49d0846a53" - -LIC_FILES_CHKSUM_MBEDTLS = "file://mbedtls/LICENSE;md5=3b83ef96387f14655fc854ddc3c6bd57" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-Platform-corstone1000-add-unique-firmware-GUID.patch b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-Platform-corstone1000-add-unique-firmware-GUID.patch deleted file mode 100644 index 2f5ba04b42..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/files/corstone1000/0005-Platform-corstone1000-add-unique-firmware-GUID.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 3004fda909079ebebd62c495a4e49e64d6c8a85f Mon Sep 17 00:00:00 2001 -From: Anusmita Dutta Mazumder -Date: Tue, 8 Aug 2023 10:58:01 +0000 -Subject: [PATCH] Platform corstone1000 add unique firmware GUID - -Add unique Corstone-1000 firmware GUID - -Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Anusmita Dutta Mazumder ---- - .../target/arm/corstone1000/fw_update_agent/fwu_agent.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c -index f564f2902c..9c31aeee9d 100644 ---- a/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c -+++ b/platform/ext/target/arm/corstone1000/fw_update_agent/fwu_agent.c -@@ -113,10 +113,10 @@ enum fwu_agent_state_t { - }; - - struct efi_guid full_capsule_image_guid = { -- .time_low = 0xe2bb9c06, -- .time_mid = 0x70e9, -- .time_hi_and_version = 0x4b14, -- .clock_seq_and_node = {0x97, 0xa3, 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f} -+ .time_low = 0x989f3a4e, -+ .time_mid = 0x46e0, -+ .time_hi_and_version = 0x4cd0, -+ .clock_seq_and_node = {0x98, 0x77, 0xa2, 0x5c, 0x70, 0xc0, 0x13, 0x29} - }; - - --- -2.38.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc index a259390a52..0831ed0e9b 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/trusted-firmware-m/trusted-firmware-m-corstone1000.inc @@ -32,7 +32,6 @@ SRC_URI:append:corstone1000 = " \ file://0002-Platform-Corstone1000-Increase-BL2_DATA_SIZE.patch \ file://0003-Platform-Corstone1000-Calculate-the-new-CRC32-value-.patch \ file://0004-arm-trusted-firmware-m-disable-fatal-warnings.patch \ - file://0005-Platform-corstone1000-add-unique-firmware-GUID.patch \ " # TF-M ships patches for external dependencies that needs to be applied diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch new file mode 100644 index 0000000000..63c42c70b7 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-Increase-the-unzipped-Kernel-size.patch @@ -0,0 +1,29 @@ +From df23489adcba1cdcbcb4fefbed0896fc1f408700 Mon Sep 17 00:00:00 2001 +From: Emekcan Aras +Date: Wed, 2 Aug 2023 17:07:05 +0100 +Subject: [PATCH] Increase the unzipped Kernel size + +Increases the unzipped kernel size for corstone1000. + +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Emekcan Aras +--- + configs/corstone1000_defconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig +index a0af413de8..54a5bca354 100644 +--- a/configs/corstone1000_defconfig ++++ b/configs/corstone1000_defconfig +@@ -15,7 +15,7 @@ CONFIG_DISTRO_DEFAULTS=y + CONFIG_BOOTDELAY=3 + CONFIG_USE_BOOTARGS=y + CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" +-CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" ++CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xfb0000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" + CONFIG_CONSOLE_RECORD=y + CONFIG_LOGLEVEL=7 + # CONFIG_DISPLAY_CPUINFO is not set +-- +2.17.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch deleted file mode 100644 index 9fd5b33b70..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0033-corstone1000-detect-inflated-kernel-size.patch +++ /dev/null @@ -1,29 +0,0 @@ -From b57e05e95735b9b58e81b7a67f483b645c56811e Mon Sep 17 00:00:00 2001 -From: Abdellatif El Khlifi -Date: Fri, 11 Aug 2023 10:41:19 +0100 -Subject: [PATCH] corstone1000: detect inflated kernel size - -use filesize variable set by unzip command - -Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Abdellatif El Khlifi ---- - configs/corstone1000_defconfig | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig -index b6b1ccdd78..8a10bca069 100644 ---- a/configs/corstone1000_defconfig -+++ b/configs/corstone1000_defconfig -@@ -17,7 +17,7 @@ CONFIG_FIT=y - CONFIG_BOOTDELAY=3 - CONFIG_USE_BOOTARGS=y - CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" --CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r 0xf00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" -+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; unzip $kernel_addr 0x90000000; loadm 0x90000000 $kernel_addr_r $filesize; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" - CONFIG_CONSOLE_RECORD=y - CONFIG_LOGLEVEL=7 - # CONFIG_DISPLAY_CPUINFO is not set --- -2.25.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch deleted file mode 100644 index 197a06950a..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone1000/0034-corstone1000-ESRT-add-unique-firmware-GUID.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 98b33cc6b3a56f56224e0a6fe6c3564de7b1341a Mon Sep 17 00:00:00 2001 -From: Anusmita Dutta Mazumder -Date: Tue, 8 Aug 2023 10:24:39 +0000 -Subject: [PATCH] corstone1000: ESRT: add unique firmware GUID - -Add unique Corstone-1000 firmware GUID - -Upstream-Status: Pending [Not submitted to upstream yet] -Signed-off-by: Anusmita Dutta Mazumder ---- - lib/efi_loader/efi_firmware.c | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c -index 6135f8ed1c..c9117ae2b2 100644 ---- a/lib/efi_loader/efi_firmware.c -+++ b/lib/efi_loader/efi_firmware.c -@@ -20,12 +20,12 @@ - #define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1') - - #if CONFIG_IS_ENABLED(TARGET_CORSTONE1000) --#define EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID \ -- EFI_GUID(0xe2bb9c06, 0x70e9, 0x4b14, 0x97, 0xa3, \ -- 0x5a, 0x79, 0x13, 0x17, 0x6e, 0x3f) -+/* Firmware GUID */ -+#define EFI_CORSTONE1000_FIRMWARE_GUID \ -+ EFI_GUID(0x989f3a4e, 0x46e0, 0x4cd0, 0x98, 0x77, \ -+ 0xa2, 0x5c, 0x70, 0xc0, 0x13, 0x29) - -- const efi_guid_t efi_firmware_image_type_uboot_raw = -- EFI_FIRMWARE_IMAGE_TYPE_UBOOT_RAW_GUID; -+efi_guid_t corstone1000_firmware_guid = EFI_CORSTONE1000_FIRMWARE_GUID; - - static efi_status_t efi_corstone1000_img_info_get ( - efi_uintn_t *image_info_size, -@@ -353,7 +353,7 @@ efi_status_t EFIAPI efi_firmware_get_image_info( - descriptor_version, descriptor_count, - descriptor_size, - package_version, package_version_name, -- &efi_firmware_image_type_uboot_raw); -+ &corstone1000_firmware_guid); - #else - ret = efi_fill_image_desc_array(image_info_size, image_info, - descriptor_version, descriptor_count, --- -2.38.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch new file mode 100644 index 0000000000..1d28631a21 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0001-armv7-adding-generic-timer-access-through-MMIO.patch @@ -0,0 +1,139 @@ +From 2bb9fb8414b8ad35ed5fc6c91a34c21cef285a01 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Wed, 18 Dec 2019 21:52:34 +0000 +Subject: [PATCH 1/2] armv7: adding generic timer access through MMIO + +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Abdellatif El Khlifi + +This driver enables the ARMv7 generic timer. + +The access to the timer registers is through memory mapping (MMIO). + +This driver can be used by u-boot to access to the timer through MMIO +when arch_timer is not available in the core (access using system +instructions not possible), for example, in case of Cortex-A5. + +This driver configures and enables the generic timer at +the u-boot initcall level (timer_init) before u-boot relocation. + +Signed-off-by: Rui Miguel Silva +Signed-off-by: Abdellatif El Khlifi + + +Signed-off-by: Rui Miguel Silva +--- + arch/arm/cpu/armv7/Makefile | 1 + + arch/arm/cpu/armv7/mmio_timer.c | 75 +++++++++++++++++++++++++++++++++ + scripts/config_whitelist.txt | 1 + + 3 files changed, 77 insertions(+) + create mode 100644 arch/arm/cpu/armv7/mmio_timer.c + +diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile +index bfbd85ae64ef..1a0a24e53110 100644 +--- a/arch/arm/cpu/armv7/Makefile ++++ b/arch/arm/cpu/armv7/Makefile +@@ -28,6 +28,7 @@ obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o + obj-$(CONFIG_IPROC) += iproc-common/ + obj-$(CONFIG_KONA) += kona-common/ + obj-$(CONFIG_SYS_ARCH_TIMER) += arch_timer.o ++obj-$(CONFIG_SYS_MMIO_TIMER) += mmio_timer.o + + ifneq (,$(filter s5pc1xx exynos,$(SOC))) + obj-y += s5p-common/ +diff --git a/arch/arm/cpu/armv7/mmio_timer.c b/arch/arm/cpu/armv7/mmio_timer.c +new file mode 100644 +index 000000000000..edd806e06e42 +--- /dev/null ++++ b/arch/arm/cpu/armv7/mmio_timer.c +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (c) 2019, Arm Limited. All rights reserved. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++#define CNTCTLBASE 0x1a020000UL ++#define CNTREADBASE 0x1a030000UL ++#define CNTEN (1 << 0) ++#define CNTFCREQ (1 << 8) ++ ++static inline uint32_t mmio_read32(uintptr_t addr) ++{ ++ return *(volatile uint32_t*)addr; ++} ++ ++static inline void mmio_write32(uintptr_t addr, uint32_t data) ++{ ++ *(volatile uint32_t*)addr = data; ++} ++ ++int timer_init(void) ++{ ++ /* calculate the frequency in ms */ ++ gd->arch.timer_rate_hz = COUNTER_FREQUENCY / CONFIG_SYS_HZ; ++ ++ /* configure CNTFID0 register: set the base frequency */ ++ mmio_write32(CNTCTLBASE + 0x20, COUNTER_FREQUENCY); ++ ++ /* ++ * configure CNTCR register: ++ * enable the generic counter and; ++ * select the first frequency entry ++ */ ++ mmio_write32(CNTCTLBASE, CNTFCREQ | CNTEN); ++ ++ return 0; ++} ++ ++unsigned long long get_ticks(void) ++{ ++ return (((u64)(mmio_read32(CNTREADBASE + 0x4)) << 32) | ++ mmio_read32(CNTREADBASE)); ++} ++ ++ulong get_timer(ulong base) ++{ ++ return lldiv(get_ticks(), gd->arch.timer_rate_hz) - base; ++} ++ ++void __udelay(unsigned long usec) ++{ ++ unsigned long endtime; ++ ++ endtime = lldiv((unsigned long long)usec * gd->arch.timer_rate_hz, ++ 1000UL); ++ ++ endtime += get_ticks(); ++ ++ while (get_ticks() < endtime) ++ ; ++} ++ ++ulong get_tbclk(void) ++{ ++ return gd->arch.timer_rate_hz; ++} +diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt +index ea71f9d23449..1496d9b88233 100644 +--- a/scripts/config_whitelist.txt ++++ b/scripts/config_whitelist.txt +@@ -610,6 +610,7 @@ CONFIG_SYS_MMC_U_BOOT_DST + CONFIG_SYS_MMC_U_BOOT_OFFS + CONFIG_SYS_MMC_U_BOOT_SIZE + CONFIG_SYS_MMC_U_BOOT_START ++CONFIG_SYS_MMIO_TIMER + CONFIG_SYS_MOR_VAL + CONFIG_SYS_MRAM_BASE + CONFIG_SYS_NAND_AMASK +-- +2.39.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch new file mode 100644 index 0000000000..5aec24cc47 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/corstone500/0002-board-arm-add-corstone500-board.patch @@ -0,0 +1,299 @@ +From 376e7cc533e27f943191d44c112e3812885b8fd1 Mon Sep 17 00:00:00 2001 +From: Rui Miguel Silva +Date: Wed, 8 Jan 2020 09:48:11 +0000 +Subject: [PATCH 2/2] board: arm: add corstone500 board + +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Abdellatif El Khlifi + +Add support for the Arm corstone500 platform, with a cortex-a5 +chip, add the default configuration, initialization and +makefile for this system. + +Signed-off-by: Rui Miguel Silva +--- + arch/arm/Kconfig | 10 +++ + board/armltd/corstone500/Kconfig | 12 +++ + board/armltd/corstone500/Makefile | 8 ++ + board/armltd/corstone500/corstone500.c | 48 ++++++++++++ + configs/corstone500_defconfig | 41 ++++++++++ + include/configs/corstone500.h | 102 +++++++++++++++++++++++++ + 6 files changed, 221 insertions(+) + create mode 100644 board/armltd/corstone500/Kconfig + create mode 100644 board/armltd/corstone500/Makefile + create mode 100644 board/armltd/corstone500/corstone500.c + create mode 100644 configs/corstone500_defconfig + create mode 100644 include/configs/corstone500.h + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index cac4fa09fd32..b875c1ef3d32 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -1309,6 +1309,15 @@ config TARGET_CORSTONE1000 + select PL01X_SERIAL + select DM + ++config TARGET_CORSTONE500 ++ bool "Support Corstone500" ++ select CPU_V7A ++ select SEMIHOSTING ++ select PL01X_SERIAL ++ help ++ This enables support for Corstone500 ARM which is a ++ Cortex-A5 system ++ + config TARGET_TOTAL_COMPUTE + bool "Support Total Compute Platform" + select ARM64 +@@ -2264,6 +2273,7 @@ source "board/bosch/shc/Kconfig" + source "board/bosch/guardian/Kconfig" + source "board/Marvell/octeontx/Kconfig" + source "board/Marvell/octeontx2/Kconfig" ++source "board/armltd/corstone500/Kconfig" + source "board/armltd/vexpress/Kconfig" + source "board/armltd/vexpress64/Kconfig" + source "board/cortina/presidio-asic/Kconfig" +diff --git a/board/armltd/corstone500/Kconfig b/board/armltd/corstone500/Kconfig +new file mode 100644 +index 000000000000..8e689bd1fdc8 +--- /dev/null ++++ b/board/armltd/corstone500/Kconfig +@@ -0,0 +1,12 @@ ++if TARGET_CORSTONE500 ++ ++config SYS_BOARD ++ default "corstone500" ++ ++config SYS_VENDOR ++ default "armltd" ++ ++config SYS_CONFIG_NAME ++ default "corstone500" ++ ++endif +diff --git a/board/armltd/corstone500/Makefile b/board/armltd/corstone500/Makefile +new file mode 100644 +index 000000000000..6598fdd3ae0d +--- /dev/null ++++ b/board/armltd/corstone500/Makefile +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++# ++# (C) Copyright 2022 ARM Limited ++# (C) Copyright 2022 Linaro ++# Rui Miguel Silva ++# ++ ++obj-y := corstone500.o +diff --git a/board/armltd/corstone500/corstone500.c b/board/armltd/corstone500/corstone500.c +new file mode 100644 +index 000000000000..e878f5c6a521 +--- /dev/null ++++ b/board/armltd/corstone500/corstone500.c +@@ -0,0 +1,48 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * (C) Copyright 2022 Linaro ++ * Rui Miguel Silva ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++static const struct pl01x_serial_plat serial_platdata = { ++ .base = V2M_UART0, ++ .type = TYPE_PL011, ++ .clock = CONFIG_PL011_CLOCK, ++}; ++ ++U_BOOT_DRVINFO(corstone500_serials) = { ++ .name = "serial_pl01x", ++ .plat = &serial_platdata, ++}; ++ ++int board_init(void) ++{ ++ return 0; ++} ++ ++int dram_init(void) ++{ ++ gd->ram_size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++int dram_init_banksize(void) ++{ ++ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; ++ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; ++ ++ return 0; ++} ++ ++void reset_cpu(ulong addr) ++{ ++} ++ +diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig +new file mode 100644 +index 000000000000..91661beb8d8d +--- /dev/null ++++ b/configs/corstone500_defconfig +@@ -0,0 +1,41 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_TARGET_CORSTONE500=y ++CONFIG_TEXT_BASE=0x88000000 ++CONFIG_SYS_MALLOC_LEN=0x840000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_SYS_PROMPT="corstone500# " ++CONFIG_IDENT_STRING=" corstone500 aarch32" ++CONFIG_SYS_LOAD_ADDR=0x90000000 ++CONFIG_SYS_MEMTEST_START=0x80000000 ++CONFIG_SYS_MEMTEST_END=0xff000000 ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000 ++CONFIG_SUPPORT_RAW_INITRD=y ++CONFIG_BOOTDELAY=1 ++CONFIG_USE_BOOTARGS=y ++CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9" ++# CONFIG_DISPLAY_CPUINFO is not set ++# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_HUSH_PARSER=y ++# CONFIG_CMD_CONSOLE is not set ++CONFIG_CMD_BOOTZ=y ++# CONFIG_CMD_XIMG is not set ++# CONFIG_CMD_EDITENV is not set ++# CONFIG_CMD_ENV_EXISTS is not set ++CONFIG_CMD_MEMTEST=y ++CONFIG_CMD_ARMFLASH=y ++# CONFIG_CMD_LOADS is not set ++# CONFIG_CMD_ITEST is not set ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_DHCP=y ++# CONFIG_CMD_NFS is not set ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_FAT=y ++CONFIG_DM=y ++CONFIG_MTD_NOR_FLASH=y ++CONFIG_DM_SERIAL=y ++CONFIG_OF_LIBFDT=y +diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h +new file mode 100644 +index 000000000000..416f5fa4399d +--- /dev/null ++++ b/include/configs/corstone500.h +@@ -0,0 +1,102 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * (C) Copyright 2022 ARM Limited ++ * (C) Copyright 2022 Linaro ++ * Rui Miguel Silva ++ * ++ * Configuration for Cortex-A5 Corstone500. Parts were derived from other ARM ++ * configurations. ++ */ ++ ++#ifndef __CORSTONE500_H ++#define __CORSTONE500_H ++ ++/* Generic Timer Definitions */ ++#define CONFIG_SYS_HZ_CLOCK 7500000 ++#define CONFIG_SYS_HZ 1000 ++#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK ++ ++#ifdef CONFIG_CORSTONE500_MEMORY_MAP_EXTENDED ++#define V2M_SRAM0 0x00010000 ++#define V2M_SRAM1 0x02200000 ++#define V2M_QSPI 0x0a800000 ++#else ++#define V2M_SRAM0 0x00000000 ++#define V2M_SRAM1 0x02000000 ++#define V2M_QSPI 0x08000000 ++#endif ++ ++#define V2M_DEBUG 0x10000000 ++#define V2M_BASE_PERIPH 0x1a000000 ++#define V2M_A5_PERIPH 0x1c000000 ++#define V2M_L2CC_PERIPH 0x1c010000 ++ ++#define V2M_MASTER_EXPANSION0 0x40000000 ++#define V2M_MASTER_EXPANSION1 0x60000000 ++ ++#define V2M_BASE 0x80000000 ++ ++#define V2M_PERIPH_OFFSET(x) (x << 16) ++ ++#define V2M_SYSID (V2M_BASE_PERIPH) ++#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1)) ++#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2)) ++#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3)) ++#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4)) ++#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5)) ++ ++#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16)) ++#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17)) ++ ++#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32)) ++#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33)) ++ ++#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34)) ++#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35)) ++ ++/* PL011 Serial Configuration */ ++#define CONFIG_CONS_INDEX 0 ++#define CONFIG_PL011_CLOCK 7500000 ++ ++/* Physical Memory Map */ ++#define PHYS_SDRAM_1 (V2M_BASE) ++ ++/* Top 16MB reserved for secure world use */ ++#define DRAM_SEC_SIZE 0x01000000 ++#define PHYS_SDRAM_1_SIZE (0x80000000 - DRAM_SEC_SIZE) ++ ++/* Miscellaneous configurable options */ ++#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 ++ ++#define CONFIG_SYS_MMIO_TIMER ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "kernel_name=Image\0" \ ++ "kernel_addr=0x80f00000\0" \ ++ "initrd_name=ramdisk.img\0" \ ++ "initrd_addr=0x84000000\0" \ ++ "fdt_name=devtree.dtb\0" \ ++ "fdt_addr=0x83000000\0" \ ++ "fdt_high=0xffffffff\0" \ ++ "initrd_high=0xffffffff\0" ++ ++#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \ ++ "cp.b 0x80100000 $kernel_addr 0xb00000; " \ ++ "cp.b 0x80d00000 $initrd_addr 0x800000; " \ ++ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr" ++ ++/* Monitor Command Prompt */ ++#define CONFIG_SYS_FLASH_BASE 0x80000000 ++/* Store environment at top of flash */ ++#define CONFIG_ENV_ADDR 0x0a7c0000 ++#define CONFIG_ENV_SECT_SIZE 0x0040000 ++ ++#define CONFIG_SYS_FLASH_CFI 1 ++#define CONFIG_FLASH_CFI_DRIVER 1 ++#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++ ++#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ ++#define FLASH_MAX_SECTOR_SI 0x00040000 ++#define CONFIG_ENV_IS_IN_FLASH 1 ++#endif +-- +2.39.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch index 45db74e133..dd6b77d3a5 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0001-armv8-Add-ARMv8-MPU-configuration-logic.patch @@ -1,7 +1,7 @@ -From 401a88bf6019941d4095476de76af5893686d6f6 Mon Sep 17 00:00:00 2001 +From e90aa7853ae32cb03c86249a6c572ec88cdebaa2 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Wed, 26 May 2021 17:41:10 +0100 -Subject: [PATCH] armv8: Add ARMv8 MPU configuration logic +Subject: [PATCH 1/9] armv8: Add ARMv8 MPU configuration logic Detect whether an MMU is present at the current exception level. If not, initialize the MPU instead of the MMU during init, and clear the @@ -19,7 +19,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17 - --- arch/arm/cpu/armv8/cache_v8.c | 101 ++++++++++++++++++++++++++++++- arch/arm/include/asm/armv8/mpu.h | 59 ++++++++++++++++++ @@ -28,7 +27,7 @@ Change-Id: I0ee3879f9d7f03fe940664b3551c68eeaa458d17 create mode 100644 arch/arm/include/asm/armv8/mpu.h diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c -index 2a226fd063..8611a35eb3 100644 +index e4736e5643..798aed8058 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -15,6 +15,7 @@ @@ -146,8 +145,8 @@ index 2a226fd063..8611a35eb3 100644 + } } - /* Set up page tables only once (it is done also by mmu_setup()) */ -@@ -523,7 +614,11 @@ void dcache_disable(void) + set_sctlr(get_sctlr() | CR_C); +@@ -519,7 +610,11 @@ void dcache_disable(void) set_sctlr(sctlr & ~(CR_C|CR_M)); flush_dcache_all(); @@ -255,3 +254,6 @@ index 87d1c77e8b..4510db98a2 100644 /* * ID_AA64PFR0_EL1 bits definitions */ +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch index 103e48479c..b8cab45e40 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0002-vexpress64-add-MPU-memory-map-for-the-BASER_FVP.patch @@ -1,7 +1,7 @@ -From 5b42322cb57692dbea7d2c39fd8769b6f0f6b7af Mon Sep 17 00:00:00 2001 +From 181f5efb401ffaa5ab0898b07a976796f75e502a Mon Sep 17 00:00:00 2001 From: Qi Feng Date: Tue, 26 Jul 2022 18:13:23 +0800 -Subject: [PATCH] vexpress64: add MPU memory map for the BASER_FVP +Subject: [PATCH 2/9] vexpress64: add MPU memory map for the BASER_FVP The previous patch added support for initializing an Armv8 MPU. There is only an MPU at S-EL2 on the BASER_FVP, so add a platform-specific MPU memory map. @@ -12,7 +12,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Signed-off-by: Qi Feng - --- board/armltd/vexpress64/vexpress64.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) @@ -57,3 +56,6 @@ index af326dc6f4..2310d18eb7 100644 static struct mm_region vexpress64_mem_map[] = { { .virt = V2M_PA_BASE, +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch index 5953abc652..caabf804b2 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0003-armv8-Allow-disabling-exception-vectors-on-non-SPL-b.patch @@ -1,7 +1,8 @@ -From ffb0f72a67926c3053308cf03420bc0c36675d42 Mon Sep 17 00:00:00 2001 +From 07cc3e4af3def76d92faf39712d4fd8717b21d2b Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Fri, 10 Dec 2021 11:41:19 +0000 -Subject: [PATCH] armv8: Allow disabling exception vectors on non-SPL builds +Subject: [PATCH 3/9] armv8: Allow disabling exception vectors on non-SPL + builds On the BASER_FVP, U-Boot shares EL2 with another bootloader, so we do not wish to overide the exception vector, but we are also not using an @@ -18,7 +19,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I0cf0fc6d7ef4d45791411cf1f67c65e198cc8b2b - --- arch/arm/cpu/armv8/Kconfig | 10 ++++++++-- arch/arm/cpu/armv8/Makefile | 6 ++---- @@ -72,7 +72,7 @@ index 2e4bf9e038..001a31cae7 100644 endif obj-y += tlb.o diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S -index f3ea858577..7fad901336 100644 +index 28f0df13f0..f831e77af3 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -104,7 +104,7 @@ pie_skip_reloc: @@ -102,3 +102,6 @@ index 495eb1dee3..683d983c36 100644 # CONFIG_MMC is not set CONFIG_VIRTIO_MMIO=y +CONFIG_ARMV8_EXCEPTION_VECTORS=n +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch index 157a15d7df..81758fce71 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0004-armv8-ARMV8_SWITCH_TO_EL1-improvements.patch @@ -1,7 +1,7 @@ -From 14e204ffca5870d6bfd238627937a2028c88589d Mon Sep 17 00:00:00 2001 +From 30405f59881c73946b6b0ffdbf25804f9fbf1585 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Wed, 14 Jul 2021 12:44:27 +0100 -Subject: [PATCH] armv8: ARMV8_SWITCH_TO_EL1 improvements +Subject: [PATCH 4/9] armv8: ARMV8_SWITCH_TO_EL1 improvements Convert CONFIG_ARMV8_SWITCH_TO_EL1 to a Kconfig variable. @@ -16,7 +16,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: If98478148d6d8d1f732acac5439276700614815f - --- arch/arm/cpu/armv8/exception_level.c | 21 ++++++++++++++-- arch/arm/lib/bootm.c | 36 ++++++++++++++++------------ @@ -67,7 +66,7 @@ index b11936548f..4aad1550f4 100644 } } diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c -index e414ef8267..9a86c17d2a 100644 +index 9f086f3b90..b044aeca88 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -270,7 +270,6 @@ __weak void update_os_arch_secondary_cores(uint8_t os_arch) @@ -85,8 +84,8 @@ index e414ef8267..9a86c17d2a 100644 -#endif /* Subcommand: GO */ - static void boot_jump_linux(struct bootm_headers *images, int flag) -@@ -312,21 +310,29 @@ static void boot_jump_linux(struct bootm_headers *images, int flag) + static void boot_jump_linux(bootm_headers_t *images, int flag) +@@ -312,21 +310,29 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) update_os_arch_secondary_cores(images->os.arch); @@ -138,3 +137,6 @@ index 683d983c36..6044f82b00 100644 CONFIG_VIRTIO_MMIO=y CONFIG_ARMV8_EXCEPTION_VECTORS=n +CONFIG_ARMV8_SWITCH_TO_EL1=y +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch index 82926cc36e..f64db3bf46 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0005-armv8-Make-disabling-HVC-configurable-when-switching.patch @@ -1,7 +1,8 @@ -From e3d24bc1fd0b09915b5181de1282f7008bbf776f Mon Sep 17 00:00:00 2001 +From a6daca56b77d7f1b26483f10eb33ebdd6e157d3e Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Fri, 10 Dec 2021 16:37:26 +0000 -Subject: [PATCH] armv8: Make disabling HVC configurable when switching to EL1 +Subject: [PATCH 5/9] armv8: Make disabling HVC configurable when switching to + EL1 On the BASER_FVP there is no EL3, so HVC is used to provide PSCI services. Therefore we cannot disable hypercalls. @@ -14,7 +15,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: I463d82f1db8a3cafcab40a9c0c208753569cc300 - --- arch/arm/cpu/armv8/Kconfig | 9 +++++++++ arch/arm/include/asm/macro.h | 10 ++++++++-- @@ -78,3 +78,6 @@ index 6044f82b00..6226f6b2c1 100644 CONFIG_ARMV8_EXCEPTION_VECTORS=n CONFIG_ARMV8_SWITCH_TO_EL1=y +CONFIG_ARMV8_DISABLE_HVC=n +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch index eb2273e565..ebbc939c05 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0006-vexpress64-Do-not-set-COUNTER_FREQUENCY.patch @@ -1,7 +1,7 @@ -From 571f44d5292cfead6f68bf4c6c9519872337bfd0 Mon Sep 17 00:00:00 2001 +From 862d3f1ac66a75cdf48adbdebd8adbaf671a9366 Mon Sep 17 00:00:00 2001 From: Qi Feng Date: Thu, 28 Jul 2022 17:47:18 +0800 -Subject: [PATCH] vexpress64: Do not set COUNTER_FREQUENCY +Subject: [PATCH 6/9] vexpress64: Do not set COUNTER_FREQUENCY VExpress boards normally run as a second-stage bootloader so should not need to modify CNTFRQ_EL0. On the BASER_FVP, U-Boot can modify it if @@ -13,7 +13,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Signed-off-by: Qi Feng - --- configs/vexpress_aemv8r_defconfig | 1 - 1 file changed, 1 deletion(-) @@ -28,3 +27,6 @@ index 6226f6b2c1..b902a6a7d9 100644 CONFIG_ARCH_VEXPRESS64=y CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="arm_fvp" +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch index 6f5bfa38c4..8c09ed2b74 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0007-vexpress64-Enable-LIBFDT_OVERLAY-in-the-vexpress_aem.patch @@ -1,7 +1,7 @@ -From df01346bb63c821cf8e73202e2894ceda9cb692b Mon Sep 17 00:00:00 2001 +From 32beea722c1167c9b33f1ecfdc28d360cabd6823 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Tue, 22 Feb 2022 15:32:51 +0000 -Subject: [PATCH] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r +Subject: [PATCH 7/9] vexpress64: Enable LIBFDT_OVERLAY in the vexpress_aemv8r defconfig Issue-Id: SCM-3874 @@ -9,7 +9,6 @@ Upstream-Status: Inappropriate [other] Implementation pending further discussion Signed-off-by: Peter Hoyes Change-Id: Ide0532cf2de89f1bca9c8d4bd2ed0c1a1c57599f - --- configs/vexpress_aemv8r_defconfig | 1 + 1 file changed, 1 insertion(+) @@ -23,3 +22,6 @@ index b902a6a7d9..a58a9db385 100644 CONFIG_ARMV8_SWITCH_TO_EL1=y CONFIG_ARMV8_DISABLE_HVC=n +CONFIG_OF_LIBFDT_OVERLAY=y +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch index 61bdf928f4..8be14ee85a 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0008-armv8-Allow-PRBAR-MPU-attributes-to-be-configured.patch @@ -1,7 +1,7 @@ -From 665ab8253a0e3e17db54a1682bbee0f5659939a2 Mon Sep 17 00:00:00 2001 +From 01490ab8deb0f0b61eeb55a02ee5ea430cfe7eee Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Wed, 18 May 2022 15:24:19 +0100 -Subject: [PATCH] armv8: Allow PRBAR MPU attributes to be configured +Subject: [PATCH 8/9] armv8: Allow PRBAR MPU attributes to be configured In a previous patch, support was added to initialize an S-EL2 MPU on armv8r64 machines. This implementation allowed the PRLAR attribute @@ -21,7 +21,6 @@ Signed-off-by: Peter Hoyes Upstream-Status: Inappropriate [other] Implementation pending further discussion Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984 - --- arch/arm/cpu/armv8/cache_v8.c | 12 ++++++++---- arch/arm/include/asm/armv8/mpu.h | 3 ++- @@ -29,7 +28,7 @@ Change-Id: I6b72aead91ad12412262aa32c61a53e12eab3984 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c -index 8611a35eb3..f7de952187 100644 +index 798aed8058..e336339281 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -390,7 +390,9 @@ static void mpu_clear_regions(void) @@ -101,3 +100,6 @@ index 2310d18eb7..531fa4d618 100644 }, { /* List terminator */ 0, +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch index a4bc746e30..0e0a248136 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot/fvp-baser-aemv8r64/0009-armv8-Enable-icache-when-switching-exception-levels-.patch @@ -1,7 +1,7 @@ -From c7301588a3aec9ebf36749da601d0d6e3d807bfc Mon Sep 17 00:00:00 2001 +From 0f15f6b02825b042ddc1d753f62cf87f30b1fe12 Mon Sep 17 00:00:00 2001 From: Peter Hoyes Date: Thu, 19 May 2022 09:02:32 +0100 -Subject: [PATCH] armv8: Enable icache when switching exception levels in +Subject: [PATCH 9/9] armv8: Enable icache when switching exception levels in bootefi bootefi calls the function switch_to_non_secure_mode before calling the @@ -26,7 +26,6 @@ Signed-off-by: Peter Hoyes Upstream-Status: Inappropriate [other] Implementation pending further discussion Change-Id: I678cd5ba39b56e124ab7854608289cd14651ce65 - --- arch/arm/cpu/armv8/exception_level.c | 3 +++ 1 file changed, 3 insertions(+) @@ -59,3 +58,6 @@ index 4aad1550f4..0a3e5428e7 100644 /* Move into EL1 and keep running there */ armv8_switch_to_el1((uintptr_t)&non_secure_jmp, 0, 0, 0, (uintptr_t)entry_non_secure, ES_TO_AARCH64); +-- +2.25.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend index d1dcd74557..6c0d49046a 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_%.bbappend @@ -1,5 +1,12 @@ FILESEXTRAPATHS:prepend := "${THISDIR}/${PN}:" +# +# Corstone-500 MACHINE +# +SRC_URI:append:corstone500 = " \ + file://0001-armv7-adding-generic-timer-access-through-MMIO.patch \ + file://0002-board-arm-add-corstone500-board.patch" + # # Corstone1000 64-bit machines # @@ -43,8 +50,7 @@ SRC_URI:append:corstone1000 = " \ file://0030-corstone1000-boot-index-from-active.patch \ file://0031-corstone1000-enable-PSCI-reset.patch \ file://0032-Enable-EFI-set-get-time-services.patch \ - file://0033-corstone1000-detect-inflated-kernel-size.patch \ - file://0034-corstone1000-ESRT-add-unique-firmware-GUID.patch \ + file://0033-Increase-the-unzipped-Kernel-size.patch \ " # diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb new file mode 100644 index 0000000000..905ae552a7 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/u-boot/u-boot_2022.10.bb @@ -0,0 +1,26 @@ +HOMEPAGE = "http://www.denx.de/wiki/U-Boot/WebHome" +DESCRIPTION = "U-Boot, a boot loader for Embedded boards based on PowerPC, \ +ARM, MIPS and several other processors, which can be installed in a boot \ +ROM and used to initialize and test the hardware or to download and run \ +application code." +SECTION = "bootloaders" +DEPENDS += "flex-native bison-native" + +LICENSE = "GPL-2.0-or-later" +LIC_FILES_CHKSUM = "file://Licenses/README;md5=2ca5f2c35c8cc335f0a19756634782f1" +PE = "1" + +# We use the revision in order to avoid having to fetch it from the +# repo during parse +SRCREV = "4debc57a3da6c3f4d3f89a637e99206f4cea0a96" + +SRC_URI = "git://git.denx.de/u-boot.git;branch=master \ + " + +S = "${WORKDIR}/git" +B = "${WORKDIR}/build" +do_configure[cleandirs] = "${B}" + +require recipes-bsp/u-boot/u-boot.inc + +DEPENDS += "bc-native dtc-native gnutls-native" diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc index fcdedf8004..0d557f3cb1 100644 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/edk2-firmware-n1sdp.inc @@ -11,16 +11,18 @@ COMPATIBLE_MACHINE = "n1sdp" EFIDIR = "/EFI/BOOT" EFI_BOOT_IMAGE = "bootaa64.efi" -FILESEXTRAPATHS:prepend := "${THISDIR}/files/n1sdp:" +FILESEXTRAPATHS:prepend := "${THISDIR}/files/edk2-platforms:" + SRC_URI:append = "\ file://0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch;patchdir=edk2-platforms \ - file://0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch;patchdir=edk2-platforms \ - file://0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch;patchdir=edk2-platforms \ - file://0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch;patchdir=edk2-platforms \ - file://0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch;patchdir=edk2-platforms \ - file://0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch;patchdir=edk2-platforms \ - file://0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch;patchdir=edk2-platforms \ - file://0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch;patchdir=edk2-platforms \ + file://0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch;patchdir=edk2-platforms \ + file://0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch;patchdir=edk2-platforms \ + file://0004-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch;patchdir=edk2-platforms \ + file://0005-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch;patchdir=edk2-platforms \ + file://0006-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch;patchdir=edk2-platforms \ + file://0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch;patchdir=edk2-platforms \ + file://0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch;patchdir=edk2-platforms \ + file://0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch;patchdir=edk2-platforms \ " do_deploy:append() { diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch new file mode 100644 index 0000000000..c7f163b40b --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch @@ -0,0 +1,471 @@ +From 928cb457b9ab2abefbacad655eefdde943b4ee9a Mon Sep 17 00:00:00 2001 +From: sahil +Date: Thu, 17 Mar 2022 16:28:05 +0530 +Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG + +NT_FW_CONFIG DTB contains platform information passed by +Tf-A boot stage. +This information is used for Virtual memory map generation +during PEI phase and passed on to DXE phase as a HOB, where +it is used in ConfigurationManagerDxe. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: I54a86277719607eb00d4a472fae8f13c180eafca +--- + .../ConfigurationManager.c | 24 ++-- + .../ConfigurationManagerDxe.inf | 3 +- + .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +-- + .../Library/PlatformLib/AArch64/Helper.S | 4 +- + .../Library/PlatformLib/PlatformLib.c | 12 +- + .../Library/PlatformLib/PlatformLib.inf | 8 +- + .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++- + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +- + 8 files changed, 152 insertions(+), 25 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index a6b4cb0e..c15020f5 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -1,7 +1,7 @@ + /** @file + Configuration Manager Dxe + +- Copyright (c) 2021, ARM Limited. All rights reserved.
++ Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -28,6 +29,7 @@ + #include "Platform.h" + + extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat; ++static NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + + /** The platform configuration repository information. + */ +@@ -1242,13 +1244,11 @@ InitializePlatformRepository ( + IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo + ) + { +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 Dram2Size; + UINT64 RemoteDdrSize; + + RemoteDdrSize = 0; + +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB); + + PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; +@@ -1512,7 +1512,6 @@ GetGicCInfo ( + ) + { + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 TotalObjCount; + UINT32 ObjIndex; + +@@ -1523,7 +1522,6 @@ GetGicCInfo ( + } + + PlatformRepo = This->PlatRepoInfo; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + + if (PlatInfo->MultichipMode == 1) { + TotalObjCount = PLAT_CPU_COUNT * 2; +@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject ( + { + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 AcpiTableCount; + + if ((This == NULL) || (CmObject == NULL)) { +@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject ( + + Status = EFI_NOT_FOUND; + PlatformRepo = This->PlatRepoInfo; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; ++ + AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList); + if (PlatInfo->MultichipMode == 0) + AcpiTableCount -= 1; +@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject ( + { + EFI_STATUS Status; + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; +- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT32 GicRedistCount; + UINT32 GicCpuCount; + UINT32 ProcHierarchyInfoCount; +@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject ( + Status = EFI_NOT_FOUND; + PlatformRepo = This->PlatRepoInfo; + +- // Probe for multi chip information +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; + if (PlatInfo->MultichipMode == 1) { + GicRedistCount = 2; + GicCpuCount = PLAT_CPU_COUNT * 2; +@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize ( + IN EFI_SYSTEM_TABLE * SystemTable + ) + { ++ VOID *PlatInfoHob; + EFI_STATUS Status; + ++ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid); ++ ++ if (PlatInfoHob == NULL) { ++ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); ++ return EFI_NOT_FOUND; ++ } ++ ++ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob); ++ + // Initialize the Platform Configuration Repository before installing the + // Configuration Manager Protocol + Status = InitializePlatformRepository ( +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +index 4f8e7f13..a4e8b783 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf +@@ -1,7 +1,7 @@ + ## @file + # Configuration Manager Dxe + # +-# Copyright (c) 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -42,6 +42,7 @@ + + [LibraryClasses] + ArmPlatformLib ++ HobLib + PrintLib + UefiBootServicesTableLib + UefiDriverEntryPoint +diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +index 097160c7..4966011e 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h ++++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +@@ -1,6 +1,6 @@ + /** @file + * +-* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. ++* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +@@ -41,11 +41,6 @@ + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + +-// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is +-// pre-populated by a earlier boot stage +-#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ +- 0x00008000) +- + /* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure +@@ -55,12 +50,17 @@ + typedef struct { + /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ + UINT8 MultichipMode; +- /*! Slave count in C2C mode */ +- UINT8 SlaveCount; ++ /*! Secondary chip count in C2C mode */ ++ UINT8 SecondaryChipCount; + /*! Local DDR memory size in GigaBytes */ + UINT8 LocalDdrSize; + /*! Remote DDR memory size in GigaBytes */ + UINT8 RemoteDdrSize; + } NEOVERSEN1SOC_PLAT_INFO; + ++// NT_FW_CONFIG DT structure ++typedef struct { ++ UINT64 NtFwConfigDtAddr; ++} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI; ++ + #endif +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S +index 8d2069de..a0b89a7b 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S +@@ -1,6 +1,6 @@ + /** @file + * +-* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. ++* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * +@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) + // the UEFI firmware through the CPU registers. + // + ASM_PFX(ArmPlatformPeiBootAction): ++ adr x10, NtFwConfigDtBlob ++ str x0, [x10] + ret + + // +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +index c0effd37..2f753be7 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c +@@ -1,6 +1,6 @@ + /** @file + +- Copyright (c) 2018-2021, ARM Limited. All rights reserved.
++ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -8,8 +8,12 @@ + + #include + #include ++#include + #include + ++UINT64 NtFwConfigDtBlob; ++STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi; ++ + STATIC ARM_CORE_INFO mCoreInfoTable[] = { + { 0x0, 0x0 }, // Cluster 0, Core 0 + { 0x0, 0x1 }, // Cluster 0, Core 1 +@@ -46,6 +50,7 @@ ArmPlatformInitialize ( + IN UINTN MpId + ) + { ++ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob; + return RETURN_SUCCESS; + } + +@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gArmMpCoreInfoPpiGuid, + &mMpCoreInfoPpi ++ }, ++ { ++ EFI_PEI_PPI_DESCRIPTOR_PPI, ++ &gNtFwConfigDtInfoPpiGuid, ++ &mNtFwConfigDtInfoPpi + } + }; + +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +index 96e590cd..78f309c3 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf +@@ -1,7 +1,7 @@ + ## @file + # Platform Library for N1Sdp. + # +-# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -18,10 +18,14 @@ + [Packages] + ArmPkg/ArmPkg.dec + ArmPlatformPkg/ArmPlatformPkg.dec ++ EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec + ++[LibraryClasses] ++ FdtLib ++ + [Sources.common] + PlatformLibMem.c + PlatformLib.c +@@ -59,7 +63,9 @@ + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + [Guids] ++ gArmNeoverseN1SocPlatformInfoDescriptorGuid + gEfiHobListGuid ## CONSUMES ## SystemTable + + [Ppis] + gArmMpCoreInfoPpiGuid ++ gNtFwConfigDtInfoPpiGuid +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +index 339fa07b..1d53ec75 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +@@ -1,6 +1,6 @@ + /** @file + +- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +@@ -10,11 +10,95 @@ + #include + #include + #include ++#include ++#include + #include + + // The total number of descriptors, including the final "end-of-table" descriptor. + #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 + ++/** A helper function to locate the NtFwConfig PPI and get the base address of ++ NT_FW_CONFIG DT from which values are obtained using FDT helper functions. ++ ++ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB ++ ++ @retval EFI_SUCCESS Success. ++ returns EFI_INVALID_PARAMETER A parameter is invalid. ++**/ ++EFI_STATUS ++GetNeoverseN1SocPlatInfo ( ++ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info ++ ) ++{ ++ CONST UINT32 *Property; ++ INT32 Offset; ++ CONST VOID *NtFwCfgDtBlob; ++ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi; ++ EFI_STATUS Status; ++ ++ Status = PeiServicesLocatePpi ( ++ &gNtFwConfigDtInfoPpiGuid, ++ 0, ++ NULL, ++ (VOID **)&NtFwConfigInfoPpi ++ ); ++ ++ if (EFI_ERROR (Status)) { ++ DEBUG (( ++ DEBUG_ERROR, ++ "PeiServicesLocatePpi failed with error %r\n", ++ Status ++ )); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr; ++ if (fdt_check_header (NtFwCfgDtBlob) != 0) { ++ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob)); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info"); ++ if (Offset == -FDT_ERR_NOTFOUND) { ++ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->LocalDdrSize = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property); ++ ++ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL); ++ if (Property == NULL) { ++ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ plat_info->MultichipMode = fdt32_to_cpu (*Property); ++ ++ return EFI_SUCCESS; ++} ++ + /** + Returns the Virtual Memory Map of the platform. + +@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap ( + NEOVERSEN1SOC_PLAT_INFO *PlatInfo; + UINT64 DramBlock2Size; + UINT64 RemoteDdrSize; ++ EFI_STATUS Status; + + Index = 0; +- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; ++ ++ // Create platform info HOB ++ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob ( ++ &gArmNeoverseN1SocPlatformInfoDescriptorGuid, ++ sizeof (NEOVERSEN1SOC_PLAT_INFO) ++ ); ++ ++ if (PlatInfo == NULL) { ++ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); ++ ASSERT (FALSE); ++ return; ++ } ++ ++ Status = GetNeoverseN1SocPlatInfo (PlatInfo); ++ ASSERT (Status == 0); + DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - + NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * + (UINT64)SIZE_1GB); +diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +index d59f25a5..9e257ebd 100644 +--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec ++++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec +@@ -1,7 +1,7 @@ + ## @file + # Describes the entire platform configuration. + # +-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -22,6 +22,8 @@ + Include # Root include for the package + + [Guids.common] ++ # ARM NeoverseN1Soc Platform Info descriptor ++ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } } + gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } + + [PcdsFixedAtBuild] +@@ -83,3 +85,6 @@ + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050 + gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051 ++ ++[Ppis] ++ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } } diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch new file mode 100644 index 0000000000..5e634175d5 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0002-Platform-ARM-N1Sdp-Fix-RemoteDdrSize-cast.patch @@ -0,0 +1,44 @@ +From ba3ed154863d1acd0996178beaf3a2bc693b938c Mon Sep 17 00:00:00 2001 +From: sahil +Date: Wed, 20 Apr 2022 12:24:41 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: Fix RemoteDdrSize cast + +RemoteDdrSize calculation wraps around when booting N1Sdp in +multichip mode. Casting it to UINT64 to fix the issue. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: Ic51269a8d67669684a5f056701cfbef6beb23da2 +--- + .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- + Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index c15020f5..b11c0425 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -1254,7 +1254,7 @@ InitializePlatformRepository ( + PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; + + if (PlatInfo->MultichipMode == 1) { +- RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); ++ RemoteDdrSize = ((UINT64)(PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); + + // Update Remote DDR Region1 + PlatRepoInfo->MemAffInfo[REMOTE_DDR_REGION1].ProximityDomain = 1; +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +index 1d53ec75..5cacd437 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +@@ -157,7 +157,7 @@ ArmPlatformGetVirtualMemoryMap ( + DramBlock2Size); + + if (PlatInfo->MultichipMode == 1) { +- RemoteDdrSize = ((PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); ++ RemoteDdrSize = ((UINT64)(PlatInfo->RemoteDdrSize - 2) * SIZE_1GB); + + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch new file mode 100644 index 0000000000..cafc299096 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0003-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch @@ -0,0 +1,63 @@ +From 2ccb463274d0c04f1e3253194ea6eee80c31cb49 Mon Sep 17 00:00:00 2001 +From: Himanshu Sharma +Date: Mon, 30 May 2022 10:53:30 +0000 +Subject: [PATCH] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and + routing it to IOFPGA UART1 + +In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the +IPI0 trigger method to "level", which prevented SGI0 to be enabled +again after a CPU offline/online cycle. + +This patch fixes the above issue by assigning a reserved IRQ ID +for the Debug UART, other than 0 and also routing it to use IOFPGA +UART1 by unsharing it from currently using serial terminal. + +Upstream-Status: Pending +Signed-off-by: Adam Johnston +Signed-off-by: Xueliang Zhong +Signed-off-by: Himanshu Sharma +Change-Id: Ib35fecc57f1d8c496135c18dbebd0be0a4b76041 +--- + .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- + Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++---- + 2 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +index b11c0425..44046a00 100644 +--- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c ++++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c +@@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { + // Debug Serial Port + { + FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress +- 0, // Interrupt -unused ++ 250, // Interrupt (reserved) + FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate + FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock + EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +index d04b22d3..676ab677 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +@@ -4,7 +4,7 @@ + # This provides platform specific component descriptions and libraries that + # conform to EFI/Framework standards. + # +-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + # +@@ -136,9 +136,9 @@ + gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 + + # PL011 Serial Debug UART (DBG2) +- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase +- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate +- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 ++ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000 + + # SBSA Watchdog + gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0004-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0004-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch new file mode 100644 index 0000000000..264d262b22 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0004-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch @@ -0,0 +1,57 @@ +From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001 +From: sahil +Date: Mon, 2 May 2022 17:43:17 +0530 +Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region + +Enable SCP QSPI flash region access by adding it in the PlatformLibMem + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005 +--- + Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++ + .../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++- + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +index 4966011e..c7219136 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h ++++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h +@@ -41,6 +41,10 @@ + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 + #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 + ++// SCP QSPI flash device ++#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000 ++#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000 ++ + /* + * Platform information structure stored in Non-secure SRAM. Platform + * information are passed from the trusted firmware with the below structure +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +index 5cacd437..8bb94074 100644 +--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c ++++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c +@@ -15,7 +15,7 @@ + #include + + // The total number of descriptors, including the final "end-of-table" descriptor. +-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 ++#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20 + + /** A helper function to locate the NtFwConfig PPI and get the base address of + NT_FW_CONFIG DT from which values are obtained using FDT helper functions. +@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap ( + VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + ++ // SCP QSPI flash device ++ VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE; ++ VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE; ++ VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ; ++ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; ++ + if (PlatInfo->MultichipMode == 1) { + //Remote DDR (2GB) + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0005-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0005-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch new file mode 100644 index 0000000000..eabbaf9976 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0005-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch @@ -0,0 +1,119 @@ +From 70e79ba5300f01a13422452c29e26c69042a0c8c Mon Sep 17 00:00:00 2001 +From: sahil +Date: Mon, 2 May 2022 18:50:08 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash library for N1Sdp + +Add NOR flash library, this library provides APIs for getting the list +of NOR flash devices on the platform. + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: I39ad4143b7fad7e33b3b151a019a74f23e0ed441 +--- + .../Library/NorFlashLib/NorFlashLib.c | 52 +++++++++++++++++++ + .../Library/NorFlashLib/NorFlashLib.inf | 36 +++++++++++++ + 2 files changed, 88 insertions(+) + create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c + create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf + +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c +new file mode 100644 +index 00000000..eee3d1c6 +--- /dev/null ++++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c +@@ -0,0 +1,52 @@ ++/** @file ++ NOR flash lib for N1Sdp ++ ++ Copyright (c) 2023, ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define FW_ENV_REGION_BASE FixedPcdGet32 (PcdFlashNvStorageVariableBase) ++#define FW_ENV_REGION_SIZE (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + \ ++ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + \ ++ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) ++ ++STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { ++ { ++ /// Environment variable region ++ NEOVERSEN1SOC_SCP_QSPI_AHB_BASE, ///< device base ++ FW_ENV_REGION_BASE, ///< region base ++ FW_ENV_REGION_SIZE, ///< region size ++ SIZE_4KB, ///< block size ++ }, ++}; ++ ++/** ++ Get NOR flash region info ++ ++ @param[out] NorFlashDevices NOR flash regions info. ++ @param[out] Count number of flash instance. ++ ++ @retval EFI_SUCCESS Success. ++**/ ++EFI_STATUS ++NorFlashPlatformGetDevices ( ++ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, ++ OUT UINT32 *Count ++ ) ++{ ++ if ((NorFlashDevices == NULL) || (Count == NULL)) { ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ *NorFlashDevices = mNorFlashDevices; ++ *Count = ARRAY_SIZE (mNorFlashDevices); ++ return EFI_SUCCESS; ++} +diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf +new file mode 100644 +index 00000000..784856c8 +--- /dev/null ++++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf +@@ -0,0 +1,36 @@ ++## @file ++# NOR flash lib for N1Sdp ++# ++# Copyright (c) 2023, ARM Limited. All rights reserved.
++# ++# SPDX-License-Identifier: BSD-2-Clause-Patent ++# ++## ++ ++[Defines] ++ INF_VERSION = 0x0001001B ++ BASE_NAME = NorFlashN1SdpLib ++ FILE_GUID = 7006fcf1-a585-4272-92e3-b286b1dff5bb ++ MODULE_TYPE = DXE_DRIVER ++ VERSION_STRING = 1.0 ++ LIBRARY_CLASS = NorFlashPlatformLib ++ ++[Sources.common] ++ NorFlashLib.c ++ ++[Packages] ++ MdeModulePkg/MdeModulePkg.dec ++ MdePkg/MdePkg.dec ++ Platform/ARM/ARM.dec ++ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec ++ ++[LibraryClasses] ++ BaseLib ++ DebugLib ++ IoLib ++ ++[FixedPcd] ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0006-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0006-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch new file mode 100644 index 0000000000..1db94e4948 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0006-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch @@ -0,0 +1,2538 @@ +From 726f4505970c82db1822b127059519044dc496c8 Mon Sep 17 00:00:00 2001 +From: sahil +Date: Mon, 2 May 2022 19:00:40 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash Dxe Driver for N1Sdp + +Add NOR flash DXE driver, this brings up NV storage on +QSPI's flash device using FVB protocol. + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: Ica383c2be6d1805daa19afd98d28b943816218dd +--- + .../Drivers/CadenceQspiDxe/CadenceQspiDxe.c | 366 +++++++ + .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 70 ++ + .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 31 + + .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 930 ++++++++++++++++++ + .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 484 +++++++++ + .../Drivers/CadenceQspiDxe/NorFlashFvb.c | 573 +++++++++++ + Platform/ARM/N1Sdp/N1SdpPlatform.dec | 5 +- + 7 files changed, 2458 insertions(+), 1 deletion(-) + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h + create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c + +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c +new file mode 100644 +index 00000000..fb1dff3e +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c +@@ -0,0 +1,366 @@ ++/** @file ++ NOR flash DXE ++ ++ Copyright (c) 2023, ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "NorFlash.h" ++ ++STATIC NOR_FLASH_INSTANCE **mNorFlashInstances; ++STATIC UINT32 mNorFlashDeviceCount; ++ ++STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; ++ ++/** ++ Install Fv block onto variable store region ++ ++ @param[in] Instance Instance of Nor flash variable region. ++ ++ @retval EFI_SUCCESS The entry point is executed successfully. ++**/ ++EFI_STATUS ++EFIAPI ++NorFlashFvbInitialize ( ++ IN NOR_FLASH_INSTANCE* Instance ++ ) ++{ ++ EFI_STATUS Status; ++ UINT32 FvbNumLba; ++ EFI_BOOT_MODE BootMode; ++ UINTN RuntimeMmioRegionSize; ++ UINTN RuntimeMmioDeviceSize; ++ UINTN BlockSize; ++ ++ DEBUG ((DEBUG_INFO,"NorFlashFvbInitialize\n")); ++ ++ BlockSize = Instance->BlockSize; ++ ++ // FirmwareVolumeHeader->FvLength is declared to have the Variable area ++ // AND the FTW working area AND the FTW Spare contiguous. ++ ASSERT (PcdGet32 (PcdFlashNvStorageVariableBase) + ++ PcdGet32 (PcdFlashNvStorageVariableSize) == ++ PcdGet32 (PcdFlashNvStorageFtwWorkingBase)); ++ ASSERT (PcdGet32 (PcdFlashNvStorageFtwWorkingBase) + ++ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == ++ PcdGet32 (PcdFlashNvStorageFtwSpareBase)); ++ ++ // Check if the size of the area is at least one block size. ++ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && ++ (PcdGet32 (PcdFlashNvStorageVariableSize) / BlockSize > 0)); ++ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && ++ (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0)); ++ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && ++ (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0)); ++ ++ // Ensure the Variable areas are aligned on block size boundaries. ++ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableBase) % BlockSize) == 0); ++ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0); ++ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0); ++ ++ Instance->Initialized = TRUE; ++ mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase); ++ ++ // Set the index of the first LBA for the FVB. ++ Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - ++ Instance->RegionBaseAddress) / BlockSize; ++ ++ BootMode = GetBootModeHob (); ++ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) { ++ Status = EFI_INVALID_PARAMETER; ++ } else { ++ // Determine if there is a valid header at the beginning of the NorFlash. ++ Status = ValidateFvHeader (Instance); ++ } ++ ++ // Install the Default FVB header if required. ++ if (EFI_ERROR(Status)) { ++ // There is no valid header, so time to install one. ++ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__)); ++ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", ++ __FUNCTION__)); ++ ++ // Erase all the NorFlash that is reserved for variable storage. ++ FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) + ++ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + ++ PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / ++ Instance->BlockSize; ++ ++ Status = FvbEraseBlocks ( ++ &Instance->FvbProtocol, ++ (EFI_LBA)0, ++ FvbNumLba, ++ EFI_LBA_LIST_TERMINATOR ++ ); ++ if (EFI_ERROR(Status)) { ++ return Status; ++ } ++ ++ // Install all appropriate headers. ++ Status = InitializeFvAndVariableStoreHeaders (Instance); ++ if (EFI_ERROR(Status)) { ++ return Status; ++ } ++ ++ // validate FV header again if FV was created successfully. ++ Status = ValidateFvHeader (Instance); ++ if (EFI_ERROR(Status)) { ++ DEBUG ((DEBUG_ERROR, "ValidateFvHeader is failed \n")); ++ return Status; ++ } ++ } ++ ++ // The driver implementing the variable read service can now be dispatched; ++ // the varstore headers are in place. ++ Status = gBS->InstallProtocolInterface ( ++ &gImageHandle, ++ &gEdkiiNvVarStoreFormattedGuid, ++ EFI_NATIVE_INTERFACE, ++ NULL ++ ); ++ if (EFI_ERROR (Status)) { ++ DEBUG ((DEBUG_ERROR, ++ "%a: Failed to install gEdkiiNvVarStoreFormattedGuid\n", ++ __FUNCTION__)); ++ return Status; ++ } ++ ++ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME. ++ RuntimeMmioRegionSize = Instance->Size; ++ RuntimeMmioDeviceSize = Instance->RegionBaseAddress - Instance->DeviceBaseAddress; ++ ++ Status = gDS->AddMemorySpace ( ++ EfiGcdMemoryTypeMemoryMappedIo, ++ Instance->RegionBaseAddress, ++ RuntimeMmioRegionSize, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ Status = gDS->AddMemorySpace ( ++ EfiGcdMemoryTypeMemoryMappedIo, ++ Instance->DeviceBaseAddress, ++ RuntimeMmioDeviceSize, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ Status = gDS->SetMemorySpaceAttributes ( ++ Instance->RegionBaseAddress, ++ RuntimeMmioRegionSize, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ Status = gDS->SetMemorySpaceAttributes ( ++ Instance->DeviceBaseAddress, ++ RuntimeMmioDeviceSize, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ return Status; ++} ++ ++/** ++ Fixup internal data so that EFI can be called in virtual mode. ++ convert any pointers in lib to virtual mode. ++ ++ @param[in] Event The Event that is being processed ++ @param[in] Context Event Context ++**/ ++STATIC ++VOID ++EFIAPI ++NorFlashVirtualNotifyEvent ( ++ IN EFI_EVENT Event, ++ IN VOID *Context ++ ) ++{ ++ UINTN Index; ++ ++ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); ++ ++ for (Index = 0; Index < mNorFlashDeviceCount; Index++) { ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->HostRegisterBaseAddress); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress); ++ ++ // Convert Fvb. ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes); ++ EfiConvertPointer (0x0, ++ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write); ++ ++ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) { ++ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer); ++ } ++ } ++} ++ ++/** ++ Entrypoint of Platform Nor flash DXE driver ++ ++ @param[in] ImageHandle The firmware allocated handle for the EFI image. ++ @param[in] SystemTable A pointer to the EFI System Table. ++ ++ @retval EFI_SUCCESS The entry point is executed successfully. ++**/ ++EFI_STATUS ++EFIAPI ++NorFlashInitialise ( ++ IN EFI_HANDLE ImageHandle, ++ IN EFI_SYSTEM_TABLE *SystemTable ++ ) ++{ ++ EFI_STATUS Status; ++ EFI_PHYSICAL_ADDRESS HostRegisterBaseAddress; ++ UINT32 Index; ++ NOR_FLASH_DESCRIPTION* NorFlashDevices; ++ BOOLEAN ContainVariableStorage; ++ ++ HostRegisterBaseAddress = PcdGet32 (PcdCadenceQspiDxeRegBaseAddress); ++ ++ Status = gDS->AddMemorySpace ( ++ EfiGcdMemoryTypeMemoryMappedIo, ++ HostRegisterBaseAddress, ++ SIZE_64KB, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ Status = gDS->SetMemorySpaceAttributes ( ++ HostRegisterBaseAddress, ++ SIZE_64KB, ++ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ // Initialize NOR flash instances. ++ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount); ++ if (EFI_ERROR (Status)) { ++ DEBUG ((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n")); ++ return Status; ++ } ++ ++ mNorFlashInstances = AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE*) * ++ mNorFlashDeviceCount); ++ ++ if(mNorFlashInstances == NULL) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashInitialise: Failed to allocate mem for NorFlashInstance\n")); ++ return EFI_OUT_OF_RESOURCES; ++ } ++ ++ for (Index = 0; Index < mNorFlashDeviceCount; Index++) { ++ // Check if this NOR Flash device contain the variable storage region. ++ ContainVariableStorage = ++ (NorFlashDevices[Index].RegionBaseAddress <= ++ PcdGet32 (PcdFlashNvStorageVariableBase)) && ++ (PcdGet32 (PcdFlashNvStorageVariableBase) + ++ PcdGet32 (PcdFlashNvStorageVariableSize) <= ++ NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); ++ ++ Status = NorFlashCreateInstance ( ++ HostRegisterBaseAddress, ++ NorFlashDevices[Index].DeviceBaseAddress, ++ NorFlashDevices[Index].RegionBaseAddress, ++ NorFlashDevices[Index].Size, ++ Index, ++ NorFlashDevices[Index].BlockSize, ++ ContainVariableStorage, ++ &mNorFlashInstances[Index] ++ ); ++ if (EFI_ERROR (Status)) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n", ++ Index)); ++ continue; ++ } ++ Status = gBS->InstallMultipleProtocolInterfaces ( ++ &mNorFlashInstances[Index]->Handle, ++ &gEfiDevicePathProtocolGuid, ++ &mNorFlashInstances[Index]->DevicePath, ++ &gEfiFirmwareVolumeBlockProtocolGuid, ++ &mNorFlashInstances[Index]->FvbProtocol, ++ NULL ++ ); ++ ASSERT_EFI_ERROR (Status); ++ } ++ // Register for the virtual address change event. ++ Status = gBS->CreateEventEx ( ++ EVT_NOTIFY_SIGNAL, ++ TPL_NOTIFY, ++ NorFlashVirtualNotifyEvent, ++ NULL, ++ &gEfiEventVirtualAddressChangeGuid, ++ &mNorFlashVirtualAddrChangeEvent ++ ); ++ ASSERT_EFI_ERROR (Status); ++ ++ return Status; ++} ++ ++/** ++ Lock all pending read/write to Nor flash device ++ ++ @param[in] Context Nor flash device context structure. ++**/ ++VOID ++EFIAPI ++NorFlashLock ( ++ IN NOR_FLASH_LOCK_CONTEXT *Context ++ ) ++{ ++ if (!EfiAtRuntime ()) { ++ // Raise TPL to TPL_HIGH to stop anyone from interrupting us. ++ Context->OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); ++ } else { ++ Context->InterruptsEnabled = SaveAndDisableInterrupts (); ++ } ++} ++ ++/** ++ Unlock all pending read/write to Nor flash device ++ ++ @param[in] Context Nor flash device context structure. ++**/ ++VOID ++EFIAPI ++NorFlashUnlock ( ++ IN NOR_FLASH_LOCK_CONTEXT *Context ++ ) ++{ ++ if (!EfiAtRuntime ()) { ++ // Interruptions can resume. ++ gBS->RestoreTPL (Context->OriginalTPL); ++ } else if (Context->InterruptsEnabled) { ++ SetInterruptState (TRUE); ++ } ++} +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf +new file mode 100644 +index 00000000..4f20c3ba +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf +@@ -0,0 +1,70 @@ ++## @file ++# NOR flash DXE ++# ++# Copyright (c) 2023, ARM Limited. All rights reserved.
++# ++# SPDX-License-Identifier: BSD-2-Clause-Patent ++# ++## ++ ++[Defines] ++ INF_VERSION = 0x0001001B ++ BASE_NAME = CadenceQspiDxe ++ FILE_GUID = CC8A9713-4442-4A6C-B389-8B46490A0641 ++ MODULE_TYPE = DXE_RUNTIME_DRIVER ++ VERSION_STRING = 0.1 ++ ENTRY_POINT = NorFlashInitialise ++ ++[Sources] ++ CadenceQspiDxe.c ++ NorFlash.c ++ NorFlash.h ++ NorFlashFvb.c ++ ++[Packages] ++ EmbeddedPkg/EmbeddedPkg.dec ++ MdeModulePkg/MdeModulePkg.dec ++ MdePkg/MdePkg.dec ++ Platform/ARM/ARM.dec ++ Platform/ARM/N1Sdp/N1SdpPlatform.dec ++ ++[LibraryClasses] ++ BaseLib ++ BaseMemoryLib ++ DebugLib ++ DevicePathLib ++ DxeServicesTableLib ++ HobLib ++ IoLib ++ MemoryAllocationLib ++ NorFlashInfoLib ++ NorFlashPlatformLib ++ UefiBootServicesTableLib ++ UefiDriverEntryPoint ++ UefiLib ++ UefiRuntimeLib ++ UefiRuntimeServicesTableLib ++ ++[Guids] ++ gEdkiiNvVarStoreFormattedGuid ++ gEfiAuthenticatedVariableGuid ++ gEfiEventVirtualAddressChangeGuid ++ gEfiSystemNvDataFvGuid ++ gEfiVariableGuid ++ gEfiGlobalVariableGuid ++ ++[Protocols] ++ gEfiDevicePathProtocolGuid ++ gEfiFirmwareVolumeBlockProtocolGuid ++ ++[FixedPcd] ++ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize ++ ++[Depex] ++ gEfiCpuArchProtocolGuid +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h +new file mode 100644 +index 00000000..fe3b327c +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h +@@ -0,0 +1,31 @@ ++/** @file ++ ++ Copyright (c) 2023, ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#ifndef CADENCE_QSPI_REG_H_ ++#define CADENCE_QSPI_REG_H_ ++ ++// QSPI Controller defines ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET 0x90 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE 0x01 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE 0x01 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20 ++ ++#define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0 ++ ++#define CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET 0x94 ++ ++#endif /* CADENCE_QSPI_REG_H_ */ +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c +new file mode 100644 +index 00000000..188c75e2 +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c +@@ -0,0 +1,930 @@ ++/** @file ++ ++ Copyright (c) 2023 ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "NorFlash.h" ++ ++STATIC CONST NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = { ++ NOR_FLASH_SIGNATURE, // Signature ++ NULL, // Handle ++ ++ FALSE, // Initialized ++ NULL, // Initialize ++ ++ 0, // HostRegisterBaseAddress ++ 0, // DeviceBaseAddress ++ 0, // RegionBaseAddress ++ 0, // Size ++ 0, // BlockSize ++ 0, // LastBlock ++ 0, // StartLba ++ 0, // OffsetLba ++ ++ { ++ FvbGetAttributes, // GetAttributes ++ FvbSetAttributes, // SetAttributes ++ FvbGetPhysicalAddress, // GetPhysicalAddress ++ FvbGetBlockSize, // GetBlockSize ++ FvbRead, // Read ++ FvbWrite, // Write ++ FvbEraseBlocks, // EraseBlocks ++ NULL, //ParentHandle ++ }, // FvbProtoccol; ++ NULL, // ShadowBuffer ++ ++ { ++ { ++ { ++ HARDWARE_DEVICE_PATH, ++ HW_VENDOR_DP, ++ { ++ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End)), ++ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8) ++ } ++ }, ++ { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } }, ++ }, ++ 0, // Index ++ ++ { ++ END_DEVICE_PATH_TYPE, ++ END_ENTIRE_DEVICE_PATH_SUBTYPE, ++ { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } ++ } ++ ++ }, // DevicePath ++ 0 // Flags ++}; ++ ++/** ++ Execute Flash cmd ctrl and Read Status. ++ ++ @param[in] Instance NOR flash Instance. ++ @param[in] Val Value to be written to Flash cmd ctrl Register. ++ ++ @retval EFI_SUCCESS Request is executed successfully. ++ ++**/ ++STATIC ++EFI_STATUS ++CdnsQspiExecuteCommand ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINT32 Val ++ ) ++{ ++ // Set the command ++ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET, ++ Val); ++ // Execute the command ++ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET, ++ Val | CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE); ++ ++ // Wait until command has been executed ++ while ((MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET) ++ & CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT) == CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT) ++ continue; ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Create Nor flash Instance for given region. ++ ++ @param[in] HostRegisterBase Base address of Nor flash controller. ++ @param[in] NorFlashDeviceBase Base address of flash device. ++ @param[in] NorFlashRegionBase Base address of flash region on device. ++ @param[in] NorFlashSize Size of flash region. ++ @param[in] Index Index of given flash region. ++ @param[in] BlockSize Block size of NOR flash device. ++ @param[in] HasVarStore Boolean set for VarStore on given region. ++ @param[out] NorFlashInstance Instance of given flash region. ++ ++ @retval EFI_SUCCESS On successful creation of NOR flash instance. ++**/ ++EFI_STATUS ++NorFlashCreateInstance ( ++ IN UINTN HostRegisterBase, ++ IN UINTN NorFlashDeviceBase, ++ IN UINTN NorFlashRegionBase, ++ IN UINTN NorFlashSize, ++ IN UINT32 Index, ++ IN UINT32 BlockSize, ++ IN BOOLEAN HasVarStore, ++ OUT NOR_FLASH_INSTANCE** NorFlashInstance ++ ) ++{ ++ EFI_STATUS Status; ++ NOR_FLASH_INSTANCE* Instance; ++ NOR_FLASH_INFO *FlashInfo; ++ UINT8 JedecId[3]; ++ ++ ASSERT(NorFlashInstance != NULL); ++ Instance = AllocateRuntimeCopyPool (sizeof (mNorFlashInstanceTemplate), ++ &mNorFlashInstanceTemplate); ++ if (Instance == NULL) { ++ return EFI_OUT_OF_RESOURCES; ++ } ++ ++ Instance->HostRegisterBaseAddress = HostRegisterBase; ++ Instance->DeviceBaseAddress = NorFlashDeviceBase; ++ Instance->RegionBaseAddress = NorFlashRegionBase; ++ Instance->Size = NorFlashSize; ++ Instance->BlockSize = BlockSize; ++ Instance->LastBlock = (NorFlashSize / BlockSize) - 1; ++ ++ Instance->OffsetLba = (NorFlashRegionBase - NorFlashDeviceBase) / BlockSize; ++ ++ CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); ++ Instance->DevicePath.Index = (UINT8)Index; ++ ++ Status = NorFlashReadID (Instance, JedecId); ++ if (EFI_ERROR (Status)) { ++ goto FreeInstance; ++ } ++ ++ Status = NorFlashGetInfo (JedecId, &FlashInfo, TRUE); ++ if (EFI_ERROR (Status)) { ++ goto FreeInstance; ++ } ++ ++ NorFlashPrintInfo (FlashInfo); ++ ++ Instance->Flags = 0; ++ if (FlashInfo->Flags & NOR_FLASH_WRITE_FSR) { ++ Instance->Flags = NOR_FLASH_POLL_FSR; ++ } ++ ++ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize); ++ if (Instance->ShadowBuffer == NULL) { ++ Status = EFI_OUT_OF_RESOURCES; ++ goto FreeInstance; ++ } ++ ++ if (HasVarStore) { ++ Instance->Initialize = NorFlashFvbInitialize; ++ } ++ ++ *NorFlashInstance = Instance; ++ FreePool (FlashInfo); ++ return EFI_SUCCESS; ++ ++FreeInstance: ++ FreePool (Instance); ++ return Status; ++} ++ ++/** ++ Check whether NOR flash opertions are Locked. ++ ++ @param[in] Instance NOR flash Instance. ++ @param[in] BlockAddress BlockAddress in NOR flash device. ++ ++ @retval FALSE If NOR flash is not locked. ++**/ ++STATIC ++BOOLEAN ++NorFlashBlockIsLocked ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ) ++{ ++ return FALSE; ++} ++ ++/** ++ Unlock NOR flash operations on given block. ++ ++ @param[in] Instance NOR flash instance. ++ @param[in] BlockAddress BlockAddress in NOR flash device. ++ ++ @retval EFI_SUCCESS NOR flash operations is unlocked. ++**/ ++STATIC ++EFI_STATUS ++NorFlashUnlockSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ) ++{ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Unlock NOR flash operations if it is necessary. ++ ++ @param[in] Instance NOR flash instance. ++ @param[in] BlockAddress BlockAddress in NOR flash device. ++ ++ @retval EFI_SUCCESS Request is executed successfully. ++**/ ++STATIC ++EFI_STATUS ++NorFlashUnlockSingleBlockIfNecessary ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ) ++{ ++ EFI_STATUS Status; ++ ++ Status = EFI_SUCCESS; ++ ++ if (!NorFlashBlockIsLocked (Instance, BlockAddress)) { ++ Status = NorFlashUnlockSingleBlock (Instance, BlockAddress); ++ } ++ ++ return Status; ++} ++ ++/** ++ Enable write to NOR flash device. ++ ++ @param[in] Instance NOR flash instance. ++ ++ @retval EFI_SUCCESS Request is executed successfully. ++**/ ++STATIC ++EFI_STATUS ++NorFlashEnableWrite ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ) ++{ ++ ++ UINT32 val; ++ ++ DEBUG ((DEBUG_INFO, "NorFlashEnableWrite()\n")); ++ val = (SPINOR_OP_WREN << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS); ++ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ The following function presumes that the block has already been unlocked. ++ ++ @param[in] Instance NOR flash instance. ++ @param[in] BlockAddress Block address within the variable region. ++ ++ @retval EFI_SUCCESS Request is executed successfully. ++ **/ ++EFI_STATUS ++NorFlashEraseSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ) ++{ ++ ++ UINT32 DevConfigVal; ++ UINT32 EraseOffset; ++ ++ EraseOffset = 0x0; ++ ++ DEBUG ((DEBUG_INFO, "NorFlashEraseSingleBlock(BlockAddress=0x%08x)\n", ++ BlockAddress)); ++ ++ if (EFI_ERROR (NorFlashEnableWrite (Instance))) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ EraseOffset = BlockAddress - Instance->DeviceBaseAddress; ++ ++ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET, ++ EraseOffset); ++ ++ DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS; ++ ++ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ This function unlock and erase an entire NOR Flash block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] BlockAddress Block address within the variable store region. ++ ++ @retval EFI_SUCCESS The erase and unlock successfully completed. ++**/ ++EFI_STATUS ++NorFlashUnlockAndEraseSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ) ++{ ++ EFI_STATUS Status; ++ UINTN Index; ++ NOR_FLASH_LOCK_CONTEXT Lock; ++ NorFlashLock (&Lock); ++ ++ Index = 0; ++ do { ++ // Unlock the block if we have to ++ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress); ++ if (EFI_ERROR (Status)) { ++ break; ++ } ++ Status = NorFlashEraseSingleBlock (Instance, BlockAddress); ++ if (EFI_ERROR (Status)) { ++ break; ++ } ++ Index++; ++ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED)); ++ ++ if (Index == NOR_FLASH_ERASE_RETRY) { ++ DEBUG ((DEBUG_ERROR, ++ "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", ++ BlockAddress,Index)); ++ } ++ ++ NorFlashUnlock (&Lock); ++ ++ return Status; ++} ++ ++/** ++ Write a single word to given location. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] WordAddress The address in NOR flash to write given word. ++ @param[in] WriteData The data to write into NOR flash location. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++STATIC ++EFI_STATUS ++NorFlashWriteSingleWord ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN WordAddress, ++ IN UINT32 WriteData ++ ) ++{ ++ DEBUG ((DEBUG_INFO, ++ "NorFlashWriteSingleWord(WordAddress=0x%08x, WriteData=0x%08x)\n", ++ WordAddress, WriteData)); ++ ++ if (EFI_ERROR (NorFlashEnableWrite (Instance))) { ++ return EFI_DEVICE_ERROR; ++ } ++ MmioWrite32 (WordAddress, WriteData); ++ return EFI_SUCCESS; ++} ++ ++/** ++ Write a full block to given location. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The logical block address in NOR flash. ++ @param[in] DataBuffer The data to write into NOR flash location. ++ @param[in] BlockSizeInWords The number of bytes to write. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++STATIC ++EFI_STATUS ++NorFlashWriteFullBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINT32 *DataBuffer, ++ IN UINT32 BlockSizeInWords ++ ) ++{ ++ EFI_STATUS Status; ++ UINTN WordAddress; ++ UINT32 WordIndex; ++ UINTN BlockAddress; ++ NOR_FLASH_LOCK_CONTEXT Lock; ++ ++ Status = EFI_SUCCESS; ++ ++ // Get the physical address of the block ++ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, ++ BlockSizeInWords * 4); ++ ++ // Start writing from the first address at the start of the block ++ WordAddress = BlockAddress; ++ ++ NorFlashLock (&Lock); ++ ++ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); ++ if (EFI_ERROR (Status)) { ++ DEBUG ((DEBUG_ERROR, ++ "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", ++ BlockAddress)); ++ goto EXIT; ++ } ++ ++ for (WordIndex=0; ++ WordIndex < BlockSizeInWords; ++ WordIndex++, DataBuffer++, WordAddress += 4) { ++ Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer); ++ if (EFI_ERROR (Status)) { ++ goto EXIT; ++ } ++ } ++ ++EXIT: ++ NorFlashUnlock (&Lock); ++ ++ if (EFI_ERROR (Status)) { ++ DEBUG ((DEBUG_ERROR, ++ "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = %r.\n", ++ WordAddress, Status)); ++ } ++ return Status; ++} ++ ++/** ++ Write a full block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index. ++ @param[in] BufferSizeInBytes The number of bytes to read. ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashWriteBlocks ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN BufferSizeInBytes, ++ IN VOID *Buffer ++ ) ++{ ++ UINT32 *pWriteBuffer; ++ EFI_STATUS Status; ++ EFI_LBA CurrentBlock; ++ UINT32 BlockSizeInWords; ++ UINT32 NumBlocks; ++ UINT32 BlockCount; ++ ++ Status = EFI_SUCCESS; ++ // The buffer must be valid ++ if (Buffer == NULL) { ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ // We must have some bytes to read ++ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n", ++ BufferSizeInBytes)); ++ if (BufferSizeInBytes == 0) { ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // The size of the buffer must be a multiple of the block size ++ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n", ++ Instance->BlockSize)); ++ if ((BufferSizeInBytes % Instance->BlockSize) != 0) { ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // All blocks must be within the device ++ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize; ++ ++ DEBUG ((DEBUG_INFO, ++ "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks, ++ Instance->LastBlock, Lba)); ++ ++ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ ASSERT (((UINTN)Buffer % sizeof (UINT32)) == 0); ++ ++ BlockSizeInWords = Instance->BlockSize / 4; ++ ++ // Because the target *Buffer is a pointer to VOID, we must put ++ // all the data into a pointer to a proper data type, so use *ReadBuffer ++ pWriteBuffer = (UINT32 *)Buffer; ++ ++ CurrentBlock = Lba; ++ for (BlockCount = 0; ++ BlockCount < NumBlocks; ++ BlockCount++, CurrentBlock++, pWriteBuffer += BlockSizeInWords) { ++ ++ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Writing block #%d\n", ++ (UINTN)CurrentBlock)); ++ ++ Status = NorFlashWriteFullBlock ( ++ Instance, ++ CurrentBlock, ++ pWriteBuffer, ++ BlockSizeInWords ++ ); ++ ++ if (EFI_ERROR (Status)) { ++ break; ++ } ++ } ++ ++ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Exit Status = %r.\n", Status)); ++ return Status; ++} ++ ++/** ++ Read a full block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to read from. ++ @param[in] BufferSizeInBytes The number of bytes to read. ++ @param[out] Buffer The pointer to a caller-allocated buffer that ++ should be copied with read data. ++ ++ @retval EFI_SUCCESS The read is completed. ++**/ ++EFI_STATUS ++NorFlashReadBlocks ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN BufferSizeInBytes, ++ OUT VOID *Buffer ++ ) ++{ ++ UINT32 NumBlocks; ++ UINTN StartAddress; ++ DEBUG ((DEBUG_INFO, ++ "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n", ++ BufferSizeInBytes, Instance->BlockSize, Instance->LastBlock, ++ Lba)); ++ ++ // The buffer must be valid ++ if (Buffer == NULL) { ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ // Return if we do not have any byte to read ++ if (BufferSizeInBytes == 0) { ++ return EFI_SUCCESS; ++ } ++ ++ // The size of the buffer must be a multiple of the block size ++ if ((BufferSizeInBytes % Instance->BlockSize) != 0) { ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize; ++ ++ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashReadBlocks: ERROR - Read will exceed last block\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ // Get the address to start reading from ++ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, ++ Instance->BlockSize); ++ ++ // Readout the data ++ CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes); ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Read from nor flash. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to read from. ++ @param[in] Offset Offset into the block at which to begin reading. ++ @param[in] BufferSizeInBytes The number of bytes to read. ++ @param[out] Buffer The pointer to a caller-allocated buffer that ++ should copied with read data. ++ ++ @retval EFI_SUCCESS The read is completed. ++**/ ++EFI_STATUS ++NorFlashRead ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN UINTN BufferSizeInBytes, ++ OUT VOID *Buffer ++ ) ++{ ++ UINTN StartAddress; ++ // The buffer must be valid ++ if (Buffer == NULL) { ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ // Return if we do not have any byte to read ++ if (BufferSizeInBytes == 0) { ++ return EFI_SUCCESS; ++ } ++ ++ if (((Lba * Instance->BlockSize) + Offset + BufferSizeInBytes) > ++ Instance->Size) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashRead: ERROR - Read will exceed device size.\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ // Get the address to start reading from ++ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, ++ Instance->BlockSize); ++ ++ // Readout the data ++ CopyMem (Buffer, (UINTN *)(StartAddress + Offset), BufferSizeInBytes); ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Write a full or portion of a block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to write to. ++ @param[in] Offset Offset into the block at which to begin writing. ++ @param[in, out] NumBytes The total size of the buffer. ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashWriteSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN UINT8 *Buffer ++ ) ++{ ++ EFI_STATUS Status; ++ UINT32 Tmp; ++ UINT32 TmpBuf; ++ UINT32 WordToWrite; ++ UINT32 Mask; ++ BOOLEAN DoErase; ++ UINTN BytesToWrite; ++ UINTN CurOffset; ++ UINTN WordAddr; ++ UINTN BlockSize; ++ UINTN BlockAddress; ++ UINTN PrevBlockAddress; ++ ++ if (Buffer == NULL) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashWriteSingleBlock: ERROR - Buffer is invalid\n" )); ++ return EFI_OUT_OF_RESOURCES; ++ } ++ ++ PrevBlockAddress = 0; ++ if (!Instance->Initialized && Instance->Initialize) { ++ Instance->Initialize(Instance); ++ } ++ ++ DEBUG ((DEBUG_INFO, ++ "NorFlashWriteSingleBlock(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", ++ Lba, Offset, *NumBytes, Buffer)); ++ ++ // Localise the block size to avoid de-referencing pointers all the time ++ BlockSize = Instance->BlockSize; ++ ++ // The write must not span block boundaries. ++ // We need to check each variable individually because adding two large ++ // values together overflows. ++ if (Offset >= BlockSize || ++ *NumBytes > BlockSize || ++ (Offset + *NumBytes) > BlockSize) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", ++ Offset, *NumBytes, BlockSize )); ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // We must have some bytes to write ++ if (*NumBytes == 0) { ++ DEBUG ((DEBUG_ERROR, ++ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", ++ Offset, *NumBytes, BlockSize )); ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // Pick 128bytes as a good start for word operations as opposed to erasing the ++ // block and writing the data regardless if an erase is really needed. ++ // It looks like most individual NV variable writes are smaller than 128bytes. ++ if (*NumBytes <= 128) { ++ // Check to see if we need to erase before programming the data into NOR. ++ // If the destination bits are only changing from 1s to 0s we can just write. ++ // After a block is erased all bits in the block is set to 1. ++ // If any byte requires us to erase we just give up and rewrite all of it. ++ DoErase = FALSE; ++ BytesToWrite = *NumBytes; ++ CurOffset = Offset; ++ ++ while (BytesToWrite > 0) { ++ // Read full word from NOR, splice as required. A word is the smallest ++ // unit we can write. ++ Status = NorFlashRead ( ++ Instance, ++ Lba, ++ CurOffset & ~(0x3), ++ sizeof(Tmp), ++ &Tmp ++ ); ++ if (EFI_ERROR (Status)) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ // Physical address of word in NOR to write. ++ WordAddr = (CurOffset & ~(0x3)) + ++ GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, ++ BlockSize); ++ ++ // The word of data that is to be written. ++ TmpBuf = ReadUnaligned32 ((UINT32 *)(Buffer + (*NumBytes - BytesToWrite))); ++ ++ // First do word aligned chunks. ++ if ((CurOffset & 0x3) == 0) { ++ if (BytesToWrite >= 4) { ++ // Is the destination still in 'erased' state? ++ if (~Tmp != 0) { ++ // Check to see if we are only changing bits to zero. ++ if ((Tmp ^ TmpBuf) & TmpBuf) { ++ DoErase = TRUE; ++ break; ++ } ++ } ++ // Write this word to NOR ++ WordToWrite = TmpBuf; ++ CurOffset += sizeof(TmpBuf); ++ BytesToWrite -= sizeof(TmpBuf); ++ } else { ++ // BytesToWrite < 4. Do small writes and left-overs ++ Mask = ~((~0) << (BytesToWrite * 8)); ++ // Mask out the bytes we want. ++ TmpBuf &= Mask; ++ // Is the destination still in 'erased' state? ++ if ((Tmp & Mask) != Mask) { ++ // Check to see if we are only changing bits to zero. ++ if ((Tmp ^ TmpBuf) & TmpBuf) { ++ DoErase = TRUE; ++ break; ++ } ++ } ++ // Merge old and new data. Write merged word to NOR ++ WordToWrite = (Tmp & ~Mask) | TmpBuf; ++ CurOffset += BytesToWrite; ++ BytesToWrite = 0; ++ } ++ } else { ++ // Do multiple words, but starting unaligned. ++ if (BytesToWrite > (4 - (CurOffset & 0x3))) { ++ Mask = ((~0) << ((CurOffset & 0x3) * 8)); ++ // Mask out the bytes we want. ++ TmpBuf &= Mask; ++ // Is the destination still in 'erased' state? ++ if ((Tmp & Mask) != Mask) { ++ // Check to see if we are only changing bits to zero. ++ if ((Tmp ^ TmpBuf) & TmpBuf) { ++ DoErase = TRUE; ++ break; ++ } ++ } ++ // Merge old and new data. Write merged word to NOR ++ WordToWrite = (Tmp & ~Mask) | TmpBuf; ++ BytesToWrite -= (4 - (CurOffset & 0x3)); ++ CurOffset += (4 - (CurOffset & 0x3)); ++ } else { ++ // Unaligned and fits in one word. ++ Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8); ++ // Mask out the bytes we want. ++ TmpBuf = (TmpBuf << ((CurOffset & 0x3) * 8)) & Mask; ++ // Is the destination still in 'erased' state? ++ if ((Tmp & Mask) != Mask) { ++ // Check to see if we are only changing bits to zero. ++ if ((Tmp ^ TmpBuf) & TmpBuf) { ++ DoErase = TRUE; ++ break; ++ } ++ } ++ // Merge old and new data. Write merged word to NOR ++ WordToWrite = (Tmp & ~Mask) | TmpBuf; ++ CurOffset += BytesToWrite; ++ BytesToWrite = 0; ++ } ++ } ++ ++ BlockAddress = GET_NOR_BLOCK_ADDRESS ( ++ Instance->RegionBaseAddress, ++ Lba, ++ BlockSize ++ ); ++ if (BlockAddress != PrevBlockAddress) { ++ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress); ++ if (EFI_ERROR (Status)) { ++ return EFI_DEVICE_ERROR; ++ } ++ PrevBlockAddress = BlockAddress; ++ } ++ Status = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite); ++ if (EFI_ERROR (Status)) { ++ return EFI_DEVICE_ERROR; ++ } ++ } ++ // Exit if we got here and could write all the data. Otherwise do the ++ // Erase-Write cycle. ++ if (!DoErase) { ++ return EFI_SUCCESS; ++ } ++ } ++ ++ // Check we did get some memory. Buffer is BlockSize. ++ if (Instance->ShadowBuffer == NULL) { ++ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n")); ++ return EFI_DEVICE_ERROR; ++ } ++ ++ // Read NOR Flash data into shadow buffer ++ Status = NorFlashReadBlocks ( ++ Instance, ++ Lba, ++ BlockSize, ++ Instance->ShadowBuffer ++ ); ++ if (EFI_ERROR (Status)) { ++ // Return one of the pre-approved error statuses ++ return EFI_DEVICE_ERROR; ++ } ++ ++ // Put the data at the appropriate location inside the buffer area ++ CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes); ++ ++ // Write the modified buffer back to the NorFlash ++ Status = NorFlashWriteBlocks ( ++ Instance, ++ Lba, ++ BlockSize, ++ Instance->ShadowBuffer ++ ); ++ if (EFI_ERROR (Status)) { ++ // Return one of the pre-approved error statuses ++ return EFI_DEVICE_ERROR; ++ } ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Read JEDEC ID of NOR flash device. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[out] JedecId JEDEC ID of NOR flash device. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashReadID ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ OUT UINT8 JedecId[3] ++ ) ++{ ++ UINT32 val; ++ if (Instance == NULL || JedecId == NULL) { ++ return EFI_INVALID_PARAMETER; ++ } ++ ++ val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS; ++ ++ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ val = MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET); ++ ++ // Manu.ID field ++ JedecId[0] = (UINT8) val; ++ // Type field ++ JedecId[1] = (UINT8) (val >> 8); ++ // Capacity field ++ JedecId[2] = (UINT8) (val >> 16); ++ ++ DEBUG ((DEBUG_INFO, ++ "Nor flash detected, Jedec ID, Manu.Id=%x Type=%x Capacity=%x \n", ++ JedecId[0],JedecId[1],JedecId[2])); ++ ++ return EFI_SUCCESS; ++} +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h +new file mode 100644 +index 00000000..e720937e +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h +@@ -0,0 +1,484 @@ ++/** @file ++ ++ Copyright (c) 2023, ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#ifndef NOR_FLASH_DXE_H_ ++#define NOR_FLASH_DXE_H_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "CadenceQspiReg.h" ++ ++#define NOR_FLASH_ERASE_RETRY 10 ++ ++#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) \ ++ ((BaseAddr) + (UINTN)((Lba) * (LbaSize))) ++ ++#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r') ++#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, \ ++ NOR_FLASH_SIGNATURE) ++ ++#define NOR_FLASH_POLL_FSR BIT0 ++ ++typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; ++ ++typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance); ++ ++#pragma pack(1) ++typedef struct { ++ VENDOR_DEVICE_PATH Vendor; ++ UINT8 Index; ++ EFI_DEVICE_PATH_PROTOCOL End; ++} NOR_FLASH_DEVICE_PATH; ++#pragma pack() ++ ++struct _NOR_FLASH_INSTANCE { ++ UINT32 Signature; ++ EFI_HANDLE Handle; ++ ++ BOOLEAN Initialized; ++ NOR_FLASH_INITIALIZE Initialize; ++ ++ UINTN HostRegisterBaseAddress; ++ UINTN DeviceBaseAddress; ++ UINTN RegionBaseAddress; ++ UINTN Size; ++ UINTN BlockSize; ++ UINTN LastBlock; ++ EFI_LBA StartLba; ++ EFI_LBA OffsetLba; ++ ++ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; ++ VOID* ShadowBuffer; ++ ++ NOR_FLASH_DEVICE_PATH DevicePath; ++ ++ UINT32 Flags; ++}; ++ ++typedef struct { ++ EFI_TPL OriginalTPL; ++ BOOLEAN InterruptsEnabled; ++} NOR_FLASH_LOCK_CONTEXT; ++ ++/** ++ Lock all pending read/write to Nor flash device ++ ++ @param[in] Context Nor flash device context structure. ++**/ ++VOID ++EFIAPI ++NorFlashLock ( ++ IN NOR_FLASH_LOCK_CONTEXT *Context ++ ); ++ ++/** ++ Unlock all pending read/write to Nor flash device ++ ++ @param[in] Context Nor flash device context structure. ++**/ ++VOID ++EFIAPI ++NorFlashUnlock ( ++ IN NOR_FLASH_LOCK_CONTEXT *Context ++ ); ++ ++extern UINTN mFlashNvStorageVariableBase; ++ ++/** ++ Create Nor flash Instance for given region. ++ ++ @param[in] HostRegisterBase Base address of Nor flash controller. ++ @param[in] NorFlashDeviceBase Base address of flash device. ++ @param[in] NorFlashRegionBase Base address of flash region on device. ++ @param[in] NorFlashSize Size of flash region. ++ @param[in] Index Index of given flash region. ++ @param[in] BlockSize Block size of NOR flash device. ++ @param[in] HasVarStore Boolean set for VarStore on given region. ++ @param[out] NorFlashInstance Instance of given flash region. ++ ++ @retval EFI_SUCCESS On successful creation of NOR flash instance. ++**/ ++EFI_STATUS ++NorFlashCreateInstance ( ++ IN UINTN HostRegisterBase, ++ IN UINTN NorFlashDeviceBase, ++ IN UINTN NorFlashRegionBase, ++ IN UINTN NorFlashSize, ++ IN UINT32 Index, ++ IN UINT32 BlockSize, ++ IN BOOLEAN HasVarStore, ++ OUT NOR_FLASH_INSTANCE** NorFlashInstance ++ ); ++ ++/** ++ Install Fv block on to variable store region ++ ++ @param[in] Instance Instance of Nor flash variable region. ++ ++ @retval EFI_SUCCESS The entry point is executed successfully. ++**/ ++EFI_STATUS ++EFIAPI ++NorFlashFvbInitialize ( ++ IN NOR_FLASH_INSTANCE* Instance ++ ); ++ ++/** ++ Check the integrity of firmware volume header. ++ ++ @param[in] Instance Instance of Nor flash variable region. ++ ++ @retval EFI_SUCCESS The firmware volume is consistent. ++ @retval EFI_NOT_FOUND The firmware volume has been corrupted. ++ ++**/ ++EFI_STATUS ++ValidateFvHeader ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ); ++ ++/** ++ Initialize the FV Header and Variable Store Header ++ to support variable operations. ++ ++ @param[in] Instance Location to Initialize the headers ++ ++ @retval EFI_SUCCESS Fv init is done ++ ++**/ ++EFI_STATUS ++InitializeFvAndVariableStoreHeaders ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ); ++ ++/** ++ Retrieves the attributes and current settings of the block. ++ ++ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and ++ current settings are returned. ++ Type EFI_FVB_ATTRIBUTES_2 is defined in ++ EFI_FIRMWARE_VOLUME_HEADER. ++ ++ @retval EFI_SUCCESS The firmware volume attributes were returned. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetAttributes( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ OUT EFI_FVB_ATTRIBUTES_2 *Attributes ++ ); ++ ++/** ++ Sets configurable firmware volume attributes and returns the ++ new settings of the firmware volume. ++ ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in, out] Attributes On input, Attributes is a pointer to ++ EFI_FVB_ATTRIBUTES_2 that contains the desired ++ firmware volume settings. ++ On successful return, it contains the new ++ settings of the firmware volume. ++ ++ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbSetAttributes( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes ++ ); ++ ++/** ++ Retrieves the base address of a memory-mapped firmware volume. ++ This function should be called only for memory-mapped firmware volumes. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[out] Address Pointer to a caller-allocated ++ EFI_PHYSICAL_ADDRESS that, on successful ++ return from GetPhysicalAddress(), contains the ++ base address of the firmware volume. ++ ++ @retval EFI_SUCCESS The firmware volume base address was returned. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetPhysicalAddress( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ OUT EFI_PHYSICAL_ADDRESS *Address ++ ); ++ ++/** ++ Retrieves the size of the requested block. ++ It also returns the number of additional blocks with the identical size. ++ The GetBlockSize() function is used to retrieve the block map ++ (see EFI_FIRMWARE_VOLUME_HEADER). ++ ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba Indicates the block whose size to return ++ ++ @param[out] BlockSize Pointer to a caller-allocated UINTN in which ++ the size of the block is returned. ++ ++ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in ++ which the number of consecutive blocks, ++ starting with Lba, is returned. All ++ blocks in this range have a size of ++ BlockSize. ++ ++ @retval EFI_SUCCESS The firmware volume base address was returned. ++ ++ @retval EFI_INVALID_PARAMETER The requested LBA is out of range. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetBlockSize( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ OUT UINTN *BlockSize, ++ OUT UINTN *NumberOfBlocks ++ ); ++ ++/** ++ Reads the specified number of bytes into a buffer from the specified block. ++ ++ The Read() function reads the requested number of bytes from the ++ requested block and stores them in the provided buffer. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba The starting logical block index from which to read ++ ++ @param[in] Offset Offset into the block at which to begin reading. ++ ++ @param[in, out] NumBytes Pointer to a UINTN. ++ At entry, *NumBytes contains the total size of the ++ buffer. *NumBytes should have a non zero value. ++ At exit, *NumBytes contains the total number of ++ bytes read. ++ ++ @param[in out] Buffer Pointer to a caller-allocated buffer that will be ++ used to hold the data that is read. ++ ++ @retval EFI_SUCCESS The firmware volume was read successfully, and ++ contents are in Buffer. ++ ++ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. ++ ++ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and ++ could not be read. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbRead( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN OUT UINT8 *Buffer ++ ); ++ ++/** ++ Writes the specified number of bytes from the input buffer to the block. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba The starting logical block index to write to. ++ ++ @param[in] Offset Offset into the block at which to begin writing. ++ ++ @param[in, out] NumBytes The pointer to a UINTN. ++ At entry, *NumBytes contains the total size of the ++ buffer. ++ At exit, *NumBytes contains the total number of ++ bytes actually written. ++ ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The firmware volume was written successfully. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbWrite( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN UINT8 *Buffer ++ ); ++ ++/** ++ Erases and initialises a firmware volume block. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL ++ ++ @param[in] ... The variable argument list is a list of tuples. ++ Each tuple describes a range of LBAs to erase ++ and consists of the following: ++ - An EFI_LBA that indicates the starting LBA ++ - A UINTN that indicates the number of blocks ++ to erase. ++ ++ The list is terminated with an ++ EFI_LBA_LIST_TERMINATOR. ++ ++ @retval EFI_SUCCESS The erase request successfully completed. ++ ++ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled ++ state. ++ ++ @retval EFI_DEVICE_ERROR The block device is not functioning correctly ++ and could not be written. ++ The firmware device may have been partially ++ erased. ++ ++ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable ++ argument list do not exist in the firmware ++ volume. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbEraseBlocks( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ ... ++ ); ++ ++/** ++ This function unlock and erase an entire NOR Flash block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] BlockAddress Block address within the variable store region. ++ ++ @retval EFI_SUCCESS The erase and unlock successfully completed. ++**/ ++EFI_STATUS ++NorFlashUnlockAndEraseSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN UINTN BlockAddress ++ ); ++ ++/** ++ Write a full or portion of a block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to write to. ++ @param[in] Offset Offset into the block at which to begin writing. ++ @param[in,out] NumBytes The total size of the buffer. ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashWriteSingleBlock ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN UINT8 *Buffer ++ ); ++ ++/** ++ Write a full block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to write to. ++ @param[in] BufferSizeInBytes The number of bytes to write. ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashWriteBlocks ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN BufferSizeInBytes, ++ IN VOID *Buffer ++ ); ++ ++/** ++ Read a full block. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to read from. ++ @param[in] BufferSizeInBytes The number of bytes to read. ++ @param[out] Buffer The pointer to a caller-allocated buffer that ++ should be copied with read data. ++ ++ @retval EFI_SUCCESS The read is completed. ++**/ ++EFI_STATUS ++NorFlashReadBlocks ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN BufferSizeInBytes, ++ OUT VOID *Buffer ++ ); ++ ++/** ++ Read from nor flash. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[in] Lba The starting logical block index to read from. ++ @param[in] Offset Offset into the block at which to begin reading. ++ @param[in] BufferSizeInBytes The number of bytes to read. ++ @param[out] Buffer The pointer to a caller-allocated buffer that ++ should copied with read data. ++ ++ @retval EFI_SUCCESS The read is completed. ++**/ ++EFI_STATUS ++NorFlashRead ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN UINTN BufferSizeInBytes, ++ OUT VOID *Buffer ++ ); ++ ++/** ++ Read JEDEC ID of NOR flash device. ++ ++ @param[in] Instance NOR flash Instance of variable store region. ++ @param[out] JedecId JEDEC ID of NOR flash device. ++ ++ @retval EFI_SUCCESS The write is completed. ++**/ ++EFI_STATUS ++NorFlashReadID ( ++ IN NOR_FLASH_INSTANCE *Instance, ++ OUT UINT8 JedecId[3] ++ ); ++ ++#define SPINOR_OP_WREN 0x06 // Write enable ++#define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block ++#define SPINOR_OP_RDID 0x9f // Read JEDEC ID ++ ++#endif /* NOR_FLASH_DXE_H_ */ +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c +new file mode 100644 +index 00000000..edd84c07 +--- /dev/null ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c +@@ -0,0 +1,573 @@ ++/** @file ++ ++ Copyright (c) 2023, ARM Limited. All rights reserved.
++ ++ SPDX-License-Identifier: BSD-2-Clause-Patent ++ ++**/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "NorFlash.h" ++ ++UINTN mFlashNvStorageVariableBase; ++ ++/** ++ Initialize the FV Header and Variable Store Header ++ to support variable operations. ++ ++ @param[in] Instance Location to initialise the headers. ++ ++ @retval EFI_SUCCESS Fv init is done. ++ ++**/ ++EFI_STATUS ++InitializeFvAndVariableStoreHeaders ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ) ++{ ++ EFI_STATUS Status; ++ VOID* Headers; ++ UINTN HeadersLength; ++ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; ++ VARIABLE_STORE_HEADER *VariableStoreHeader; ++ ++ if (!Instance->Initialized && Instance->Initialize) { ++ Instance->Initialize (Instance); ++ } ++ ++ HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + ++ sizeof (EFI_FV_BLOCK_MAP_ENTRY) + ++ sizeof (VARIABLE_STORE_HEADER); ++ Headers = AllocateZeroPool (HeadersLength); ++ ++ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers; ++ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid); ++ FirmwareVolumeHeader->FvLength = ++ PcdGet32 (PcdFlashNvStorageVariableSize) + ++ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + ++ PcdGet32 (PcdFlashNvStorageFtwSpareSize); ++ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE; ++ FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP | ++ EFI_FVB2_READ_STATUS | ++ EFI_FVB2_STICKY_WRITE | ++ EFI_FVB2_MEMORY_MAPPED | ++ EFI_FVB2_ERASE_POLARITY | ++ EFI_FVB2_WRITE_STATUS | ++ EFI_FVB2_WRITE_ENABLED_CAP; ++ ++ FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + ++ sizeof (EFI_FV_BLOCK_MAP_ENTRY); ++ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION; ++ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->LastBlock + 1; ++ FirmwareVolumeHeader->BlockMap[0].Length = Instance->BlockSize; ++ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0; ++ FirmwareVolumeHeader->BlockMap[1].Length = 0; ++ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ( ++ (UINT16*)FirmwareVolumeHeader, ++ FirmwareVolumeHeader->HeaderLength); ++ ++ VariableStoreHeader = (VOID *)((UINTN)Headers + ++ FirmwareVolumeHeader->HeaderLength); ++ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid); ++ VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) - ++ FirmwareVolumeHeader->HeaderLength; ++ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED; ++ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY; ++ ++ // Install the combined super-header in the NorFlash ++ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers); ++ ++ FreePool (Headers); ++ return Status; ++} ++ ++/** ++ Check the integrity of firmware volume header. ++ ++ @param[in] Instance Instance of Nor flash variable region. ++ ++ @retval EFI_SUCCESS The firmware volume is consistent. ++ @retval EFI_NOT_FOUND The firmware volume has been corrupted. ++ ++**/ ++EFI_STATUS ++ValidateFvHeader ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ) ++{ ++ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; ++ VARIABLE_STORE_HEADER *VariableStoreHeader; ++ UINTN VariableStoreLength; ++ UINTN FvLength; ++ ++ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress; ++ ++ FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + ++ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + ++ PcdGet32 (PcdFlashNvStorageFtwSpareSize); ++ ++ if ((FwVolHeader->Revision != EFI_FVH_REVISION) ++ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE) ++ || (FwVolHeader->FvLength != FvLength) ++ ) ++ { ++ DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", ++ __FUNCTION__)); ++ return EFI_NOT_FOUND; ++ } ++ ++ // Check the Firmware Volume Guid ++ if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) { ++ DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", ++ __FUNCTION__)); ++ return EFI_NOT_FOUND; ++ } ++ ++ VariableStoreHeader = (VOID *)((UINTN)FwVolHeader + ++ FwVolHeader->HeaderLength); ++ ++ // Check the Variable Store Guid ++ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && ++ !CompareGuid (&VariableStoreHeader->Signature, ++ &gEfiAuthenticatedVariableGuid)) { ++ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n", ++ __FUNCTION__)); ++ return EFI_NOT_FOUND; ++ } ++ ++ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - ++ FwVolHeader->HeaderLength; ++ if (VariableStoreHeader->Size != VariableStoreLength) { ++ DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", ++ __FUNCTION__)); ++ return EFI_NOT_FOUND; ++ } ++ return EFI_SUCCESS; ++} ++ ++/** ++ Retrieves the attributes and current settings of the block. ++ ++ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and ++ current settings are returned. ++ Type EFI_FVB_ATTRIBUTES_2 is defined in ++ EFI_FIRMWARE_VOLUME_HEADER. ++ ++ @retval EFI_SUCCESS The firmware volume attributes were returned. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetAttributes( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ OUT EFI_FVB_ATTRIBUTES_2 *Attributes ++ ) ++{ ++ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; ++ ++ FlashFvbAttributes = EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS | ++ EFI_FVB2_WRITE_ENABLED_CAP | EFI_FVB2_WRITE_STATUS | ++ EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED | ++ EFI_FVB2_ERASE_POLARITY; ++ ++ *Attributes = FlashFvbAttributes; ++ ++ DEBUG ((DEBUG_INFO, "FvbGetAttributes(0x%X)\n", *Attributes)); ++ ++ return EFI_SUCCESS; ++} ++ ++/** ++ Sets configurable firmware volume attributes and returns the ++ new settings of the firmware volume. ++ ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in, out] Attributes On input, Attributes is a pointer to ++ EFI_FVB_ATTRIBUTES_2 that contains the desired ++ firmware volume settings. ++ On successful return, it contains the new ++ settings of the firmware volume. ++ ++ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbSetAttributes( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes ++ ) ++{ ++ DEBUG ((DEBUG_INFO, "FvbSetAttributes(0x%X) is not supported\n", ++ *Attributes)); ++ return EFI_UNSUPPORTED; ++} ++ ++/** ++ Retrieves the base address of a memory-mapped firmware volume. ++ This function should be called only for memory-mapped firmware volumes. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[out] Address Pointer to a caller-allocated ++ EFI_PHYSICAL_ADDRESS that, on successful ++ return from GetPhysicalAddress(), contains the ++ base address of the firmware volume. ++ ++ @retval EFI_SUCCESS The firmware volume base address was returned. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetPhysicalAddress ( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ OUT EFI_PHYSICAL_ADDRESS *Address ++ ) ++{ ++ NOR_FLASH_INSTANCE *Instance; ++ ++ Instance = INSTANCE_FROM_FVB_THIS (This); ++ ++ DEBUG ((DEBUG_INFO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n", ++ Instance->RegionBaseAddress)); ++ ++ ASSERT(Address != NULL); ++ ++ *Address = Instance->RegionBaseAddress; ++ return EFI_SUCCESS; ++} ++ ++/** ++ Retrieves the size of the requested block. ++ It also returns the number of additional blocks with the identical size. ++ The GetBlockSize() function is used to retrieve the block map ++ (see EFI_FIRMWARE_VOLUME_HEADER). ++ ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba Indicates the block whose size to return ++ ++ @param[out] BlockSize Pointer to a caller-allocated UINTN in which ++ the size of the block is returned. ++ ++ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in ++ which the number of consecutive blocks, ++ starting with Lba, is returned. All ++ blocks in this range have a size of ++ BlockSize. ++ ++ @retval EFI_SUCCESS The firmware volume base address was returned. ++ ++ @retval EFI_INVALID_PARAMETER The requested LBA is out of range. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbGetBlockSize ( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ OUT UINTN *BlockSize, ++ OUT UINTN *NumberOfBlocks ++ ) ++{ ++ EFI_STATUS Status; ++ NOR_FLASH_INSTANCE *Instance; ++ ++ Instance = INSTANCE_FROM_FVB_THIS (This); ++ ++ DEBUG ((DEBUG_INFO, ++ "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba, ++ Instance->BlockSize, Instance->LastBlock)); ++ ++ if (Lba > Instance->LastBlock) { ++ DEBUG ((DEBUG_ERROR, ++ "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n", ++ Lba, Instance->LastBlock)); ++ Status = EFI_INVALID_PARAMETER; ++ } else { ++ // This is easy because in this platform each NorFlash device has equal sized blocks. ++ *BlockSize = (UINTN) Instance->BlockSize; ++ *NumberOfBlocks = (UINTN) (Instance->LastBlock - Lba + 1); ++ ++ DEBUG ((DEBUG_INFO, ++ "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize, ++ *NumberOfBlocks)); ++ ++ Status = EFI_SUCCESS; ++ } ++ ++ return Status; ++} ++ ++/** ++ Reads the specified number of bytes into a buffer from the specified block. ++ ++ The Read() function reads the requested number of bytes from the ++ requested block and stores them in the provided buffer. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba The starting logical block index from which to read ++ ++ @param[in] Offset Offset into the block at which to begin reading. ++ ++ @param[in, out] NumBytes Pointer to a UINTN. ++ At entry, *NumBytes contains the total size of the ++ buffer. *NumBytes should have a non zero value. ++ At exit, *NumBytes contains the total number of ++ bytes read. ++ ++ @param[in, out] Buffer Pointer to a caller-allocated buffer that will be ++ used to hold the data that is read. ++ ++ @retval EFI_SUCCESS The firmware volume was read successfully, and ++ contents are in Buffer. ++ ++ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. ++ ++ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and ++ could not be read. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbRead ( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN OUT UINT8 *Buffer ++ ) ++{ ++ EFI_STATUS Status; ++ UINTN BlockSize; ++ NOR_FLASH_INSTANCE *Instance; ++ ++ Instance = INSTANCE_FROM_FVB_THIS (This); ++ ++ DEBUG ((DEBUG_INFO, ++ "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", ++ Instance->StartLba + Lba, Offset, *NumBytes, Buffer)); ++ ++ if (!Instance->Initialized && Instance->Initialize) { ++ Instance->Initialize(Instance); ++ } ++ ++ BlockSize = Instance->BlockSize; ++ ++ DEBUG ((DEBUG_INFO, ++ "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n", ++ Offset, *NumBytes, BlockSize )); ++ ++ // The read must not span block boundaries. ++ // We need to check each variable individually because adding two large ++ // values together overflows. ++ if (Offset >= BlockSize || ++ *NumBytes > BlockSize || ++ (Offset + *NumBytes) > BlockSize) { ++ DEBUG ((DEBUG_ERROR, ++ "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", ++ Offset, *NumBytes, BlockSize )); ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // We must have some bytes to read ++ if (*NumBytes == 0) { ++ return EFI_BAD_BUFFER_SIZE; ++ } ++ ++ // Decide if we are doing full block reads or not. ++ if (*NumBytes % BlockSize != 0) { ++ Status = NorFlashRead (Instance, Instance->StartLba + Lba, Offset, ++ *NumBytes, Buffer); ++ } else { ++ // Read NOR Flash data into shadow buffer ++ Status = NorFlashReadBlocks (Instance, Instance->StartLba + Lba, ++ BlockSize, Buffer); ++ } ++ if (EFI_ERROR (Status)) { ++ // Return one of the pre-approved error statuses ++ return EFI_DEVICE_ERROR; ++ } ++ return EFI_SUCCESS; ++} ++ ++/** ++ Writes the specified number of bytes from the input buffer to the block. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. ++ ++ @param[in] Lba The starting logical block index to write to. ++ ++ @param[in] Offset Offset into the block at which to begin writing. ++ ++ @param[in, out] NumBytes The pointer to a UINTN. ++ At entry, *NumBytes contains the total size of the ++ buffer. ++ At exit, *NumBytes contains the total number of ++ bytes actually written. ++ ++ @param[in] Buffer The pointer to a caller-allocated buffer that ++ contains the source for the write. ++ ++ @retval EFI_SUCCESS The firmware volume was written successfully. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbWrite ( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ IN EFI_LBA Lba, ++ IN UINTN Offset, ++ IN OUT UINTN *NumBytes, ++ IN UINT8 *Buffer ++ ) ++{ ++ NOR_FLASH_INSTANCE *Instance; ++ ++ Instance = INSTANCE_FROM_FVB_THIS (This); ++ ++ return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset, ++ NumBytes, Buffer); ++} ++ ++/** ++ Erases and initialises a firmware volume block. ++ ++ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL ++ ++ @param[in] ... The variable argument list is a list of tuples. ++ Each tuple describes a range of LBAs to erase ++ and consists of the following: ++ - An EFI_LBA that indicates the starting LBA ++ - A UINTN that indicates the number of blocks ++ to erase. ++ ++ The list is terminated with an ++ EFI_LBA_LIST_TERMINATOR. ++ ++ @retval EFI_SUCCESS The erase request successfully completed. ++ ++ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled ++ state. ++ ++ @retval EFI_DEVICE_ERROR The block device is not functioning correctly ++ and could not be written. ++ The firmware device may have been partially ++ erased. ++ ++ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable ++ argument list do not exist in the firmware ++ volume. ++ ++**/ ++EFI_STATUS ++EFIAPI ++FvbEraseBlocks ( ++ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, ++ ... ++ ) ++{ ++ EFI_STATUS Status; ++ VA_LIST Args; ++ UINTN BlockAddress; // Physical address of Lba to erase ++ EFI_LBA StartingLba; // Lba from which we start erasing ++ UINTN NumOfLba; // Number of Lba blocks to erase ++ NOR_FLASH_INSTANCE *Instance; ++ ++ Instance = INSTANCE_FROM_FVB_THIS (This); ++ ++ DEBUG ((DEBUG_INFO, "FvbEraseBlocks()\n")); ++ ++ Status = EFI_SUCCESS; ++ ++ // Before erasing, check the entire list of parameters to ensure ++ // all specified blocks are valid ++ ++ VA_START (Args, This); ++ do { ++ // Get the Lba from which we start erasing ++ StartingLba = VA_ARG (Args, EFI_LBA); ++ ++ // Have we reached the end of the list? ++ if (StartingLba == EFI_LBA_LIST_TERMINATOR) { ++ break; ++ } ++ ++ // How many Lba blocks are we requested to erase? ++ NumOfLba = VA_ARG (Args, UINT32); ++ ++ // All blocks must be within range ++ DEBUG ((DEBUG_INFO, ++ "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n", ++ Instance->StartLba + StartingLba, NumOfLba, Instance->LastBlock)); ++ if (NumOfLba == 0 || ++ (Instance->StartLba + StartingLba + NumOfLba - 1) > ++ Instance->LastBlock) { ++ VA_END (Args); ++ DEBUG ((DEBUG_ERROR, ++ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n")); ++ return EFI_INVALID_PARAMETER; ++ } ++ } while (TRUE); ++ VA_END (Args); ++ ++ VA_START (Args, This); ++ do { ++ // Get the Lba from which we start erasing ++ StartingLba = VA_ARG (Args, EFI_LBA); ++ ++ // Have we reached the end of the list? ++ if (StartingLba == EFI_LBA_LIST_TERMINATOR) { ++ // Exit the while loop ++ break; ++ } ++ ++ // How many Lba blocks are we requested to erase? ++ NumOfLba = VA_ARG (Args, UINT32); ++ ++ // Go through each one and erase it ++ while (NumOfLba > 0) { ++ ++ // Get the physical address of Lba to erase ++ BlockAddress = GET_NOR_BLOCK_ADDRESS ( ++ Instance->RegionBaseAddress, ++ Instance->StartLba + StartingLba, ++ Instance->BlockSize ++ ); ++ ++ // Erase it ++ DEBUG ((DEBUG_INFO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n", ++ Instance->StartLba + StartingLba, BlockAddress)); ++ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); ++ if (EFI_ERROR(Status)) { ++ VA_END (Args); ++ return EFI_DEVICE_ERROR; ++ } ++ ++ // Move to the next Lba ++ StartingLba++; ++ NumOfLba--; ++ } ++ } while (TRUE); ++ VA_END (Args); ++ ++ return Status; ++ ++} +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec +index 16937197..986a078f 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec +@@ -1,7 +1,7 @@ + ## @file + # Describes the N1Sdp configuration. + # +-# Copyright (c) 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2021-2022, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + ## +@@ -89,3 +89,6 @@ + # unmapped reserved region results in a DECERR response. + # + gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 ++ ++ # Base address of Cadence QSPI controller configuration registers ++ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress|0x1C0C0000|UINT32|0x0000004A diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch new file mode 100644 index 0000000000..197a6eca48 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0007-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch @@ -0,0 +1,88 @@ +From e79fd5cfa3190eb27a9637facc9891cab55b5e09 Mon Sep 17 00:00:00 2001 +From: sahil +Date: Mon, 2 May 2022 19:24:47 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: Persistent storage for N1Sdp + +Enable persistent storage on QSPI flash device. + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: I403113bb885d1d411d433a7f266715d007509a5e +--- + Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 18 +++++++++++++----- + Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 4 +++- + 2 files changed, 16 insertions(+), 6 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +index 676ab677..80bc875a 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +@@ -44,6 +44,9 @@ + # file explorer library support + FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf + ++ # NOR flash support ++ NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf ++ + [LibraryClasses.common.SEC] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +@@ -161,11 +164,9 @@ + # ACPI Table Version + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + +- # Runtime Variable storage +- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 +- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE +- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 +- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 ++ # NOR flash support ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000 ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000 + + ################################################################################ + # +@@ -197,6 +198,12 @@ + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F + } + ++ # NOR flash support ++ Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf { ++ ++ NorFlashPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf ++ } ++ + # Architectural Protocols + ArmPkg/Drivers/CpuDxe/CpuDxe.inf + ArmPkg/Drivers/ArmGic/ArmGicDxe.inf +@@ -217,6 +224,7 @@ + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf ++ NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } + +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf +index e5e24ea5..4329f892 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf +@@ -1,7 +1,7 @@ + ## @file + # FDF file of N1Sdp + # +-# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
++# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
+ # + # SPDX-License-Identifier: BSD-2-Clause-Patent + ## +@@ -140,6 +140,8 @@ READ_LOCK_STATUS = TRUE + INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + ++ INF Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf ++ + INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch new file mode 100644 index 0000000000..3951b48be4 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0008-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch @@ -0,0 +1,50 @@ +From 5e8fbb3ba0f634f7fc873c6577269845f9e243db Mon Sep 17 00:00:00 2001 +From: sahil +Date: Mon, 2 May 2022 19:28:19 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: Enable FaultTolerantWrite Dxe driver for + N1Sdp + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: If448ad95b2e72cef31ce1e1e5ab2504d607f0545 +--- + Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +++++ + Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 + + 2 files changed, 6 insertions(+) + +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +index 80bc875a..90a0d5b6 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc +@@ -165,6 +165,10 @@ + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 + + # NOR flash support ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x18F40000 ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000 ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x18F20000 ++ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00020000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000 + +@@ -227,6 +231,7 @@ + NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + } ++ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + + # ACPI Support + MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf +index 4329f892..17d370a3 100644 +--- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf ++++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf +@@ -90,6 +90,7 @@ READ_LOCK_STATUS = TRUE + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf ++ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch new file mode 100644 index 0000000000..8e14699585 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/edk2-platforms/0009-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch @@ -0,0 +1,197 @@ +From 6d274379f584a638c1f2b4b8a19014d4baef1d9f Mon Sep 17 00:00:00 2001 +From: sahil +Date: Thu, 11 Aug 2022 11:26:29 +0530 +Subject: [PATCH] Platform/ARM/N1Sdp: manually poll QSPI status bit after + erase/write + +This patch adds a function to poll Nor flash memory's status register +bit (WIP bit) to wait for an erase/write operation to complete. +The polling timeout is set to 1 second. + +Upstream-Status: Pending +Signed-off-by: Xueliang Zhong +Signed-off-by: sahil +Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4 +--- + .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 1 + + .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 6 +- + .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 80 ++++++++++++++++++- + .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 5 ++ + 4 files changed, 88 insertions(+), 4 deletions(-) + +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf +index 4f20c3ba..7a39eb2d 100644 +--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf +@@ -39,6 +39,7 @@ + MemoryAllocationLib + NorFlashInfoLib + NorFlashPlatformLib ++ TimerLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h +index fe3b327c..1971631d 100644 +--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h +@@ -16,13 +16,15 @@ + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02 +-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03 +-#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23 + #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C 0x8 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS 7 ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS) ++#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS) + + #define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0 + +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c +index 188c75e2..6832351a 100644 +--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c +@@ -10,6 +10,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -184,6 +185,74 @@ FreeInstance: + return Status; + } + ++/** ++ Converts milliseconds into number of ticks of the performance counter. ++ ++ @param[in] Milliseconds Milliseconds to convert into ticks. ++ ++ @retval Milliseconds expressed as number of ticks. ++ ++**/ ++STATIC ++UINT64 ++MilliSecondsToTicks ( ++ IN UINTN Milliseconds ++ ) ++{ ++ CONST UINT64 NanoSecondsPerTick = GetTimeInNanoSecond (1); ++ ++ return (Milliseconds * 1000000) / NanoSecondsPerTick; ++} ++ ++/** ++ Poll Status register for NOR flash erase/write completion. ++ ++ @param[in] Instance NOR flash Instance. ++ ++ @retval EFI_SUCCESS Request is executed successfully. ++ @retval EFI_TIMEOUT Operation timed out. ++ @retval EFI_DEVICE_ERROR Controller operartion failed. ++ ++**/ ++STATIC ++EFI_STATUS ++NorFlashPollStatusRegister ( ++ IN NOR_FLASH_INSTANCE *Instance ++ ) ++{ ++ BOOLEAN SRegDone; ++ UINT32 val; ++ ++ val = SPINOR_OP_RDSR << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(1) | ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C << CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS; ++ ++ CONST UINT64 TickOut = ++ GetPerformanceCounter () + MilliSecondsToTicks (SPINOR_SR_WIP_POLL_TIMEOUT_MS); ++ ++ do { ++ if (GetPerformanceCounter () > TickOut) { ++ DEBUG (( ++ DEBUG_ERROR, ++ "NorFlashPollStatusRegister: Timeout waiting for erase/write.\n" ++ )); ++ return EFI_TIMEOUT; ++ } ++ ++ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { ++ return EFI_DEVICE_ERROR; ++ } ++ ++ SRegDone = ++ (MmioRead8 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET) ++ & SPINOR_SR_WIP) == 0; ++ ++ } while (!SRegDone); ++ ++ return EFI_SUCCESS; ++} ++ + /** + Check whether NOR flash opertions are Locked. + +@@ -305,12 +374,16 @@ NorFlashEraseSingleBlock ( + + DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | + CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS | +- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS; ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(3); + + if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) { + return EFI_DEVICE_ERROR; + } + ++ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) { ++ return EFI_DEVICE_ERROR; ++ } ++ + return EFI_SUCCESS; + } + +@@ -383,6 +456,9 @@ NorFlashWriteSingleWord ( + return EFI_DEVICE_ERROR; + } + MmioWrite32 (WordAddress, WriteData); ++ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) { ++ return EFI_DEVICE_ERROR; ++ } + return EFI_SUCCESS; + } + +@@ -907,7 +983,7 @@ NorFlashReadID ( + + val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | + CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | +- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS; ++ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(3); + + if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { + return EFI_DEVICE_ERROR; +diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h +index e720937e..eb0afc60 100644 +--- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h ++++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h +@@ -477,8 +477,13 @@ NorFlashReadID ( + OUT UINT8 JedecId[3] + ); + ++#define SPINOR_SR_WIP BIT0 // Write in progress ++ + #define SPINOR_OP_WREN 0x06 // Write enable + #define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block + #define SPINOR_OP_RDID 0x9f // Read JEDEC ID ++#define SPINOR_OP_RDSR 0x05 // Read status register ++ ++#define SPINOR_SR_WIP_POLL_TIMEOUT_MS 1000u // Status Register read timeout + + #endif /* NOR_FLASH_DXE_H_ */ diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch deleted file mode 100644 index c7f163b40b..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0001-Platform-ARM-N1sdp-Add-support-to-parse-NT_FW_CONFIG.patch +++ /dev/null @@ -1,471 +0,0 @@ -From 928cb457b9ab2abefbacad655eefdde943b4ee9a Mon Sep 17 00:00:00 2001 -From: sahil -Date: Thu, 17 Mar 2022 16:28:05 +0530 -Subject: [PATCH] Platform/ARM/N1sdp: Add support to parse NT_FW_CONFIG - -NT_FW_CONFIG DTB contains platform information passed by -Tf-A boot stage. -This information is used for Virtual memory map generation -during PEI phase and passed on to DXE phase as a HOB, where -it is used in ConfigurationManagerDxe. - -Upstream-Status: Pending -Signed-off-by: Adam Johnston -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: I54a86277719607eb00d4a472fae8f13c180eafca ---- - .../ConfigurationManager.c | 24 ++-- - .../ConfigurationManagerDxe.inf | 3 +- - .../ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 16 +-- - .../Library/PlatformLib/AArch64/Helper.S | 4 +- - .../Library/PlatformLib/PlatformLib.c | 12 +- - .../Library/PlatformLib/PlatformLib.inf | 8 +- - .../Library/PlatformLib/PlatformLibMem.c | 103 +++++++++++++++++- - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec | 7 +- - 8 files changed, 152 insertions(+), 25 deletions(-) - -diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -index a6b4cb0e..c15020f5 100644 ---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -@@ -1,7 +1,7 @@ - /** @file - Configuration Manager Dxe - -- Copyright (c) 2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -16,6 +16,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -28,6 +29,7 @@ - #include "Platform.h" - - extern struct EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat; -+static NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - - /** The platform configuration repository information. - */ -@@ -1242,13 +1244,11 @@ InitializePlatformRepository ( - IN EDKII_PLATFORM_REPOSITORY_INFO * CONST PlatRepoInfo - ) - { -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT64 Dram2Size; - UINT64 RemoteDdrSize; - - RemoteDdrSize = 0; - -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - Dram2Size = ((PlatInfo->LocalDdrSize - 2) * SIZE_1GB); - - PlatRepoInfo->MemAffInfo[LOCAL_DDR_REGION2].Length = Dram2Size; -@@ -1512,7 +1512,6 @@ GetGicCInfo ( - ) - { - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 TotalObjCount; - UINT32 ObjIndex; - -@@ -1523,7 +1522,6 @@ GetGicCInfo ( - } - - PlatformRepo = This->PlatRepoInfo; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - - if (PlatInfo->MultichipMode == 1) { - TotalObjCount = PLAT_CPU_COUNT * 2; -@@ -1623,7 +1621,6 @@ GetStandardNameSpaceObject ( - { - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 AcpiTableCount; - - if ((This == NULL) || (CmObject == NULL)) { -@@ -1634,7 +1631,7 @@ GetStandardNameSpaceObject ( - - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; -+ - AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList); - if (PlatInfo->MultichipMode == 0) - AcpiTableCount -= 1; -@@ -1697,7 +1694,6 @@ GetArmNameSpaceObject ( - { - EFI_STATUS Status; - EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; -- NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT32 GicRedistCount; - UINT32 GicCpuCount; - UINT32 ProcHierarchyInfoCount; -@@ -1718,8 +1714,6 @@ GetArmNameSpaceObject ( - Status = EFI_NOT_FOUND; - PlatformRepo = This->PlatRepoInfo; - -- // Probe for multi chip information -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; - if (PlatInfo->MultichipMode == 1) { - GicRedistCount = 2; - GicCpuCount = PLAT_CPU_COUNT * 2; -@@ -2162,8 +2156,18 @@ ConfigurationManagerDxeInitialize ( - IN EFI_SYSTEM_TABLE * SystemTable - ) - { -+ VOID *PlatInfoHob; - EFI_STATUS Status; - -+ PlatInfoHob = GetFirstGuidHob (&gArmNeoverseN1SocPlatformInfoDescriptorGuid); -+ -+ if (PlatInfoHob == NULL) { -+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); -+ return EFI_NOT_FOUND; -+ } -+ -+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)GET_GUID_HOB_DATA (PlatInfoHob); -+ - // Initialize the Platform Configuration Repository before installing the - // Configuration Manager Protocol - Status = InitializePlatformRepository ( -diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -index 4f8e7f13..a4e8b783 100644 ---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf -@@ -1,7 +1,7 @@ - ## @file - # Configuration Manager Dxe - # --# Copyright (c) 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2021 - 2023, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -42,6 +42,7 @@ - - [LibraryClasses] - ArmPlatformLib -+ HobLib - PrintLib - UefiBootServicesTableLib - UefiDriverEntryPoint -diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -index 097160c7..4966011e 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -@@ -1,6 +1,6 @@ - /** @file - * --* Copyright (c) 2018 - 2020, ARM Limited. All rights reserved. -+* Copyright (c) 2018 - 2023, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * -@@ -41,11 +41,6 @@ - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 - --// Base address to a structure of type NEOVERSEN1SOC_PLAT_INFO which is --// pre-populated by a earlier boot stage --#define NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE (NEOVERSEN1SOC_NON_SECURE_SRAM_BASE + \ -- 0x00008000) -- - /* - * Platform information structure stored in Non-secure SRAM. Platform - * information are passed from the trusted firmware with the below structure -@@ -55,12 +50,17 @@ - typedef struct { - /*! 0 - Single Chip, 1 - Chip to Chip (C2C) */ - UINT8 MultichipMode; -- /*! Slave count in C2C mode */ -- UINT8 SlaveCount; -+ /*! Secondary chip count in C2C mode */ -+ UINT8 SecondaryChipCount; - /*! Local DDR memory size in GigaBytes */ - UINT8 LocalDdrSize; - /*! Remote DDR memory size in GigaBytes */ - UINT8 RemoteDdrSize; - } NEOVERSEN1SOC_PLAT_INFO; - -+// NT_FW_CONFIG DT structure -+typedef struct { -+ UINT64 NtFwConfigDtAddr; -+} NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI; -+ - #endif -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -index 8d2069de..a0b89a7b 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/AArch64/Helper.S -@@ -1,6 +1,6 @@ - /** @file - * --* Copyright (c) 2019 - 2020, ARM Limited. All rights reserved. -+* Copyright (c) 2019 - 2023, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-2-Clause-Patent - * -@@ -25,6 +25,8 @@ GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) - // the UEFI firmware through the CPU registers. - // - ASM_PFX(ArmPlatformPeiBootAction): -+ adr x10, NtFwConfigDtBlob -+ str x0, [x10] - ret - - // -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -index c0effd37..2f753be7 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.c -@@ -1,6 +1,6 @@ - /** @file - -- Copyright (c) 2018-2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -8,8 +8,12 @@ - - #include - #include -+#include - #include - -+UINT64 NtFwConfigDtBlob; -+STATIC NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI mNtFwConfigDtInfoPpi; -+ - STATIC ARM_CORE_INFO mCoreInfoTable[] = { - { 0x0, 0x0 }, // Cluster 0, Core 0 - { 0x0, 0x1 }, // Cluster 0, Core 1 -@@ -46,6 +50,7 @@ ArmPlatformInitialize ( - IN UINTN MpId - ) - { -+ mNtFwConfigDtInfoPpi.NtFwConfigDtAddr = NtFwConfigDtBlob; - return RETURN_SUCCESS; - } - -@@ -80,6 +85,11 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gArmMpCoreInfoPpiGuid, - &mMpCoreInfoPpi -+ }, -+ { -+ EFI_PEI_PPI_DESCRIPTOR_PPI, -+ &gNtFwConfigDtInfoPpiGuid, -+ &mNtFwConfigDtInfoPpi - } - }; - -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -index 96e590cd..78f309c3 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf -@@ -1,7 +1,7 @@ - ## @file - # Platform Library for N1Sdp. - # --# Copyright (c) 2018-2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -18,10 +18,14 @@ - [Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec -+ EmbeddedPkg/EmbeddedPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec - -+[LibraryClasses] -+ FdtLib -+ - [Sources.common] - PlatformLibMem.c - PlatformLib.c -@@ -59,7 +63,9 @@ - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Guids] -+ gArmNeoverseN1SocPlatformInfoDescriptorGuid - gEfiHobListGuid ## CONSUMES ## SystemTable - - [Ppis] - gArmMpCoreInfoPpiGuid -+ gNtFwConfigDtInfoPpiGuid -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -index 339fa07b..1d53ec75 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -@@ -1,6 +1,6 @@ - /** @file - -- Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+ Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- - SPDX-License-Identifier: BSD-2-Clause-Patent - -@@ -10,11 +10,95 @@ - #include - #include - #include -+#include -+#include - #include - - // The total number of descriptors, including the final "end-of-table" descriptor. - #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 - -+/** A helper function to locate the NtFwConfig PPI and get the base address of -+ NT_FW_CONFIG DT from which values are obtained using FDT helper functions. -+ -+ @param [out] plat_info Pointer to the NeoverseN1Soc PLATFORM_INFO HOB -+ -+ @retval EFI_SUCCESS Success. -+ returns EFI_INVALID_PARAMETER A parameter is invalid. -+**/ -+EFI_STATUS -+GetNeoverseN1SocPlatInfo ( -+ OUT NEOVERSEN1SOC_PLAT_INFO *plat_info -+ ) -+{ -+ CONST UINT32 *Property; -+ INT32 Offset; -+ CONST VOID *NtFwCfgDtBlob; -+ NEOVERSEN1SOC_NT_FW_CONFIG_INFO_PPI *NtFwConfigInfoPpi; -+ EFI_STATUS Status; -+ -+ Status = PeiServicesLocatePpi ( -+ &gNtFwConfigDtInfoPpiGuid, -+ 0, -+ NULL, -+ (VOID **)&NtFwConfigInfoPpi -+ ); -+ -+ if (EFI_ERROR (Status)) { -+ DEBUG (( -+ DEBUG_ERROR, -+ "PeiServicesLocatePpi failed with error %r\n", -+ Status -+ )); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ NtFwCfgDtBlob = (VOID *)(UINTN)NtFwConfigInfoPpi->NtFwConfigDtAddr; -+ if (fdt_check_header (NtFwCfgDtBlob) != 0) { -+ DEBUG ((DEBUG_ERROR, "Invalid DTB file %p passed\n", NtFwCfgDtBlob)); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ Offset = fdt_subnode_offset (NtFwCfgDtBlob, 0, "platform-info"); -+ if (Offset == -FDT_ERR_NOTFOUND) { -+ DEBUG ((DEBUG_ERROR, "Invalid DTB : platform-info node not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "local-ddr-size", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "local-ddr-size property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->LocalDdrSize = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "remote-ddr-size", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "remote-ddr-size property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->RemoteDdrSize = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "secondary-chip-count", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "secondary-chip-count property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->SecondaryChipCount = fdt32_to_cpu (*Property); -+ -+ Property = fdt_getprop (NtFwCfgDtBlob, Offset, "multichip-mode", NULL); -+ if (Property == NULL) { -+ DEBUG ((DEBUG_ERROR, "multichip-mode property not found\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ plat_info->MultichipMode = fdt32_to_cpu (*Property); -+ -+ return EFI_SUCCESS; -+} -+ - /** - Returns the Virtual Memory Map of the platform. - -@@ -36,9 +120,24 @@ ArmPlatformGetVirtualMemoryMap ( - NEOVERSEN1SOC_PLAT_INFO *PlatInfo; - UINT64 DramBlock2Size; - UINT64 RemoteDdrSize; -+ EFI_STATUS Status; - - Index = 0; -- PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)NEOVERSEN1SOC_PLAT_INFO_STRUCT_BASE; -+ -+ // Create platform info HOB -+ PlatInfo = (NEOVERSEN1SOC_PLAT_INFO *)BuildGuidHob ( -+ &gArmNeoverseN1SocPlatformInfoDescriptorGuid, -+ sizeof (NEOVERSEN1SOC_PLAT_INFO) -+ ); -+ -+ if (PlatInfo == NULL) { -+ DEBUG ((DEBUG_ERROR, "Platform HOB is NULL\n")); -+ ASSERT (FALSE); -+ return; -+ } -+ -+ Status = GetNeoverseN1SocPlatInfo (PlatInfo); -+ ASSERT (Status == 0); - DramBlock2Size = ((UINT64)(PlatInfo->LocalDdrSize - - NEOVERSEN1SOC_DRAM_BLOCK1_SIZE / SIZE_1GB) * - (UINT64)SIZE_1GB); -diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -index d59f25a5..9e257ebd 100644 ---- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -@@ -1,7 +1,7 @@ - ## @file - # Describes the entire platform configuration. - # --# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -22,6 +22,8 @@ - Include # Root include for the package - - [Guids.common] -+ # ARM NeoverseN1Soc Platform Info descriptor -+ gArmNeoverseN1SocPlatformInfoDescriptorGuid = { 0x095cb024, 0x1e00, 0x4d6f, { 0xaa, 0x34, 0x4a, 0xf8, 0xaf, 0x0e, 0xad, 0x99 } } - gArmNeoverseN1SocTokenSpaceGuid = { 0xab93eb78, 0x60d7, 0x4099, { 0xac, 0xeb, 0x6d, 0xb5, 0x02, 0x58, 0x7c, 0x24 } } - - [PcdsFixedAtBuild] -@@ -83,3 +85,6 @@ - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio32Translation|0x40000000000|UINT64|0x0000004F - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050 - gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051 -+ -+[Ppis] -+ gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } } diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch deleted file mode 100644 index cafc299096..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0002-Platform-ARM-N1Sdp-Modify-the-IRQ-ID-of-Debug-UART-a.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 2ccb463274d0c04f1e3253194ea6eee80c31cb49 Mon Sep 17 00:00:00 2001 -From: Himanshu Sharma -Date: Mon, 30 May 2022 10:53:30 +0000 -Subject: [PATCH] Platform/ARM/N1Sdp: Modify the IRQ ID of Debug UART and - routing it to IOFPGA UART1 - -In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the -IPI0 trigger method to "level", which prevented SGI0 to be enabled -again after a CPU offline/online cycle. - -This patch fixes the above issue by assigning a reserved IRQ ID -for the Debug UART, other than 0 and also routing it to use IOFPGA -UART1 by unsharing it from currently using serial terminal. - -Upstream-Status: Pending -Signed-off-by: Adam Johnston -Signed-off-by: Xueliang Zhong -Signed-off-by: Himanshu Sharma -Change-Id: Ib35fecc57f1d8c496135c18dbebd0be0a4b76041 ---- - .../ConfigurationManagerDxe/ConfigurationManager.c | 2 +- - Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 8 ++++---- - 2 files changed, 5 insertions(+), 5 deletions(-) - -diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -index b11c0425..44046a00 100644 ---- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c -@@ -320,7 +320,7 @@ EDKII_PLATFORM_REPOSITORY_INFO N1sdpRepositoryInfo = { - // Debug Serial Port - { - FixedPcdGet64 (PcdSerialDbgRegisterBase), // BaseAddress -- 0, // Interrupt -unused -+ 250, // Interrupt (reserved) - FixedPcdGet64 (PcdSerialDbgUartBaudRate), // BaudRate - FixedPcdGet32 (PcdSerialDbgUartClkInHz), // Clock - EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART // Port subtype -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -index d04b22d3..676ab677 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -@@ -4,7 +4,7 @@ - # This provides platform specific component descriptions and libraries that - # conform to EFI/Framework standards. - # --# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - # -@@ -136,9 +136,9 @@ - gArmPlatformTokenSpaceGuid.PL011UartInterrupt|95 - - # PL011 Serial Debug UART (DBG2) -- gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase -- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate -- gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|50000000 -+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x1C0A0000 -+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|115200 -+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|24000000 - - # SBSA Watchdog - gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93 diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch deleted file mode 100644 index 264d262b22..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0003-Silicon-ARM-NeoverseN1Soc-Enable-SCP-QSPI-flash-regi.patch +++ /dev/null @@ -1,57 +0,0 @@ -From e4b0fced6f3fd3c8ce5ab4d3aae97b880e7e07b0 Mon Sep 17 00:00:00 2001 -From: sahil -Date: Mon, 2 May 2022 17:43:17 +0530 -Subject: [PATCH] Silicon/ARM/NeoverseN1Soc: Enable SCP QSPI flash region - -Enable SCP QSPI flash region access by adding it in the PlatformLibMem - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: I3ff832746ca94974ed72309eebe00e0024c47005 ---- - Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h | 4 ++++ - .../NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c | 8 +++++++- - 2 files changed, 11 insertions(+), 1 deletion(-) - -diff --git a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -index 4966011e..c7219136 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -+++ b/Silicon/ARM/NeoverseN1Soc/Include/NeoverseN1Soc.h -@@ -41,6 +41,10 @@ - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0 0x1C000000 - #define NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ 0x1300000 - -+// SCP QSPI flash device -+#define NEOVERSEN1SOC_SCP_QSPI_AHB_BASE 0x18000000 -+#define NEOVERSEN1SOC_SCP_QSPI_AHB_SZ 0x2000000 -+ - /* - * Platform information structure stored in Non-secure SRAM. Platform - * information are passed from the trusted firmware with the below structure -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -index 5cacd437..8bb94074 100644 ---- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c -@@ -15,7 +15,7 @@ - #include - - // The total number of descriptors, including the final "end-of-table" descriptor. --#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 19 -+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 20 - - /** A helper function to locate the NtFwConfig PPI and get the base address of - NT_FW_CONFIG DT from which values are obtained using FDT helper functions. -@@ -283,6 +283,12 @@ ArmPlatformGetVirtualMemoryMap ( - VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_EXP_PERIPH_BASE0_SZ; - VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; - -+ // SCP QSPI flash device -+ VirtualMemoryTable[++Index].PhysicalBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE; -+ VirtualMemoryTable[Index].VirtualBase = NEOVERSEN1SOC_SCP_QSPI_AHB_BASE; -+ VirtualMemoryTable[Index].Length = NEOVERSEN1SOC_SCP_QSPI_AHB_SZ; -+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; -+ - if (PlatInfo->MultichipMode == 1) { - //Remote DDR (2GB) - VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdExtMemorySpace) + diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch deleted file mode 100644 index eabbaf9976..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0004-Platform-ARM-N1Sdp-NOR-flash-library-for-N1Sdp.patch +++ /dev/null @@ -1,119 +0,0 @@ -From 70e79ba5300f01a13422452c29e26c69042a0c8c Mon Sep 17 00:00:00 2001 -From: sahil -Date: Mon, 2 May 2022 18:50:08 +0530 -Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash library for N1Sdp - -Add NOR flash library, this library provides APIs for getting the list -of NOR flash devices on the platform. - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: I39ad4143b7fad7e33b3b151a019a74f23e0ed441 ---- - .../Library/NorFlashLib/NorFlashLib.c | 52 +++++++++++++++++++ - .../Library/NorFlashLib/NorFlashLib.inf | 36 +++++++++++++ - 2 files changed, 88 insertions(+) - create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c - create mode 100644 Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf - -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c -new file mode 100644 -index 00000000..eee3d1c6 ---- /dev/null -+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.c -@@ -0,0 +1,52 @@ -+/** @file -+ NOR flash lib for N1Sdp -+ -+ Copyright (c) 2023, ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define FW_ENV_REGION_BASE FixedPcdGet32 (PcdFlashNvStorageVariableBase) -+#define FW_ENV_REGION_SIZE (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + \ -+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + \ -+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) -+ -+STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { -+ { -+ /// Environment variable region -+ NEOVERSEN1SOC_SCP_QSPI_AHB_BASE, ///< device base -+ FW_ENV_REGION_BASE, ///< region base -+ FW_ENV_REGION_SIZE, ///< region size -+ SIZE_4KB, ///< block size -+ }, -+}; -+ -+/** -+ Get NOR flash region info -+ -+ @param[out] NorFlashDevices NOR flash regions info. -+ @param[out] Count number of flash instance. -+ -+ @retval EFI_SUCCESS Success. -+**/ -+EFI_STATUS -+NorFlashPlatformGetDevices ( -+ OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, -+ OUT UINT32 *Count -+ ) -+{ -+ if ((NorFlashDevices == NULL) || (Count == NULL)) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ *NorFlashDevices = mNorFlashDevices; -+ *Count = ARRAY_SIZE (mNorFlashDevices); -+ return EFI_SUCCESS; -+} -diff --git a/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf -new file mode 100644 -index 00000000..784856c8 ---- /dev/null -+++ b/Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf -@@ -0,0 +1,36 @@ -+## @file -+# NOR flash lib for N1Sdp -+# -+# Copyright (c) 2023, ARM Limited. All rights reserved.
-+# -+# SPDX-License-Identifier: BSD-2-Clause-Patent -+# -+## -+ -+[Defines] -+ INF_VERSION = 0x0001001B -+ BASE_NAME = NorFlashN1SdpLib -+ FILE_GUID = 7006fcf1-a585-4272-92e3-b286b1dff5bb -+ MODULE_TYPE = DXE_DRIVER -+ VERSION_STRING = 1.0 -+ LIBRARY_CLASS = NorFlashPlatformLib -+ -+[Sources.common] -+ NorFlashLib.c -+ -+[Packages] -+ MdeModulePkg/MdeModulePkg.dec -+ MdePkg/MdePkg.dec -+ Platform/ARM/ARM.dec -+ Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec -+ -+[LibraryClasses] -+ BaseLib -+ DebugLib -+ IoLib -+ -+[FixedPcd] -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch deleted file mode 100644 index 1db94e4948..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0005-Platform-ARM-N1Sdp-NOR-flash-Dxe-Driver-for-N1Sdp.patch +++ /dev/null @@ -1,2538 +0,0 @@ -From 726f4505970c82db1822b127059519044dc496c8 Mon Sep 17 00:00:00 2001 -From: sahil -Date: Mon, 2 May 2022 19:00:40 +0530 -Subject: [PATCH] Platform/ARM/N1Sdp: NOR flash Dxe Driver for N1Sdp - -Add NOR flash DXE driver, this brings up NV storage on -QSPI's flash device using FVB protocol. - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: Ica383c2be6d1805daa19afd98d28b943816218dd ---- - .../Drivers/CadenceQspiDxe/CadenceQspiDxe.c | 366 +++++++ - .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 70 ++ - .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 31 + - .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 930 ++++++++++++++++++ - .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 484 +++++++++ - .../Drivers/CadenceQspiDxe/NorFlashFvb.c | 573 +++++++++++ - Platform/ARM/N1Sdp/N1SdpPlatform.dec | 5 +- - 7 files changed, 2458 insertions(+), 1 deletion(-) - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h - create mode 100644 Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c - -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c -new file mode 100644 -index 00000000..fb1dff3e ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.c -@@ -0,0 +1,366 @@ -+/** @file -+ NOR flash DXE -+ -+ Copyright (c) 2023, ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "NorFlash.h" -+ -+STATIC NOR_FLASH_INSTANCE **mNorFlashInstances; -+STATIC UINT32 mNorFlashDeviceCount; -+ -+STATIC EFI_EVENT mNorFlashVirtualAddrChangeEvent; -+ -+/** -+ Install Fv block onto variable store region -+ -+ @param[in] Instance Instance of Nor flash variable region. -+ -+ @retval EFI_SUCCESS The entry point is executed successfully. -+**/ -+EFI_STATUS -+EFIAPI -+NorFlashFvbInitialize ( -+ IN NOR_FLASH_INSTANCE* Instance -+ ) -+{ -+ EFI_STATUS Status; -+ UINT32 FvbNumLba; -+ EFI_BOOT_MODE BootMode; -+ UINTN RuntimeMmioRegionSize; -+ UINTN RuntimeMmioDeviceSize; -+ UINTN BlockSize; -+ -+ DEBUG ((DEBUG_INFO,"NorFlashFvbInitialize\n")); -+ -+ BlockSize = Instance->BlockSize; -+ -+ // FirmwareVolumeHeader->FvLength is declared to have the Variable area -+ // AND the FTW working area AND the FTW Spare contiguous. -+ ASSERT (PcdGet32 (PcdFlashNvStorageVariableBase) + -+ PcdGet32 (PcdFlashNvStorageVariableSize) == -+ PcdGet32 (PcdFlashNvStorageFtwWorkingBase)); -+ ASSERT (PcdGet32 (PcdFlashNvStorageFtwWorkingBase) + -+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) == -+ PcdGet32 (PcdFlashNvStorageFtwSpareBase)); -+ -+ // Check if the size of the area is at least one block size. -+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableSize) > 0) && -+ (PcdGet32 (PcdFlashNvStorageVariableSize) / BlockSize > 0)); -+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingSize) > 0) && -+ (PcdGet32 (PcdFlashNvStorageFtwWorkingSize) / BlockSize > 0)); -+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareSize) > 0) && -+ (PcdGet32 (PcdFlashNvStorageFtwSpareSize) / BlockSize > 0)); -+ -+ // Ensure the Variable areas are aligned on block size boundaries. -+ ASSERT ((PcdGet32 (PcdFlashNvStorageVariableBase) % BlockSize) == 0); -+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwWorkingBase) % BlockSize) == 0); -+ ASSERT ((PcdGet32 (PcdFlashNvStorageFtwSpareBase) % BlockSize) == 0); -+ -+ Instance->Initialized = TRUE; -+ mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase); -+ -+ // Set the index of the first LBA for the FVB. -+ Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - -+ Instance->RegionBaseAddress) / BlockSize; -+ -+ BootMode = GetBootModeHob (); -+ if (BootMode == BOOT_WITH_DEFAULT_SETTINGS) { -+ Status = EFI_INVALID_PARAMETER; -+ } else { -+ // Determine if there is a valid header at the beginning of the NorFlash. -+ Status = ValidateFvHeader (Instance); -+ } -+ -+ // Install the Default FVB header if required. -+ if (EFI_ERROR(Status)) { -+ // There is no valid header, so time to install one. -+ DEBUG ((DEBUG_INFO, "%a: The FVB Header is not valid.\n", __FUNCTION__)); -+ DEBUG ((DEBUG_INFO, "%a: Installing a correct one for this volume.\n", -+ __FUNCTION__)); -+ -+ // Erase all the NorFlash that is reserved for variable storage. -+ FvbNumLba = (PcdGet32 (PcdFlashNvStorageVariableSize) + -+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + -+ PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / -+ Instance->BlockSize; -+ -+ Status = FvbEraseBlocks ( -+ &Instance->FvbProtocol, -+ (EFI_LBA)0, -+ FvbNumLba, -+ EFI_LBA_LIST_TERMINATOR -+ ); -+ if (EFI_ERROR(Status)) { -+ return Status; -+ } -+ -+ // Install all appropriate headers. -+ Status = InitializeFvAndVariableStoreHeaders (Instance); -+ if (EFI_ERROR(Status)) { -+ return Status; -+ } -+ -+ // validate FV header again if FV was created successfully. -+ Status = ValidateFvHeader (Instance); -+ if (EFI_ERROR(Status)) { -+ DEBUG ((DEBUG_ERROR, "ValidateFvHeader is failed \n")); -+ return Status; -+ } -+ } -+ -+ // The driver implementing the variable read service can now be dispatched; -+ // the varstore headers are in place. -+ Status = gBS->InstallProtocolInterface ( -+ &gImageHandle, -+ &gEdkiiNvVarStoreFormattedGuid, -+ EFI_NATIVE_INTERFACE, -+ NULL -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((DEBUG_ERROR, -+ "%a: Failed to install gEdkiiNvVarStoreFormattedGuid\n", -+ __FUNCTION__)); -+ return Status; -+ } -+ -+ // Declare the Non-Volatile storage as EFI_MEMORY_RUNTIME. -+ RuntimeMmioRegionSize = Instance->Size; -+ RuntimeMmioDeviceSize = Instance->RegionBaseAddress - Instance->DeviceBaseAddress; -+ -+ Status = gDS->AddMemorySpace ( -+ EfiGcdMemoryTypeMemoryMappedIo, -+ Instance->RegionBaseAddress, -+ RuntimeMmioRegionSize, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ Status = gDS->AddMemorySpace ( -+ EfiGcdMemoryTypeMemoryMappedIo, -+ Instance->DeviceBaseAddress, -+ RuntimeMmioDeviceSize, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ Status = gDS->SetMemorySpaceAttributes ( -+ Instance->RegionBaseAddress, -+ RuntimeMmioRegionSize, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ Status = gDS->SetMemorySpaceAttributes ( -+ Instance->DeviceBaseAddress, -+ RuntimeMmioDeviceSize, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ return Status; -+} -+ -+/** -+ Fixup internal data so that EFI can be called in virtual mode. -+ convert any pointers in lib to virtual mode. -+ -+ @param[in] Event The Event that is being processed -+ @param[in] Context Event Context -+**/ -+STATIC -+VOID -+EFIAPI -+NorFlashVirtualNotifyEvent ( -+ IN EFI_EVENT Event, -+ IN VOID *Context -+ ) -+{ -+ UINTN Index; -+ -+ EfiConvertPointer (0x0, (VOID**)&mFlashNvStorageVariableBase); -+ -+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) { -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->HostRegisterBaseAddress); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->DeviceBaseAddress); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->RegionBaseAddress); -+ -+ // Convert Fvb. -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.EraseBlocks); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetAttributes); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetBlockSize); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.GetPhysicalAddress); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Read); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.SetAttributes); -+ EfiConvertPointer (0x0, -+ (VOID**)&mNorFlashInstances[Index]->FvbProtocol.Write); -+ -+ if (mNorFlashInstances[Index]->ShadowBuffer != NULL) { -+ EfiConvertPointer (0x0, (VOID**)&mNorFlashInstances[Index]->ShadowBuffer); -+ } -+ } -+} -+ -+/** -+ Entrypoint of Platform Nor flash DXE driver -+ -+ @param[in] ImageHandle The firmware allocated handle for the EFI image. -+ @param[in] SystemTable A pointer to the EFI System Table. -+ -+ @retval EFI_SUCCESS The entry point is executed successfully. -+**/ -+EFI_STATUS -+EFIAPI -+NorFlashInitialise ( -+ IN EFI_HANDLE ImageHandle, -+ IN EFI_SYSTEM_TABLE *SystemTable -+ ) -+{ -+ EFI_STATUS Status; -+ EFI_PHYSICAL_ADDRESS HostRegisterBaseAddress; -+ UINT32 Index; -+ NOR_FLASH_DESCRIPTION* NorFlashDevices; -+ BOOLEAN ContainVariableStorage; -+ -+ HostRegisterBaseAddress = PcdGet32 (PcdCadenceQspiDxeRegBaseAddress); -+ -+ Status = gDS->AddMemorySpace ( -+ EfiGcdMemoryTypeMemoryMappedIo, -+ HostRegisterBaseAddress, -+ SIZE_64KB, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ Status = gDS->SetMemorySpaceAttributes ( -+ HostRegisterBaseAddress, -+ SIZE_64KB, -+ EFI_MEMORY_UC | EFI_MEMORY_RUNTIME -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ // Initialize NOR flash instances. -+ Status = NorFlashPlatformGetDevices (&NorFlashDevices, &mNorFlashDeviceCount); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((DEBUG_ERROR,"NorFlashInitialise: Fail to get Nor Flash devices\n")); -+ return Status; -+ } -+ -+ mNorFlashInstances = AllocateRuntimePool (sizeof (NOR_FLASH_INSTANCE*) * -+ mNorFlashDeviceCount); -+ -+ if(mNorFlashInstances == NULL) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashInitialise: Failed to allocate mem for NorFlashInstance\n")); -+ return EFI_OUT_OF_RESOURCES; -+ } -+ -+ for (Index = 0; Index < mNorFlashDeviceCount; Index++) { -+ // Check if this NOR Flash device contain the variable storage region. -+ ContainVariableStorage = -+ (NorFlashDevices[Index].RegionBaseAddress <= -+ PcdGet32 (PcdFlashNvStorageVariableBase)) && -+ (PcdGet32 (PcdFlashNvStorageVariableBase) + -+ PcdGet32 (PcdFlashNvStorageVariableSize) <= -+ NorFlashDevices[Index].RegionBaseAddress + NorFlashDevices[Index].Size); -+ -+ Status = NorFlashCreateInstance ( -+ HostRegisterBaseAddress, -+ NorFlashDevices[Index].DeviceBaseAddress, -+ NorFlashDevices[Index].RegionBaseAddress, -+ NorFlashDevices[Index].Size, -+ Index, -+ NorFlashDevices[Index].BlockSize, -+ ContainVariableStorage, -+ &mNorFlashInstances[Index] -+ ); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashInitialise: Fail to create instance for NorFlash[%d]\n", -+ Index)); -+ continue; -+ } -+ Status = gBS->InstallMultipleProtocolInterfaces ( -+ &mNorFlashInstances[Index]->Handle, -+ &gEfiDevicePathProtocolGuid, -+ &mNorFlashInstances[Index]->DevicePath, -+ &gEfiFirmwareVolumeBlockProtocolGuid, -+ &mNorFlashInstances[Index]->FvbProtocol, -+ NULL -+ ); -+ ASSERT_EFI_ERROR (Status); -+ } -+ // Register for the virtual address change event. -+ Status = gBS->CreateEventEx ( -+ EVT_NOTIFY_SIGNAL, -+ TPL_NOTIFY, -+ NorFlashVirtualNotifyEvent, -+ NULL, -+ &gEfiEventVirtualAddressChangeGuid, -+ &mNorFlashVirtualAddrChangeEvent -+ ); -+ ASSERT_EFI_ERROR (Status); -+ -+ return Status; -+} -+ -+/** -+ Lock all pending read/write to Nor flash device -+ -+ @param[in] Context Nor flash device context structure. -+**/ -+VOID -+EFIAPI -+NorFlashLock ( -+ IN NOR_FLASH_LOCK_CONTEXT *Context -+ ) -+{ -+ if (!EfiAtRuntime ()) { -+ // Raise TPL to TPL_HIGH to stop anyone from interrupting us. -+ Context->OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL); -+ } else { -+ Context->InterruptsEnabled = SaveAndDisableInterrupts (); -+ } -+} -+ -+/** -+ Unlock all pending read/write to Nor flash device -+ -+ @param[in] Context Nor flash device context structure. -+**/ -+VOID -+EFIAPI -+NorFlashUnlock ( -+ IN NOR_FLASH_LOCK_CONTEXT *Context -+ ) -+{ -+ if (!EfiAtRuntime ()) { -+ // Interruptions can resume. -+ gBS->RestoreTPL (Context->OriginalTPL); -+ } else if (Context->InterruptsEnabled) { -+ SetInterruptState (TRUE); -+ } -+} -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -new file mode 100644 -index 00000000..4f20c3ba ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -@@ -0,0 +1,70 @@ -+## @file -+# NOR flash DXE -+# -+# Copyright (c) 2023, ARM Limited. All rights reserved.
-+# -+# SPDX-License-Identifier: BSD-2-Clause-Patent -+# -+## -+ -+[Defines] -+ INF_VERSION = 0x0001001B -+ BASE_NAME = CadenceQspiDxe -+ FILE_GUID = CC8A9713-4442-4A6C-B389-8B46490A0641 -+ MODULE_TYPE = DXE_RUNTIME_DRIVER -+ VERSION_STRING = 0.1 -+ ENTRY_POINT = NorFlashInitialise -+ -+[Sources] -+ CadenceQspiDxe.c -+ NorFlash.c -+ NorFlash.h -+ NorFlashFvb.c -+ -+[Packages] -+ EmbeddedPkg/EmbeddedPkg.dec -+ MdeModulePkg/MdeModulePkg.dec -+ MdePkg/MdePkg.dec -+ Platform/ARM/ARM.dec -+ Platform/ARM/N1Sdp/N1SdpPlatform.dec -+ -+[LibraryClasses] -+ BaseLib -+ BaseMemoryLib -+ DebugLib -+ DevicePathLib -+ DxeServicesTableLib -+ HobLib -+ IoLib -+ MemoryAllocationLib -+ NorFlashInfoLib -+ NorFlashPlatformLib -+ UefiBootServicesTableLib -+ UefiDriverEntryPoint -+ UefiLib -+ UefiRuntimeLib -+ UefiRuntimeServicesTableLib -+ -+[Guids] -+ gEdkiiNvVarStoreFormattedGuid -+ gEfiAuthenticatedVariableGuid -+ gEfiEventVirtualAddressChangeGuid -+ gEfiSystemNvDataFvGuid -+ gEfiVariableGuid -+ gEfiGlobalVariableGuid -+ -+[Protocols] -+ gEfiDevicePathProtocolGuid -+ gEfiFirmwareVolumeBlockProtocolGuid -+ -+[FixedPcd] -+ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize -+ -+[Depex] -+ gEfiCpuArchProtocolGuid -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h -new file mode 100644 -index 00000000..fe3b327c ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h -@@ -0,0 +1,31 @@ -+/** @file -+ -+ Copyright (c) 2023, ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#ifndef CADENCE_QSPI_REG_H_ -+#define CADENCE_QSPI_REG_H_ -+ -+// QSPI Controller defines -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET 0x90 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE 0x01 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE 0x01 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20 -+ -+#define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0 -+ -+#define CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET 0x94 -+ -+#endif /* CADENCE_QSPI_REG_H_ */ -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c -new file mode 100644 -index 00000000..188c75e2 ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c -@@ -0,0 +1,930 @@ -+/** @file -+ -+ Copyright (c) 2023 ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "NorFlash.h" -+ -+STATIC CONST NOR_FLASH_INSTANCE mNorFlashInstanceTemplate = { -+ NOR_FLASH_SIGNATURE, // Signature -+ NULL, // Handle -+ -+ FALSE, // Initialized -+ NULL, // Initialize -+ -+ 0, // HostRegisterBaseAddress -+ 0, // DeviceBaseAddress -+ 0, // RegionBaseAddress -+ 0, // Size -+ 0, // BlockSize -+ 0, // LastBlock -+ 0, // StartLba -+ 0, // OffsetLba -+ -+ { -+ FvbGetAttributes, // GetAttributes -+ FvbSetAttributes, // SetAttributes -+ FvbGetPhysicalAddress, // GetPhysicalAddress -+ FvbGetBlockSize, // GetBlockSize -+ FvbRead, // Read -+ FvbWrite, // Write -+ FvbEraseBlocks, // EraseBlocks -+ NULL, //ParentHandle -+ }, // FvbProtoccol; -+ NULL, // ShadowBuffer -+ -+ { -+ { -+ { -+ HARDWARE_DEVICE_PATH, -+ HW_VENDOR_DP, -+ { -+ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End)), -+ (UINT8)(OFFSET_OF (NOR_FLASH_DEVICE_PATH, End) >> 8) -+ } -+ }, -+ { 0x0, 0x0, 0x0, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } }, -+ }, -+ 0, // Index -+ -+ { -+ END_DEVICE_PATH_TYPE, -+ END_ENTIRE_DEVICE_PATH_SUBTYPE, -+ { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } -+ } -+ -+ }, // DevicePath -+ 0 // Flags -+}; -+ -+/** -+ Execute Flash cmd ctrl and Read Status. -+ -+ @param[in] Instance NOR flash Instance. -+ @param[in] Val Value to be written to Flash cmd ctrl Register. -+ -+ @retval EFI_SUCCESS Request is executed successfully. -+ -+**/ -+STATIC -+EFI_STATUS -+CdnsQspiExecuteCommand ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINT32 Val -+ ) -+{ -+ // Set the command -+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET, -+ Val); -+ // Execute the command -+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET, -+ Val | CDNS_QSPI_FLASH_CMD_CTRL_REG_EXECUTE); -+ -+ // Wait until command has been executed -+ while ((MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_CTRL_REG_OFFSET) -+ & CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT) == CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT) -+ continue; -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Create Nor flash Instance for given region. -+ -+ @param[in] HostRegisterBase Base address of Nor flash controller. -+ @param[in] NorFlashDeviceBase Base address of flash device. -+ @param[in] NorFlashRegionBase Base address of flash region on device. -+ @param[in] NorFlashSize Size of flash region. -+ @param[in] Index Index of given flash region. -+ @param[in] BlockSize Block size of NOR flash device. -+ @param[in] HasVarStore Boolean set for VarStore on given region. -+ @param[out] NorFlashInstance Instance of given flash region. -+ -+ @retval EFI_SUCCESS On successful creation of NOR flash instance. -+**/ -+EFI_STATUS -+NorFlashCreateInstance ( -+ IN UINTN HostRegisterBase, -+ IN UINTN NorFlashDeviceBase, -+ IN UINTN NorFlashRegionBase, -+ IN UINTN NorFlashSize, -+ IN UINT32 Index, -+ IN UINT32 BlockSize, -+ IN BOOLEAN HasVarStore, -+ OUT NOR_FLASH_INSTANCE** NorFlashInstance -+ ) -+{ -+ EFI_STATUS Status; -+ NOR_FLASH_INSTANCE* Instance; -+ NOR_FLASH_INFO *FlashInfo; -+ UINT8 JedecId[3]; -+ -+ ASSERT(NorFlashInstance != NULL); -+ Instance = AllocateRuntimeCopyPool (sizeof (mNorFlashInstanceTemplate), -+ &mNorFlashInstanceTemplate); -+ if (Instance == NULL) { -+ return EFI_OUT_OF_RESOURCES; -+ } -+ -+ Instance->HostRegisterBaseAddress = HostRegisterBase; -+ Instance->DeviceBaseAddress = NorFlashDeviceBase; -+ Instance->RegionBaseAddress = NorFlashRegionBase; -+ Instance->Size = NorFlashSize; -+ Instance->BlockSize = BlockSize; -+ Instance->LastBlock = (NorFlashSize / BlockSize) - 1; -+ -+ Instance->OffsetLba = (NorFlashRegionBase - NorFlashDeviceBase) / BlockSize; -+ -+ CopyGuid (&Instance->DevicePath.Vendor.Guid, &gEfiCallerIdGuid); -+ Instance->DevicePath.Index = (UINT8)Index; -+ -+ Status = NorFlashReadID (Instance, JedecId); -+ if (EFI_ERROR (Status)) { -+ goto FreeInstance; -+ } -+ -+ Status = NorFlashGetInfo (JedecId, &FlashInfo, TRUE); -+ if (EFI_ERROR (Status)) { -+ goto FreeInstance; -+ } -+ -+ NorFlashPrintInfo (FlashInfo); -+ -+ Instance->Flags = 0; -+ if (FlashInfo->Flags & NOR_FLASH_WRITE_FSR) { -+ Instance->Flags = NOR_FLASH_POLL_FSR; -+ } -+ -+ Instance->ShadowBuffer = AllocateRuntimePool (BlockSize); -+ if (Instance->ShadowBuffer == NULL) { -+ Status = EFI_OUT_OF_RESOURCES; -+ goto FreeInstance; -+ } -+ -+ if (HasVarStore) { -+ Instance->Initialize = NorFlashFvbInitialize; -+ } -+ -+ *NorFlashInstance = Instance; -+ FreePool (FlashInfo); -+ return EFI_SUCCESS; -+ -+FreeInstance: -+ FreePool (Instance); -+ return Status; -+} -+ -+/** -+ Check whether NOR flash opertions are Locked. -+ -+ @param[in] Instance NOR flash Instance. -+ @param[in] BlockAddress BlockAddress in NOR flash device. -+ -+ @retval FALSE If NOR flash is not locked. -+**/ -+STATIC -+BOOLEAN -+NorFlashBlockIsLocked ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ) -+{ -+ return FALSE; -+} -+ -+/** -+ Unlock NOR flash operations on given block. -+ -+ @param[in] Instance NOR flash instance. -+ @param[in] BlockAddress BlockAddress in NOR flash device. -+ -+ @retval EFI_SUCCESS NOR flash operations is unlocked. -+**/ -+STATIC -+EFI_STATUS -+NorFlashUnlockSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ) -+{ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Unlock NOR flash operations if it is necessary. -+ -+ @param[in] Instance NOR flash instance. -+ @param[in] BlockAddress BlockAddress in NOR flash device. -+ -+ @retval EFI_SUCCESS Request is executed successfully. -+**/ -+STATIC -+EFI_STATUS -+NorFlashUnlockSingleBlockIfNecessary ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ) -+{ -+ EFI_STATUS Status; -+ -+ Status = EFI_SUCCESS; -+ -+ if (!NorFlashBlockIsLocked (Instance, BlockAddress)) { -+ Status = NorFlashUnlockSingleBlock (Instance, BlockAddress); -+ } -+ -+ return Status; -+} -+ -+/** -+ Enable write to NOR flash device. -+ -+ @param[in] Instance NOR flash instance. -+ -+ @retval EFI_SUCCESS Request is executed successfully. -+**/ -+STATIC -+EFI_STATUS -+NorFlashEnableWrite ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ) -+{ -+ -+ UINT32 val; -+ -+ DEBUG ((DEBUG_INFO, "NorFlashEnableWrite()\n")); -+ val = (SPINOR_OP_WREN << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS); -+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ The following function presumes that the block has already been unlocked. -+ -+ @param[in] Instance NOR flash instance. -+ @param[in] BlockAddress Block address within the variable region. -+ -+ @retval EFI_SUCCESS Request is executed successfully. -+ **/ -+EFI_STATUS -+NorFlashEraseSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ) -+{ -+ -+ UINT32 DevConfigVal; -+ UINT32 EraseOffset; -+ -+ EraseOffset = 0x0; -+ -+ DEBUG ((DEBUG_INFO, "NorFlashEraseSingleBlock(BlockAddress=0x%08x)\n", -+ BlockAddress)); -+ -+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ EraseOffset = BlockAddress - Instance->DeviceBaseAddress; -+ -+ MmioWrite32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_ADDR_REG_OFFSET, -+ EraseOffset); -+ -+ DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS; -+ -+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ This function unlock and erase an entire NOR Flash block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] BlockAddress Block address within the variable store region. -+ -+ @retval EFI_SUCCESS The erase and unlock successfully completed. -+**/ -+EFI_STATUS -+NorFlashUnlockAndEraseSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ) -+{ -+ EFI_STATUS Status; -+ UINTN Index; -+ NOR_FLASH_LOCK_CONTEXT Lock; -+ NorFlashLock (&Lock); -+ -+ Index = 0; -+ do { -+ // Unlock the block if we have to -+ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress); -+ if (EFI_ERROR (Status)) { -+ break; -+ } -+ Status = NorFlashEraseSingleBlock (Instance, BlockAddress); -+ if (EFI_ERROR (Status)) { -+ break; -+ } -+ Index++; -+ } while ((Index < NOR_FLASH_ERASE_RETRY) && (Status == EFI_WRITE_PROTECTED)); -+ -+ if (Index == NOR_FLASH_ERASE_RETRY) { -+ DEBUG ((DEBUG_ERROR, -+ "EraseSingleBlock(BlockAddress=0x%08x: Block Locked Error (try to erase %d times)\n", -+ BlockAddress,Index)); -+ } -+ -+ NorFlashUnlock (&Lock); -+ -+ return Status; -+} -+ -+/** -+ Write a single word to given location. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] WordAddress The address in NOR flash to write given word. -+ @param[in] WriteData The data to write into NOR flash location. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+STATIC -+EFI_STATUS -+NorFlashWriteSingleWord ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN WordAddress, -+ IN UINT32 WriteData -+ ) -+{ -+ DEBUG ((DEBUG_INFO, -+ "NorFlashWriteSingleWord(WordAddress=0x%08x, WriteData=0x%08x)\n", -+ WordAddress, WriteData)); -+ -+ if (EFI_ERROR (NorFlashEnableWrite (Instance))) { -+ return EFI_DEVICE_ERROR; -+ } -+ MmioWrite32 (WordAddress, WriteData); -+ return EFI_SUCCESS; -+} -+ -+/** -+ Write a full block to given location. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The logical block address in NOR flash. -+ @param[in] DataBuffer The data to write into NOR flash location. -+ @param[in] BlockSizeInWords The number of bytes to write. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+STATIC -+EFI_STATUS -+NorFlashWriteFullBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINT32 *DataBuffer, -+ IN UINT32 BlockSizeInWords -+ ) -+{ -+ EFI_STATUS Status; -+ UINTN WordAddress; -+ UINT32 WordIndex; -+ UINTN BlockAddress; -+ NOR_FLASH_LOCK_CONTEXT Lock; -+ -+ Status = EFI_SUCCESS; -+ -+ // Get the physical address of the block -+ BlockAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, -+ BlockSizeInWords * 4); -+ -+ // Start writing from the first address at the start of the block -+ WordAddress = BlockAddress; -+ -+ NorFlashLock (&Lock); -+ -+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); -+ if (EFI_ERROR (Status)) { -+ DEBUG ((DEBUG_ERROR, -+ "WriteSingleBlock: ERROR - Failed to Unlock and Erase the single block at 0x%X\n", -+ BlockAddress)); -+ goto EXIT; -+ } -+ -+ for (WordIndex=0; -+ WordIndex < BlockSizeInWords; -+ WordIndex++, DataBuffer++, WordAddress += 4) { -+ Status = NorFlashWriteSingleWord (Instance, WordAddress, *DataBuffer); -+ if (EFI_ERROR (Status)) { -+ goto EXIT; -+ } -+ } -+ -+EXIT: -+ NorFlashUnlock (&Lock); -+ -+ if (EFI_ERROR (Status)) { -+ DEBUG ((DEBUG_ERROR, -+ "NOR FLASH Programming [WriteSingleBlock] failed at address 0x%08x. Exit Status = %r.\n", -+ WordAddress, Status)); -+ } -+ return Status; -+} -+ -+/** -+ Write a full block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index. -+ @param[in] BufferSizeInBytes The number of bytes to read. -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashWriteBlocks ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN BufferSizeInBytes, -+ IN VOID *Buffer -+ ) -+{ -+ UINT32 *pWriteBuffer; -+ EFI_STATUS Status; -+ EFI_LBA CurrentBlock; -+ UINT32 BlockSizeInWords; -+ UINT32 NumBlocks; -+ UINT32 BlockCount; -+ -+ Status = EFI_SUCCESS; -+ // The buffer must be valid -+ if (Buffer == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // We must have some bytes to read -+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BufferSizeInBytes=0x%x\n", -+ BufferSizeInBytes)); -+ if (BufferSizeInBytes == 0) { -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // The size of the buffer must be a multiple of the block size -+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: BlockSize in bytes =0x%x\n", -+ Instance->BlockSize)); -+ if ((BufferSizeInBytes % Instance->BlockSize) != 0) { -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // All blocks must be within the device -+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize; -+ -+ DEBUG ((DEBUG_INFO, -+ "NorFlashWriteBlocks: NumBlocks=%d, LastBlock=%ld, Lba=%ld.\n", NumBlocks, -+ Instance->LastBlock, Lba)); -+ -+ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashWriteBlocks: ERROR - Write will exceed last block.\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ ASSERT (((UINTN)Buffer % sizeof (UINT32)) == 0); -+ -+ BlockSizeInWords = Instance->BlockSize / 4; -+ -+ // Because the target *Buffer is a pointer to VOID, we must put -+ // all the data into a pointer to a proper data type, so use *ReadBuffer -+ pWriteBuffer = (UINT32 *)Buffer; -+ -+ CurrentBlock = Lba; -+ for (BlockCount = 0; -+ BlockCount < NumBlocks; -+ BlockCount++, CurrentBlock++, pWriteBuffer += BlockSizeInWords) { -+ -+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Writing block #%d\n", -+ (UINTN)CurrentBlock)); -+ -+ Status = NorFlashWriteFullBlock ( -+ Instance, -+ CurrentBlock, -+ pWriteBuffer, -+ BlockSizeInWords -+ ); -+ -+ if (EFI_ERROR (Status)) { -+ break; -+ } -+ } -+ -+ DEBUG ((DEBUG_INFO, "NorFlashWriteBlocks: Exit Status = %r.\n", Status)); -+ return Status; -+} -+ -+/** -+ Read a full block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to read from. -+ @param[in] BufferSizeInBytes The number of bytes to read. -+ @param[out] Buffer The pointer to a caller-allocated buffer that -+ should be copied with read data. -+ -+ @retval EFI_SUCCESS The read is completed. -+**/ -+EFI_STATUS -+NorFlashReadBlocks ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN BufferSizeInBytes, -+ OUT VOID *Buffer -+ ) -+{ -+ UINT32 NumBlocks; -+ UINTN StartAddress; -+ DEBUG ((DEBUG_INFO, -+ "NorFlashReadBlocks: BufferSize=0x%xB BlockSize=0x%xB LastBlock=%ld, Lba=%ld.\n", -+ BufferSizeInBytes, Instance->BlockSize, Instance->LastBlock, -+ Lba)); -+ -+ // The buffer must be valid -+ if (Buffer == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // Return if we do not have any byte to read -+ if (BufferSizeInBytes == 0) { -+ return EFI_SUCCESS; -+ } -+ -+ // The size of the buffer must be a multiple of the block size -+ if ((BufferSizeInBytes % Instance->BlockSize) != 0) { -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ NumBlocks = ((UINT32)BufferSizeInBytes) / Instance->BlockSize; -+ -+ if ((Lba + NumBlocks) > (Instance->LastBlock + 1)) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashReadBlocks: ERROR - Read will exceed last block\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // Get the address to start reading from -+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, -+ Instance->BlockSize); -+ -+ // Readout the data -+ CopyMem(Buffer, (UINTN *)StartAddress, BufferSizeInBytes); -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Read from nor flash. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to read from. -+ @param[in] Offset Offset into the block at which to begin reading. -+ @param[in] BufferSizeInBytes The number of bytes to read. -+ @param[out] Buffer The pointer to a caller-allocated buffer that -+ should copied with read data. -+ -+ @retval EFI_SUCCESS The read is completed. -+**/ -+EFI_STATUS -+NorFlashRead ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN UINTN BufferSizeInBytes, -+ OUT VOID *Buffer -+ ) -+{ -+ UINTN StartAddress; -+ // The buffer must be valid -+ if (Buffer == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // Return if we do not have any byte to read -+ if (BufferSizeInBytes == 0) { -+ return EFI_SUCCESS; -+ } -+ -+ if (((Lba * Instance->BlockSize) + Offset + BufferSizeInBytes) > -+ Instance->Size) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashRead: ERROR - Read will exceed device size.\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ // Get the address to start reading from -+ StartAddress = GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, -+ Instance->BlockSize); -+ -+ // Readout the data -+ CopyMem (Buffer, (UINTN *)(StartAddress + Offset), BufferSizeInBytes); -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Write a full or portion of a block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to write to. -+ @param[in] Offset Offset into the block at which to begin writing. -+ @param[in, out] NumBytes The total size of the buffer. -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashWriteSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN UINT8 *Buffer -+ ) -+{ -+ EFI_STATUS Status; -+ UINT32 Tmp; -+ UINT32 TmpBuf; -+ UINT32 WordToWrite; -+ UINT32 Mask; -+ BOOLEAN DoErase; -+ UINTN BytesToWrite; -+ UINTN CurOffset; -+ UINTN WordAddr; -+ UINTN BlockSize; -+ UINTN BlockAddress; -+ UINTN PrevBlockAddress; -+ -+ if (Buffer == NULL) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashWriteSingleBlock: ERROR - Buffer is invalid\n" )); -+ return EFI_OUT_OF_RESOURCES; -+ } -+ -+ PrevBlockAddress = 0; -+ if (!Instance->Initialized && Instance->Initialize) { -+ Instance->Initialize(Instance); -+ } -+ -+ DEBUG ((DEBUG_INFO, -+ "NorFlashWriteSingleBlock(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", -+ Lba, Offset, *NumBytes, Buffer)); -+ -+ // Localise the block size to avoid de-referencing pointers all the time -+ BlockSize = Instance->BlockSize; -+ -+ // The write must not span block boundaries. -+ // We need to check each variable individually because adding two large -+ // values together overflows. -+ if (Offset >= BlockSize || -+ *NumBytes > BlockSize || -+ (Offset + *NumBytes) > BlockSize) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", -+ Offset, *NumBytes, BlockSize )); -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // We must have some bytes to write -+ if (*NumBytes == 0) { -+ DEBUG ((DEBUG_ERROR, -+ "NorFlashWriteSingleBlock: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", -+ Offset, *NumBytes, BlockSize )); -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // Pick 128bytes as a good start for word operations as opposed to erasing the -+ // block and writing the data regardless if an erase is really needed. -+ // It looks like most individual NV variable writes are smaller than 128bytes. -+ if (*NumBytes <= 128) { -+ // Check to see if we need to erase before programming the data into NOR. -+ // If the destination bits are only changing from 1s to 0s we can just write. -+ // After a block is erased all bits in the block is set to 1. -+ // If any byte requires us to erase we just give up and rewrite all of it. -+ DoErase = FALSE; -+ BytesToWrite = *NumBytes; -+ CurOffset = Offset; -+ -+ while (BytesToWrite > 0) { -+ // Read full word from NOR, splice as required. A word is the smallest -+ // unit we can write. -+ Status = NorFlashRead ( -+ Instance, -+ Lba, -+ CurOffset & ~(0x3), -+ sizeof(Tmp), -+ &Tmp -+ ); -+ if (EFI_ERROR (Status)) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ // Physical address of word in NOR to write. -+ WordAddr = (CurOffset & ~(0x3)) + -+ GET_NOR_BLOCK_ADDRESS (Instance->RegionBaseAddress, Lba, -+ BlockSize); -+ -+ // The word of data that is to be written. -+ TmpBuf = ReadUnaligned32 ((UINT32 *)(Buffer + (*NumBytes - BytesToWrite))); -+ -+ // First do word aligned chunks. -+ if ((CurOffset & 0x3) == 0) { -+ if (BytesToWrite >= 4) { -+ // Is the destination still in 'erased' state? -+ if (~Tmp != 0) { -+ // Check to see if we are only changing bits to zero. -+ if ((Tmp ^ TmpBuf) & TmpBuf) { -+ DoErase = TRUE; -+ break; -+ } -+ } -+ // Write this word to NOR -+ WordToWrite = TmpBuf; -+ CurOffset += sizeof(TmpBuf); -+ BytesToWrite -= sizeof(TmpBuf); -+ } else { -+ // BytesToWrite < 4. Do small writes and left-overs -+ Mask = ~((~0) << (BytesToWrite * 8)); -+ // Mask out the bytes we want. -+ TmpBuf &= Mask; -+ // Is the destination still in 'erased' state? -+ if ((Tmp & Mask) != Mask) { -+ // Check to see if we are only changing bits to zero. -+ if ((Tmp ^ TmpBuf) & TmpBuf) { -+ DoErase = TRUE; -+ break; -+ } -+ } -+ // Merge old and new data. Write merged word to NOR -+ WordToWrite = (Tmp & ~Mask) | TmpBuf; -+ CurOffset += BytesToWrite; -+ BytesToWrite = 0; -+ } -+ } else { -+ // Do multiple words, but starting unaligned. -+ if (BytesToWrite > (4 - (CurOffset & 0x3))) { -+ Mask = ((~0) << ((CurOffset & 0x3) * 8)); -+ // Mask out the bytes we want. -+ TmpBuf &= Mask; -+ // Is the destination still in 'erased' state? -+ if ((Tmp & Mask) != Mask) { -+ // Check to see if we are only changing bits to zero. -+ if ((Tmp ^ TmpBuf) & TmpBuf) { -+ DoErase = TRUE; -+ break; -+ } -+ } -+ // Merge old and new data. Write merged word to NOR -+ WordToWrite = (Tmp & ~Mask) | TmpBuf; -+ BytesToWrite -= (4 - (CurOffset & 0x3)); -+ CurOffset += (4 - (CurOffset & 0x3)); -+ } else { -+ // Unaligned and fits in one word. -+ Mask = (~((~0) << (BytesToWrite * 8))) << ((CurOffset & 0x3) * 8); -+ // Mask out the bytes we want. -+ TmpBuf = (TmpBuf << ((CurOffset & 0x3) * 8)) & Mask; -+ // Is the destination still in 'erased' state? -+ if ((Tmp & Mask) != Mask) { -+ // Check to see if we are only changing bits to zero. -+ if ((Tmp ^ TmpBuf) & TmpBuf) { -+ DoErase = TRUE; -+ break; -+ } -+ } -+ // Merge old and new data. Write merged word to NOR -+ WordToWrite = (Tmp & ~Mask) | TmpBuf; -+ CurOffset += BytesToWrite; -+ BytesToWrite = 0; -+ } -+ } -+ -+ BlockAddress = GET_NOR_BLOCK_ADDRESS ( -+ Instance->RegionBaseAddress, -+ Lba, -+ BlockSize -+ ); -+ if (BlockAddress != PrevBlockAddress) { -+ Status = NorFlashUnlockSingleBlockIfNecessary (Instance, BlockAddress); -+ if (EFI_ERROR (Status)) { -+ return EFI_DEVICE_ERROR; -+ } -+ PrevBlockAddress = BlockAddress; -+ } -+ Status = NorFlashWriteSingleWord (Instance, WordAddr, WordToWrite); -+ if (EFI_ERROR (Status)) { -+ return EFI_DEVICE_ERROR; -+ } -+ } -+ // Exit if we got here and could write all the data. Otherwise do the -+ // Erase-Write cycle. -+ if (!DoErase) { -+ return EFI_SUCCESS; -+ } -+ } -+ -+ // Check we did get some memory. Buffer is BlockSize. -+ if (Instance->ShadowBuffer == NULL) { -+ DEBUG ((DEBUG_ERROR, "FvbWrite: ERROR - Buffer not ready\n")); -+ return EFI_DEVICE_ERROR; -+ } -+ -+ // Read NOR Flash data into shadow buffer -+ Status = NorFlashReadBlocks ( -+ Instance, -+ Lba, -+ BlockSize, -+ Instance->ShadowBuffer -+ ); -+ if (EFI_ERROR (Status)) { -+ // Return one of the pre-approved error statuses -+ return EFI_DEVICE_ERROR; -+ } -+ -+ // Put the data at the appropriate location inside the buffer area -+ CopyMem ((VOID*)((UINTN)Instance->ShadowBuffer + Offset), Buffer, *NumBytes); -+ -+ // Write the modified buffer back to the NorFlash -+ Status = NorFlashWriteBlocks ( -+ Instance, -+ Lba, -+ BlockSize, -+ Instance->ShadowBuffer -+ ); -+ if (EFI_ERROR (Status)) { -+ // Return one of the pre-approved error statuses -+ return EFI_DEVICE_ERROR; -+ } -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Read JEDEC ID of NOR flash device. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[out] JedecId JEDEC ID of NOR flash device. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashReadID ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ OUT UINT8 JedecId[3] -+ ) -+{ -+ UINT32 val; -+ if (Instance == NULL || JedecId == NULL) { -+ return EFI_INVALID_PARAMETER; -+ } -+ -+ val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS; -+ -+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ val = MmioRead32 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET); -+ -+ // Manu.ID field -+ JedecId[0] = (UINT8) val; -+ // Type field -+ JedecId[1] = (UINT8) (val >> 8); -+ // Capacity field -+ JedecId[2] = (UINT8) (val >> 16); -+ -+ DEBUG ((DEBUG_INFO, -+ "Nor flash detected, Jedec ID, Manu.Id=%x Type=%x Capacity=%x \n", -+ JedecId[0],JedecId[1],JedecId[2])); -+ -+ return EFI_SUCCESS; -+} -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h -new file mode 100644 -index 00000000..e720937e ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h -@@ -0,0 +1,484 @@ -+/** @file -+ -+ Copyright (c) 2023, ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#ifndef NOR_FLASH_DXE_H_ -+#define NOR_FLASH_DXE_H_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "CadenceQspiReg.h" -+ -+#define NOR_FLASH_ERASE_RETRY 10 -+ -+#define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) \ -+ ((BaseAddr) + (UINTN)((Lba) * (LbaSize))) -+ -+#define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r') -+#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, \ -+ NOR_FLASH_SIGNATURE) -+ -+#define NOR_FLASH_POLL_FSR BIT0 -+ -+typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE; -+ -+typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance); -+ -+#pragma pack(1) -+typedef struct { -+ VENDOR_DEVICE_PATH Vendor; -+ UINT8 Index; -+ EFI_DEVICE_PATH_PROTOCOL End; -+} NOR_FLASH_DEVICE_PATH; -+#pragma pack() -+ -+struct _NOR_FLASH_INSTANCE { -+ UINT32 Signature; -+ EFI_HANDLE Handle; -+ -+ BOOLEAN Initialized; -+ NOR_FLASH_INITIALIZE Initialize; -+ -+ UINTN HostRegisterBaseAddress; -+ UINTN DeviceBaseAddress; -+ UINTN RegionBaseAddress; -+ UINTN Size; -+ UINTN BlockSize; -+ UINTN LastBlock; -+ EFI_LBA StartLba; -+ EFI_LBA OffsetLba; -+ -+ EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol; -+ VOID* ShadowBuffer; -+ -+ NOR_FLASH_DEVICE_PATH DevicePath; -+ -+ UINT32 Flags; -+}; -+ -+typedef struct { -+ EFI_TPL OriginalTPL; -+ BOOLEAN InterruptsEnabled; -+} NOR_FLASH_LOCK_CONTEXT; -+ -+/** -+ Lock all pending read/write to Nor flash device -+ -+ @param[in] Context Nor flash device context structure. -+**/ -+VOID -+EFIAPI -+NorFlashLock ( -+ IN NOR_FLASH_LOCK_CONTEXT *Context -+ ); -+ -+/** -+ Unlock all pending read/write to Nor flash device -+ -+ @param[in] Context Nor flash device context structure. -+**/ -+VOID -+EFIAPI -+NorFlashUnlock ( -+ IN NOR_FLASH_LOCK_CONTEXT *Context -+ ); -+ -+extern UINTN mFlashNvStorageVariableBase; -+ -+/** -+ Create Nor flash Instance for given region. -+ -+ @param[in] HostRegisterBase Base address of Nor flash controller. -+ @param[in] NorFlashDeviceBase Base address of flash device. -+ @param[in] NorFlashRegionBase Base address of flash region on device. -+ @param[in] NorFlashSize Size of flash region. -+ @param[in] Index Index of given flash region. -+ @param[in] BlockSize Block size of NOR flash device. -+ @param[in] HasVarStore Boolean set for VarStore on given region. -+ @param[out] NorFlashInstance Instance of given flash region. -+ -+ @retval EFI_SUCCESS On successful creation of NOR flash instance. -+**/ -+EFI_STATUS -+NorFlashCreateInstance ( -+ IN UINTN HostRegisterBase, -+ IN UINTN NorFlashDeviceBase, -+ IN UINTN NorFlashRegionBase, -+ IN UINTN NorFlashSize, -+ IN UINT32 Index, -+ IN UINT32 BlockSize, -+ IN BOOLEAN HasVarStore, -+ OUT NOR_FLASH_INSTANCE** NorFlashInstance -+ ); -+ -+/** -+ Install Fv block on to variable store region -+ -+ @param[in] Instance Instance of Nor flash variable region. -+ -+ @retval EFI_SUCCESS The entry point is executed successfully. -+**/ -+EFI_STATUS -+EFIAPI -+NorFlashFvbInitialize ( -+ IN NOR_FLASH_INSTANCE* Instance -+ ); -+ -+/** -+ Check the integrity of firmware volume header. -+ -+ @param[in] Instance Instance of Nor flash variable region. -+ -+ @retval EFI_SUCCESS The firmware volume is consistent. -+ @retval EFI_NOT_FOUND The firmware volume has been corrupted. -+ -+**/ -+EFI_STATUS -+ValidateFvHeader ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ); -+ -+/** -+ Initialize the FV Header and Variable Store Header -+ to support variable operations. -+ -+ @param[in] Instance Location to Initialize the headers -+ -+ @retval EFI_SUCCESS Fv init is done -+ -+**/ -+EFI_STATUS -+InitializeFvAndVariableStoreHeaders ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ); -+ -+/** -+ Retrieves the attributes and current settings of the block. -+ -+ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and -+ current settings are returned. -+ Type EFI_FVB_ATTRIBUTES_2 is defined in -+ EFI_FIRMWARE_VOLUME_HEADER. -+ -+ @retval EFI_SUCCESS The firmware volume attributes were returned. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetAttributes( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes -+ ); -+ -+/** -+ Sets configurable firmware volume attributes and returns the -+ new settings of the firmware volume. -+ -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in, out] Attributes On input, Attributes is a pointer to -+ EFI_FVB_ATTRIBUTES_2 that contains the desired -+ firmware volume settings. -+ On successful return, it contains the new -+ settings of the firmware volume. -+ -+ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbSetAttributes( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes -+ ); -+ -+/** -+ Retrieves the base address of a memory-mapped firmware volume. -+ This function should be called only for memory-mapped firmware volumes. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[out] Address Pointer to a caller-allocated -+ EFI_PHYSICAL_ADDRESS that, on successful -+ return from GetPhysicalAddress(), contains the -+ base address of the firmware volume. -+ -+ @retval EFI_SUCCESS The firmware volume base address was returned. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetPhysicalAddress( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ OUT EFI_PHYSICAL_ADDRESS *Address -+ ); -+ -+/** -+ Retrieves the size of the requested block. -+ It also returns the number of additional blocks with the identical size. -+ The GetBlockSize() function is used to retrieve the block map -+ (see EFI_FIRMWARE_VOLUME_HEADER). -+ -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba Indicates the block whose size to return -+ -+ @param[out] BlockSize Pointer to a caller-allocated UINTN in which -+ the size of the block is returned. -+ -+ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in -+ which the number of consecutive blocks, -+ starting with Lba, is returned. All -+ blocks in this range have a size of -+ BlockSize. -+ -+ @retval EFI_SUCCESS The firmware volume base address was returned. -+ -+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetBlockSize( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ OUT UINTN *BlockSize, -+ OUT UINTN *NumberOfBlocks -+ ); -+ -+/** -+ Reads the specified number of bytes into a buffer from the specified block. -+ -+ The Read() function reads the requested number of bytes from the -+ requested block and stores them in the provided buffer. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba The starting logical block index from which to read -+ -+ @param[in] Offset Offset into the block at which to begin reading. -+ -+ @param[in, out] NumBytes Pointer to a UINTN. -+ At entry, *NumBytes contains the total size of the -+ buffer. *NumBytes should have a non zero value. -+ At exit, *NumBytes contains the total number of -+ bytes read. -+ -+ @param[in out] Buffer Pointer to a caller-allocated buffer that will be -+ used to hold the data that is read. -+ -+ @retval EFI_SUCCESS The firmware volume was read successfully, and -+ contents are in Buffer. -+ -+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. -+ -+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and -+ could not be read. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbRead( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN OUT UINT8 *Buffer -+ ); -+ -+/** -+ Writes the specified number of bytes from the input buffer to the block. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba The starting logical block index to write to. -+ -+ @param[in] Offset Offset into the block at which to begin writing. -+ -+ @param[in, out] NumBytes The pointer to a UINTN. -+ At entry, *NumBytes contains the total size of the -+ buffer. -+ At exit, *NumBytes contains the total number of -+ bytes actually written. -+ -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The firmware volume was written successfully. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbWrite( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN UINT8 *Buffer -+ ); -+ -+/** -+ Erases and initialises a firmware volume block. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL -+ -+ @param[in] ... The variable argument list is a list of tuples. -+ Each tuple describes a range of LBAs to erase -+ and consists of the following: -+ - An EFI_LBA that indicates the starting LBA -+ - A UINTN that indicates the number of blocks -+ to erase. -+ -+ The list is terminated with an -+ EFI_LBA_LIST_TERMINATOR. -+ -+ @retval EFI_SUCCESS The erase request successfully completed. -+ -+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled -+ state. -+ -+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly -+ and could not be written. -+ The firmware device may have been partially -+ erased. -+ -+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable -+ argument list do not exist in the firmware -+ volume. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbEraseBlocks( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ ... -+ ); -+ -+/** -+ This function unlock and erase an entire NOR Flash block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] BlockAddress Block address within the variable store region. -+ -+ @retval EFI_SUCCESS The erase and unlock successfully completed. -+**/ -+EFI_STATUS -+NorFlashUnlockAndEraseSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN UINTN BlockAddress -+ ); -+ -+/** -+ Write a full or portion of a block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to write to. -+ @param[in] Offset Offset into the block at which to begin writing. -+ @param[in,out] NumBytes The total size of the buffer. -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashWriteSingleBlock ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN UINT8 *Buffer -+ ); -+ -+/** -+ Write a full block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to write to. -+ @param[in] BufferSizeInBytes The number of bytes to write. -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashWriteBlocks ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN BufferSizeInBytes, -+ IN VOID *Buffer -+ ); -+ -+/** -+ Read a full block. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to read from. -+ @param[in] BufferSizeInBytes The number of bytes to read. -+ @param[out] Buffer The pointer to a caller-allocated buffer that -+ should be copied with read data. -+ -+ @retval EFI_SUCCESS The read is completed. -+**/ -+EFI_STATUS -+NorFlashReadBlocks ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN BufferSizeInBytes, -+ OUT VOID *Buffer -+ ); -+ -+/** -+ Read from nor flash. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[in] Lba The starting logical block index to read from. -+ @param[in] Offset Offset into the block at which to begin reading. -+ @param[in] BufferSizeInBytes The number of bytes to read. -+ @param[out] Buffer The pointer to a caller-allocated buffer that -+ should copied with read data. -+ -+ @retval EFI_SUCCESS The read is completed. -+**/ -+EFI_STATUS -+NorFlashRead ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN UINTN BufferSizeInBytes, -+ OUT VOID *Buffer -+ ); -+ -+/** -+ Read JEDEC ID of NOR flash device. -+ -+ @param[in] Instance NOR flash Instance of variable store region. -+ @param[out] JedecId JEDEC ID of NOR flash device. -+ -+ @retval EFI_SUCCESS The write is completed. -+**/ -+EFI_STATUS -+NorFlashReadID ( -+ IN NOR_FLASH_INSTANCE *Instance, -+ OUT UINT8 JedecId[3] -+ ); -+ -+#define SPINOR_OP_WREN 0x06 // Write enable -+#define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block -+#define SPINOR_OP_RDID 0x9f // Read JEDEC ID -+ -+#endif /* NOR_FLASH_DXE_H_ */ -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c -new file mode 100644 -index 00000000..edd84c07 ---- /dev/null -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlashFvb.c -@@ -0,0 +1,573 @@ -+/** @file -+ -+ Copyright (c) 2023, ARM Limited. All rights reserved.
-+ -+ SPDX-License-Identifier: BSD-2-Clause-Patent -+ -+**/ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "NorFlash.h" -+ -+UINTN mFlashNvStorageVariableBase; -+ -+/** -+ Initialize the FV Header and Variable Store Header -+ to support variable operations. -+ -+ @param[in] Instance Location to initialise the headers. -+ -+ @retval EFI_SUCCESS Fv init is done. -+ -+**/ -+EFI_STATUS -+InitializeFvAndVariableStoreHeaders ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ) -+{ -+ EFI_STATUS Status; -+ VOID* Headers; -+ UINTN HeadersLength; -+ EFI_FIRMWARE_VOLUME_HEADER *FirmwareVolumeHeader; -+ VARIABLE_STORE_HEADER *VariableStoreHeader; -+ -+ if (!Instance->Initialized && Instance->Initialize) { -+ Instance->Initialize (Instance); -+ } -+ -+ HeadersLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + -+ sizeof (EFI_FV_BLOCK_MAP_ENTRY) + -+ sizeof (VARIABLE_STORE_HEADER); -+ Headers = AllocateZeroPool (HeadersLength); -+ -+ FirmwareVolumeHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Headers; -+ CopyGuid (&FirmwareVolumeHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid); -+ FirmwareVolumeHeader->FvLength = -+ PcdGet32 (PcdFlashNvStorageVariableSize) + -+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + -+ PcdGet32 (PcdFlashNvStorageFtwSpareSize); -+ FirmwareVolumeHeader->Signature = EFI_FVH_SIGNATURE; -+ FirmwareVolumeHeader->Attributes = EFI_FVB2_READ_ENABLED_CAP | -+ EFI_FVB2_READ_STATUS | -+ EFI_FVB2_STICKY_WRITE | -+ EFI_FVB2_MEMORY_MAPPED | -+ EFI_FVB2_ERASE_POLARITY | -+ EFI_FVB2_WRITE_STATUS | -+ EFI_FVB2_WRITE_ENABLED_CAP; -+ -+ FirmwareVolumeHeader->HeaderLength = sizeof (EFI_FIRMWARE_VOLUME_HEADER) + -+ sizeof (EFI_FV_BLOCK_MAP_ENTRY); -+ FirmwareVolumeHeader->Revision = EFI_FVH_REVISION; -+ FirmwareVolumeHeader->BlockMap[0].NumBlocks = Instance->LastBlock + 1; -+ FirmwareVolumeHeader->BlockMap[0].Length = Instance->BlockSize; -+ FirmwareVolumeHeader->BlockMap[1].NumBlocks = 0; -+ FirmwareVolumeHeader->BlockMap[1].Length = 0; -+ FirmwareVolumeHeader->Checksum = CalculateCheckSum16 ( -+ (UINT16*)FirmwareVolumeHeader, -+ FirmwareVolumeHeader->HeaderLength); -+ -+ VariableStoreHeader = (VOID *)((UINTN)Headers + -+ FirmwareVolumeHeader->HeaderLength); -+ CopyGuid (&VariableStoreHeader->Signature, &gEfiAuthenticatedVariableGuid); -+ VariableStoreHeader->Size = PcdGet32 (PcdFlashNvStorageVariableSize) - -+ FirmwareVolumeHeader->HeaderLength; -+ VariableStoreHeader->Format = VARIABLE_STORE_FORMATTED; -+ VariableStoreHeader->State = VARIABLE_STORE_HEALTHY; -+ -+ // Install the combined super-header in the NorFlash -+ Status = FvbWrite (&Instance->FvbProtocol, 0, 0, &HeadersLength, Headers); -+ -+ FreePool (Headers); -+ return Status; -+} -+ -+/** -+ Check the integrity of firmware volume header. -+ -+ @param[in] Instance Instance of Nor flash variable region. -+ -+ @retval EFI_SUCCESS The firmware volume is consistent. -+ @retval EFI_NOT_FOUND The firmware volume has been corrupted. -+ -+**/ -+EFI_STATUS -+ValidateFvHeader ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ) -+{ -+ EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; -+ VARIABLE_STORE_HEADER *VariableStoreHeader; -+ UINTN VariableStoreLength; -+ UINTN FvLength; -+ -+ FwVolHeader = (EFI_FIRMWARE_VOLUME_HEADER*)Instance->RegionBaseAddress; -+ -+ FvLength = PcdGet32 (PcdFlashNvStorageVariableSize) + -+ PcdGet32 (PcdFlashNvStorageFtwWorkingSize) + -+ PcdGet32 (PcdFlashNvStorageFtwSpareSize); -+ -+ if ((FwVolHeader->Revision != EFI_FVH_REVISION) -+ || (FwVolHeader->Signature != EFI_FVH_SIGNATURE) -+ || (FwVolHeader->FvLength != FvLength) -+ ) -+ { -+ DEBUG ((DEBUG_ERROR, "%a: No Firmware Volume header present\n", -+ __FUNCTION__)); -+ return EFI_NOT_FOUND; -+ } -+ -+ // Check the Firmware Volume Guid -+ if (!CompareGuid (&FwVolHeader->FileSystemGuid, &gEfiSystemNvDataFvGuid)) { -+ DEBUG ((DEBUG_ERROR, "%a: Firmware Volume Guid non-compatible\n", -+ __FUNCTION__)); -+ return EFI_NOT_FOUND; -+ } -+ -+ VariableStoreHeader = (VOID *)((UINTN)FwVolHeader + -+ FwVolHeader->HeaderLength); -+ -+ // Check the Variable Store Guid -+ if (!CompareGuid (&VariableStoreHeader->Signature, &gEfiVariableGuid) && -+ !CompareGuid (&VariableStoreHeader->Signature, -+ &gEfiAuthenticatedVariableGuid)) { -+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Guid non-compatible\n", -+ __FUNCTION__)); -+ return EFI_NOT_FOUND; -+ } -+ -+ VariableStoreLength = PcdGet32 (PcdFlashNvStorageVariableSize) - -+ FwVolHeader->HeaderLength; -+ if (VariableStoreHeader->Size != VariableStoreLength) { -+ DEBUG ((DEBUG_ERROR, "%a: Variable Store Length does not match\n", -+ __FUNCTION__)); -+ return EFI_NOT_FOUND; -+ } -+ return EFI_SUCCESS; -+} -+ -+/** -+ Retrieves the attributes and current settings of the block. -+ -+ @param[in] This Indicates the EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[out] Attributes Pointer to EFI_FVB_ATTRIBUTES_2 in which the attributes and -+ current settings are returned. -+ Type EFI_FVB_ATTRIBUTES_2 is defined in -+ EFI_FIRMWARE_VOLUME_HEADER. -+ -+ @retval EFI_SUCCESS The firmware volume attributes were returned. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetAttributes( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes -+ ) -+{ -+ EFI_FVB_ATTRIBUTES_2 FlashFvbAttributes; -+ -+ FlashFvbAttributes = EFI_FVB2_READ_ENABLED_CAP | EFI_FVB2_READ_STATUS | -+ EFI_FVB2_WRITE_ENABLED_CAP | EFI_FVB2_WRITE_STATUS | -+ EFI_FVB2_STICKY_WRITE | EFI_FVB2_MEMORY_MAPPED | -+ EFI_FVB2_ERASE_POLARITY; -+ -+ *Attributes = FlashFvbAttributes; -+ -+ DEBUG ((DEBUG_INFO, "FvbGetAttributes(0x%X)\n", *Attributes)); -+ -+ return EFI_SUCCESS; -+} -+ -+/** -+ Sets configurable firmware volume attributes and returns the -+ new settings of the firmware volume. -+ -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in, out] Attributes On input, Attributes is a pointer to -+ EFI_FVB_ATTRIBUTES_2 that contains the desired -+ firmware volume settings. -+ On successful return, it contains the new -+ settings of the firmware volume. -+ -+ @retval EFI_UNSUPPORTED The firmware volume attributes are not supported. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbSetAttributes( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes -+ ) -+{ -+ DEBUG ((DEBUG_INFO, "FvbSetAttributes(0x%X) is not supported\n", -+ *Attributes)); -+ return EFI_UNSUPPORTED; -+} -+ -+/** -+ Retrieves the base address of a memory-mapped firmware volume. -+ This function should be called only for memory-mapped firmware volumes. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[out] Address Pointer to a caller-allocated -+ EFI_PHYSICAL_ADDRESS that, on successful -+ return from GetPhysicalAddress(), contains the -+ base address of the firmware volume. -+ -+ @retval EFI_SUCCESS The firmware volume base address was returned. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetPhysicalAddress ( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ OUT EFI_PHYSICAL_ADDRESS *Address -+ ) -+{ -+ NOR_FLASH_INSTANCE *Instance; -+ -+ Instance = INSTANCE_FROM_FVB_THIS (This); -+ -+ DEBUG ((DEBUG_INFO, "FvbGetPhysicalAddress(BaseAddress=0x%08x)\n", -+ Instance->RegionBaseAddress)); -+ -+ ASSERT(Address != NULL); -+ -+ *Address = Instance->RegionBaseAddress; -+ return EFI_SUCCESS; -+} -+ -+/** -+ Retrieves the size of the requested block. -+ It also returns the number of additional blocks with the identical size. -+ The GetBlockSize() function is used to retrieve the block map -+ (see EFI_FIRMWARE_VOLUME_HEADER). -+ -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba Indicates the block whose size to return -+ -+ @param[out] BlockSize Pointer to a caller-allocated UINTN in which -+ the size of the block is returned. -+ -+ @param[out] NumberOfBlocks Pointer to a caller-allocated UINTN in -+ which the number of consecutive blocks, -+ starting with Lba, is returned. All -+ blocks in this range have a size of -+ BlockSize. -+ -+ @retval EFI_SUCCESS The firmware volume base address was returned. -+ -+ @retval EFI_INVALID_PARAMETER The requested LBA is out of range. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbGetBlockSize ( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ OUT UINTN *BlockSize, -+ OUT UINTN *NumberOfBlocks -+ ) -+{ -+ EFI_STATUS Status; -+ NOR_FLASH_INSTANCE *Instance; -+ -+ Instance = INSTANCE_FROM_FVB_THIS (This); -+ -+ DEBUG ((DEBUG_INFO, -+ "FvbGetBlockSize(Lba=%ld, BlockSize=0x%x, LastBlock=%ld)\n", Lba, -+ Instance->BlockSize, Instance->LastBlock)); -+ -+ if (Lba > Instance->LastBlock) { -+ DEBUG ((DEBUG_ERROR, -+ "FvbGetBlockSize: ERROR - Parameter LBA %ld is beyond the last Lba (%ld).\n", -+ Lba, Instance->LastBlock)); -+ Status = EFI_INVALID_PARAMETER; -+ } else { -+ // This is easy because in this platform each NorFlash device has equal sized blocks. -+ *BlockSize = (UINTN) Instance->BlockSize; -+ *NumberOfBlocks = (UINTN) (Instance->LastBlock - Lba + 1); -+ -+ DEBUG ((DEBUG_INFO, -+ "FvbGetBlockSize: *BlockSize=0x%x, *NumberOfBlocks=0x%x.\n", *BlockSize, -+ *NumberOfBlocks)); -+ -+ Status = EFI_SUCCESS; -+ } -+ -+ return Status; -+} -+ -+/** -+ Reads the specified number of bytes into a buffer from the specified block. -+ -+ The Read() function reads the requested number of bytes from the -+ requested block and stores them in the provided buffer. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba The starting logical block index from which to read -+ -+ @param[in] Offset Offset into the block at which to begin reading. -+ -+ @param[in, out] NumBytes Pointer to a UINTN. -+ At entry, *NumBytes contains the total size of the -+ buffer. *NumBytes should have a non zero value. -+ At exit, *NumBytes contains the total number of -+ bytes read. -+ -+ @param[in, out] Buffer Pointer to a caller-allocated buffer that will be -+ used to hold the data that is read. -+ -+ @retval EFI_SUCCESS The firmware volume was read successfully, and -+ contents are in Buffer. -+ -+ @retval EFI_BAD_BUFFER_SIZE Read attempted across an LBA boundary. -+ -+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly and -+ could not be read. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbRead ( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN OUT UINT8 *Buffer -+ ) -+{ -+ EFI_STATUS Status; -+ UINTN BlockSize; -+ NOR_FLASH_INSTANCE *Instance; -+ -+ Instance = INSTANCE_FROM_FVB_THIS (This); -+ -+ DEBUG ((DEBUG_INFO, -+ "FvbRead(Parameters: Lba=%ld, Offset=0x%x, *NumBytes=0x%x, Buffer @ 0x%08x)\n", -+ Instance->StartLba + Lba, Offset, *NumBytes, Buffer)); -+ -+ if (!Instance->Initialized && Instance->Initialize) { -+ Instance->Initialize(Instance); -+ } -+ -+ BlockSize = Instance->BlockSize; -+ -+ DEBUG ((DEBUG_INFO, -+ "FvbRead: Check if (Offset=0x%x + NumBytes=0x%x) <= BlockSize=0x%x\n", -+ Offset, *NumBytes, BlockSize )); -+ -+ // The read must not span block boundaries. -+ // We need to check each variable individually because adding two large -+ // values together overflows. -+ if (Offset >= BlockSize || -+ *NumBytes > BlockSize || -+ (Offset + *NumBytes) > BlockSize) { -+ DEBUG ((DEBUG_ERROR, -+ "FvbRead: ERROR - EFI_BAD_BUFFER_SIZE: (Offset=0x%x + NumBytes=0x%x) > BlockSize=0x%x\n", -+ Offset, *NumBytes, BlockSize )); -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // We must have some bytes to read -+ if (*NumBytes == 0) { -+ return EFI_BAD_BUFFER_SIZE; -+ } -+ -+ // Decide if we are doing full block reads or not. -+ if (*NumBytes % BlockSize != 0) { -+ Status = NorFlashRead (Instance, Instance->StartLba + Lba, Offset, -+ *NumBytes, Buffer); -+ } else { -+ // Read NOR Flash data into shadow buffer -+ Status = NorFlashReadBlocks (Instance, Instance->StartLba + Lba, -+ BlockSize, Buffer); -+ } -+ if (EFI_ERROR (Status)) { -+ // Return one of the pre-approved error statuses -+ return EFI_DEVICE_ERROR; -+ } -+ return EFI_SUCCESS; -+} -+ -+/** -+ Writes the specified number of bytes from the input buffer to the block. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL instance. -+ -+ @param[in] Lba The starting logical block index to write to. -+ -+ @param[in] Offset Offset into the block at which to begin writing. -+ -+ @param[in, out] NumBytes The pointer to a UINTN. -+ At entry, *NumBytes contains the total size of the -+ buffer. -+ At exit, *NumBytes contains the total number of -+ bytes actually written. -+ -+ @param[in] Buffer The pointer to a caller-allocated buffer that -+ contains the source for the write. -+ -+ @retval EFI_SUCCESS The firmware volume was written successfully. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbWrite ( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ IN EFI_LBA Lba, -+ IN UINTN Offset, -+ IN OUT UINTN *NumBytes, -+ IN UINT8 *Buffer -+ ) -+{ -+ NOR_FLASH_INSTANCE *Instance; -+ -+ Instance = INSTANCE_FROM_FVB_THIS (This); -+ -+ return NorFlashWriteSingleBlock (Instance, Instance->StartLba + Lba, Offset, -+ NumBytes, Buffer); -+} -+ -+/** -+ Erases and initialises a firmware volume block. -+ -+ @param[in] This EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL -+ -+ @param[in] ... The variable argument list is a list of tuples. -+ Each tuple describes a range of LBAs to erase -+ and consists of the following: -+ - An EFI_LBA that indicates the starting LBA -+ - A UINTN that indicates the number of blocks -+ to erase. -+ -+ The list is terminated with an -+ EFI_LBA_LIST_TERMINATOR. -+ -+ @retval EFI_SUCCESS The erase request successfully completed. -+ -+ @retval EFI_ACCESS_DENIED The firmware volume is in the WriteDisabled -+ state. -+ -+ @retval EFI_DEVICE_ERROR The block device is not functioning correctly -+ and could not be written. -+ The firmware device may have been partially -+ erased. -+ -+ @retval EFI_INVALID_PARAMETER One or more of the LBAs listed in the variable -+ argument list do not exist in the firmware -+ volume. -+ -+**/ -+EFI_STATUS -+EFIAPI -+FvbEraseBlocks ( -+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This, -+ ... -+ ) -+{ -+ EFI_STATUS Status; -+ VA_LIST Args; -+ UINTN BlockAddress; // Physical address of Lba to erase -+ EFI_LBA StartingLba; // Lba from which we start erasing -+ UINTN NumOfLba; // Number of Lba blocks to erase -+ NOR_FLASH_INSTANCE *Instance; -+ -+ Instance = INSTANCE_FROM_FVB_THIS (This); -+ -+ DEBUG ((DEBUG_INFO, "FvbEraseBlocks()\n")); -+ -+ Status = EFI_SUCCESS; -+ -+ // Before erasing, check the entire list of parameters to ensure -+ // all specified blocks are valid -+ -+ VA_START (Args, This); -+ do { -+ // Get the Lba from which we start erasing -+ StartingLba = VA_ARG (Args, EFI_LBA); -+ -+ // Have we reached the end of the list? -+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) { -+ break; -+ } -+ -+ // How many Lba blocks are we requested to erase? -+ NumOfLba = VA_ARG (Args, UINT32); -+ -+ // All blocks must be within range -+ DEBUG ((DEBUG_INFO, -+ "FvbEraseBlocks: Check if: ( StartingLba=%ld + NumOfLba=%d - 1 ) > LastBlock=%ld.\n", -+ Instance->StartLba + StartingLba, NumOfLba, Instance->LastBlock)); -+ if (NumOfLba == 0 || -+ (Instance->StartLba + StartingLba + NumOfLba - 1) > -+ Instance->LastBlock) { -+ VA_END (Args); -+ DEBUG ((DEBUG_ERROR, -+ "FvbEraseBlocks: ERROR - Lba range goes past the last Lba.\n")); -+ return EFI_INVALID_PARAMETER; -+ } -+ } while (TRUE); -+ VA_END (Args); -+ -+ VA_START (Args, This); -+ do { -+ // Get the Lba from which we start erasing -+ StartingLba = VA_ARG (Args, EFI_LBA); -+ -+ // Have we reached the end of the list? -+ if (StartingLba == EFI_LBA_LIST_TERMINATOR) { -+ // Exit the while loop -+ break; -+ } -+ -+ // How many Lba blocks are we requested to erase? -+ NumOfLba = VA_ARG (Args, UINT32); -+ -+ // Go through each one and erase it -+ while (NumOfLba > 0) { -+ -+ // Get the physical address of Lba to erase -+ BlockAddress = GET_NOR_BLOCK_ADDRESS ( -+ Instance->RegionBaseAddress, -+ Instance->StartLba + StartingLba, -+ Instance->BlockSize -+ ); -+ -+ // Erase it -+ DEBUG ((DEBUG_INFO, "FvbEraseBlocks: Erasing Lba=%ld @ 0x%08x.\n", -+ Instance->StartLba + StartingLba, BlockAddress)); -+ Status = NorFlashUnlockAndEraseSingleBlock (Instance, BlockAddress); -+ if (EFI_ERROR(Status)) { -+ VA_END (Args); -+ return EFI_DEVICE_ERROR; -+ } -+ -+ // Move to the next Lba -+ StartingLba++; -+ NumOfLba--; -+ } -+ } while (TRUE); -+ VA_END (Args); -+ -+ return Status; -+ -+} -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dec b/Platform/ARM/N1Sdp/N1SdpPlatform.dec -index 16937197..986a078f 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dec -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dec -@@ -1,7 +1,7 @@ - ## @file - # Describes the N1Sdp configuration. - # --# Copyright (c) 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2021-2022, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - ## -@@ -89,3 +89,6 @@ - # unmapped reserved region results in a DECERR response. - # - gArmN1SdpTokenSpaceGuid.PcdCsComponentSize|0x1000|UINT32|0x00000049 -+ -+ # Base address of Cadence QSPI controller configuration registers -+ gArmN1SdpTokenSpaceGuid.PcdCadenceQspiDxeRegBaseAddress|0x1C0C0000|UINT32|0x0000004A diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch deleted file mode 100644 index 197a6eca48..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0006-Platform-ARM-N1Sdp-Persistent-storage-for-N1Sdp.patch +++ /dev/null @@ -1,88 +0,0 @@ -From e79fd5cfa3190eb27a9637facc9891cab55b5e09 Mon Sep 17 00:00:00 2001 -From: sahil -Date: Mon, 2 May 2022 19:24:47 +0530 -Subject: [PATCH] Platform/ARM/N1Sdp: Persistent storage for N1Sdp - -Enable persistent storage on QSPI flash device. - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: I403113bb885d1d411d433a7f266715d007509a5e ---- - Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 18 +++++++++++++----- - Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 4 +++- - 2 files changed, 16 insertions(+), 6 deletions(-) - -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -index 676ab677..80bc875a 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -@@ -44,6 +44,9 @@ - # file explorer library support - FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf - -+ # NOR flash support -+ NorFlashInfoLib|EmbeddedPkg/Library/NorFlashInfoLib/NorFlashInfoLib.inf -+ - [LibraryClasses.common.SEC] - HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf - MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf -@@ -161,11 +164,9 @@ - # ACPI Table Version - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 - -- # Runtime Variable storage -- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 -- gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE -- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 -- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxAuthVariableSize|0x2800 -+ # NOR flash support -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000 -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000 - - ################################################################################ - # -@@ -197,6 +198,12 @@ - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F - } - -+ # NOR flash support -+ Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf { -+ -+ NorFlashPlatformLib|Silicon/ARM/NeoverseN1Soc/Library/NorFlashLib/NorFlashLib.inf -+ } -+ - # Architectural Protocols - ArmPkg/Drivers/CpuDxe/CpuDxe.inf - ArmPkg/Drivers/ArmGic/ArmGicDxe.inf -@@ -217,6 +224,7 @@ - MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { - - NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf -+ NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } - -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -index e5e24ea5..4329f892 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -@@ -1,7 +1,7 @@ - ## @file - # FDF file of N1Sdp - # --# Copyright (c) 2018 - 2021, ARM Limited. All rights reserved.
-+# Copyright (c) 2018 - 2023, ARM Limited. All rights reserved.
- # - # SPDX-License-Identifier: BSD-2-Clause-Patent - ## -@@ -140,6 +140,8 @@ READ_LOCK_STATUS = TRUE - INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf - INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf - -+ INF Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -+ - INF Platform/ARM/Drivers/BootMonFs/BootMonFs.inf - INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf - diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch deleted file mode 100644 index 3951b48be4..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0007-Platform-ARM-N1Sdp-Enable-FaultTolerantWrite-Dxe-dri.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 5e8fbb3ba0f634f7fc873c6577269845f9e243db Mon Sep 17 00:00:00 2001 -From: sahil -Date: Mon, 2 May 2022 19:28:19 +0530 -Subject: [PATCH] Platform/ARM/N1Sdp: Enable FaultTolerantWrite Dxe driver for - N1Sdp - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: If448ad95b2e72cef31ce1e1e5ab2504d607f0545 ---- - Platform/ARM/N1Sdp/N1SdpPlatform.dsc | 5 +++++ - Platform/ARM/N1Sdp/N1SdpPlatform.fdf | 1 + - 2 files changed, 6 insertions(+) - -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -index 80bc875a..90a0d5b6 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.dsc -@@ -165,6 +165,10 @@ - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20 - - # NOR flash support -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x18F40000 -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00020000 -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x18F20000 -+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00020000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x18F00000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00020000 - -@@ -227,6 +231,7 @@ - NULL|EmbeddedPkg/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf - BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf - } -+ MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - - # ACPI Support - MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf -diff --git a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -index 4329f892..17d370a3 100644 ---- a/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -+++ b/Platform/ARM/N1Sdp/N1SdpPlatform.fdf -@@ -90,6 +90,7 @@ READ_LOCK_STATUS = TRUE - INF MdeModulePkg/Universal/Metronome/Metronome.inf - INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf - INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf -+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf - INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf - INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf - INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf diff --git a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch b/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch deleted file mode 100644 index 8e14699585..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-bsp/uefi/files/n1sdp/0008-Platform-ARM-N1Sdp-manually-poll-QSPI-status-bit-aft.patch +++ /dev/null @@ -1,197 +0,0 @@ -From 6d274379f584a638c1f2b4b8a19014d4baef1d9f Mon Sep 17 00:00:00 2001 -From: sahil -Date: Thu, 11 Aug 2022 11:26:29 +0530 -Subject: [PATCH] Platform/ARM/N1Sdp: manually poll QSPI status bit after - erase/write - -This patch adds a function to poll Nor flash memory's status register -bit (WIP bit) to wait for an erase/write operation to complete. -The polling timeout is set to 1 second. - -Upstream-Status: Pending -Signed-off-by: Xueliang Zhong -Signed-off-by: sahil -Change-Id: Ie678b7586671964ae0f8506a0542d73cbddddfe4 ---- - .../Drivers/CadenceQspiDxe/CadenceQspiDxe.inf | 1 + - .../Drivers/CadenceQspiDxe/CadenceQspiReg.h | 6 +- - .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c | 80 ++++++++++++++++++- - .../N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h | 5 ++ - 4 files changed, 88 insertions(+), 4 deletions(-) - -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -index 4f20c3ba..7a39eb2d 100644 ---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiDxe.inf -@@ -39,6 +39,7 @@ - MemoryAllocationLib - NorFlashInfoLib - NorFlashPlatformLib -+ TimerLib - UefiBootServicesTableLib - UefiDriverEntryPoint - UefiLib -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h -index fe3b327c..1971631d 100644 ---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/CadenceQspiReg.h -@@ -16,13 +16,15 @@ - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS 19 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS 16 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_STATUS_BIT 0x02 --#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_4B 0x03 --#define CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B 0x02 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS 24 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE 0x01 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_BYTE_3B 0x02 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS 23 - #define CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS 20 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C 0x8 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS 7 -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS) -+#define CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(x) ((x - 1) << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS) - - #define CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET 0xA0 - -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c -index 188c75e2..6832351a 100644 ---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.c -@@ -10,6 +10,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -184,6 +185,74 @@ FreeInstance: - return Status; - } - -+/** -+ Converts milliseconds into number of ticks of the performance counter. -+ -+ @param[in] Milliseconds Milliseconds to convert into ticks. -+ -+ @retval Milliseconds expressed as number of ticks. -+ -+**/ -+STATIC -+UINT64 -+MilliSecondsToTicks ( -+ IN UINTN Milliseconds -+ ) -+{ -+ CONST UINT64 NanoSecondsPerTick = GetTimeInNanoSecond (1); -+ -+ return (Milliseconds * 1000000) / NanoSecondsPerTick; -+} -+ -+/** -+ Poll Status register for NOR flash erase/write completion. -+ -+ @param[in] Instance NOR flash Instance. -+ -+ @retval EFI_SUCCESS Request is executed successfully. -+ @retval EFI_TIMEOUT Operation timed out. -+ @retval EFI_DEVICE_ERROR Controller operartion failed. -+ -+**/ -+STATIC -+EFI_STATUS -+NorFlashPollStatusRegister ( -+ IN NOR_FLASH_INSTANCE *Instance -+ ) -+{ -+ BOOLEAN SRegDone; -+ UINT32 val; -+ -+ val = SPINOR_OP_RDSR << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(1) | -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_8C << CDNS_QSPI_FLASH_CMD_CTRL_REG_DUMMY_BIT_POS; -+ -+ CONST UINT64 TickOut = -+ GetPerformanceCounter () + MilliSecondsToTicks (SPINOR_SR_WIP_POLL_TIMEOUT_MS); -+ -+ do { -+ if (GetPerformanceCounter () > TickOut) { -+ DEBUG (( -+ DEBUG_ERROR, -+ "NorFlashPollStatusRegister: Timeout waiting for erase/write.\n" -+ )); -+ return EFI_TIMEOUT; -+ } -+ -+ if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { -+ return EFI_DEVICE_ERROR; -+ } -+ -+ SRegDone = -+ (MmioRead8 (Instance->HostRegisterBaseAddress + CDNS_QSPI_FLASH_CMD_READ_DATA_REG_OFFSET) -+ & SPINOR_SR_WIP) == 0; -+ -+ } while (!SRegDone); -+ -+ return EFI_SUCCESS; -+} -+ - /** - Check whether NOR flash opertions are Locked. - -@@ -305,12 +374,16 @@ NorFlashEraseSingleBlock ( - - DevConfigVal = SPINOR_OP_BE_4K << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | - CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BIT_POS | -- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_BIT_POS; -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_ADDR_BYTES(3); - - if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, DevConfigVal))) { - return EFI_DEVICE_ERROR; - } - -+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) { -+ return EFI_DEVICE_ERROR; -+ } -+ - return EFI_SUCCESS; - } - -@@ -383,6 +456,9 @@ NorFlashWriteSingleWord ( - return EFI_DEVICE_ERROR; - } - MmioWrite32 (WordAddress, WriteData); -+ if (EFI_ERROR (NorFlashPollStatusRegister (Instance))) { -+ return EFI_DEVICE_ERROR; -+ } - return EFI_SUCCESS; - } - -@@ -907,7 +983,7 @@ NorFlashReadID ( - - val = SPINOR_OP_RDID << CDNS_QSPI_FLASH_CMD_CTRL_REG_OPCODE_BIT_POS | - CDNS_QSPI_FLASH_CMD_CTRL_REG_READ_ENABLE << CDNS_QSPI_FLASH_CMD_CTRL_REG_READEN_BIT_POS | -- CDNS_QSPI_FLASH_CMD_CTRL_REG_ADDR_BYTE_3B << CDNS_QSPI_FLASH_CMD_CTRL_REG_READBYTE_BIT_POS; -+ CDNS_QSPI_FLASH_CMD_CTRL_REG_NUM_DATA_BYTES(3); - - if (EFI_ERROR (CdnsQspiExecuteCommand (Instance, val))) { - return EFI_DEVICE_ERROR; -diff --git a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h -index e720937e..eb0afc60 100644 ---- a/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h -+++ b/Platform/ARM/N1Sdp/Drivers/CadenceQspiDxe/NorFlash.h -@@ -477,8 +477,13 @@ NorFlashReadID ( - OUT UINT8 JedecId[3] - ); - -+#define SPINOR_SR_WIP BIT0 // Write in progress -+ - #define SPINOR_OP_WREN 0x06 // Write enable - #define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block - #define SPINOR_OP_RDID 0x9f // Read JEDEC ID -+#define SPINOR_OP_RDSR 0x05 // Read status register -+ -+#define SPINOR_SR_WIP_POLL_TIMEOUT_MS 1000u // Status Register read timeout - - #endif /* NOR_FLASH_DXE_H_ */ diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch new file mode 100644 index 0000000000..329c939fb6 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch @@ -0,0 +1,138 @@ +From dc250cab31c6611cc7fa76bc8b2027dbd56dd65d Mon Sep 17 00:00:00 2001 +From: Pierre Gondois +Date: Mon, 7 Nov 2022 16:56:58 +0100 +Subject: [PATCH] arm64: dts: Update cache properties for Arm Ltd platforms + +The DeviceTree Specification v0.3 specifies that the cache node +"compatible" and "cache-level" properties are required. + +Cf. s3.8 Multi-level and Shared Cache Nodes +The 'cache-unified' property should be present if one of the properties +for unified cache is present ('cache-size', ...). + +Update the relevant device trees nodes accordingly. + +Signed-off-by: Pierre Gondois +Link: https://lore.kernel.org/r/20221107155825.1644604-6-pierre.gondois@arm.com +Signed-off-by: Sudeep Holla + +Signed-off-by: Jon Mason +Upstream-Status: Backport +--- + arch/arm64/boot/dts/arm/corstone1000.dtsi | 1 + + arch/arm64/boot/dts/arm/foundation-v8.dtsi | 1 + + arch/arm64/boot/dts/arm/juno-r1.dts | 2 ++ + arch/arm64/boot/dts/arm/juno-r2.dts | 2 ++ + arch/arm64/boot/dts/arm/juno.dts | 2 ++ + arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 1 + + arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts | 1 + + 7 files changed, 10 insertions(+) + +diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi +index 4e46826f883a..21f1f952e985 100644 +--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi ++++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi +@@ -53,6 +53,7 @@ gic: interrupt-controller@1c000000 { + + L2_0: l2-cache0 { + compatible = "cache"; ++ cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; +diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +index 83e3e7e3984f..c8bd23b1a7ba 100644 +--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi ++++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +@@ -58,6 +58,7 @@ cpu3: cpu@3 { + + L2_0: l2-cache0 { + compatible = "cache"; ++ cache-level = <2>; + }; + }; + +diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts +index 6451c62146fd..1d90eeebb37d 100644 +--- a/arch/arm64/boot/dts/arm/juno-r1.dts ++++ b/arch/arm64/boot/dts/arm/juno-r1.dts +@@ -189,6 +189,7 @@ A53_3: cpu@103 { + + A57_L2: l2-cache0 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; +@@ -197,6 +198,7 @@ A57_L2: l2-cache0 { + + A53_L2: l2-cache1 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; +diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts +index 438cd1ff4bd0..d2ada69b0a43 100644 +--- a/arch/arm64/boot/dts/arm/juno-r2.dts ++++ b/arch/arm64/boot/dts/arm/juno-r2.dts +@@ -195,6 +195,7 @@ A53_3: cpu@103 { + + A72_L2: l2-cache0 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; +@@ -203,6 +204,7 @@ A72_L2: l2-cache0 { + + A53_L2: l2-cache1 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; +diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts +index cf4a58211399..5e48a01a5b9f 100644 +--- a/arch/arm64/boot/dts/arm/juno.dts ++++ b/arch/arm64/boot/dts/arm/juno.dts +@@ -194,6 +194,7 @@ A53_3: cpu@103 { + + A57_L2: l2-cache0 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; +@@ -202,6 +203,7 @@ A57_L2: l2-cache0 { + + A53_L2: l2-cache1 { + compatible = "cache"; ++ cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; +diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +index 258991ad7cc0..ef68f5aae7dd 100644 +--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts ++++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts +@@ -71,6 +71,7 @@ cpu@3 { + + L2_0: l2-cache0 { + compatible = "cache"; ++ cache-level = <2>; + }; + }; + +diff --git a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +index 5b6d9d8e934d..796cd7d02eb5 100644 +--- a/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts ++++ b/arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts +@@ -57,6 +57,7 @@ cpu@1 { + + L2_0: l2-cache0 { + compatible = "cache"; ++ cache-level = <2>; + }; + }; + diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch new file mode 100644 index 0000000000..4495f397bd --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch @@ -0,0 +1,35 @@ +From bd354219987dddbf8ab6fd11450b4046547aca1b Mon Sep 17 00:00:00 2001 +From: James Clark +Date: Thu, 17 Nov 2022 10:25:36 +0000 +Subject: [PATCH] arm64: dts: fvp: Add SPE to Foundation FVP + +Add SPE DT node to FVP model. If the model doesn't support SPE (e.g., +turned off via parameter), the driver will skip the initialisation +accordingly and thus is safe. + +Signed-off-by: James Clark +Link: https://lore.kernel.org/r/20221117102536.237515-1-james.clark@arm.com +Signed-off-by: Sudeep Holla + +Signed-off-by: Jon Mason +Upstream-Status: Backport +--- + arch/arm64/boot/dts/arm/foundation-v8.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +index c8bd23b1a7ba..029578072d8f 100644 +--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi ++++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi +@@ -85,6 +85,11 @@ pmu { + ; + }; + ++ spe-pmu { ++ compatible = "arm,statistical-profiling-extension-v1"; ++ interrupts = ; ++ }; ++ + watchdog@2a440000 { + compatible = "arm,sbsa-gwdt"; + reg = <0x0 0x2a440000 0 0x1000>, diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch new file mode 100644 index 0000000000..fc02751004 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch @@ -0,0 +1,146 @@ +From 22e740d069e14875a64864bf86e0826a96560b44 Mon Sep 17 00:00:00 2001 +From: Sudeep Holla +Date: Fri, 18 Nov 2022 15:10:17 +0000 +Subject: [PATCH] arm64: dts: fvp: Add information about L1 and L2 caches + +Add the information about L1 and L2 caches on FVP RevC platform. +Though the cache size is configurable through the model parameters, +having default values in the device tree helps to exercise and debug +any code utilising the cache information without the need of real +hardware. + +Link: https://lore.kernel.org/r/20221118151017.704716-1-sudeep.holla@arm.com +Signed-off-by: Sudeep Holla + +Signed-off-by: Jon Mason +Upstream-Status: Backport +--- + arch/arm64/boot/dts/arm/fvp-base-revc.dts | 73 +++++++++++++++++++++++ + 1 file changed, 73 insertions(+) + +diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts +index 5f6f30c801a7..60472d65a355 100644 +--- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts ++++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts +@@ -47,48 +47,121 @@ cpu0: cpu@0 { + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C0_L2>; + }; + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C0_L2>; + }; + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C0_L2>; + }; + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C0_L2>; + }; + cpu4: cpu@10000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10000>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C1_L2>; + }; + cpu5: cpu@10100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10100>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C1_L2>; + }; + cpu6: cpu@10200 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10200>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C1_L2>; + }; + cpu7: cpu@10300 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x10300>; + enable-method = "psci"; ++ i-cache-size = <0x8000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; ++ d-cache-size = <0x8000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; ++ next-level-cache = <&C1_L2>; ++ }; ++ C0_L2: l2-cache0 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; ++ }; ++ ++ C1_L2: l2-cache1 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <64>; ++ cache-sets = <512>; ++ cache-level = <2>; ++ cache-unified; + }; + }; + diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch new file mode 100644 index 0000000000..e3828ec96a --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/files/juno/0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch @@ -0,0 +1,81 @@ +From 4edb625e2256d5761312110e34cbc0164915d772 Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Fri, 25 Nov 2022 15:41:12 +0100 +Subject: [PATCH] ARM: dts: vexpress: align LED node names with dtschema + +The node names should be generic and DT schema expects certain pattern. + + vexpress-v2p-ca9.dtb: leds: 'user1', 'user2', 'user3', 'user4', 'user5', 'user6', 'user7', 'user8' do not match any of the regexes: '(^led-[0-9a-f]$|led)', 'pinctrl-[0-9]+' + +Signed-off-by: Krzysztof Kozlowski +Link: https://lore.kernel.org/r/20221125144112.476817-1-krzysztof.kozlowski@linaro.org +Signed-off-by: Sudeep Holla + +Signed-off-by: Jon Mason +Upstream-Status: Backport +--- + arch/arm/boot/dts/vexpress-v2m.dtsi | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi +index f434fe5cf4a1..def538ce8769 100644 +--- a/arch/arm/boot/dts/vexpress-v2m.dtsi ++++ b/arch/arm/boot/dts/vexpress-v2m.dtsi +@@ -383,49 +383,49 @@ v2m_refclk32khz: refclk32khz { + leds { + compatible = "gpio-leds"; + +- user1 { ++ led-user1 { + label = "v2m:green:user1"; + gpios = <&v2m_led_gpios 0 0>; + linux,default-trigger = "heartbeat"; + }; + +- user2 { ++ led-user2 { + label = "v2m:green:user2"; + gpios = <&v2m_led_gpios 1 0>; + linux,default-trigger = "mmc0"; + }; + +- user3 { ++ led-user3 { + label = "v2m:green:user3"; + gpios = <&v2m_led_gpios 2 0>; + linux,default-trigger = "cpu0"; + }; + +- user4 { ++ led-user4 { + label = "v2m:green:user4"; + gpios = <&v2m_led_gpios 3 0>; + linux,default-trigger = "cpu1"; + }; + +- user5 { ++ led-user5 { + label = "v2m:green:user5"; + gpios = <&v2m_led_gpios 4 0>; + linux,default-trigger = "cpu2"; + }; + +- user6 { ++ led-user6 { + label = "v2m:green:user6"; + gpios = <&v2m_led_gpios 5 0>; + linux,default-trigger = "cpu3"; + }; + +- user7 { ++ led-user7 { + label = "v2m:green:user7"; + gpios = <&v2m_led_gpios 6 0>; + linux,default-trigger = "cpu4"; + }; + +- user8 { ++ led-user8 { + label = "v2m:green:user8"; + gpios = <&v2m_led_gpios 7 0>; + linux,default-trigger = "cpu5"; diff --git a/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc b/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc index b49ac800a2..64b1e41e60 100644 --- a/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc +++ b/meta-arm/meta-arm-bsp/recipes-kernel/linux/linux-arm-platforms.inc @@ -19,6 +19,13 @@ SRC_URI:append:juno = " ${SRC_URI_KMETA}" SRC_URI:append:n1sdp = " ${SRC_URI_KMETA}" SRCREV:arm-platforms-kmeta = "6147e82375aa9df8f2a162d42ea6406c79c854c5" +# +# Corstone-500 KMACHINE +# +COMPATIBLE_MACHINE:corstone500 = "corstone500" +KBUILD_DEFCONFIG:corstone500 = "multi_v7_defconfig" +KCONFIG_MODE:corstone500 = "--alldefconfig" + # # Corstone1000 KMACHINE # @@ -70,6 +77,12 @@ SRC_URI:append:fvp-baser-aemv8r64 = " file://fvp-baser-aemv8r64.dts;subdir=git/a # COMPATIBLE_MACHINE:juno = "juno" FILESEXTRAPATHS:prepend:juno := "${ARMBSPFILESPATHS}" +SRC_URI:append:juno = " \ + file://0001-arm64-dts-Update-cache-properties-for-Arm-Ltd-platfo.patch \ + file://0002-arm64-dts-fvp-Add-SPE-to-Foundation-FVP.patch \ + file://0003-arm64-dts-fvp-Add-information-about-L1-and-L2-caches.patch \ + file://0004-ARM-dts-vexpress-align-LED-node-names-with-dtschema.patch \ + " # # Musca B1/S2 can't run Linux diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0001-WIP-Enable-managed-exit.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0001-WIP-Enable-managed-exit.patch index 4571409bc6..0f0a76e4f1 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0001-WIP-Enable-managed-exit.patch +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0001-WIP-Enable-managed-exit.patch @@ -1,7 +1,7 @@ -From f449f6fdcbd987e18a26f0daeccfa447fe76821a Mon Sep 17 00:00:00 2001 +From 34db1357ab3192f18629ceadf4ea33b948513fec Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Mon, 16 Nov 2020 10:14:02 +0100 -Subject: [PATCH] WIP: Enable managed exit +Subject: [PATCH 1/2] WIP: Enable managed exit This change declares OP-TEE SP as supporting managed exit in response to a NS interrupt triggering while the SWd runs. @@ -23,7 +23,6 @@ Signed-off-by: Arunachalam Ganapathy Upstream-Status: Pending [Not submitted to upstream yet] Signed-off-by: Arunachalam Ganapathy - --- core/arch/arm/kernel/boot.c | 12 ++++++++++++ core/arch/arm/kernel/thread_a64.S | 11 ++++++++++- @@ -32,10 +31,10 @@ Signed-off-by: Arunachalam Ganapathy 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/core/arch/arm/kernel/boot.c b/core/arch/arm/kernel/boot.c -index dd34173e8..7d2ac74e8 100644 +index f173384d..466c042e 100644 --- a/core/arch/arm/kernel/boot.c +++ b/core/arch/arm/kernel/boot.c -@@ -1424,6 +1424,18 @@ static void init_secondary_helper(unsigned long nsec_entry) +@@ -1350,6 +1350,18 @@ static void init_secondary_helper(unsigned long nsec_entry) init_vfp_sec(); init_vfp_nsec(); @@ -55,10 +54,10 @@ index dd34173e8..7d2ac74e8 100644 } diff --git a/core/arch/arm/kernel/thread_a64.S b/core/arch/arm/kernel/thread_a64.S -index 4fa97de24..4facc7631 100644 +index d6baee4d..1b0c8f37 100644 --- a/core/arch/arm/kernel/thread_a64.S +++ b/core/arch/arm/kernel/thread_a64.S -@@ -1162,6 +1162,14 @@ END_FUNC el0_sync_abort +@@ -1087,6 +1087,14 @@ END_FUNC el0_sync_abort bl dcache_op_louis ic iallu #endif @@ -73,7 +72,7 @@ index 4fa97de24..4facc7631 100644 /* * Mark current thread as suspended */ -@@ -1318,8 +1326,9 @@ LOCAL_FUNC elx_irq , : +@@ -1204,8 +1212,9 @@ LOCAL_FUNC elx_irq , : #endif END_FUNC elx_irq @@ -85,10 +84,10 @@ index 4fa97de24..4facc7631 100644 #else native_intr_handler fiq diff --git a/core/arch/arm/kernel/thread_spmc.c b/core/arch/arm/kernel/thread_spmc.c -index 3b4ac0b4e..8f7c18dfa 100644 +index ea9e8f03..15577e7e 100644 --- a/core/arch/arm/kernel/thread_spmc.c +++ b/core/arch/arm/kernel/thread_spmc.c -@@ -1517,6 +1517,17 @@ static TEE_Result spmc_init(void) +@@ -1518,6 +1518,17 @@ static TEE_Result spmc_init(void) my_endpoint_id = spmc_get_id(); DMSG("My endpoint ID %#x", my_endpoint_id); @@ -107,7 +106,7 @@ index 3b4ac0b4e..8f7c18dfa 100644 } #endif /* !defined(CFG_CORE_SEL1_SPMC) */ diff --git a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts -index 3ebbaddc8..56e69f372 100644 +index 0bfe33f3..00cfa5b2 100644 --- a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts +++ b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts @@ -24,6 +24,7 @@ @@ -118,3 +117,6 @@ index 3ebbaddc8..56e69f372 100644 device-regions { compatible = "arm,ffa-manifest-device-regions"; +-- +2.34.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch index c516be4638..ff7f513357 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/files/optee-os/tc/0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch @@ -1,23 +1,23 @@ -From 5ddda749c60dce834bcd79e8b8d904858319adc0 Mon Sep 17 00:00:00 2001 -From: Rupinderjit Singh -Date: Tue, 7 Feb 2023 09:45:02 +0000 -Subject: [PATCH] plat-totalcompute: update TZDRAM_SIZE +From 35dba075593cb32c62b881e7763fcf0ea37908f7 Mon Sep 17 00:00:00 2001 +From: Arunachalam Ganapathy +Date: Mon, 23 May 2022 11:32:41 +0100 +Subject: [PATCH 2/2] plat-totalcompute: fix TZDRAM start and size -For CFG_CORE_SEL2_SPMC, manifest size is increased from 0x1000 to -0x4000 for boot protocol support. +- Fix TZDRAM_SIZE in TC platform +- For CFG_CORE_SEL2_SPMC, manifest size is increased from 0x1000 to + 0x4000 for boot protocol support. -Signed-off-by: Rupinderjit Singh -Acked-by: Jens Wiklander - -Upstream-Status: Backport -Signed-off-by: Jon Mason +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Arunachalam Ganapathy +Change-Id: Iff19c498e9edae961f469604d69419c1a32145f5 --- - core/arch/arm/plat-totalcompute/conf.mk | 5 +++-- - 1 file changed, 3 insertions(+), 2 deletions(-) + core/arch/arm/plat-totalcompute/conf.mk | 5 +++-- + core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts | 2 +- + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/core/arch/arm/plat-totalcompute/conf.mk b/core/arch/arm/plat-totalcompute/conf.mk -index b39ac0f0667f..2f6c0ee1460a 100644 +index b39ac0f0..2f6c0ee1 100644 --- a/core/arch/arm/plat-totalcompute/conf.mk +++ b/core/arch/arm/plat-totalcompute/conf.mk @@ -32,8 +32,9 @@ ifeq ($(CFG_CORE_SEL1_SPMC),y) @@ -32,3 +32,19 @@ index b39ac0f0667f..2f6c0ee1460a 100644 else CFG_TZDRAM_START ?= 0xff000000 CFG_TZDRAM_SIZE ?= 0x01000000 +diff --git a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts +index 00cfa5b2..56e69f37 100644 +--- a/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts ++++ b/core/arch/arm/plat-totalcompute/fdts/optee_sp_manifest.dts +@@ -20,7 +20,7 @@ + exception-level = <2>; /* S-EL1 */ + execution-state = <0>; /* AARCH64 */ + load-address = <0xfd280000>; +- entrypoint-offset = <0x1000>; ++ entrypoint-offset = <0x4000>; + xlat-granule = <0>; /* 4KiB */ + boot-order = <0>; + messaging-method = <0x3>; /* Direct request/response supported */ +-- +2.34.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-client/tee-supplicant.service b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-client/tee-supplicant.service index 6b00df7421..c273832d72 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-client/tee-supplicant.service +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-client/tee-supplicant.service @@ -1,6 +1,5 @@ [Unit] Description=TEE Supplicant -ConditionPathExistsGlob=/dev/teepriv[0-9]* [Service] User=root diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc index eaee7ae91c..1f028ffa37 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-corstone1000-common.inc @@ -1,3 +1,9 @@ +SRC_URI:remove = " \ + file://0003-core-link-add-no-warn-rwx-segments.patch \ + file://0007-core-spmc-handle-non-secure-interrupts.patch \ + file://0008-core-spmc-configure-SP-s-NS-interrupt-action-based-o.patch \ + " + COMPATIBLE_MACHINE = "corstone1000" OPTEEMACHINE = "corstone1000" diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-generic-tc.inc b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-generic-tc.inc new file mode 100644 index 0000000000..31f1915868 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-generic-tc.inc @@ -0,0 +1,14 @@ +# Total Compute (tc) specific configuration for optee-os and optee-os-tadevkit + +FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/tc:" +SRC_URI:append:tc = " \ + file://sp_layout.json \ + file://0001-WIP-Enable-managed-exit.patch \ + file://0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch \ + " + +COMPATIBLE_MACHINE = "(tc?)" + +OPTEEMACHINE:tc0 = "totalcompute-tc0" +OPTEEMACHINE:tc1 = "totalcompute-tc1" + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc index 80a11b5330..a40c93dcba 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-n1sdp.inc @@ -27,5 +27,3 @@ EXTRA_OEMAKE += " CFG_DT=y" EXTRA_OEMAKE += " CFG_SECURE_PARTITION=y" EXTRA_OEMAKE += " CFG_MAP_EXT_DT_SECURE=y" - -EXTRA_OEMAKE += " CFG_ENABLE_EMBEDDED_TESTS=y" diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tadevkit_3.18.0.bbappend b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tadevkit_3.18.0.bbappend index 0cb9b05e0b..6a22d47ef1 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tadevkit_3.18.0.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tadevkit_3.18.0.bbappend @@ -1,6 +1,6 @@ # Machine specific configurations MACHINE_OPTEE_OS_TADEVKIT_REQUIRE ?= "" -MACHINE_OPTEE_OS_TADEVKIT_REQUIRE:tc = "optee-os-tc.inc" +MACHINE_OPTEE_OS_TADEVKIT_REQUIRE:tc = "optee-os-generic-tc.inc" require ${MACHINE_OPTEE_OS_TADEVKIT_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tc.inc b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tc.inc index c4049f5afb..793665222b 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tc.inc +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os-tc.inc @@ -1,16 +1,6 @@ # TC0 specific configuration -# Total Compute (tc) specific configuration for optee-os and optee-os-tadevkit - -FILESEXTRAPATHS:prepend := "${THISDIR}/files/optee-os/tc:" -SRC_URI:append:tc = " file://sp_layout.json \ - file://0001-WIP-Enable-managed-exit.patch \ - file://0002-plat-totalcompute-fix-TZDRAM-start-and-size.patch \ - " - -COMPATIBLE_MACHINE = "(tc?)" - -OPTEEMACHINE:tc1 = "totalcompute-tc1" +require optee-os-generic-tc.inc # Enable optee memory layout and boot logs EXTRA_OEMAKE += " CFG_TEE_CORE_LOG_LEVEL=3" diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.20.0.bbappend b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.20.0.bbappend index bc933dd54c..b5493e5e2a 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.20.0.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.20.0.bbappend @@ -1,7 +1,7 @@ # Machine specific configurations MACHINE_OPTEE_OS_REQUIRE ?= "" +MACHINE_OPTEE_OS_REQUIRE:corstone1000 = "optee-os-corstone1000-common.inc" MACHINE_OPTEE_OS_REQUIRE:n1sdp = "optee-os-n1sdp.inc" -MACHINE_OPTEE_OS_REQUIRE:tc = "optee-os-tc.inc" require ${MACHINE_OPTEE_OS_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.22.0.bbappend b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.22.0.bbappend deleted file mode 100644 index e732c80f88..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-os_3.22.0.bbappend +++ /dev/null @@ -1,6 +0,0 @@ -# Machine specific configurations - -MACHINE_OPTEE_OS_REQUIRE ?= "" -MACHINE_OPTEE_OS_REQUIRE:corstone1000 = "optee-os-corstone1000-common.inc" - -require ${MACHINE_OPTEE_OS_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch deleted file mode 100644 index 98c49a2087..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 53642dc98630b9c725977ab935c5bdd9c401e1aa Mon Sep 17 00:00:00 2001 -From: Jon Mason -Date: Sat, 15 Jul 2023 15:08:43 -0400 -Subject: [PATCH] xtest: regression_1000: remove unneeded stat.h include - -Hack to work around musl compile error: - In file included from optee-test/3.17.0-r0/recipe-sysroot/usr/include/sys/stat.h:23, - from optee-test/3.17.0-r0/git/host/xtest/regression_1000.c:25: - optee-test/3.17.0-r0/recipe-sysroot/usr/include/bits/stat.h:17:26: error: expected identifier or '(' before '[' token - 17 | unsigned __unused[2]; - | ^ - -stat.h is not needed, since it is not being used in this file. So removing it. - -Upstream-Status: Backport -Signed-off-by: Jon Mason -Reviewed-by: Jerome Forissier -Acked-by: Jens Wiklander ---- - host/xtest/regression_1000.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/host/xtest/regression_1000.c b/host/xtest/regression_1000.c -index de32c4184fd8..25b4721cdc45 100644 ---- a/host/xtest/regression_1000.c -+++ b/host/xtest/regression_1000.c -@@ -22,7 +22,6 @@ - #include - #include - #include --#include - #include - #include - #include diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0002-ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0002-ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch deleted file mode 100644 index 24cdf0ad1a..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0002-ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch +++ /dev/null @@ -1,160 +0,0 @@ -From 717ff43f0d58e5f5a87893bd0cf3274a1e0164dc Mon Sep 17 00:00:00 2001 -From: Gabor Toth -Date: Fri, 3 Mar 2023 12:25:58 +0100 -Subject: [PATCH] ffa_spmc: Add arm_ffa_user driver compatibility check - -Check the version of the arm_ffa_user Kernel Driver and fail with a -meaningful message if incompatible driver is detected. - -Upstream-Status: Backport - -Signed-off-by: Gabor Toth -Acked-by: Jens Wiklander ---- - host/xtest/ffa_spmc_1000.c | 68 ++++++++++++++++++++++++++++++++++---- - 1 file changed, 61 insertions(+), 7 deletions(-) - -diff --git a/host/xtest/ffa_spmc_1000.c b/host/xtest/ffa_spmc_1000.c -index 15f4a468a775..1839d03f29be 100644 ---- a/host/xtest/ffa_spmc_1000.c -+++ b/host/xtest/ffa_spmc_1000.c -@@ -1,11 +1,12 @@ - // SPDX-License-Identifier: BSD-3-Clause - /* -- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. -+ * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. - */ - #include - #include - #include - #include -+#include - #include - #include - #include "include/uapi/linux/arm_ffa_user.h" -@@ -17,6 +18,10 @@ - #define INCORRECT_ENDPOINT_ID 0xffff - #define NORMAL_WORLD_ENDPOINT_ID 0 - -+#define FFA_USER_REQ_VER_MAJOR 5 -+#define FFA_USER_REQ_VER_MINOR 0 -+#define FFA_USER_REQ_VER_PATCH 1 -+ - /* Get the 32 least significant bits of a handle.*/ - #define MEM_SHARE_HANDLE_LOW(x) ((x) & 0xffffffff) - /* Get the 32 most significant bits of a handle.*/ -@@ -62,6 +67,50 @@ static struct ffa_ioctl_ep_desc test_endpoint3 = { - .uuid_ptr = (uint64_t)test_endpoint3_uuid, - }; - -+static bool check_ffa_user_version(void) -+{ -+ FILE *f = NULL; -+ int ver_major = -1; -+ int ver_minor = -1; -+ int ver_patch = -1; -+ int scan_cnt = 0; -+ -+ f = fopen("/sys/module/arm_ffa_user/version", "r"); -+ if (f) { -+ scan_cnt = fscanf(f, "%d.%d.%d", -+ &ver_major, &ver_minor, &ver_patch); -+ fclose(f); -+ if (scan_cnt != 3) { -+ printf("error: failed to parse arm_ffa_user version\n"); -+ return false; -+ } -+ } else { -+ printf("error: failed to read arm_ffa_user module info - %s\n", -+ strerror(errno)); -+ return false; -+ } -+ -+ if (ver_major != FFA_USER_REQ_VER_MAJOR) -+ goto err; -+ -+ if (ver_minor < FFA_USER_REQ_VER_MINOR) -+ goto err; -+ -+ if (ver_minor == FFA_USER_REQ_VER_MINOR) -+ if (ver_patch < FFA_USER_REQ_VER_PATCH) -+ goto err; -+ -+ return true; -+ -+err: -+ printf("error: Incompatible arm_ffa_user driver detected."); -+ printf("Found v%d.%d.%d wanted >= v%d.%d.%d)\n", -+ ver_major, ver_minor, ver_patch, FFA_USER_REQ_VER_MAJOR, -+ FFA_USER_REQ_VER_MINOR, FFA_USER_REQ_VER_PATCH); -+ -+ return false; -+} -+ - static void close_debugfs(void) - { - int err = 0; -@@ -76,6 +125,9 @@ static void close_debugfs(void) - - static bool init_sp_xtest(ADBG_Case_t *c) - { -+ if (!check_ffa_user_version()) -+ return false; -+ - if (ffa_fd < 0) { - ffa_fd = open(FFA_DRIVER_FS_PATH, O_RDWR); - if (ffa_fd < 0) { -@@ -83,6 +135,7 @@ static bool init_sp_xtest(ADBG_Case_t *c) - return false; - } - } -+ - return true; - } - -@@ -99,7 +152,7 @@ static uint16_t get_endpoint_id(uint64_t endp) - struct ffa_ioctl_ep_desc sid = { .uuid_ptr = endp }; - - /* Get ID of destination SP based on UUID */ -- if(ioctl(ffa_fd, FFA_IOC_GET_PART_ID, &sid)) -+ if (ioctl(ffa_fd, FFA_IOC_GET_PART_ID, &sid)) - return INCORRECT_ENDPOINT_ID; - - return sid.id; -@@ -213,14 +266,15 @@ static int set_up_mem(struct ffa_ioctl_ep_desc *endp, - rc = share_mem(endpoint, handle); - ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); - -- if (!ADBG_EXPECT_TRUE(c, handle != NULL)) -- return TEEC_ERROR_GENERIC; -+ if (!ADBG_EXPECT_NOT_NULL(c, handle)) -+ return TEEC_ERROR_GENERIC; - - /* SP will retrieve the memory region. */ - memset(args, 0, sizeof(*args)); - args->dst_id = endpoint; - args->args[MEM_SHARE_HANDLE_LOW_INDEX] = MEM_SHARE_HANDLE_LOW(*handle); -- args->args[MEM_SHARE_HANDLE_HIGH_INDEX] = MEM_SHARE_HANDLE_HIGH(*handle); -+ args->args[MEM_SHARE_HANDLE_HIGH_INDEX] = -+ MEM_SHARE_HANDLE_HIGH(*handle); - args->args[MEM_SHARE_HANDLE_ENDPOINT_INDEX] = NORMAL_WORLD_ENDPOINT_ID; - - rc = start_sp_test(endpoint, EP_RETRIEVE, args); -@@ -254,7 +308,7 @@ static void xtest_ffa_spmc_test_1002(ADBG_Case_t *c) - rc = start_sp_test(endpoint1_id, EP_TEST_SP, &args); - ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); - if (!ADBG_EXPECT_COMPARE_UNSIGNED(c, args.args[0], ==, SPMC_TEST_OK)) -- goto out; -+ goto out; - - /* Set up memory and have the SP retrieve it. */ - Do_ADBG_BeginSubCase(c, "Test memory set-up"); -@@ -469,7 +523,7 @@ static void xtest_ffa_spmc_test_1005(ADBG_Case_t *c) - memset(&args, 0, sizeof(args)); - args.args[1] = endpoint2; - args.args[2] = endpoint3; -- rc = start_sp_test(endpoint1, EP_SP_MEM_SHARING_MULTI,&args); -+ rc = start_sp_test(endpoint1, EP_SP_MEM_SHARING_MULTI, &args); - ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); - ADBG_EXPECT_COMPARE_UNSIGNED(c, args.args[0], ==, SPMC_TEST_OK); - diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0003-Update-arm_ffa_user-driver-dependency.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0003-Update-arm_ffa_user-driver-dependency.patch deleted file mode 100644 index 44d9f9477d..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/0003-Update-arm_ffa_user-driver-dependency.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 3de910a19f01a2a9e1c9a6bd6feee1aef547f676 Mon Sep 17 00:00:00 2001 -From: Gabor Toth -Date: Fri, 3 Mar 2023 12:23:45 +0100 -Subject: [PATCH] Update arm_ffa_user driver dependency - -Updating arm-ffa-user to v5.0.1 to get the following changes: - - move to 64 bit direct messages - - add Linux Kernel v6.1 compatibility -The motivation is to update x-test to depend on the same driver -version as TS uefi-test and thus to enable running these in a single -configuration. -Note: arm_ffa_user.h was copied from: - - URL:https://git.gitlab.arm.com/linux-arm/linux-trusted-services.git - - SHA:18e3be71f65a405dfb5d97603ae71b3c11759861 - -Upstream-Status: Backport - -Signed-off-by: Gabor Toth -Acked-by: Jens Wiklander ---- - host/xtest/include/uapi/linux/arm_ffa_user.h | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/host/xtest/include/uapi/linux/arm_ffa_user.h b/host/xtest/include/uapi/linux/arm_ffa_user.h -index 9ef0be3e1664..0acde4fb2020 100644 ---- a/host/xtest/include/uapi/linux/arm_ffa_user.h -+++ b/host/xtest/include/uapi/linux/arm_ffa_user.h -@@ -33,7 +33,7 @@ struct ffa_ioctl_ep_desc { - * @dst_id: [in] 16-bit ID of destination endpoint. - */ - struct ffa_ioctl_msg_args { -- __u32 args[5]; -+ __u64 args[5]; - __u16 dst_id; - }; - #define FFA_IOC_MSG_SEND _IOWR(FFA_IOC_MAGIC, FFA_IOC_BASE + 1, \ diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/Update-arm_ffa_user-driver-dependency.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/Update-arm_ffa_user-driver-dependency.patch new file mode 100644 index 0000000000..e889f74051 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/Update-arm_ffa_user-driver-dependency.patch @@ -0,0 +1,39 @@ +From 7e15470f3dd45c844f0e0901f0c85c46a0882b8b Mon Sep 17 00:00:00 2001 +From: Gabor Toth +Date: Fri, 3 Mar 2023 12:23:45 +0100 +Subject: [PATCH 1/2] Update arm_ffa_user driver dependency + +Updating arm-ffa-user to v5.0.1 to get the following changes: + - move to 64 bit direct messages + - add Linux Kernel v6.1 compatibility +The motivation is to update x-test to depend on the same driver +version as TS uefi-test and thus to enable running these in a single +configuration. +Note: arm_ffa_user.h was copied from: + - URL:https://git.gitlab.arm.com/linux-arm/linux-trusted-services.git + - SHA:18e3be71f65a405dfb5d97603ae71b3c11759861 + +Upstream-Status: Backport + +Signed-off-by: Gabor Toth +Acked-by: Jens Wiklander +--- + host/xtest/include/uapi/linux/arm_ffa_user.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/host/xtest/include/uapi/linux/arm_ffa_user.h b/host/xtest/include/uapi/linux/arm_ffa_user.h +index 9ef0be3..0acde4f 100644 +--- a/host/xtest/include/uapi/linux/arm_ffa_user.h ++++ b/host/xtest/include/uapi/linux/arm_ffa_user.h +@@ -33,7 +33,7 @@ struct ffa_ioctl_ep_desc { + * @dst_id: [in] 16-bit ID of destination endpoint. + */ + struct ffa_ioctl_msg_args { +- __u32 args[5]; ++ __u64 args[5]; + __u16 dst_id; + }; + #define FFA_IOC_MSG_SEND _IOWR(FFA_IOC_MAGIC, FFA_IOC_BASE + 1, \ +-- +2.39.1.windows.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch new file mode 100644 index 0000000000..d333e860a7 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch @@ -0,0 +1,163 @@ +From 6734d14cc249af37705129de7874533df9535cd3 Mon Sep 17 00:00:00 2001 +From: Gabor Toth +Date: Fri, 3 Mar 2023 12:25:58 +0100 +Subject: [PATCH 2/2] ffa_spmc: Add arm_ffa_user driver compatibility check + +Check the version of the arm_ffa_user Kernel Driver and fail with a +meaningful message if incompatible driver is detected. + +Upstream-Status: Backport + +Signed-off-by: Gabor Toth +Acked-by: Jens Wiklander +--- + host/xtest/ffa_spmc_1000.c | 68 ++++++++++++++++++++++++++++++++++---- + 1 file changed, 61 insertions(+), 7 deletions(-) + +diff --git a/host/xtest/ffa_spmc_1000.c b/host/xtest/ffa_spmc_1000.c +index 15f4a46..1839d03 100644 +--- a/host/xtest/ffa_spmc_1000.c ++++ b/host/xtest/ffa_spmc_1000.c +@@ -1,11 +1,12 @@ + // SPDX-License-Identifier: BSD-3-Clause + /* +- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. ++ * Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved. + */ + #include + #include + #include + #include ++#include + #include + #include + #include "include/uapi/linux/arm_ffa_user.h" +@@ -17,6 +18,10 @@ + #define INCORRECT_ENDPOINT_ID 0xffff + #define NORMAL_WORLD_ENDPOINT_ID 0 + ++#define FFA_USER_REQ_VER_MAJOR 5 ++#define FFA_USER_REQ_VER_MINOR 0 ++#define FFA_USER_REQ_VER_PATCH 1 ++ + /* Get the 32 least significant bits of a handle.*/ + #define MEM_SHARE_HANDLE_LOW(x) ((x) & 0xffffffff) + /* Get the 32 most significant bits of a handle.*/ +@@ -62,6 +67,50 @@ static struct ffa_ioctl_ep_desc test_endpoint3 = { + .uuid_ptr = (uint64_t)test_endpoint3_uuid, + }; + ++static bool check_ffa_user_version(void) ++{ ++ FILE *f = NULL; ++ int ver_major = -1; ++ int ver_minor = -1; ++ int ver_patch = -1; ++ int scan_cnt = 0; ++ ++ f = fopen("/sys/module/arm_ffa_user/version", "r"); ++ if (f) { ++ scan_cnt = fscanf(f, "%d.%d.%d", ++ &ver_major, &ver_minor, &ver_patch); ++ fclose(f); ++ if (scan_cnt != 3) { ++ printf("error: failed to parse arm_ffa_user version\n"); ++ return false; ++ } ++ } else { ++ printf("error: failed to read arm_ffa_user module info - %s\n", ++ strerror(errno)); ++ return false; ++ } ++ ++ if (ver_major != FFA_USER_REQ_VER_MAJOR) ++ goto err; ++ ++ if (ver_minor < FFA_USER_REQ_VER_MINOR) ++ goto err; ++ ++ if (ver_minor == FFA_USER_REQ_VER_MINOR) ++ if (ver_patch < FFA_USER_REQ_VER_PATCH) ++ goto err; ++ ++ return true; ++ ++err: ++ printf("error: Incompatible arm_ffa_user driver detected."); ++ printf("Found v%d.%d.%d wanted >= v%d.%d.%d)\n", ++ ver_major, ver_minor, ver_patch, FFA_USER_REQ_VER_MAJOR, ++ FFA_USER_REQ_VER_MINOR, FFA_USER_REQ_VER_PATCH); ++ ++ return false; ++} ++ + static void close_debugfs(void) + { + int err = 0; +@@ -76,6 +125,9 @@ static void close_debugfs(void) + + static bool init_sp_xtest(ADBG_Case_t *c) + { ++ if (!check_ffa_user_version()) ++ return false; ++ + if (ffa_fd < 0) { + ffa_fd = open(FFA_DRIVER_FS_PATH, O_RDWR); + if (ffa_fd < 0) { +@@ -83,6 +135,7 @@ static bool init_sp_xtest(ADBG_Case_t *c) + return false; + } + } ++ + return true; + } + +@@ -99,7 +152,7 @@ static uint16_t get_endpoint_id(uint64_t endp) + struct ffa_ioctl_ep_desc sid = { .uuid_ptr = endp }; + + /* Get ID of destination SP based on UUID */ +- if(ioctl(ffa_fd, FFA_IOC_GET_PART_ID, &sid)) ++ if (ioctl(ffa_fd, FFA_IOC_GET_PART_ID, &sid)) + return INCORRECT_ENDPOINT_ID; + + return sid.id; +@@ -213,14 +266,15 @@ static int set_up_mem(struct ffa_ioctl_ep_desc *endp, + rc = share_mem(endpoint, handle); + ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); + +- if (!ADBG_EXPECT_TRUE(c, handle != NULL)) +- return TEEC_ERROR_GENERIC; ++ if (!ADBG_EXPECT_NOT_NULL(c, handle)) ++ return TEEC_ERROR_GENERIC; + + /* SP will retrieve the memory region. */ + memset(args, 0, sizeof(*args)); + args->dst_id = endpoint; + args->args[MEM_SHARE_HANDLE_LOW_INDEX] = MEM_SHARE_HANDLE_LOW(*handle); +- args->args[MEM_SHARE_HANDLE_HIGH_INDEX] = MEM_SHARE_HANDLE_HIGH(*handle); ++ args->args[MEM_SHARE_HANDLE_HIGH_INDEX] = ++ MEM_SHARE_HANDLE_HIGH(*handle); + args->args[MEM_SHARE_HANDLE_ENDPOINT_INDEX] = NORMAL_WORLD_ENDPOINT_ID; + + rc = start_sp_test(endpoint, EP_RETRIEVE, args); +@@ -254,7 +308,7 @@ static void xtest_ffa_spmc_test_1002(ADBG_Case_t *c) + rc = start_sp_test(endpoint1_id, EP_TEST_SP, &args); + ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); + if (!ADBG_EXPECT_COMPARE_UNSIGNED(c, args.args[0], ==, SPMC_TEST_OK)) +- goto out; ++ goto out; + + /* Set up memory and have the SP retrieve it. */ + Do_ADBG_BeginSubCase(c, "Test memory set-up"); +@@ -469,7 +523,7 @@ static void xtest_ffa_spmc_test_1005(ADBG_Case_t *c) + memset(&args, 0, sizeof(args)); + args.args[1] = endpoint2; + args.args[2] = endpoint3; +- rc = start_sp_test(endpoint1, EP_SP_MEM_SHARING_MULTI,&args); ++ rc = start_sp_test(endpoint1, EP_SP_MEM_SHARING_MULTI, &args); + ADBG_EXPECT_COMPARE_SIGNED(c, rc, ==, 0); + ADBG_EXPECT_COMPARE_UNSIGNED(c, args.args[0], ==, SPMC_TEST_OK); + +-- +2.39.1.windows.1 + diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/musl-workaround.patch b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/musl-workaround.patch new file mode 100644 index 0000000000..eed1bd4be1 --- /dev/null +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test/musl-workaround.patch @@ -0,0 +1,24 @@ +Hack to work around musl compile error: + In file included from optee-test/3.17.0-r0/recipe-sysroot/usr/include/sys/stat.h:23, + from optee-test/3.17.0-r0/git/host/xtest/regression_1000.c:25: + optee-test/3.17.0-r0/recipe-sysroot/usr/include/bits/stat.h:17:26: error: expected identifier or '(' before '[' token + 17 | unsigned __unused[2]; + | ^ + +stat.h is not needed, since it is not being used in this file. So removing it. + +Upstream-Status: Pending [Not submitted to upstream yet] +Signed-off-by: Jon Mason + +diff --git a/host/xtest/regression_1000.c b/host/xtest/regression_1000.c +index 4264884..7f1baca 100644 +--- a/host/xtest/regression_1000.c ++++ b/host/xtest/regression_1000.c +@@ -22,7 +22,6 @@ + #include + #include + #include +-#include + #include + #include + #include diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bb b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bb index cf8ea01baa..436733ea09 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bb +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bb @@ -1,7 +1,7 @@ require recipes-security/optee/optee-test.inc SRC_URI += " \ - file://0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch \ + file://musl-workaround.patch \ " SRCREV = "da5282a011b40621a2cf7a296c11a35c833ed91b" diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bbappend b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bbappend index 05e2abca63..9318a07e0a 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bbappend +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.18.0.bbappend @@ -1,6 +1,7 @@ # Machine specific configurations MACHINE_OPTEE_TEST_REQUIRE ?= "" +MACHINE_OPTEE_TEST_REQUIRE:tc = "optee-test-tc.inc" MACHINE_OPTEE_TEST_REQUIRE:n1sdp = "optee-os-generic-n1sdp.inc" require ${MACHINE_OPTEE_TEST_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bb b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bb index 5f73d41405..03ea9116c5 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bb +++ b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bb @@ -1,9 +1,9 @@ require recipes-security/optee/optee-test.inc SRC_URI += " \ - file://0001-xtest-regression_1000-remove-unneeded-stat.h-include.patch \ - file://0002-ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch \ - file://0003-Update-arm_ffa_user-driver-dependency.patch \ + file://Update-arm_ffa_user-driver-dependency.patch \ + file://ffa_spmc-Add-arm_ffa_user-driver-compatibility-check.patch \ + file://musl-workaround.patch \ " SRCREV = "5db8ab4c733d5b2f4afac3e9aef0a26634c4b444" diff --git a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bbappend b/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bbappend deleted file mode 100644 index 490b350049..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/optee/optee-test_3.20.0.bbappend +++ /dev/null @@ -1,6 +0,0 @@ -# Machine specific configurations - -MACHINE_OPTEE_TEST_REQUIRE ?= "" -MACHINE_OPTEE_TEST_REQUIRE:tc = "optee-test-tc.inc" - -require ${MACHINE_OPTEE_TEST_REQUIRE} diff --git a/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/0008-plat-corstone1000-change-ns-interrupt-action.patch b/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/0008-plat-corstone1000-change-ns-interrupt-action.patch deleted file mode 100644 index c50f2866bb..0000000000 --- a/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/0008-plat-corstone1000-change-ns-interrupt-action.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 7f51fa5f848b77b5aadfc553e1aeca52f4bcc5a1 Mon Sep 17 00:00:00 2001 -From: Emekcan Aras -Date: Tue, 22 Aug 2023 17:18:26 +0100 -Subject: [PATCH] platform: corstone1000: change ns-interrupt-action - -Changes ns-interrupt-action for corstone1000. The interrupts are queued as -in the previous optee release. Currently, enabling preemption (settig this field -to 2) will halt psa-test from linux-userspace in corstone1000. - -Signed-off-by: Emekcan Aras -Upstream-Status: Pending [Not submitted to upstream yet] ---- - .../config/corstone1000-opteesp/default_se-proxy.dts.in | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/deployments/se-proxy/config/corstone1000-opteesp/default_se-proxy.dts.in b/deployments/se-proxy/config/corstone1000-opteesp/default_se-proxy.dts.in -index cc42929d..839f7464 100644 ---- a/deployments/se-proxy/config/corstone1000-opteesp/default_se-proxy.dts.in -+++ b/deployments/se-proxy/config/corstone1000-opteesp/default_se-proxy.dts.in -@@ -16,7 +16,7 @@ - execution-state = <0>; /* AArch64 */ - xlat-granule = <0>; /* 4KiB */ - messaging-method = <3>; /* Direct messaging only */ -- ns-interrupts-action = <2>; /* Non-secure interrupts are signaled */ -+ ns-interrupts-action = <0>; /* Non-secure interrupts are signaled */ - elf-format = <1>; - - device-regions { --- -2.17.1 - diff --git a/meta-arm/meta-arm-bsp/recipes-security/trusted-services/ts-arm-platforms.inc b/meta-arm/meta-arm-bsp/recipes-security/trusted-services/ts-arm-platforms.inc index 29e33ffed0..3535ddb60e 100644 --- a/meta-arm/meta-arm-bsp/recipes-security/trusted-services/ts-arm-platforms.inc +++ b/meta-arm/meta-arm-bsp/recipes-security/trusted-services/ts-arm-platforms.inc @@ -9,7 +9,6 @@ SRC_URI:append:corstone1000 = " \ file://0005-plat-corstone1000-add-compile-definitions-for-ECP_DP.patch;patchdir=../trusted-services \ file://0006-plat-corstone1000-Use-the-stateless-platform-service.patch;patchdir=../trusted-services \ file://0007-plat-corstone1000-Initialize-capsule-update-provider.patch;patchdir=../trusted-services \ - file://0008-plat-corstone1000-change-ns-interrupt-action.patch;patchdir=../trusted-services \ " diff --git a/meta-arm/meta-arm-bsp/recipes-test/corstone1000-external-sys-tests/corstone1000-external-sys-tests_1.0.bb b/meta-arm/meta-arm-bsp/recipes-test/corstone1000-external-sys-tests/corstone1000-external-sys-tests_1.0.bb index 0fa01b58b9..474342040e 100644 --- a/meta-arm/meta-arm-bsp/recipes-test/corstone1000-external-sys-tests/corstone1000-external-sys-tests_1.0.bb +++ b/meta-arm/meta-arm-bsp/recipes-test/corstone1000-external-sys-tests/corstone1000-external-sys-tests_1.0.bb @@ -6,7 +6,7 @@ LIC_FILES_CHKSUM = "file://license.md;md5=e44b2531cd6ffe9dece394dbe988d9a0" SRC_URI = "git://git.gitlab.arm.com/arm-reference-solutions/corstone1000/applications.git;protocol=https;branch=master" SRCREV = "2945cd92f7c6dbe4999ee72cd5cf1e2615eedba7" -PV .= "+git" +PV .= "+git${SRCPV}" COMPATIBLE_MACHINE = "corstone1000" diff --git a/meta-arm/meta-arm-bsp/wic/core-image-minimal.corstone500.wks b/meta-arm/meta-arm-bsp/wic/core-image-minimal.corstone500.wks new file mode 100644 index 0000000000..0ab359c40a --- /dev/null +++ b/meta-arm/meta-arm-bsp/wic/core-image-minimal.corstone500.wks @@ -0,0 +1,12 @@ +# WIC partitioning for corstone500 +# Layout and maximum sizes (to be defined): +# + +# Rawcopy of the FIP binary +part --source rawcopy --sourceparams="file=fip.bin" --no-table --align 1 --fixed-size 1 + +# Rawcopy of the kernel binary +part --source rawcopy --sourceparams="file=zImage" --no-table --fixed-size 12 + +# Rawcopy of the rootfs +part --source rawcopy --sourceparams="file=${IMGDEPLOYDIR}/core-image-minimal-corstone500.squashfs" --no-table -- cgit v1.2.3