From 10fa14942b9cb27780f9496382107516639208b4 Mon Sep 17 00:00:00 2001
From: Andrew Geissler <geissonator@yahoo.com>
Date: Fri, 11 Dec 2020 16:25:29 -0600
Subject: meta-xilinx: subtree update:569f52f275..b3e37df5d9

Mark Hatle (11):
      meta-microblaze: Move gcc patch that was missed in the prior work
      Uprev standalone toolchain bbappends
      pmu-firmware: Latest toolchain always treats 'assert' as a macro
      binutils: update to early gatesgarth version
      gdb: update to early gatesgarth version
      gcc: update to early gatesgarth version
      newlib: update to early gatesgarth version
      machine/aarch64-tc.conf: Fix incorrect ilp32 pkgarch
      libgcc.bbappend: Clear empty lib directory
      newlib: Upstream now disabled builtin symbols
      gdb: Fix on-target GDB compilation

Sai Hari Chandana Kalluri (5):
      linux-xlnx_2020.2: Fix previous git cherry-pick
      xrt: Remove stale patch to fix endian issues with latest version of boost
      opencl-clhpp, ocl-icd: Remove recipes from meta-xilinx
      esw.bbclass: Remove trailing / after S
      Remove recipe bbappends pointing to older versions

Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Change-Id: I18b028388a5b55a49ef135b98290228fa797e38d
---
 ...blaze-Add-config-microblaze.mt-for-target.patch |   10 +-
 ...-microblaze-Modified-_exceptional_handler.patch |    6 +-
 ...issing-declarations-for-xil_printf-to-std.patch |    6 +-
 ...ing-the-xil_printf.c-file-as-now-it-part-.patch |    8 +-
 ...l-deleting-the-xil_printf.o-from-MAKEFILE.patch |    6 +-
 .../newlib/files/0006-MB-X-intial-commit.patch     |   24 +-
 ...blaze-newlib-port-for-microblaze-m64-flag.patch |   66 +-
 ...bug-in-crt-files-added-addlik-instead-of-.patch |   14 +-
 ...-64-support-to-strcmp-strcpy-strlen-files.patch |  227 -
 ...Blaze-Added-MB-64-support-to-strcmp-strcp.patch |  230 +
 ...Blaze-typos-in-string-functions-microblaz.patch |   87 -
 ...e-Assembly-implementation-of-64bit-string.patch |  334 ++
 ...0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch |   25 +
 ...e-Assembly-implementation-of-64bit-string.patch |  332 --
 ...e-microblaze-strcmp.c-Fix-missing-end-of-.patch |   26 +
 .../recipes-core/newlib/microblaze-newlib.inc      |   25 +-
 .../binutils/binutils-microblaze.inc               |   92 +-
 ...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch |   65 +
 .../0001-sim-Allow-microblaze-architecture.patch   |   40 -
 ...-Add-mlittle-endian-and-mbig-endian-flags.patch |   64 +
 ...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch |   65 -
 ...-Add-mlittle-endian-and-mbig-endian-flags.patch |   64 -
 ...able-the-warning-message-for-eh_frame_hdr.patch |   31 +
 ...able-the-warning-message-for-eh_frame_hdr.patch |   31 -
 ...elaxation-of-assembler-resolved-reference.patch |  304 ++
 ...laxation-of-assembler-resolved-references.patch |   77 -
 ...ange-to-garbage-collection-sweep-causes-m.patch |   39 +
 .../0006-Fix-bug-in-TLSTPREL-Relocation.patch      |   33 +
 ...Fixup-debug_loc-sections-after-linker-rel.patch |  222 -
 ...0007-Added-Address-extension-instructions.patch |  101 +
 ...ange-to-garbage-collection-sweep-causes-m.patch |   39 -
 .../0008-Fix-bug-in-TLSTPREL-Relocation.patch      |   33 -
 ...8-fixing-the-MAX_OPCODES-to-correct-value.patch |   25 +
 .../0009-Add-new-bit-field-instructions.patch      |  237 +
 ...0009-Added-Address-extension-instructions.patch |  108 -
 .../0010-Add-new-bit-field-instructions.patch      |  231 -
 .../binutils/0010-fixing-the-imm-bug.patch         |   27 +
 ...blaze-fixed-bug-in-GCC-so-that-It-will-su.patch |   33 +
 .../binutils/0011-fixing-the-imm-bug.patch         |   27 -
 ...blaze-fixed-bug-in-GCC-so-that-It-will-su.patch |   33 -
 ...012-fixing-the-constant-range-check-issue.patch |   26 +
 ...blaze-Compiler-will-give-error-messages-i.patch |   36 +
 ...013-fixing-the-constant-range-check-issue.patch |   26 -
 ...blaze-Compiler-will-give-error-messages-i.patch |   36 -
 .../binutils/0014-intial-commit-of-MB-64-bit.patch | 4760 ++++++++++++++++++++
 .../binutils/0015-MB-X-initial-commit.patch        |  684 +++
 .../binutils/0015-intial-commit-of-MB-64-bit.patch | 4734 -------------------
 .../binutils/0016-MB-X-initial-commit.patch        |  635 ---
 ...blaze-negl-instruction-is-overriding-rsub.patch |   36 +
 .../binutils/0017-Added-relocations-for-MB-X.patch |  346 ++
 ...blaze-negl-instruction-is-overriding-rsub.patch |   37 -
 .../binutils/0018-Added-relocations-for-MB-X.patch |  300 --
 .../0018-Fixed-MB-x-relocation-issues.patch        |  373 ++
 .../0019-Fixing-the-branch-related-issues.patch    |   28 +
 .../binutils/binutils/0019-Update-MB-x.patch       |  478 --
 ...ess-computation-issues-with-64bit-address.patch |  223 +
 .../binutils/binutils/0020-Various-fixes.patch     |  221 -
 ...ng-new-relocation-to-support-64bit-rodata.patch |   36 +-
 .../0022-fixing-the-.bss-relocation-issue.patch    |   26 +-
 ...ug-in-the-R_MICROBLAZE_64_NONE-relocation.patch |   10 +-
 ...-Revert-ld-Remove-unused-expression-state.patch |    8 +-
 ...blaze-Binutils-security-check-is-causing-.patch |   33 -
 ...-the-long-long-long-mingw-toolchain-issue.patch |   57 +
 ...rt-to-new-arithmetic-single-register-inst.patch |  364 ++
 ...-the-long-long-long-mingw-toolchain-issue.patch |   57 -
 ...rt-to-new-arithmetic-single-register-inst.patch |  370 --
 ...Blaze-double-imml-generation-for-64-bit-v.patch |  551 +++
 ...in-generation-of-IMML-instruction-for-the.patch |   86 +
 ...Blaze-double-imml-generation-for-64-bit-v.patch |  552 ---
 ...in-generation-of-IMML-instruction-for-the.patch |   86 -
 ...Blaze-m64-This-patch-will-remove-imml-0-a.patch |   38 +
 ...Blaze-improper-address-mapping-of-PROVIDE.patch |   39 +
 ...Blaze-m64-Update-imml-instructions-for-Ty.patch |   47 -
 ...vert-moving-of-md_pseudo_table-from-const.patch |   83 +
 ...rkaround-for-improper-address-mapping-cau.patch |   38 -
 ...vert-moving-of-md_pseudo_table-from-const.patch |   83 -
 ...ms-elf64microblaze-Fix-emulation-generati.patch |   43 +
 ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch |  435 ++
 .../0033-Fix-various-compile-warnings.patch        |  105 -
 .../0034-Add-initial-port-of-linux-gdbserver.patch |  500 --
 ...t-of-core-reading-support-Added-support-f.patch |  388 ++
 ...ebug-message-when-register-is-unavailable.patch |   40 +
 ...0035-Initial-port-of-core-reading-support.patch |  298 --
 ...ebug-message-when-register-is-unavailable.patch |   40 -
 ...revert-master-rebase-changes-to-gdbserver.patch |   31 +
 ...Add-build_gdbserver-yes-to-top-level-conf.patch |   32 -
 ...er-rebase-changes-to-gdbserver-previous-c.patch |   36 +
 .../0038-Initial-support-for-native-gdb.patch      |  492 --
 ...Add-build_gdbserver-yes-to-top-level-conf.patch |   32 +
 ...039-Fixing-the-issues-related-to-GDB-7.12.patch |  216 -
 .../0039-Initial-support-for-native-gdb.patch      |  495 ++
 ...issues-related-to-GDB-7.12-added-all-the-.patch |  309 ++
 ...Patch-microblaze-Adding-64-bit-MB-support.patch |  998 ----
 ...it-MB-support-Added-new-architecture-to-M.patch | 1008 +++++
 .../binutils/0042-porting-GDB-for-linux.patch      |  155 +
 ...curity-check-is-causing-build-error-for-w.patch |   41 +
 ...the-register-names-from-slr-shr-to-rslr-r.patch |  146 +
 ...e-header-gdb_assert.h-from-MB-target-file.patch |   24 +
 ...bfd-cpu-microblaze.c-Enhance-disassembler.patch |   39 +
 ...bfd-elf64-microblaze.c-Fix-build-failures.patch |   87 +
 ...-elf-microblaze.c-Remove-obsolete-entries.patch |   75 +
 ...icroblaze.c-Resolve-various-compiler-warn.patch |   45 +
 ...des-microblaze-dis.c-Fix-compile-warnings.patch |   37 +
 ...microblaze-tdep.c-Remove-unused-functions.patch |   99 +
 .../0052-sim-Allow-microblaze-architecture.patch   |   40 +
 ...053-gdb-Fix-microblaze-target-compilation.patch |  288 ++
 ...CAL-Testsuite-builtins-tests-require-fpic.patch |   20 +-
 ...0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch |   11 +-
 ...ejagnu-static-testing-on-qemu-suppress-wa.patch |   35 +
 ...uite-explicitly-add-fivopts-for-tests-tha.patch |  117 -
 ...ejagnu-static-testing-on-qemu-suppress-wa.patch |   30 -
 ...uite-Add-MicroBlaze-to-target-supports-fo.patch |   35 +
 ...uite-Add-MicroBlaze-to-target-supports-fo.patch |   35 -
 ...-testsuite-Update-MicroBlaze-strings-test.patch |   43 +
 ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch |   67 +
 ...-testsuite-Update-MicroBlaze-strings-test.patch |   44 -
 ...uite-Add-MicroBlaze-to-check_profiling_av.patch |   28 +
 ...uite-Allow-MicroBlaze-.weakext-pattern-in.patch |   69 -
 ...-Patch-microblaze-Fix-atomic-side-effects.patch |   68 +
 ...uite-Add-MicroBlaze-to-check_profiling_av.patch |   29 -
 ...icroblaze-Fix-atomic-boolean-return-value.patch |   40 +
 ...-Patch-microblaze-Fix-atomic-side-effects.patch |   69 -
 ...icroblaze-Fix-atomic-boolean-return-value.patch |   42 -
 ...blaze-Fix-the-Microblaze-crash-with-msmal.patch |   33 +
 ...ch-microblaze-Added-ashrsi3_with_size_opt.patch |   48 +
 ...blaze-Fix-the-Microblaze-crash-with-msmal.patch |   34 -
 ...ch-microblaze-Added-ashrsi3_with_size_opt.patch |   49 -
 ...-microblaze-Use-bralid-for-profiler-calls.patch |   26 +
 ...-Patch-microblaze-Removed-moddi3-routinue.patch |  157 +
 ...-microblaze-Use-bralid-for-profiler-calls.patch |   26 -
 ...atch-microblaze-Add-INIT_PRIORITY-support.patch |  101 +
 ...tch-microblaze-Disable-fivopts-by-default.patch |   43 -
 ...15-Patch-microblaze-Add-optimized-lshrsi3.patch |   81 +
 ...-Patch-microblaze-Removed-moddi3-routinue.patch |  161 -
 ...atch-microblaze-Add-INIT_PRIORITY-support.patch |  102 -
 .../0016-Patch-microblaze-Add-cbranchsi4_reg.patch |  147 +
 ...17-Patch-microblaze-Add-optimized-lshrsi3.patch |   83 -
 ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch |   58 +
 ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch |   63 +
 ...oblaze-Reducing-Stack-space-for-arguments.patch |  205 -
 .../0019-Patch-microblaze-Add-cbranchsi4_reg.patch |  148 -
 ...-microblaze-Update-ashlsi3-movsf-patterns.patch |   72 +
 ...icroblaze-8-stage-pipeline-for-microblaze.patch |  178 +
 ...roblaze-Inline-Expansion-of-fsqrt-builtin.patch |   61 -
 ...pdate-heuristics-for-loop-invariant-for-a.patch |   47 -
 ...blaze-Correct-the-const-high-double-immed.patch |   58 +
 ...aze-Fix-internal-compiler-error-with-msma.patch |   36 +
 ...blaze.md-Improve-adddi3-and-subdi3-insn-d.patch |   66 -
 ...-microblaze-Update-ashlsi3-movsf-patterns.patch |   60 -
 ...blaze-Fix-the-calculation-of-high-word-in.patch |   45 +
 ...icroblaze-8-stage-pipeline-for-microblaze.patch |  213 -
 ...microblaze-Add-new-bit-field-instructions.patch |  162 +
 ...roblaze-Fix-bug-in-MB-version-calculation.patch |  247 +
 ...ptimization-Better-register-pressure-esti.patch |  142 -
 ...6-Fixing-the-issue-with-the-builtin_alloc.patch |   44 +
 ...blaze-Correct-the-const-high-double-immed.patch |   69 -
 ...aze-Fix-internal-compiler-error-with-msma.patch |   37 -
 ...blaze-update-in-constraints-for-bitfield-.patch |   84 +
 ...blaze-Removed-fsqrt-generation-for-double.patch |   38 +
 ...blaze-Fix-the-calculation-of-high-word-in.patch |   45 -
 ...oBlaze-Intial-commit-of-64-bit-Microblaze.patch |  845 ++++
 ...microblaze-Add-new-bit-field-instructions.patch |  143 -
 .../0030-Intial-commit-for-64bit-MB-sources.patch  | 2459 ++++++++++
 ...roblaze-Fix-bug-in-MB-version-calculation.patch |  241 -
 ...1-Fixing-the-issue-with-the-builtin_alloc.patch |   45 -
 ...31-re-arrangement-of-the-compare-branches.patch |  268 ++
 ...blaze-previous-commit-broke-the-handling-.patch |   28 +
 ...blaze-update-in-constraints-for-bitfield-.patch |   80 -
 ...blaze-Removed-fsqrt-generation-for-double.patch |   38 -
 ...-Microblaze-Support-of-multilibs-with-m64.patch |   73 +
 .../gcc/gcc-10/0034-Fixed-issues-like.patch        |   70 +
 .../0034-Intial-commit-of-64-bit-Microblaze.patch  |  844 ----
 .../gcc/gcc-10/0035-Fixed-below-issues.patch       |  307 ++
 .../0035-Intial-commit-for-64bit-MB-sources.patch  | 2463 ----------
 .../0036-Added-double-arith-instructions.patch     |  135 +
 ...36-re-arrangement-of-the-compare-branches.patch |  268 --
 ...ssue-in-the-delay-slot-with-swap-instruct.patch |   37 +
 ...blaze-previous-commit-broke-the-handling-.patch |   28 -
 ...oad-store-issue-with-the-32bit-arith-libr.patch |  256 ++
 ...-Microblaze-Support-of-multilibs-with-m64.patch |   73 -
 .../gcc/gcc-10/0039-Fix-various-issues.patch       |   72 -
 ...ing-the-Dwarf-support-to-64bit-Microblaze.patch |   25 +
 .../gcc/gcc-10/0040-Fixed-below-issues.patch       |  304 --
 ...40-fixing-the-typo-errors-in-umodsi3-file.patch |   29 +
 .../gcc/gcc-10/0041-Fix-various.patch              |  136 -
 ...xing-the-32bit-LTO-related-issue9-1014024.patch |   68 +
 ...ssue-in-the-delay-slot-with-swap-instruct.patch |   37 -
 ...issing-stack-adjustment-in-prologue-of-mo.patch |   25 +
 ...oad-store-issue-with-the-32bit-arith-libr.patch |  256 --
 ...blaze-corrected-SPN-for-dlong-instruction.patch |   29 +
 ...ing-the-Dwarf-support-to-64bit-Microblaze.patch |   25 -
 ...-the-long-long-long-mingw-toolchain-issue.patch |   59 +
 ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch |   47 +
 ...45-fixing-the-typo-errors-in-umodsi3-file.patch |   29 -
 ...blaze-We-will-check-the-possibility-of-pe.patch |   87 +
 ...xing-the-32bit-LTO-related-issue9-1014024.patch |   68 -
 ...issing-stack-adjustment-in-prologue-of-mo.patch |   25 -
 ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch |  466 ++
 .../0048-Author-Nagaraju-nmekala-xilinx.com.patch  |  479 ++
 ...blaze-corrected-SPN-for-dlong-instruction.patch |   29 -
 ...B-64-single-register-arithmetic-instructi.patch |  107 +
 ...-the-long-long-long-mingw-toolchain-issue.patch |   59 -
 ...-Fix-the-MB-64-bug-of-handling-QI-objects.patch |   47 -
 ...Blaze-Added-support-for-64-bit-Immediate-.patch |   44 +
 ...blaze-Check-the-possibiity-of-peephole2-o.patch |   89 -
 ...blaze-Fix-Compiler-crash-with-freg-struct.patch |   86 +
 ...Blaze-fixed-typos-in-mul-div-and-mod-asse.patch |  466 --
 ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch |   45 +
 ...blaze-MB-64-removal-of-barrel-shift-instr.patch |  478 --
 ...oblaze-Reducing-Stack-space-for-arguments.patch |  198 +
 ...blaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch |   41 -
 ...B-64-single-register-arithmetic-instructi.patch |  107 -
 ...Blaze-Added-support-for-64-bit-Immediate-.patch |   44 -
 ...blaze-Fix-Compiler-crash-with-freg-struct.patch |   86 -
 ...aze-Avoid-UINTPTR_TYPE-macro-redefinition.patch |   29 -
 .../gcc/gcc-10/microblaze-mulitlib-hack.patch      |   58 +
 .../recipes-devtools/gcc/gcc-source_10.%.bbappend  |  108 +-
 .../recipes-devtools/gdb/gdb-microblaze.inc        |   83 +-
 ...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch |   65 +
 .../0001-sim-Allow-microblaze-architecture.patch   |   40 -
 ...Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch |   65 -
 ...able-the-warning-message-for-eh_frame_hdr.patch |   28 +
 ...able-the-warning-message-for-eh_frame_hdr.patch |   31 -
 ...elaxation-of-assembler-resolved-reference.patch |  261 ++
 ...laxation-of-assembler-resolved-references.patch |   64 -
 ...ange-to-garbage-collection-sweep-causes-m.patch |   36 +
 .../gdb/0006-Fix-bug-in-TLSTPREL-Relocation.patch  |   30 +
 ...Fixup-debug_loc-sections-after-linker-rel.patch |  184 -
 ...0007-Added-Address-extension-instructions.patch |   97 +
 ...ange-to-garbage-collection-sweep-causes-m.patch |   39 -
 .../gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch  |   33 -
 ...8-fixing-the-MAX_OPCODES-to-correct-value.patch |   22 +
 .../gdb/0009-Add-new-bit-field-instructions.patch  |  144 +
 ...0009-Added-Address-extension-instructions.patch |  124 -
 .../gdb/0010-Add-new-bit-field-instructions.patch  |  140 -
 .../gdb/gdb/0010-fixing-the-imm-bug.patch          |   24 +
 .../gdb/gdb/0011-fixing-the-imm-bug.patch          |   27 -
 .../gdb/gdb/0014-intial-commit-of-MB-64-bit.patch  | 4277 ++++++++++++++++++
 .../gdb/gdb/0015-MB-X-initial-commit.patch         |  359 ++
 .../gdb/gdb/0015-intial-commit-of-MB-64-bit.patch  | 4189 -----------------
 .../gdb/gdb/0016-MB-X-initial-commit.patch         |  337 --
 ...blaze-negl-instruction-is-overriding-rsub.patch |   33 +
 .../gdb/gdb/0017-Added-relocations-for-MB-X.patch  |  113 +
 ...blaze-negl-instruction-is-overriding-rsub.patch |   37 -
 .../gdb/gdb/0018-Added-relocations-for-MB-X.patch  |  113 -
 .../gdb/0018-Fixed-MB-x-relocation-issues.patch    |  114 +
 .../0019-Fixing-the-branch-related-issues.patch    |   25 +
 .../gdb/gdb/0019-Update-MB-x.patch                 |  116 -
 ...ess-computation-issues-with-64bit-address.patch |   98 +
 .../gdb/gdb/0020-Various-fixes.patch               |   98 -
 ...ng-new-relocation-to-support-64bit-rodata.patch |   30 +-
 .../0022-fixing-the-.bss-relocation-issue.patch    |   35 +-
 ...ug-in-the-R_MICROBLAZE_64_NONE-relocation.patch |   25 +-
 ...blaze-Binutils-security-check-is-causing-.patch |   34 -
 ...-the-long-long-long-mingw-toolchain-issue.patch |   25 +
 ...rt-to-new-arithmetic-single-register-inst.patch |  169 +
 ...-the-long-long-long-mingw-toolchain-issue.patch |   27 -
 ...rt-to-new-arithmetic-single-register-inst.patch |  181 -
 ...Blaze-double-imml-generation-for-64-bit-v.patch |   26 +
 ...Blaze-double-imml-generation-for-64-bit-v.patch |   28 -
 ...ms-elf64microblaze-Fix-emulation-generati.patch |   40 +
 ...-port-of-linux-gdbserver-add-gdb_proc_ser.patch |  429 ++
 .../gdb/0033-Fix-various-compile-warnings.patch    |   60 -
 .../0034-Add-initial-port-of-linux-gdbserver.patch |  500 --
 ...t-of-core-reading-support-Added-support-f.patch |  385 ++
 ...ebug-message-when-register-is-unavailable.patch |   37 +
 ...0035-Initial-port-of-core-reading-support.patch |  298 --
 ...ebug-message-when-register-is-unavailable.patch |   40 -
 ...revert-master-rebase-changes-to-gdbserver.patch |   28 +
 ...Add-build_gdbserver-yes-to-top-level-conf.patch |   32 -
 ...er-rebase-changes-to-gdbserver-previous-c.patch |   30 +
 .../gdb/0038-Initial-support-for-native-gdb.patch  |  492 --
 ...Add-build_gdbserver-yes-to-top-level-conf.patch |   29 +
 ...039-Fixing-the-issues-related-to-GDB-7.12.patch |  216 -
 .../gdb/0039-Initial-support-for-native-gdb.patch  |  490 ++
 ...issues-related-to-GDB-7.12-added-all-the-.patch |  306 ++
 ...Patch-microblaze-Adding-64-bit-MB-support.patch |  949 ----
 ...it-MB-support-Added-new-architecture-to-M.patch |  953 ++++
 .../gdb/gdb/0042-porting-GDB-for-linux.patch       |  151 +
 ...curity-check-is-causing-build-error-for-w.patch |   32 +
 ...the-register-names-from-slr-shr-to-rslr-r.patch |  143 +
 ...e-header-gdb_assert.h-from-MB-target-file.patch |   21 +
 ...bfd-cpu-microblaze.c-Enhance-disassembler.patch |   36 +
 ...bfd-elf64-microblaze.c-Fix-build-failures.patch |   84 +
 ...-elf-microblaze.c-Remove-obsolete-entries.patch |   72 +
 ...icroblaze.c-Resolve-various-compiler-warn.patch |   42 +
 ...des-microblaze-dis.c-Fix-compile-warnings.patch |   34 +
 ...microblaze-tdep.c-Remove-unused-functions.patch |   96 +
 .../0052-sim-Allow-microblaze-architecture.patch   |   37 +
 ...053-gdb-Fix-microblaze-target-compilation.patch |  288 ++
 .../meta-xilinx-bsp/conf/machine/aarch64-tc.conf   |    2 +-
 .../recipes-kernel/linux/linux-xlnx_2020.2.bb      |    9 +
 .../gcc/gcc-9/0065-microblaze-multilib-hack.patch  |   58 -
 .../recipes-xrt/ocl-icd/ocl-icd_git.bb             |   19 -
 .../recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb   |   29 -
 ...st-detail-endian.hpp-with-boost-predef-ot.patch |   80 -
 .../meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb     |    2 -
 .../meta-xilinx-standalone/classes/esw.bbclass     |    4 +-
 .../recipes-core/newlib/libgloss_3.%.bbappend      |   12 +
 .../recipes-core/newlib/libgloss_3.1.0.bbappend    |   13 -
 .../recipes-core/newlib/newlib_3.%.bbappend        |   20 +
 .../recipes-core/newlib/newlib_3.1.0.bbappend      |   21 -
 .../gcc-10/additional-microblaze-multilibs.patch   |   86 +
 .../gcc-9/additional-microblaze-multilibs.patch    |   86 -
 .../recipes-devtools/gcc/gcc-source_10.%.bbappend  |    7 +
 .../recipes-devtools/gcc/gcc-source_9.%.bbappend   |    7 -
 .../recipes-devtools/gcc/libgcc_%.bbappend         |    3 +
 .../pmu-firmware/fix-zynqmp-assert.patch           |   68 +
 .../pmu-firmware/pmu-firmware_2020.2.bb            |    3 +-
 309 files changed, 31781 insertions(+), 29827 deletions(-)
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Added-MB-64-support-to-strcmp-strcpy-strlen-files.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Patch-MicroBlaze-Added-MB-64-support-to-strcmp-strcp.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Patch-MicroBlaze-typos-in-string-functions-microblaz.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Removing-the-Assembly-implementation-of-64bit-string.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Removing-the-Assembly-implementation-of-64bit-string.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-core/newlib/files/0012-libc-machine-microblaze-strcmp.c-Fix-missing-end-of-.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-sim-Allow-microblaze-architecture.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Add-mlittle-endian-and-mbig-endian-flags.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-Fix-relaxation-of-assembler-resolved-references.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-Fix-bug-in-TLSTPREL-Relocation.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-Added-Address-extension-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-Fix-bug-in-TLSTPREL-Relocation.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Add-new-bit-field-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Added-Address-extension-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-Add-new-bit-field-instructions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-fixing-the-imm-bug.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-fixing-the-imm-bug.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-fixing-the-constant-range-check-issue.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-intial-commit-of-MB-64-bit.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-MB-X-initial-commit.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-MB-X-initial-commit.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Added-relocations-for-MB-X.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Added-relocations-for-MB-X.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Fixed-MB-x-relocation-issues.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Fixing-the-branch-related-issues.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Update-MB-x.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Fixed-address-computation-issues-with-64bit-address.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Various-fixes.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-Added-support-to-new-arithmetic-single-register-inst.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Added-support-to-new-arithmetic-single-register-inst.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-improper-address-mapping-of-PROVIDE.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-m64-Update-imml-instructions-for-Ty.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-gas-revert-moving-of-md_pseudo_table-from-const.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-ldlang.c-Workaround-for-improper-address-mapping-cau.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-gas-revert-moving-of-md_pseudo_table-from-const.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Fix-various-compile-warnings.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Add-initial-port-of-linux-gdbserver.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Initial-port-of-core-reading-support-Added-support-f.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Fix-debug-message-when-register-is-unavailable.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Initial-port-of-core-reading-support.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-Fix-debug-message-when-register-is-unavailable.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-Initial-support-for-native-gdb.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-support-for-native-gdb.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0042-porting-GDB-for-linux.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0043-Binutils-security-check-is-causing-build-error-for-w.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0052-sim-Allow-microblaze-architecture.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0053-gdb-Fix-microblaze-target-compilation.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fix-bug-in-TLSTPREL-Relocation.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-Added-Address-extension-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Add-new-bit-field-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-fixing-the-imm-bug.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0014-intial-commit-of-MB-64-bit.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-MB-X-initial-commit.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Added-relocations-for-MB-X.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Fixed-MB-x-relocation-issues.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Fixing-the-branch-related-issues.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Fixed-address-computation-issues-with-64bit-address.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-Added-support-to-new-arithmetic-single-register-inst.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Initial-port-of-core-reading-support-Added-support-f.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Fix-debug-message-when-register-is-unavailable.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-revert-master-rebase-changes-to-gdbserver.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-support-for-native-gdb.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
 delete mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0042-porting-GDB-for-linux.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0043-Binutils-security-check-is-causing-build-error-for-w.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0052-sim-Allow-microblaze-architecture.patch
 create mode 100644 meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0053-gdb-Fix-microblaze-target-compilation.patch
 delete mode 100644 meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0065-microblaze-multilib-hack.patch
 delete mode 100644 meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb
 delete mode 100644 meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb
 delete mode 100644 meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt/0001-Replace-boost-detail-endian.hpp-with-boost-predef-ot.patch
 create mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.%.bbappend
 delete mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.1.0.bbappend
 create mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.%.bbappend
 delete mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.1.0.bbappend
 create mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-10/additional-microblaze-multilibs.patch
 delete mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-9/additional-microblaze-multilibs.patch
 create mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_10.%.bbappend
 delete mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_9.%.bbappend
 create mode 100644 meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware/fix-zynqmp-assert.patch

(limited to 'meta-xilinx')

diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch
index 950e0b30dd..0d984e4bbc 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch
@@ -1,4 +1,4 @@
-From 4926aec8897dc574d442e5a87b2576ab80046b10 Mon Sep 17 00:00:00 2001
+From 3be7340059deb6fd74873978ee4e435c84a15b8b Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 23 Jan 2017 15:27:25 +0530
 Subject: [PATCH 01/11] [Patch, microblaze]: Add config/microblaze.mt for
@@ -26,7 +26,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 
 diff --git a/libgloss/config/microblaze.mt b/libgloss/config/microblaze.mt
 new file mode 100644
-index 0000000..e8fb922
+index 000000000..e8fb922dd
 --- /dev/null
 +++ b/libgloss/config/microblaze.mt
 @@ -0,0 +1,30 @@
@@ -61,7 +61,7 @@ index 0000000..e8fb922
 +write.o: ${srcdir}/../write.c
 +	$(CC) $(CFLAGS_FOR_TARGET) -O2 $(INCLUDES) -c $(CFLAGS) $?
 diff --git a/libgloss/microblaze/configure b/libgloss/microblaze/configure
-index 9b2bc7a..01f0fb2 100644
+index 9b2bc7ab4..01f0fb29d 100644
 --- a/libgloss/microblaze/configure
 +++ b/libgloss/microblaze/configure
 @@ -2020,7 +2020,7 @@ LIB_AM_PROG_AS
@@ -74,7 +74,7 @@ index 9b2bc7a..01f0fb2 100644
  host_makefile_frag_path=$host_makefile_frag
  
 diff --git a/libgloss/microblaze/configure.in b/libgloss/microblaze/configure.in
-index 77aa769..5d179fd 100644
+index 77aa769d4..5d179fdfc 100644
 --- a/libgloss/microblaze/configure.in
 +++ b/libgloss/microblaze/configure.in
 @@ -35,7 +35,7 @@ LIB_AM_PROG_AS
@@ -87,5 +87,5 @@ index 77aa769..5d179fd 100644
  dnl We have to assign the same value to other variables because autoconf
  dnl doesn't provide a mechanism to substitute a replacement keyword with
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0002-Patch-microblaze-Modified-_exceptional_handler.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0002-Patch-microblaze-Modified-_exceptional_handler.patch
index 51785d9a09..27f8a60bd5 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0002-Patch-microblaze-Modified-_exceptional_handler.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0002-Patch-microblaze-Modified-_exceptional_handler.patch
@@ -1,4 +1,4 @@
-From ee559eb522edcb793e4df62f61849748445a056e Mon Sep 17 00:00:00 2001
+From f3ffd847282fa3bf676ccd05cbdcba33eea06416 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 23 Jan 2017 15:30:02 +0530
 Subject: [PATCH 02/11] [Patch, microblaze]: Modified _exceptional_handler
@@ -11,7 +11,7 @@ Signed-off-by:Nagaraju Mekala<nmekala@xilix.com>
  1 file changed, 1 deletion(-)
 
 diff --git a/libgloss/microblaze/_exception_handler.S b/libgloss/microblaze/_exception_handler.S
-index 59385ad..7a91a78 100644
+index 59385ad9b..7a91a781e 100644
 --- a/libgloss/microblaze/_exception_handler.S
 +++ b/libgloss/microblaze/_exception_handler.S
 @@ -36,5 +36,4 @@
@@ -21,5 +21,5 @@ index 59385ad..7a91a78 100644
 -	addi r11,r11,8
  	bra r11
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch
index 21c5580093..aa257a40f4 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch
@@ -1,4 +1,4 @@
-From 829dcc7967bd2a99b583fba1129ae71dbe8335ff Mon Sep 17 00:00:00 2001
+From cf8c0c5d167386aa3f8bee6feb531b451461f99c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 23 Jan 2017 15:39:45 +0530
 Subject: [PATCH 03/11] [LOCAL]: Add missing declarations for xil_printf to
@@ -10,7 +10,7 @@ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
  1 file changed, 3 insertions(+)
 
 diff --git a/newlib/libc/include/stdio.h b/newlib/libc/include/stdio.h
-index 164d95b..7bb729c 100644
+index 164d95bca..7bb729c11 100644
 --- a/newlib/libc/include/stdio.h
 +++ b/newlib/libc/include/stdio.h
 @@ -245,6 +245,9 @@ int	sprintf (char *__restrict, const char *__restrict, ...)
@@ -24,5 +24,5 @@ index 164d95b..7bb729c 100644
  int	_rename (const char *, const char *);
  #endif
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch
index f56f618765..9c59e4f552 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch
@@ -1,17 +1,17 @@
-From 379f231f0afb5e10cd82bc6346e4a6776df3e21e Mon Sep 17 00:00:00 2001
+From b2e081bd0c00dce23a6824db050bbfca991d79ab Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 23 Jan 2017 15:42:11 +0530
 Subject: [PATCH 04/11] [Local]: deleting the xil_printf.c file as now it part
  of BSP
 
 ---
- libgloss/microblaze/xil_printf.c | 284 ---------------------------------------
+ libgloss/microblaze/xil_printf.c | 284 -------------------------------
  1 file changed, 284 deletions(-)
  delete mode 100644 libgloss/microblaze/xil_printf.c
 
 diff --git a/libgloss/microblaze/xil_printf.c b/libgloss/microblaze/xil_printf.c
 deleted file mode 100644
-index f18ee84..0000000
+index f18ee8446..000000000
 --- a/libgloss/microblaze/xil_printf.c
 +++ /dev/null
 @@ -1,284 +0,0 @@
@@ -300,5 +300,5 @@ index f18ee84..0000000
 -
 -/*---------------------------------------------------*/
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch
index 6e32e1775a..850a614259 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch
@@ -1,4 +1,4 @@
-From 96e6a596356fa605bbe00f7f69afb52f80329eb6 Mon Sep 17 00:00:00 2001
+From 5071ea41bb6a54b8205665d307876ab0130d8825 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Mon, 23 Jan 2017 15:44:17 +0530
 Subject: [PATCH 05/11] [Local]: deleting the xil_printf.o from MAKEFILE
@@ -8,7 +8,7 @@ Subject: [PATCH 05/11] [Local]: deleting the xil_printf.o from MAKEFILE
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/libgloss/microblaze/Makefile.in b/libgloss/microblaze/Makefile.in
-index fe04a08..32aafda 100644
+index fe04a08c9..32aafda37 100644
 --- a/libgloss/microblaze/Makefile.in
 +++ b/libgloss/microblaze/Makefile.in
 @@ -81,7 +81,7 @@ GENOBJS = fstat.o getpid.o isatty.o kill.o lseek.o print.o putnum.o stat.o unlin
@@ -21,5 +21,5 @@ index fe04a08..32aafda 100644
  
  # Tiny Linux BSP.
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0006-MB-X-intial-commit.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0006-MB-X-intial-commit.patch
index 18b78f0908..a3c1f0e084 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0006-MB-X-intial-commit.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0006-MB-X-intial-commit.patch
@@ -1,4 +1,4 @@
-From bb9e95aa1da6c1f8974702685db9b8486210ac5c Mon Sep 17 00:00:00 2001
+From f5f363cd879ea60cc8fb5507e8a01533fd0c55a9 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 27 Jul 2018 16:10:36 +0530
 Subject: [PATCH 06/11] MB-X intial commit
@@ -17,7 +17,7 @@ Subject: [PATCH 06/11] MB-X intial commit
  10 files changed, 17 insertions(+), 17 deletions(-)
 
 diff --git a/libgloss/microblaze/crt0.S b/libgloss/microblaze/crt0.S
-index b39ea90..865a8c2 100644
+index b39ea90b3..865a8c269 100644
 --- a/libgloss/microblaze/crt0.S
 +++ b/libgloss/microblaze/crt0.S
 @@ -84,7 +84,7 @@ _vector_hw_exception:
@@ -30,7 +30,7 @@ index b39ea90..865a8c2 100644
  	brlid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crt1.S b/libgloss/microblaze/crt1.S
-index 20323ff..a8bf749 100644
+index 20323ff6d..a8bf74937 100644
 --- a/libgloss/microblaze/crt1.S
 +++ b/libgloss/microblaze/crt1.S
 @@ -75,7 +75,7 @@ _vector_hw_exception:
@@ -43,7 +43,7 @@ index 20323ff..a8bf749 100644
  	brlid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crt2.S b/libgloss/microblaze/crt2.S
-index e3fb15b..34d9f95 100644
+index e3fb15b26..34d9f951d 100644
 --- a/libgloss/microblaze/crt2.S
 +++ b/libgloss/microblaze/crt2.S
 @@ -73,7 +73,7 @@ _vector_hw_exception:
@@ -56,7 +56,7 @@ index e3fb15b..34d9f95 100644
  	brlid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crt3.S b/libgloss/microblaze/crt3.S
-index 452ea52..ebcf207 100644
+index 452ea5265..ebcf207f5 100644
 --- a/libgloss/microblaze/crt3.S
 +++ b/libgloss/microblaze/crt3.S
 @@ -59,7 +59,7 @@
@@ -69,7 +69,7 @@ index 452ea52..ebcf207 100644
  	brlid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crt4.S b/libgloss/microblaze/crt4.S
-index 475acec..4cf0b01 100644
+index 475acecfd..4cf0b01a4 100644
 --- a/libgloss/microblaze/crt4.S
 +++ b/libgloss/microblaze/crt4.S
 @@ -59,7 +59,7 @@
@@ -82,7 +82,7 @@ index 475acec..4cf0b01 100644
  	brlid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crtinit.S b/libgloss/microblaze/crtinit.S
-index 78eb76d..86c6dfc 100644
+index 78eb76df6..86c6dfcb0 100644
 --- a/libgloss/microblaze/crtinit.S
 +++ b/libgloss/microblaze/crtinit.S
 @@ -33,7 +33,7 @@
@@ -103,7 +103,7 @@ index 78eb76d..86c6dfc 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/pgcrtinit.S b/libgloss/microblaze/pgcrtinit.S
-index fca1bc4..2593082 100644
+index fca1bc45e..25930821c 100644
 --- a/libgloss/microblaze/pgcrtinit.S
 +++ b/libgloss/microblaze/pgcrtinit.S
 @@ -33,7 +33,7 @@
@@ -124,7 +124,7 @@ index fca1bc4..2593082 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/sim-crtinit.S b/libgloss/microblaze/sim-crtinit.S
-index d2f59fe..74586d9 100644
+index d2f59fe6d..74586d9a7 100644
 --- a/libgloss/microblaze/sim-crtinit.S
 +++ b/libgloss/microblaze/sim-crtinit.S
 @@ -39,7 +39,7 @@
@@ -145,7 +145,7 @@ index d2f59fe..74586d9 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/sim-pgcrtinit.S b/libgloss/microblaze/sim-pgcrtinit.S
-index 3c6ba83..82ebcca 100644
+index 3c6ba8371..82ebccad4 100644
 --- a/libgloss/microblaze/sim-pgcrtinit.S
 +++ b/libgloss/microblaze/sim-pgcrtinit.S
 @@ -39,7 +39,7 @@
@@ -166,7 +166,7 @@ index 3c6ba83..82ebcca 100644
  	.end _crtinit
  
 diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
-index 434195e..3119d82 100644
+index 434195e2c..3119d82c5 100644
 --- a/newlib/libc/machine/microblaze/strcmp.c
 +++ b/newlib/libc/machine/microblaze/strcmp.c
 @@ -96,15 +96,15 @@ strcmp (const char *s1,
@@ -190,5 +190,5 @@ index 434195e..3119d82 100644
          {
            /* To get here, *a1 == *a2, thus if we find a null in *a1,
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch
index c62a9919ad..55dde80339 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch
@@ -1,4 +1,4 @@
-From eab8d664224d134b2c4d638d9c6bebb84ae777ad Mon Sep 17 00:00:00 2001
+From 5040f7d8abb79bf4240d0b446e2d33d26680d9fc Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Tue, 11 Sep 2018 14:32:20 +0530
 Subject: [PATCH 07/11] [Patch, Microblaze]: newlib port for microblaze m64
@@ -13,23 +13,23 @@ Conflicts:
  libgloss/microblaze/_interrupt_handler.S    |   7 +-
  libgloss/microblaze/_program_clean.S        |   6 +-
  libgloss/microblaze/_program_init.S         |   6 +-
- libgloss/microblaze/crt0.S                  |  53 ++++++++++--
- libgloss/microblaze/crt1.S                  |  54 +++++++++++--
- libgloss/microblaze/crt2.S                  |  52 ++++++++++--
- libgloss/microblaze/crt3.S                  |  32 +++++++-
- libgloss/microblaze/crt4.S                  |  37 +++++++--
- libgloss/microblaze/crtinit.S               | 120 ++++++++++++++++++++--------
- libgloss/microblaze/linux-crt0.S            |  60 +++++++++++---
- libgloss/microblaze/linux-syscalls.S        |  15 +++-
- libgloss/microblaze/pgcrtinit.S             |  59 +++++++++++++-
- libgloss/microblaze/sim-crtinit.S           |  31 +++++++
- libgloss/microblaze/sim-pgcrtinit.S         |  31 +++++++
- newlib/libc/machine/microblaze/longjmp.S    |  45 +++++++++--
- newlib/libc/machine/microblaze/setjmp.S     |  33 +++++++-
+ libgloss/microblaze/crt0.S                  |  53 ++++++++-
+ libgloss/microblaze/crt1.S                  |  54 +++++++--
+ libgloss/microblaze/crt2.S                  |  52 +++++++--
+ libgloss/microblaze/crt3.S                  |  32 +++++-
+ libgloss/microblaze/crt4.S                  |  37 +++++-
+ libgloss/microblaze/crtinit.S               | 120 ++++++++++++++------
+ libgloss/microblaze/linux-crt0.S            |  60 ++++++++--
+ libgloss/microblaze/linux-syscalls.S        |  15 ++-
+ libgloss/microblaze/pgcrtinit.S             |  59 +++++++++-
+ libgloss/microblaze/sim-crtinit.S           |  31 +++++
+ libgloss/microblaze/sim-pgcrtinit.S         |  31 +++++
+ newlib/libc/machine/microblaze/longjmp.S    |  45 ++++++--
+ newlib/libc/machine/microblaze/setjmp.S     |  33 +++++-
  18 files changed, 563 insertions(+), 91 deletions(-)
 
 diff --git a/libgloss/microblaze/_exception_handler.S b/libgloss/microblaze/_exception_handler.S
-index 7a91a78..0fdff3f 100644
+index 7a91a781e..0fdff3fec 100644
 --- a/libgloss/microblaze/_exception_handler.S
 +++ b/libgloss/microblaze/_exception_handler.S
 @@ -30,7 +30,11 @@
@@ -46,7 +46,7 @@ index 7a91a78..0fdff3f 100644
  	.ent _exception_handler
  	.type _exception_handler, @function
 diff --git a/libgloss/microblaze/_hw_exception_handler.S b/libgloss/microblaze/_hw_exception_handler.S
-index 47df945..b951a63 100644
+index 47df945c4..b951a6325 100644
 --- a/libgloss/microblaze/_hw_exception_handler.S
 +++ b/libgloss/microblaze/_hw_exception_handler.S
 @@ -32,8 +32,11 @@
@@ -64,7 +64,7 @@ index 47df945..b951a63 100644
  	rted    r17, 0
  	nop
 diff --git a/libgloss/microblaze/_interrupt_handler.S b/libgloss/microblaze/_interrupt_handler.S
-index 5bb7329..a0ef92d 100644
+index 5bb7329cc..a0ef92df0 100644
 --- a/libgloss/microblaze/_interrupt_handler.S
 +++ b/libgloss/microblaze/_interrupt_handler.S
 @@ -32,8 +32,11 @@
@@ -82,7 +82,7 @@ index 5bb7329..a0ef92d 100644
  	rtid    r14, 0
  	nop
 diff --git a/libgloss/microblaze/_program_clean.S b/libgloss/microblaze/_program_clean.S
-index c460594..0d55d8a 100644
+index c46059434..0d55d8ab8 100644
 --- a/libgloss/microblaze/_program_clean.S
 +++ b/libgloss/microblaze/_program_clean.S
 @@ -33,7 +33,11 @@
@@ -99,7 +99,7 @@ index c460594..0d55d8a 100644
  	.ent	_program_clean
  _program_clean:
 diff --git a/libgloss/microblaze/_program_init.S b/libgloss/microblaze/_program_init.S
-index 0daa42e..862ef78 100644
+index 0daa42e14..862ef786b 100644
 --- a/libgloss/microblaze/_program_init.S
 +++ b/libgloss/microblaze/_program_init.S
 @@ -32,7 +32,11 @@
@@ -116,7 +116,7 @@ index 0daa42e..862ef78 100644
  	.ent	_program_init
  _program_init:
 diff --git a/libgloss/microblaze/crt0.S b/libgloss/microblaze/crt0.S
-index 865a8c2..e4df73b 100644
+index 865a8c269..e4df73b66 100644
 --- a/libgloss/microblaze/crt0.S
 +++ b/libgloss/microblaze/crt0.S
 @@ -54,7 +54,11 @@
@@ -222,7 +222,7 @@ index 865a8c2..e4df73b 100644
 +#endif
  	.end _exit        
 diff --git a/libgloss/microblaze/crt1.S b/libgloss/microblaze/crt1.S
-index a8bf749..b24eeb5 100644
+index a8bf74937..b24eeb531 100644
 --- a/libgloss/microblaze/crt1.S
 +++ b/libgloss/microblaze/crt1.S
 @@ -53,36 +53,67 @@
@@ -321,7 +321,7 @@ index a8bf749..b24eeb5 100644
  	.end _exit        
 -
 diff --git a/libgloss/microblaze/crt2.S b/libgloss/microblaze/crt2.S
-index 34d9f95..ae4c89e 100644
+index 34d9f951d..ae4c89ee0 100644
 --- a/libgloss/microblaze/crt2.S
 +++ b/libgloss/microblaze/crt2.S
 @@ -51,26 +51,56 @@
@@ -415,7 +415,7 @@ index 34d9f95..ae4c89e 100644
 +#endif
  	.end _exit        
 diff --git a/libgloss/microblaze/crt3.S b/libgloss/microblaze/crt3.S
-index ebcf207..a8bc783 100644
+index ebcf207f5..a8bc7839b 100644
 --- a/libgloss/microblaze/crt3.S
 +++ b/libgloss/microblaze/crt3.S
 @@ -53,10 +53,26 @@
@@ -476,7 +476,7 @@ index ebcf207..a8bc783 100644
 +#endif
  	.end _exit        
 diff --git a/libgloss/microblaze/crt4.S b/libgloss/microblaze/crt4.S
-index 4cf0b01..54ba473 100644
+index 4cf0b01a4..54ba473ea 100644
 --- a/libgloss/microblaze/crt4.S
 +++ b/libgloss/microblaze/crt4.S
 @@ -53,10 +53,27 @@
@@ -542,7 +542,7 @@ index 4cf0b01..54ba473 100644
 +#endif
  	.end _exit        
 diff --git a/libgloss/microblaze/crtinit.S b/libgloss/microblaze/crtinit.S
-index 86c6dfc..8541175 100644
+index 86c6dfcb0..854117536 100644
 --- a/libgloss/microblaze/crtinit.S
 +++ b/libgloss/microblaze/crtinit.S
 @@ -29,59 +29,115 @@
@@ -694,7 +694,7 @@ index 86c6dfc..8541175 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/linux-crt0.S b/libgloss/microblaze/linux-crt0.S
-index 8650bb5..503439b 100644
+index 8650bb5d2..503439b2e 100644
 --- a/libgloss/microblaze/linux-crt0.S
 +++ b/libgloss/microblaze/linux-crt0.S
 @@ -18,26 +18,50 @@
@@ -789,7 +789,7 @@ index 8650bb5..503439b 100644
  	sw      r15, r0, r1
 +#endif
 diff --git a/libgloss/microblaze/linux-syscalls.S b/libgloss/microblaze/linux-syscalls.S
-index 506de78..8594f13 100644
+index 506de78fd..8594f136e 100644
 --- a/libgloss/microblaze/linux-syscalls.S
 +++ b/libgloss/microblaze/linux-syscalls.S
 @@ -20,8 +20,9 @@
@@ -823,7 +823,7 @@ index 506de78..8594f13 100644
  SYSCALL(exit)
  SYSCALL(read)
 diff --git a/libgloss/microblaze/pgcrtinit.S b/libgloss/microblaze/pgcrtinit.S
-index 2593082..638dbd3 100644
+index 25930821c..638dbd383 100644
 --- a/libgloss/microblaze/pgcrtinit.S
 +++ b/libgloss/microblaze/pgcrtinit.S
 @@ -29,10 +29,66 @@
@@ -904,7 +904,7 @@ index 2593082..638dbd3 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/sim-crtinit.S b/libgloss/microblaze/sim-crtinit.S
-index 74586d9..9892cb0 100644
+index 74586d9a7..9892cb0bd 100644
 --- a/libgloss/microblaze/sim-crtinit.S
 +++ b/libgloss/microblaze/sim-crtinit.S
 @@ -35,10 +35,39 @@
@@ -958,7 +958,7 @@ index 74586d9..9892cb0 100644
  	.end _crtinit
  
 diff --git a/libgloss/microblaze/sim-pgcrtinit.S b/libgloss/microblaze/sim-pgcrtinit.S
-index 82ebcca..939f537 100644
+index 82ebccad4..939f5372f 100644
 --- a/libgloss/microblaze/sim-pgcrtinit.S
 +++ b/libgloss/microblaze/sim-pgcrtinit.S
 @@ -35,10 +35,40 @@
@@ -1010,7 +1010,7 @@ index 82ebcca..939f537 100644
  	.end _crtinit
  
 diff --git a/newlib/libc/machine/microblaze/longjmp.S b/newlib/libc/machine/microblaze/longjmp.S
-index f972bbd..5ed1c26 100644
+index f972bbd88..5ed1c2626 100644
 --- a/newlib/libc/machine/microblaze/longjmp.S
 +++ b/newlib/libc/machine/microblaze/longjmp.S
 @@ -51,16 +51,46 @@
@@ -1082,7 +1082,7 @@ index f972bbd..5ed1c26 100644
 +#endif
  .end longjmp    
 diff --git a/newlib/libc/machine/microblaze/setjmp.S b/newlib/libc/machine/microblaze/setjmp.S
-index cdd87c7..971862b 100644
+index cdd87c76f..971862bcb 100644
 --- a/newlib/libc/machine/microblaze/setjmp.S
 +++ b/newlib/libc/machine/microblaze/setjmp.S
 @@ -50,9 +50,39 @@
@@ -1133,5 +1133,5 @@ index cdd87c7..971862b 100644
 +#endif
  .end setjmp    
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch
index 9f27cd60ca..437d29f327 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch
@@ -1,4 +1,4 @@
-From 1c7a9150b63089baf3f63c64bf3dbb4d73c814f5 Mon Sep 17 00:00:00 2001
+From 000cfdc6f16009e62c236267ce7123a9ef2380e9 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Fri, 28 Sep 2018 12:07:43 +0530
 Subject: [PATCH 08/11] fixing the bug in crt files, added addlik instead of
@@ -13,7 +13,7 @@ Subject: [PATCH 08/11] fixing the bug in crt files, added addlik instead of
  5 files changed, 15 insertions(+), 15 deletions(-)
 
 diff --git a/libgloss/microblaze/crt0.S b/libgloss/microblaze/crt0.S
-index e4df73b..25e7c4a 100644
+index e4df73b66..25e7c4af3 100644
 --- a/libgloss/microblaze/crt0.S
 +++ b/libgloss/microblaze/crt0.S
 @@ -106,9 +106,9 @@ _vector_hw_exception:
@@ -30,7 +30,7 @@ index e4df73b..25e7c4a 100644
          nop
          addlik   r5, r3, 0
 diff --git a/libgloss/microblaze/crt1.S b/libgloss/microblaze/crt1.S
-index b24eeb5..38440c9 100644
+index b24eeb531..38440c957 100644
 --- a/libgloss/microblaze/crt1.S
 +++ b/libgloss/microblaze/crt1.S
 @@ -94,9 +94,9 @@ _vector_hw_exception:
@@ -47,7 +47,7 @@ index b24eeb5..38440c9 100644
          brealid   r15, _crtinit               /* Initialize BSS and run program */
  	nop
 diff --git a/libgloss/microblaze/crt2.S b/libgloss/microblaze/crt2.S
-index ae4c89e..352927d 100644
+index ae4c89ee0..352927dab 100644
 --- a/libgloss/microblaze/crt2.S
 +++ b/libgloss/microblaze/crt2.S
 @@ -92,9 +92,9 @@ _vector_hw_exception:
@@ -64,7 +64,7 @@ index ae4c89e..352927d 100644
          nop
  	addlik	r5, r3, 0
 diff --git a/libgloss/microblaze/crt3.S b/libgloss/microblaze/crt3.S
-index a8bc783..bc32cda 100644
+index a8bc7839b..bc32cda86 100644
 --- a/libgloss/microblaze/crt3.S
 +++ b/libgloss/microblaze/crt3.S
 @@ -62,9 +62,9 @@
@@ -81,7 +81,7 @@ index a8bc783..bc32cda 100644
          brealid	r15, _crtinit               /* Initialize BSS and run program */
          nop
 diff --git a/libgloss/microblaze/crt4.S b/libgloss/microblaze/crt4.S
-index 54ba473..a25c847 100644
+index 54ba473ea..a25c84734 100644
 --- a/libgloss/microblaze/crt4.S
 +++ b/libgloss/microblaze/crt4.S
 @@ -63,9 +63,9 @@
@@ -98,5 +98,5 @@ index 54ba473..a25c847 100644
          brealid	r15, _crtinit               /* Initialize BSS and run program */
  	nop
 -- 
-2.7.4
+2.17.1
 
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Added-MB-64-support-to-strcmp-strcpy-strlen-files.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Added-MB-64-support-to-strcmp-strcpy-strlen-files.patch
deleted file mode 100644
index 38508b550e..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Added-MB-64-support-to-strcmp-strcpy-strlen-files.patch
+++ /dev/null
@@ -1,227 +0,0 @@
-From 19d7b2a34f3c69d62f570ac9d0f6bc3cd584b496 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 14 Mar 2019 18:16:32 +0530
-Subject: [PATCH 09/11] Added MB-64 support to strcmp/strcpy/strlen files
-
----
- newlib/libc/machine/microblaze/strcmp.c | 61 ++++++++++++++++++++++++++++++++-
- newlib/libc/machine/microblaze/strcpy.c | 57 ++++++++++++++++++++++++++++++
- newlib/libc/machine/microblaze/strlen.c | 38 ++++++++++++++++++++
- 3 files changed, 155 insertions(+), 1 deletion(-)
-
-diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
-index 3119d82..dac64da 100644
---- a/newlib/libc/machine/microblaze/strcmp.c
-+++ b/newlib/libc/machine/microblaze/strcmp.c
-@@ -133,6 +133,65 @@ strcmp (const char *s1,
- 
- #include "mb_endian.h"
- 
-+#ifdef __arch64__
-+    asm volatile ("                                          \n\
-+        orl      r9, r0, r0               /* Index register */\n\
-+check_alignment:                                             \n\
-+        andli    r3, r5, 3                                    \n\
-+        andli    r4, r6, 3                                    \n\
-+        beanei    r3, try_align_args                           \n\
-+        beanei    r4, regular_strcmp     /* At this point we don't have a choice */ \n\
-+cmp_loop:                                                                       \n"
-+        LOAD4BYTES("r3", "r5", "r9")
-+        LOAD4BYTES("r4", "r6", "r9")
-+"                                                                                      \n\
-+        pcmplbf  r7, r3, r0              /* See if there is Null byte */                         \n\
-+        beanei    r7, end_cmp_loop        /* IF yes (r7 > 0) use byte compares in end_cmp_loop */ \n\
-+        cmplu    r7, r4, r3              /* ELSE compare whole word */                   \n\
-+        beanei    r7, end_cmp                                                             \n\
-+        addlik   r9, r9, 4               /* delay slot */                                \n\
-+        breaid    cmp_loop                                                                \n\
-+        nop		               /* delay slot */                                \n\
-+end_cmp_loop:                                                                           \n\
-+        lbu     r3, r5, r9              /* byte compare loop */                         \n\
-+        lbu     r4, r6, r9                                                              \n\
-+        cmplu    r7, r4, r3              /* Compare bytes */                             \n\
-+        beanei    r7, end_cmp_early                                                       \n\
-+        addlik   r9, r9, 1               /* delay slot */                        \n\
-+        beaneid   r3, end_cmp_loop        /* If reached null on one string, terminate */  \n\
-+        nop					                              \n\
-+end_cmp_early:                                                                  \n\
-+        or   r3, r0, r7               /* delay slot */                        \n\
-+        rtsd    r15, 8                                                          \n\
-+        nop		                                                         \n\
-+try_align_args:                                                                 \n\
-+        xorl     r7, r4, r3                                                      \n\
-+        beanei    r7, regular_strcmp      /* cannot align args */                 \n\
-+        rsublik  r10, r3, 4              /* Number of initial bytes to align */  \n\
-+align_loop:                                                                     \n\
-+        lbu     r3, r5, r9                                                      \n\
-+        lbu     r4, r6, r9                                                      \n\
-+        cmpu    r7, r4, r3                                                      \n\
-+        beanei    r7, end_cmp                                                     \n\
-+        beaeqi    r3, end_cmp                                                     \n\
-+        addlik   r10, r10, -1                                                    \n\
-+        addlik   r9, r9, 1                                                       \n\
-+        beaeqid   r10, cmp_loop                                                   \n\
-+        nop		                                                           \n\
-+        breai     align_loop                                                      \n\
-+regular_strcmp:                                                                 \n\
-+        lbu     r3, r5, r9                                                      \n\
-+        lbu     r4, r6, r9                                                      \n\
-+        cmplu    r7, r4, r3                                                      \n\
-+        beanei    r7, end_cmp                                                     \n\
-+        beaeqi    r3, end_cmp                                                     \n\
-+        breaid    regular_strcmp                                                  \n\
-+        addlik   r9, r9, 1                                                       \n\
-+end_cmp:                                                                        \n\
-+        or       r3, r0, r7                                                       \n\
-+        rtsd    r15, 8                                                          \n\
-+        nop              /* Return strcmp result */");
-+#else
-     asm volatile ("                                          \n\
-         or      r9, r0, r0               /* Index register */\n\
- check_alignment:                                             \n\
-@@ -181,11 +240,11 @@ regular_strcmp:
-         bnei    r7, end_cmp                                                     \n\
-         beqi    r3, end_cmp                                                     \n\
-         brid    regular_strcmp                                                  \n\
--        addik   r9, r9, 1                                                       \n\
- end_cmp:                                                                        \n\
-         rtsd    r15, 8                                                          \n\
-         or      r3, r0, r7              /* Return strcmp result */");
- 
-+#endif
- #endif /* ! HAVE_HW_PCMP */
- }
- 
-diff --git a/newlib/libc/machine/microblaze/strcpy.c b/newlib/libc/machine/microblaze/strcpy.c
-index 62072fa..6dbc60d 100644
---- a/newlib/libc/machine/microblaze/strcpy.c
-+++ b/newlib/libc/machine/microblaze/strcpy.c
-@@ -125,6 +125,62 @@ strcpy (char *__restrict dst0,
- #else    
- 
- #include "mb_endian.h"
-+#ifdef __arch64__
-+
-+  asm volatile ("                                                   \n\
-+        orl      r9, r0, r0              /* Index register */        \n\
-+check_alignment:                                                    \n\
-+        andli    r3, r5, 3                                           \n\
-+        andli    r4, r6, 3                                           \n\
-+        beanei    r3, try_align_args                                  \n\
-+        beanei    r4, regular_strcpy      /* At this point we dont have a choice */       \n\
-+cpy_loop:                                   \n"
-+        LOAD4BYTES("r3", "r6", "r9")
-+"                                           \n\
-+        pcmplbf  r4, r0, r3                  \n\
-+        beanei    r4, cpy_bytes           /* If r4 != 0, then null present within string */\n"
-+        STORE4BYTES("r3", "r5", "r9")
-+"                                           \n\
-+        addlik   r9, r9, 4                   \n\
-+        breaid    cpy_loop                    \n\
-+	nop					\n\
-+cpy_bytes:                                  \n\
-+        lbu     r3, r6, r9                  \n\
-+        sb      r3, r5, r9                  \n\
-+        addlik   r4, r4, -1                  \n\
-+        addlik   r9, r9, 1               /* delay slot */\n\
-+        beaneid   r4, cpy_bytes               \n\
-+	nop					\n\
-+cpy_null:                                   \n\
-+        orl      r3, r0, r5              /* Return strcpy result */\n\
-+        rtsd    r15, 8                      \n\
-+	nop					\n\
-+try_align_args:                             \n\
-+        xorl     r7, r4, r3                  \n\
-+        beanei    r7, regular_strcpy      /* cannot align args */\n\
-+        rsublik  r10, r3, 4              /* Number of initial bytes to align */\n\
-+align_loop:                                 \n\
-+        lbu     r3, r6, r9                  \n\
-+        sb      r3, r5, r9                  \n\
-+        addlik   r10, r10, -1                \n\
-+        beaeqid   r3, end_cpy             /* Break if we have seen null character */\n\
-+	nop					\n\
-+        addlik   r9, r9, 1                   \n\
-+        beaneid   r10, align_loop             \n\
-+	nop					\n\
-+        breai     cpy_loop                    \n\
-+regular_strcpy:                             \n\
-+        lbu     r3, r6, r9                  \n\
-+        sb      r3, r5, r9                  \n\
-+        addlik   r9, r9, 1                   \n\
-+        beaneid   r3, regular_strcpy          \n\
-+	nop					\n\
-+end_cpy:                                    \n\
-+        orl      r3, r0, r5  			\n\
-+        rtsd    r15, 8                      \n\
-+	nop			 /* Return strcpy result */");
-+
-+#else
- 
-   asm volatile ("                                                   \n\
-         or      r9, r0, r0              /* Index register */        \n\
-@@ -171,6 +227,7 @@ regular_strcpy:                             \n\
- end_cpy:                                    \n\
-         rtsd    r15, 8                      \n\
-         or      r3, r0, r5              /* Return strcpy result */");
-+#endif
- #endif /* ! HAVE_HW_PCMP */
- }
- 
-diff --git a/newlib/libc/machine/microblaze/strlen.c b/newlib/libc/machine/microblaze/strlen.c
-index acb4464..c04fa4f 100644
---- a/newlib/libc/machine/microblaze/strlen.c
-+++ b/newlib/libc/machine/microblaze/strlen.c
-@@ -116,6 +116,43 @@ strlen (const char *str)
- 
- #include "mb_endian.h"
- 
-+#ifdef __arch64__
-+  asm volatile ("                                               \n\
-+        orl      r9, r0, r0              /* Index register */    \n\
-+check_alignment:                                                \n\
-+        andli    r3, r5, 3                                       \n\
-+        beanei    r3, align_arg                                   \n\
-+len_loop:                                                       \n"
-+        LOAD4BYTES("r3", "r5", "r9")
-+"                                                               \n\
-+        pcmplbf  r4, r3, r0                                      \n\
-+        beanei    r4, end_len                                     \n\
-+        addik   r9, r9, 4                                       \n\
-+        breaid    len_loop                                        \n\
-+        nop		                                        \n\
-+end_len:                                                        \n\
-+        lbu     r3, r5, r9                                      \n\
-+        beaeqi    r3, done_len                                    \n\
-+        addik   r9, r9, 1                                       \n\
-+        breaid    end_len                                         \n\
-+        nop		                                       \n\
-+done_len:                                                       \n\
-+        orl      r3, r0, r9              /* Return len */        \n\
-+        rtsd    r15, 8                                          \n\
-+        nop						        \n\
-+align_arg:                                                      \n\
-+        rsublik  r10, r3, 4                                      \n\
-+align_loop:                                                     \n\
-+        lbu     r3, r5, r9                                      \n\
-+        addlik   r10, r10, -1                                    \n\
-+        beaeqid   r3, done_len                                    \n\
-+        nop		                                       \n\
-+        addlik   r9, r9, 1                                       \n\
-+        beaneid   r10, align_loop                                 \n\
-+        nop		                                        \n\
-+        breai     len_loop");
-+
-+#else
-   asm volatile ("                                               \n\
-         or      r9, r0, r0              /* Index register */    \n\
- check_alignment:                                                \n\
-@@ -146,5 +183,6 @@ align_loop:                                                     \n\
-         addik   r9, r9, 1                                       \n\
-         bri     len_loop");
- 
-+#endif
- #endif  /* ! HAVE_HW_PCMP */
- }
--- 
-2.7.4
-
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Patch-MicroBlaze-Added-MB-64-support-to-strcmp-strcp.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Patch-MicroBlaze-Added-MB-64-support-to-strcmp-strcp.patch
new file mode 100644
index 0000000000..1d4394d362
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0009-Patch-MicroBlaze-Added-MB-64-support-to-strcmp-strcp.patch
@@ -0,0 +1,230 @@
+From 6587a1cae28468f5a49659a39040f60e425827a7 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Nov 2020 13:06:41 +0530
+Subject: [PATCH 09/11] [Patch,MicroBlaze] : Added MB-64 support to
+ strcmp/strcpy/strlen files Signed-off-by:Mahesh Bodapati<mbodapat@xilinx.com>
+
+---
+ newlib/libc/machine/microblaze/strcmp.c | 63 ++++++++++++++++++++++++-
+ newlib/libc/machine/microblaze/strcpy.c | 57 ++++++++++++++++++++++
+ newlib/libc/machine/microblaze/strlen.c | 38 +++++++++++++++
+ 3 files changed, 157 insertions(+), 1 deletion(-)
+
+diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
+index 3119d82c5..2cfef7388 100644
+--- a/newlib/libc/machine/microblaze/strcmp.c
++++ b/newlib/libc/machine/microblaze/strcmp.c
+@@ -133,6 +133,66 @@ strcmp (const char *s1,
+ 
+ #include "mb_endian.h"
+ 
++#ifdef __arch64__
++    asm volatile ("                                          \n\
++        orl      r9, r0, r0               /* Index register */ \n\
++check_alignment:                                             \n\
++        andli    r3, r5, 3                                    \n\
++        andli    r4, r6, 3                                    \n\
++        beanei    r3, try_align_args                           \n\
++        beanei    r4, regular_strcmp     /* At this point we don't have a choice */ \n\
++cmp_loop:                                                                       \n"
++        LOAD4BYTES("r3", "r5", "r9")
++        LOAD4BYTES("r4", "r6", "r9")
++"                                                                                      \n\
++        pcmplbf  r7, r3, r0              /* See if there is Null byte */                         \n\
++        beanei    r7, end_cmp_loop        /* IF yes (r7 > 0) use byte compares in end_cmp_loop */ \n\
++        cmplu    r7, r4, r3              /* ELSE compare whole word */                   \n\
++        beanei    r7, end_cmp                                                             \n\
++        addlik   r9, r9, 4               /* delay slot */                                \n\
++        breaid    cmp_loop                                                                \n\
++        nop		               /* delay slot */                                \n\
++end_cmp_loop:                                                                           \n\
++        lbu     r3, r5, r9              /* byte compare loop */                         \n\
++        lbu     r4, r6, r9                                                              \n\
++        cmplu    r7, r4, r3              /* Compare bytes */                             \n\
++        beanei    r7, end_cmp_early                                                       \n\
++        addlik   r9, r9, 1               /* delay slot */                        \n\
++        beaneid   r3, end_cmp_loop        /* If reached null on one string, terminate */  \n\
++        nop					                              \n\
++end_cmp_early:                                                                  \n\
++        orl   r3, r0, r7               /* delay slot */                        \n\
++        rtsd    r15, 8                                                          \n\
++        nop		                                                         \n\
++try_align_args:                                                                 \n\
++        xorl     r7, r4, r3                                                      \n\
++        beanei    r7, regular_strcmp      /* cannot align args */                 \n\
++        rsublik  r10, r3, 4              /* Number of initial bytes to align */  \n\
++align_loop:                                                                     \n\
++        lbu     r3, r5, r9                                                      \n\
++        lbu     r4, r6, r9                                                      \n\
++        cmplu    r7, r4, r3                                                      \n\
++        beanei    r7, end_cmp                                                     \n\
++        beaeqi    r3, end_cmp                                                     \n\
++        addlik   r10, r10, -1                                                    \n\
++        addlik   r9, r9, 1                                                       \n\
++        beaeqid   r10, cmp_loop                                                   \n\
++        nop		                                                           \n\
++        breai     align_loop                                                      \n\
++regular_strcmp:                                                                 \n\
++        lbu     r3, r5, r9                                                      \n\
++        lbu     r4, r6, r9                                                      \n\
++        cmplu    r7, r4, r3                                                      \n\
++        beanei    r7, end_cmp                                                     \n\
++        beaeqi    r3, end_cmp                                                     \n\
++        addlik   r9, r9, 1                                                       \n\
++        breaid    regular_strcmp                                                  \n\
++        nop									\n\
++end_cmp:                                                                        \n\
++        orl       r3, r0, r7                                                       \n\
++        rtsd    r15, 8                                                          \n\
++        nop              /* Return strcmp result */");
++#else
+     asm volatile ("                                          \n\
+         or      r9, r0, r0               /* Index register */\n\
+ check_alignment:                                             \n\
+@@ -181,11 +241,12 @@ regular_strcmp:
+         bnei    r7, end_cmp                                                     \n\
+         beqi    r3, end_cmp                                                     \n\
+         brid    regular_strcmp                                                  \n\
+-        addik   r9, r9, 1                                                       \n\
++        addik	r9, r9, 1
+ end_cmp:                                                                        \n\
+         rtsd    r15, 8                                                          \n\
+         or      r3, r0, r7              /* Return strcmp result */");
+ 
++#endif
+ #endif /* ! HAVE_HW_PCMP */
+ }
+ 
+diff --git a/newlib/libc/machine/microblaze/strcpy.c b/newlib/libc/machine/microblaze/strcpy.c
+index 62072fa28..6dbc60d77 100644
+--- a/newlib/libc/machine/microblaze/strcpy.c
++++ b/newlib/libc/machine/microblaze/strcpy.c
+@@ -125,6 +125,62 @@ strcpy (char *__restrict dst0,
+ #else    
+ 
+ #include "mb_endian.h"
++#ifdef __arch64__
++
++  asm volatile ("                                                   \n\
++        orl      r9, r0, r0              /* Index register */        \n\
++check_alignment:                                                    \n\
++        andli    r3, r5, 3                                           \n\
++        andli    r4, r6, 3                                           \n\
++        beanei    r3, try_align_args                                  \n\
++        beanei    r4, regular_strcpy      /* At this point we dont have a choice */       \n\
++cpy_loop:                                   \n"
++        LOAD4BYTES("r3", "r6", "r9")
++"                                           \n\
++        pcmplbf  r4, r0, r3                  \n\
++        beanei    r4, cpy_bytes           /* If r4 != 0, then null present within string */\n"
++        STORE4BYTES("r3", "r5", "r9")
++"                                           \n\
++        addlik   r9, r9, 4                   \n\
++        breaid    cpy_loop                    \n\
++	nop					\n\
++cpy_bytes:                                  \n\
++        lbu     r3, r6, r9                  \n\
++        sb      r3, r5, r9                  \n\
++        addlik   r4, r4, -1                  \n\
++        addlik   r9, r9, 1               /* delay slot */\n\
++        beaneid   r4, cpy_bytes               \n\
++	nop					\n\
++cpy_null:                                   \n\
++        orl      r3, r0, r5              /* Return strcpy result */\n\
++        rtsd    r15, 8                      \n\
++	nop					\n\
++try_align_args:                             \n\
++        xorl     r7, r4, r3                  \n\
++        beanei    r7, regular_strcpy      /* cannot align args */\n\
++        rsublik  r10, r3, 4              /* Number of initial bytes to align */\n\
++align_loop:                                 \n\
++        lbu     r3, r6, r9                  \n\
++        sb      r3, r5, r9                  \n\
++        addlik   r10, r10, -1                \n\
++        beaeqid   r3, end_cpy             /* Break if we have seen null character */\n\
++	nop					\n\
++        addlik   r9, r9, 1                   \n\
++        beaneid   r10, align_loop             \n\
++	nop					\n\
++        breai     cpy_loop                    \n\
++regular_strcpy:                             \n\
++        lbu     r3, r6, r9                  \n\
++        sb      r3, r5, r9                  \n\
++        addlik   r9, r9, 1                   \n\
++        beaneid   r3, regular_strcpy          \n\
++	nop					\n\
++end_cpy:                                    \n\
++        orl      r3, r0, r5  			\n\
++        rtsd    r15, 8                      \n\
++	nop			 /* Return strcpy result */");
++
++#else
+ 
+   asm volatile ("                                                   \n\
+         or      r9, r0, r0              /* Index register */        \n\
+@@ -171,6 +227,7 @@ regular_strcpy:                             \n\
+ end_cpy:                                    \n\
+         rtsd    r15, 8                      \n\
+         or      r3, r0, r5              /* Return strcpy result */");
++#endif
+ #endif /* ! HAVE_HW_PCMP */
+ }
+ 
+diff --git a/newlib/libc/machine/microblaze/strlen.c b/newlib/libc/machine/microblaze/strlen.c
+index acb4464bc..b6f2d3c13 100644
+--- a/newlib/libc/machine/microblaze/strlen.c
++++ b/newlib/libc/machine/microblaze/strlen.c
+@@ -116,6 +116,43 @@ strlen (const char *str)
+ 
+ #include "mb_endian.h"
+ 
++#ifdef __arch64__
++  asm volatile ("                                               \n\
++        orl      r9, r0, r0              /* Index register */    \n\
++check_alignment:                                                \n\
++        andli    r3, r5, 3                                       \n\
++        beanei    r3, align_arg                                   \n\
++len_loop:                                                       \n"
++        LOAD4BYTES("r3", "r5", "r9")
++"                                                               \n\
++        pcmplbf  r4, r3, r0                                      \n\
++        beanei    r4, end_len                                     \n\
++        addlik   r9, r9, 4                                       \n\
++        breaid    len_loop                                        \n\
++        nop		                                        \n\
++end_len:                                                        \n\
++        lbu     r3, r5, r9                                      \n\
++        beaeqi    r3, done_len                                    \n\
++        addlik   r9, r9, 1                                       \n\
++        breaid    end_len                                         \n\
++        nop		                                       \n\
++done_len:                                                       \n\
++        orl      r3, r0, r9              /* Return len */        \n\
++        rtsd    r15, 8                                          \n\
++        nop						        \n\
++align_arg:                                                      \n\
++        rsublik  r10, r3, 4                                      \n\
++align_loop:                                                     \n\
++        lbu     r3, r5, r9                                      \n\
++        addlik   r10, r10, -1                                    \n\
++        beaeqid   r3, done_len                                    \n\
++        nop		                                       \n\
++        addlik   r9, r9, 1                                       \n\
++        beaneid   r10, align_loop                                 \n\
++        nop		                                        \n\
++        breai     len_loop");
++
++#else
+   asm volatile ("                                               \n\
+         or      r9, r0, r0              /* Index register */    \n\
+ check_alignment:                                                \n\
+@@ -146,5 +183,6 @@ align_loop:                                                     \n\
+         addik   r9, r9, 1                                       \n\
+         bri     len_loop");
+ 
++#endif
+ #endif  /* ! HAVE_HW_PCMP */
+ }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Patch-MicroBlaze-typos-in-string-functions-microblaz.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Patch-MicroBlaze-typos-in-string-functions-microblaz.patch
deleted file mode 100644
index d1f19a74f9..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Patch-MicroBlaze-typos-in-string-functions-microblaz.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 70281e45fa433ec854f60b43fef019ebc8ca0649 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 3 Apr 2019 11:52:50 +0530
-Subject: [PATCH 10/11] [Patch,MicroBlaze] : typos in string functions
- microblaze 64 bit port.fixed the issues.
-
----
- newlib/libc/machine/microblaze/strcmp.c | 12 +++++++-----
- newlib/libc/machine/microblaze/strlen.c |  4 ++--
- 2 files changed, 9 insertions(+), 7 deletions(-)
-
-diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
-index dac64da..acfe4cd 100644
---- a/newlib/libc/machine/microblaze/strcmp.c
-+++ b/newlib/libc/machine/microblaze/strcmp.c
-@@ -135,7 +135,7 @@ strcmp (const char *s1,
- 
- #ifdef __arch64__
-     asm volatile ("                                          \n\
--        orl      r9, r0, r0               /* Index register */\n\
-+        orl      r9, r0, r0               /* Index register */ \n\
- check_alignment:                                             \n\
-         andli    r3, r5, 3                                    \n\
-         andli    r4, r6, 3                                    \n\
-@@ -161,7 +161,7 @@ end_cmp_loop:
-         beaneid   r3, end_cmp_loop        /* If reached null on one string, terminate */  \n\
-         nop					                              \n\
- end_cmp_early:                                                                  \n\
--        or   r3, r0, r7               /* delay slot */                        \n\
-+        orl   r3, r0, r7               /* delay slot */                        \n\
-         rtsd    r15, 8                                                          \n\
-         nop		                                                         \n\
- try_align_args:                                                                 \n\
-@@ -171,7 +171,7 @@ try_align_args:
- align_loop:                                                                     \n\
-         lbu     r3, r5, r9                                                      \n\
-         lbu     r4, r6, r9                                                      \n\
--        cmpu    r7, r4, r3                                                      \n\
-+        cmplu    r7, r4, r3                                                      \n\
-         beanei    r7, end_cmp                                                     \n\
-         beaeqi    r3, end_cmp                                                     \n\
-         addlik   r10, r10, -1                                                    \n\
-@@ -185,10 +185,11 @@ regular_strcmp:
-         cmplu    r7, r4, r3                                                      \n\
-         beanei    r7, end_cmp                                                     \n\
-         beaeqi    r3, end_cmp                                                     \n\
--        breaid    regular_strcmp                                                  \n\
-         addlik   r9, r9, 1                                                       \n\
-+        breaid    regular_strcmp                                                  \n\
-+        nop                                                  \n\
- end_cmp:                                                                        \n\
--        or       r3, r0, r7                                                       \n\
-+        orl       r3, r0, r7                                                       \n\
-         rtsd    r15, 8                                                          \n\
-         nop              /* Return strcmp result */");
- #else
-@@ -240,6 +241,7 @@ regular_strcmp:
-         bnei    r7, end_cmp                                                     \n\
-         beqi    r3, end_cmp                                                     \n\
-         brid    regular_strcmp                                                  \n\
-+        addik   r9, r9, 1                                                       \n\
- end_cmp:                                                                        \n\
-         rtsd    r15, 8                                                          \n\
-         or      r3, r0, r7              /* Return strcmp result */");
-diff --git a/newlib/libc/machine/microblaze/strlen.c b/newlib/libc/machine/microblaze/strlen.c
-index c04fa4f..b6f2d3c 100644
---- a/newlib/libc/machine/microblaze/strlen.c
-+++ b/newlib/libc/machine/microblaze/strlen.c
-@@ -127,13 +127,13 @@ len_loop:                                                       \n"
- "                                                               \n\
-         pcmplbf  r4, r3, r0                                      \n\
-         beanei    r4, end_len                                     \n\
--        addik   r9, r9, 4                                       \n\
-+        addlik   r9, r9, 4                                       \n\
-         breaid    len_loop                                        \n\
-         nop		                                        \n\
- end_len:                                                        \n\
-         lbu     r3, r5, r9                                      \n\
-         beaeqi    r3, done_len                                    \n\
--        addik   r9, r9, 1                                       \n\
-+        addlik   r9, r9, 1                                       \n\
-         breaid    end_len                                         \n\
-         nop		                                       \n\
- done_len:                                                       \n\
--- 
-2.7.4
-
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Removing-the-Assembly-implementation-of-64bit-string.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Removing-the-Assembly-implementation-of-64bit-string.patch
new file mode 100644
index 0000000000..a63b9dfd12
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0010-Removing-the-Assembly-implementation-of-64bit-string.patch
@@ -0,0 +1,334 @@
+From fd624fc28cbca8863f4dd75f0bc08aba58f8455e Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 24 Apr 2019 23:29:21 +0530
+Subject: [PATCH 10/11] Removing the Assembly implementation of 64bit string
+ function. Revisit in next release and fix it
+
+Conflicts:
+	newlib/libc/machine/microblaze/strcmp.c
+---
+ newlib/libc/machine/microblaze/mb_endian.h |  4 +
+ newlib/libc/machine/microblaze/strcmp.c    | 94 ++++++++--------------
+ newlib/libc/machine/microblaze/strcpy.c    | 82 ++++++-------------
+ newlib/libc/machine/microblaze/strlen.c    | 59 +++++---------
+ 4 files changed, 81 insertions(+), 158 deletions(-)
+
+diff --git a/newlib/libc/machine/microblaze/mb_endian.h b/newlib/libc/machine/microblaze/mb_endian.h
+index fb217ec85..17772c88f 100644
+--- a/newlib/libc/machine/microblaze/mb_endian.h
++++ b/newlib/libc/machine/microblaze/mb_endian.h
+@@ -8,8 +8,12 @@
+ #ifdef __LITTLE_ENDIAN__
+ #define LOAD4BYTES(rD,rA,rB)   "\tlwr\t" rD ", " rA ", " rB "\n"
+ #define STORE4BYTES(rD,rA,rB)  "\tswr\t" rD ", " rA ", " rB "\n"
++#define LOAD8BYTES(rD,rA,rB)   "\tllr\t" rD ", " rA ", " rB "\n"
++#define STORE8BYTES(rD,rA,rB)  "\tslr\t" rD ", " rA ", " rB "\n"
+ #else
+ #define LOAD4BYTES(rD,rA,rB)   "\tlw\t" rD ", " rA ", " rB "\n"
+ #define STORE4BYTES(rD,rA,rB)  "\tsw\t" rD ", " rA ", " rB "\n"
++#define LOAD8BYTES(rD,rA,rB)   "\tll\t" rD ", " rA ", " rB "\n"
++#define STORE8BYTES(rD,rA,rB)  "\tsl\t" rD ", " rA ", " rB "\n"
+ #endif
+ #endif
+diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
+index 2cfef7388..007d9e1eb 100644
+--- a/newlib/libc/machine/microblaze/strcmp.c
++++ b/newlib/libc/machine/microblaze/strcmp.c
+@@ -129,70 +129,41 @@ strcmp (const char *s1,
+   return (*(unsigned char *) s1) - (*(unsigned char *) s2);
+ #endif /* not PREFER_SIZE_OVER_SPEED */
+ 
+-#else
++#elif __arch64__
++  unsigned int *a1;
++  unsigned int *a2;
+ 
+-#include "mb_endian.h"
++  /* If s1 or s2 are unaligned, then compare bytes. */
++  if (!UNALIGNED (s1, s2))
++    {  
++      /* If s1 and s2 are word-aligned, compare them a word at a time. */
++      a1 = (unsigned int*)s1;
++      a2 = (unsigned int*)s2;
++      while (*a1 == *a2)
++        {
++          /* To get here, *a1 == *a2, thus if we find a null in *a1,
++	     then the strings must be equal, so return zero.  */
++          if (DETECTNULL (*a1))
++	    return 0;
+ 
+-#ifdef __arch64__
+-    asm volatile ("                                          \n\
+-        orl      r9, r0, r0               /* Index register */ \n\
+-check_alignment:                                             \n\
+-        andli    r3, r5, 3                                    \n\
+-        andli    r4, r6, 3                                    \n\
+-        beanei    r3, try_align_args                           \n\
+-        beanei    r4, regular_strcmp     /* At this point we don't have a choice */ \n\
+-cmp_loop:                                                                       \n"
+-        LOAD4BYTES("r3", "r5", "r9")
+-        LOAD4BYTES("r4", "r6", "r9")
+-"                                                                                      \n\
+-        pcmplbf  r7, r3, r0              /* See if there is Null byte */                         \n\
+-        beanei    r7, end_cmp_loop        /* IF yes (r7 > 0) use byte compares in end_cmp_loop */ \n\
+-        cmplu    r7, r4, r3              /* ELSE compare whole word */                   \n\
+-        beanei    r7, end_cmp                                                             \n\
+-        addlik   r9, r9, 4               /* delay slot */                                \n\
+-        breaid    cmp_loop                                                                \n\
+-        nop		               /* delay slot */                                \n\
+-end_cmp_loop:                                                                           \n\
+-        lbu     r3, r5, r9              /* byte compare loop */                         \n\
+-        lbu     r4, r6, r9                                                              \n\
+-        cmplu    r7, r4, r3              /* Compare bytes */                             \n\
+-        beanei    r7, end_cmp_early                                                       \n\
+-        addlik   r9, r9, 1               /* delay slot */                        \n\
+-        beaneid   r3, end_cmp_loop        /* If reached null on one string, terminate */  \n\
+-        nop					                              \n\
+-end_cmp_early:                                                                  \n\
+-        orl   r3, r0, r7               /* delay slot */                        \n\
+-        rtsd    r15, 8                                                          \n\
+-        nop		                                                         \n\
+-try_align_args:                                                                 \n\
+-        xorl     r7, r4, r3                                                      \n\
+-        beanei    r7, regular_strcmp      /* cannot align args */                 \n\
+-        rsublik  r10, r3, 4              /* Number of initial bytes to align */  \n\
+-align_loop:                                                                     \n\
+-        lbu     r3, r5, r9                                                      \n\
+-        lbu     r4, r6, r9                                                      \n\
+-        cmplu    r7, r4, r3                                                      \n\
+-        beanei    r7, end_cmp                                                     \n\
+-        beaeqi    r3, end_cmp                                                     \n\
+-        addlik   r10, r10, -1                                                    \n\
+-        addlik   r9, r9, 1                                                       \n\
+-        beaeqid   r10, cmp_loop                                                   \n\
+-        nop		                                                           \n\
+-        breai     align_loop                                                      \n\
+-regular_strcmp:                                                                 \n\
+-        lbu     r3, r5, r9                                                      \n\
+-        lbu     r4, r6, r9                                                      \n\
+-        cmplu    r7, r4, r3                                                      \n\
+-        beanei    r7, end_cmp                                                     \n\
+-        beaeqi    r3, end_cmp                                                     \n\
+-        addlik   r9, r9, 1                                                       \n\
+-        breaid    regular_strcmp                                                  \n\
+-        nop									\n\
+-end_cmp:                                                                        \n\
+-        orl       r3, r0, r7                                                       \n\
+-        rtsd    r15, 8                                                          \n\
+-        nop              /* Return strcmp result */");
++          a1++;
++          a2++;
++        }
++
++      /* A difference was detected in last few bytes of s1, so search bytewise */
++      s1 = (char*)a1;
++      s2 = (char*)a2;
++    }
++
++  while (*s1 != '\0' && *s1 == *s2)
++    {
++      s1++;
++      s2++;
++    }
++  return (*(unsigned char *) s1) - (*(unsigned char *) s2);
+ #else
++
++#include "mb_endian.h"
+     asm volatile ("                                          \n\
+         or      r9, r0, r0               /* Index register */\n\
+ check_alignment:                                             \n\
+@@ -246,7 +217,6 @@ end_cmp:
+         rtsd    r15, 8                                                          \n\
+         or      r3, r0, r7              /* Return strcmp result */");
+ 
+-#endif
+ #endif /* ! HAVE_HW_PCMP */
+ }
+ 
+diff --git a/newlib/libc/machine/microblaze/strcpy.c b/newlib/libc/machine/microblaze/strcpy.c
+index 6dbc60d77..ddb69227e 100644
+--- a/newlib/libc/machine/microblaze/strcpy.c
++++ b/newlib/libc/machine/microblaze/strcpy.c
+@@ -121,67 +121,36 @@ strcpy (char *__restrict dst0,
+     ;
+   return dst0;
+ #endif /* not PREFER_SIZE_OVER_SPEED */
++#elif __arch64__
++  char *dst = dst0;
++  const char *src = src0;
++  long *aligned_dst;
++  const long *aligned_src;
+ 
+-#else    
++  /* If SRC or DEST is unaligned, then copy bytes.  */
++  if (!UNALIGNED (src, dst))
++    {
++      aligned_dst = (long*)dst;
++      aligned_src = (long*)src;
+ 
+-#include "mb_endian.h"
+-#ifdef __arch64__
++      /* SRC and DEST are both "long int" aligned, try to do "long int"
++         sized copies.  */
++      while (!DETECTNULL(*aligned_src))
++        {
++          *aligned_dst++ = *aligned_src++;
++        }
+ 
+-  asm volatile ("                                                   \n\
+-        orl      r9, r0, r0              /* Index register */        \n\
+-check_alignment:                                                    \n\
+-        andli    r3, r5, 3                                           \n\
+-        andli    r4, r6, 3                                           \n\
+-        beanei    r3, try_align_args                                  \n\
+-        beanei    r4, regular_strcpy      /* At this point we dont have a choice */       \n\
+-cpy_loop:                                   \n"
+-        LOAD4BYTES("r3", "r6", "r9")
+-"                                           \n\
+-        pcmplbf  r4, r0, r3                  \n\
+-        beanei    r4, cpy_bytes           /* If r4 != 0, then null present within string */\n"
+-        STORE4BYTES("r3", "r5", "r9")
+-"                                           \n\
+-        addlik   r9, r9, 4                   \n\
+-        breaid    cpy_loop                    \n\
+-	nop					\n\
+-cpy_bytes:                                  \n\
+-        lbu     r3, r6, r9                  \n\
+-        sb      r3, r5, r9                  \n\
+-        addlik   r4, r4, -1                  \n\
+-        addlik   r9, r9, 1               /* delay slot */\n\
+-        beaneid   r4, cpy_bytes               \n\
+-	nop					\n\
+-cpy_null:                                   \n\
+-        orl      r3, r0, r5              /* Return strcpy result */\n\
+-        rtsd    r15, 8                      \n\
+-	nop					\n\
+-try_align_args:                             \n\
+-        xorl     r7, r4, r3                  \n\
+-        beanei    r7, regular_strcpy      /* cannot align args */\n\
+-        rsublik  r10, r3, 4              /* Number of initial bytes to align */\n\
+-align_loop:                                 \n\
+-        lbu     r3, r6, r9                  \n\
+-        sb      r3, r5, r9                  \n\
+-        addlik   r10, r10, -1                \n\
+-        beaeqid   r3, end_cpy             /* Break if we have seen null character */\n\
+-	nop					\n\
+-        addlik   r9, r9, 1                   \n\
+-        beaneid   r10, align_loop             \n\
+-	nop					\n\
+-        breai     cpy_loop                    \n\
+-regular_strcpy:                             \n\
+-        lbu     r3, r6, r9                  \n\
+-        sb      r3, r5, r9                  \n\
+-        addlik   r9, r9, 1                   \n\
+-        beaneid   r3, regular_strcpy          \n\
+-	nop					\n\
+-end_cpy:                                    \n\
+-        orl      r3, r0, r5  			\n\
+-        rtsd    r15, 8                      \n\
+-	nop			 /* Return strcpy result */");
++      dst = (char*)aligned_dst;
++      src = (char*)aligned_src;
++    }
+ 
+-#else
++  while (*dst++ = *src++)
++    ;
++  return dst0;
++
++#else    
+ 
++#include "mb_endian.h"
+   asm volatile ("                                                   \n\
+         or      r9, r0, r0              /* Index register */        \n\
+ check_alignment:                                                    \n\
+@@ -227,7 +196,6 @@ regular_strcpy:                             \n\
+ end_cpy:                                    \n\
+         rtsd    r15, 8                      \n\
+         or      r3, r0, r5              /* Return strcpy result */");
+-#endif
+ #endif /* ! HAVE_HW_PCMP */
+ }
+ 
+diff --git a/newlib/libc/machine/microblaze/strlen.c b/newlib/libc/machine/microblaze/strlen.c
+index b6f2d3c13..940753996 100644
+--- a/newlib/libc/machine/microblaze/strlen.c
++++ b/newlib/libc/machine/microblaze/strlen.c
+@@ -112,47 +112,29 @@ strlen (const char *str)
+   return str - start;
+ #endif /* not PREFER_SIZE_OVER_SPEED */
+ 
+-#else
+-
+-#include "mb_endian.h"
++#elif __arch64__
++  const char *start = str;
++  unsigned long *aligned_addr;
+ 
+-#ifdef __arch64__
+-  asm volatile ("                                               \n\
+-        orl      r9, r0, r0              /* Index register */    \n\
+-check_alignment:                                                \n\
+-        andli    r3, r5, 3                                       \n\
+-        beanei    r3, align_arg                                   \n\
+-len_loop:                                                       \n"
+-        LOAD4BYTES("r3", "r5", "r9")
+-"                                                               \n\
+-        pcmplbf  r4, r3, r0                                      \n\
+-        beanei    r4, end_len                                     \n\
+-        addlik   r9, r9, 4                                       \n\
+-        breaid    len_loop                                        \n\
+-        nop		                                        \n\
+-end_len:                                                        \n\
+-        lbu     r3, r5, r9                                      \n\
+-        beaeqi    r3, done_len                                    \n\
+-        addlik   r9, r9, 1                                       \n\
+-        breaid    end_len                                         \n\
+-        nop		                                       \n\
+-done_len:                                                       \n\
+-        orl      r3, r0, r9              /* Return len */        \n\
+-        rtsd    r15, 8                                          \n\
+-        nop						        \n\
+-align_arg:                                                      \n\
+-        rsublik  r10, r3, 4                                      \n\
+-align_loop:                                                     \n\
+-        lbu     r3, r5, r9                                      \n\
+-        addlik   r10, r10, -1                                    \n\
+-        beaeqid   r3, done_len                                    \n\
+-        nop		                                       \n\
+-        addlik   r9, r9, 1                                       \n\
+-        beaneid   r10, align_loop                                 \n\
+-        nop		                                        \n\
+-        breai     len_loop");
++  if (!UNALIGNED (str))
++    {
++      /* If the string is word-aligned, we can check for the presence of 
++         a null in each word-sized block.  */
++      aligned_addr = (unsigned long*)str;
++      while (!DETECTNULL (*aligned_addr))
++        aligned_addr++;
+ 
++      /* Once a null is detected, we check each byte in that block for a
++         precise position of the null.  */
++      str = (char*)aligned_addr;
++    }
++ 
++  while (*str)
++    str++;
++  return str - start;
+ #else
++
++#include "mb_endian.h"
+   asm volatile ("                                               \n\
+         or      r9, r0, r0              /* Index register */    \n\
+ check_alignment:                                                \n\
+@@ -183,6 +165,5 @@ align_loop:                                                     \n\
+         addik   r9, r9, 1                                       \n\
+         bri     len_loop");
+ 
+-#endif
+ #endif  /* ! HAVE_HW_PCMP */
+ }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch
new file mode 100644
index 0000000000..b6e03d42b8
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch
@@ -0,0 +1,25 @@
+From e0e6f5367eede4292d31c3dd901425bcd251595a Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Tue, 14 Jan 2020 22:32:30 +0530
+Subject: [PATCH 11/11] Fixed the bug in crtinit.s for MB-64
+
+---
+ libgloss/microblaze/crtinit.S | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/libgloss/microblaze/crtinit.S b/libgloss/microblaze/crtinit.S
+index 854117536..f79140734 100644
+--- a/libgloss/microblaze/crtinit.S
++++ b/libgloss/microblaze/crtinit.S
+@@ -48,7 +48,7 @@ _crtinit:
+ 
+ .Lloopsbss:	
+ 	sli	r0, r6, 0
+-	addli	r6, r6, 4
++	addli	r6, r6, 8
+ 	rsubl	r18, r6, r7
+ 	beagti	r18, .Lloopsbss
+ .Lendsbss:
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Removing-the-Assembly-implementation-of-64bit-string.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Removing-the-Assembly-implementation-of-64bit-string.patch
deleted file mode 100644
index c8d13af008..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0011-Removing-the-Assembly-implementation-of-64bit-string.patch
+++ /dev/null
@@ -1,332 +0,0 @@
-From b35b582ef3f6575447097585174302fde1761078 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Wed, 24 Apr 2019 23:29:21 +0530
-Subject: [PATCH 11/11] Removing the Assembly implementation of 64bit string
- function. Revisit in next release and fix it
-
----
- newlib/libc/machine/microblaze/mb_endian.h |  4 ++
- newlib/libc/machine/microblaze/strcmp.c    | 93 ++++++++++--------------------
- newlib/libc/machine/microblaze/strcpy.c    | 82 ++++++++------------------
- newlib/libc/machine/microblaze/strlen.c    | 59 +++++++------------
- 4 files changed, 81 insertions(+), 157 deletions(-)
-
-diff --git a/newlib/libc/machine/microblaze/mb_endian.h b/newlib/libc/machine/microblaze/mb_endian.h
-index fb217ec..17772c8 100644
---- a/newlib/libc/machine/microblaze/mb_endian.h
-+++ b/newlib/libc/machine/microblaze/mb_endian.h
-@@ -8,8 +8,12 @@
- #ifdef __LITTLE_ENDIAN__
- #define LOAD4BYTES(rD,rA,rB)   "\tlwr\t" rD ", " rA ", " rB "\n"
- #define STORE4BYTES(rD,rA,rB)  "\tswr\t" rD ", " rA ", " rB "\n"
-+#define LOAD8BYTES(rD,rA,rB)   "\tllr\t" rD ", " rA ", " rB "\n"
-+#define STORE8BYTES(rD,rA,rB)  "\tslr\t" rD ", " rA ", " rB "\n"
- #else
- #define LOAD4BYTES(rD,rA,rB)   "\tlw\t" rD ", " rA ", " rB "\n"
- #define STORE4BYTES(rD,rA,rB)  "\tsw\t" rD ", " rA ", " rB "\n"
-+#define LOAD8BYTES(rD,rA,rB)   "\tll\t" rD ", " rA ", " rB "\n"
-+#define STORE8BYTES(rD,rA,rB)  "\tsl\t" rD ", " rA ", " rB "\n"
- #endif
- #endif
-diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
-index acfe4cd..e34c64a 100644
---- a/newlib/libc/machine/microblaze/strcmp.c
-+++ b/newlib/libc/machine/microblaze/strcmp.c
-@@ -129,70 +129,42 @@ strcmp (const char *s1,
-   return (*(unsigned char *) s1) - (*(unsigned char *) s2);
- #endif /* not PREFER_SIZE_OVER_SPEED */
- 
-+#elif __arch64__
-+  unsigned int *a1;
-+  unsigned int *a2;
-+
-+  /* If s1 or s2 are unaligned, then compare bytes. */
-+  if (!UNALIGNED (s1, s2))
-+    {  
-+      /* If s1 and s2 are word-aligned, compare them a word at a time. */
-+      a1 = (unsigned int*)s1;
-+      a2 = (unsigned int*)s2;
-+      while (*a1 == *a2)
-+        {
-+          /* To get here, *a1 == *a2, thus if we find a null in *a1,
-+	     then the strings must be equal, so return zero.  */
-+          if (DETECTNULL (*a1))
-+	    return 0;
-+
-+          a1++;
-+          a2++;
-+        }
-+
-+      /* A difference was detected in last few bytes of s1, so search bytewise */
-+      s1 = (char*)a1;
-+      s2 = (char*)a2;
-+    }
-+
-+  while (*s1 != '\0' && *s1 == *s2)
-+    {
-+      s1++;
-+      s2++;
-+    }
-+  return (*(unsigned char *) s1) - (*(unsigned char *) s2);
- #else
- 
- #include "mb_endian.h"
- 
--#ifdef __arch64__
--    asm volatile ("                                          \n\
--        orl      r9, r0, r0               /* Index register */ \n\
--check_alignment:                                             \n\
--        andli    r3, r5, 3                                    \n\
--        andli    r4, r6, 3                                    \n\
--        beanei    r3, try_align_args                           \n\
--        beanei    r4, regular_strcmp     /* At this point we don't have a choice */ \n\
--cmp_loop:                                                                       \n"
--        LOAD4BYTES("r3", "r5", "r9")
--        LOAD4BYTES("r4", "r6", "r9")
--"                                                                                      \n\
--        pcmplbf  r7, r3, r0              /* See if there is Null byte */                         \n\
--        beanei    r7, end_cmp_loop        /* IF yes (r7 > 0) use byte compares in end_cmp_loop */ \n\
--        cmplu    r7, r4, r3              /* ELSE compare whole word */                   \n\
--        beanei    r7, end_cmp                                                             \n\
--        addlik   r9, r9, 4               /* delay slot */                                \n\
--        breaid    cmp_loop                                                                \n\
--        nop		               /* delay slot */                                \n\
--end_cmp_loop:                                                                           \n\
--        lbu     r3, r5, r9              /* byte compare loop */                         \n\
--        lbu     r4, r6, r9                                                              \n\
--        cmplu    r7, r4, r3              /* Compare bytes */                             \n\
--        beanei    r7, end_cmp_early                                                       \n\
--        addlik   r9, r9, 1               /* delay slot */                        \n\
--        beaneid   r3, end_cmp_loop        /* If reached null on one string, terminate */  \n\
--        nop					                              \n\
--end_cmp_early:                                                                  \n\
--        orl   r3, r0, r7               /* delay slot */                        \n\
--        rtsd    r15, 8                                                          \n\
--        nop		                                                         \n\
--try_align_args:                                                                 \n\
--        xorl     r7, r4, r3                                                      \n\
--        beanei    r7, regular_strcmp      /* cannot align args */                 \n\
--        rsublik  r10, r3, 4              /* Number of initial bytes to align */  \n\
--align_loop:                                                                     \n\
--        lbu     r3, r5, r9                                                      \n\
--        lbu     r4, r6, r9                                                      \n\
--        cmplu    r7, r4, r3                                                      \n\
--        beanei    r7, end_cmp                                                     \n\
--        beaeqi    r3, end_cmp                                                     \n\
--        addlik   r10, r10, -1                                                    \n\
--        addlik   r9, r9, 1                                                       \n\
--        beaeqid   r10, cmp_loop                                                   \n\
--        nop		                                                           \n\
--        breai     align_loop                                                      \n\
--regular_strcmp:                                                                 \n\
--        lbu     r3, r5, r9                                                      \n\
--        lbu     r4, r6, r9                                                      \n\
--        cmplu    r7, r4, r3                                                      \n\
--        beanei    r7, end_cmp                                                     \n\
--        beaeqi    r3, end_cmp                                                     \n\
--        addlik   r9, r9, 1                                                       \n\
--        breaid    regular_strcmp                                                  \n\
--        nop                                                  \n\
--end_cmp:                                                                        \n\
--        orl       r3, r0, r7                                                       \n\
--        rtsd    r15, 8                                                          \n\
--        nop              /* Return strcmp result */");
--#else
-     asm volatile ("                                          \n\
-         or      r9, r0, r0               /* Index register */\n\
- check_alignment:                                             \n\
-@@ -246,7 +218,6 @@ end_cmp:
-         rtsd    r15, 8                                                          \n\
-         or      r3, r0, r7              /* Return strcmp result */");
- 
--#endif
- #endif /* ! HAVE_HW_PCMP */
- }
- 
-diff --git a/newlib/libc/machine/microblaze/strcpy.c b/newlib/libc/machine/microblaze/strcpy.c
-index 6dbc60d..ddb6922 100644
---- a/newlib/libc/machine/microblaze/strcpy.c
-+++ b/newlib/libc/machine/microblaze/strcpy.c
-@@ -121,67 +121,36 @@ strcpy (char *__restrict dst0,
-     ;
-   return dst0;
- #endif /* not PREFER_SIZE_OVER_SPEED */
-+#elif __arch64__
-+  char *dst = dst0;
-+  const char *src = src0;
-+  long *aligned_dst;
-+  const long *aligned_src;
- 
--#else    
-+  /* If SRC or DEST is unaligned, then copy bytes.  */
-+  if (!UNALIGNED (src, dst))
-+    {
-+      aligned_dst = (long*)dst;
-+      aligned_src = (long*)src;
- 
--#include "mb_endian.h"
--#ifdef __arch64__
-+      /* SRC and DEST are both "long int" aligned, try to do "long int"
-+         sized copies.  */
-+      while (!DETECTNULL(*aligned_src))
-+        {
-+          *aligned_dst++ = *aligned_src++;
-+        }
- 
--  asm volatile ("                                                   \n\
--        orl      r9, r0, r0              /* Index register */        \n\
--check_alignment:                                                    \n\
--        andli    r3, r5, 3                                           \n\
--        andli    r4, r6, 3                                           \n\
--        beanei    r3, try_align_args                                  \n\
--        beanei    r4, regular_strcpy      /* At this point we dont have a choice */       \n\
--cpy_loop:                                   \n"
--        LOAD4BYTES("r3", "r6", "r9")
--"                                           \n\
--        pcmplbf  r4, r0, r3                  \n\
--        beanei    r4, cpy_bytes           /* If r4 != 0, then null present within string */\n"
--        STORE4BYTES("r3", "r5", "r9")
--"                                           \n\
--        addlik   r9, r9, 4                   \n\
--        breaid    cpy_loop                    \n\
--	nop					\n\
--cpy_bytes:                                  \n\
--        lbu     r3, r6, r9                  \n\
--        sb      r3, r5, r9                  \n\
--        addlik   r4, r4, -1                  \n\
--        addlik   r9, r9, 1               /* delay slot */\n\
--        beaneid   r4, cpy_bytes               \n\
--	nop					\n\
--cpy_null:                                   \n\
--        orl      r3, r0, r5              /* Return strcpy result */\n\
--        rtsd    r15, 8                      \n\
--	nop					\n\
--try_align_args:                             \n\
--        xorl     r7, r4, r3                  \n\
--        beanei    r7, regular_strcpy      /* cannot align args */\n\
--        rsublik  r10, r3, 4              /* Number of initial bytes to align */\n\
--align_loop:                                 \n\
--        lbu     r3, r6, r9                  \n\
--        sb      r3, r5, r9                  \n\
--        addlik   r10, r10, -1                \n\
--        beaeqid   r3, end_cpy             /* Break if we have seen null character */\n\
--	nop					\n\
--        addlik   r9, r9, 1                   \n\
--        beaneid   r10, align_loop             \n\
--	nop					\n\
--        breai     cpy_loop                    \n\
--regular_strcpy:                             \n\
--        lbu     r3, r6, r9                  \n\
--        sb      r3, r5, r9                  \n\
--        addlik   r9, r9, 1                   \n\
--        beaneid   r3, regular_strcpy          \n\
--	nop					\n\
--end_cpy:                                    \n\
--        orl      r3, r0, r5  			\n\
--        rtsd    r15, 8                      \n\
--	nop			 /* Return strcpy result */");
-+      dst = (char*)aligned_dst;
-+      src = (char*)aligned_src;
-+    }
- 
--#else
-+  while (*dst++ = *src++)
-+    ;
-+  return dst0;
-+
-+#else    
- 
-+#include "mb_endian.h"
-   asm volatile ("                                                   \n\
-         or      r9, r0, r0              /* Index register */        \n\
- check_alignment:                                                    \n\
-@@ -227,7 +196,6 @@ regular_strcpy:                             \n\
- end_cpy:                                    \n\
-         rtsd    r15, 8                      \n\
-         or      r3, r0, r5              /* Return strcpy result */");
--#endif
- #endif /* ! HAVE_HW_PCMP */
- }
- 
-diff --git a/newlib/libc/machine/microblaze/strlen.c b/newlib/libc/machine/microblaze/strlen.c
-index b6f2d3c..9407539 100644
---- a/newlib/libc/machine/microblaze/strlen.c
-+++ b/newlib/libc/machine/microblaze/strlen.c
-@@ -112,47 +112,29 @@ strlen (const char *str)
-   return str - start;
- #endif /* not PREFER_SIZE_OVER_SPEED */
- 
--#else
--
--#include "mb_endian.h"
-+#elif __arch64__
-+  const char *start = str;
-+  unsigned long *aligned_addr;
- 
--#ifdef __arch64__
--  asm volatile ("                                               \n\
--        orl      r9, r0, r0              /* Index register */    \n\
--check_alignment:                                                \n\
--        andli    r3, r5, 3                                       \n\
--        beanei    r3, align_arg                                   \n\
--len_loop:                                                       \n"
--        LOAD4BYTES("r3", "r5", "r9")
--"                                                               \n\
--        pcmplbf  r4, r3, r0                                      \n\
--        beanei    r4, end_len                                     \n\
--        addlik   r9, r9, 4                                       \n\
--        breaid    len_loop                                        \n\
--        nop		                                        \n\
--end_len:                                                        \n\
--        lbu     r3, r5, r9                                      \n\
--        beaeqi    r3, done_len                                    \n\
--        addlik   r9, r9, 1                                       \n\
--        breaid    end_len                                         \n\
--        nop		                                       \n\
--done_len:                                                       \n\
--        orl      r3, r0, r9              /* Return len */        \n\
--        rtsd    r15, 8                                          \n\
--        nop						        \n\
--align_arg:                                                      \n\
--        rsublik  r10, r3, 4                                      \n\
--align_loop:                                                     \n\
--        lbu     r3, r5, r9                                      \n\
--        addlik   r10, r10, -1                                    \n\
--        beaeqid   r3, done_len                                    \n\
--        nop		                                       \n\
--        addlik   r9, r9, 1                                       \n\
--        beaneid   r10, align_loop                                 \n\
--        nop		                                        \n\
--        breai     len_loop");
-+  if (!UNALIGNED (str))
-+    {
-+      /* If the string is word-aligned, we can check for the presence of 
-+         a null in each word-sized block.  */
-+      aligned_addr = (unsigned long*)str;
-+      while (!DETECTNULL (*aligned_addr))
-+        aligned_addr++;
- 
-+      /* Once a null is detected, we check each byte in that block for a
-+         precise position of the null.  */
-+      str = (char*)aligned_addr;
-+    }
-+ 
-+  while (*str)
-+    str++;
-+  return str - start;
- #else
-+
-+#include "mb_endian.h"
-   asm volatile ("                                               \n\
-         or      r9, r0, r0              /* Index register */    \n\
- check_alignment:                                                \n\
-@@ -183,6 +165,5 @@ align_loop:                                                     \n\
-         addik   r9, r9, 1                                       \n\
-         bri     len_loop");
- 
--#endif
- #endif  /* ! HAVE_HW_PCMP */
- }
--- 
-2.7.4
-
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0012-libc-machine-microblaze-strcmp.c-Fix-missing-end-of-.patch b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0012-libc-machine-microblaze-strcmp.c-Fix-missing-end-of-.patch
new file mode 100644
index 0000000000..c92942fc2a
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/files/0012-libc-machine-microblaze-strcmp.c-Fix-missing-end-of-.patch
@@ -0,0 +1,26 @@
+From c2a8d7e6326a309221e4a287517a4920d33aa674 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Mon, 30 Nov 2020 18:26:47 -0800
+Subject: [PATCH] libc/machine/microblaze/strcmp.c: Fix missing end of line
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ newlib/libc/machine/microblaze/strcmp.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/newlib/libc/machine/microblaze/strcmp.c b/newlib/libc/machine/microblaze/strcmp.c
+index 007d9e1eb..5d13d64ab 100644
+--- a/newlib/libc/machine/microblaze/strcmp.c
++++ b/newlib/libc/machine/microblaze/strcmp.c
+@@ -212,7 +212,7 @@ regular_strcmp:
+         bnei    r7, end_cmp                                                     \n\
+         beqi    r3, end_cmp                                                     \n\
+         brid    regular_strcmp                                                  \n\
+-        addik	r9, r9, 1
++        addik   r9, r9, 1                                                       \n\
+ end_cmp:                                                                        \n\
+         rtsd    r15, 8                                                          \n\
+         or      r3, r0, r7              /* Return strcmp result */");
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-core/newlib/microblaze-newlib.inc b/meta-xilinx/meta-microblaze/recipes-core/newlib/microblaze-newlib.inc
index c3b6acdc2e..1a4a90adf9 100644
--- a/meta-xilinx/meta-microblaze/recipes-core/newlib/microblaze-newlib.inc
+++ b/meta-xilinx/meta-microblaze/recipes-core/newlib/microblaze-newlib.inc
@@ -1,15 +1,16 @@
 # Add MicroBlaze Patches
 FILESEXTRAPATHS_append_microblaze := ":${THISDIR}/files"
 SRC_URI_append_microblaze = " \
-        file://0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch \
-        file://0002-Patch-microblaze-Modified-_exceptional_handler.patch \
-        file://0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch \
-        file://0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch \
-        file://0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch \
-        file://0006-MB-X-intial-commit.patch \
-        file://0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch \
-        file://0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch \
-        file://0009-Added-MB-64-support-to-strcmp-strcpy-strlen-files.patch \
-        file://0010-Patch-MicroBlaze-typos-in-string-functions-microblaz.patch \
-        file://0011-Removing-the-Assembly-implementation-of-64bit-string.patch \
-        "
+    file://0001-Patch-microblaze-Add-config-microblaze.mt-for-target.patch \
+    file://0002-Patch-microblaze-Modified-_exceptional_handler.patch \
+    file://0003-LOCAL-Add-missing-declarations-for-xil_printf-to-std.patch \
+    file://0004-Local-deleting-the-xil_printf.c-file-as-now-it-part-.patch \
+    file://0005-Local-deleting-the-xil_printf.o-from-MAKEFILE.patch \
+    file://0006-MB-X-intial-commit.patch \
+    file://0007-Patch-Microblaze-newlib-port-for-microblaze-m64-flag.patch \
+    file://0008-fixing-the-bug-in-crt-files-added-addlik-instead-of-.patch \
+    file://0009-Patch-MicroBlaze-Added-MB-64-support-to-strcmp-strcp.patch \
+    file://0010-Removing-the-Assembly-implementation-of-64bit-string.patch \
+    file://0011-Fixed-the-bug-in-crtinit.s-for-MB-64.patch \
+    file://0012-libc-machine-microblaze-strcmp.c-Fix-missing-end-of-.patch \
+    "
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
index e10c34ffd9..c1a7bb4c45 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils-microblaze.inc
@@ -1,44 +1,64 @@
 FILESEXTRAPATHS_append := ":${THISDIR}/binutils"
 
 SRC_URI_append = " \
-     file://0001-sim-Allow-microblaze-architecture.patch \
-     file://0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
-     file://0003-Add-mlittle-endian-and-mbig-endian-flags.patch \
-     file://0004-Disable-the-warning-message-for-eh_frame_hdr.patch \
-     file://0005-Fix-relaxation-of-assembler-resolved-references.patch \
-     file://0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch \
-     file://0007-upstream-change-to-garbage-collection-sweep-causes-m.patch \
-     file://0008-Fix-bug-in-TLSTPREL-Relocation.patch \
-     file://0009-Added-Address-extension-instructions.patch \
-     file://0010-Add-new-bit-field-instructions.patch \
-     file://0011-fixing-the-imm-bug.patch \
-     file://0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch \
-     file://0013-fixing-the-constant-range-check-issue.patch \
-     file://0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch \
-     file://0015-intial-commit-of-MB-64-bit.patch \
-     file://0016-MB-X-initial-commit.patch \
-     file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
-     file://0018-Added-relocations-for-MB-X.patch \
-     file://0019-Update-MB-x.patch \
-     file://0020-Various-fixes.patch \
+     file://0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+     file://0002-Add-mlittle-endian-and-mbig-endian-flags.patch \
+     file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
+     file://0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch \
+     file://0005-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+     file://0006-Fix-bug-in-TLSTPREL-Relocation.patch \
+     file://0007-Added-Address-extension-instructions.patch \
+     file://0008-fixing-the-MAX_OPCODES-to-correct-value.patch \
+     file://0009-Add-new-bit-field-instructions.patch \
+     file://0010-fixing-the-imm-bug.patch \
+     file://0011-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch \
+     file://0012-fixing-the-constant-range-check-issue.patch \
+     file://0013-Patch-Microblaze-Compiler-will-give-error-messages-i.patch \
+     file://0014-intial-commit-of-MB-64-bit.patch \
+     file://0015-MB-X-initial-commit.patch \
+     file://0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
+     file://0017-Added-relocations-for-MB-X.patch \
+     file://0018-Fixed-MB-x-relocation-issues.patch \
+     file://0019-Fixing-the-branch-related-issues.patch \
+     file://0020-Fixed-address-computation-issues-with-64bit-address.patch \
      file://0021-Adding-new-relocation-to-support-64bit-rodata.patch \
      file://0022-fixing-the-.bss-relocation-issue.patch \
      file://0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
      file://0024-Revert-ld-Remove-unused-expression-state.patch \
-     file://0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch \
-     file://0026-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-     file://0027-Added-support-to-new-arithmetic-single-register-inst.patch \
-     file://0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
-     file://0029-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch \
-     file://0030-Patch-MicroBlaze-m64-Update-imml-instructions-for-Ty.patch \
-     file://0031-ldlang.c-Workaround-for-improper-address-mapping-cau.patch \
-     file://0032-gas-revert-moving-of-md_pseudo_table-from-const.patch \
-     file://0033-Fix-various-compile-warnings.patch \
-     file://0034-Add-initial-port-of-linux-gdbserver.patch \
-     file://0035-Initial-port-of-core-reading-support.patch \
-     file://0036-Fix-debug-message-when-register-is-unavailable.patch \
-     file://0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
-     file://0038-Initial-support-for-native-gdb.patch \
-     file://0039-Fixing-the-issues-related-to-GDB-7.12.patch \
-     file://0040-Patch-microblaze-Adding-64-bit-MB-support.patch \
+     file://0025-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+     file://0026-Added-support-to-new-arithmetic-single-register-inst.patch \
+     file://0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
+     file://0028-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch \
+     file://0029-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch \
+     file://0030-Patch-MicroBlaze-improper-address-mapping-of-PROVIDE.patch \
+     file://0031-gas-revert-moving-of-md_pseudo_table-from-const.patch \
+     file://0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \
+     file://0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+     file://0034-Initial-port-of-core-reading-support-Added-support-f.patch \
+     file://0035-Fix-debug-message-when-register-is-unavailable.patch \
+     file://0036-revert-master-rebase-changes-to-gdbserver.patch \
+     file://0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch \
+     file://0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
+     file://0039-Initial-support-for-native-gdb.patch \
+     file://0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch \
+     file://0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \
+     file://0042-porting-GDB-for-linux.patch \
+     file://0043-Binutils-security-check-is-causing-build-error-for-w.patch \
+     file://0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch \
+     file://0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch \
+     file://0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch \
+     file://0047-bfd-elf64-microblaze.c-Fix-build-failures.patch \
+     file://0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch \
+     file://0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch \
+     file://0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch \
+     file://0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch \
+     file://0052-sim-Allow-microblaze-architecture.patch \
+     file://0053-gdb-Fix-microblaze-target-compilation.patch \
      "
+
+#
+##     file://0048-bfd-gas-Use-standard-method-to-set-the-machine-arch.patch \
+##     file://0052-opcodes-microblaze-opc.h-Expand-the-size-to-int-to-d.patch \
+##     file://0053-opcodes-microblaze-opc.h-MIN_IMML-is-too-large.patch \
+##     file://0054-gas-config-tc-microblaze.c-Resolve-numerous-compiler.patch \
+#
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000000..fe3f2bff05
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From 212bd1115f13cc0904fb5556751585c775bc51a6 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: [PATCH 01/52] Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ opcodes/microblaze-opc.h  | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 27d8684df0..b6c5016e4d 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+ 
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index aa53dfe6bb..795c57b5ff 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-sim-Allow-microblaze-architecture.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-sim-Allow-microblaze-architecture.patch
deleted file mode 100644
index 9671968a1e..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0001-sim-Allow-microblaze-architecture.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 501b60af6b36fc69987e1610645742f5593a6da2 Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Thu, 6 Aug 2020 15:37:52 -0500
-Subject: [PATCH 01/40] sim: Allow microblaze* architecture
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- sim/configure     | 2 +-
- sim/configure.tgt | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/sim/configure b/sim/configure
-index 72f95cd5c7a..9e28cc78687 100755
---- a/sim/configure
-+++ b/sim/configure
-@@ -3795,7 +3795,7 @@ subdirs="$subdirs aarch64"
- 
- 
-        ;;
--   microblaze-*-*)
-+   microblaze*-*-*)
- 
-   sim_arch=microblaze
-   subdirs="$subdirs microblaze"
-diff --git a/sim/configure.tgt b/sim/configure.tgt
-index 8a8e03d96f4..f6743fe8d41 100644
---- a/sim/configure.tgt
-+++ b/sim/configure.tgt
-@@ -59,7 +59,7 @@ case "${target}" in
-    mcore-*-*)
-        SIM_ARCH(mcore)
-        ;;
--   microblaze-*-*)
-+   microblaze*-*-*)
-        SIM_ARCH(microblaze)
-        ;;
-    mips*-*-*)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
new file mode 100644
index 0000000000..78f4be14f3
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-mlittle-endian-and-mbig-endian-flags.patch
@@ -0,0 +1,64 @@
+From 23ed5e7ab73a2b5dc1ca09362d4815a643a2d187 Mon Sep 17 00:00:00 2001
+From: nagaraju <nmekala@xilix.com>
+Date: Tue, 19 Mar 2013 17:18:23 +0530
+Subject: [PATCH 02/52] Add mlittle-endian and mbig-endian flags
+
+Added support in gas for mlittle-endian and mbig-endian flags
+as options.
+
+Updated show usage for MicroBlaze specific assembler options
+to include new entries.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gas/config/tc-microblaze.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index ae5d36dc9c..34eeb97235 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -37,6 +37,8 @@
+ 
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
++#define OPTION_LITTLE (OPTION_MD_BASE + 2)
++#define OPTION_BIG (OPTION_MD_BASE + 3)
+ 
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -1842,6 +1844,8 @@ struct option md_longopts[] =
+ {
+   {"EB", no_argument, NULL, OPTION_EB},
+   {"EL", no_argument, NULL, OPTION_EL},
++  {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
++  {"mbig-endian", no_argument, NULL, OPTION_BIG},
+   { NULL,          no_argument, NULL, 0}
+ };
+ 
+@@ -2494,9 +2498,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+   switch (c)
+     {
+     case OPTION_EB:
++    case OPTION_BIG:
+       target_big_endian = 1;
+       break;
+     case OPTION_EL:
++    case OPTION_LITTLE:
+       target_big_endian = 0;
+       break;
+     default:
+@@ -2511,6 +2517,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+   /*  fprintf(stream, _("\
+       MicroBlaze options:\n\
+       -noSmall         Data in the comm and data sections do not go into the small data section\n")); */
++  fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
++  fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
++  fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
+ }
+ 
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
deleted file mode 100644
index 039bfc9649..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From b8e39d2a6b83d0f0a14d4bfeafd47a37d746f159 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Wed, 8 May 2013 11:03:36 +1000
-Subject: [PATCH 02/40] Add wdc.ext.clear and wdc.ext.flush insns
-
-Added two new instructions, wdc.ext.clear and wdc.ext.flush,
-to enable MicroBlaze to flush an external cache, which is
-used with the new coherency support for multiprocessing.
-
-Signed-off-by:nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- opcodes/microblaze-opc.h  | 5 ++++-
- opcodes/microblaze-opcm.h | 4 ++--
- 2 files changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 27d8684df04..b6c5016e4d2 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -91,6 +91,7 @@
- #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
-+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
- 
- /* New Mask for msrset, msrclr insns.  */
-@@ -101,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 289
-+#define MAX_OPCODES 291
- 
- struct op_code_struct
- {
-@@ -174,7 +175,9 @@ struct op_code_struct
-   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
-   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
-   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
-+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
-   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index aa53dfe6bb5..795c57b5ff6 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,8 +33,8 @@ enum microblaze_instr
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
--  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
-+  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Add-mlittle-endian-and-mbig-endian-flags.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Add-mlittle-endian-and-mbig-endian-flags.patch
deleted file mode 100644
index 2d4d65e446..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Add-mlittle-endian-and-mbig-endian-flags.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From d2a03159f8643b1c6a2db5d95c478540cc6ca6c4 Mon Sep 17 00:00:00 2001
-From: nagaraju <nmekala@xilix.com>
-Date: Tue, 19 Mar 2013 17:18:23 +0530
-Subject: [PATCH 03/40] Add mlittle-endian and mbig-endian flags
-
-Added support in gas for mlittle-endian and mbig-endian flags
-as options.
-
-Updated show usage for MicroBlaze specific assembler options
-to include new entries.
-
-Signed-off-by:nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gas/config/tc-microblaze.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index ae5d36dc9c3..34eeb972357 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -37,6 +37,8 @@
- 
- #define OPTION_EB (OPTION_MD_BASE + 0)
- #define OPTION_EL (OPTION_MD_BASE + 1)
-+#define OPTION_LITTLE (OPTION_MD_BASE + 2)
-+#define OPTION_BIG (OPTION_MD_BASE + 3)
- 
- void microblaze_generate_symbol (char *sym);
- static bfd_boolean check_spl_reg (unsigned *);
-@@ -1842,6 +1844,8 @@ struct option md_longopts[] =
- {
-   {"EB", no_argument, NULL, OPTION_EB},
-   {"EL", no_argument, NULL, OPTION_EL},
-+  {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
-+  {"mbig-endian", no_argument, NULL, OPTION_BIG},
-   { NULL,          no_argument, NULL, 0}
- };
- 
-@@ -2494,9 +2498,11 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
-   switch (c)
-     {
-     case OPTION_EB:
-+    case OPTION_BIG:
-       target_big_endian = 1;
-       break;
-     case OPTION_EL:
-+    case OPTION_LITTLE:
-       target_big_endian = 0;
-       break;
-     default:
-@@ -2511,6 +2517,9 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
-   /*  fprintf(stream, _("\
-       MicroBlaze options:\n\
-       -noSmall         Data in the comm and data sections do not go into the small data section\n")); */
-+  fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
-+  fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
-+  fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
- }
- 
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000000..96ddefa068
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,31 @@
+From f74d7754befd636c6139261e6c6b23ed49aa0fa9 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 03/52] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+---
+ bfd/elf-eh-frame.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
+index 7a129b00f8..d5e4a5c062 100644
+--- a/bfd/elf-eh-frame.c
++++ b/bfd/elf-eh-frame.c
+@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
+   goto success;
+ 
+  free_no_table:
++/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
++if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+   _bfd_error_handler
+     /* xgettext:c-format */
+     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
+      abfd, sec);
++}
+   hdr_info->u.dwarf.table = FALSE;
+   free (sec_info);
+  success:
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
deleted file mode 100644
index f7b9c7b052..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From a8d621e5ab335e6e61de0f081036b4705071fb74 Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
-Date: Fri, 22 Jun 2012 01:20:20 +0200
-Subject: [PATCH 04/40] Disable the warning message for eh_frame_hdr
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- bfd/elf-eh-frame.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
-index 7a129b00f8d..d5e4a5c062d 100644
---- a/bfd/elf-eh-frame.c
-+++ b/bfd/elf-eh-frame.c
-@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
-   goto success;
- 
-  free_no_table:
-+/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
-+if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
-   _bfd_error_handler
-     /* xgettext:c-format */
-     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
-      abfd, sec);
-+}
-   hdr_info->u.dwarf.table = FALSE;
-   free (sec_info);
-  success:
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
new file mode 100644
index 0000000000..a63ad020c2
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
@@ -0,0 +1,304 @@
+From 6aadc146948741df27125cc2253ba9a50efa5cfc Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 8 Nov 2016 11:54:08 +0530
+Subject: [PATCH 04/52] [LOCAL]: Fix relaxation of assembler resolved
+ references,Fixup debug_loc sections after linker relaxation Adds a new
+ reloctype R_MICROBLAZE_32_NONE, used for passing reloc info from the
+ assembler to the linker when the linker manages to fully resolve a local
+ symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+	bfd/elf32-microblaze.c
+	binutils/readelf.c
+	include/elf/microblaze.h
+---
+ bfd/bfd-in2.h              |   5 ++
+ bfd/elf32-microblaze.c     | 126 ++++++++++++++++++++++++++++---------
+ bfd/libbfd.h               |   1 +
+ bfd/reloc.c                |   6 ++
+ binutils/readelf.c         |   4 ++
+ gas/config/tc-microblaze.c |   4 ++
+ include/elf/microblaze.h   |   2 +
+ 7 files changed, 119 insertions(+), 29 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 35ef4d755b..1bd19a2b63 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5428,6 +5428,11 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).No relocation is 
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 693fc71f73..e9715eae6a 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 	  FALSE),		/* PC relative offset?  */
+ 
+    /* This reloc does nothing.	Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
+    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+ 	  3,			/* Size (0 = byte, 1 = short, 2 = long).  */
+@@ -562,7 +576,10 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64_NONE:
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
++     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+     case BFD_RELOC_32:
+@@ -1914,18 +1931,26 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		}
+ 	      break;
+ 	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
+ 	      {
+ 		/* This was a PC-relative instruction that was
+ 		   completely resolved.  */
+ 		int sfix, efix;
++                unsigned int val;
+ 		bfd_vma target_address;
+ 		target_address = irel->r_addend + irel->r_offset;
+ 		sfix = calc_fixup (irel->r_offset, 0, sec);
+ 		efix = calc_fixup (target_address, 0, sec);
+-		irel->r_addend -= (efix - sfix);
+-		/* Should use HOWTO.  */
+-		microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+-						   irel->r_addend);
++
++                /* Validate the in-band val.  */
++                val = bfd_get_32 (abfd, contents + irel->r_offset);
++                if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++                }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
+ 	      }
+ 	      break;
+ 	    case R_MICROBLAZE_64_NONE:
+@@ -1969,30 +1994,73 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	  irelscanend = irelocs + o->reloc_count;
+ 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ 	    {
+-	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+-		{
+-		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++              if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++		      if (elf_section_data (o)->this_hdr.contents != NULL)
++		          ocontents = elf_section_data (o)->this_hdr.contents;
++		      else
++		        {
++		          /* We always cache the section contents.
++			     Perhaps, if info->keep_memory is FALSE, we
++			     should free them, if we are permitted to.  */
++
++		          if (o->rawsize == 0)
++			      o->rawsize = o->size;
++		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++		          if (ocontents == NULL)
++			      goto error_return;
++		          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++		          elf_section_data (o)->this_hdr.contents = ocontents;
++		        }
++		    }
+ 
+-		  /* Look at the reloc only if the value has been resolved.  */
+-		  if (isym->st_shndx == shndx
+-		      && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION))
+-		    {
+-		      if (ocontents == NULL)
+-			{
+-			  if (elf_section_data (o)->this_hdr.contents != NULL)
+-			    ocontents = elf_section_data (o)->this_hdr.contents;
+-			  else
+-			    {
+-			      /* We always cache the section contents.
+-				 Perhaps, if info->keep_memory is FALSE, we
+-				 should free them, if we are permitted to.  */
+-			      if (o->rawsize == 0)
+-				o->rawsize = o->size;
+-			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
+-			      if (ocontents == NULL)
+-				goto error_return;
+-			      if (!bfd_get_section_contents (abfd, o, ocontents,
+-							     (file_ptr) 0,
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++			fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++                {
++	          isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* Look at the reloc only if the value has been resolved.  */
++                  if (isym->st_shndx == shndx
++                      && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION))
++                    {
++                      if (ocontents == NULL)
++                        {
++                          if (elf_section_data (o)->this_hdr.contents != NULL)
++                            ocontents = elf_section_data (o)->this_hdr.contents;
++                          else
++                            {
++                              /* We always cache the section contents.
++                                 Perhaps, if info->keep_memory is FALSE, we
++                                 should free them, if we are permitted to.  */
++		              if (o->rawsize == 0)
++			        o->rawsize = o->size;
++                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                              if (ocontents == NULL)
++                                goto error_return;
++                              if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                             (file_ptr) 0,
+ 							     o->rawsize))
+ 				goto error_return;
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+@@ -2028,7 +2096,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+ 			    }
+ 			}
+-		      irelscan->r_addend -= calc_fixup (irel->r_addend
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ 							+ isym->st_value,
+ 							0,
+ 							sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index b97534fc9f..c1551b9240 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2967,6 +2967,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 9aba84ca81..9b39b41941 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6858,6 +6858,12 @@ ENUM
+ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
++ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index 6057515a89..2b797ef2db 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -13187,6 +13187,10 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
+       return reloc_type == 1;  /* R_Z80_8.  */
+     default:
+       return FALSE;
++    case EM_MICROBLAZE:
++      return reloc_type == 33 /* R_MICROBLAZE_32_NONE.  */
++             || reloc_type == 0 /* R_MICROBLAZE_NONE.  */
++             || reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     }
+ }
+ 
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 34eeb97235..74a63abeb0 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2198,9 +2198,12 @@ md_apply_fix (fixS *   fixP,
+ 	 moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++      else if (fixP->fx_r_type == BFD_RELOC_32)
++	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+ 	fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
++      fixP->fx_done = 0;
+     }
+   return;
+ }
+@@ -2421,6 +2424,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   switch (fixp->fx_r_type)
+     {
+     case BFD_RELOC_NONE:
++    case BFD_RELOC_MICROBLAZE_32_NONE:
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+     case BFD_RELOC_32:
+     case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index 2fec296967..3978a3dc01 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -61,6 +61,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
++  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++   
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-Fix-relaxation-of-assembler-resolved-references.patch
deleted file mode 100644
index 14a4f32986..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-Fix-relaxation-of-assembler-resolved-references.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From c4ce6cb47613293e02837fc00c2c2ebfcdd596f6 Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
-Date: Tue, 14 Feb 2012 01:00:22 +0100
-Subject: [PATCH 05/40] Fix relaxation of assembler resolved references
-
----
- bfd/elf32-microblaze.c     | 41 ++++++++++++++++++++++++++++++++++++++
- gas/config/tc-microblaze.c |  1 +
- 2 files changed, 42 insertions(+)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 693fc71f730..09dedc46106 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1969,6 +1969,47 @@ microblaze_elf_relax_section (bfd *abfd,
- 	  irelscanend = irelocs + o->reloc_count;
- 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- 	    {
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+                {
-+                  unsigned int val;
-+
-+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+
-+                  /* This was a PC-relative instruction that was completely resolved.  */
-+                  if (ocontents == NULL)
-+                    {
-+                      if (elf_section_data (o)->this_hdr.contents != NULL)
-+                          ocontents = elf_section_data (o)->this_hdr.contents;
-+                      else
-+                        {
-+                          /* We always cache the section contents.
-+                             Perhaps, if info->keep_memory is FALSE, we
-+                             should free them, if we are permitted to.  */
-+
-+                          if (o->rawsize == 0)
-+                              o->rawsize = o->size;
-+                          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+                          if (ocontents == NULL)
-+                              goto error_return;
-+                          if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                         (file_ptr) 0,
-+                                                         o->rawsize))
-+                              goto error_return;
-+                          elf_section_data (o)->this_hdr.contents = ocontents;
-+                        }
-+                    }
-+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+                  if (val != irelscan->r_addend) {
-+                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+                  }
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
-+                                                    + isym->st_value, 0, sec);
-+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                                     irelscan->r_addend);
-+              }
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
-+                  fprintf(stderr, "Unhandled NONE 64\n");
-+              }
- 	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- 		{
- 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 34eeb972357..d01653aeef9 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -2201,6 +2201,7 @@ md_apply_fix (fixS *   fixP,
-       else
- 	fixP->fx_r_type = BFD_RELOC_NONE;
-       fixP->fx_addsy = section_symbol (absolute_section);
-+      fixP->fx_done = 0;
-     }
-   return;
- }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
new file mode 100644
index 0000000000..95e4a363ff
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -0,0 +1,39 @@
+From 4fc5075cebc9c76053b5ff683ab75c9e8b46ca1a Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 05/52] upstream change to garbage collection sweep causes mb
+ regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 998b72f228..2daf8fdf6a 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -6372,7 +6372,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
+ 
+       inf = (struct elf_gc_sweep_symbol_info *) data;
+       (*inf->hide_symbol) (inf->info, h, TRUE);
+-      h->def_regular = 0;
+       h->ref_regular = 0;
+       h->ref_regular_nonweak = 0;
+     }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-Fix-bug-in-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000000..fcbd662e10
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-Fix-bug-in-TLSTPREL-Relocation.patch
@@ -0,0 +1,33 @@
+From 4e8bd012d3025a6f6b2b2794930f1bfbad7932e8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 15 Jun 2015 16:50:30 +0530
+Subject: [PATCH 06/52] Fix bug in TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index e9715eae6a..9c4f809eaa 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1447,9 +1447,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 	      relocation += addend;
+ 	      relocation -= dtprel_base(info);
+ 	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+-			  contents + offset + 2);
++			  contents + offset + endian);
+ 	      bfd_put_16 (input_bfd, relocation & 0xffff,
+-			  contents + offset + 2 + INST_WORD_SIZE);
++			  contents + offset + endian + INST_WORD_SIZE);
+ 	      break;
+ 	    case (int) R_MICROBLAZE_TEXTREL_64:
+ 	    case (int) R_MICROBLAZE_TEXTREL_32_LO:
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
deleted file mode 100644
index 308a453e6c..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
+++ /dev/null
@@ -1,222 +0,0 @@
-From 77c9dd2085e5a9e116cd8d8b4fbc1387c93d26d8 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 6 Feb 2017 15:53:08 +0530
-Subject: [PATCH 06/40] microblaze: Fixup debug_loc sections after linker
- relaxation
-
-Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
-reloc info from the assembler to the linker when the linker
-manages to fully resolve a local symbol reference.
-
-This is a workaround for design flaws in the assembler to
-linker interface with regards to linker relaxation.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
----
- bfd/bfd-in2.h              |  5 +++++
- bfd/elf32-microblaze.c     | 39 +++++++++++++++++++++++++++++++-------
- bfd/libbfd.h               |  1 +
- bfd/reloc.c                |  6 ++++++
- binutils/readelf.c         |  4 ++++
- gas/config/tc-microblaze.c |  3 +++
- include/elf/microblaze.h   |  1 +
- 7 files changed, 52 insertions(+), 7 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 35ef4d755bb..3fdbf8ed755 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5428,6 +5428,11 @@ value relative to the read-write small data area anchor  */
- expressions of the form "Symbol Op Symbol"  */
-   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
- 
-+/* This is a 32 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imm instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_32_NONE,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 09dedc46106..1be1ead2f41 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  FALSE),		/* PC relative offset?  */
- 
-+   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
-+          0,         /* Rightshift.  */
-+          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,           /* Bitsize.  */
-+          TRUE,         /* PC_relative.  */
-+          0,           /* Bitpos.  */
-+          complain_overflow_bitfield,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_32_NONE",/* Name.  */
-+          FALSE,       /* Partial Inplace.  */
-+          0,          /* Source Mask.  */
-+          0,         /* Dest Mask.  */
-+          FALSE),       /* PC relative offset?  */
-+
-    /* This reloc does nothing.	Used for relaxation.  */
-    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_NONE:
-       microblaze_reloc = R_MICROBLAZE_NONE;
-       break;
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-+      microblaze_reloc = R_MICROBLAZE_32_NONE;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_NONE:
-       microblaze_reloc = R_MICROBLAZE_64_NONE;
-       break;
-@@ -1914,14 +1931,22 @@ microblaze_elf_relax_section (bfd *abfd,
- 		}
- 	      break;
- 	    case R_MICROBLAZE_NONE:
-+	    case R_MICROBLAZE_32_NONE:
- 	      {
- 		/* This was a PC-relative instruction that was
- 		   completely resolved.  */
- 		int sfix, efix;
-+		unsigned int val;
- 		bfd_vma target_address;
- 		target_address = irel->r_addend + irel->r_offset;
- 		sfix = calc_fixup (irel->r_offset, 0, sec);
- 		efix = calc_fixup (target_address, 0, sec);
-+
-+		/* Validate the in-band val.  */
-+		val = bfd_get_32 (abfd, contents + irel->r_offset);
-+		if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+		       fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+		}
- 		irel->r_addend -= (efix - sfix);
- 		/* Should use HOWTO.  */
- 		microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-@@ -1969,12 +1994,16 @@ microblaze_elf_relax_section (bfd *abfd,
- 	  irelscanend = irelocs + o->reloc_count;
- 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- 	    {
--              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
-                 {
-                   unsigned int val;
- 
-                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
- 
-+                  /* hax: We only do the following fixup for debug location lists.  */
-+                  if (strcmp(".debug_loc", o->name))
-+                    continue;
-+
-                   /* This was a PC-relative instruction that was completely resolved.  */
-                   if (ocontents == NULL)
-                     {
-@@ -2002,14 +2031,10 @@ microblaze_elf_relax_section (bfd *abfd,
-                   if (val != irelscan->r_addend) {
-                     fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-                   }
--                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
--                                                    + isym->st_value, 0, sec);
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-                                                      irelscan->r_addend);
-               }
--              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
--                  fprintf(stderr, "Unhandled NONE 64\n");
--              }
- 	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- 		{
- 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-@@ -2069,7 +2094,7 @@ microblaze_elf_relax_section (bfd *abfd,
- 			      elf_section_data (o)->this_hdr.contents = ocontents;
- 			    }
- 			}
--		      irelscan->r_addend -= calc_fixup (irel->r_addend
-+                     irelscan->r_addend -= calc_fixup (irelscan->r_addend
- 							+ isym->st_value,
- 							0,
- 							sec);
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index b97534fc9fe..c1551b92405 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2967,6 +2967,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_ROSDA",
-   "BFD_RELOC_MICROBLAZE_32_RWSDA",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-+  "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 9aba84ca81e..9b39b419415 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6858,6 +6858,12 @@ ENUM
- ENUMDOC
-   This is a 32 bit reloc for the microblaze to handle
-   expressions of the form "Symbol Op Symbol"
-+ENUM
-+  BFD_RELOC_MICROBLAZE_32_NONE
-+ENUMDOC
-+  This is a 32 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imm instruction).  No relocation is
-+  done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
-diff --git a/binutils/readelf.c b/binutils/readelf.c
-index 6057515a89b..04704d22fef 100644
---- a/binutils/readelf.c
-+++ b/binutils/readelf.c
-@@ -13406,6 +13406,10 @@ is_none_reloc (Filedata * filedata, unsigned int reloc_type)
- 	      || reloc_type == 32 /* R_AVR_DIFF32.  */);
-     case EM_METAG:
-       return reloc_type == 3; /* R_METAG_NONE.  */
-+    case EM_MICROBLAZE:
-+      return reloc_type == 30 /* R_MICROBLAZE_32_NONE.  */
-+             || reloc_type == 0 /* R_MICROBLAZE_NONE.  */
-+             || reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
-     case EM_NDS32:
-       return (reloc_type == 0       /* R_XTENSA_NONE.  */
- 	      || reloc_type == 204  /* R_NDS32_DIFF8.  */
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index d01653aeef9..74a63abeb0c 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -2198,6 +2198,8 @@ md_apply_fix (fixS *   fixP,
- 	 moves code around due to relaxing.  */
-       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-+      else if (fixP->fx_r_type == BFD_RELOC_32)
-+	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
-       else
- 	fixP->fx_r_type = BFD_RELOC_NONE;
-       fixP->fx_addsy = section_symbol (absolute_section);
-@@ -2422,6 +2424,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
-   switch (fixp->fx_r_type)
-     {
-     case BFD_RELOC_NONE:
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-     case BFD_RELOC_MICROBLAZE_64_NONE:
-     case BFD_RELOC_32:
-     case BFD_RELOC_MICROBLAZE_32_LO:
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 2fec296967b..55f34f72b0d 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
-   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
-+  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
- 
- /* Global base address names.  */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-Added-Address-extension-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-Added-Address-extension-instructions.patch
new file mode 100644
index 0000000000..fd15e23c1d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-Added-Address-extension-instructions.patch
@@ -0,0 +1,101 @@
+From 1d1344e5786d435f4f492739d0c477befa4c6906 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jan 2016 12:28:21 +0530
+Subject: [PATCH 07/52] Added Address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+  2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
+
+  *microblaze-opc.h (op_code_struct): Update
+     Added new instructions
+  *microblaze-opcm.h (microblaze_instr): Update
+     Added new instructions
+
+Conflicts:
+	opcodes/microblaze-opcm.h
+---
+ opcodes/microblaze-opc.h  | 11 +++++++++++
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 16 insertions(+), 5 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index b6c5016e4d..1f1ade40b2 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -178,8 +178,11 @@ struct op_code_struct
+   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
+   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
+   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
++  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
++  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 795c57b5ff..b05e319862 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+-  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+-  shr, sw, swr, swx, lbui, lhui, lwi,
++  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+   sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   fint, fsqrt,
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
deleted file mode 100644
index 4319f1d705..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 3f743710f53d86ed5e53d97b3b1b06d7a8cbcdc1 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Wed, 27 Feb 2013 13:56:11 +1000
-Subject: [PATCH 07/40] upstream change to garbage collection sweep causes mb
- regression
-
-Upstream change for PR13177 now clears the def_regular during gc_sweep of a
-section. (All other archs in binutils/bfd/elf32-*.c received an update
-to a warning about unresolvable relocations - this warning is not present
-in binutils/bfd/elf32-microblaze.c, but this warning check would not
-prevent the error being seen)
-
-The visible issue with this change is when running a c++ application
-in Petalinux which links libstdc++.so for exception handling it segfaults
-on execution.
-
-This does not occur if static linking libstdc++.a, so its during the
-relocations for a shared lib with garbage collection this occurs
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- bfd/elflink.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/bfd/elflink.c b/bfd/elflink.c
-index 998b72f2281..2daf8fdf6a8 100644
---- a/bfd/elflink.c
-+++ b/bfd/elflink.c
-@@ -6372,7 +6372,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
- 
-       inf = (struct elf_gc_sweep_symbol_info *) data;
-       (*inf->hide_symbol) (inf->info, h, TRUE);
--      h->def_regular = 0;
-       h->ref_regular = 0;
-       h->ref_regular_nonweak = 0;
-     }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-Fix-bug-in-TLSTPREL-Relocation.patch
deleted file mode 100644
index 4ab7681e85..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-Fix-bug-in-TLSTPREL-Relocation.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 481dd44f36e7df691037201d9865482debbb397d Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 15 Jun 2015 16:50:30 +0530
-Subject: [PATCH 08/40] Fix bug in TLSTPREL Relocation
-
-Fixed the problem related to the fixup/relocations TLSTPREL.
-When the fixup is applied the addend is not added at the correct offset
-of the instruction. The offset is hard coded considering its big endian
-and it fails for Little endian. This patch allows support for both
-big & little-endian compilers
----
- bfd/elf32-microblaze.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 1be1ead2f41..ec1944c6faf 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1447,9 +1447,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 	      relocation += addend;
- 	      relocation -= dtprel_base(info);
- 	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
--			  contents + offset + 2);
-+			  contents + offset + endian);
- 	      bfd_put_16 (input_bfd, relocation & 0xffff,
--			  contents + offset + 2 + INST_WORD_SIZE);
-+			  contents + offset + endian + INST_WORD_SIZE);
- 	      break;
- 	    case (int) R_MICROBLAZE_TEXTREL_64:
- 	    case (int) R_MICROBLAZE_TEXTREL_32_LO:
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-fixing-the-MAX_OPCODES-to-correct-value.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
new file mode 100644
index 0000000000..8564003cb0
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
@@ -0,0 +1,25 @@
+From b2e494ee992ef0509bd2a4512f62841098631219 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 28 Jan 2016 14:07:34 +0530
+Subject: [PATCH 08/52] fixing the MAX_OPCODES to correct value
+
+---
+ opcodes/microblaze-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 1f1ade40b2..c7a506b845 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+ 
+ struct op_code_struct
+ {
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000000..0188629db2
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Add-new-bit-field-instructions.patch
@@ -0,0 +1,237 @@
+From cea8d524fca305c2878374433d9745b938e4c78f Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jul 2016 12:24:28 +0530
+Subject: [PATCH 09/52] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+Conflicts:
+	opcodes/microblaze-dis.c
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   | 20 +++++++++--
+ opcodes/microblaze-opc.h   | 12 ++++++-
+ opcodes/microblaze-opcm.h  |  6 +++-
+ 4 files changed, 104 insertions(+), 5 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 74a63abeb0..765abfb388 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -917,7 +917,7 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned int immed, temp;
++  unsigned int immed, immed2, temp;
+   expressionS exp;
+   char name[20];
+ 
+@@ -1172,7 +1172,76 @@ md_assemble (char * str)
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+       inst |= (immed << IMM_LOW) & IMM5_MASK;
+       break;
++ case INST_TYPE_RD_R1_IMM5_IMM5:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++	{
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++	{
++          as_fatal (_("Error in statement syntax"));
++          reg2 = 0;
++        }
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (&reg2))
++        as_fatal (_("Cannot use special register with this instruction"));
+ 
++      /* Width immediate value.  */
++      if (strcmp (op_end, ""))
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++      else
++        as_fatal (_("Error in statement syntax"));
++      if (exp.X_op != O_constant)
++	{
++          as_warn (_("Symbol used as immediate width value for bit field instruction"));
++          immed = 1;
++        }
++      else
++        immed = exp.X_add_number;
++      if (opcode->instr == bsefi && immed > 31)
++        as_fatal (_("Width value must be less than 32"));
++
++      /* Shift immediate value.  */
++      if (strcmp (op_end, ""))
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++      else
++        as_fatal (_("Error in statement syntax"));
++      if (exp.X_op != O_constant)
++	    {
++          as_warn (_("Symbol used as immediate shift value for bit field instruction"));
++          immed2 = 0;
++        }
++      else
++	    {
++          output = frag_more (isize);
++          immed2 = exp.X_add_number;
++	    }
++      if (immed2 != (immed2 % 32))
++	    {
++          as_warn (_("Shift value greater than 32. using <value %% 32>"));
++          immed2 = immed2 % 32;
++        }
++
++      /* Check combined value.  */
++      if (immed + immed2 > 32)
++        as_fatal (_("Width value + shift value must not be greater than 32"));
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++      if (opcode->instr == bsefi)
++        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++      else
++        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
++      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++      break;
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index be1534c257..315c6e9350 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -91,7 +91,19 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_rfsl (struct string_buf *buf, long instr)
++get_field_imm5width (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
++static char *
++get_field_rfsl (struct string_buf *buf,long instr)
+ {
+   char *p = strbuf (buf);
+ 
+@@ -427,7 +439,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
+-	  /* For tuqula instruction */
++        /* For bit field insns.  */
++	case INST_TYPE_RD_R1_IMM5_IMM5:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++	     break;
++	/* For tuqula instruction */
+ 	case INST_TYPE_RD:
+ 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
+ 	  break;
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index c7a506b845..f61f4ef66d 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar.  */
+ #define INST_TYPE_IMM5 20
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+ 
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index b05e319862..fa921c90c9 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu,swapb,swaph,
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+-  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW  11 /* Low bit for RB.  */
+ #define IMM_LOW  0 /* Low bit for immediate.  */
+ #define IMM_MBAR 21 /* low bit for mbar instruction.  */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+ 
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Added-Address-extension-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Added-Address-extension-instructions.patch
deleted file mode 100644
index c5bd3b2d5b..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0009-Added-Address-extension-instructions.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From fa85df88dc229f7f8f0bc09cd0995d05f49c03b7 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 18 Jan 2016 12:28:21 +0530
-Subject: [PATCH 09/40] Added Address extension instructions
-
-This patch adds the support of new instructions which are required
-for supporting Address extension feature.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-  2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze-opc.h (op_code_struct): Update
-     Added new instructions
-     Set MAX_OPCODES to matching value
-  *microblaze-opcm.h (microblaze_instr): Update
-     Added new instructions
----
- opcodes/microblaze-opc.h  | 13 ++++++++++++-
- opcodes/microblaze-opcm.h | 10 +++++-----
- 2 files changed, 17 insertions(+), 6 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index b6c5016e4d2..c7a506b845a 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -102,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 291
-+#define MAX_OPCODES 299
- 
- struct op_code_struct
- {
-@@ -178,8 +178,11 @@ struct op_code_struct
-   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
-   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-+  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
-   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-+  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
-   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-+  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
-   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
-   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
-@@ -229,18 +232,24 @@ struct op_code_struct
-   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
-   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
-   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
-+  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
-   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
-   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
-+  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
-   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
-   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
-   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
-+  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
-   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
-   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
-+  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
-   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
-   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
-+  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
-   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
-   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
-   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
-+  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
-   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
-   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
-   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
-@@ -405,6 +414,8 @@ struct op_code_struct
-   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
-   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
-   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
-+  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
-+  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
-   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
-   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 795c57b5ff6..b05e319862e 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,13 +33,13 @@ enum microblaze_instr
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
--  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
--  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
-+  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
-+  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
--  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
--  shr, sw, swr, swx, lbui, lhui, lwi,
-+  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
-+  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
-   sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
-   fint, fsqrt,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-Add-new-bit-field-instructions.patch
deleted file mode 100644
index 1612c11cbd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-Add-new-bit-field-instructions.patch
+++ /dev/null
@@ -1,231 +0,0 @@
-From 0034d6b5231a0a72c5f9fc47ba4c8eba0c35ff39 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 18 Jul 2016 12:24:28 +0530
-Subject: [PATCH 10/40] Add new bit-field instructions
-
-This patches adds new bsefi and bsifi instructions.
-BSEFI- The instruction shall extract a bit field from a
-register and place it right-adjusted in the destination register.
-The other bits in the destination register shall be set to zero
-BSIFI- The instruction shall insert a right-adjusted bit field
-from a register at another position in the destination register.
-The rest of the bits in the destination register shall be unchanged
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
- opcodes/microblaze-dis.c   | 17 +++++++++
- opcodes/microblaze-opc.h   | 12 ++++++-
- opcodes/microblaze-opcm.h  |  6 +++-
- 4 files changed, 103 insertions(+), 3 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 74a63abeb0c..765abfb3885 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -917,7 +917,7 @@ md_assemble (char * str)
-   unsigned reg2;
-   unsigned reg3;
-   unsigned isize;
--  unsigned int immed, temp;
-+  unsigned int immed, immed2, temp;
-   expressionS exp;
-   char name[20];
- 
-@@ -1172,7 +1172,76 @@ md_assemble (char * str)
-       inst |= (reg2 << RA_LOW) & RA_MASK;
-       inst |= (immed << IMM_LOW) & IMM5_MASK;
-       break;
-+ case INST_TYPE_RD_R1_IMM5_IMM5:
-+      if (strcmp (op_end, ""))
-+        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
-+      else
-+	{
-+          as_fatal (_("Error in statement syntax"));
-+          reg1 = 0;
-+        }
-+      if (strcmp (op_end, ""))
-+        op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
-+      else
-+	{
-+          as_fatal (_("Error in statement syntax"));
-+          reg2 = 0;
-+        }
-+
-+      /* Check for spl registers.  */
-+      if (check_spl_reg (&reg1))
-+        as_fatal (_("Cannot use special register with this instruction"));
-+      if (check_spl_reg (&reg2))
-+        as_fatal (_("Cannot use special register with this instruction"));
- 
-+      /* Width immediate value.  */
-+      if (strcmp (op_end, ""))
-+        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
-+      else
-+        as_fatal (_("Error in statement syntax"));
-+      if (exp.X_op != O_constant)
-+	{
-+          as_warn (_("Symbol used as immediate width value for bit field instruction"));
-+          immed = 1;
-+        }
-+      else
-+        immed = exp.X_add_number;
-+      if (opcode->instr == bsefi && immed > 31)
-+        as_fatal (_("Width value must be less than 32"));
-+
-+      /* Shift immediate value.  */
-+      if (strcmp (op_end, ""))
-+        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
-+      else
-+        as_fatal (_("Error in statement syntax"));
-+      if (exp.X_op != O_constant)
-+	    {
-+          as_warn (_("Symbol used as immediate shift value for bit field instruction"));
-+          immed2 = 0;
-+        }
-+      else
-+	    {
-+          output = frag_more (isize);
-+          immed2 = exp.X_add_number;
-+	    }
-+      if (immed2 != (immed2 % 32))
-+	    {
-+          as_warn (_("Shift value greater than 32. using <value %% 32>"));
-+          immed2 = immed2 % 32;
-+        }
-+
-+      /* Check combined value.  */
-+      if (immed + immed2 > 32)
-+        as_fatal (_("Width value + shift value must not be greater than 32"));
-+
-+      inst |= (reg1 << RD_LOW) & RD_MASK;
-+      inst |= (reg2 << RA_LOW) & RA_MASK;
-+      if (opcode->instr == bsefi)
-+        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
-+      else
-+        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
-+      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
-+      break;
-     case INST_TYPE_R1_R2:
-       if (strcmp (op_end, ""))
-         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index be1534c257c..52c9068805f 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -90,6 +90,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
-   return p;
- }
- 
-+static char *
-+get_field_imm5width (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  if (instr & 0x00004000)
-+    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+ else
-+    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+  return p;
-+}
-+
- static char *
- get_field_rfsl (struct string_buf *buf, long instr)
- {
-@@ -428,6 +440,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	case INST_TYPE_NONE:
- 	  break;
- 	  /* For tuqula instruction */
-+        /* For bit field insns.  */
-+	case INST_TYPE_RD_R1_IMM5_IMM5:
-+	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
-+	  break;
-+	/* For tuqula instruction */
- 	case INST_TYPE_RD:
- 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
- 	  break;
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index c7a506b845a..f61f4ef66d9 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -59,6 +59,9 @@
- /* For mbar.  */
- #define INST_TYPE_IMM5 20
- 
-+/* For bsefi and bsifi */
-+#define INST_TYPE_RD_R1_IMM5_IMM5  21
-+
- #define INST_TYPE_NONE 25
- 
- 
-@@ -89,7 +92,9 @@
- #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
- #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
-+#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
-+#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
- #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
-@@ -102,7 +107,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 299
-+#define MAX_OPCODES 301
- 
- struct op_code_struct
- {
-@@ -159,6 +164,8 @@ struct op_code_struct
-   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
-   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
-   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
-+  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
-   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
-   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5  ((int) 0x00000000)
- #define MAX_IMM5  ((int) 0x0000001f)
- 
-+#define MIN_IMM_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM_WIDTH  ((int) 0x00000020)
-+
- #endif /* MICROBLAZE_OPC */
- 
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index b05e319862e..fa921c90c98 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -29,7 +29,7 @@ enum microblaze_instr
-   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
-   mulh, mulhu, mulhsu,swapb,swaph,
-   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
--  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
-+  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-@@ -129,6 +129,7 @@ enum microblaze_instr_type
- #define RB_LOW  11 /* Low bit for RB.  */
- #define IMM_LOW  0 /* Low bit for immediate.  */
- #define IMM_MBAR 21 /* low bit for mbar instruction.  */
-+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
- 
- #define RD_MASK 0x03E00000
- #define RA_MASK 0x001F0000
-@@ -141,6 +142,9 @@ enum microblaze_instr_type
- /* Imm mask for mbar.  */
- #define IMM5_MBAR_MASK 0x03E00000
- 
-+/* Imm mask for extract/insert width. */
-+#define IMM5_WIDTH_MASK 0x000007C0
-+
- /* FSL imm mask for get, put instructions.  */
- #define  RFSL_MASK 0x000000F
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-fixing-the-imm-bug.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-fixing-the-imm-bug.patch
new file mode 100644
index 0000000000..892205cd99
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0010-fixing-the-imm-bug.patch
@@ -0,0 +1,27 @@
+From d6ccef90be40de63ee6da4943a601edaf7b1a136 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 10 Jul 2017 16:07:28 +0530
+Subject: [PATCH 10/52] fixing the imm bug. with relax option imm -1 is also
+ getting removed this is corrected now.
+
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index 9c4f809eaa..c22130fd8c 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -1865,8 +1865,7 @@ microblaze_elf_relax_section (bfd *abfd,
+       else
+ 	symval += irel->r_addend;
+ 
+-      if ((symval & 0xffff8000) == 0
+-	  || (symval & 0xffff8000) == 0xffff8000)
++      if ((symval & 0xffff8000) == 0)
+ 	{
+ 	  /* We can delete this instruction.  */
+ 	  sec->relax[sec->relax_count].addr = irel->r_offset;
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
new file mode 100644
index 0000000000..db23fe1473
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
@@ -0,0 +1,33 @@
+From 3bb637b058c5f2622950e6984695e36f9cac067a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Sep 2017 18:00:23 +0530
+Subject: [PATCH 11/52] [Patch,Microblaze]: fixed bug in GCC so that It will
+ support .long 0U and .long 0u
+
+---
+ gas/expr.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/gas/expr.c b/gas/expr.c
+index 6f8ccb8230..0e34ca53d9 100644
+--- a/gas/expr.c
++++ b/gas/expr.c
+@@ -803,6 +803,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
+ 	      break;
+ 	    }
+ 	}
++      if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
++      {
++      input_line_pointer--;
++
++      integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
++                        ? 0 : 10,
++                        expressionP);
++      break;
++      }
+       c = *input_line_pointer;
+       switch (c)
+ 	{
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-fixing-the-imm-bug.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-fixing-the-imm-bug.patch
deleted file mode 100644
index fcb9c8ae08..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0011-fixing-the-imm-bug.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 75e55d8ebf3cd780fe69c066163ab2da7ac204f2 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 10 Jul 2017 16:07:28 +0530
-Subject: [PATCH 11/40] fixing the imm bug.
-
-with relax option imm -1 is also getting removed this is corrected now.
----
- bfd/elf32-microblaze.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index ec1944c6faf..cf4a7fdba33 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1865,8 +1865,7 @@ microblaze_elf_relax_section (bfd *abfd,
-       else
- 	symval += irel->r_addend;
- 
--      if ((symval & 0xffff8000) == 0
--	  || (symval & 0xffff8000) == 0xffff8000)
-+      if ((symval & 0xffff8000) == 0)
- 	{
- 	  /* We can delete this instruction.  */
- 	  sec->relax[sec->relax_count].addr = irel->r_offset;
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
deleted file mode 100644
index 02cc12593b..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-Patch-Microblaze-fixed-bug-in-GCC-so-that-It-will-su.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 5432f81ba9d7c17b20ff576c7c09ae78f4fe6e9c Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Fri, 29 Sep 2017 18:00:23 +0530
-Subject: [PATCH 12/40] [Patch,Microblaze]: fixed bug in GCC so that It will
- support .long 0U and .long 0u
-
----
- gas/expr.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gas/expr.c b/gas/expr.c
-index 6f8ccb82303..0e34ca53d9b 100644
---- a/gas/expr.c
-+++ b/gas/expr.c
-@@ -803,6 +803,15 @@ operand (expressionS *expressionP, enum expr_mode mode)
- 	      break;
- 	    }
- 	}
-+      if ((*input_line_pointer == 'U') || (*input_line_pointer == 'u'))
-+      {
-+      input_line_pointer--;
-+
-+      integer_constant ((NUMBERS_WITH_SUFFIX || flag_m68k_mri)
-+                        ? 0 : 10,
-+                        expressionP);
-+      break;
-+      }
-       c = *input_line_pointer;
-       switch (c)
- 	{
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-fixing-the-constant-range-check-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-fixing-the-constant-range-check-issue.patch
new file mode 100644
index 0000000000..4145b0dadd
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0012-fixing-the-constant-range-check-issue.patch
@@ -0,0 +1,26 @@
+From e1cb5c37efd76b44a878574ee3baad4c7a882e3b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 16 Oct 2017 15:44:23 +0530
+Subject: [PATCH 12/52] fixing the constant range check issue sample error: not
+ in range ffffffff80000000..7fffffff, not ffffffff70000000
+
+---
+ gas/config/tc-microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 765abfb388..5810a74a5f 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -757,7 +757,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+       if ((e->X_add_number >> 31) == 1)
+ 	e->X_add_number |= -((addressT) (1U << 31));
+ 
+-      if (e->X_add_number < min || e->X_add_number > max)
++      if ((int)e->X_add_number < min || (int)e->X_add_number > max)
+ 	{
+ 	  as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
+ 		    (long) min, (long) max, (long) e->X_add_number);
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-Patch-Microblaze-Compiler-will-give-error-messages-i.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
new file mode 100644
index 0000000000..a74f2b9e5b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
@@ -0,0 +1,36 @@
+From 1a3f130008b4ebcd9a6e45cdac7188bde88f2f28 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 21 Feb 2018 12:32:02 +0530
+Subject: [PATCH 13/52] [Patch,Microblaze]: Compiler will give error messages
+ in more detail for mxl-gp-opt flag..
+
+---
+ ld/ldmain.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/ld/ldmain.c b/ld/ldmain.c
+index 08be9030cb..613d748fef 100644
+--- a/ld/ldmain.c
++++ b/ld/ldmain.c
+@@ -1515,6 +1515,18 @@ reloc_overflow (struct bfd_link_info *info,
+ 	  break;
+ 	case bfd_link_hash_defined:
+ 	case bfd_link_hash_defweak:
++
++         if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) &&  entry->type == bfd_link_hash_defined)
++	  {
++	  einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: "
++		 "%s against symbol `%T' defined in %A section in %B"),
++                 reloc_name, entry->root.string,
++                 entry->u.def.section,
++                 entry->u.def.section == bfd_abs_section_ptr
++                  ? info->output_bfd : entry->u.def.section->owner);
++	      break;
++	  }
++
+ 	  einfo (_(" relocation truncated to fit: "
+ 		   "%s against symbol `%pT' defined in %pA section in %pB"),
+ 		 reloc_name, entry->root.string,
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
deleted file mode 100644
index accff21495..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0013-fixing-the-constant-range-check-issue.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 6337e24a220dca86b71efcc10c5ffed6bf11bc22 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 16 Oct 2017 15:44:23 +0530
-Subject: [PATCH 13/40] fixing the constant range check issue
-
-sample error: not in range ffffffff80000000..7fffffff, not ffffffff70000000
----
- gas/config/tc-microblaze.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 765abfb3885..5810a74a5fc 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -757,7 +757,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
-       if ((e->X_add_number >> 31) == 1)
- 	e->X_add_number |= -((addressT) (1U << 31));
- 
--      if (e->X_add_number < min || e->X_add_number > max)
-+      if ((int)e->X_add_number < min || (int)e->X_add_number > max)
- 	{
- 	  as_fatal (_("operand must be absolute in range %lx..%lx, not %lx"),
- 		    (long) min, (long) max, (long) e->X_add_number);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
deleted file mode 100644
index cdbe65a625..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-Patch-Microblaze-Compiler-will-give-error-messages-i.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From e7e06edfb6c24a993603c9100f8ab8c29999ef90 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 21 Feb 2018 12:32:02 +0530
-Subject: [PATCH 14/40] [Patch,Microblaze]: Compiler will give error messages
- in more detail for mxl-gp-opt flag..
-
----
- ld/ldmain.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
-diff --git a/ld/ldmain.c b/ld/ldmain.c
-index 08be9030cb5..613d748fefd 100644
---- a/ld/ldmain.c
-+++ b/ld/ldmain.c
-@@ -1515,6 +1515,18 @@ reloc_overflow (struct bfd_link_info *info,
- 	  break;
- 	case bfd_link_hash_defined:
- 	case bfd_link_hash_defweak:
-+
-+         if((strcmp(reloc_name,"R_MICROBLAZE_SRW32") == 0) &&  entry->type == bfd_link_hash_defined)
-+	  {
-+	  einfo (_(" relocation truncated to fit: don't enable small data pointer optimizations[mxl-gp-opt] if extern or multiple declarations used: "
-+		 "%s against symbol `%T' defined in %A section in %B"),
-+                 reloc_name, entry->root.string,
-+                 entry->u.def.section,
-+                 entry->u.def.section == bfd_abs_section_ptr
-+                  ? info->output_bfd : entry->u.def.section->owner);
-+	      break;
-+	  }
-+
- 	  einfo (_(" relocation truncated to fit: "
- 		   "%s against symbol `%pT' defined in %pA section in %pB"),
- 		 reloc_name, entry->root.string,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-intial-commit-of-MB-64-bit.patch
new file mode 100644
index 0000000000..f0037e1f57
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0014-intial-commit-of-MB-64-bit.patch
@@ -0,0 +1,4760 @@
+From d25d934f076297615cb0287488449fb32b9c46e8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:28:28 +0530
+Subject: [PATCH 14/52] intial commit of MB 64-bit
+
+Conflicts:
+	bfd/configure
+	bfd/configure.ac
+	bfd/cpu-microblaze.c
+	ld/Makefile.am
+	ld/Makefile.in
+	opcodes/microblaze-dis.c
+---
+ bfd/Makefile.am                    |    2 +
+ bfd/Makefile.in                    |    3 +
+ bfd/config.bfd                     |    4 +
+ bfd/configure                      |    2 +
+ bfd/configure.ac                   |    2 +
+ bfd/cpu-microblaze.c               |   53 +-
+ bfd/elf64-microblaze.c             | 3610 ++++++++++++++++++++++++++++
+ bfd/targets.c                      |    6 +
+ gas/config/tc-microblaze.c         |  274 ++-
+ gas/config/tc-microblaze.h         |    4 +-
+ include/elf/common.h               |    1 +
+ ld/Makefile.am                     |    4 +
+ ld/Makefile.in                     |    6 +
+ ld/configure.tgt                   |    3 +
+ ld/emulparams/elf64microblaze.sh   |   23 +
+ ld/emulparams/elf64microblazeel.sh |   23 +
+ opcodes/microblaze-dis.c           |   35 +-
+ opcodes/microblaze-opc.h           |  162 +-
+ opcodes/microblaze-opcm.h          |   20 +-
+ 19 files changed, 4197 insertions(+), 40 deletions(-)
+ create mode 100644 bfd/elf64-microblaze.c
+ create mode 100644 ld/emulparams/elf64microblaze.sh
+ create mode 100644 ld/emulparams/elf64microblazeel.sh
+
+diff --git a/bfd/Makefile.am b/bfd/Makefile.am
+index c88c448000..d86f1c5697 100644
+--- a/bfd/Makefile.am
++++ b/bfd/Makefile.am
+@@ -562,6 +562,7 @@ BFD64_BACKENDS = \
+ 	elf64-riscv.lo \
+ 	elfxx-riscv.lo \
+ 	elf64-s390.lo \
++	elf64-microblaze.lo \
+ 	elf64-sparc.lo \
+ 	elf64-tilegx.lo \
+ 	elf64-x86-64.lo \
+@@ -596,6 +597,7 @@ BFD64_BACKENDS_CFILES = \
+ 	elf64-nfp.c \
+ 	elf64-ppc.c \
+ 	elf64-s390.c \
++	elf64-microblaze.c \
+ 	elf64-sparc.c \
+ 	elf64-tilegx.c \
+ 	elf64-x86-64.c \
+diff --git a/bfd/Makefile.in b/bfd/Makefile.in
+index d0d14c6ab3..a54abeca48 100644
+--- a/bfd/Makefile.in
++++ b/bfd/Makefile.in
+@@ -988,6 +988,7 @@ BFD64_BACKENDS = \
+ 	elf64-riscv.lo \
+ 	elfxx-riscv.lo \
+ 	elf64-s390.lo \
++	elf64-microblaze.lo \
+ 	elf64-sparc.lo \
+ 	elf64-tilegx.lo \
+ 	elf64-x86-64.lo \
+@@ -1022,6 +1023,7 @@ BFD64_BACKENDS_CFILES = \
+ 	elf64-nfp.c \
+ 	elf64-ppc.c \
+ 	elf64-s390.c \
++	elf64-microblaze.c \
+ 	elf64-sparc.c \
+ 	elf64-tilegx.c \
+ 	elf64-x86-64.c \
+@@ -1501,6 +1503,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
+diff --git a/bfd/config.bfd b/bfd/config.bfd
+index 14523caf0c..437c03bb9d 100644
+--- a/bfd/config.bfd
++++ b/bfd/config.bfd
+@@ -825,11 +825,15 @@ case "${targ}" in
+   microblazeel*-*)
+     targ_defvec=microblaze_elf32_le_vec
+     targ_selvecs=microblaze_elf32_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+   microblaze*-*)
+     targ_defvec=microblaze_elf32_vec
+     targ_selvecs=microblaze_elf32_le_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+ #ifdef BFD64
+diff --git a/bfd/configure b/bfd/configure
+index 0340ed541b..ff5ae4706c 100755
+--- a/bfd/configure
++++ b/bfd/configure
+@@ -14903,6 +14903,8 @@ do
+     s390_elf64_vec)		 tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
++    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     sh_coff_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_le_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_small_vec)		 tb="$tb coff-sh.lo $coff" ;;
+diff --git a/bfd/configure.ac b/bfd/configure.ac
+index 8e86f8399c..408092d3be 100644
+--- a/bfd/configure.ac
++++ b/bfd/configure.ac
+@@ -639,6 +639,8 @@ do
+     s390_elf64_vec)		 tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo elf64.lo $elf"; want64=true; target_size=64 ;;
++    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     sh_coff_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_le_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_small_vec)		 tb="$tb coff-sh.lo $coff" ;;
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index 05a3f767e2..194920b20b 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -23,7 +23,24 @@
+ #include "bfd.h"
+ #include "libbfd.h"
+ 
+-const bfd_arch_info_type bfd_microblaze_arch =
++const bfd_arch_info_type bfd_microblaze_arch[] =
++{
++#if BFD_DEFAULT_TARGET_SIZE == 64
++{
++  64,		  		/* 32 bits in a word.  */
++  64,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  FALSE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  &bfd_microblaze_arch[1]  	/* Next in list.  */
++},
+ {
+   32,				/* Bits in a word.  */
+   32,				/* Bits in an address.  */
+@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_arch =
+   bfd_arch_default_fill,	/* Default fill.  */
+   NULL,				/* Next in list.  */
+   0 /* Maximum offset of a reloc from the start of an insn.  */
++}
++#else
++{
++  32,		  		/* 32 bits in a word.  */
++  32,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  TRUE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  &bfd_microblaze_arch[1]   	/* Next in list.  */
++},
++{
++  64,		  		/* 32 bits in a word.  */
++  64,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  FALSE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  NULL,			  	/* Next in list.  */
++  0  /* Maximum offset of a reloc from the start of an insn.  */
++}
++#endif
+ };
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+new file mode 100644
+index 0000000000..a357388115
+--- /dev/null
++++ b/bfd/elf64-microblaze.c
+@@ -0,0 +1,3610 @@
++/* Xilinx MicroBlaze-specific support for 32-bit ELF
++
++   Copyright (C) 2009-2016 Free Software Foundation, Inc.
++
++   This file is part of BFD, the Binary File Descriptor library.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program; if not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
++   Boston, MA 02110-1301, USA.  */
++
++
++int dbg1 = 0;
++
++#include "sysdep.h"
++#include "bfd.h"
++#include "bfdlink.h"
++#include "libbfd.h"
++#include "elf-bfd.h"
++#include "elf/microblaze.h"
++#include <assert.h>
++
++#define	USE_RELA	/* Only USE_REL is actually significant, but this is
++			   here are a reminder...  */
++#define INST_WORD_SIZE 4
++
++static int ro_small_data_pointer = 0;
++static int rw_small_data_pointer = 0;
++
++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
++
++static reloc_howto_type microblaze_elf_howto_raw[] =
++{
++   /* This reloc does nothing.  */
++   HOWTO (R_MICROBLAZE_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          0,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_NONE", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
++   /* A standard 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A standard PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_PCREL",   	/* Name.  */
++          TRUE,			/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit PCREL relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_64_PCREL,/* Type.  */
++          0,			/* Rightshift.  */
++          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          64,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_64_PCREL", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* The low half of a PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL_LO,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_signed, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_32_PCREL_LO", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit relocation.  Table entry not really used.  */
++   HOWTO (R_MICROBLAZE_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* The low half of a 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_LO,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_signed, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_LO", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Read-only small data section relocation.  */
++   HOWTO (R_MICROBLAZE_SRO32,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_SRO32", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Read-write small data area relocation.  */
++   HOWTO (R_MICROBLAZE_SRW32,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_SRW32", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
++          0,         /* Rightshift.  */
++          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
++          32,           /* Bitsize.  */
++          TRUE,         /* PC_relative.  */
++          0,           /* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          FALSE,       /* Partial Inplace.  */
++          0,          /* Source Mask.  */
++          0,         /* Dest Mask.  */
++          FALSE),       /* PC relative offset?  */
++
++   /* This reloc does nothing.  Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          0,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_64_NONE",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
++   /* Symbol Op Symbol relocation.  */
++   HOWTO (R_MICROBLAZE_32_SYM_OP_SYM,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_SYM_OP_SYM",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable hierarchy.  */
++   HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type.  */
++          0,                     /* Rightshift.  */
++          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
++          0,                     /* Bitsize.  */
++          FALSE,                 /* PC_relative.  */
++          0,                     /* Bitpos.  */
++          complain_overflow_dont,/* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_GNU_VTINHERIT", /* Name.  */
++          FALSE,                 /* Partial Inplace.  */
++          0,                     /* Source Mask.  */
++          0,                     /* Dest Mask.  */
++          FALSE),                /* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable member usage.  */
++   HOWTO (R_MICROBLAZE_GNU_VTENTRY,   /* Type.  */
++          0,                     /* Rightshift.  */
++          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
++          0,                     /* Bitsize.  */
++          FALSE,                 /* PC_relative.  */
++          0,                     /* Bitpos.  */
++          complain_overflow_dont,/* Complain on overflow.  */
++          _bfd_elf_rel_vtable_reloc_fn,  /* Special Function.  */
++          "R_MICROBLAZE_GNU_VTENTRY", /* Name.  */
++          FALSE,                 /* Partial Inplace.  */
++          0,                     /* Source Mask.  */
++          0,                     /* Dest Mask.  */
++          FALSE),                /* PC relative offset?  */
++
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GOTPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit GOT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GOT_64",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A 64 bit PLT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_PLT_64,  /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_PLT_64",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_REL,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_REL", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_JUMP_SLOT", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GLOB_DAT", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GOTOFF_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A 32 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_32,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GOTOFF_32", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* COPY relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_COPY,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_COPY", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Marker relocs for TLS.  */
++   HOWTO (R_MICROBLAZE_TLS,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc,	/* special_function */
++	 "R_MICROBLAZE_TLS",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,			/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSGD,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSGD",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,			/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSLD,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSLD",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes the load module index of the load module that contains the
++      definition of its TLS sym.  */
++   HOWTO (R_MICROBLAZE_TLSDTPMOD32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPMOD32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  Used for initializing GOT */
++   HOWTO (R_MICROBLAZE_TLSDTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  */
++   HOWTO (R_MICROBLAZE_TLSDTPREL64,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPREL64",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSGOTTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++};
++
++#ifndef NUM_ELEM
++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
++#endif
++
++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done.  */
++
++static void
++microblaze_elf_howto_init (void)
++{
++  unsigned int i;
++
++  for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
++    {
++      unsigned int type;
++
++      type = microblaze_elf_howto_raw[i].type;
++
++      BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
++
++      microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
++    }
++}
++
++static reloc_howto_type *
++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
++				  bfd_reloc_code_real_type code)
++{
++  enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
++
++  switch (code)
++    {
++    case BFD_RELOC_NONE:
++      microblaze_reloc = R_MICROBLAZE_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_NONE:
++      microblaze_reloc = R_MICROBLAZE_64_NONE;
++      break;
++    case BFD_RELOC_32:
++      microblaze_reloc = R_MICROBLAZE_32;
++      break;
++      /* RVA is treated the same as 32 */
++    case BFD_RELOC_RVA:
++      microblaze_reloc = R_MICROBLAZE_32;
++      break;
++    case BFD_RELOC_32_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL;
++      break;
++    case BFD_RELOC_64_PCREL:
++      microblaze_reloc = R_MICROBLAZE_64_PCREL;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
++      break;
++    case BFD_RELOC_64:
++      microblaze_reloc = R_MICROBLAZE_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO:
++      microblaze_reloc = R_MICROBLAZE_32_LO;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_ROSDA:
++      microblaze_reloc = R_MICROBLAZE_SRO32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_RWSDA:
++      microblaze_reloc = R_MICROBLAZE_SRW32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++      microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
++      break;
++    case BFD_RELOC_VTABLE_INHERIT:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
++      break;
++    case BFD_RELOC_VTABLE_ENTRY:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTPC:
++      microblaze_reloc = R_MICROBLAZE_GOTPC_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOT:
++      microblaze_reloc = R_MICROBLAZE_GOT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_PLT:
++      microblaze_reloc = R_MICROBLAZE_PLT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGD:
++      microblaze_reloc = R_MICROBLAZE_TLSGD;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSLD:
++      microblaze_reloc = R_MICROBLAZE_TLSLD;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_COPY:
++      microblaze_reloc = R_MICROBLAZE_COPY;
++      break;
++    default:
++      return (reloc_howto_type *) NULL;
++    }
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  return microblaze_elf_howto_table [(int) microblaze_reloc];
++};
++
++static reloc_howto_type *
++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
++				  const char *r_name)
++{
++  unsigned int i;
++
++  for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
++    if (microblaze_elf_howto_raw[i].name != NULL
++	&& strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
++      return &microblaze_elf_howto_raw[i];
++
++  return NULL;
++}
++
++/* Set the howto pointer for a RCE ELF reloc.  */
++
++static bfd_boolean
++microblaze_elf_info_to_howto (bfd * abfd,
++			      arelent * cache_ptr,
++			      Elf_Internal_Rela * dst)
++{
++  unsigned int r_type;
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  r_type = ELF64_R_TYPE (dst->r_info);
++  if (r_type >= R_MICROBLAZE_max)
++    {
++      /* xgettext:c-format */
++      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
++			  abfd, r_type);
++      bfd_set_error (bfd_error_bad_value);
++      return FALSE;
++    }
++
++  cache_ptr->howto = microblaze_elf_howto_table [r_type];
++  return TRUE;
++}
++
++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
++
++static bfd_boolean
++microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
++{
++  if (name[0] == 'L' && name[1] == '.')
++    return TRUE;
++
++  if (name[0] == '$' && name[1] == 'L')
++    return TRUE;
++
++  /* With gcc, the labels go back to starting with '.', so we accept
++     the generic ELF local label syntax as well.  */
++  return _bfd_elf_is_local_label_name (abfd, name);
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf64_mb_dyn_relocs
++{
++  struct elf64_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
++/* ELF linker hash entry.  */
++
++struct elf64_mb_link_hash_entry
++{
++  struct elf_link_hash_entry elf;
++
++  /* Track dynamic relocs copied for this symbol.  */
++  struct elf64_mb_dyn_relocs *dyn_relocs;
++
++  /* TLS Reference Types for the symbol; Updated by check_relocs */
++#define TLS_GD     1  /* GD reloc. */
++#define TLS_LD     2  /* LD reloc. */
++#define TLS_TPREL  4  /* TPREL reloc, => IE. */
++#define TLS_DTPREL 8  /* DTPREL reloc, => LD. */
++#define TLS_TLS    16 /* Any TLS reloc.  */
++  unsigned char tls_mask;
++
++};
++
++#define IS_TLS_GD(x)     (x == (TLS_TLS | TLS_GD))
++#define IS_TLS_LD(x)     (x == (TLS_TLS | TLS_LD))
++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
++#define IS_TLS_NONE(x)   (x == 0)
++
++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
++
++/* ELF linker hash table.  */
++
++struct elf64_mb_link_hash_table
++{
++  struct elf_link_hash_table elf;
++
++  /* Short-cuts to get to dynamic linker sections.  */
++  asection *sgot;
++  asection *sgotplt;
++  asection *srelgot;
++  asection *splt;
++  asection *srelplt;
++  asection *sdynbss;
++  asection *srelbss;
++
++  /* Small local sym to section mapping cache.  */
++  struct sym_cache sym_sec;
++
++  /* TLS Local Dynamic GOT Entry */
++  union {
++    bfd_signed_vma refcount;
++    bfd_vma offset;
++  } tlsld_got;
++};
++
++/* Nonzero if this section has TLS related relocations.  */
++#define has_tls_reloc sec_flg0
++
++/* Get the ELF linker hash table from a link_info structure.  */
++
++#define elf64_mb_hash_table(p)				\
++  (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
++  == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL)
++
++/* Create an entry in a microblaze ELF linker hash table.  */
++
++static struct bfd_hash_entry *
++link_hash_newfunc (struct bfd_hash_entry *entry,
++		   struct bfd_hash_table *table,
++		   const char *string)
++{
++  /* Allocate the structure if it has not already been allocated by a
++     subclass.  */
++  if (entry == NULL)
++    {
++      entry = bfd_hash_allocate (table,
++				 sizeof (struct elf64_mb_link_hash_entry));
++      if (entry == NULL)
++	return entry;
++    }
++
++  /* Call the allocation method of the superclass.  */
++  entry = _bfd_elf_link_hash_newfunc (entry, table, string);
++  if (entry != NULL)
++    {
++      struct elf64_mb_link_hash_entry *eh;
++
++      eh = (struct elf64_mb_link_hash_entry *) entry;
++      eh->tls_mask = 0;
++    }
++
++  return entry;
++}
++
++/* Create a mb ELF linker hash table.  */
++
++static struct bfd_link_hash_table *
++microblaze_elf_link_hash_table_create (bfd *abfd)
++{
++  struct elf64_mb_link_hash_table *ret;
++  size_t amt = sizeof (struct elf64_mb_link_hash_table);
++
++  ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
++  if (ret == NULL)
++    return NULL;
++
++  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
++				      sizeof (struct elf64_mb_link_hash_entry),
++				      MICROBLAZE_ELF_DATA))
++    {
++      free (ret);
++      return NULL;
++    }
++
++  return &ret->elf.root;
++}
++
++/* Set the values of the small data pointers.  */
++
++static void
++microblaze_elf_final_sdp (struct bfd_link_info *info)
++{
++  struct bfd_link_hash_entry *h;
++
++  h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    ro_small_data_pointer = (h->u.def.value
++                             + h->u.def.section->output_section->vma
++                             + h->u.def.section->output_offset);
++
++  h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    rw_small_data_pointer = (h->u.def.value
++                             + h->u.def.section->output_section->vma
++                             + h->u.def.section->output_offset);
++}
++
++static bfd_vma
++dtprel_base (struct bfd_link_info *info)
++{
++  /* If tls_sec is NULL, we should have signalled an error already.  */
++  if (elf_hash_table (info)->tls_sec == NULL)
++    return 0;
++  return elf_hash_table (info)->tls_sec->vma;
++}
++
++/* The size of the thread control block.  */
++#define TCB_SIZE	8
++
++/* Output a simple dynamic relocation into SRELOC.  */
++
++static void
++microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
++					  asection *sreloc,
++					  unsigned long reloc_index,
++					  unsigned long indx,
++					  int r_type,
++					  bfd_vma offset,
++					  bfd_vma addend)
++{
++
++  Elf_Internal_Rela rel;
++
++  rel.r_info = ELF64_R_INFO (indx, r_type);
++  rel.r_offset = offset;
++  rel.r_addend = addend;
++
++  bfd_elf64_swap_reloca_out (output_bfd, &rel,
++              (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
++}
++
++/* This code is taken from elf64-m32r.c
++   There is some attempt to make this function usable for many architectures,
++   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
++   if only to serve as a learning tool.
++
++   The RELOCATE_SECTION function is called by the new ELF backend linker
++   to handle the relocations for a section.
++
++   The relocs are always passed as Rela structures; if the section
++   actually uses Rel structures, the r_addend field will always be
++   zero.
++
++   This function is responsible for adjust the section contents as
++   necessary, and (if using Rela relocs and generating a
++   relocatable output file) adjusting the reloc addend as
++   necessary.
++
++   This function does not have to worry about setting the reloc
++   address or the reloc symbol index.
++
++   LOCAL_SYMS is a pointer to the swapped in local symbols.
++
++   LOCAL_SECTIONS is an array giving the section in the input file
++   corresponding to the st_shndx field of each local symbol.
++
++   The global hash table entry for the global symbols can be found
++   via elf_sym_hashes (input_bfd).
++
++   When generating relocatable output, this function must handle
++   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
++   going to be the section symbol corresponding to the output
++   section, which means that the addend must be adjusted
++   accordingly.  */
++
++static bfd_boolean
++microblaze_elf_relocate_section (bfd *output_bfd,
++			         struct bfd_link_info *info,
++			         bfd *input_bfd,
++			         asection *input_section,
++			         bfd_byte *contents,
++			         Elf_Internal_Rela *relocs,
++			         Elf_Internal_Sym *local_syms,
++			         asection **local_sections)
++{
++  struct elf64_mb_link_hash_table *htab;
++  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
++  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
++  Elf_Internal_Rela *rel, *relend;
++  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
++  /* Assume success.  */
++  bfd_boolean ret = TRUE;
++  asection *sreloc;
++  bfd_vma *local_got_offsets;
++  unsigned int tls_type;
++
++  if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
++    microblaze_elf_howto_init ();
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  local_got_offsets = elf_local_got_offsets (input_bfd);
++
++  sreloc = elf_section_data (input_section)->sreloc;
++
++  rel = relocs;
++  relend = relocs + input_section->reloc_count;
++  for (; rel < relend; rel++)
++    {
++      int r_type;
++      reloc_howto_type *howto;
++      unsigned long r_symndx;
++      bfd_vma addend = rel->r_addend;
++      bfd_vma offset = rel->r_offset;
++      struct elf_link_hash_entry *h;
++      Elf_Internal_Sym *sym;
++      asection *sec;
++      const char *sym_name;
++      bfd_reloc_status_type r = bfd_reloc_ok;
++      const char *errmsg = NULL;
++      bfd_boolean unresolved_reloc = FALSE;
++
++      h = NULL;
++      r_type = ELF64_R_TYPE (rel->r_info);
++      tls_type = 0;
++
++      if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
++	{
++	  (*_bfd_error_handler) (_("%s: unknown relocation type %d"),
++				 bfd_get_filename (input_bfd), (int) r_type);
++	  bfd_set_error (bfd_error_bad_value);
++	  ret = FALSE;
++	  continue;
++	}
++
++      howto = microblaze_elf_howto_table[r_type];
++      r_symndx = ELF64_R_SYM (rel->r_info);
++
++      if (bfd_link_relocatable (info))
++	{
++	  /* This is a relocatable link.  We don't have to change
++	     anything, unless the reloc is against a section symbol,
++	     in which case we have to adjust according to where the
++	     section symbol winds up in the output section.  */
++	  sec = NULL;
++	  if (r_symndx >= symtab_hdr->sh_info)
++	    /* External symbol.  */
++	    continue;
++
++	  /* Local symbol.  */
++	  sym = local_syms + r_symndx;
++	  sym_name = "<local symbol>";
++	  /* STT_SECTION: symbol is associated with a section.  */
++	  if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
++	    /* Symbol isn't associated with a section.  Nothing to do.  */
++	    continue;
++
++	  sec = local_sections[r_symndx];
++	  addend += sec->output_offset + sym->st_value;
++#ifndef USE_REL
++	  /* This can't be done for USE_REL because it doesn't mean anything
++	     and elf_link_input_bfd asserts this stays zero.  */
++	  /* rel->r_addend = addend; */
++#endif
++
++#ifndef USE_REL
++	  /* Addends are stored with relocs.  We're done.  */
++	  continue;
++#else /* USE_REL */
++	  /* If partial_inplace, we need to store any additional addend
++	     back in the section.  */
++	  if (!howto->partial_inplace)
++	    continue;
++	  /* ??? Here is a nice place to call a special_function like handler.  */
++	  r = _bfd_relocate_contents (howto, input_bfd, addend,
++				      contents + offset);
++#endif /* USE_REL */
++	}
++      else
++	{
++	  bfd_vma relocation;
++	  bfd_boolean resolved_to_zero;
++
++	  /* This is a final link.  */
++	  sym = NULL;
++	  sec = NULL;
++	  unresolved_reloc = FALSE;
++
++	  if (r_symndx < symtab_hdr->sh_info)
++	    {
++	      /* Local symbol.  */
++	      sym = local_syms + r_symndx;
++	      sec = local_sections[r_symndx];
++	      if (sec == 0)
++		continue;
++	      sym_name = "<local symbol>";
++	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
++	      /* r_addend may have changed if the reference section was
++		 a merge section.  */
++	      addend = rel->r_addend;
++	    }
++	  else
++	    {
++	      /* External symbol.  */
++	      bfd_boolean warned ATTRIBUTE_UNUSED;
++	      bfd_boolean ignored ATTRIBUTE_UNUSED;
++
++	      RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
++				       r_symndx, symtab_hdr, sym_hashes,
++				       h, sec, relocation,
++				       unresolved_reloc, warned, ignored);
++	      sym_name = h->root.root.string;
++	    }
++
++	  /* Sanity check the address.  */
++	  if (offset > bfd_get_section_limit (input_bfd, input_section))
++	    {
++	      r = bfd_reloc_outofrange;
++	      goto check_reloc;
++	    }
++
++	  resolved_to_zero = (h != NULL
++			      && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
++
++	  switch ((int) r_type)
++	    {
++	    case (int) R_MICROBLAZE_SRO32 :
++	      {
++		const char *name;
++
++		/* Only relocate if the symbol is defined.  */
++		if (sec)
++		  {
++		    name = bfd_section_name (sec);
++
++		    if (strcmp (name, ".sdata2") == 0
++			|| strcmp (name, ".sbss2") == 0)
++		      {
++			if (ro_small_data_pointer == 0)
++			  microblaze_elf_final_sdp (info);
++			if (ro_small_data_pointer == 0)
++			  {
++			    ret = FALSE;
++			    r = bfd_reloc_undefined;
++			    goto check_reloc;
++			  }
++
++			/* At this point `relocation' contains the object's
++			   address.  */
++			relocation -= ro_small_data_pointer;
++			/* Now it contains the offset from _SDA2_BASE_.  */
++			r = _bfd_final_link_relocate (howto, input_bfd,
++						      input_section,
++						      contents, offset,
++						      relocation, addend);
++		      }
++		    else
++		      {
++			_bfd_error_handler
++			  /* xgettext:c-format */
++			  (_("%pB: the target (%s) of an %s relocation"
++			     " is in the wrong section (%pA)"),
++			   input_bfd,
++			   sym_name,
++			   microblaze_elf_howto_table[(int) r_type]->name,
++			   sec);
++			/*bfd_set_error (bfd_error_bad_value); ??? why? */
++			ret = FALSE;
++			continue;
++		      }
++		  }
++	      }
++	      break;
++
++	    case (int) R_MICROBLAZE_SRW32 :
++	      {
++		const char *name;
++
++		/* Only relocate if the symbol is defined.  */
++		if (sec)
++		  {
++		    name = bfd_section_name (sec);
++
++		    if (strcmp (name, ".sdata") == 0
++			|| strcmp (name, ".sbss") == 0)
++		      {
++			if (rw_small_data_pointer == 0)
++			  microblaze_elf_final_sdp (info);
++			if (rw_small_data_pointer == 0)
++			  {
++			    ret = FALSE;
++			    r = bfd_reloc_undefined;
++			    goto check_reloc;
++			  }
++
++			/* At this point `relocation' contains the object's
++			   address.  */
++			relocation -= rw_small_data_pointer;
++			/* Now it contains the offset from _SDA_BASE_.  */
++			r = _bfd_final_link_relocate (howto, input_bfd,
++						      input_section,
++						      contents, offset,
++						      relocation, addend);
++		      }
++		    else
++		      {
++			_bfd_error_handler
++			  /* xgettext:c-format */
++			  (_("%pB: the target (%s) of an %s relocation"
++			     " is in the wrong section (%pA)"),
++			   input_bfd,
++			   sym_name,
++			   microblaze_elf_howto_table[(int) r_type]->name,
++			   sec);
++			/*bfd_set_error (bfd_error_bad_value); ??? why? */
++			ret = FALSE;
++			continue;
++		      }
++		  }
++	      }
++	      break;
++
++	    case (int) R_MICROBLAZE_32_SYM_OP_SYM:
++	      break; /* Do nothing.  */
++
++	    case (int) R_MICROBLAZE_GOTPC_64:
++	      relocation = htab->sgotplt->output_section->vma
++		+ htab->sgotplt->output_offset;
++	      relocation -= (input_section->output_section->vma
++			     + input_section->output_offset
++			     + offset + INST_WORD_SIZE);
++	      relocation += addend;
++	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++	                  contents + offset + endian);
++	      bfd_put_16 (input_bfd, relocation & 0xffff,
++	                  contents + offset + endian + INST_WORD_SIZE);
++	      break;
++
++	    case (int) R_MICROBLAZE_PLT_64:
++	      {
++		bfd_vma immediate;
++		if (htab->splt != NULL && h != NULL
++		    && h->plt.offset != (bfd_vma) -1)
++		  {
++		    relocation = (htab->splt->output_section->vma
++				  + htab->splt->output_offset
++				  + h->plt.offset);
++		    unresolved_reloc = FALSE;
++		    immediate = relocation - (input_section->output_section->vma
++					      + input_section->output_offset
++					      + offset + INST_WORD_SIZE);
++		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++		                contents + offset + endian);
++		    bfd_put_16 (input_bfd, immediate & 0xffff,
++		                contents + offset + endian + INST_WORD_SIZE);
++		  }
++		else
++		  {
++		    relocation -= (input_section->output_section->vma
++				   + input_section->output_offset
++				   + offset + INST_WORD_SIZE);
++		    immediate = relocation;
++		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++		                contents + offset + endian);
++		    bfd_put_16 (input_bfd, immediate & 0xffff,
++		                contents + offset + endian + INST_WORD_SIZE);
++		  }
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_TLSGD:
++	      tls_type = (TLS_TLS | TLS_GD);
++	      goto dogot;
++	    case (int) R_MICROBLAZE_TLSLD:
++	      tls_type = (TLS_TLS | TLS_LD);
++	    dogot:
++	    case (int) R_MICROBLAZE_GOT_64:
++	      {
++		bfd_vma *offp;
++		bfd_vma off, off2;
++		unsigned long indx;
++		bfd_vma static_value;
++
++		bfd_boolean need_relocs = FALSE;
++		if (htab->sgot == NULL)
++		  abort ();
++
++		indx = 0;
++		offp = NULL;
++
++		/* 1. Identify GOT Offset;
++		   2. Compute Static Values
++		   3. Process Module Id, Process Offset
++		   4. Fixup Relocation with GOT offset value. */
++
++		/* 1. Determine GOT Offset to use : TLS_LD, global, local */
++		if (IS_TLS_LD (tls_type))
++		  offp = &htab->tlsld_got.offset;
++		else if (h != NULL)
++		  {
++		    if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1)
++			offp = &h->got.offset;
++		    else
++			abort ();
++		  }
++		else
++		  {
++		    if (local_got_offsets == NULL)
++		      abort ();
++		    offp = &local_got_offsets[r_symndx];
++		  }
++
++		if (!offp)
++		  abort ();
++
++		off = (*offp) & ~1;
++		off2 = off;
++
++		if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
++		  off2 = off + 4;
++
++		/* Symbol index to use for relocs */
++		if (h != NULL)
++		  {
++		    bfd_boolean dyn =
++			elf_hash_table (info)->dynamic_sections_created;
++
++		    if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
++							 bfd_link_pic (info),
++							 h)
++			&& (!bfd_link_pic (info)
++			    || !SYMBOL_REFERENCES_LOCAL (info, h)))
++		      indx = h->dynindx;
++		  }
++
++		/* Need to generate relocs ? */
++		if ((bfd_link_pic (info) || indx != 0)
++		    && (h == NULL
++		    || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++			&& !resolved_to_zero)
++		    || h->root.type != bfd_link_hash_undefweak))
++		  need_relocs = TRUE;
++
++		/* 2. Compute/Emit Static value of r-expression */
++		static_value = relocation + addend;
++
++		/* 3. Process module-id and offset */
++		if (! ((*offp) & 1) )
++		  {
++		    bfd_vma got_offset;
++
++		    got_offset = (htab->sgot->output_section->vma
++				  + htab->sgot->output_offset
++				  + off);
++
++		    /* Process module-id */
++		    if (IS_TLS_LD(tls_type))
++		      {
++			if (! bfd_link_pic (info))
++			  {
++			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++			  }
++			else
++			  {
++			    microblaze_elf_output_dynamic_relocation (output_bfd,
++			      htab->srelgot, htab->srelgot->reloc_count++,
++			      /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
++			      got_offset, 0);
++			  }
++		      }
++		    else if (IS_TLS_GD(tls_type))
++		      {
++		        if (! need_relocs)
++			  {
++			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++			  }
++		        else
++			  {
++			    microblaze_elf_output_dynamic_relocation (output_bfd,
++			      htab->srelgot,
++			      htab->srelgot->reloc_count++,
++			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
++			      got_offset, indx ? 0 : static_value);
++			  }
++		      }
++
++		    /* Process Offset */
++		    if (htab->srelgot == NULL)
++		      abort ();
++
++		    got_offset = (htab->sgot->output_section->vma
++				  + htab->sgot->output_offset
++				  + off2);
++		    if (IS_TLS_LD(tls_type))
++		      {
++		        /* For LD, offset should be 0 */
++		        *offp |= 1;
++		        bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2);
++		      }
++		    else if (IS_TLS_GD(tls_type))
++		      {
++			*offp |= 1;
++			static_value -= dtprel_base(info);
++			if (need_relocs)
++			  microblaze_elf_output_dynamic_relocation
++			    (output_bfd,
++			     htab->elf.srelgot,
++			     htab->elf.srelgot->reloc_count++,
++			     /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
++			     got_offset, indx ? 0 : static_value);
++			else
++			  bfd_put_32 (output_bfd, static_value,
++				      htab->elf.sgot->contents + off2);
++		      }
++		    else
++		      {
++			bfd_put_32 (output_bfd, static_value,
++				    htab->elf.sgot->contents + off2);
++
++			/* Relocs for dyn symbols generated by
++			   finish_dynamic_symbols */
++			if (bfd_link_pic (info) && h == NULL)
++			  {
++			    *offp |= 1;
++			    microblaze_elf_output_dynamic_relocation
++			      (output_bfd,
++			       htab->elf.srelgot,
++			       htab->elf.srelgot->reloc_count++,
++			       /* symindex= */ indx, R_MICROBLAZE_REL,
++			       got_offset, static_value);
++			  }
++		      }
++		  }
++
++		/* 4. Fixup Relocation with GOT offset value
++		      Compute relative address of GOT entry for applying
++		      the current relocation */
++		relocation = htab->elf.sgot->output_section->vma
++			     + htab->elf.sgot->output_offset
++			     + off
++			     - htab->elf.sgotplt->output_section->vma
++			     - htab->elf.sgotplt->output_offset;
++
++		/* Apply Current Relocation */
++		bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++		            contents + offset + endian);
++		bfd_put_16 (input_bfd, relocation & 0xffff,
++		            contents + offset + endian + INST_WORD_SIZE);
++
++		unresolved_reloc = FALSE;
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_GOTOFF_64:
++	      {
++		bfd_vma immediate;
++		unsigned short lo, high;
++		relocation += addend;
++		relocation -= (htab->elf.sgotplt->output_section->vma
++			       + htab->elf.sgotplt->output_offset);
++		/* Write this value into correct location.  */
++		immediate = relocation;
++		lo = immediate & 0x0000ffff;
++		high = (immediate >> 16) & 0x0000ffff;
++		bfd_put_16 (input_bfd, high, contents + offset + endian);
++		bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian);
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_GOTOFF_32:
++	      {
++		relocation += addend;
++		relocation -= (htab->elf.sgotplt->output_section->vma
++			       + htab->elf.sgotplt->output_offset);
++		/* Write this value into correct location.  */
++		bfd_put_32 (input_bfd, relocation, contents + offset);
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_TLSDTPREL64:
++	      relocation += addend;
++	      relocation -= dtprel_base(info);
++	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			  contents + offset + endian);
++	      bfd_put_16 (input_bfd, relocation & 0xffff,
++			  contents + offset + endian + INST_WORD_SIZE);
++	      break;
++	    case (int) R_MICROBLAZE_64_PCREL :
++	    case (int) R_MICROBLAZE_64:
++	    case (int) R_MICROBLAZE_32:
++	      {
++		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
++		   from removed linkonce sections, or sections discarded by
++		   a linker script.  */
++		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
++		  {
++		    relocation += addend;
++		    if (r_type == R_MICROBLAZE_32)
++		      bfd_put_32 (input_bfd, relocation, contents + offset);
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_64_PCREL)
++			  relocation -= (input_section->output_section->vma
++					 + input_section->output_offset
++					 + offset + INST_WORD_SIZE);
++			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			            contents + offset + endian);
++			bfd_put_16 (input_bfd, relocation & 0xffff,
++			            contents + offset + endian + INST_WORD_SIZE);
++		      }
++		    break;
++		  }
++
++		if ((bfd_link_pic (info)
++		     && (h == NULL
++			 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++			     && !resolved_to_zero)
++			 || h->root.type != bfd_link_hash_undefweak)
++		     && (!howto->pc_relative
++			 || (h != NULL
++			     && h->dynindx != -1
++			     && (!info->symbolic
++				 || !h->def_regular))))
++		    || (!bfd_link_pic (info)
++			&& h != NULL
++			&& h->dynindx != -1
++			&& !h->non_got_ref
++			&& ((h->def_dynamic
++			     && !h->def_regular)
++			    || h->root.type == bfd_link_hash_undefweak
++			    || h->root.type == bfd_link_hash_undefined)))
++		  {
++		    Elf_Internal_Rela outrel;
++		    bfd_byte *loc;
++		    bfd_boolean skip;
++
++		    /* When generating a shared object, these relocations
++		       are copied into the output file to be resolved at run
++		       time.  */
++
++		    BFD_ASSERT (sreloc != NULL);
++
++		    skip = FALSE;
++
++		    outrel.r_offset =
++		      _bfd_elf_section_offset (output_bfd, info, input_section,
++					       rel->r_offset);
++		    if (outrel.r_offset == (bfd_vma) -1)
++		      skip = TRUE;
++		    else if (outrel.r_offset == (bfd_vma) -2)
++		      skip = TRUE;
++		    outrel.r_offset += (input_section->output_section->vma
++					+ input_section->output_offset);
++
++		    if (skip)
++		      memset (&outrel, 0, sizeof outrel);
++		    /* h->dynindx may be -1 if the symbol was marked to
++		       become local.  */
++		    else if (h != NULL
++			     && ((! info->symbolic && h->dynindx != -1)
++				 || !h->def_regular))
++		      {
++			BFD_ASSERT (h->dynindx != -1);
++			outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
++			outrel.r_addend = addend;
++		      }
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_32)
++			  {
++			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
++			    outrel.r_addend = relocation + addend;
++			  }
++			else
++			  {
++			    BFD_FAIL ();
++			    (*_bfd_error_handler)
++			      (_("%B: probably compiled without -fPIC?"),
++			       input_bfd);
++			    bfd_set_error (bfd_error_bad_value);
++			    return FALSE;
++			  }
++		      }
++
++		    loc = sreloc->contents;
++		    loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
++		    bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
++		    break;
++		  }
++		else
++		  {
++		    relocation += addend;
++		    if (r_type == R_MICROBLAZE_32)
++		      bfd_put_32 (input_bfd, relocation, contents + offset);
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_64_PCREL)
++			  relocation -= (input_section->output_section->vma
++					 + input_section->output_offset
++					 + offset + INST_WORD_SIZE);
++			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			            contents + offset + endian);
++			bfd_put_16 (input_bfd, relocation & 0xffff,
++			            contents + offset + endian + INST_WORD_SIZE);
++		      }
++		    break;
++		  }
++	      }
++
++	    default :
++	      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
++					    contents, offset,
++					    relocation, addend);
++	      break;
++	    }
++	}
++
++    check_reloc:
++
++      if (r != bfd_reloc_ok)
++	{
++	  /* FIXME: This should be generic enough to go in a utility.  */
++	  const char *name;
++
++	  if (h != NULL)
++	    name = h->root.root.string;
++	  else
++	    {
++	      name = (bfd_elf_string_from_elf_section
++		      (input_bfd, symtab_hdr->sh_link, sym->st_name));
++	      if (name == NULL || *name == '\0')
++		name = bfd_section_name (sec);
++	    }
++
++	  if (errmsg != NULL)
++	    goto common_error;
++
++	  switch (r)
++	    {
++	    case bfd_reloc_overflow:
++	      (*info->callbacks->reloc_overflow)
++		(info, (h ? &h->root : NULL), name, howto->name,
++		 (bfd_vma) 0, input_bfd, input_section, offset);
++	      break;
++
++	    case bfd_reloc_undefined:
++	      (*info->callbacks->undefined_symbol)
++		(info, name, input_bfd, input_section, offset, TRUE);
++	      break;
++
++	    case bfd_reloc_outofrange:
++	      errmsg = _("internal error: out of range error");
++	      goto common_error;
++
++	    case bfd_reloc_notsupported:
++	      errmsg = _("internal error: unsupported relocation error");
++	      goto common_error;
++
++	    case bfd_reloc_dangerous:
++	      errmsg = _("internal error: dangerous error");
++	      goto common_error;
++
++	    default:
++	      errmsg = _("internal error: unknown error");
++	      /* Fall through.  */
++	    common_error:
++	      (*info->callbacks->warning) (info, errmsg, name, input_bfd,
++					   input_section, offset);
++	      break;
++	    }
++	}
++    }
++
++  return ret;
++}
++
++/* Merge backend specific data from an object file to the output
++   object file when linking.
++
++   Note: We only use this hook to catch endian mismatches.  */
++static bfd_boolean
++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
++{
++  /* Check if we have the same endianess.  */
++  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
++    return FALSE;
++
++  return TRUE;
++}
++
++
++/* Calculate fixup value for reference.  */
++
++static int
++calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
++{
++  bfd_vma end = start + size;
++  int i, fixup = 0;
++
++  if (sec == NULL || sec->relax == NULL)
++    return 0;
++
++  /* Look for addr in relax table, total fixup value.  */
++  for (i = 0; i < sec->relax_count; i++)
++    {
++      if (end <= sec->relax[i].addr)
++        break;
++      if ((end != start) && (start > sec->relax[i].addr))
++        continue;
++      fixup += sec->relax[i].size;
++    }
++  return fixup;
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   a 32-bit instruction.  */
++static void
++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr = bfd_get_32 (abfd, bfd_addr);
++    instr &= ~0x0000ffff;
++    instr |= (val & 0x0000ffff);
++    bfd_put_32 (abfd, instr, bfd_addr);
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   two consecutive 32-bit instructions.  */
++static void
++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr_hi;
++    unsigned long instr_lo;
++
++    instr_hi = bfd_get_32 (abfd, bfd_addr);
++    instr_hi &= ~0x0000ffff;
++    instr_hi |= ((val >> 16) & 0x0000ffff);
++    bfd_put_32 (abfd, instr_hi, bfd_addr);
++
++    instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
++    instr_lo &= ~0x0000ffff;
++    instr_lo |= (val & 0x0000ffff);
++    bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
++}
++
++static bfd_boolean
++microblaze_elf_relax_section (bfd *abfd,
++			      asection *sec,
++			      struct bfd_link_info *link_info,
++			      bfd_boolean *again)
++{
++  Elf_Internal_Shdr *symtab_hdr;
++  Elf_Internal_Rela *internal_relocs;
++  Elf_Internal_Rela *free_relocs = NULL;
++  Elf_Internal_Rela *irel, *irelend;
++  bfd_byte *contents = NULL;
++  bfd_byte *free_contents = NULL;
++  int rel_count;
++  unsigned int shndx;
++  int i, sym_index;
++  asection *o;
++  struct elf_link_hash_entry *sym_hash;
++  Elf_Internal_Sym *isymbuf, *isymend;
++  Elf_Internal_Sym *isym;
++  int symcount;
++  int offset;
++  bfd_vma src, dest;
++
++  /* We only do this once per section.  We may be able to delete some code
++     by running multiple passes, but it is not worth it.  */
++  *again = FALSE;
++
++  /* Only do this for a text section.  */
++  if (bfd_link_relocatable (link_info)
++      || (sec->flags & SEC_RELOC) == 0
++      || (sec->reloc_count == 0)
++      || (sec->flags & SEC_CODE) == 0)
++    return TRUE;
++
++  BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
++
++  /* If this is the first time we have been called for this section,
++     initialize the cooked size.  */
++  if (sec->size == 0)
++    sec->size = sec->rawsize;
++
++  /* Get symbols for this section.  */
++  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
++  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
++  symcount =  symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (isymbuf == NULL)
++    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
++ 			     	    0, NULL, NULL, NULL);
++  BFD_ASSERT (isymbuf != NULL);
++
++  internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
++  if (internal_relocs == NULL)
++    goto error_return;
++  if (! link_info->keep_memory)
++    free_relocs = internal_relocs;
++
++  sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
++						  * sizeof (struct relax_table));
++  if (sec->relax == NULL)
++    goto error_return;
++  sec->relax_count = 0;
++
++  irelend = internal_relocs + sec->reloc_count;
++  rel_count = 0;
++  for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++    {
++      bfd_vma symval;
++      if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
++	  && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ))
++	continue; /* Can't delete this reloc.  */
++
++      /* Get the section contents.  */
++      if (contents == NULL)
++	{
++	  if (elf_section_data (sec)->this_hdr.contents != NULL)
++	    contents = elf_section_data (sec)->this_hdr.contents;
++	  else
++	    {
++	      contents = (bfd_byte *) bfd_malloc (sec->size);
++	      if (contents == NULL)
++		goto error_return;
++	      free_contents = contents;
++
++	      if (!bfd_get_section_contents (abfd, sec, contents,
++					     (file_ptr) 0, sec->size))
++		goto error_return;
++              elf_section_data (sec)->this_hdr.contents = contents;
++	    }
++	}
++
++      /* Get the value of the symbol referred to by the reloc.  */
++      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++	{
++	  /* A local symbol.  */
++	  asection *sym_sec;
++
++	  isym = isymbuf + ELF64_R_SYM (irel->r_info);
++          if (isym->st_shndx == SHN_UNDEF)
++	    sym_sec = bfd_und_section_ptr;
++	  else if (isym->st_shndx == SHN_ABS)
++	    sym_sec = bfd_abs_section_ptr;
++	  else if (isym->st_shndx == SHN_COMMON)
++	    sym_sec = bfd_com_section_ptr;
++	  else
++	    sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
++
++	  symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
++	}
++      else
++	{
++	  unsigned long indx;
++	  struct elf_link_hash_entry *h;
++
++	  indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
++	  h = elf_sym_hashes (abfd)[indx];
++	  BFD_ASSERT (h != NULL);
++
++          if (h->root.type != bfd_link_hash_defined
++	      && h->root.type != bfd_link_hash_defweak)
++	    /* This appears to be a reference to an undefined
++	       symbol.  Just ignore it--it will be caught by the
++	       regular reloc processing.  */
++	    continue;
++
++	  symval = (h->root.u.def.value
++		    + h->root.u.def.section->output_section->vma
++		    + h->root.u.def.section->output_offset);
++	}
++
++      /* If this is a PC-relative reloc, subtract the instr offset from
++         the symbol value.  */
++      if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
++	{
++	  symval = symval + irel->r_addend
++	    - (irel->r_offset
++	       + sec->output_section->vma
++	       + sec->output_offset);
++        }
++      else
++	symval += irel->r_addend;
++
++      if ((symval & 0xffff8000) == 0)
++	{
++          /* We can delete this instruction.  */
++	  sec->relax[sec->relax_count].addr = irel->r_offset;
++	  sec->relax[sec->relax_count].size = INST_WORD_SIZE;
++	  sec->relax_count++;
++
++	  /* Rewrite relocation type.  */
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++	    {
++	    case R_MICROBLAZE_64_PCREL:
++	      irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_PCREL_LO);
++	      break;
++	    case R_MICROBLAZE_64:
++              irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_LO);
++	      break;
++	    default:
++	      /* Cannot happen.  */
++	      BFD_ASSERT (FALSE);
++            }
++        }
++    } /* Loop through all relocations.  */
++
++  /* Loop through the relocs again, and see if anything needs to change.  */
++  if (sec->relax_count > 0)
++    {
++      shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
++      rel_count = 0;
++      sec->relax[sec->relax_count].addr = sec->size;
++
++      for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++        {
++	  bfd_vma nraddr;
++
++          /* Get the new reloc address.  */
++	  nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++	    {
++	    default:
++	      break;
++	    case R_MICROBLAZE_64_PCREL:
++	      break;
++	    case R_MICROBLAZE_64:
++	    case R_MICROBLAZE_32_LO:
++	      /* If this reloc is against a symbol defined in this
++	         section, we must check the addend to see it will put the value in
++	         range to be adjusted, and hence must be changed.  */
++	      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++	        {
++		  isym = isymbuf + ELF64_R_SYM (irel->r_info);
++		  /* Only handle relocs against .text.  */
++		  if (isym->st_shndx == shndx
++		      && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
++		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
++	        }
++	      break;
++	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
++	    case R_MICROBLAZE_64_NONE:
++	      {
++	        /* This was a PC-relative 64-bit instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++	        bfd_vma target_address;
++		target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
++		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
++		efix = calc_fixup (target_address, 0, sec);
++		irel->r_addend -= (efix - sfix);
++    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
++                                       + INST_WORD_SIZE, irel->r_addend);
++	      }
++	      break;
++	    }
++          irel->r_offset = nraddr;
++        } /* Change all relocs in this section.  */
++
++      /* Look through all other sections.  */
++      for (o = abfd->sections; o != NULL; o = o->next)
++        {
++          Elf_Internal_Rela *irelocs;
++          Elf_Internal_Rela *irelscan, *irelscanend;
++          bfd_byte *ocontents;
++
++          if (o == sec
++              || (o->flags & SEC_RELOC) == 0
++              || o->reloc_count == 0)
++            continue;
++
++          /* We always cache the relocs.  Perhaps, if info->keep_memory is
++             FALSE, we should free them, if we are permitted to.  */
++
++          irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE);
++          if (irelocs == NULL)
++            goto error_return;
++
++          ocontents = NULL;
++          irelscanend = irelocs + o->reloc_count;
++          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
++            {
++              if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++		      if (elf_section_data (o)->this_hdr.contents != NULL)
++		          ocontents = elf_section_data (o)->this_hdr.contents;
++		      else
++		        {
++		          /* We always cache the section contents.
++			     Perhaps, if info->keep_memory is FALSE, we
++			     should free them, if we are permitted to.  */
++
++		          if (o->rawsize == 0)
++			      o->rawsize = o->size;
++		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++		          if (ocontents == NULL)
++			      goto error_return;
++		          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++		          elf_section_data (o)->this_hdr.contents = ocontents;
++		        }
++		    }
++
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++                {
++	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* Look at the reloc only if the value has been resolved.  */
++                  if (isym->st_shndx == shndx
++                      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                    {
++                      if (ocontents == NULL)
++                        {
++                          if (elf_section_data (o)->this_hdr.contents != NULL)
++                            ocontents = elf_section_data (o)->this_hdr.contents;
++                          else
++                            {
++                              /* We always cache the section contents.
++                                 Perhaps, if info->keep_memory is FALSE, we
++                                 should free them, if we are permitted to.  */
++		              if (o->rawsize == 0)
++			        o->rawsize = o->size;
++                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                              if (ocontents == NULL)
++                                goto error_return;
++                              if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                             (file_ptr) 0,
++							     o->rawsize))
++                                goto error_return;
++                              elf_section_data (o)->this_hdr.contents = ocontents;
++                            }
++
++                        }
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                    }
++		  else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
++		    {
++		      isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		      /* Look at the reloc only if the value has been resolved.  */
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++              irelscan->r_addend -= calc_fixup (irelscan->r_addend
++							+ isym->st_value,
++							0,
++							sec);
++		    }
++		}
++	      else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
++		       || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO))
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++		      bfd_vma target_address;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++
++		      unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++		      immediate = instr & 0x0000ffff;
++		      target_address = immediate;
++		      offset = calc_fixup (target_address, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                             irelscan->r_addend);
++		    }
++		}
++
++	      if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64)
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++          immediate = (instr_hi & 0x0000ffff) << 16;
++          immediate |= (instr_lo & 0x0000ffff);
++		      offset = calc_fixup (irelscan->r_addend, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++		    }
++		}
++	      else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++		      bfd_vma target_address;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++          immediate = (instr_hi & 0x0000ffff) << 16;
++          immediate |= (instr_lo & 0x0000ffff);
++		      target_address = immediate;
++		      offset = calc_fixup (target_address, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_64 (abfd, ocontents
++                                             + irelscan->r_offset, immediate);
++		    }
++		}
++            }
++        }
++
++      /* Adjust the local symbols defined in this section.  */
++      isymend = isymbuf + symtab_hdr->sh_info;
++      for (isym = isymbuf; isym < isymend; isym++)
++        {
++          if (isym->st_shndx == shndx)
++            {
++              isym->st_value -= calc_fixup (isym->st_value, 0, sec);
++              if (isym->st_size)
++                isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
++            }
++        }
++
++      /* Now adjust the global symbols defined in this section.  */
++      isym = isymbuf + symtab_hdr->sh_info;
++      symcount =  (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
++      for (sym_index = 0; sym_index < symcount; sym_index++)
++        {
++          sym_hash = elf_sym_hashes (abfd)[sym_index];
++          if ((sym_hash->root.type == bfd_link_hash_defined
++                  || sym_hash->root.type == bfd_link_hash_defweak)
++              && sym_hash->root.u.def.section == sec)
++            {
++              sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
++                                                        0, sec);
++              if (sym_hash->size)
++                sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
++                                              sym_hash->size, sec);
++            }
++        }
++
++      /* Physically move the code and change the cooked size.  */
++      dest = sec->relax[0].addr;
++      for (i = 0; i < sec->relax_count; i++)
++        {
++          int len;
++          src = sec->relax[i].addr + sec->relax[i].size;
++          len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size;
++
++          memmove (contents + dest, contents + src, len);
++          sec->size -= sec->relax[i].size;
++          dest += len;
++        }
++
++      elf_section_data (sec)->relocs = internal_relocs;
++      free_relocs = NULL;
++
++      elf_section_data (sec)->this_hdr.contents = contents;
++      free_contents = NULL;
++
++      symtab_hdr->contents = (bfd_byte *) isymbuf;
++    }
++
++  if (free_relocs != NULL)
++    {
++      free (free_relocs);
++      free_relocs = NULL;
++    }
++
++  if (free_contents != NULL)
++    {
++      if (!link_info->keep_memory)
++	free (free_contents);
++      else
++	/* Cache the section contents for elf_link_input_bfd.  */
++	elf_section_data (sec)->this_hdr.contents = contents;
++      free_contents = NULL;
++    }
++
++  if (sec->relax_count == 0)
++    {
++      *again = FALSE;
++      free (sec->relax);
++      sec->relax = NULL;
++    }
++  else
++    *again = TRUE;
++  return TRUE;
++
++ error_return:
++  if (free_relocs != NULL)
++    free (free_relocs);
++  if (free_contents != NULL)
++    free (free_contents);
++  if (sec->relax != NULL)
++    {
++      free (sec->relax);
++      sec->relax = NULL;
++      sec->relax_count = 0;
++    }
++  return FALSE;
++}
++
++/* Return the section that should be marked against GC for a given
++   relocation.  */
++
++static asection *
++microblaze_elf_gc_mark_hook (asection *sec,
++			     struct bfd_link_info * info,
++     			     Elf_Internal_Rela * rel,
++     			     struct elf_link_hash_entry * h,
++     			     Elf_Internal_Sym * sym)
++{
++  if (h != NULL)
++    switch (ELF64_R_TYPE (rel->r_info))
++      {
++      case R_MICROBLAZE_GNU_VTINHERIT:
++      case R_MICROBLAZE_GNU_VTENTRY:
++	return NULL;
++      }
++
++  return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
++}
++
++/* Update the got entry reference counts for the section being removed.  */
++
++static bfd_boolean
++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
++     			      struct bfd_link_info * info ATTRIBUTE_UNUSED,
++     			      asection * sec ATTRIBUTE_UNUSED,
++     			      const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
++{
++  return TRUE;
++}
++
++/* PIC support.  */
++
++#define PLT_ENTRY_SIZE 16
++
++#define PLT_ENTRY_WORD_0  0xb0000000          /* "imm 0".  */
++#define PLT_ENTRY_WORD_1  0xe9940000          /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT.  */
++#define PLT_ENTRY_WORD_1_NOPIC  0xe9800000    /* "lwi r12,r0,0" - non-PIC object.  */
++#define PLT_ENTRY_WORD_2  0x98186000          /* "brad r12".  */
++#define PLT_ENTRY_WORD_3  0x80000000          /* "nop".  */
++
++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
++   shortcuts to them in our hash table.  */
++
++static bfd_boolean
++create_got_section (bfd *dynobj, struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++
++  if (! _bfd_elf_create_got_section (dynobj, info))
++    return FALSE;
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  htab->sgot = bfd_get_linker_section (dynobj, ".got");
++  htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt");
++  if (!htab->sgot || !htab->sgotplt)
++    return FALSE;
++
++  if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL)
++    htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got");
++  if (htab->srelgot == NULL
++      || ! bfd_set_section_flags (htab->srelgot, SEC_ALLOC
++                                  | SEC_LOAD
++                                  | SEC_HAS_CONTENTS
++                                  | SEC_IN_MEMORY
++                                  | SEC_LINKER_CREATED
++                                  | SEC_READONLY)
++      || ! bfd_set_section_alignment (htab->srelgot, 2))
++    return FALSE;
++  return TRUE;
++}
++
++static bfd_boolean
++update_local_sym_info (bfd *abfd,
++		       Elf_Internal_Shdr *symtab_hdr,
++		       unsigned long r_symndx,
++		       unsigned int tls_type)
++{
++  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
++  unsigned char *local_got_tls_masks;
++
++  if (local_got_refcounts == NULL)
++    {
++      bfd_size_type size = symtab_hdr->sh_info;
++
++      size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
++      local_got_refcounts = bfd_zalloc (abfd, size);
++      if (local_got_refcounts == NULL)
++        return FALSE;
++      elf_local_got_refcounts (abfd) = local_got_refcounts;
++    }
++
++  local_got_tls_masks =
++         (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
++  local_got_tls_masks[r_symndx] |= tls_type;
++  local_got_refcounts[r_symndx] += 1;
++
++  return TRUE;
++}
++/* Look through the relocs for a section during the first phase.  */
++
++static bfd_boolean
++microblaze_elf_check_relocs (bfd * abfd,
++			     struct bfd_link_info * info,
++     			     asection * sec,
++			     const Elf_Internal_Rela * relocs)
++{
++  Elf_Internal_Shdr *           symtab_hdr;
++  struct elf_link_hash_entry ** sym_hashes;
++  struct elf_link_hash_entry ** sym_hashes_end;
++  const Elf_Internal_Rela *     rel;
++  const Elf_Internal_Rela *     rel_end;
++  struct elf64_mb_link_hash_table *htab;
++  asection *sreloc = NULL;
++
++  if (bfd_link_relocatable (info))
++    return TRUE;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
++  sym_hashes = elf_sym_hashes (abfd);
++  sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (!elf_bad_symtab (abfd))
++    sym_hashes_end -= symtab_hdr->sh_info;
++
++  rel_end = relocs + sec->reloc_count;
++
++  for (rel = relocs; rel < rel_end; rel++)
++    {
++      unsigned int r_type;
++      struct elf_link_hash_entry * h;
++      unsigned long r_symndx;
++      unsigned char tls_type = 0;
++
++      r_symndx = ELF64_R_SYM (rel->r_info);
++      r_type = ELF64_R_TYPE (rel->r_info);
++
++      if (r_symndx < symtab_hdr->sh_info)
++        h = NULL;
++      else
++	{
++	  h = sym_hashes [r_symndx - symtab_hdr->sh_info];
++	  while (h->root.type == bfd_link_hash_indirect
++		 || h->root.type == bfd_link_hash_warning)
++	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
++	}
++
++      switch (r_type)
++        {
++	  /* This relocation describes the C++ object vtable hierarchy.
++	     Reconstruct it for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTINHERIT:
++          if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
++            return FALSE;
++          break;
++
++	  /* This relocation describes which C++ vtable entries are actually
++	     used.  Record for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTENTRY:
++          if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
++            return FALSE;
++          break;
++
++	  /* This relocation requires .plt entry.  */
++        case R_MICROBLAZE_PLT_64:
++          if (h != NULL)
++	    {
++	      h->needs_plt = 1;
++	      h->plt.refcount += 1;
++	    }
++          break;
++
++	  /* This relocation requires .got entry.  */
++        case R_MICROBLAZE_TLSGD:
++          tls_type |= (TLS_TLS | TLS_GD);
++          goto dogottls;
++        case R_MICROBLAZE_TLSLD:
++          tls_type |= (TLS_TLS | TLS_LD);
++        dogottls:
++          sec->has_tls_reloc = 1;
++        case R_MICROBLAZE_GOT_64:
++          if (htab->sgot == NULL)
++            {
++              if (htab->elf.dynobj == NULL)
++                htab->elf.dynobj = abfd;
++              if (!create_got_section (htab->elf.dynobj, info))
++                return FALSE;
++            }
++          if (h != NULL)
++	    {
++	      h->got.refcount += 1;
++	      elf64_mb_hash_entry (h)->tls_mask |= tls_type;
++	    }
++          else
++	    {
++	      if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
++		return FALSE;
++	    }
++          break;
++
++        case R_MICROBLAZE_64:
++        case R_MICROBLAZE_64_PCREL:
++        case R_MICROBLAZE_32:
++          {
++            if (h != NULL && !bfd_link_pic (info))
++	      {
++		/* we may need a copy reloc.  */
++		h->non_got_ref = 1;
++
++		/* we may also need a .plt entry.  */
++		h->plt.refcount += 1;
++		if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
++		  h->pointer_equality_needed = 1;
++	      }
++
++
++	    /* If we are creating a shared library, and this is a reloc
++	       against a global symbol, or a non PC relative reloc
++	       against a local symbol, then we need to copy the reloc
++	       into the shared library.  However, if we are linking with
++	       -Bsymbolic, we do not need to copy a reloc against a
++	       global symbol which is defined in an object we are
++	       including in the link (i.e., DEF_REGULAR is set).  At
++	       this point we have not seen all the input files, so it is
++	       possible that DEF_REGULAR is not set now but will be set
++	       later (it is never cleared).  In case of a weak definition,
++	       DEF_REGULAR may be cleared later by a strong definition in
++	       a shared library.  We account for that possibility below by
++	       storing information in the relocs_copied field of the hash
++	       table entry.  A similar situation occurs when creating
++	       shared libraries and symbol visibility changes render the
++	       symbol local.
++
++	       If on the other hand, we are creating an executable, we
++	       may need to keep relocations for symbols satisfied by a
++	       dynamic library if we manage to avoid copy relocs for the
++	       symbol.  */
++
++            if ((bfd_link_pic (info)
++                 && (sec->flags & SEC_ALLOC) != 0
++                 && (r_type != R_MICROBLAZE_64_PCREL
++                     || (h != NULL
++			 && (! info->symbolic
++			     || h->root.type == bfd_link_hash_defweak
++			     || !h->def_regular))))
++                || (!bfd_link_pic (info)
++                    && (sec->flags & SEC_ALLOC) != 0
++                    && h != NULL
++                    && (h->root.type == bfd_link_hash_defweak
++                        || !h->def_regular)))
++              {
++                struct elf64_mb_dyn_relocs *p;
++                struct elf64_mb_dyn_relocs **head;
++
++                /* When creating a shared object, we must copy these
++                   relocs into the output file.  We create a reloc
++                   section in dynobj and make room for the reloc.  */
++
++		if (sreloc == NULL)
++		  {
++		    bfd *dynobj;
++
++		    if (htab->elf.dynobj == NULL)
++		      htab->elf.dynobj = abfd;
++		    dynobj = htab->elf.dynobj;
++
++		    sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
++								  2, abfd, 1);
++		    if (sreloc == NULL)
++		      return FALSE;
++		  }
++
++		/* If this is a global symbol, we count the number of
++		   relocations we need for this symbol.  */
++		if (h != NULL)
++		  head = &h->dyn_relocs;
++		else
++		  {
++		    /* Track dynamic relocs needed for local syms too.
++		       We really need local syms available to do this
++		       easily.  Oh well.  */
++
++		    asection *s;
++		    Elf_Internal_Sym *isym;
++		    void *vpp;
++
++		    isym = bfd_sym_from_r_symndx (&htab->sym_sec,
++						  abfd, r_symndx);
++		    if (isym == NULL)
++		      return FALSE;
++
++		    s = bfd_section_from_elf_index (abfd, isym->st_shndx);
++		    if (s == NULL)
++		      return FALSE;
++
++		    vpp = &elf_section_data (s)->local_dynrel;
++		    head = (struct elf64_mb_dyn_relocs **) vpp;
++		  }
++
++		p = *head;
++		if (p == NULL || p->sec != sec)
++		  {
++		    size_t amt = sizeof *p;
++		    p = ((struct elf64_mb_dyn_relocs *)
++			 bfd_alloc (htab->elf.dynobj, amt));
++		    if (p == NULL)
++		      return FALSE;
++		    p->next = *head;
++		    *head = p;
++		    p->sec = sec;
++		    p->count = 0;
++		    p->pc_count = 0;
++		  }
++
++		p->count += 1;
++		if (r_type == R_MICROBLAZE_64_PCREL)
++		  p->pc_count += 1;
++	      }
++          }
++          break;
++        }
++    }
++
++  return TRUE;
++}
++
++static bfd_boolean
++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (!htab->sgot && !create_got_section (dynobj, info))
++    return FALSE;
++
++  if (!_bfd_elf_create_dynamic_sections (dynobj, info))
++    return FALSE;
++
++  htab->splt = bfd_get_linker_section (dynobj, ".plt");
++  htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
++  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
++  if (!bfd_link_pic (info))
++    htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
++
++  if (!htab->splt || !htab->srelplt || !htab->sdynbss
++      || (!bfd_link_pic (info) && !htab->srelbss))
++    abort ();
++
++  return TRUE;
++}
++
++/* Copy the extra info we tack onto an elf_link_hash_entry.  */
++
++static void
++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
++				     struct elf_link_hash_entry *dir,
++				     struct elf_link_hash_entry *ind)
++{
++  struct elf64_mb_link_hash_entry *edir, *eind;
++
++  edir = (struct elf64_mb_link_hash_entry *) dir;
++  eind = (struct elf64_mb_link_hash_entry *) ind;
++
++  if (eind->dyn_relocs != NULL)
++    {
++      if (edir->dyn_relocs != NULL)
++	{
++	  struct elf64_mb_dyn_relocs **pp;
++	  struct elf64_mb_dyn_relocs *p;
++
++	  if (ind->root.type == bfd_link_hash_indirect)
++	    abort ();
++
++	  /* Add reloc counts against the weak sym to the strong sym
++	     list.  Merge any entries against the same section.  */
++	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
++	    {
++	      struct elf64_mb_dyn_relocs *q;
++
++	      for (q = edir->dyn_relocs; q != NULL; q = q->next)
++		if (q->sec == p->sec)
++		  {
++		    q->pc_count += p->pc_count;
++		    q->count += p->count;
++		    *pp = p->next;
++		    break;
++		  }
++	      if (q == NULL)
++		pp = &p->next;
++	    }
++	  *pp = edir->dyn_relocs;
++	}
++
++      edir->dyn_relocs = eind->dyn_relocs;
++      eind->dyn_relocs = NULL;
++    }
++
++  edir->tls_mask |= eind->tls_mask;
++
++  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
++}
++
++static bfd_boolean
++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
++				      struct elf_link_hash_entry *h)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry * eh;
++  struct elf64_mb_dyn_relocs *p;
++  asection *sdynbss;
++  asection *s, *srel;
++  unsigned int power_of_two;
++  bfd *dynobj;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  /* If this is a function, put it in the procedure linkage table.  We
++     will fill in the contents of the procedure linkage table later,
++     when we know the address of the .got section.  */
++  if (h->type == STT_FUNC
++      || h->needs_plt)
++    {
++      if (h->plt.refcount <= 0
++	  || SYMBOL_CALLS_LOCAL (info, h)
++	  || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
++	      && h->root.type == bfd_link_hash_undefweak))
++	{
++	  /* This case can occur if we saw a PLT reloc in an input
++	     file, but the symbol was never referred to by a dynamic
++	     object, or if all references were garbage collected.  In
++	     such a case, we don't actually need to build a procedure
++	     linkage table, and we can just do a PC32 reloc instead.  */
++	  h->plt.offset = (bfd_vma) -1;
++	  h->needs_plt = 0;
++	}
++
++      return TRUE;
++    }
++  else
++    /* It's possible that we incorrectly decided a .plt reloc was
++       needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
++       check_relocs.  We can't decide accurately between function and
++       non-function syms in check-relocs;  Objects loaded later in
++       the link may change h->type.  So fix it now.  */
++    h->plt.offset = (bfd_vma) -1;
++
++  /* If this is a weak symbol, and there is a real definition, the
++     processor independent code will have arranged for us to see the
++     real definition first, and we can just use the same value.  */
++  if (h->is_weakalias)
++    {
++      struct elf_link_hash_entry *def = weakdef (h);
++      BFD_ASSERT (def->root.type == bfd_link_hash_defined);
++      h->root.u.def.section = def->root.u.def.section;
++      h->root.u.def.value = def->root.u.def.value;
++      return TRUE;
++    }
++
++  /* This is a reference to a symbol defined by a dynamic object which
++     is not a function.  */
++
++  /* If we are creating a shared library, we must presume that the
++     only references to the symbol are via the global offset table.
++     For such cases we need not do anything here; the relocations will
++     be handled correctly by relocate_section.  */
++  if (bfd_link_pic (info))
++    return TRUE;
++
++  /* If there are no references to this symbol that do not use the
++     GOT, we don't need to generate a copy reloc.  */
++  if (!h->non_got_ref)
++    return TRUE;
++
++  /* If -z nocopyreloc was given, we won't generate them either.  */
++  if (info->nocopyreloc)
++    {
++      h->non_got_ref = 0;
++      return TRUE;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  for (p = eh->dyn_relocs; p != NULL; p = p->next)
++    {
++      s = p->sec->output_section;
++      if (s != NULL && (s->flags & SEC_READONLY) != 0)
++	break;
++    }
++
++  /* If we didn't find any dynamic relocs in read-only sections, then
++     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
++  if (!_bfd_elf_readonly_dynrelocs (h))
++    {
++      h->non_got_ref = 0;
++      return TRUE;
++    }
++
++  /* We must allocate the symbol in our .dynbss section, which will
++     become part of the .bss section of the executable.  There will be
++     an entry for this symbol in the .dynsym section.  The dynamic
++     object will contain position independent code, so all references
++     from the dynamic object to this symbol will go through the global
++     offset table.  The dynamic linker will use the .dynsym entry to
++     determine the address it must put in the global offset table, so
++     both the dynamic object and the regular object will refer to the
++     same memory location for the variable.  */
++
++  /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
++     to copy the initial value out of the dynamic object and into the
++     runtime process image.  */
++  if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
++    {
++      s = htab->elf.sdynrelro;
++      srel = htab->elf.sreldynrelro;
++    }
++  else
++    {
++      s = htab->elf.sdynbss;
++      srel = htab->elf.srelbss;
++    }
++  if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
++    {
++      srel->size += sizeof (Elf64_External_Rela);
++      h->needs_copy = 1;
++    }
++
++  /* We need to figure out the alignment required for this symbol.  I
++     have no idea how ELF linkers handle this.  */
++  power_of_two = bfd_log2 (h->size);
++  if (power_of_two > 3)
++    power_of_two = 3;
++
++  /* Apply the required alignment.  */
++  s->size = BFD_ALIGN (s->size, (bfd_size_type) (1 << power_of_two));
++  if (power_of_two > s->alignment_power)
++    {
++      if (!bfd_set_section_alignment (s, power_of_two))
++	return FALSE;
++    }
++
++  /* Define the symbol as being at this point in the section.  */
++  h->root.u.def.section = s;
++  h->root.u.def.value = s->size;
++
++  /* Increment the section size to make room for the symbol.  */
++  s->size += h->size;
++  return TRUE;
++}
++
++/* Allocate space in .plt, .got and associated reloc sections for
++   dynamic relocs.  */
++
++static bfd_boolean
++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
++{
++  struct bfd_link_info *info;
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh;
++  struct elf64_mb_dyn_relocs *p;
++
++  if (h->root.type == bfd_link_hash_indirect)
++    return TRUE;
++
++  info = (struct bfd_link_info *) dat;
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (htab->elf.dynamic_sections_created
++      && h->plt.refcount > 0)
++    {
++      /* Make sure this symbol is output as a dynamic symbol.
++	 Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return FALSE;
++        }
++
++      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
++        {
++          asection *s = htab->splt;
++
++          /* The first entry in .plt is reserved.  */
++          if (s->size == 0)
++            s->size = PLT_ENTRY_SIZE;
++
++          h->plt.offset = s->size;
++
++          /* If this symbol is not defined in a regular file, and we are
++             not generating a shared library, then set the symbol to this
++             location in the .plt.  This is required to make function
++             pointers compare as equal between the normal executable and
++             the shared library.  */
++          if (! bfd_link_pic (info)
++              && !h->def_regular)
++            {
++              h->root.u.def.section = s;
++              h->root.u.def.value = h->plt.offset;
++            }
++
++          /* Make room for this entry.  */
++          s->size += PLT_ENTRY_SIZE;
++
++	  /* We also need to make an entry in the .got.plt section, which
++	     will be placed in the .got section by the linker script.  */
++	  htab->elf.sgotplt->size += 4;
++
++	  /* We also need to make an entry in the .rel.plt section.  */
++	  htab->elf.srelplt->size += sizeof (Elf32_External_Rela);
++	}
++      else
++        {
++          h->plt.offset = (bfd_vma) -1;
++          h->needs_plt = 0;
++        }
++    }
++  else
++    {
++      h->plt.offset = (bfd_vma) -1;
++      h->needs_plt = 0;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  if (h->got.refcount > 0)
++    {
++      unsigned int need;
++      asection *s;
++
++      /* Make sure this symbol is output as a dynamic symbol.
++         Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return FALSE;
++        }
++
++      need = 0;
++      if ((eh->tls_mask & TLS_TLS) != 0)
++        {
++          /* Handle TLS Symbol */
++          if ((eh->tls_mask & TLS_LD) != 0)
++            {
++              if (!eh->elf.def_dynamic)
++                /* We'll just use htab->tlsld_got.offset.  This should
++                   always be the case.  It's a little odd if we have
++                   a local dynamic reloc against a non-local symbol.  */
++                htab->tlsld_got.refcount += 1;
++              else
++                need += 8;
++            }
++          if ((eh->tls_mask & TLS_GD) != 0)
++            need += 8;
++        }
++      else
++        {
++          /* Regular (non-TLS) symbol */
++          need += 4;
++        }
++      if (need == 0)
++        {
++          h->got.offset = (bfd_vma) -1;
++        }
++      else
++	{
++	  s = htab->elf.sgot;
++	  h->got.offset = s->size;
++	  s->size += need;
++	  htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
++	}
++    }
++  else
++    h->got.offset = (bfd_vma) -1;
++
++  if (h->dyn_relocs == NULL)
++    return TRUE;
++
++  /* In the shared -Bsymbolic case, discard space allocated for
++     dynamic pc-relative relocs against symbols which turn out to be
++     defined in regular objects.  For the normal shared case, discard
++     space for pc-relative relocs that have become local due to symbol
++     visibility changes.  */
++
++  if (bfd_link_pic (info))
++    {
++      if (h->def_regular
++	  && (h->forced_local
++	      || info->symbolic))
++	{
++	  struct elf64_mb_dyn_relocs **pp;
++
++	  for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
++	    {
++	      p->count -= p->pc_count;
++	      p->pc_count = 0;
++	      if (p->count == 0)
++		*pp = p->next;
++	      else
++		pp = &p->next;
++	    }
++	}
++      else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
++	h->dyn_relocs = NULL;
++    }
++  else
++    {
++      /* For the non-shared case, discard space for relocs against
++	 symbols which turn out to need copy relocs or are not
++	 dynamic.  */
++
++      if (!h->non_got_ref
++	  && ((h->def_dynamic
++	       && !h->def_regular)
++	      || (htab->elf.dynamic_sections_created
++		  && (h->root.type == bfd_link_hash_undefweak
++		      || h->root.type == bfd_link_hash_undefined))))
++	{
++	  /* Make sure this symbol is output as a dynamic symbol.
++	     Undefined weak syms won't yet be marked as dynamic.  */
++	  if (h->dynindx == -1
++	      && !h->forced_local)
++	    {
++	      if (! bfd_elf_link_record_dynamic_symbol (info, h))
++		return FALSE;
++	    }
++
++	  /* If that succeeded, we know we'll be keeping all the
++	     relocs.  */
++	  if (h->dynindx != -1)
++	    goto keep;
++	}
++
++      h->dyn_relocs = NULL;
++
++    keep: ;
++    }
++
++  /* Finally, allocate space.  */
++  for (p = h->dyn_relocs; p != NULL; p = p->next)
++    {
++      asection *sreloc = elf_section_data (p->sec)->sreloc;
++      sreloc->size += p->count * sizeof (Elf64_External_Rela);
++    }
++
++  return TRUE;
++}
++
++/* Set the sizes of the dynamic sections.  */
++
++static bfd_boolean
++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
++				      struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++  bfd *dynobj;
++  asection *s;
++  bfd *ibfd;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  dynobj = htab->elf.dynobj;
++  BFD_ASSERT (dynobj != NULL);
++
++  /* Set up .got offsets for local syms, and space for local dynamic
++     relocs.  */
++  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
++    {
++      bfd_signed_vma *local_got;
++      bfd_signed_vma *end_local_got;
++      bfd_size_type locsymcount;
++      Elf_Internal_Shdr *symtab_hdr;
++      unsigned char *lgot_masks;
++      asection *srel;
++
++      if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
++        continue;
++
++      for (s = ibfd->sections; s != NULL; s = s->next)
++	{
++	  struct elf64_mb_dyn_relocs *p;
++
++	  for (p = ((struct elf64_mb_dyn_relocs *)
++		    elf_section_data (s)->local_dynrel);
++	       p != NULL;
++	       p = p->next)
++	    {
++	      if (!bfd_is_abs_section (p->sec)
++		  && bfd_is_abs_section (p->sec->output_section))
++		{
++		  /* Input section has been discarded, either because
++		     it is a copy of a linkonce section or due to
++		     linker script /DISCARD/, so we'll be discarding
++		     the relocs too.  */
++		}
++	      else if (p->count != 0)
++		{
++		  srel = elf_section_data (p->sec)->sreloc;
++		  srel->size += p->count * sizeof (Elf64_External_Rela);
++		  if ((p->sec->output_section->flags & SEC_READONLY) != 0)
++		    info->flags |= DF_TEXTREL;
++		}
++	    }
++	}
++
++      local_got = elf_local_got_refcounts (ibfd);
++      if (!local_got)
++        continue;
++
++      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
++      locsymcount = symtab_hdr->sh_info;
++      end_local_got = local_got + locsymcount;
++      lgot_masks = (unsigned char *) end_local_got;
++      s = htab->elf.sgot;
++      srel = htab->elf.srelgot;
++
++      for (; local_got < end_local_got; ++local_got, ++lgot_masks)
++	{
++	  if (*local_got > 0)
++	    {
++	      unsigned int need = 0;
++	      if ((*lgot_masks & TLS_TLS) != 0)
++		{
++		  if ((*lgot_masks & TLS_GD) != 0)
++		    need += 8;
++		  if ((*lgot_masks & TLS_LD) != 0)
++		    htab->tlsld_got.refcount += 1;
++		}
++	      else
++		need += 4;
++
++	      if (need == 0)
++		{
++		  *local_got = (bfd_vma) -1;
++		}
++	      else
++		{
++		  *local_got = s->size;
++		  s->size += need;
++		  if (bfd_link_pic (info))
++		    srel->size += need * (sizeof (Elf64_External_Rela) / 4);
++		}
++            }
++          else
++            *local_got = (bfd_vma) -1;
++        }
++    }
++
++  /* Allocate global sym .plt and .got entries, and space for global
++     sym dynamic relocs.  */
++  elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
++
++  if (htab->tlsld_got.refcount > 0)
++    {
++      htab->tlsld_got.offset = htab->elf.sgot->size;
++      htab->elf.sgot->size += 8;
++      if (bfd_link_pic (info))
++	htab->elf.srelgot->size += sizeof (Elf64_External_Rela);
++    }
++  else
++    htab->tlsld_got.offset = (bfd_vma) -1;
++
++  if (elf_hash_table (info)->dynamic_sections_created)
++    {
++      /* Make space for the trailing nop in .plt.  */
++      if (htab->elf.splt->size > 0)
++	htab->elf.splt->size += 4;
++    }
++
++  /* The check_relocs and adjust_dynamic_symbol entry points have
++     determined the sizes of the various dynamic sections.  Allocate
++     memory for them.  */
++  for (s = dynobj->sections; s != NULL; s = s->next)
++    {
++      const char *name;
++      bfd_boolean strip = FALSE;
++
++      if ((s->flags & SEC_LINKER_CREATED) == 0)
++        continue;
++
++      /* It's OK to base decisions on the section name, because none
++	 of the dynobj section names depend upon the input files.  */
++      name = bfd_section_name (s);
++
++      if (strncmp (name, ".rela", 5) == 0)
++	{
++	  if (s->size == 0)
++	    {
++	      /* If we don't need this section, strip it from the
++		 output file.  This is to handle .rela.bss and
++		 .rela.plt.  We must create it in
++		 create_dynamic_sections, because it must be created
++		 before the linker maps input sections to output
++		 sections.  The linker does that before
++		 adjust_dynamic_symbol is called, and it is that
++		 function which decides whether anything needs to go
++		 into these sections.  */
++	      strip = TRUE;
++	    }
++	  else
++	    {
++	      /* We use the reloc_count field as a counter if we need
++		 to copy relocs into the output file.  */
++	      s->reloc_count = 0;
++	    }
++	}
++      else if (s != htab->elf.splt
++	       && s != htab->elf.sgot
++	       && s != htab->elf.sgotplt
++	       && s != htab->elf.sdynbss
++	       && s != htab->elf.sdynrelro)
++	{
++	  /* It's not one of our sections, so don't allocate space.  */
++	  continue;
++	}
++
++      if (strip)
++        {
++          s->flags |= SEC_EXCLUDE;
++          continue;
++        }
++
++      /* Allocate memory for the section contents.  */
++      /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
++         Unused entries should be reclaimed before the section's contents
++         are written out, but at the moment this does not happen.  Thus in
++         order to prevent writing out garbage, we initialise the section's
++         contents to zero.  */
++      s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
++      if (s->contents == NULL && s->size != 0)
++        return FALSE;
++    }
++
++  if (elf_hash_table (info)->dynamic_sections_created)
++    {
++      /* Add some entries to the .dynamic section.  We fill in the
++	 values later, in microblaze_elf_finish_dynamic_sections, but we
++	 must add the entries now so that we get the correct size for
++	 the .dynamic section.  The DT_DEBUG entry is filled in by the
++	 dynamic linker and used by the debugger.  */
++#define add_dynamic_entry(TAG, VAL)			\
++      _bfd_elf_add_dynamic_entry (info, TAG, VAL)
++
++      if (bfd_link_executable (info))
++        {
++          if (!add_dynamic_entry (DT_DEBUG, 0))
++            return FALSE;
++        }
++
++      if (!add_dynamic_entry (DT_RELA, 0)
++          || !add_dynamic_entry (DT_RELASZ, 0)
++          || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela)))
++	return FALSE;
++
++      if (htab->splt->size != 0)
++        {
++          if (!add_dynamic_entry (DT_PLTGOT, 0)
++              || !add_dynamic_entry (DT_PLTRELSZ, 0)
++              || !add_dynamic_entry (DT_PLTREL, DT_RELA)
++              || !add_dynamic_entry (DT_JMPREL, 0)
++              || !add_dynamic_entry (DT_BIND_NOW, 1))
++            return FALSE;
++        }
++
++      if (info->flags & DF_TEXTREL)
++        {
++          if (!add_dynamic_entry (DT_TEXTREL, 0))
++            return FALSE;
++        }
++    }
++#undef add_dynamic_entry
++  return TRUE;
++}
++
++/* Finish up dynamic symbol handling.  We set the contents of various
++   dynamic sections here.  */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
++				      struct bfd_link_info *info,
++				      struct elf_link_hash_entry *h,
++				      Elf_Internal_Sym *sym)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (h->plt.offset != (bfd_vma) -1)
++    {
++      asection *splt;
++      asection *srela;
++      asection *sgotplt;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++      bfd_vma plt_index;
++      bfd_vma got_offset;
++      bfd_vma got_addr;
++
++      /* This symbol has an entry in the procedure linkage table.  Set
++         it up.  */
++      BFD_ASSERT (h->dynindx != -1);
++
++      splt = htab->splt;
++      srela = htab->srelplt;
++      sgotplt = htab->sgotplt;
++      BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
++
++      plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved.  */
++      got_offset = (plt_index + 3) * 4; /* 3 reserved ???  */
++      got_addr = got_offset;
++
++      /* For non-PIC objects we need absolute address of the GOT entry.  */
++      if (!bfd_link_pic (info))
++	got_addr += sgotplt->output_section->vma + sgotplt->output_offset;
++
++      /* Fill in the entry in the procedure linkage table.  */
++      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
++                  splt->contents + h->plt.offset);
++      if (bfd_link_pic (info))
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      else
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
++                  splt->contents + h->plt.offset + 8);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
++                  splt->contents + h->plt.offset + 12);
++
++      /* Any additions to the .got section??? */
++      /*      bfd_put_32 (output_bfd,
++	      splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
++	      sgotplt->contents + got_offset); */
++
++      /* Fill in the entry in the .rela.plt section.  */
++      rela.r_offset = (sgotplt->output_section->vma
++                       + sgotplt->output_offset
++                       + got_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
++      rela.r_addend = 0;
++      loc = srela->contents;
++      loc += plt_index * sizeof (Elf64_External_Rela);
++      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++
++      if (!h->def_regular)
++        {
++          /* Mark the symbol as undefined, rather than as defined in
++             the .plt section.  Zero the value.  */
++          sym->st_shndx = SHN_UNDEF;
++          sym->st_value = 0;
++        }
++    }
++
++  /* h->got.refcount to be checked ? */
++  if (h->got.offset != (bfd_vma) -1 &&
++      ! ((h->got.offset & 1) ||
++          IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
++    {
++      asection *sgot;
++      asection *srela;
++      bfd_vma offset;
++
++      /* This symbol has an entry in the global offset table.  Set it
++         up.  */
++
++      sgot = htab->elf.sgot;
++      srela = htab->elf.srelgot;
++      BFD_ASSERT (sgot != NULL && srela != NULL);
++
++      offset = (sgot->output_section->vma + sgot->output_offset
++		+ (h->got.offset &~ (bfd_vma) 1));
++
++      /* If this is a -Bsymbolic link, and the symbol is defined
++         locally, we just want to emit a RELATIVE reloc.  Likewise if
++         the symbol was forced to be local because of a version file.
++         The entry in the global offset table will already have been
++         initialized in the relocate_section function.  */
++      if (bfd_link_pic (info)
++          && ((info->symbolic && h->def_regular)
++	      || h->dynindx == -1))
++        {
++          asection *sec = h->root.u.def.section;
++          microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                    srela, srela->reloc_count++,
++                                                    /* symindex= */ 0,
++                                                    R_MICROBLAZE_REL, offset,
++                                                    h->root.u.def.value
++                                                    + sec->output_section->vma
++                                                    + sec->output_offset);
++        }
++      else
++        {
++          microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                    srela, srela->reloc_count++,
++                                                    h->dynindx,
++                                                    R_MICROBLAZE_GLOB_DAT,
++                                                    offset, 0);
++        }
++
++      bfd_put_32 (output_bfd, (bfd_vma) 0,
++                  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
++    }
++
++  if (h->needs_copy)
++    {
++      asection *s;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++
++      /* This symbols needs a copy reloc.  Set it up.  */
++
++      BFD_ASSERT (h->dynindx != -1);
++
++      s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss");
++      BFD_ASSERT (s != NULL);
++
++      rela.r_offset = (h->root.u.def.value
++                       + h->root.u.def.section->output_section->vma
++                       + h->root.u.def.section->output_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
++      rela.r_addend = 0;
++      loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
++      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++    }
++
++  /* Mark some specially defined symbols as absolute.  */
++  if (h == htab->elf.hdynamic
++      || h == htab->elf.hgot
++      || h == htab->elf.hplt)
++    sym->st_shndx = SHN_ABS;
++
++  return TRUE;
++}
++
++
++/* Finish up the dynamic sections.  */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
++					struct bfd_link_info *info)
++{
++  bfd *dynobj;
++  asection *sdyn, *sgot;
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  dynobj = htab->elf.dynobj;
++
++  sdyn = bfd_get_linker_section (dynobj, ".dynamic");
++
++  if (htab->elf.dynamic_sections_created)
++    {
++      asection *splt;
++      Elf64_External_Dyn *dyncon, *dynconend;
++
++      splt = bfd_get_linker_section (dynobj, ".plt");
++      BFD_ASSERT (splt != NULL && sdyn != NULL);
++
++      dyncon = (Elf64_External_Dyn *) sdyn->contents;
++      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
++      for (; dyncon < dynconend; dyncon++)
++        {
++          Elf_Internal_Dyn dyn;
++          const char *name;
++          bfd_boolean size;
++
++          bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
++
++          switch (dyn.d_tag)
++            {
++            case DT_PLTGOT:   name = ".got.plt"; size = FALSE; break;
++            case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break;
++            case DT_JMPREL:   name = ".rela.plt"; size = FALSE; break;
++            case DT_RELA:     name = ".rela.dyn"; size = FALSE; break;
++            case DT_RELASZ:   name = ".rela.dyn"; size = TRUE; break;
++            default:	  name = NULL; size = FALSE; break;
++            }
++
++          if (name != NULL)
++            {
++              asection *s;
++
++              s = bfd_get_section_by_name (output_bfd, name);
++              if (s == NULL)
++                dyn.d_un.d_val = 0;
++              else
++                {
++                  if (! size)
++                    dyn.d_un.d_ptr = s->vma;
++                  else
++                    dyn.d_un.d_val = s->size;
++                }
++              bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
++            }
++        }
++
++      /* Clear the first entry in the procedure linkage table,
++	 and put a nop in the last four bytes.  */
++      if (splt->size > 0)
++        {
++          memset (splt->contents, 0, PLT_ENTRY_SIZE);
++          bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
++                      splt->contents + splt->size - 4);
++        }
++
++      elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
++    }
++
++  /* Set the first entry in the global offset table to the address of
++     the dynamic section.  */
++  sgot = htab->elf.sgotplt;
++  if (sgot && sgot->size > 0)
++    {
++      if (sdyn == NULL)
++        bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
++      else
++        bfd_put_32 (output_bfd,
++                    sdyn->output_section->vma + sdyn->output_offset,
++                    sgot->contents);
++      elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
++    }
++
++  if (htab->elf.sgot && htab->elf.sgot->size > 0)
++    elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4;
++
++  return TRUE;
++}
++
++/* Hook called by the linker routine which adds symbols from an object
++   file.  We use it to put .comm items in .sbss, and not .bss.  */
++
++static bfd_boolean
++microblaze_elf_add_symbol_hook (bfd *abfd,
++			        struct bfd_link_info *info,
++			        Elf_Internal_Sym *sym,
++			        const char **namep ATTRIBUTE_UNUSED,
++			        flagword *flagsp ATTRIBUTE_UNUSED,
++			        asection **secp,
++			        bfd_vma *valp)
++{
++  if (sym->st_shndx == SHN_COMMON
++      && !bfd_link_relocatable (info)
++      && sym->st_size <= elf_gp_size (abfd))
++    {
++      /* Common symbols less than or equal to -G nn bytes are automatically
++	 put into .sbss.  */
++      *secp = bfd_make_section_old_way (abfd, ".sbss");
++      if (*secp == NULL
++	  || !bfd_set_section_flags (*secp, SEC_IS_COMMON))
++	return FALSE;
++
++      *valp = sym->st_size;
++    }
++
++  return TRUE;
++}
++
++#define TARGET_LITTLE_SYM      microblaze_elf64_le_vec
++#define TARGET_LITTLE_NAME     "elf64-microblazeel"
++
++#define TARGET_BIG_SYM          microblaze_elf64_vec
++#define TARGET_BIG_NAME		"elf64-microblaze"
++
++#define ELF_ARCH		bfd_arch_microblaze
++#define ELF_TARGET_ID		MICROBLAZE_ELF_DATA
++#define ELF_MACHINE_CODE	EM_MICROBLAZE
++#define ELF_MACHINE_ALT1	EM_MICROBLAZE_OLD
++#define ELF_MAXPAGESIZE		0x1000
++#define elf_info_to_howto	microblaze_elf_info_to_howto
++#define elf_info_to_howto_rel	NULL
++
++#define bfd_elf64_bfd_reloc_type_lookup		microblaze_elf_reloc_type_lookup
++#define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
++#define elf_backend_relocate_section		microblaze_elf_relocate_section
++#define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
++#define bfd_elf64_bfd_merge_private_bfd_data    microblaze_elf_merge_private_bfd_data
++#define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
++
++#define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
++#define elf_backend_gc_sweep_hook		microblaze_elf_gc_sweep_hook
++#define elf_backend_check_relocs                microblaze_elf_check_relocs
++#define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
++#define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
++#define elf_backend_can_gc_sections		1
++#define elf_backend_can_refcount    		1
++#define elf_backend_want_got_plt    		1
++#define elf_backend_plt_readonly    		1
++#define elf_backend_got_header_size 		12
++#define elf_backend_rela_normal     		1
++
++#define elf_backend_adjust_dynamic_symbol       microblaze_elf_adjust_dynamic_symbol
++#define elf_backend_create_dynamic_sections     microblaze_elf_create_dynamic_sections
++#define elf_backend_finish_dynamic_sections     microblaze_elf_finish_dynamic_sections
++#define elf_backend_finish_dynamic_symbol       microblaze_elf_finish_dynamic_symbol
++#define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
++#define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
++
++#include "elf64-target.h"
+diff --git a/bfd/targets.c b/bfd/targets.c
+index 0732c5e429..1ec226b2f4 100644
+--- a/bfd/targets.c
++++ b/bfd/targets.c
+@@ -782,6 +782,8 @@ extern const bfd_target mep_elf32_le_vec;
+ extern const bfd_target metag_elf32_vec;
+ extern const bfd_target microblaze_elf32_vec;
+ extern const bfd_target microblaze_elf32_le_vec;
++extern const bfd_target microblaze_elf64_vec;
++extern const bfd_target microblaze_elf64_le_vec;
+ extern const bfd_target mips_ecoff_be_vec;
+ extern const bfd_target mips_ecoff_le_vec;
+ extern const bfd_target mips_ecoff_bele_vec;
+@@ -1150,6 +1152,10 @@ static const bfd_target * const _bfd_target_vector[] =
+ 
+ 	&metag_elf32_vec,
+ 
++#ifdef BFD64
++	&microblaze_elf64_vec,
++	&microblaze_elf64_le_vec,
++#endif
+ 	&microblaze_elf32_vec,
+ 
+ 	&mips_ecoff_be_vec,
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 5810a74a5f..ffbb843d33 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -35,10 +35,13 @@
+ #define streq(a,b) (strcmp (a, b) == 0)
+ #endif
+ 
++static int microblaze_arch_size = 0;
++
+ #define OPTION_EB (OPTION_MD_BASE + 0)
+ #define OPTION_EL (OPTION_MD_BASE + 1)
+ #define OPTION_LITTLE (OPTION_MD_BASE + 2)
+ #define OPTION_BIG (OPTION_MD_BASE + 3)
++#define OPTION_M64 (OPTION_MD_BASE + 4)
+ 
+ void microblaze_generate_symbol (char *sym);
+ static bfd_boolean check_spl_reg (unsigned *);
+@@ -773,6 +776,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+   return new_pointer;
+ }
+ 
++ static char *
++parse_imml (char * s, expressionS * e, long min, long max)
++{
++  char *new_pointer;
++  char *atp;
++  int itype, ilen;
++
++  ilen = 0;
++
++  /* Find the start of "@GOT" or "@PLT" suffix (if any) */
++  for (atp = s; *atp != '@'; atp++)
++    if (is_end_of_line[(unsigned char) *atp])
++      break;
++
++  if (*atp == '@')
++    {
++      itype = match_imm (atp + 1, &ilen);
++      if (itype != 0)
++        {
++          *atp = 0;
++          e->X_md = itype;
++        }
++      else
++        {
++          atp = NULL;
++          e->X_md = 0;
++          ilen = 0;
++        }
++      *atp = 0;
++    }
++  else
++    {
++      atp = NULL;
++      e->X_md = 0;
++    }
++
++  if (atp && !GOT_symbol)
++    {
++      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
++    }
++
++  new_pointer = parse_exp (s, e);
++
++  if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20))
++    {
++      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
++    }
++
++  if (e->X_op == O_absent)
++    ; /* An error message has already been emitted.  */
++  else if ((e->X_op != O_constant && e->X_op != O_symbol) )
++    as_fatal (_("operand must be a constant or a label"));
++  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
++				       || (long) e->X_add_number > max))
++    {
++      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
++                min, max, (long) e->X_add_number);
++    }
++
++  if (atp)
++    {
++      *atp = '@'; /* restore back (needed?)  */
++      if (new_pointer >= atp)
++        new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */
++    }
++  return new_pointer;
++}
++
+ static char *
+ check_got (int * got_type, int * got_len)
+ {
+@@ -920,6 +991,7 @@ md_assemble (char * str)
+   unsigned int immed, immed2, temp;
+   expressionS exp;
+   char name[20];
++  long immedl;
+ 
+   /* Drop leading whitespace.  */
+   while (ISSPACE (* str))
+@@ -1129,7 +1201,7 @@ md_assemble (char * str)
+ 	}
+       break;
+ 
+-    case INST_TYPE_RD_R1_IMM5:
++    case INST_TYPE_RD_R1_IMMS:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+       else
+@@ -1163,16 +1235,22 @@ md_assemble (char * str)
+           immed = exp.X_add_number;
+         }
+ 
+-      if (immed != (immed % 32))
++      if ((immed != (immed % 32)) &&
++          (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli))
+ 	{
+           as_warn (_("Shift value > 32. using <value %% 32>"));
+           immed = immed % 32;
+         }
++      else if (immed != (immed % 64))
++	{
++          as_warn (_("Shift value > 64. using <value %% 64>"));
++          immed = immed % 64;
++        }
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+-      inst |= (immed << IMM_LOW) & IMM5_MASK;
++      inst |= (immed << IMM_LOW) & IMM6_MASK;
+       break;
+- case INST_TYPE_RD_R1_IMM5_IMM5:
++ case INST_TYPE_RD_R1_IMMW_IMMS:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
+       else
+@@ -1196,7 +1274,7 @@ md_assemble (char * str)
+ 
+       /* Width immediate value.  */
+       if (strcmp (op_end, ""))
+-        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
+       else
+         as_fatal (_("Error in statement syntax"));
+       if (exp.X_op != O_constant)
+@@ -1208,6 +1286,8 @@ md_assemble (char * str)
+         immed = exp.X_add_number;
+       if (opcode->instr == bsefi && immed > 31)
+         as_fatal (_("Width value must be less than 32"));
++      else if (opcode->instr == bslefi && immed > 63)
++        as_fatal (_("Width value must be less than 64"));
+ 
+       /* Shift immediate value.  */
+       if (strcmp (op_end, ""))
+@@ -1215,32 +1295,40 @@ md_assemble (char * str)
+       else
+         as_fatal (_("Error in statement syntax"));
+       if (exp.X_op != O_constant)
+-	    {
++       {
+           as_warn (_("Symbol used as immediate shift value for bit field instruction"));
+           immed2 = 0;
+         }
+       else
+-	    {
++        {
+           output = frag_more (isize);
+           immed2 = exp.X_add_number;
+-	    }
+-      if (immed2 != (immed2 % 32))
+-	    {
+-          as_warn (_("Shift value greater than 32. using <value %% 32>"));
++	}
++      if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi))
++	{
++          
++	  as_warn (_("Shift value greater than 32. using <value %% 32>"));
+           immed2 = immed2 % 32;
+         }
++      else if (immed2 != (immed2 % 64))
++	{
++          as_warn (_("Shift value greater than 64. using <value %% 64>"));
++          immed2 = immed2 % 64;
++        }
+ 
+       /* Check combined value.  */
+-      if (immed + immed2 > 32)
++      if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi))
+         as_fatal (_("Width value + shift value must not be greater than 32"));
+ 
++      else if (immed + immed2 > 64)
++        as_fatal (_("Width value + shift value must not be greater than 64"));
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (reg2 << RA_LOW) & RA_MASK;
+-      if (opcode->instr == bsefi)
+-        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++      if (opcode->instr == bsefi || opcode->instr == bslefi)
++        inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */
+       else
+-        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
+-      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++        inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */
++      inst |= (immed2 << IMM_LOW) & IMM6_MASK;
+       break;
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+@@ -1808,6 +1896,142 @@ md_assemble (char * str)
+       }
+       inst |= (immed << IMM_MBAR);
+       break;
++    /* For 64-bit instructions */
++    case INST_TYPE_RD_R1_IMML:
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++ 	{
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++	{
++          as_fatal (_("Error in statement syntax"));
++          reg2 = 0;
++        }
++      if (strcmp (op_end, ""))
++	op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++	as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (& reg1))
++	as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (& reg2))
++	as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++	{
++	  char *opc = NULL;
++	  relax_substateT subtype;
++
++	  if (exp.X_md != 0)
++	    subtype = get_imm_otype(exp.X_md);
++	  else
++	    subtype = opcode->inst_offset_type;
++
++	  output = frag_var (rs_machine_dependent,
++			     isize * 2, /* maxm of 2 words.  */
++			     isize * 2, /* minm of 2 words.  */
++			     subtype,   /* PC-relative or not.  */
++			     exp.X_add_symbol,
++			     exp.X_add_number,
++			     opc);
++	  immedl = 0L;
++        }
++      else
++	{
++	  output = frag_more (isize);
++	  immedl = exp.X_add_number;
++
++	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++	  if (opcode1 == NULL)
++	    {
++	      as_bad (_("unknown opcode \"%s\""), "imml");
++	      return;
++	    }
++
++	  inst1 = opcode1->bit_sequence;
++	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++	  output[0] = INST_BYTE0 (inst1);
++	  output[1] = INST_BYTE1 (inst1);
++	  output[2] = INST_BYTE2 (inst1);
++	  output[3] = INST_BYTE3 (inst1);
++	  output = frag_more (isize);
++        }
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_R1_IMML:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
++      else
++	{
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++      if (strcmp (op_end, ""))
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++      else
++        as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++
++      if (exp.X_op != O_constant)
++	{
++          char *opc = NULL;
++          relax_substateT subtype;
++
++	  if (exp.X_md != 0)
++	    subtype = get_imm_otype(exp.X_md);
++	  else
++	    subtype = opcode->inst_offset_type;
++
++	  output = frag_var (rs_machine_dependent,
++			     isize * 2, /* maxm of 2 words.  */
++			     isize * 2, /* minm of 2 words.  */
++			     subtype,   /* PC-relative or not.  */
++			     exp.X_add_symbol,
++			     exp.X_add_number,
++			     opc);
++	  immedl = 0L;
++	}
++      else
++	{
++          output = frag_more (isize);
++          immedl = exp.X_add_number;
++
++	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++	  if (opcode1 == NULL)
++	    {
++	      as_bad (_("unknown opcode \"%s\""), "imml");
++	      return;
++	    }
++
++          inst1 = opcode1->bit_sequence;
++	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++
++      inst |= (reg1 << RA_LOW) & RA_MASK;
++      inst |= (immedl << IMM_LOW) & IMM_MASK;
++      break;
++
++    case INST_TYPE_IMML:
++      as_fatal (_("An IMML instruction should not be present in the .s file"));
++      break;
+ 
+     default:
+       as_fatal (_("unimplemented opcode \"%s\""), name);
+@@ -1915,6 +2139,7 @@ struct option md_longopts[] =
+   {"EL", no_argument, NULL, OPTION_EL},
+   {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
+   {"mbig-endian", no_argument, NULL, OPTION_BIG},
++  {"m64", no_argument, NULL, OPTION_M64},
+   { NULL,          no_argument, NULL, 0}
+ };
+ 
+@@ -2565,6 +2790,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   return rel;
+ }
+ 
++/* Called by TARGET_FORMAT.  */
++const char *
++microblaze_target_format (void)
++{
++
++  if (microblaze_arch_size == 64)
++    return "elf64-microblazeel";
++  else 
++      return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel";
++}
++
++
+ int
+ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+ {
+@@ -2578,6 +2815,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_LITTLE:
+       target_big_endian = 0;
+       break;
++    case OPTION_M64:
++      //if (arg != NULL && strcmp (arg, "64") == 0)
++      microblaze_arch_size = 64;
++      break;
+     default:
+       return 0;
+     }
+@@ -2593,6 +2834,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+   fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
+   fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
+   fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
++  fprintf (stream, "  -%-23s%s\n", "m64", N_("generate 64-bit elf"));
+ }
+ 
+ 
+diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
+index 01cb3e894f..7435a70ef5 100644
+--- a/gas/config/tc-microblaze.h
++++ b/gas/config/tc-microblaze.h
+@@ -78,7 +78,9 @@ extern const struct relax_type md_relax_table[];
+ 
+ #ifdef OBJ_ELF
+ 
+-#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
++#define TARGET_FORMAT microblaze_target_format()
++extern const char *microblaze_target_format (void);
++//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
+ 
+ #define ELF_TC_SPECIAL_SECTIONS \
+   { ".sdata",		SHT_PROGBITS,	SHF_ALLOC + SHF_WRITE }, \
+diff --git a/include/elf/common.h b/include/elf/common.h
+index 4d94c4fd5b..f709a01816 100644
+--- a/include/elf/common.h
++++ b/include/elf/common.h
+@@ -340,6 +340,7 @@
+ #define EM_RISCV 	243 	/* RISC-V */
+ #define EM_LANAI	244	/* Lanai 32-bit processor.  */
+ #define EM_BPF		247	/* Linux BPF – in-kernel virtual machine.  */
++#define EM_MB_64	248	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
+ #define EM_NFP		250	/* Netronome Flow Processor.  */
+ #define EM_CSKY		252	/* C-SKY processor family.  */
+ 
+diff --git a/ld/Makefile.am b/ld/Makefile.am
+index 02c4fc1639..d063e2d32c 100644
+--- a/ld/Makefile.am
++++ b/ld/Makefile.am
+@@ -416,6 +416,8 @@ ALL_64_EMULATION_SOURCES = \
+ 	eelf32ltsmipn32.c \
+ 	eelf32ltsmipn32_fbsd.c \
+ 	eelf32mipswindiss.c \
++	eelf64microblazeel.c \
++	eelf64microblaze.c \
+ 	eelf64_aix.c \
+ 	eelf64bpf.c \
+ 	eelf64_ia64.c \
+@@ -898,6 +900,8 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Pc@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
+diff --git a/ld/Makefile.in b/ld/Makefile.in
+index 2fe12e14f6..797212859f 100644
+--- a/ld/Makefile.in
++++ b/ld/Makefile.in
+@@ -898,6 +898,8 @@ ALL_64_EMULATION_SOURCES = \
+ 	eelf32ltsmipn32.c \
+ 	eelf32ltsmipn32_fbsd.c \
+ 	eelf32mipswindiss.c \
++	eelf64microblazeel.c \
++	eelf64microblaze.c \
+ 	eelf64_aix.c \
+ 	eelf64bpf.c \
+ 	eelf64_ia64.c \
+@@ -1338,6 +1340,8 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xstormy16.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32xtensa.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32z80.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Po@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Po@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64_fbsd.Po@am__quote@
+@@ -2493,6 +2497,8 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Pc@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
+diff --git a/ld/configure.tgt b/ld/configure.tgt
+index 87c7d9a4ca..801d27c9e3 100644
+--- a/ld/configure.tgt
++++ b/ld/configure.tgt
+@@ -469,6 +469,9 @@ microblaze*-linux*)	targ_emul="elf32mb_linux"
+ microblazeel*)		targ_emul=elf32microblazeel
+ 			targ_extra_emuls=elf32microblaze
+ 			;;
++microblazeel64*)	targ_emul=elf64microblazeel
++			targ_extra_emuls=elf64microblaze
++			;;
+ microblaze*)		targ_emul=elf32microblaze
+ 			targ_extra_emuls=elf32microblazeel
+ 			;;
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+new file mode 100644
+index 0000000000..9c7b0eb708
+--- /dev/null
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+new file mode 100644
+index 0000000000..9c7b0eb708
+--- /dev/null
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 315c6e9350..f643f2600d 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -33,6 +33,7 @@
+ #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
+ #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
+ #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
++#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
+ 
+ #define NUM_STRBUFS 3
+@@ -73,11 +74,19 @@ get_field_imm (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_imm5 (struct string_buf *buf, long instr)
++get_field_imml (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
++  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++  return p;
++}
+ 
+-  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
++static char *
++get_field_imms (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
+@@ -91,14 +100,14 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+ }
+ 
+ static char *
+-get_field_imm5width (struct string_buf *buf, long instr)
++get_field_immw (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+ 
+   if (instr & 0x00004000)
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
+  else
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
+   return p;
+ }
+ 
+@@ -308,9 +317,13 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 		}
+ 	    }
+ 	  break;
+-	case INST_TYPE_RD_R1_IMM5:
++	case INST_TYPE_RD_R1_IMML:
++	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
++		      get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
++          /* TODO: Also print symbol */
++	case INST_TYPE_RD_R1_IMMS:
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+-		      get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
++	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+ 	  break;
+ 	case INST_TYPE_RD_RFSL:
+ 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -417,6 +430,10 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	case INST_TYPE_RD_R2:
+ 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+ 		      get_field_r2 (&buf, inst));
++          break;
++        case INST_TYPE_IMML:
++	  print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
+ 	  break;
+ 	case INST_TYPE_R2:
+ 	  print_func (stream, "\t%s", get_field_r2 (&buf, inst));
+@@ -440,8 +457,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	case INST_TYPE_NONE:
+ 	  break;
+         /* For bit field insns.  */
+-	case INST_TYPE_RD_R1_IMM5_IMM5:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++	case INST_TYPE_RD_R1_IMMW_IMMS:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+ 	     break;
+ 	/* For tuqula instruction */
+ 	case INST_TYPE_RD:
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f61f4ef66d..61eaa39b3e 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -40,7 +40,7 @@
+ #define INST_TYPE_RD_SPECIAL 11
+ #define INST_TYPE_R1 12
+ /* New instn type for barrel shift imms.  */
+-#define INST_TYPE_RD_R1_IMM5  13
++#define INST_TYPE_RD_R1_IMMS  13
+ #define INST_TYPE_RD_RFSL    14
+ #define INST_TYPE_R1_RFSL    15
+ 
+@@ -60,7 +60,13 @@
+ #define INST_TYPE_IMM5 20
+ 
+ /* For bsefi and bsifi */
+-#define INST_TYPE_RD_R1_IMM5_IMM5  21
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
+ 
+@@ -91,13 +97,14 @@
+ #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+-#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
++#define OPCODE_MASK_H3  0xFC000700  /* High 6 bits and bits 21, 22, 23.  */
++#define OPCODE_MASK_H3B 0xFC00E600  /* High 6 bits and bits 16, 17, 18, 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
++#define OPCODE_MASK_H32B 0xFC00E000  /* High 6 bits and bit 16, 17, 18.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -107,7 +114,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 301
++#define MAX_OPCODES 412
+ 
+ struct op_code_struct
+ {
+@@ -125,6 +132,7 @@ struct op_code_struct
+   /* More info about output format here.  */
+ } opcodes[MAX_OPCODES] =
+ {
++  /* 32-bit instructions */
+   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+@@ -161,11 +169,11 @@ struct op_code_struct
+   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+-  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+-  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+-  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
+-  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+-  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
++  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -425,6 +433,129 @@ struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
++
++  /* 64-bit instructions */
++  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
++  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
++  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
++  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
++  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
++  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
++  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
++  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
++  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
++  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
++  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
++  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
++  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
++  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
++  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
++  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
++  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
++  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
++  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
++  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
++  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
++  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
++  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
++  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
++  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
++  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
++  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
++  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
++  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
++  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
++  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
++  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
++  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
++  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
++  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
++  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
++  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
++  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
++  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
++  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
++  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
++  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
++  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
++  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
++  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
++  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
++  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
++  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
++  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
++  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
++  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
++  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
++  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
++  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
++  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
++  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
++  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
++  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
++  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
++  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
++  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
++  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
++  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
++  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
++  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
++  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
++  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
++  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
++  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
++  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
++  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
++  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
++  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
++  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
++  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
++  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
++  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
++  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
++  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
++  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
++  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
++  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
++  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
++  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
++  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
++  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
++  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
++  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
++  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
++  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
++  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
++  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
++  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
++  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
++  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
++  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
++  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
++  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
++  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
++  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
++  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
++  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
++  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
++  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
++  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
++  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM6  ((int) 0x00000000)
++#define MAX_IMM6  ((int) 0x0000003f)
++
+ #define MIN_IMM_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM_WIDTH  ((int) 0x00000020)
+ 
++#define MIN_IMM6_WIDTH  ((int) 0x00000001)
++#define MAX_IMM6_WIDTH  ((int) 0x00000040)
++
++#define MIN_IMML  ((long) 0xffffff8000000000L)
++#define MAX_IMML  ((long) 0x0000007fffffffffL)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index fa921c90c9..1dcd3dca3d 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -25,6 +25,7 @@
+ 
+ enum microblaze_instr
+ {
++  /* 32-bit instructions */
+   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu,swapb,swaph,
+@@ -58,6 +59,18 @@ enum microblaze_instr
+   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
+   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
++
++  /* 64-bit instructions */
++  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
++  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
++  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
++  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
++  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
++  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
++  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
++  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
++  dcmp_un, dbl, dlong, dsqrt,
+   invalid_inst
+ };
+ 
+@@ -135,15 +148,18 @@ enum microblaze_instr_type
+ #define RA_MASK 0x001F0000
+ #define RB_MASK 0x0000F800
+ #define IMM_MASK 0x0000FFFF
++#define IMML_MASK 0x00FFFFFF
+ 
+-/* Imm mask for barrel shifts.  */
++/* Imm masks for barrel shifts.  */
+ #define IMM5_MASK 0x0000001F
++#define IMM6_MASK 0x0000003F
+ 
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
+-/* Imm mask for extract/insert width. */
++/* Imm masks for extract/insert width. */
+ #define IMM5_WIDTH_MASK 0x000007C0
++#define IMM6_WIDTH_MASK 0x00000FC0
+ 
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-MB-X-initial-commit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-MB-X-initial-commit.patch
new file mode 100644
index 0000000000..7b87f40f4b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-MB-X-initial-commit.patch
@@ -0,0 +1,684 @@
+From 550150a8f97738902539ad774fbd0c977ab3a427 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:31:26 +0530
+Subject: [PATCH 15/52] MB-X initial commit code cleanup is needed.
+
+Conflicts:
+	bfd/elf32-microblaze.c
+	gas/config/tc-microblaze.c
+	opcodes/microblaze-opcm.h
+---
+ bfd/bfd-in2.h              |  10 +++
+ bfd/elf32-microblaze.c     |  59 +++++++++++++-
+ bfd/elf64-microblaze.c     |  61 ++++++++++++++-
+ bfd/libbfd.h               |   2 +
+ bfd/reloc.c                |  12 +++
+ gas/config/tc-microblaze.c | 154 ++++++++++++++++++++++++++++++-------
+ include/elf/microblaze.h   |   2 +
+ opcodes/microblaze-opc.h   |   4 +-
+ opcodes/microblaze-opcm.h  |   4 +-
+ 9 files changed, 275 insertions(+), 33 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 1bd19a2b63..a335182ba1 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5438,11 +5438,21 @@ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_64_NONE,
+ 
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index c22130fd8c..14bb6de052 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  TRUE),		/* PC relative offset?  */
+ 
++   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  TRUE),		/* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1463,7 +1498,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+ 		  {
+ 		    relocation += addend;
+-		    if (r_type == R_MICROBLAZE_32)
++		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+ 		      bfd_put_32 (input_bfd, relocation, contents + offset);
+ 		    else
+ 		      {
+@@ -1929,6 +1964,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ 		}
+ 	      break;
++	    case R_MICROBLAZE_IMML_64:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
+ 	    case R_MICROBLAZE_NONE:
+ 	    case R_MICROBLAZE_32_NONE:
+ 	      {
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index a357388115..6b1f47d00d 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+           0x0000ffff,		/* Dest Mask.  */
+           TRUE), 		/* PC relative offset?  */
+ 
++   /* A 64 bit relocation.  Table entry not really used.  */
++   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          64,			/* Bitsize.  */
++          TRUE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
+           0,			/* Rightshift.  */
+@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+           0x0000ffff,		/* Dest Mask.  */
+           TRUE), 		/* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+           0,			/* Rightshift.  */
+@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1172,6 +1208,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 	      break; /* Do nothing.  */
+ 
+ 	    case (int) R_MICROBLAZE_GOTPC_64:
++	    case (int) R_MICROBLAZE_GPC_64:
+ 	      relocation = htab->sgotplt->output_section->vma
+ 		+ htab->sgotplt->output_offset;
+ 	      relocation -= (input_section->output_section->vma
+@@ -1443,7 +1480,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+ 		  {
+ 		    relocation += addend;
+-		    if (r_type == R_MICROBLAZE_32)
++		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+ 		      bfd_put_32 (input_bfd, relocation, contents + offset);
+ 		    else
+ 		      {
+@@ -1889,6 +1926,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ 	        }
+ 	      break;
++	    case R_MICROBLAZE_IMML_64:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
+ 	    case R_MICROBLAZE_NONE:
+ 	    case R_MICROBLAZE_32_NONE:
+ 	      {
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index c1551b9240..b4aace6a70 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2969,7 +2969,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
++  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 9b39b41941..0e8a24e9cb 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6866,12 +6866,24 @@ ENUMDOC
+   done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index ffbb843d33..33eda2a4da 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -94,6 +94,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
+ #define TLSTPREL_OFFSET      16
+ #define TEXT_OFFSET	     17
+ #define TEXT_PC_OFFSET       18
++#define DEFINED_64_OFFSET   19
+ 
+ /* Initialize the relax table.  */
+ const relax_typeS md_relax_table[] =
+@@ -116,7 +117,9 @@ const relax_typeS md_relax_table[] =
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 15: TLSGOTTPREL_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 16: TLSTPREL_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
+-  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 18: TEXT_PC_OFFSET.  */
++  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },   /* 18: TEXT_PC_OFFSET.  */
++//  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 16: TLSTPREL_OFFSET.  */
++  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }   /* 17: DEFINED_64_OFFSET.  */
+ };
+ 
+ static struct hash_control * opcode_hash_control;	/* Opcode mnemonics.  */
+@@ -396,7 +399,8 @@ const pseudo_typeS md_pseudo_table[] =
+   {"data32", cons, 4},     /* Same as word.  */
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+-  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
++  {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
++  {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -405,6 +409,7 @@ const pseudo_typeS md_pseudo_table[] =
+   {"sbss", microblaze_s_bss, 1},
+   {"text", microblaze_s_text, 0},
+   {"word", cons, 4},
++  {"dword", cons, 8},
+   {"frame", s_ignore, 0},
+   {"mask", s_ignore, 0}, /* Emitted by gcc.  */
+   {NULL, NULL, 0}
+@@ -898,7 +903,7 @@ check_got (int * got_type, int * got_len)
+ extern bfd_reloc_code_real_type
+ parse_cons_expression_microblaze (expressionS *exp, int size)
+ {
+-  if (size == 4)
++  if (size == 4 || (microblaze_arch_size == 64 && size == 8))
+     {
+       /* Handle @GOTOFF et.al.  */
+       char *save, *gotfree_copy;
+@@ -930,6 +935,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size)
+ 
+ static const char * str_microblaze_ro_anchor = "RO";
+ static const char * str_microblaze_rw_anchor = "RW";
++static const char * str_microblaze_64 = "64";
+ 
+ static bfd_boolean
+ check_spl_reg (unsigned * reg)
+@@ -1174,6 +1180,33 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+ 	}
++#if 0 //revisit
++      else if (streq (name, "lli") || streq (name, "sli"))
++	{
++          temp = immed & 0xFFFFFFFFFFFF8000;
++          if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000))
++	    {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++
++              inst1 = opcode1->bit_sequence;
++	      inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++	    }
++	  inst |= (reg1 << RD_LOW) & RD_MASK;
++	  inst |= (reg2 << RA_LOW) & RA_MASK;
++	  inst |= (immed << IMM_LOW) & IMM_MASK;
++        }
++#endif
+       else
+ 	{
+           temp = immed & 0xFFFF8000;
+@@ -1926,6 +1959,7 @@ md_assemble (char * str)
+       if (exp.X_op != O_constant)
+ 	{
+ 	  char *opc = NULL;
++	  //char *opc = str_microblaze_64;
+ 	  relax_substateT subtype;
+ 
+ 	  if (exp.X_md != 0)
+@@ -1939,7 +1973,7 @@ md_assemble (char * str)
+ 			     subtype,   /* PC-relative or not.  */
+ 			     exp.X_add_symbol,
+ 			     exp.X_add_number,
+-			     opc);
++			     (char *) opc);
+ 	  immedl = 0L;
+         }
+       else
+@@ -1977,7 +2011,7 @@ md_assemble (char * str)
+           reg1 = 0;
+         }
+       if (strcmp (op_end, ""))
+-        op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
+       else
+         as_fatal (_("Error in statement syntax"));
+ 
+@@ -1987,7 +2021,8 @@ md_assemble (char * str)
+ 
+       if (exp.X_op != O_constant)
+ 	{
+-          char *opc = NULL;
++	  //char *opc = NULL;
++          char *opc = str_microblaze_64;
+           relax_substateT subtype;
+ 
+ 	  if (exp.X_md != 0)
+@@ -2001,14 +2036,13 @@ md_assemble (char * str)
+ 			     subtype,   /* PC-relative or not.  */
+ 			     exp.X_add_symbol,
+ 			     exp.X_add_number,
+-			     opc);
++			     (char *) opc);
+ 	  immedl = 0L;
+ 	}
+       else
+ 	{
+           output = frag_more (isize);
+           immedl = exp.X_add_number;
+-
+ 	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+ 	  if (opcode1 == NULL)
+ 	    {
+@@ -2184,13 +2218,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
++    case DEFINED_64_OFFSET:
++      if (fragP->fr_symbol == GOT_symbol)
++        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC);
++      else
++        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64);
++      fragP->fr_fix += INST_WORD_SIZE * 2;
++      fragP->fr_var = 0;
++      break;
+     case DEFINED_ABS_SEGMENT:
+       if (fragP->fr_symbol == GOT_symbol)
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+ 	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+-	         fragP->fr_offset, FALSE, BFD_RELOC_64);
++	         fragP->fr_offset, TRUE, BFD_RELOC_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+@@ -2412,22 +2456,38 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_64_PCREL:
+     case BFD_RELOC_64:
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
++    case BFD_RELOC_MICROBLAZE_64:
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+ 	buf[i + INST_WORD_SIZE] = buf[i];
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++        {
++          /* Generate the imm instruction.  */
++          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++          if (opcode1 == NULL)
++	    {
++	      as_bad (_("unknown opcode \"%s\""), "imml");
++	      return;
++	    }
+ 
+-      /* Generate the imm instruction.  */
+-      opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+-      if (opcode1 == NULL)
+-	{
+-	  as_bad (_("unknown opcode \"%s\""), "imm");
+-	  return;
+-	}
+-
+-      inst1 = opcode1->bit_sequence;
+-      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-	inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+-
++           inst1 = opcode1->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++         }
++      else
++        {
++          /* Generate the imm instruction.  */
++          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++          if (opcode1 == NULL)
++	    {
++	      as_bad (_("unknown opcode \"%s\""), "imm");
++	      return;
++	    }
++     
++          inst1 = opcode1->bit_sequence;
++          if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
++         }
+       buf[0] = INST_BYTE0 (inst1);
+       buf[1] = INST_BYTE1 (inst1);
+       buf[2] = INST_BYTE2 (inst1);
+@@ -2456,6 +2516,7 @@ md_apply_fix (fixS *   fixP,
+       /* Fall through.  */
+ 
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
++    case BFD_RELOC_MICROBLAZE_64_GPC:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+@@ -2463,12 +2524,16 @@ md_apply_fix (fixS *   fixP,
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+ 	buf[i + INST_WORD_SIZE] = buf[i];
+-
+-      /* Generate the imm instruction.  */
+-      opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
++        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++      else
++        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+       if (opcode1 == NULL)
+ 	{
+-	  as_bad (_("unknown opcode \"%s\""), "imm");
++      	  if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
++	    as_bad (_("unknown opcode \"%s\""), "imml");
++          else
++	    as_bad (_("unknown opcode \"%s\""), "imm");
+ 	  return;
+ 	}
+ 
+@@ -2492,6 +2557,8 @@ md_apply_fix (fixS *   fixP,
+ 	 moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++	    fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+@@ -2535,6 +2602,32 @@ md_estimate_size_before_relax (fragS * fragP,
+           as_bad (_("Absolute PC-relative value in relaxation code.  Assembler error....."));
+           abort ();
+         }
++      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type
++               && !S_IS_WEAK (fragP->fr_symbol))
++        {
++           if (fragP->fr_opcode != NULL) {
++	     if(streq (fragP->fr_opcode, str_microblaze_64)) 
++             {
++               /* Used as an absolute value.  */
++              fragP->fr_subtype = DEFINED_64_OFFSET;
++               /* Variable part does not change.  */
++              fragP->fr_var = INST_WORD_SIZE;
++	     }
++	   else
++	     {
++               fragP->fr_subtype = DEFINED_PC_OFFSET;
++      	       /* Don't know now whether we need an imm instruction.  */
++               fragP->fr_var = INST_WORD_SIZE;
++	     }
++	   }  
++	   else
++	     {
++               fragP->fr_subtype = DEFINED_PC_OFFSET;
++      	       /* Don't know now whether we need an imm instruction.  */
++               fragP->fr_var = INST_WORD_SIZE;
++	     }
++        }
++    #if 0
+       else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
+                !S_IS_WEAK (fragP->fr_symbol))
+         {
+@@ -2542,6 +2635,7 @@ md_estimate_size_before_relax (fragS * fragP,
+           /* Don't know now whether we need an imm instruction.  */
+           fragP->fr_var = INST_WORD_SIZE;
+         }
++#endif
+       else if (S_IS_DEFINED (fragP->fr_symbol)
+ 	       && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0))
+         {
+@@ -2644,6 +2738,7 @@ md_estimate_size_before_relax (fragS * fragP,
+     case TLSLD_OFFSET:
+     case TLSTPREL_OFFSET:
+     case TLSDTPREL_OFFSET:
++    case DEFINED_64_OFFSET:
+       fragP->fr_var = INST_WORD_SIZE*2;
+       break;
+     case DEFINED_RO_SEGMENT:
+@@ -2697,7 +2792,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
+   else
+     {
+       /* The case where we are going to resolve things... */
+-      if (fixp->fx_r_type == BFD_RELOC_64_PCREL)
++      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
+       else
+         return  fixp->fx_where + fixp->fx_frag->fr_address;
+@@ -2730,6 +2825,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_32_RWSDA:
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++    case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+@@ -2872,7 +2969,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          r = BFD_RELOC_64;
++          if (microblaze_arch_size == 64)
++            r = BFD_RELOC_32;
++          else
++            r = BFD_RELOC_64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index 3978a3dc01..938841b240 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
++  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
+    
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 61eaa39b3e..f2139a6839 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -538,8 +538,8 @@ struct op_code_struct
+   {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
+   {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
+   {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
+-  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
+-  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
+   {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
+   {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
+   {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 1dcd3dca3d..fcf259a362 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -40,8 +40,8 @@ enum microblaze_instr
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+-  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+-  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
++  sbi, shi, swi, sli, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   fint, fsqrt,
+   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
deleted file mode 100644
index 9f22801512..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0015-intial-commit-of-MB-64-bit.patch
+++ /dev/null
@@ -1,4734 +0,0 @@
-From a7626e576d867c6c9c8321f00cf5e17dc31c52b8 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sun, 30 Sep 2018 16:28:28 +0530
-Subject: [PATCH 15/40] intial commit of MB 64-bit
-
----
- bfd/Makefile.am                    |    2 +
- bfd/Makefile.in                    |    3 +
- bfd/config.bfd                     |    4 +
- bfd/configure                      |    2 +
- bfd/configure.ac                   |    2 +
- bfd/cpu-microblaze.c               |   55 +-
- bfd/doc/Makefile.in                |    1 +
- bfd/elf64-microblaze.c             | 3560 ++++++++++++++++++++++++++++
- bfd/targets.c                      |    6 +
- gas/config/tc-microblaze.c         |  274 ++-
- gas/config/tc-microblaze.h         |    4 +-
- include/elf/common.h               |    1 +
- ld/Makefile.am                     |    4 +
- ld/Makefile.in                     |    7 +
- ld/configure.tgt                   |    3 +
- ld/emulparams/elf64microblaze.sh   |   23 +
- ld/emulparams/elf64microblazeel.sh |   23 +
- opcodes/microblaze-dis.c           |   43 +-
- opcodes/microblaze-opc.h           |  162 +-
- opcodes/microblaze-opcm.h          |   20 +-
- 20 files changed, 4156 insertions(+), 43 deletions(-)
- create mode 100644 bfd/elf64-microblaze.c
- create mode 100644 ld/emulparams/elf64microblaze.sh
- create mode 100644 ld/emulparams/elf64microblazeel.sh
-
-diff --git a/bfd/Makefile.am b/bfd/Makefile.am
-index c88c4480001..9e12b34038c 100644
---- a/bfd/Makefile.am
-+++ b/bfd/Makefile.am
-@@ -552,6 +552,7 @@ BFD64_BACKENDS = \
- 	elf64-ia64.lo \
- 	elf64-ia64-vms.lo \
- 	elfxx-ia64.lo \
-+	elf64-microblaze.lo \
- 	elfn32-mips.lo \
- 	elf64-mips.lo \
- 	elfxx-mips.lo \
-@@ -591,6 +592,7 @@ BFD64_BACKENDS_CFILES = \
- 	elf64-gen.c \
- 	elf64-hppa.c \
- 	elf64-ia64-vms.c \
-+	elf64-microblaze.c \
- 	elf64-mips.c \
- 	elf64-mmix.c \
- 	elf64-nfp.c \
-diff --git a/bfd/Makefile.in b/bfd/Makefile.in
-index d0d14c6ab32..5c12b706616 100644
---- a/bfd/Makefile.in
-+++ b/bfd/Makefile.in
-@@ -978,6 +978,7 @@ BFD64_BACKENDS = \
- 	elf64-ia64.lo \
- 	elf64-ia64-vms.lo \
- 	elfxx-ia64.lo \
-+	elf64-microblaze.lo \
- 	elfn32-mips.lo \
- 	elf64-mips.lo \
- 	elfxx-mips.lo \
-@@ -1017,6 +1018,7 @@ BFD64_BACKENDS_CFILES = \
- 	elf64-gen.c \
- 	elf64-hppa.c \
- 	elf64-ia64-vms.c \
-+	elf64-microblaze.c \
- 	elf64-mips.c \
- 	elf64-mmix.c \
- 	elf64-nfp.c \
-@@ -1495,6 +1497,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-nfp.Plo@am__quote@
-diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 14523caf0c5..437c03bb9d9 100644
---- a/bfd/config.bfd
-+++ b/bfd/config.bfd
-@@ -825,11 +825,15 @@ case "${targ}" in
-   microblazeel*-*)
-     targ_defvec=microblaze_elf32_le_vec
-     targ_selvecs=microblaze_elf32_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
-   microblaze*-*)
-     targ_defvec=microblaze_elf32_vec
-     targ_selvecs=microblaze_elf32_le_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
- #ifdef BFD64
-diff --git a/bfd/configure b/bfd/configure
-index 5ab3e856bc2..982ecd254a8 100755
---- a/bfd/configure
-+++ b/bfd/configure
-@@ -14828,6 +14828,8 @@ do
-     metag_elf32_vec)		 tb="$tb elf32-metag.lo elf32.lo $elf" ;;
-     microblaze_elf32_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-     microblaze_elf32_le_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-+    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-     mips_ecoff_be_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_le_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_bele_vec)	 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-diff --git a/bfd/configure.ac b/bfd/configure.ac
-index 8e86f8399ce..38e80148171 100644
---- a/bfd/configure.ac
-+++ b/bfd/configure.ac
-@@ -564,6 +564,8 @@ do
-     metag_elf32_vec)		 tb="$tb elf32-metag.lo elf32.lo $elf" ;;
-     microblaze_elf32_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-     microblaze_elf32_le_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-+    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-     mips_ecoff_be_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_le_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_bele_vec)	 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index 05a3f767e22..f94dc2c177b 100644
---- a/bfd/cpu-microblaze.c
-+++ b/bfd/cpu-microblaze.c
-@@ -23,7 +23,25 @@
- #include "bfd.h"
- #include "libbfd.h"
- 
--const bfd_arch_info_type bfd_microblaze_arch =
-+const bfd_arch_info_type bfd_microblaze_arch[] =
-+{
-+#if BFD_DEFAULT_TARGET_SIZE == 64
-+{
-+  64,		  		/* 32 bits in a word.  */
-+  64,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  FALSE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  &bfd_microblaze_arch[1],  	/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+},
- {
-   32,				/* Bits in a word.  */
-   32,				/* Bits in an address.  */
-@@ -39,4 +57,39 @@ const bfd_arch_info_type bfd_microblaze_arch =
-   bfd_arch_default_fill,	/* Default fill.  */
-   NULL,				/* Next in list.  */
-   0 /* Maximum offset of a reloc from the start of an insn.  */
-+}
-+#else
-+{
-+  32,		  		/* 32 bits in a word.  */
-+  32,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  TRUE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  &bfd_microblaze_arch[1],   	/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+},
-+{
-+  64,		  		/* 32 bits in a word.  */
-+  64,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  FALSE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  NULL,				/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+}
-+#endif
- };
-diff --git a/bfd/doc/Makefile.in b/bfd/doc/Makefile.in
-index 2c1ddd45b8d..a976b24d0bf 100644
---- a/bfd/doc/Makefile.in
-+++ b/bfd/doc/Makefile.in
-@@ -375,6 +375,7 @@ pdfdir = @pdfdir@
- prefix = @prefix@
- program_transform_name = @program_transform_name@
- psdir = @psdir@
-+runstatedir = @runstatedir@
- sbindir = @sbindir@
- sharedstatedir = @sharedstatedir@
- srcdir = @srcdir@
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-new file mode 100644
-index 00000000000..fa4b95e47e0
---- /dev/null
-+++ b/bfd/elf64-microblaze.c
-@@ -0,0 +1,3560 @@
-+/* Xilinx MicroBlaze-specific support for 32-bit ELF
-+
-+   Copyright (C) 2009-2016 Free Software Foundation, Inc.
-+
-+   This file is part of BFD, the Binary File Descriptor library.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the
-+   Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
-+   Boston, MA 02110-1301, USA.  */
-+
-+
-+int dbg1 = 0;
-+
-+#include "sysdep.h"
-+#include "bfd.h"
-+#include "bfdlink.h"
-+#include "libbfd.h"
-+#include "elf-bfd.h"
-+#include "elf/microblaze.h"
-+#include <assert.h>
-+
-+#define	USE_RELA	/* Only USE_REL is actually significant, but this is
-+			   here are a reminder...  */
-+#define INST_WORD_SIZE 4
-+
-+static int ro_small_data_pointer = 0;
-+static int rw_small_data_pointer = 0;
-+
-+static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
-+
-+static reloc_howto_type microblaze_elf_howto_raw[] =
-+{
-+   /* This reloc does nothing.  */
-+   HOWTO (R_MICROBLAZE_NONE,	/* Type.  */
-+          0,			/* Rightshift.  */
-+          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_NONE", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0,			/* Dest Mask.  */
-+          FALSE),		/* PC relative offset?  */
-+
-+   /* A standard 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A standard PCREL 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_PCREL,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_PCREL",   	/* Name.  */
-+          TRUE,			/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit PCREL relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_64_PCREL,/* Type.  */
-+          0,			/* Rightshift.  */
-+          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          64,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_64_PCREL", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* The low half of a PCREL 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_PCREL_LO,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_signed, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_32_PCREL_LO", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit relocation.  Table entry not really used.  */
-+   HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* The low half of a 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_LO,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_signed, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_LO", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Read-only small data section relocation.  */
-+   HOWTO (R_MICROBLAZE_SRO32,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_SRO32", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Read-write small data area relocation.  */
-+   HOWTO (R_MICROBLAZE_SRW32,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_SRW32", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
-+          0,         /* Rightshift.  */
-+          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,           /* Bitsize.  */
-+          TRUE,         /* PC_relative.  */
-+          0,           /* Bitpos.  */
-+          complain_overflow_bitfield,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_32_NONE",/* Name.  */
-+          FALSE,       /* Partial Inplace.  */
-+          0,          /* Source Mask.  */
-+          0,         /* Dest Mask.  */
-+          FALSE),       /* PC relative offset?  */
-+
-+   /* This reloc does nothing.  Used for relaxation.  */
-+   HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
-+          0,			/* Rightshift.  */
-+          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_64_NONE",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0,			/* Dest Mask.  */
-+          FALSE),		/* PC relative offset?  */
-+
-+   /* Symbol Op Symbol relocation.  */
-+   HOWTO (R_MICROBLAZE_32_SYM_OP_SYM,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_SYM_OP_SYM",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* GNU extension to record C++ vtable hierarchy.  */
-+   HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type.  */
-+          0,                     /* Rightshift.  */
-+          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,                     /* Bitsize.  */
-+          FALSE,                 /* PC_relative.  */
-+          0,                     /* Bitpos.  */
-+          complain_overflow_dont,/* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_GNU_VTINHERIT", /* Name.  */
-+          FALSE,                 /* Partial Inplace.  */
-+          0,                     /* Source Mask.  */
-+          0,                     /* Dest Mask.  */
-+          FALSE),                /* PC relative offset?  */
-+
-+   /* GNU extension to record C++ vtable member usage.  */
-+   HOWTO (R_MICROBLAZE_GNU_VTENTRY,   /* Type.  */
-+          0,                     /* Rightshift.  */
-+          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,                     /* Bitsize.  */
-+          FALSE,                 /* PC_relative.  */
-+          0,                     /* Bitpos.  */
-+          complain_overflow_dont,/* Complain on overflow.  */
-+          _bfd_elf_rel_vtable_reloc_fn,  /* Special Function.  */
-+          "R_MICROBLAZE_GNU_VTENTRY", /* Name.  */
-+          FALSE,                 /* Partial Inplace.  */
-+          0,                     /* Source Mask.  */
-+          0,                     /* Dest Mask.  */
-+          FALSE),                /* PC relative offset?  */
-+
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GOTPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit GOT relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GOT_64",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit PLT relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_PLT_64,  /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_PLT_64",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_REL,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_REL", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_JUMP_SLOT", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GLOB_DAT", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit GOT relative relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTOFF_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GOTOFF_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A 32 bit GOT relative relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTOFF_32,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GOTOFF_32", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* COPY relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_COPY,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_COPY", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Marker relocs for TLS.  */
-+   HOWTO (R_MICROBLAZE_TLS,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_MICROBLAZE_TLS",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   HOWTO (R_MICROBLAZE_TLSGD,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSGD",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   HOWTO (R_MICROBLAZE_TLSLD,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSLD",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes the load module index of the load module that contains the
-+      definition of its TLS sym.  */
-+   HOWTO (R_MICROBLAZE_TLSDTPMOD32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPMOD32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a dtv-relative displacement, the difference between the value
-+      of sym+add and the base address of the thread-local storage block that
-+      contains the definition of sym, minus 0x8000.  Used for initializing GOT */
-+   HOWTO (R_MICROBLAZE_TLSDTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a dtv-relative displacement, the difference between the value
-+      of sym+add and the base address of the thread-local storage block that
-+      contains the definition of sym, minus 0x8000.  */
-+   HOWTO (R_MICROBLAZE_TLSDTPREL64,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPREL64",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a tp-relative displacement, the difference between the value of
-+      sym+add and the value of the thread pointer (r13).  */
-+   HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSGOTTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a tp-relative displacement, the difference between the value of
-+      sym+add and the value of the thread pointer (r13).  */
-+   HOWTO (R_MICROBLAZE_TLSTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+};
-+
-+#ifndef NUM_ELEM
-+#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
-+#endif
-+
-+/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done.  */
-+
-+static void
-+microblaze_elf_howto_init (void)
-+{
-+  unsigned int i;
-+
-+  for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
-+    {
-+      unsigned int type;
-+
-+      type = microblaze_elf_howto_raw[i].type;
-+
-+      BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
-+
-+      microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
-+    }
-+}
-+
-+static reloc_howto_type *
-+microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-+				  bfd_reloc_code_real_type code)
-+{
-+  enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
-+
-+  switch (code)
-+    {
-+    case BFD_RELOC_NONE:
-+      microblaze_reloc = R_MICROBLAZE_NONE;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-+      microblaze_reloc = R_MICROBLAZE_32_NONE;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_NONE:
-+      microblaze_reloc = R_MICROBLAZE_64_NONE;
-+      break;
-+    case BFD_RELOC_32:
-+      microblaze_reloc = R_MICROBLAZE_32;
-+      break;
-+      /* RVA is treated the same as 32 */
-+    case BFD_RELOC_RVA:
-+      microblaze_reloc = R_MICROBLAZE_32;
-+      break;
-+    case BFD_RELOC_32_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_32_PCREL;
-+      break;
-+    case BFD_RELOC_64_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_64_PCREL;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
-+      break;
-+    case BFD_RELOC_64:
-+      microblaze_reloc = R_MICROBLAZE_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_LO:
-+      microblaze_reloc = R_MICROBLAZE_32_LO;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_ROSDA:
-+      microblaze_reloc = R_MICROBLAZE_SRO32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_RWSDA:
-+      microblaze_reloc = R_MICROBLAZE_SRW32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
-+      microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
-+      break;
-+    case BFD_RELOC_VTABLE_INHERIT:
-+      microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
-+      break;
-+    case BFD_RELOC_VTABLE_ENTRY:
-+      microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOTPC:
-+      microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOT:
-+      microblaze_reloc = R_MICROBLAZE_GOT_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_PLT:
-+      microblaze_reloc = R_MICROBLAZE_PLT_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOTOFF:
-+      microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_GOTOFF:
-+      microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSGD:
-+      microblaze_reloc = R_MICROBLAZE_TLSGD;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSLD:
-+      microblaze_reloc = R_MICROBLAZE_TLSLD;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_COPY:
-+      microblaze_reloc = R_MICROBLAZE_COPY;
-+      break;
-+    default:
-+      return (reloc_howto_type *) NULL;
-+    }
-+
-+  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
-+    /* Initialize howto table if needed.  */
-+    microblaze_elf_howto_init ();
-+
-+  return microblaze_elf_howto_table [(int) microblaze_reloc];
-+};
-+
-+static reloc_howto_type *
-+microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-+				  const char *r_name)
-+{
-+  unsigned int i;
-+
-+  for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
-+    if (microblaze_elf_howto_raw[i].name != NULL
-+	&& strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
-+      return &microblaze_elf_howto_raw[i];
-+
-+  return NULL;
-+}
-+
-+/* Set the howto pointer for a RCE ELF reloc.  */
-+
-+static bfd_boolean
-+microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-+			      arelent * cache_ptr,
-+			      Elf_Internal_Rela * dst)
-+{
-+  unsigned int r_type;
-+
-+  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
-+    /* Initialize howto table if needed.  */
-+    microblaze_elf_howto_init ();
-+
-+  r_type = ELF64_R_TYPE (dst->r_info);
-+  if (r_type >= R_MICROBLAZE_max)
-+    {
-+      (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
-+			     abfd, r_type);
-+      bfd_set_error (bfd_error_bad_value);
-+      return FALSE;
-+    }
-+
-+  cache_ptr->howto = microblaze_elf_howto_table [r_type];
-+ return TRUE;
-+}
-+
-+/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
-+
-+static bfd_boolean
-+microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
-+{
-+  if (name[0] == 'L' && name[1] == '.')
-+    return TRUE;
-+
-+  if (name[0] == '$' && name[1] == 'L')
-+    return TRUE;
-+
-+  /* With gcc, the labels go back to starting with '.', so we accept
-+     the generic ELF local label syntax as well.  */
-+  return _bfd_elf_is_local_label_name (abfd, name);
-+}
-+
-+/* The microblaze linker (like many others) needs to keep track of
-+   the number of relocs that it decides to copy as dynamic relocs in
-+   check_relocs for each symbol. This is so that it can later discard
-+   them if they are found to be unnecessary.  We store the information
-+   in a field extending the regular ELF linker hash table.  */
-+
-+struct elf64_mb_dyn_relocs
-+{
-+  struct elf64_mb_dyn_relocs *next;
-+
-+  /* The input section of the reloc.  */
-+  asection *sec;
-+
-+  /* Total number of relocs copied for the input section.  */
-+  bfd_size_type count;
-+
-+  /* Number of pc-relative relocs copied for the input section.  */
-+  bfd_size_type pc_count;
-+};
-+
-+/* ELF linker hash entry.  */
-+
-+struct elf64_mb_link_hash_entry
-+{
-+  struct elf_link_hash_entry elf;
-+
-+  /* Track dynamic relocs copied for this symbol.  */
-+  struct elf64_mb_dyn_relocs *dyn_relocs;
-+
-+  /* TLS Reference Types for the symbol; Updated by check_relocs */
-+#define TLS_GD     1  /* GD reloc. */
-+#define TLS_LD     2  /* LD reloc. */
-+#define TLS_TPREL  4  /* TPREL reloc, => IE. */
-+#define TLS_DTPREL 8  /* DTPREL reloc, => LD. */
-+#define TLS_TLS    16 /* Any TLS reloc.  */
-+  unsigned char tls_mask;
-+
-+};
-+
-+#define IS_TLS_GD(x)     (x == (TLS_TLS | TLS_GD))
-+#define IS_TLS_LD(x)     (x == (TLS_TLS | TLS_LD))
-+#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
-+#define IS_TLS_NONE(x)   (x == 0)
-+
-+#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
-+
-+/* ELF linker hash table.  */
-+
-+struct elf64_mb_link_hash_table
-+{
-+  struct elf_link_hash_table elf;
-+
-+  /* Short-cuts to get to dynamic linker sections.  */
-+  asection *sgot;
-+  asection *sgotplt;
-+  asection *srelgot;
-+  asection *splt;
-+  asection *srelplt;
-+  asection *sdynbss;
-+  asection *srelbss;
-+
-+  /* Small local sym to section mapping cache.  */
-+  struct sym_cache sym_sec;
-+
-+  /* TLS Local Dynamic GOT Entry */
-+  union {
-+    bfd_signed_vma refcount;
-+    bfd_vma offset;
-+  } tlsld_got;
-+};
-+
-+/* Nonzero if this section has TLS related relocations.  */
-+#define has_tls_reloc sec_flg0
-+
-+/* Get the ELF linker hash table from a link_info structure.  */
-+
-+#define elf64_mb_hash_table(p)				\
-+  (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
-+  == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL)
-+
-+/* Create an entry in a microblaze ELF linker hash table.  */
-+
-+static struct bfd_hash_entry *
-+link_hash_newfunc (struct bfd_hash_entry *entry,
-+		   struct bfd_hash_table *table,
-+		   const char *string)
-+{
-+  /* Allocate the structure if it has not already been allocated by a
-+     subclass.  */
-+  if (entry == NULL)
-+    {
-+      entry = bfd_hash_allocate (table,
-+				 sizeof (struct elf64_mb_link_hash_entry));
-+      if (entry == NULL)
-+	return entry;
-+    }
-+
-+  /* Call the allocation method of the superclass.  */
-+  entry = _bfd_elf_link_hash_newfunc (entry, table, string);
-+  if (entry != NULL)
-+    {
-+      struct elf64_mb_link_hash_entry *eh;
-+
-+      eh = (struct elf64_mb_link_hash_entry *) entry;
-+      eh->dyn_relocs = NULL;
-+      eh->tls_mask = 0;
-+    }
-+
-+  return entry;
-+}
-+
-+/* Create a mb ELF linker hash table.  */
-+
-+static struct bfd_link_hash_table *
-+microblaze_elf_link_hash_table_create (bfd *abfd)
-+{
-+  struct elf64_mb_link_hash_table *ret;
-+  bfd_size_type amt = sizeof (struct elf64_mb_link_hash_table);
-+
-+  ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
-+  if (ret == NULL)
-+    return NULL;
-+
-+  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
-+				      sizeof (struct elf64_mb_link_hash_entry),
-+				      MICROBLAZE_ELF_DATA))
-+    {
-+      free (ret);
-+      return NULL;
-+    }
-+
-+  return &ret->elf.root;
-+}
-+
-+/* Set the values of the small data pointers.  */
-+
-+static void
-+microblaze_elf_final_sdp (struct bfd_link_info *info)
-+{
-+  struct bfd_link_hash_entry *h;
-+
-+  h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
-+  if (h != (struct bfd_link_hash_entry *) NULL
-+      && h->type == bfd_link_hash_defined)
-+    ro_small_data_pointer = (h->u.def.value
-+                             + h->u.def.section->output_section->vma
-+                             + h->u.def.section->output_offset);
-+
-+  h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
-+  if (h != (struct bfd_link_hash_entry *) NULL
-+      && h->type == bfd_link_hash_defined)
-+    rw_small_data_pointer = (h->u.def.value
-+                             + h->u.def.section->output_section->vma
-+                             + h->u.def.section->output_offset);
-+}
-+
-+static bfd_vma
-+dtprel_base (struct bfd_link_info *info)
-+{
-+  /* If tls_sec is NULL, we should have signalled an error already.  */
-+  if (elf_hash_table (info)->tls_sec == NULL)
-+    return 0;
-+  return elf_hash_table (info)->tls_sec->vma;
-+}
-+
-+/* The size of the thread control block.  */
-+#define TCB_SIZE	8
-+
-+/* Output a simple dynamic relocation into SRELOC.  */
-+
-+static void
-+microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
-+					  asection *sreloc,
-+					  unsigned long reloc_index,
-+					  unsigned long indx,
-+					  int r_type,
-+					  bfd_vma offset,
-+					  bfd_vma addend)
-+{
-+
-+  Elf_Internal_Rela rel;
-+
-+  rel.r_info = ELF64_R_INFO (indx, r_type);
-+  rel.r_offset = offset;
-+  rel.r_addend = addend;
-+
-+  bfd_elf64_swap_reloca_out (output_bfd, &rel,
-+              (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
-+}
-+
-+/* This code is taken from elf64-m32r.c
-+   There is some attempt to make this function usable for many architectures,
-+   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
-+   if only to serve as a learning tool.
-+
-+   The RELOCATE_SECTION function is called by the new ELF backend linker
-+   to handle the relocations for a section.
-+
-+   The relocs are always passed as Rela structures; if the section
-+   actually uses Rel structures, the r_addend field will always be
-+   zero.
-+
-+   This function is responsible for adjust the section contents as
-+   necessary, and (if using Rela relocs and generating a
-+   relocatable output file) adjusting the reloc addend as
-+   necessary.
-+
-+   This function does not have to worry about setting the reloc
-+   address or the reloc symbol index.
-+
-+   LOCAL_SYMS is a pointer to the swapped in local symbols.
-+
-+   LOCAL_SECTIONS is an array giving the section in the input file
-+   corresponding to the st_shndx field of each local symbol.
-+
-+   The global hash table entry for the global symbols can be found
-+   via elf_sym_hashes (input_bfd).
-+
-+   When generating relocatable output, this function must handle
-+   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
-+   going to be the section symbol corresponding to the output
-+   section, which means that the addend must be adjusted
-+   accordingly.  */
-+
-+static bfd_boolean
-+microblaze_elf_relocate_section (bfd *output_bfd,
-+			         struct bfd_link_info *info,
-+			         bfd *input_bfd,
-+			         asection *input_section,
-+			         bfd_byte *contents,
-+			         Elf_Internal_Rela *relocs,
-+			         Elf_Internal_Sym *local_syms,
-+			         asection **local_sections)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
-+  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
-+  Elf_Internal_Rela *rel, *relend;
-+  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
-+  /* Assume success.  */
-+  bfd_boolean ret = TRUE;
-+  asection *sreloc;
-+  bfd_vma *local_got_offsets;
-+  unsigned int tls_type;
-+
-+  if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
-+    microblaze_elf_howto_init ();
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  local_got_offsets = elf_local_got_offsets (input_bfd);
-+
-+  sreloc = elf_section_data (input_section)->sreloc;
-+
-+  rel = relocs;
-+  relend = relocs + input_section->reloc_count;
-+  for (; rel < relend; rel++)
-+    {
-+      int r_type;
-+      reloc_howto_type *howto;
-+      unsigned long r_symndx;
-+      bfd_vma addend = rel->r_addend;
-+      bfd_vma offset = rel->r_offset;
-+      struct elf_link_hash_entry *h;
-+      Elf_Internal_Sym *sym;
-+      asection *sec;
-+      const char *sym_name;
-+      bfd_reloc_status_type r = bfd_reloc_ok;
-+      const char *errmsg = NULL;
-+      bfd_boolean unresolved_reloc = FALSE;
-+
-+      h = NULL;
-+      r_type = ELF64_R_TYPE (rel->r_info);
-+      tls_type = 0;
-+
-+      if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
-+	{
-+	  (*_bfd_error_handler) (_("%s: unknown relocation type %d"),
-+				 bfd_get_filename (input_bfd), (int) r_type);
-+	  bfd_set_error (bfd_error_bad_value);
-+	  ret = FALSE;
-+	  continue;
-+	}
-+
-+      howto = microblaze_elf_howto_table[r_type];
-+      r_symndx = ELF64_R_SYM (rel->r_info);
-+
-+      if (bfd_link_relocatable (info))
-+	{
-+	  /* This is a relocatable link.  We don't have to change
-+	     anything, unless the reloc is against a section symbol,
-+	     in which case we have to adjust according to where the
-+	     section symbol winds up in the output section.  */
-+	  sec = NULL;
-+	  if (r_symndx >= symtab_hdr->sh_info)
-+	    /* External symbol.  */
-+	    continue;
-+
-+	  /* Local symbol.  */
-+	  sym = local_syms + r_symndx;
-+	  sym_name = "<local symbol>";
-+	  /* STT_SECTION: symbol is associated with a section.  */
-+	  if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
-+	    /* Symbol isn't associated with a section.  Nothing to do.  */
-+	    continue;
-+
-+	  sec = local_sections[r_symndx];
-+	  addend += sec->output_offset + sym->st_value;
-+#ifndef USE_REL
-+	  /* This can't be done for USE_REL because it doesn't mean anything
-+	     and elf_link_input_bfd asserts this stays zero.  */
-+	  /* rel->r_addend = addend; */
-+#endif
-+
-+#ifndef USE_REL
-+	  /* Addends are stored with relocs.  We're done.  */
-+	  continue;
-+#else /* USE_REL */
-+	  /* If partial_inplace, we need to store any additional addend
-+	     back in the section.  */
-+	  if (!howto->partial_inplace)
-+	    continue;
-+	  /* ??? Here is a nice place to call a special_function like handler.  */
-+	  r = _bfd_relocate_contents (howto, input_bfd, addend,
-+				      contents + offset);
-+#endif /* USE_REL */
-+	}
-+      else
-+	{
-+	  bfd_vma relocation;
-+
-+	  /* This is a final link.  */
-+	  sym = NULL;
-+	  sec = NULL;
-+	  unresolved_reloc = FALSE;
-+
-+	  if (r_symndx < symtab_hdr->sh_info)
-+	    {
-+	      /* Local symbol.  */
-+	      sym = local_syms + r_symndx;
-+	      sec = local_sections[r_symndx];
-+	      if (sec == 0)
-+		continue;
-+	      sym_name = "<local symbol>";
-+	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
-+	      /* r_addend may have changed if the reference section was
-+		 a merge section.  */
-+	      addend = rel->r_addend;
-+	    }
-+	  else
-+	    {
-+	      /* External symbol.  */
-+	      bfd_boolean warned ATTRIBUTE_UNUSED;
-+	      bfd_boolean ignored ATTRIBUTE_UNUSED;
-+
-+	      RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
-+				       r_symndx, symtab_hdr, sym_hashes,
-+				       h, sec, relocation,
-+				       unresolved_reloc, warned, ignored);
-+	      sym_name = h->root.root.string;
-+	    }
-+
-+	  /* Sanity check the address.  */
-+	  if (offset > bfd_get_section_limit (input_bfd, input_section))
-+	    {
-+	      r = bfd_reloc_outofrange;
-+	      goto check_reloc;
-+	    }
-+
-+	  switch ((int) r_type)
-+	    {
-+	    case (int) R_MICROBLAZE_SRO32 :
-+	      {
-+		const char *name;
-+
-+		/* Only relocate if the symbol is defined.  */
-+		if (sec)
-+		  {
-+		    name = bfd_section_name (sec);
-+
-+		    if (strcmp (name, ".sdata2") == 0
-+			|| strcmp (name, ".sbss2") == 0)
-+		      {
-+			if (ro_small_data_pointer == 0)
-+			  microblaze_elf_final_sdp (info);
-+			if (ro_small_data_pointer == 0)
-+			  {
-+			    ret = FALSE;
-+			    r = bfd_reloc_undefined;
-+			    goto check_reloc;
-+			  }
-+
-+			/* At this point `relocation' contains the object's
-+			   address.  */
-+			relocation -= ro_small_data_pointer;
-+			/* Now it contains the offset from _SDA2_BASE_.  */
-+			r = _bfd_final_link_relocate (howto, input_bfd,
-+						      input_section,
-+						      contents, offset,
-+						      relocation, addend);
-+		      }
-+		    else
-+		      {
-+			(*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
-+					       bfd_get_filename (input_bfd),
-+					       sym_name,
-+					       microblaze_elf_howto_table[(int) r_type]->name,
-+					       bfd_section_name (sec));
-+			/*bfd_set_error (bfd_error_bad_value); ??? why? */
-+			ret = FALSE;
-+			continue;
-+		      }
-+		  }
-+	      }
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_SRW32 :
-+	      {
-+		const char *name;
-+
-+		/* Only relocate if the symbol is defined.  */
-+		if (sec)
-+		  {
-+		    name = bfd_section_name (sec);
-+
-+		    if (strcmp (name, ".sdata") == 0
-+			|| strcmp (name, ".sbss") == 0)
-+		      {
-+			if (rw_small_data_pointer == 0)
-+			  microblaze_elf_final_sdp (info);
-+			if (rw_small_data_pointer == 0)
-+			  {
-+			    ret = FALSE;
-+			    r = bfd_reloc_undefined;
-+			    goto check_reloc;
-+			  }
-+
-+			/* At this point `relocation' contains the object's
-+			   address.  */
-+			relocation -= rw_small_data_pointer;
-+			/* Now it contains the offset from _SDA_BASE_.  */
-+			r = _bfd_final_link_relocate (howto, input_bfd,
-+						      input_section,
-+						      contents, offset,
-+						      relocation, addend);
-+		      }
-+		    else
-+		      {
-+			(*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
-+					       bfd_get_filename (input_bfd),
-+					       sym_name,
-+					       microblaze_elf_howto_table[(int) r_type]->name,
-+					       bfd_section_name (sec));
-+			/*bfd_set_error (bfd_error_bad_value); ??? why? */
-+			ret = FALSE;
-+			continue;
-+		      }
-+		  }
-+	      }
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_32_SYM_OP_SYM:
-+	      break; /* Do nothing.  */
-+
-+	    case (int) R_MICROBLAZE_GOTPC_64:
-+	      relocation = htab->sgotplt->output_section->vma
-+		+ htab->sgotplt->output_offset;
-+	      relocation -= (input_section->output_section->vma
-+			     + input_section->output_offset
-+			     + offset + INST_WORD_SIZE);
-+	      relocation += addend;
-+	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+	                  contents + offset + endian);
-+	      bfd_put_16 (input_bfd, relocation & 0xffff,
-+	                  contents + offset + endian + INST_WORD_SIZE);
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_PLT_64:
-+	      {
-+		bfd_vma immediate;
-+		if (htab->splt != NULL && h != NULL
-+		    && h->plt.offset != (bfd_vma) -1)
-+		  {
-+		    relocation = (htab->splt->output_section->vma
-+				  + htab->splt->output_offset
-+				  + h->plt.offset);
-+		    unresolved_reloc = FALSE;
-+		    immediate = relocation - (input_section->output_section->vma
-+					      + input_section->output_offset
-+					      + offset + INST_WORD_SIZE);
-+		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
-+		                contents + offset + endian);
-+		    bfd_put_16 (input_bfd, immediate & 0xffff,
-+		                contents + offset + endian + INST_WORD_SIZE);
-+		  }
-+		else
-+		  {
-+		    relocation -= (input_section->output_section->vma
-+				   + input_section->output_offset
-+				   + offset + INST_WORD_SIZE);
-+		    immediate = relocation;
-+		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
-+		                contents + offset + endian);
-+		    bfd_put_16 (input_bfd, immediate & 0xffff,
-+		                contents + offset + endian + INST_WORD_SIZE);
-+		  }
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_TLSGD:
-+	      tls_type = (TLS_TLS | TLS_GD);
-+	      goto dogot;
-+	    case (int) R_MICROBLAZE_TLSLD:
-+	      tls_type = (TLS_TLS | TLS_LD);
-+              /* Fall through. */
-+	    dogot:
-+	    case (int) R_MICROBLAZE_GOT_64:
-+	      {
-+		bfd_vma *offp;
-+		bfd_vma off, off2;
-+		unsigned long indx;
-+		bfd_vma static_value;
-+
-+		bfd_boolean need_relocs = FALSE;
-+		if (htab->sgot == NULL)
-+		  abort ();
-+
-+		indx = 0;
-+		offp = NULL;
-+
-+		/* 1. Identify GOT Offset;
-+		   2. Compute Static Values
-+		   3. Process Module Id, Process Offset
-+		   4. Fixup Relocation with GOT offset value. */
-+
-+		/* 1. Determine GOT Offset to use : TLS_LD, global, local */
-+		if (IS_TLS_LD (tls_type))
-+		  offp = &htab->tlsld_got.offset;
-+		else if (h != NULL)
-+		  {
-+		    if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1)
-+			offp = &h->got.offset;
-+		    else
-+			abort ();
-+		  }
-+		else
-+		  {
-+		    if (local_got_offsets == NULL)
-+		      abort ();
-+		    offp = &local_got_offsets[r_symndx];
-+		  }
-+
-+		if (!offp)
-+		  abort ();
-+
-+		off = (*offp) & ~1;
-+		off2 = off;
-+
-+		if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
-+		  off2 = off + 4;
-+
-+		/* Symbol index to use for relocs */
-+		if (h != NULL)
-+		  {
-+		    bfd_boolean dyn =
-+			elf_hash_table (info)->dynamic_sections_created;
-+
-+		    if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
-+							 bfd_link_pic (info),
-+							 h)
-+			&& (!bfd_link_pic (info)
-+			    || !SYMBOL_REFERENCES_LOCAL (info, h)))
-+		      indx = h->dynindx;
-+		  }
-+
-+		/* Need to generate relocs ? */
-+		if ((bfd_link_pic (info) || indx != 0)
-+		    && (h == NULL
-+		    || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-+		    || h->root.type != bfd_link_hash_undefweak))
-+		  need_relocs = TRUE;
-+
-+		/* 2. Compute/Emit Static value of r-expression */
-+		static_value = relocation + addend;
-+
-+		/* 3. Process module-id and offset */
-+		if (! ((*offp) & 1) )
-+		  {
-+		    bfd_vma got_offset;
-+
-+		    got_offset = (htab->sgot->output_section->vma
-+				  + htab->sgot->output_offset
-+				  + off);
-+
-+		    /* Process module-id */
-+		    if (IS_TLS_LD(tls_type))
-+		      {
-+			if (! bfd_link_pic (info))
-+			  {
-+			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
-+			  }
-+			else
-+			  {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot, htab->srelgot->reloc_count++,
-+			      /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
-+			      got_offset, 0);
-+			  }
-+		      }
-+		    else if (IS_TLS_GD(tls_type))
-+		      {
-+		        if (! need_relocs)
-+			  {
-+			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
-+			  }
-+		        else
-+			  {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot,
-+			      htab->srelgot->reloc_count++,
-+			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
-+			      got_offset, indx ? 0 : static_value);
-+			  }
-+		      }
-+
-+		    /* Process Offset */
-+		    if (htab->srelgot == NULL)
-+		      abort ();
-+
-+		    got_offset = (htab->sgot->output_section->vma
-+				  + htab->sgot->output_offset
-+				  + off2);
-+		    if (IS_TLS_LD(tls_type))
-+		      {
-+		        /* For LD, offset should be 0 */
-+		        *offp |= 1;
-+		        bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2);
-+		      }
-+		    else if (IS_TLS_GD(tls_type))
-+		      {
-+		        *offp |= 1;
-+		        static_value -= dtprel_base(info);
-+		        if (need_relocs)
-+		          {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot, htab->srelgot->reloc_count++,
-+			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
-+			      got_offset, indx ? 0 : static_value);
-+		          }
-+		        else
-+			  {
-+			    bfd_put_32 (output_bfd, static_value,
-+					htab->sgot->contents + off2);
-+		          }
-+		      }
-+		    else
-+		      {
-+			  bfd_put_32 (output_bfd, static_value,
-+				      htab->sgot->contents + off2);
-+
-+			  /* Relocs for dyn symbols generated by
-+			     finish_dynamic_symbols */
-+			  if (bfd_link_pic (info) && h == NULL)
-+			    {
-+			      *offp |= 1;
-+			      microblaze_elf_output_dynamic_relocation (output_bfd,
-+				htab->srelgot, htab->srelgot->reloc_count++,
-+				/* symindex= */ indx, R_MICROBLAZE_REL,
-+				got_offset, static_value);
-+			    }
-+		      }
-+		  }
-+
-+		/* 4. Fixup Relocation with GOT offset value
-+		      Compute relative address of GOT entry for applying
-+		      the current relocation */
-+		relocation = htab->sgot->output_section->vma
-+			     + htab->sgot->output_offset
-+			     + off
-+			     - htab->sgotplt->output_section->vma
-+			     - htab->sgotplt->output_offset;
-+
-+		/* Apply Current Relocation */
-+		bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+		            contents + offset + endian);
-+		bfd_put_16 (input_bfd, relocation & 0xffff,
-+		            contents + offset + endian + INST_WORD_SIZE);
-+
-+		unresolved_reloc = FALSE;
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_GOTOFF_64:
-+	      {
-+		bfd_vma immediate;
-+		unsigned short lo, high;
-+		relocation += addend;
-+		relocation -= htab->sgotplt->output_section->vma
-+		  + htab->sgotplt->output_offset;
-+		/* Write this value into correct location.  */
-+		immediate = relocation;
-+		lo = immediate & 0x0000ffff;
-+		high = (immediate >> 16) & 0x0000ffff;
-+		bfd_put_16 (input_bfd, high, contents + offset + endian);
-+		bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian);
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_GOTOFF_32:
-+	      {
-+		relocation += addend;
-+		relocation -= htab->sgotplt->output_section->vma
-+		  + htab->sgotplt->output_offset;
-+		/* Write this value into correct location.  */
-+		bfd_put_32 (input_bfd, relocation, contents + offset);
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_TLSDTPREL64:
-+	      relocation += addend;
-+	      relocation -= dtprel_base(info);
-+	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			  contents + offset + endian);
-+	      bfd_put_16 (input_bfd, relocation & 0xffff,
-+			  contents + offset + endian + INST_WORD_SIZE);
-+	      break;
-+	    case (int) R_MICROBLAZE_64_PCREL :
-+	    case (int) R_MICROBLAZE_64:
-+	    case (int) R_MICROBLAZE_32:
-+	      {
-+		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
-+		   from removed linkonce sections, or sections discarded by
-+		   a linker script.  */
-+		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
-+		  {
-+		    relocation += addend;
-+		    if (r_type == R_MICROBLAZE_32)
-+		      bfd_put_32 (input_bfd, relocation, contents + offset);
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_64_PCREL)
-+			  relocation -= (input_section->output_section->vma
-+					 + input_section->output_offset
-+					 + offset + INST_WORD_SIZE);
-+			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			            contents + offset + endian);
-+			bfd_put_16 (input_bfd, relocation & 0xffff,
-+			            contents + offset + endian + INST_WORD_SIZE);
-+		      }
-+		    break;
-+		  }
-+
-+		if ((bfd_link_pic (info)
-+		     && (h == NULL
-+			 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-+			 || h->root.type != bfd_link_hash_undefweak)
-+		     && (!howto->pc_relative
-+			 || (h != NULL
-+			     && h->dynindx != -1
-+			     && (!info->symbolic
-+				 || !h->def_regular))))
-+		    || (!bfd_link_pic (info)
-+			&& h != NULL
-+			&& h->dynindx != -1
-+			&& !h->non_got_ref
-+			&& ((h->def_dynamic
-+			     && !h->def_regular)
-+			    || h->root.type == bfd_link_hash_undefweak
-+			    || h->root.type == bfd_link_hash_undefined)))
-+		  {
-+		    Elf_Internal_Rela outrel;
-+		    bfd_byte *loc;
-+		    bfd_boolean skip;
-+
-+		    /* When generating a shared object, these relocations
-+		       are copied into the output file to be resolved at run
-+		       time.  */
-+
-+		    BFD_ASSERT (sreloc != NULL);
-+
-+		    skip = FALSE;
-+
-+		    outrel.r_offset =
-+		      _bfd_elf_section_offset (output_bfd, info, input_section,
-+					       rel->r_offset);
-+		    if (outrel.r_offset == (bfd_vma) -1)
-+		      skip = TRUE;
-+		    else if (outrel.r_offset == (bfd_vma) -2)
-+		      skip = TRUE;
-+		    outrel.r_offset += (input_section->output_section->vma
-+					+ input_section->output_offset);
-+
-+		    if (skip)
-+		      memset (&outrel, 0, sizeof outrel);
-+		    /* h->dynindx may be -1 if the symbol was marked to
-+		       become local.  */
-+		    else if (h != NULL
-+			     && ((! info->symbolic && h->dynindx != -1)
-+				 || !h->def_regular))
-+		      {
-+			BFD_ASSERT (h->dynindx != -1);
-+			outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
-+			outrel.r_addend = addend;
-+		      }
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_32)
-+			  {
-+			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
-+			    outrel.r_addend = relocation + addend;
-+			  }
-+			else
-+			  {
-+			    BFD_FAIL ();
-+			    (*_bfd_error_handler)
-+			      (_("%pB: probably compiled without -fPIC?"),
-+			       input_bfd);
-+			    bfd_set_error (bfd_error_bad_value);
-+			    return FALSE;
-+			  }
-+		      }
-+
-+		    loc = sreloc->contents;
-+		    loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-+		    bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
-+		    break;
-+		  }
-+		else
-+		  {
-+		    relocation += addend;
-+		    if (r_type == R_MICROBLAZE_32)
-+		      bfd_put_32 (input_bfd, relocation, contents + offset);
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_64_PCREL)
-+			  relocation -= (input_section->output_section->vma
-+					 + input_section->output_offset
-+					 + offset + INST_WORD_SIZE);
-+			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			            contents + offset + endian);
-+			bfd_put_16 (input_bfd, relocation & 0xffff,
-+			            contents + offset + endian + INST_WORD_SIZE);
-+		      }
-+		    break;
-+		  }
-+	      }
-+
-+	    default :
-+	      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
-+					    contents, offset,
-+					    relocation, addend);
-+	      break;
-+	    }
-+	}
-+
-+    check_reloc:
-+
-+      if (r != bfd_reloc_ok)
-+	{
-+	  /* FIXME: This should be generic enough to go in a utility.  */
-+	  const char *name;
-+
-+	  if (h != NULL)
-+	    name = h->root.root.string;
-+	  else
-+	    {
-+	      name = (bfd_elf_string_from_elf_section
-+		      (input_bfd, symtab_hdr->sh_link, sym->st_name));
-+	      if (name == NULL || *name == '\0')
-+		name = bfd_section_name (sec);
-+	    }
-+
-+	  if (errmsg != NULL)
-+	    goto common_error;
-+
-+	  switch (r)
-+	    {
-+	    case bfd_reloc_overflow:
-+	      (*info->callbacks->reloc_overflow)
-+		(info, (h ? &h->root : NULL), name, howto->name,
-+		 (bfd_vma) 0, input_bfd, input_section, offset);
-+	      break;
-+
-+	    case bfd_reloc_undefined:
-+	      (*info->callbacks->undefined_symbol)
-+		(info, name, input_bfd, input_section, offset, TRUE);
-+	      break;
-+
-+	    case bfd_reloc_outofrange:
-+	      errmsg = _("internal error: out of range error");
-+	      goto common_error;
-+
-+	    case bfd_reloc_notsupported:
-+	      errmsg = _("internal error: unsupported relocation error");
-+	      goto common_error;
-+
-+	    case bfd_reloc_dangerous:
-+	      errmsg = _("internal error: dangerous error");
-+	      goto common_error;
-+
-+	    default:
-+	      errmsg = _("internal error: unknown error");
-+	      /* Fall through.  */
-+	    common_error:
-+	      (*info->callbacks->warning) (info, errmsg, name, input_bfd,
-+					   input_section, offset);
-+	      break;
-+	    }
-+	}
-+    }
-+
-+  return ret;
-+}
-+
-+/* Calculate fixup value for reference.  */
-+
-+static int
-+calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
-+{
-+  bfd_vma end = start + size;
-+  int i, fixup = 0;
-+
-+  if (sec == NULL || sec->relax == NULL)
-+    return 0;
-+
-+  /* Look for addr in relax table, total fixup value.  */
-+  for (i = 0; i < sec->relax_count; i++)
-+    {
-+      if (end <= sec->relax[i].addr)
-+        break;
-+      if ((end != start) && (start > sec->relax[i].addr))
-+        continue;
-+      fixup += sec->relax[i].size;
-+    }
-+  return fixup;
-+}
-+
-+/* Read-modify-write into the bfd, an immediate value into appropriate fields of
-+   a 32-bit instruction.  */
-+static void
-+microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-+{
-+    unsigned long instr = bfd_get_32 (abfd, bfd_addr);
-+    instr &= ~0x0000ffff;
-+    instr |= (val & 0x0000ffff);
-+    bfd_put_32 (abfd, instr, bfd_addr);
-+}
-+
-+/* Read-modify-write into the bfd, an immediate value into appropriate fields of
-+   two consecutive 32-bit instructions.  */
-+static void
-+microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-+{
-+    unsigned long instr_hi;
-+    unsigned long instr_lo;
-+
-+    instr_hi = bfd_get_32 (abfd, bfd_addr);
-+    instr_hi &= ~0x0000ffff;
-+    instr_hi |= ((val >> 16) & 0x0000ffff);
-+    bfd_put_32 (abfd, instr_hi, bfd_addr);
-+
-+    instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
-+    instr_lo &= ~0x0000ffff;
-+    instr_lo |= (val & 0x0000ffff);
-+    bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_relax_section (bfd *abfd,
-+			      asection *sec,
-+			      struct bfd_link_info *link_info,
-+			      bfd_boolean *again)
-+{
-+  Elf_Internal_Shdr *symtab_hdr;
-+  Elf_Internal_Rela *internal_relocs;
-+  Elf_Internal_Rela *free_relocs = NULL;
-+  Elf_Internal_Rela *irel, *irelend;
-+  bfd_byte *contents = NULL;
-+  bfd_byte *free_contents = NULL;
-+  int rel_count;
-+  unsigned int shndx;
-+  int i, sym_index;
-+  asection *o;
-+  struct elf_link_hash_entry *sym_hash;
-+  Elf_Internal_Sym *isymbuf, *isymend;
-+  Elf_Internal_Sym *isym;
-+  int symcount;
-+  int offset;
-+  bfd_vma src, dest;
-+
-+  /* We only do this once per section.  We may be able to delete some code
-+     by running multiple passes, but it is not worth it.  */
-+  *again = FALSE;
-+
-+  /* Only do this for a text section.  */
-+  if (bfd_link_relocatable (link_info)
-+      || (sec->flags & SEC_RELOC) == 0
-+      || (sec->reloc_count == 0)
-+      || (sec->flags & SEC_CODE) == 0)
-+    return TRUE;
-+
-+  BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
-+
-+  /* If this is the first time we have been called for this section,
-+     initialize the cooked size.  */
-+  if (sec->size == 0)
-+    sec->size = sec->rawsize;
-+
-+  /* Get symbols for this section.  */
-+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
-+  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
-+  symcount =  symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
-+  if (isymbuf == NULL)
-+    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
-+ 			     	    0, NULL, NULL, NULL);
-+  BFD_ASSERT (isymbuf != NULL);
-+
-+  internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
-+  if (internal_relocs == NULL)
-+    goto error_return;
-+  if (! link_info->keep_memory)
-+    free_relocs = internal_relocs;
-+
-+  sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
-+						  * sizeof (struct relax_table));
-+  if (sec->relax == NULL)
-+    goto error_return;
-+  sec->relax_count = 0;
-+
-+  irelend = internal_relocs + sec->reloc_count;
-+  rel_count = 0;
-+  for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
-+    {
-+      bfd_vma symval;
-+      if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
-+	  && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ))
-+	continue; /* Can't delete this reloc.  */
-+
-+      /* Get the section contents.  */
-+      if (contents == NULL)
-+	{
-+	  if (elf_section_data (sec)->this_hdr.contents != NULL)
-+	    contents = elf_section_data (sec)->this_hdr.contents;
-+	  else
-+	    {
-+	      contents = (bfd_byte *) bfd_malloc (sec->size);
-+	      if (contents == NULL)
-+		goto error_return;
-+	      free_contents = contents;
-+
-+	      if (!bfd_get_section_contents (abfd, sec, contents,
-+					     (file_ptr) 0, sec->size))
-+		goto error_return;
-+              elf_section_data (sec)->this_hdr.contents = contents;
-+	    }
-+	}
-+
-+      /* Get the value of the symbol referred to by the reloc.  */
-+      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
-+	{
-+	  /* A local symbol.  */
-+	  asection *sym_sec;
-+
-+	  isym = isymbuf + ELF64_R_SYM (irel->r_info);
-+          if (isym->st_shndx == SHN_UNDEF)
-+	    sym_sec = bfd_und_section_ptr;
-+	  else if (isym->st_shndx == SHN_ABS)
-+	    sym_sec = bfd_abs_section_ptr;
-+	  else if (isym->st_shndx == SHN_COMMON)
-+	    sym_sec = bfd_com_section_ptr;
-+	  else
-+	    sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
-+
-+	  symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
-+	}
-+      else
-+	{
-+	  unsigned long indx;
-+	  struct elf_link_hash_entry *h;
-+
-+	  indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
-+	  h = elf_sym_hashes (abfd)[indx];
-+	  BFD_ASSERT (h != NULL);
-+
-+          if (h->root.type != bfd_link_hash_defined
-+	      && h->root.type != bfd_link_hash_defweak)
-+	    /* This appears to be a reference to an undefined
-+	       symbol.  Just ignore it--it will be caught by the
-+	       regular reloc processing.  */
-+	    continue;
-+
-+	  symval = (h->root.u.def.value
-+		    + h->root.u.def.section->output_section->vma
-+		    + h->root.u.def.section->output_offset);
-+	}
-+
-+      /* If this is a PC-relative reloc, subtract the instr offset from
-+         the symbol value.  */
-+      if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
-+	{
-+	  symval = symval + irel->r_addend
-+	    - (irel->r_offset
-+	       + sec->output_section->vma
-+	       + sec->output_offset);
-+        }
-+      else
-+	symval += irel->r_addend;
-+
-+      if ((symval & 0xffff8000) == 0)
-+	{
-+          /* We can delete this instruction.  */
-+	  sec->relax[sec->relax_count].addr = irel->r_offset;
-+	  sec->relax[sec->relax_count].size = INST_WORD_SIZE;
-+	  sec->relax_count++;
-+
-+	  /* Rewrite relocation type.  */
-+          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
-+	    {
-+	    case R_MICROBLAZE_64_PCREL:
-+	      irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
-+                                           (int) R_MICROBLAZE_32_PCREL_LO);
-+	      break;
-+	    case R_MICROBLAZE_64:
-+              irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
-+                                           (int) R_MICROBLAZE_32_LO);
-+	      break;
-+	    default:
-+	      /* Cannot happen.  */
-+	      BFD_ASSERT (FALSE);
-+            }
-+        }
-+    } /* Loop through all relocations.  */
-+
-+  /* Loop through the relocs again, and see if anything needs to change.  */
-+  if (sec->relax_count > 0)
-+    {
-+      shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
-+      rel_count = 0;
-+      sec->relax[sec->relax_count].addr = sec->size;
-+
-+      for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
-+        {
-+	  bfd_vma nraddr;
-+
-+          /* Get the new reloc address.  */
-+	  nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
-+          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
-+	    {
-+	    default:
-+	      break;
-+	    case R_MICROBLAZE_64_PCREL:
-+	      break;
-+	    case R_MICROBLAZE_64:
-+	    case R_MICROBLAZE_32_LO:
-+	      /* If this reloc is against a symbol defined in this
-+	         section, we must check the addend to see it will put the value in
-+	         range to be adjusted, and hence must be changed.  */
-+	      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
-+	        {
-+		  isym = isymbuf + ELF64_R_SYM (irel->r_info);
-+		  /* Only handle relocs against .text.  */
-+		  if (isym->st_shndx == shndx
-+		      && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
-+		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
-+	        }
-+	      break;
-+	    case R_MICROBLAZE_NONE:
-+	    case R_MICROBLAZE_32_NONE:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+ 		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
-+	    case R_MICROBLAZE_64_NONE:
-+	      {
-+	        /* This was a PC-relative 64-bit instruction that was
-+ 		   completely resolved.  */
-+	        int sfix, efix;
-+	        bfd_vma target_address;
-+		target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
-+		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
-+		efix = calc_fixup (target_address, 0, sec);
-+		irel->r_addend -= (efix - sfix);
-+    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
-+                                       + INST_WORD_SIZE, irel->r_addend);
-+	      }
-+	      break;
-+	    }
-+          irel->r_offset = nraddr;
-+        } /* Change all relocs in this section.  */
-+
-+      /* Look through all other sections.  */
-+      for (o = abfd->sections; o != NULL; o = o->next)
-+        {
-+          Elf_Internal_Rela *irelocs;
-+          Elf_Internal_Rela *irelscan, *irelscanend;
-+          bfd_byte *ocontents;
-+
-+          if (o == sec
-+              || (o->flags & SEC_RELOC) == 0
-+              || o->reloc_count == 0)
-+            continue;
-+
-+          /* We always cache the relocs.  Perhaps, if info->keep_memory is
-+             FALSE, we should free them, if we are permitted to.  */
-+
-+          irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE);
-+          if (irelocs == NULL)
-+            goto error_return;
-+
-+          ocontents = NULL;
-+          irelscanend = irelocs + o->reloc_count;
-+          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
-+            {
-+              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
-+                {
-+                  unsigned int val;
-+
-+                  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+                  /* hax: We only do the following fixup for debug location lists.  */
-+                  if (strcmp(".debug_loc", o->name))
-+                    continue;
-+
-+                  /* This was a PC-relative instruction that was completely resolved.  */
-+                  if (ocontents == NULL)
-+                    {
-+		      if (elf_section_data (o)->this_hdr.contents != NULL)
-+		          ocontents = elf_section_data (o)->this_hdr.contents;
-+		      else
-+		        {
-+		          /* We always cache the section contents.
-+			     Perhaps, if info->keep_memory is FALSE, we
-+			     should free them, if we are permitted to.  */
-+
-+		          if (o->rawsize == 0)
-+			      o->rawsize = o->size;
-+		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+		          if (ocontents == NULL)
-+			      goto error_return;
-+		          if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                         (file_ptr) 0,
-+                                                         o->rawsize))
-+                              goto error_return;
-+		          elf_section_data (o)->this_hdr.contents = ocontents;
-+		        }
-+		    }
-+
-+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+                  if (val != irelscan->r_addend) {
-+                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+                  }
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                                     irelscan->r_addend);
-+              }
-+              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
-+                {
-+	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+                  /* Look at the reloc only if the value has been resolved.  */
-+                  if (isym->st_shndx == shndx
-+                      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+                    {
-+                      if (ocontents == NULL)
-+                        {
-+                          if (elf_section_data (o)->this_hdr.contents != NULL)
-+                            ocontents = elf_section_data (o)->this_hdr.contents;
-+                          else
-+                            {
-+                              /* We always cache the section contents.
-+                                 Perhaps, if info->keep_memory is FALSE, we
-+                                 should free them, if we are permitted to.  */
-+		              if (o->rawsize == 0)
-+			        o->rawsize = o->size;
-+                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+                              if (ocontents == NULL)
-+                                goto error_return;
-+                              if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                             (file_ptr) 0,
-+							     o->rawsize))
-+                                goto error_return;
-+                              elf_section_data (o)->this_hdr.contents = ocontents;
-+                            }
-+
-+                        }
-+		      irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-+                    }
-+		  else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
-+		    {
-+		      isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		      /* Look at the reloc only if the value has been resolved.  */
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+              irelscan->r_addend -= calc_fixup (irelscan->r_addend
-+							+ isym->st_value,
-+							0,
-+							sec);
-+		    }
-+		}
-+	      else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
-+		       || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO))
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+		      bfd_vma target_address;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+
-+		      unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+		      immediate = instr & 0x0000ffff;
-+		      target_address = immediate;
-+		      offset = calc_fixup (target_address, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+          microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                             irelscan->r_addend);
-+		    }
-+		}
-+
-+	      if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64)
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset);
-+          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset
-+                                                + INST_WORD_SIZE);
-+          immediate = (instr_hi & 0x0000ffff) << 16;
-+          immediate |= (instr_lo & 0x0000ffff);
-+		      offset = calc_fixup (irelscan->r_addend, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+		    }
-+		}
-+	      else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+		      bfd_vma target_address;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset);
-+          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset
-+                                                + INST_WORD_SIZE);
-+          immediate = (instr_hi & 0x0000ffff) << 16;
-+          immediate |= (instr_lo & 0x0000ffff);
-+		      target_address = immediate;
-+		      offset = calc_fixup (target_address, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+          microblaze_bfd_write_imm_value_64 (abfd, ocontents
-+                                             + irelscan->r_offset, immediate);
-+		    }
-+		}
-+            }
-+        }
-+
-+      /* Adjust the local symbols defined in this section.  */
-+      isymend = isymbuf + symtab_hdr->sh_info;
-+      for (isym = isymbuf; isym < isymend; isym++)
-+        {
-+          if (isym->st_shndx == shndx)
-+            {
-+              isym->st_value -= calc_fixup (isym->st_value, 0, sec);
-+              if (isym->st_size)
-+                isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
-+            }
-+        }
-+
-+      /* Now adjust the global symbols defined in this section.  */
-+      isym = isymbuf + symtab_hdr->sh_info;
-+      symcount =  (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
-+      for (sym_index = 0; sym_index < symcount; sym_index++)
-+        {
-+          sym_hash = elf_sym_hashes (abfd)[sym_index];
-+          if ((sym_hash->root.type == bfd_link_hash_defined
-+                  || sym_hash->root.type == bfd_link_hash_defweak)
-+              && sym_hash->root.u.def.section == sec)
-+            {
-+              sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
-+                                                        0, sec);
-+              if (sym_hash->size)
-+                sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
-+                                              sym_hash->size, sec);
-+            }
-+        }
-+
-+      /* Physically move the code and change the cooked size.  */
-+      dest = sec->relax[0].addr;
-+      for (i = 0; i < sec->relax_count; i++)
-+        {
-+          int len;
-+          src = sec->relax[i].addr + sec->relax[i].size;
-+          len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size;
-+
-+          memmove (contents + dest, contents + src, len);
-+          sec->size -= sec->relax[i].size;
-+          dest += len;
-+        }
-+
-+      elf_section_data (sec)->relocs = internal_relocs;
-+      free_relocs = NULL;
-+
-+      elf_section_data (sec)->this_hdr.contents = contents;
-+      free_contents = NULL;
-+
-+      symtab_hdr->contents = (bfd_byte *) isymbuf;
-+    }
-+
-+  if (free_relocs != NULL)
-+    {
-+      free (free_relocs);
-+      free_relocs = NULL;
-+    }
-+
-+  if (free_contents != NULL)
-+    {
-+      if (!link_info->keep_memory)
-+	free (free_contents);
-+      else
-+	/* Cache the section contents for elf_link_input_bfd.  */
-+	elf_section_data (sec)->this_hdr.contents = contents;
-+      free_contents = NULL;
-+    }
-+
-+  if (sec->relax_count == 0)
-+    {
-+      *again = FALSE;
-+      free (sec->relax);
-+      sec->relax = NULL;
-+    }
-+  else
-+    *again = TRUE;
-+  return TRUE;
-+
-+ error_return:
-+  if (free_relocs != NULL)
-+    free (free_relocs);
-+  if (free_contents != NULL)
-+    free (free_contents);
-+  if (sec->relax != NULL)
-+    {
-+      free (sec->relax);
-+      sec->relax = NULL;
-+      sec->relax_count = 0;
-+    }
-+  return FALSE;
-+}
-+
-+/* Return the section that should be marked against GC for a given
-+   relocation.  */
-+
-+static asection *
-+microblaze_elf_gc_mark_hook (asection *sec,
-+			     struct bfd_link_info * info,
-+     			     Elf_Internal_Rela * rel,
-+     			     struct elf_link_hash_entry * h,
-+     			     Elf_Internal_Sym * sym)
-+{
-+  if (h != NULL)
-+    switch (ELF64_R_TYPE (rel->r_info))
-+      {
-+      case R_MICROBLAZE_GNU_VTINHERIT:
-+      case R_MICROBLAZE_GNU_VTENTRY:
-+	return NULL;
-+      }
-+
-+  return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
-+}
-+
-+/* PIC support.  */
-+
-+#define PLT_ENTRY_SIZE 16
-+
-+#define PLT_ENTRY_WORD_0  0xb0000000          /* "imm 0".  */
-+#define PLT_ENTRY_WORD_1  0xe9940000          /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT.  */
-+#define PLT_ENTRY_WORD_1_NOPIC  0xe9800000    /* "lwi r12,r0,0" - non-PIC object.  */
-+#define PLT_ENTRY_WORD_2  0x98186000          /* "brad r12".  */
-+#define PLT_ENTRY_WORD_3  0x80000000          /* "nop".  */
-+
-+/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
-+   shortcuts to them in our hash table.  */
-+
-+static bfd_boolean
-+create_got_section (bfd *dynobj, struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  if (! _bfd_elf_create_got_section (dynobj, info))
-+    return FALSE;
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  htab->sgot = bfd_get_linker_section (dynobj, ".got");
-+  htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt");
-+  if (!htab->sgot || !htab->sgotplt)
-+    return FALSE;
-+
-+  if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL)
-+    htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got");
-+  if (htab->srelgot == NULL
-+      || ! bfd_set_section_flags (htab->srelgot, SEC_ALLOC
-+                                  | SEC_LOAD
-+                                  | SEC_HAS_CONTENTS
-+                                  | SEC_IN_MEMORY
-+                                  | SEC_LINKER_CREATED
-+                                  | SEC_READONLY)
-+      || ! bfd_set_section_alignment (htab->srelgot, 2))
-+    return FALSE;
-+  return TRUE;
-+}
-+
-+static bfd_boolean
-+update_local_sym_info (bfd *abfd,
-+		       Elf_Internal_Shdr *symtab_hdr,
-+		       unsigned long r_symndx,
-+		       unsigned int tls_type)
-+{
-+  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
-+  unsigned char *local_got_tls_masks;
-+
-+  if (local_got_refcounts == NULL)
-+    {
-+      bfd_size_type size = symtab_hdr->sh_info;
-+
-+      size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
-+      local_got_refcounts = bfd_zalloc (abfd, size);
-+      if (local_got_refcounts == NULL)
-+        return FALSE;
-+      elf_local_got_refcounts (abfd) = local_got_refcounts;
-+    }
-+
-+  local_got_tls_masks =
-+         (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
-+  local_got_tls_masks[r_symndx] |= tls_type;
-+  local_got_refcounts[r_symndx] += 1;
-+
-+  return TRUE;
-+}
-+/* Look through the relocs for a section during the first phase.  */
-+
-+static bfd_boolean
-+microblaze_elf_check_relocs (bfd * abfd,
-+			     struct bfd_link_info * info,
-+     			     asection * sec,
-+			     const Elf_Internal_Rela * relocs)
-+{
-+  Elf_Internal_Shdr *           symtab_hdr;
-+  struct elf_link_hash_entry ** sym_hashes;
-+  struct elf_link_hash_entry ** sym_hashes_end;
-+  const Elf_Internal_Rela *     rel;
-+  const Elf_Internal_Rela *     rel_end;
-+  struct elf64_mb_link_hash_table *htab;
-+  asection *sreloc = NULL;
-+
-+  if (bfd_link_relocatable (info))
-+    return TRUE;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
-+  sym_hashes = elf_sym_hashes (abfd);
-+  sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
-+  if (!elf_bad_symtab (abfd))
-+    sym_hashes_end -= symtab_hdr->sh_info;
-+
-+  rel_end = relocs + sec->reloc_count;
-+
-+  for (rel = relocs; rel < rel_end; rel++)
-+    {
-+      unsigned int r_type;
-+      struct elf_link_hash_entry * h;
-+      unsigned long r_symndx;
-+      unsigned char tls_type = 0;
-+
-+      r_symndx = ELF64_R_SYM (rel->r_info);
-+      r_type = ELF64_R_TYPE (rel->r_info);
-+
-+      if (r_symndx < symtab_hdr->sh_info)
-+        h = NULL;
-+      else
-+	{
-+	  h = sym_hashes [r_symndx - symtab_hdr->sh_info];
-+
-+	  /* PR15323, ref flags aren't set for references in the same
-+	     object.  */
-+	  h->root.non_ir_ref_regular = 1;
-+	}
-+
-+      switch (r_type)
-+        {
-+	  /* This relocation describes the C++ object vtable hierarchy.
-+	     Reconstruct it for later use during GC.  */
-+        case R_MICROBLAZE_GNU_VTINHERIT:
-+          if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
-+            return FALSE;
-+          break;
-+
-+	  /* This relocation describes which C++ vtable entries are actually
-+	     used.  Record for later use during GC.  */
-+        case R_MICROBLAZE_GNU_VTENTRY:
-+          if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
-+            return FALSE;
-+          break;
-+
-+	  /* This relocation requires .plt entry.  */
-+        case R_MICROBLAZE_PLT_64:
-+          if (h != NULL)
-+	    {
-+	      h->needs_plt = 1;
-+	      h->plt.refcount += 1;
-+	    }
-+          break;
-+
-+	  /* This relocation requires .got entry.  */
-+        case R_MICROBLAZE_TLSGD:
-+          tls_type |= (TLS_TLS | TLS_GD);
-+          goto dogottls;
-+        case R_MICROBLAZE_TLSLD:
-+          tls_type |= (TLS_TLS | TLS_LD);
-+        dogottls:
-+          sec->has_tls_reloc = 1;
-+          /* Fall through. */
-+        case R_MICROBLAZE_GOT_64:
-+          if (htab->sgot == NULL)
-+            {
-+              if (htab->elf.dynobj == NULL)
-+                htab->elf.dynobj = abfd;
-+              if (!create_got_section (htab->elf.dynobj, info))
-+                return FALSE;
-+            }
-+          if (h != NULL)
-+	    {
-+	      h->got.refcount += 1;
-+	      elf64_mb_hash_entry (h)->tls_mask |= tls_type;
-+	    }
-+          else
-+	    {
-+	      if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
-+		return FALSE;
-+	    }
-+          break;
-+
-+        case R_MICROBLAZE_64:
-+        case R_MICROBLAZE_64_PCREL:
-+        case R_MICROBLAZE_32:
-+          {
-+            if (h != NULL && !bfd_link_pic (info))
-+	      {
-+		/* we may need a copy reloc.  */
-+		h->non_got_ref = 1;
-+
-+		/* we may also need a .plt entry.  */
-+		h->plt.refcount += 1;
-+		if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
-+		  h->pointer_equality_needed = 1;
-+	      }
-+
-+
-+	    /* If we are creating a shared library, and this is a reloc
-+	       against a global symbol, or a non PC relative reloc
-+	       against a local symbol, then we need to copy the reloc
-+	       into the shared library.  However, if we are linking with
-+	       -Bsymbolic, we do not need to copy a reloc against a
-+	       global symbol which is defined in an object we are
-+	       including in the link (i.e., DEF_REGULAR is set).  At
-+	       this point we have not seen all the input files, so it is
-+	       possible that DEF_REGULAR is not set now but will be set
-+	       later (it is never cleared).  In case of a weak definition,
-+	       DEF_REGULAR may be cleared later by a strong definition in
-+	       a shared library.  We account for that possibility below by
-+	       storing information in the relocs_copied field of the hash
-+	       table entry.  A similar situation occurs when creating
-+	       shared libraries and symbol visibility changes render the
-+	       symbol local.
-+
-+	       If on the other hand, we are creating an executable, we
-+	       may need to keep relocations for symbols satisfied by a
-+	       dynamic library if we manage to avoid copy relocs for the
-+	       symbol.  */
-+
-+            if ((bfd_link_pic (info)
-+                 && (sec->flags & SEC_ALLOC) != 0
-+                 && (r_type != R_MICROBLAZE_64_PCREL
-+                     || (h != NULL
-+			 && (! info->symbolic
-+			     || h->root.type == bfd_link_hash_defweak
-+			     || !h->def_regular))))
-+                || (!bfd_link_pic (info)
-+                    && (sec->flags & SEC_ALLOC) != 0
-+                    && h != NULL
-+                    && (h->root.type == bfd_link_hash_defweak
-+                        || !h->def_regular)))
-+              {
-+                struct elf64_mb_dyn_relocs *p;
-+                struct elf64_mb_dyn_relocs **head;
-+
-+                /* When creating a shared object, we must copy these
-+                   relocs into the output file.  We create a reloc
-+                   section in dynobj and make room for the reloc.  */
-+
-+		if (sreloc == NULL)
-+		  {
-+		    bfd *dynobj;
-+
-+		    if (htab->elf.dynobj == NULL)
-+		      htab->elf.dynobj = abfd;
-+		    dynobj = htab->elf.dynobj;
-+
-+		    sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
-+								  2, abfd, 1);
-+		    if (sreloc == NULL)
-+		      return FALSE;
-+		  }
-+
-+		/* If this is a global symbol, we count the number of
-+		   relocations we need for this symbol.  */
-+		if (h != NULL)
-+		  head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs;
-+		else
-+		  {
-+		    /* Track dynamic relocs needed for local syms too.
-+		       We really need local syms available to do this
-+		       easily.  Oh well.  */
-+
-+		    asection *s;
-+		    Elf_Internal_Sym *isym;
-+		    void *vpp;
-+
-+		    isym = bfd_sym_from_r_symndx (&htab->sym_sec,
-+						  abfd, r_symndx);
-+		    if (isym == NULL)
-+		      return FALSE;
-+
-+		    s = bfd_section_from_elf_index (abfd, isym->st_shndx);
-+		    if (s == NULL)
-+		      return FALSE;
-+
-+		    vpp = &elf_section_data (s)->local_dynrel;
-+		    head = (struct elf64_mb_dyn_relocs **) vpp;
-+		  }
-+
-+		p = *head;
-+		if (p == NULL || p->sec != sec)
-+		  {
-+		    bfd_size_type amt = sizeof *p;
-+		    p = ((struct elf64_mb_dyn_relocs *)
-+			 bfd_alloc (htab->elf.dynobj, amt));
-+		    if (p == NULL)
-+		      return FALSE;
-+		    p->next = *head;
-+		    *head = p;
-+		    p->sec = sec;
-+		    p->count = 0;
-+		    p->pc_count = 0;
-+		  }
-+
-+		p->count += 1;
-+		if (r_type == R_MICROBLAZE_64_PCREL)
-+		  p->pc_count += 1;
-+	      }
-+          }
-+          break;
-+        }
-+    }
-+
-+  return TRUE;
-+}
-+
-+static bfd_boolean
-+microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (!htab->sgot && !create_got_section (dynobj, info))
-+    return FALSE;
-+
-+  if (!_bfd_elf_create_dynamic_sections (dynobj, info))
-+    return FALSE;
-+
-+  htab->splt = bfd_get_linker_section (dynobj, ".plt");
-+  htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
-+  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
-+  if (!bfd_link_pic (info))
-+    htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
-+
-+  if (!htab->splt || !htab->srelplt || !htab->sdynbss
-+      || (!bfd_link_pic (info) && !htab->srelbss))
-+    abort ();
-+
-+  return TRUE;
-+}
-+
-+/* Copy the extra info we tack onto an elf_link_hash_entry.  */
-+
-+static void
-+microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
-+				     struct elf_link_hash_entry *dir,
-+				     struct elf_link_hash_entry *ind)
-+{
-+  struct elf64_mb_link_hash_entry *edir, *eind;
-+
-+  edir = (struct elf64_mb_link_hash_entry *) dir;
-+  eind = (struct elf64_mb_link_hash_entry *) ind;
-+
-+  if (eind->dyn_relocs != NULL)
-+    {
-+      if (edir->dyn_relocs != NULL)
-+	{
-+	  struct elf64_mb_dyn_relocs **pp;
-+	  struct elf64_mb_dyn_relocs *p;
-+
-+	  if (ind->root.type == bfd_link_hash_indirect)
-+	    abort ();
-+
-+	  /* Add reloc counts against the weak sym to the strong sym
-+	     list.  Merge any entries against the same section.  */
-+	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
-+	    {
-+	      struct elf64_mb_dyn_relocs *q;
-+
-+	      for (q = edir->dyn_relocs; q != NULL; q = q->next)
-+		if (q->sec == p->sec)
-+		  {
-+		    q->pc_count += p->pc_count;
-+		    q->count += p->count;
-+		    *pp = p->next;
-+		    break;
-+		  }
-+	      if (q == NULL)
-+		pp = &p->next;
-+	    }
-+	  *pp = edir->dyn_relocs;
-+	}
-+
-+      edir->dyn_relocs = eind->dyn_relocs;
-+      eind->dyn_relocs = NULL;
-+    }
-+
-+  edir->tls_mask |= eind->tls_mask;
-+
-+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
-+				      struct elf_link_hash_entry *h)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry * eh;
-+  struct elf64_mb_dyn_relocs *p;
-+  asection *sdynbss, *s;
-+  unsigned int power_of_two;
-+  bfd *dynobj;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  /* If this is a function, put it in the procedure linkage table.  We
-+     will fill in the contents of the procedure linkage table later,
-+     when we know the address of the .got section.  */
-+  if (h->type == STT_FUNC
-+      || h->needs_plt)
-+    {
-+      if (h->plt.refcount <= 0
-+	  || SYMBOL_CALLS_LOCAL (info, h)
-+	  || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
-+	      && h->root.type == bfd_link_hash_undefweak))
-+	{
-+	  /* This case can occur if we saw a PLT reloc in an input
-+	     file, but the symbol was never referred to by a dynamic
-+	     object, or if all references were garbage collected.  In
-+	     such a case, we don't actually need to build a procedure
-+	     linkage table, and we can just do a PC32 reloc instead.  */
-+	  h->plt.offset = (bfd_vma) -1;
-+	  h->needs_plt = 0;
-+	}
-+
-+      return TRUE;
-+    }
-+  else
-+    /* It's possible that we incorrectly decided a .plt reloc was
-+       needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
-+       check_relocs.  We can't decide accurately between function and
-+       non-function syms in check-relocs;  Objects loaded later in
-+       the link may change h->type.  So fix it now.  */
-+    h->plt.offset = (bfd_vma) -1;
-+
-+  /* If this is a weak symbol, and there is a real definition, the
-+     processor independent code will have arranged for us to see the
-+     real definition first, and we can just use the same value.  */
-+  if (h->is_weakalias)
-+    {
-+      struct elf_link_hash_entry *def = weakdef (h);
-+      BFD_ASSERT (def->root.type == bfd_link_hash_defined);
-+      h->root.u.def.section = def->root.u.def.section;
-+      h->root.u.def.value = def->root.u.def.value;
-+      return TRUE;
-+    }
-+
-+  /* This is a reference to a symbol defined by a dynamic object which
-+     is not a function.  */
-+
-+  /* If we are creating a shared library, we must presume that the
-+     only references to the symbol are via the global offset table.
-+     For such cases we need not do anything here; the relocations will
-+     be handled correctly by relocate_section.  */
-+  if (bfd_link_pic (info))
-+    return TRUE;
-+
-+  /* If there are no references to this symbol that do not use the
-+     GOT, we don't need to generate a copy reloc.  */
-+  if (!h->non_got_ref)
-+    return TRUE;
-+
-+  /* If -z nocopyreloc was given, we won't generate them either.  */
-+  if (info->nocopyreloc)
-+    {
-+      h->non_got_ref = 0;
-+      return TRUE;
-+    }
-+
-+  eh = (struct elf64_mb_link_hash_entry *) h;
-+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
-+    {
-+      s = p->sec->output_section;
-+      if (s != NULL && (s->flags & SEC_READONLY) != 0)
-+	break;
-+    }
-+
-+  /* If we didn't find any dynamic relocs in read-only sections, then
-+     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
-+  if (p == NULL)
-+    {
-+      h->non_got_ref = 0;
-+      return TRUE;
-+    }
-+
-+  /* We must allocate the symbol in our .dynbss section, which will
-+     become part of the .bss section of the executable.  There will be
-+     an entry for this symbol in the .dynsym section.  The dynamic
-+     object will contain position independent code, so all references
-+     from the dynamic object to this symbol will go through the global
-+     offset table.  The dynamic linker will use the .dynsym entry to
-+     determine the address it must put in the global offset table, so
-+     both the dynamic object and the regular object will refer to the
-+     same memory location for the variable.  */
-+
-+  /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
-+     to copy the initial value out of the dynamic object and into the
-+     runtime process image.  */
-+  dynobj = elf_hash_table (info)->dynobj;
-+  BFD_ASSERT (dynobj != NULL);
-+  if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
-+    {
-+      htab->srelbss->size += sizeof (Elf64_External_Rela);
-+      h->needs_copy = 1;
-+    }
-+
-+  /* We need to figure out the alignment required for this symbol.  I
-+     have no idea how ELF linkers handle this.  */
-+  power_of_two = bfd_log2 (h->size);
-+  if (power_of_two > 3)
-+    power_of_two = 3;
-+
-+  sdynbss = htab->sdynbss;
-+  /* Apply the required alignment.  */
-+  sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two));
-+  if (power_of_two > bfd_section_alignment (sdynbss))
-+    {
-+      if (! bfd_set_section_alignment (sdynbss, power_of_two))
-+	return FALSE;
-+    }
-+
-+  /* Define the symbol as being at this point in the section.  */
-+  h->root.u.def.section = sdynbss;
-+  h->root.u.def.value = sdynbss->size;
-+
-+  /* Increment the section size to make room for the symbol.  */
-+  sdynbss->size += h->size;
-+  return TRUE;
-+}
-+
-+/* Allocate space in .plt, .got and associated reloc sections for
-+   dynamic relocs.  */
-+
-+static bfd_boolean
-+allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
-+{
-+  struct bfd_link_info *info;
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry *eh;
-+  struct elf64_mb_dyn_relocs *p;
-+
-+  if (h->root.type == bfd_link_hash_indirect)
-+    return TRUE;
-+
-+  info = (struct bfd_link_info *) dat;
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (htab->elf.dynamic_sections_created
-+      && h->plt.refcount > 0)
-+    {
-+      /* Make sure this symbol is output as a dynamic symbol.
-+	 Undefined weak syms won't yet be marked as dynamic.  */
-+      if (h->dynindx == -1
-+          && !h->forced_local)
-+        {
-+          if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+            return FALSE;
-+        }
-+
-+      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
-+        {
-+          asection *s = htab->splt;
-+
-+          /* The first entry in .plt is reserved.  */
-+          if (s->size == 0)
-+            s->size = PLT_ENTRY_SIZE;
-+
-+          h->plt.offset = s->size;
-+
-+          /* If this symbol is not defined in a regular file, and we are
-+             not generating a shared library, then set the symbol to this
-+             location in the .plt.  This is required to make function
-+             pointers compare as equal between the normal executable and
-+             the shared library.  */
-+          if (! bfd_link_pic (info)
-+              && !h->def_regular)
-+            {
-+              h->root.u.def.section = s;
-+              h->root.u.def.value = h->plt.offset;
-+            }
-+
-+          /* Make room for this entry.  */
-+          s->size += PLT_ENTRY_SIZE;
-+
-+          /* We also need to make an entry in the .got.plt section, which
-+             will be placed in the .got section by the linker script.  */
-+	  htab->sgotplt->size += 4;
-+
-+          /* We also need to make an entry in the .rel.plt section.  */
-+          htab->srelplt->size += sizeof (Elf64_External_Rela);
-+        }
-+      else
-+        {
-+          h->plt.offset = (bfd_vma) -1;
-+          h->needs_plt = 0;
-+        }
-+    }
-+  else
-+    {
-+      h->plt.offset = (bfd_vma) -1;
-+      h->needs_plt = 0;
-+    }
-+
-+  eh = (struct elf64_mb_link_hash_entry *) h;
-+  if (h->got.refcount > 0)
-+    {
-+      unsigned int need;
-+      asection *s;
-+
-+      /* Make sure this symbol is output as a dynamic symbol.
-+         Undefined weak syms won't yet be marked as dynamic.  */
-+      if (h->dynindx == -1
-+          && !h->forced_local)
-+        {
-+          if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+            return FALSE;
-+        }
-+
-+      need = 0;
-+      if ((eh->tls_mask & TLS_TLS) != 0)
-+        {
-+          /* Handle TLS Symbol */
-+          if ((eh->tls_mask & TLS_LD) != 0)
-+            {
-+              if (!eh->elf.def_dynamic)
-+                /* We'll just use htab->tlsld_got.offset.  This should
-+                   always be the case.  It's a little odd if we have
-+                   a local dynamic reloc against a non-local symbol.  */
-+                htab->tlsld_got.refcount += 1;
-+              else
-+                need += 8;
-+            }
-+          if ((eh->tls_mask & TLS_GD) != 0)
-+            need += 8;
-+        }
-+      else
-+        {
-+          /* Regular (non-TLS) symbol */
-+          need += 4;
-+        }
-+      if (need == 0)
-+        {
-+          h->got.offset = (bfd_vma) -1;
-+        }
-+      else
-+        {
-+          s = htab->sgot;
-+          h->got.offset = s->size;
-+          s->size += need;
-+          htab->srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
-+        }
-+    }
-+  else
-+    h->got.offset = (bfd_vma) -1;
-+
-+  if (eh->dyn_relocs == NULL)
-+    return TRUE;
-+
-+  /* In the shared -Bsymbolic case, discard space allocated for
-+     dynamic pc-relative relocs against symbols which turn out to be
-+     defined in regular objects.  For the normal shared case, discard
-+     space for pc-relative relocs that have become local due to symbol
-+     visibility changes.  */
-+
-+  if (bfd_link_pic (info))
-+    {
-+      if (h->def_regular
-+	  && (h->forced_local
-+	      || info->symbolic))
-+	{
-+	  struct elf64_mb_dyn_relocs **pp;
-+
-+	  for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
-+	    {
-+	      p->count -= p->pc_count;
-+	      p->pc_count = 0;
-+	      if (p->count == 0)
-+		*pp = p->next;
-+	      else
-+		pp = &p->next;
-+	    }
-+	}
-+    }
-+  else
-+    {
-+      /* For the non-shared case, discard space for relocs against
-+	 symbols which turn out to need copy relocs or are not
-+	 dynamic.  */
-+
-+      if (!h->non_got_ref
-+	  && ((h->def_dynamic
-+	       && !h->def_regular)
-+	      || (htab->elf.dynamic_sections_created
-+		  && (h->root.type == bfd_link_hash_undefweak
-+		      || h->root.type == bfd_link_hash_undefined))))
-+	{
-+	  /* Make sure this symbol is output as a dynamic symbol.
-+	     Undefined weak syms won't yet be marked as dynamic.  */
-+	  if (h->dynindx == -1
-+	      && !h->forced_local)
-+	    {
-+	      if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+		return FALSE;
-+	    }
-+
-+	  /* If that succeeded, we know we'll be keeping all the
-+	     relocs.  */
-+	  if (h->dynindx != -1)
-+	    goto keep;
-+	}
-+
-+      eh->dyn_relocs = NULL;
-+
-+    keep: ;
-+    }
-+
-+  /* Finally, allocate space.  */
-+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
-+    {
-+      asection *sreloc = elf_section_data (p->sec)->sreloc;
-+      sreloc->size += p->count * sizeof (Elf64_External_Rela);
-+    }
-+
-+  return TRUE;
-+}
-+
-+/* Set the sizes of the dynamic sections.  */
-+
-+static bfd_boolean
-+microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-+				      struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  bfd *dynobj;
-+  asection *s;
-+  bfd *ibfd;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  dynobj = htab->elf.dynobj;
-+  BFD_ASSERT (dynobj != NULL);
-+
-+  /* Set up .got offsets for local syms, and space for local dynamic
-+     relocs.  */
-+  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
-+    {
-+      bfd_signed_vma *local_got;
-+      bfd_signed_vma *end_local_got;
-+      bfd_size_type locsymcount;
-+      Elf_Internal_Shdr *symtab_hdr;
-+      unsigned char *lgot_masks;
-+      asection *srel;
-+
-+      if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
-+        continue;
-+
-+      for (s = ibfd->sections; s != NULL; s = s->next)
-+	{
-+	  struct elf64_mb_dyn_relocs *p;
-+
-+	  for (p = ((struct elf64_mb_dyn_relocs *)
-+		    elf_section_data (s)->local_dynrel);
-+	       p != NULL;
-+	       p = p->next)
-+	    {
-+	      if (!bfd_is_abs_section (p->sec)
-+		  && bfd_is_abs_section (p->sec->output_section))
-+		{
-+		  /* Input section has been discarded, either because
-+		     it is a copy of a linkonce section or due to
-+		     linker script /DISCARD/, so we'll be discarding
-+		     the relocs too.  */
-+		}
-+	      else if (p->count != 0)
-+		{
-+		  srel = elf_section_data (p->sec)->sreloc;
-+		  srel->size += p->count * sizeof (Elf64_External_Rela);
-+		  if ((p->sec->output_section->flags & SEC_READONLY) != 0)
-+		    info->flags |= DF_TEXTREL;
-+		}
-+	    }
-+	}
-+
-+      local_got = elf_local_got_refcounts (ibfd);
-+      if (!local_got)
-+        continue;
-+
-+      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
-+      locsymcount = symtab_hdr->sh_info;
-+      end_local_got = local_got + locsymcount;
-+      lgot_masks = (unsigned char *) end_local_got;
-+      s = htab->sgot;
-+      srel = htab->srelgot;
-+
-+      for (; local_got < end_local_got; ++local_got, ++lgot_masks)
-+	{
-+	  if (*local_got > 0)
-+	    {
-+	      unsigned int need = 0;
-+	      if ((*lgot_masks & TLS_TLS) != 0)
-+		{
-+		  if ((*lgot_masks & TLS_GD) != 0)
-+		    need += 8;
-+		  if ((*lgot_masks & TLS_LD) != 0)
-+		    htab->tlsld_got.refcount += 1;
-+		}
-+	      else
-+		need += 4;
-+
-+	      if (need == 0)
-+		{
-+		  *local_got = (bfd_vma) -1;
-+		}
-+	      else
-+		{
-+		  *local_got = s->size;
-+		  s->size += need;
-+		  if (bfd_link_pic (info))
-+		    srel->size += need * (sizeof (Elf64_External_Rela) / 4);
-+		}
-+            }
-+          else
-+            *local_got = (bfd_vma) -1;
-+        }
-+    }
-+
-+  /* Allocate global sym .plt and .got entries, and space for global
-+     sym dynamic relocs.  */
-+  elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
-+
-+  if (htab->tlsld_got.refcount > 0)
-+    {
-+      htab->tlsld_got.offset = htab->sgot->size;
-+      htab->sgot->size += 8;
-+      if (bfd_link_pic (info))
-+        htab->srelgot->size += sizeof (Elf64_External_Rela);
-+    }
-+  else
-+    htab->tlsld_got.offset = (bfd_vma) -1;
-+
-+  if (elf_hash_table (info)->dynamic_sections_created)
-+    {
-+      /* Make space for the trailing nop in .plt.  */
-+      if (htab->splt->size > 0)
-+        htab->splt->size += 4;
-+    }
-+
-+  /* The check_relocs and adjust_dynamic_symbol entry points have
-+     determined the sizes of the various dynamic sections.  Allocate
-+     memory for them.  */
-+  for (s = dynobj->sections; s != NULL; s = s->next)
-+    {
-+      const char *name;
-+      bfd_boolean strip = FALSE;
-+
-+      if ((s->flags & SEC_LINKER_CREATED) == 0)
-+        continue;
-+
-+      /* It's OK to base decisions on the section name, because none
-+         of the dynobj section names depend upon the input files.  */
-+      name = bfd_section_name (s);
-+
-+      if (strncmp (name, ".rela", 5) == 0)
-+        {
-+          if (s->size == 0)
-+            {
-+              /* If we don't need this section, strip it from the
-+        	 output file.  This is to handle .rela.bss and
-+        	 .rela.plt.  We must create it in
-+        	 create_dynamic_sections, because it must be created
-+        	 before the linker maps input sections to output
-+        	 sections.  The linker does that before
-+        	 adjust_dynamic_symbol is called, and it is that
-+        	 function which decides whether anything needs to go
-+        	 into these sections.  */
-+              strip = TRUE;
-+            }
-+          else
-+            {
-+              /* We use the reloc_count field as a counter if we need
-+        	 to copy relocs into the output file.  */
-+              s->reloc_count = 0;
-+            }
-+        }
-+      else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt)
-+        {
-+          /* It's not one of our sections, so don't allocate space.  */
-+          continue;
-+        }
-+
-+      if (strip)
-+        {
-+          s->flags |= SEC_EXCLUDE;
-+          continue;
-+        }
-+
-+      /* Allocate memory for the section contents.  */
-+      /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
-+         Unused entries should be reclaimed before the section's contents
-+         are written out, but at the moment this does not happen.  Thus in
-+         order to prevent writing out garbage, we initialise the section's
-+         contents to zero.  */
-+      s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
-+      if (s->contents == NULL && s->size != 0)
-+        return FALSE;
-+    }
-+
-+  if (elf_hash_table (info)->dynamic_sections_created)
-+    {
-+      /* Add some entries to the .dynamic section.  We fill in the
-+	 values later, in microblaze_elf_finish_dynamic_sections, but we
-+	 must add the entries now so that we get the correct size for
-+	 the .dynamic section.  The DT_DEBUG entry is filled in by the
-+	 dynamic linker and used by the debugger.  */
-+#define add_dynamic_entry(TAG, VAL)			\
-+      _bfd_elf_add_dynamic_entry (info, TAG, VAL)
-+
-+      if (bfd_link_executable (info))
-+        {
-+          if (!add_dynamic_entry (DT_DEBUG, 0))
-+            return FALSE;
-+        }
-+
-+      if (!add_dynamic_entry (DT_RELA, 0)
-+          || !add_dynamic_entry (DT_RELASZ, 0)
-+          || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela)))
-+	return FALSE;
-+
-+      if (htab->splt->size != 0)
-+        {
-+          if (!add_dynamic_entry (DT_PLTGOT, 0)
-+              || !add_dynamic_entry (DT_PLTRELSZ, 0)
-+              || !add_dynamic_entry (DT_PLTREL, DT_RELA)
-+              || !add_dynamic_entry (DT_JMPREL, 0)
-+              || !add_dynamic_entry (DT_BIND_NOW, 1))
-+            return FALSE;
-+        }
-+
-+      if (info->flags & DF_TEXTREL)
-+        {
-+          if (!add_dynamic_entry (DT_TEXTREL, 0))
-+            return FALSE;
-+        }
-+    }
-+#undef add_dynamic_entry
-+  return TRUE;
-+}
-+
-+/* Finish up dynamic symbol handling.  We set the contents of various
-+   dynamic sections here.  */
-+
-+static bfd_boolean
-+microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
-+				      struct bfd_link_info *info,
-+				      struct elf_link_hash_entry *h,
-+				      Elf_Internal_Sym *sym)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (h->plt.offset != (bfd_vma) -1)
-+    {
-+      asection *splt;
-+      asection *srela;
-+      asection *sgotplt;
-+      Elf_Internal_Rela rela;
-+      bfd_byte *loc;
-+      bfd_vma plt_index;
-+      bfd_vma got_offset;
-+      bfd_vma got_addr;
-+
-+      /* This symbol has an entry in the procedure linkage table.  Set
-+         it up.  */
-+      BFD_ASSERT (h->dynindx != -1);
-+
-+      splt = htab->splt;
-+      srela = htab->srelplt;
-+      sgotplt = htab->sgotplt;
-+      BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
-+
-+      plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved.  */
-+      got_offset = (plt_index + 3) * 4; /* 3 reserved ???  */
-+      got_addr = got_offset;
-+
-+      /* For non-PIC objects we need absolute address of the GOT entry.  */
-+      if (!bfd_link_pic (info))
-+        got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset;
-+
-+      /* Fill in the entry in the procedure linkage table.  */
-+      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
-+                  splt->contents + h->plt.offset);
-+      if (bfd_link_pic (info))
-+        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
-+                    splt->contents + h->plt.offset + 4);
-+      else
-+        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
-+                    splt->contents + h->plt.offset + 4);
-+      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
-+                  splt->contents + h->plt.offset + 8);
-+      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
-+                  splt->contents + h->plt.offset + 12);
-+
-+      /* Any additions to the .got section??? */
-+      /*      bfd_put_32 (output_bfd,
-+	      splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
-+	      sgotplt->contents + got_offset); */
-+
-+      /* Fill in the entry in the .rela.plt section.  */
-+      rela.r_offset = (sgotplt->output_section->vma
-+                       + sgotplt->output_offset
-+                       + got_offset);
-+      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
-+      rela.r_addend = 0;
-+      loc = srela->contents;
-+      loc += plt_index * sizeof (Elf64_External_Rela);
-+      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
-+
-+      if (!h->def_regular)
-+        {
-+          /* Mark the symbol as undefined, rather than as defined in
-+             the .plt section.  Zero the value.  */
-+          sym->st_shndx = SHN_UNDEF;
-+          sym->st_value = 0;
-+        }
-+    }
-+
-+  /* h->got.refcount to be checked ? */
-+  if (h->got.offset != (bfd_vma) -1 &&
-+      ! ((h->got.offset & 1) ||
-+          IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
-+    {
-+      asection *sgot;
-+      asection *srela;
-+      bfd_vma offset;
-+
-+      /* This symbol has an entry in the global offset table.  Set it
-+         up.  */
-+
-+      sgot = htab->sgot;
-+      srela = htab->srelgot;
-+      BFD_ASSERT (sgot != NULL && srela != NULL);
-+
-+      offset = (sgot->output_section->vma + sgot->output_offset
-+		+ (h->got.offset &~ (bfd_vma) 1));
-+
-+      /* If this is a -Bsymbolic link, and the symbol is defined
-+         locally, we just want to emit a RELATIVE reloc.  Likewise if
-+         the symbol was forced to be local because of a version file.
-+         The entry in the global offset table will already have been
-+         initialized in the relocate_section function.  */
-+      if (bfd_link_pic (info)
-+          && ((info->symbolic && h->def_regular)
-+	      || h->dynindx == -1))
-+        {
-+          asection *sec = h->root.u.def.section;
-+          microblaze_elf_output_dynamic_relocation (output_bfd,
-+                                                    srela, srela->reloc_count++,
-+                                                    /* symindex= */ 0,
-+                                                    R_MICROBLAZE_REL, offset,
-+                                                    h->root.u.def.value
-+                                                    + sec->output_section->vma
-+                                                    + sec->output_offset);
-+        }
-+      else
-+        {
-+          microblaze_elf_output_dynamic_relocation (output_bfd,
-+                                                    srela, srela->reloc_count++,
-+                                                    h->dynindx,
-+                                                    R_MICROBLAZE_GLOB_DAT,
-+                                                    offset, 0);
-+        }
-+
-+      bfd_put_32 (output_bfd, (bfd_vma) 0,
-+                  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
-+    }
-+
-+  if (h->needs_copy)
-+    {
-+      asection *s;
-+      Elf_Internal_Rela rela;
-+      bfd_byte *loc;
-+
-+      /* This symbols needs a copy reloc.  Set it up.  */
-+
-+      BFD_ASSERT (h->dynindx != -1);
-+
-+      s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss");
-+      BFD_ASSERT (s != NULL);
-+
-+      rela.r_offset = (h->root.u.def.value
-+                       + h->root.u.def.section->output_section->vma
-+                       + h->root.u.def.section->output_offset);
-+      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
-+      rela.r_addend = 0;
-+      loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
-+      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
-+    }
-+
-+  /* Mark some specially defined symbols as absolute.  */
-+  if (h == htab->elf.hdynamic
-+      || h == htab->elf.hgot
-+      || h == htab->elf.hplt)
-+    sym->st_shndx = SHN_ABS;
-+
-+  return TRUE;
-+}
-+
-+
-+/* Finish up the dynamic sections.  */
-+
-+static bfd_boolean
-+microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-+					struct bfd_link_info *info)
-+{
-+  bfd *dynobj;
-+  asection *sdyn, *sgot;
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  dynobj = htab->elf.dynobj;
-+
-+  sdyn = bfd_get_linker_section (dynobj, ".dynamic");
-+
-+  if (htab->elf.dynamic_sections_created)
-+    {
-+      asection *splt;
-+      Elf64_External_Dyn *dyncon, *dynconend;
-+
-+      splt = bfd_get_linker_section (dynobj, ".plt");
-+      BFD_ASSERT (splt != NULL && sdyn != NULL);
-+
-+      dyncon = (Elf64_External_Dyn *) sdyn->contents;
-+      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
-+      for (; dyncon < dynconend; dyncon++)
-+        {
-+          Elf_Internal_Dyn dyn;
-+          const char *name;
-+          bfd_boolean size;
-+
-+          bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
-+
-+          switch (dyn.d_tag)
-+            {
-+            case DT_PLTGOT:   name = ".got.plt"; size = FALSE; break;
-+            case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break;
-+            case DT_JMPREL:   name = ".rela.plt"; size = FALSE; break;
-+            case DT_RELA:     name = ".rela.dyn"; size = FALSE; break;
-+            case DT_RELASZ:   name = ".rela.dyn"; size = TRUE; break;
-+            default:	  name = NULL; size = FALSE; break;
-+            }
-+
-+          if (name != NULL)
-+            {
-+              asection *s;
-+
-+              s = bfd_get_section_by_name (output_bfd, name);
-+              if (s == NULL)
-+                dyn.d_un.d_val = 0;
-+              else
-+                {
-+                  if (! size)
-+                    dyn.d_un.d_ptr = s->vma;
-+                  else
-+                    dyn.d_un.d_val = s->size;
-+                }
-+              bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
-+            }
-+        }
-+
-+      /* Clear the first entry in the procedure linkage table,
-+	 and put a nop in the last four bytes.  */
-+      if (splt->size > 0)
-+        {
-+          memset (splt->contents, 0, PLT_ENTRY_SIZE);
-+          bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
-+                      splt->contents + splt->size - 4);
-+        }
-+
-+      elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
-+    }
-+
-+  /* Set the first entry in the global offset table to the address of
-+     the dynamic section.  */
-+  sgot = bfd_get_linker_section (dynobj, ".got.plt");
-+  if (sgot && sgot->size > 0)
-+    {
-+      if (sdyn == NULL)
-+        bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
-+      else
-+        bfd_put_32 (output_bfd,
-+                    sdyn->output_section->vma + sdyn->output_offset,
-+                    sgot->contents);
-+      elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
-+    }
-+
-+  if (htab->sgot && htab->sgot->size > 0)
-+    elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4;
-+
-+  return TRUE;
-+}
-+
-+/* Hook called by the linker routine which adds symbols from an object
-+   file.  We use it to put .comm items in .sbss, and not .bss.  */
-+
-+static bfd_boolean
-+microblaze_elf_add_symbol_hook (bfd *abfd,
-+			        struct bfd_link_info *info,
-+			        Elf_Internal_Sym *sym,
-+			        const char **namep ATTRIBUTE_UNUSED,
-+			        flagword *flagsp ATTRIBUTE_UNUSED,
-+			        asection **secp,
-+			        bfd_vma *valp)
-+{
-+  if (sym->st_shndx == SHN_COMMON
-+      && !bfd_link_relocatable (info)
-+      && sym->st_size <= elf_gp_size (abfd))
-+    {
-+      /* Common symbols less than or equal to -G nn bytes are automatically
-+	 put into .sbss.  */
-+      *secp = bfd_make_section_old_way (abfd, ".sbss");
-+      if (*secp == NULL
-+          || ! bfd_set_section_flags (*secp, SEC_IS_COMMON))
-+        return FALSE;
-+
-+      *valp = sym->st_size;
-+    }
-+
-+  return TRUE;
-+}
-+
-+#define TARGET_LITTLE_SYM      microblaze_elf64_le_vec
-+#define TARGET_LITTLE_NAME     "elf64-microblazeel"
-+
-+#define TARGET_BIG_SYM          microblaze_elf64_vec
-+#define TARGET_BIG_NAME		"elf64-microblaze"
-+
-+#define ELF_ARCH		bfd_arch_microblaze
-+#define ELF_TARGET_ID		MICROBLAZE_ELF_DATA
-+#define ELF_MACHINE_CODE	EM_MICROBLAZE
-+#define ELF_MACHINE_ALT1	EM_MICROBLAZE_OLD
-+#define ELF_MAXPAGESIZE		0x1000
-+#define elf_info_to_howto	microblaze_elf_info_to_howto
-+#define elf_info_to_howto_rel	NULL
-+
-+#define bfd_elf64_bfd_reloc_type_lookup		microblaze_elf_reloc_type_lookup
-+#define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
-+#define elf_backend_relocate_section		microblaze_elf_relocate_section
-+#define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
-+#define bfd_elf64_bfd_merge_private_bfd_data    _bfd_generic_verify_endian_match
-+#define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
-+
-+#define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
-+#define elf_backend_check_relocs                microblaze_elf_check_relocs
-+#define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
-+#define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
-+#define elf_backend_can_gc_sections		1
-+#define elf_backend_can_refcount    		1
-+#define elf_backend_want_got_plt    		1
-+#define elf_backend_plt_readonly    		1
-+#define elf_backend_got_header_size 		12
-+#define elf_backend_rela_normal     		1
-+
-+#define elf_backend_adjust_dynamic_symbol       microblaze_elf_adjust_dynamic_symbol
-+#define elf_backend_create_dynamic_sections     microblaze_elf_create_dynamic_sections
-+#define elf_backend_finish_dynamic_sections     microblaze_elf_finish_dynamic_sections
-+#define elf_backend_finish_dynamic_symbol       microblaze_elf_finish_dynamic_symbol
-+#define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
-+#define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
-+
-+#include "elf64-target.h"
-diff --git a/bfd/targets.c b/bfd/targets.c
-index 0732c5e4292..1ec226b2f47 100644
---- a/bfd/targets.c
-+++ b/bfd/targets.c
-@@ -782,6 +782,8 @@ extern const bfd_target mep_elf32_le_vec;
- extern const bfd_target metag_elf32_vec;
- extern const bfd_target microblaze_elf32_vec;
- extern const bfd_target microblaze_elf32_le_vec;
-+extern const bfd_target microblaze_elf64_vec;
-+extern const bfd_target microblaze_elf64_le_vec;
- extern const bfd_target mips_ecoff_be_vec;
- extern const bfd_target mips_ecoff_le_vec;
- extern const bfd_target mips_ecoff_bele_vec;
-@@ -1150,6 +1152,10 @@ static const bfd_target * const _bfd_target_vector[] =
- 
- 	&metag_elf32_vec,
- 
-+#ifdef BFD64
-+	&microblaze_elf64_vec,
-+	&microblaze_elf64_le_vec,
-+#endif
- 	&microblaze_elf32_vec,
- 
- 	&mips_ecoff_be_vec,
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 5810a74a5fc..ffbb843d33e 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -35,10 +35,13 @@
- #define streq(a,b) (strcmp (a, b) == 0)
- #endif
- 
-+static int microblaze_arch_size = 0;
-+
- #define OPTION_EB (OPTION_MD_BASE + 0)
- #define OPTION_EL (OPTION_MD_BASE + 1)
- #define OPTION_LITTLE (OPTION_MD_BASE + 2)
- #define OPTION_BIG (OPTION_MD_BASE + 3)
-+#define OPTION_M64 (OPTION_MD_BASE + 4)
- 
- void microblaze_generate_symbol (char *sym);
- static bfd_boolean check_spl_reg (unsigned *);
-@@ -773,6 +776,74 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
-   return new_pointer;
- }
- 
-+ static char *
-+parse_imml (char * s, expressionS * e, long min, long max)
-+{
-+  char *new_pointer;
-+  char *atp;
-+  int itype, ilen;
-+
-+  ilen = 0;
-+
-+  /* Find the start of "@GOT" or "@PLT" suffix (if any) */
-+  for (atp = s; *atp != '@'; atp++)
-+    if (is_end_of_line[(unsigned char) *atp])
-+      break;
-+
-+  if (*atp == '@')
-+    {
-+      itype = match_imm (atp + 1, &ilen);
-+      if (itype != 0)
-+        {
-+          *atp = 0;
-+          e->X_md = itype;
-+        }
-+      else
-+        {
-+          atp = NULL;
-+          e->X_md = 0;
-+          ilen = 0;
-+        }
-+      *atp = 0;
-+    }
-+  else
-+    {
-+      atp = NULL;
-+      e->X_md = 0;
-+    }
-+
-+  if (atp && !GOT_symbol)
-+    {
-+      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
-+    }
-+
-+  new_pointer = parse_exp (s, e);
-+
-+  if (!GOT_symbol && ! strncmp (s, GOT_SYMBOL_NAME, 20))
-+    {
-+      GOT_symbol = symbol_find_or_make (GOT_SYMBOL_NAME);
-+    }
-+
-+  if (e->X_op == O_absent)
-+    ; /* An error message has already been emitted.  */
-+  else if ((e->X_op != O_constant && e->X_op != O_symbol) )
-+    as_fatal (_("operand must be a constant or a label"));
-+  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
-+				       || (long) e->X_add_number > max))
-+    {
-+      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
-+                min, max, (long) e->X_add_number);
-+    }
-+
-+  if (atp)
-+    {
-+      *atp = '@'; /* restore back (needed?)  */
-+      if (new_pointer >= atp)
-+        new_pointer += ilen + 1; /* sizeof (imm_suffix) + 1 for '@' */
-+    }
-+  return new_pointer;
-+}
-+
- static char *
- check_got (int * got_type, int * got_len)
- {
-@@ -920,6 +991,7 @@ md_assemble (char * str)
-   unsigned int immed, immed2, temp;
-   expressionS exp;
-   char name[20];
-+  long immedl;
- 
-   /* Drop leading whitespace.  */
-   while (ISSPACE (* str))
-@@ -1129,7 +1201,7 @@ md_assemble (char * str)
- 	}
-       break;
- 
--    case INST_TYPE_RD_R1_IMM5:
-+    case INST_TYPE_RD_R1_IMMS:
-       if (strcmp (op_end, ""))
-         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
-       else
-@@ -1163,16 +1235,22 @@ md_assemble (char * str)
-           immed = exp.X_add_number;
-         }
- 
--      if (immed != (immed % 32))
-+      if ((immed != (immed % 32)) &&
-+          (opcode->instr == bslli || opcode->instr == bsrai || opcode->instr == bsrli))
- 	{
-           as_warn (_("Shift value > 32. using <value %% 32>"));
-           immed = immed % 32;
-         }
-+      else if (immed != (immed % 64))
-+	{
-+          as_warn (_("Shift value > 64. using <value %% 64>"));
-+          immed = immed % 64;
-+        }
-       inst |= (reg1 << RD_LOW) & RD_MASK;
-       inst |= (reg2 << RA_LOW) & RA_MASK;
--      inst |= (immed << IMM_LOW) & IMM5_MASK;
-+      inst |= (immed << IMM_LOW) & IMM6_MASK;
-       break;
-- case INST_TYPE_RD_R1_IMM5_IMM5:
-+ case INST_TYPE_RD_R1_IMMW_IMMS:
-       if (strcmp (op_end, ""))
-         op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
-       else
-@@ -1196,7 +1274,7 @@ md_assemble (char * str)
- 
-       /* Width immediate value.  */
-       if (strcmp (op_end, ""))
--        op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
-+        op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
-       else
-         as_fatal (_("Error in statement syntax"));
-       if (exp.X_op != O_constant)
-@@ -1208,6 +1286,8 @@ md_assemble (char * str)
-         immed = exp.X_add_number;
-       if (opcode->instr == bsefi && immed > 31)
-         as_fatal (_("Width value must be less than 32"));
-+      else if (opcode->instr == bslefi && immed > 63)
-+        as_fatal (_("Width value must be less than 64"));
- 
-       /* Shift immediate value.  */
-       if (strcmp (op_end, ""))
-@@ -1215,32 +1295,40 @@ md_assemble (char * str)
-       else
-         as_fatal (_("Error in statement syntax"));
-       if (exp.X_op != O_constant)
--	    {
-+       {
-           as_warn (_("Symbol used as immediate shift value for bit field instruction"));
-           immed2 = 0;
-         }
-       else
--	    {
-+        {
-           output = frag_more (isize);
-           immed2 = exp.X_add_number;
--	    }
--      if (immed2 != (immed2 % 32))
--	    {
--          as_warn (_("Shift value greater than 32. using <value %% 32>"));
-+	}
-+      if ((immed2 != (immed2 % 32)) && (opcode->instr == bsefi || opcode->instr == bsifi))
-+	{
-+          
-+	  as_warn (_("Shift value greater than 32. using <value %% 32>"));
-           immed2 = immed2 % 32;
-         }
-+      else if (immed2 != (immed2 % 64))
-+	{
-+          as_warn (_("Shift value greater than 64. using <value %% 64>"));
-+          immed2 = immed2 % 64;
-+        }
- 
-       /* Check combined value.  */
--      if (immed + immed2 > 32)
-+      if ((immed + immed2 > 32) && (opcode->instr == bsefi || opcode->instr == bsifi))
-         as_fatal (_("Width value + shift value must not be greater than 32"));
- 
-+      else if (immed + immed2 > 64)
-+        as_fatal (_("Width value + shift value must not be greater than 64"));
-       inst |= (reg1 << RD_LOW) & RD_MASK;
-       inst |= (reg2 << RA_LOW) & RA_MASK;
--      if (opcode->instr == bsefi)
--        inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
-+      if (opcode->instr == bsefi || opcode->instr == bslefi)
-+        inst |= (immed & IMM6_MASK) << IMM_WIDTH_LOW; /* bsefi or bslefi */
-       else
--        inst |= ((immed + immed2 - 1) & IMM5_MASK) << IMM_WIDTH_LOW; /* bsifi */
--      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
-+        inst |= ((immed + immed2 - 1) & IMM6_MASK) << IMM_WIDTH_LOW; /* bsifi or bslifi */
-+      inst |= (immed2 << IMM_LOW) & IMM6_MASK;
-       break;
-     case INST_TYPE_R1_R2:
-       if (strcmp (op_end, ""))
-@@ -1808,6 +1896,142 @@ md_assemble (char * str)
-       }
-       inst |= (immed << IMM_MBAR);
-       break;
-+    /* For 64-bit instructions */
-+    case INST_TYPE_RD_R1_IMML:
-+      if (strcmp (op_end, ""))
-+	op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
-+      else
-+ 	{
-+          as_fatal (_("Error in statement syntax"));
-+          reg1 = 0;
-+        }
-+      if (strcmp (op_end, ""))
-+	op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
-+      else
-+	{
-+          as_fatal (_("Error in statement syntax"));
-+          reg2 = 0;
-+        }
-+      if (strcmp (op_end, ""))
-+	op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-+      else
-+	as_fatal (_("Error in statement syntax"));
-+
-+      /* Check for spl registers.  */
-+      if (check_spl_reg (& reg1))
-+	as_fatal (_("Cannot use special register with this instruction"));
-+      if (check_spl_reg (& reg2))
-+	as_fatal (_("Cannot use special register with this instruction"));
-+
-+      if (exp.X_op != O_constant)
-+	{
-+	  char *opc = NULL;
-+	  relax_substateT subtype;
-+
-+	  if (exp.X_md != 0)
-+	    subtype = get_imm_otype(exp.X_md);
-+	  else
-+	    subtype = opcode->inst_offset_type;
-+
-+	  output = frag_var (rs_machine_dependent,
-+			     isize * 2, /* maxm of 2 words.  */
-+			     isize * 2, /* minm of 2 words.  */
-+			     subtype,   /* PC-relative or not.  */
-+			     exp.X_add_symbol,
-+			     exp.X_add_number,
-+			     opc);
-+	  immedl = 0L;
-+        }
-+      else
-+	{
-+	  output = frag_more (isize);
-+	  immedl = exp.X_add_number;
-+
-+	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+	  if (opcode1 == NULL)
-+	    {
-+	      as_bad (_("unknown opcode \"%s\""), "imml");
-+	      return;
-+	    }
-+
-+	  inst1 = opcode1->bit_sequence;
-+	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+	  output[0] = INST_BYTE0 (inst1);
-+	  output[1] = INST_BYTE1 (inst1);
-+	  output[2] = INST_BYTE2 (inst1);
-+	  output[3] = INST_BYTE3 (inst1);
-+	  output = frag_more (isize);
-+        }
-+
-+      inst |= (reg1 << RD_LOW) & RD_MASK;
-+      inst |= (reg2 << RA_LOW) & RA_MASK;
-+      inst |= (immedl << IMM_LOW) & IMM_MASK;
-+      break;
-+
-+    case INST_TYPE_R1_IMML:
-+      if (strcmp (op_end, ""))
-+        op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
-+      else
-+	{
-+          as_fatal (_("Error in statement syntax"));
-+          reg1 = 0;
-+        }
-+      if (strcmp (op_end, ""))
-+        op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+      else
-+        as_fatal (_("Error in statement syntax"));
-+
-+      /* Check for spl registers.  */
-+      if (check_spl_reg (&reg1))
-+        as_fatal (_("Cannot use special register with this instruction"));
-+
-+      if (exp.X_op != O_constant)
-+	{
-+          char *opc = NULL;
-+          relax_substateT subtype;
-+
-+	  if (exp.X_md != 0)
-+	    subtype = get_imm_otype(exp.X_md);
-+	  else
-+	    subtype = opcode->inst_offset_type;
-+
-+	  output = frag_var (rs_machine_dependent,
-+			     isize * 2, /* maxm of 2 words.  */
-+			     isize * 2, /* minm of 2 words.  */
-+			     subtype,   /* PC-relative or not.  */
-+			     exp.X_add_symbol,
-+			     exp.X_add_number,
-+			     opc);
-+	  immedl = 0L;
-+	}
-+      else
-+	{
-+          output = frag_more (isize);
-+          immedl = exp.X_add_number;
-+
-+	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+	  if (opcode1 == NULL)
-+	    {
-+	      as_bad (_("unknown opcode \"%s\""), "imml");
-+	      return;
-+	    }
-+
-+          inst1 = opcode1->bit_sequence;
-+	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-+        }
-+
-+      inst |= (reg1 << RA_LOW) & RA_MASK;
-+      inst |= (immedl << IMM_LOW) & IMM_MASK;
-+      break;
-+
-+    case INST_TYPE_IMML:
-+      as_fatal (_("An IMML instruction should not be present in the .s file"));
-+      break;
- 
-     default:
-       as_fatal (_("unimplemented opcode \"%s\""), name);
-@@ -1915,6 +2139,7 @@ struct option md_longopts[] =
-   {"EL", no_argument, NULL, OPTION_EL},
-   {"mlittle-endian", no_argument, NULL, OPTION_LITTLE},
-   {"mbig-endian", no_argument, NULL, OPTION_BIG},
-+  {"m64", no_argument, NULL, OPTION_M64},
-   { NULL,          no_argument, NULL, 0}
- };
- 
-@@ -2565,6 +2790,18 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
-   return rel;
- }
- 
-+/* Called by TARGET_FORMAT.  */
-+const char *
-+microblaze_target_format (void)
-+{
-+
-+  if (microblaze_arch_size == 64)
-+    return "elf64-microblazeel";
-+  else 
-+      return target_big_endian ? "elf32-microblaze" : "elf32-microblazeel";
-+}
-+
-+
- int
- md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
- {
-@@ -2578,6 +2815,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
-     case OPTION_LITTLE:
-       target_big_endian = 0;
-       break;
-+    case OPTION_M64:
-+      //if (arg != NULL && strcmp (arg, "64") == 0)
-+      microblaze_arch_size = 64;
-+      break;
-     default:
-       return 0;
-     }
-@@ -2593,6 +2834,7 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
-   fprintf (stream, _(" MicroBlaze specific assembler options:\n"));
-   fprintf (stream, "  -%-23s%s\n", "mbig-endian", N_("assemble for a big endian cpu"));
-   fprintf (stream, "  -%-23s%s\n", "mlittle-endian", N_("assemble for a little endian cpu"));
-+  fprintf (stream, "  -%-23s%s\n", "m64", N_("generate 64-bit elf"));
- }
- 
- 
-diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
-index 01cb3e894f7..7435a70ef5e 100644
---- a/gas/config/tc-microblaze.h
-+++ b/gas/config/tc-microblaze.h
-@@ -78,7 +78,9 @@ extern const struct relax_type md_relax_table[];
- 
- #ifdef OBJ_ELF
- 
--#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
-+#define TARGET_FORMAT microblaze_target_format()
-+extern const char *microblaze_target_format (void);
-+//#define TARGET_FORMAT (target_big_endian ? "elf32-microblaze" : "elf32-microblazeel")
- 
- #define ELF_TC_SPECIAL_SECTIONS \
-   { ".sdata",		SHT_PROGBITS,	SHF_ALLOC + SHF_WRITE }, \
-diff --git a/include/elf/common.h b/include/elf/common.h
-index 4d94c4fd5b3..f709a01816c 100644
---- a/include/elf/common.h
-+++ b/include/elf/common.h
-@@ -340,6 +340,7 @@
- #define EM_RISCV 	243 	/* RISC-V */
- #define EM_LANAI	244	/* Lanai 32-bit processor.  */
- #define EM_BPF		247	/* Linux BPF – in-kernel virtual machine.  */
-+#define EM_MB_64	248	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
- #define EM_NFP		250	/* Netronome Flow Processor.  */
- #define EM_CSKY		252	/* C-SKY processor family.  */
- 
-diff --git a/ld/Makefile.am b/ld/Makefile.am
-index 02c4fc16395..d063e2d32c5 100644
---- a/ld/Makefile.am
-+++ b/ld/Makefile.am
-@@ -416,6 +416,8 @@ ALL_64_EMULATION_SOURCES = \
- 	eelf32ltsmipn32.c \
- 	eelf32ltsmipn32_fbsd.c \
- 	eelf32mipswindiss.c \
-+	eelf64microblazeel.c \
-+	eelf64microblaze.c \
- 	eelf64_aix.c \
- 	eelf64bpf.c \
- 	eelf64_ia64.c \
-@@ -898,6 +900,8 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Pc@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
-diff --git a/ld/Makefile.in b/ld/Makefile.in
-index 2fe12e14f63..01ebb051faa 100644
---- a/ld/Makefile.in
-+++ b/ld/Makefile.in
-@@ -515,6 +515,7 @@ pdfdir = @pdfdir@
- prefix = @prefix@
- program_transform_name = @program_transform_name@
- psdir = @psdir@
-+runstatedir = @runstatedir@
- sbindir = @sbindir@
- sharedstatedir = @sharedstatedir@
- srcdir = @srcdir@
-@@ -898,6 +899,8 @@ ALL_64_EMULATION_SOURCES = \
- 	eelf32ltsmipn32.c \
- 	eelf32ltsmipn32_fbsd.c \
- 	eelf32mipswindiss.c \
-+	eelf64microblazeel.c \
-+	eelf64microblaze.c \
- 	eelf64_aix.c \
- 	eelf64bpf.c \
- 	eelf64_ia64.c \
-@@ -1360,6 +1363,8 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64lriscv_lp64f.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ltsmip_fbsd.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Po@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64mmix.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc.Po@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64ppc_fbsd.Po@am__quote@
-@@ -2493,6 +2498,8 @@ $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): $(GEN_DEPENDS)
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Pc@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblazeel.Pc@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64microblaze.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_aix.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64bpf.Pc@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf64_ia64.Pc@am__quote@
-diff --git a/ld/configure.tgt b/ld/configure.tgt
-index 87c7d9a4cad..801d27c9e3f 100644
---- a/ld/configure.tgt
-+++ b/ld/configure.tgt
-@@ -469,6 +469,9 @@ microblaze*-linux*)	targ_emul="elf32mb_linux"
- microblazeel*)		targ_emul=elf32microblazeel
- 			targ_extra_emuls=elf32microblaze
- 			;;
-+microblazeel64*)	targ_emul=elf64microblazeel
-+			targ_extra_emuls=elf64microblaze
-+			;;
- microblaze*)		targ_emul=elf32microblaze
- 			targ_extra_emuls=elf32microblazeel
- 			;;
-diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
-new file mode 100644
-index 00000000000..7b4c7c411bd
---- /dev/null
-+++ b/ld/emulparams/elf64microblaze.sh
-@@ -0,0 +1,23 @@
-+SCRIPT_NAME=elfmicroblaze
-+OUTPUT_FORMAT="elf64-microblazeel"
-+#BIG_OUTPUT_FORMAT="elf64-microblaze"
-+LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
-+#TEXT_START_ADDR=0
-+NONPAGED_TEXT_START_ADDR=0x28
-+ALIGNMENT=4
-+MAXPAGESIZE=4
-+ARCH=microblaze
-+EMBEDDED=yes
-+
-+NOP=0x80000000
-+
-+# Hmmm, there's got to be a better way.  This sets the stack to the
-+# top of the simulator memory (2^19 bytes).
-+#PAGE_SIZE=0x1000
-+#DATA_ADDR=0x10000
-+#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
-+#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
-+#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
-+
-+TEMPLATE_NAME=elf
-+#GENERATE_SHLIB_SCRIPT=yes
-diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
-new file mode 100644
-index 00000000000..7b4c7c411bd
---- /dev/null
-+++ b/ld/emulparams/elf64microblazeel.sh
-@@ -0,0 +1,23 @@
-+SCRIPT_NAME=elfmicroblaze
-+OUTPUT_FORMAT="elf64-microblazeel"
-+#BIG_OUTPUT_FORMAT="elf64-microblaze"
-+LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
-+#TEXT_START_ADDR=0
-+NONPAGED_TEXT_START_ADDR=0x28
-+ALIGNMENT=4
-+MAXPAGESIZE=4
-+ARCH=microblaze
-+EMBEDDED=yes
-+
-+NOP=0x80000000
-+
-+# Hmmm, there's got to be a better way.  This sets the stack to the
-+# top of the simulator memory (2^19 bytes).
-+#PAGE_SIZE=0x1000
-+#DATA_ADDR=0x10000
-+#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
-+#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
-+#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
-+
-+TEMPLATE_NAME=elf
-+#GENERATE_SHLIB_SCRIPT=yes
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 52c9068805f..a03f5b7a55b 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -33,6 +33,7 @@
- #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
- #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
- #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
-+#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
- #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
- 
- #define NUM_STRBUFS 3
-@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
- }
- 
- static char *
--get_field_imm5 (struct string_buf *buf, long instr)
-+get_field_imml (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
--  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
-+  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
-+  return p;
-+}
-+
-+static char *
-+get_field_imms (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
-   return p;
- }
- 
-@@ -91,14 +101,14 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
- }
- 
- static char *
--get_field_imm5width (struct string_buf *buf, long instr)
-+get_field_immw (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
-   if (instr & 0x00004000)
--    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-  else
--    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
-   return p;
- }
- 
-@@ -308,9 +318,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 		}
- 	    }
- 	  break;
--	case INST_TYPE_RD_R1_IMM5:
-+	case INST_TYPE_RD_R1_IMML:
- 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
--		      get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
-+		   get_field_r1(&buf, inst), get_field_imm (&buf, inst));
-+          /* TODO: Also print symbol */
-+          break;
-+	case INST_TYPE_RD_R1_IMMS:
-+	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
-+	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
- 	  break;
- 	case INST_TYPE_RD_RFSL:
- 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
-@@ -414,9 +429,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 		}
- 	    }
- 	  break;
--	case INST_TYPE_RD_R2:
--	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
--		      get_field_r2 (&buf, inst));
-+        case INST_TYPE_IMML:
-+	  print_func (stream, "\t%s", get_field_imml (&buf, inst));
-+          /* TODO: Also print symbol */
-+	  break;
-+        case INST_TYPE_RD_R2:
-+	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
- 	  break;
- 	case INST_TYPE_R2:
- 	  print_func (stream, "\t%s", get_field_r2 (&buf, inst));
-@@ -441,8 +459,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  break;
- 	  /* For tuqula instruction */
-         /* For bit field insns.  */
--	case INST_TYPE_RD_R1_IMM5_IMM5:
--	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
-+	case INST_TYPE_RD_R1_IMMW_IMMS:
-+	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
-+		   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
- 	  break;
- 	/* For tuqula instruction */
- 	case INST_TYPE_RD:
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index f61f4ef66d9..61eaa39b3eb 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -40,7 +40,7 @@
- #define INST_TYPE_RD_SPECIAL 11
- #define INST_TYPE_R1 12
- /* New instn type for barrel shift imms.  */
--#define INST_TYPE_RD_R1_IMM5  13
-+#define INST_TYPE_RD_R1_IMMS  13
- #define INST_TYPE_RD_RFSL    14
- #define INST_TYPE_R1_RFSL    15
- 
-@@ -60,7 +60,13 @@
- #define INST_TYPE_IMM5 20
- 
- /* For bsefi and bsifi */
--#define INST_TYPE_RD_R1_IMM5_IMM5  21
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
-+
-+/* For 64-bit instructions */
-+#define INST_TYPE_IMML 22
-+#define INST_TYPE_RD_R1_IMML 23
-+#define INST_TYPE_R1_IMML 24
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
- 
- #define INST_TYPE_NONE 25
- 
-@@ -91,13 +97,14 @@
- #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
- #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
--#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
--#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
-+#define OPCODE_MASK_H3  0xFC000700  /* High 6 bits and bits 21, 22, 23.  */
-+#define OPCODE_MASK_H3B 0xFC00E600  /* High 6 bits and bits 16, 17, 18, 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
--#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
-+#define OPCODE_MASK_H32B 0xFC00E000  /* High 6 bits and bit 16, 17, 18.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
- #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
-+#define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
- 
- /* New Mask for msrset, msrclr insns.  */
- #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
-@@ -107,7 +114,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 301
-+#define MAX_OPCODES 412
- 
- struct op_code_struct
- {
-@@ -125,6 +132,7 @@ struct op_code_struct
-   /* More info about output format here.  */
- } opcodes[MAX_OPCODES] =
- {
-+  /* 32-bit instructions */
-   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
-   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
-   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
-@@ -161,11 +169,11 @@ struct op_code_struct
-   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
-   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
-   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
--  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
--  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
--  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
--  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
--  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-+  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
-+  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
-+  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
-+  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
-   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
-   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -425,6 +433,129 @@ struct op_code_struct
-   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
-   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
-   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
-+
-+  /* 64-bit instructions */
-+  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
-+  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
-+  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
-+  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
-+  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
-+  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
-+  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
-+  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
-+  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
-+  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
-+  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
-+  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
-+  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
-+  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
-+  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
-+  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
-+  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
-+  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
-+  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
-+  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
-+  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
-+  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
-+  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
-+  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
-+  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
-+  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
-+  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
-+  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
-+  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
-+  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
-+  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
-+  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
-+  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
-+  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
-+  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
-+  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
-+  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
-+  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
-+  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
-+  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
-+  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
-+  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
-+  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
-+  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
-+  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
-+  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
-+  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
-+  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
-+  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
-+  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
-+  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
-+  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
-+  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
-+  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
-+  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
-+  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
-+  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
-+  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
-+  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
-+  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
-+  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
-+  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
-+  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
-+  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
-+  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
-+  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
-+  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
-+  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
-+  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
-+  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
-+  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
-+  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
-+  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
-+  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
-+  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
-+  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
-+  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
-+  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
-+  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
-+  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
-+  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
-+  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
-+  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
-+  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
-+  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
-+  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
-+  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
-+  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
-+  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
-+  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
-+  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
-+  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
-+  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
-+  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-+  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
-+  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
-+  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
-+  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
-+  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
-+  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
-+  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
-+  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
-+  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
-+  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
-+  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
-+  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
-+  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
-+  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
-+  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
-+
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
- };
- 
-@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5  ((int) 0x00000000)
- #define MAX_IMM5  ((int) 0x0000001f)
- 
-+#define MIN_IMM6  ((int) 0x00000000)
-+#define MAX_IMM6  ((int) 0x0000003f)
-+
- #define MIN_IMM_WIDTH  ((int) 0x00000001)
- #define MAX_IMM_WIDTH  ((int) 0x00000020)
- 
-+#define MIN_IMM6_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM6_WIDTH  ((int) 0x00000040)
-+
-+#define MIN_IMML  ((long) 0xffffff8000000000L)
-+#define MAX_IMML  ((long) 0x0000007fffffffffL)
-+
- #endif /* MICROBLAZE_OPC */
- 
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index fa921c90c98..1dcd3dca3d1 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -25,6 +25,7 @@
- 
- enum microblaze_instr
- {
-+  /* 32-bit instructions */
-   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
-   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
-   mulh, mulhu, mulhsu,swapb,swaph,
-@@ -58,6 +59,18 @@ enum microblaze_instr
-   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
-   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
-   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
-+
-+  /* 64-bit instructions */
-+  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
-+  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
-+  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
-+  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
-+  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
-+  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
-+  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
-+  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
-+  dcmp_un, dbl, dlong, dsqrt,
-   invalid_inst
- };
- 
-@@ -135,15 +148,18 @@ enum microblaze_instr_type
- #define RA_MASK 0x001F0000
- #define RB_MASK 0x0000F800
- #define IMM_MASK 0x0000FFFF
-+#define IMML_MASK 0x00FFFFFF
- 
--/* Imm mask for barrel shifts.  */
-+/* Imm masks for barrel shifts.  */
- #define IMM5_MASK 0x0000001F
-+#define IMM6_MASK 0x0000003F
- 
- /* Imm mask for mbar.  */
- #define IMM5_MBAR_MASK 0x03E00000
- 
--/* Imm mask for extract/insert width. */
-+/* Imm masks for extract/insert width. */
- #define IMM5_WIDTH_MASK 0x000007C0
-+#define IMM6_WIDTH_MASK 0x00000FC0
- 
- /* FSL imm mask for get, put instructions.  */
- #define  RFSL_MASK 0x000000F
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-MB-X-initial-commit.patch
deleted file mode 100644
index 06a8f70a03..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-MB-X-initial-commit.patch
+++ /dev/null
@@ -1,635 +0,0 @@
-From 49a85544705ec3057f0a1f32807b7b986127cec1 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sun, 30 Sep 2018 16:31:26 +0530
-Subject: [PATCH 16/40] MB-X initial commit code cleanup is needed.
-
----
- bfd/bfd-in2.h              |  10 +++
- bfd/elf32-microblaze.c     |  63 +++++++++++++++++-
- bfd/elf64-microblaze.c     |  59 +++++++++++++++++
- bfd/libbfd.h               |   2 +
- bfd/reloc.c                |  12 ++++
- gas/config/tc-microblaze.c | 127 +++++++++++++++++++++++++++----------
- include/elf/microblaze.h   |   2 +
- opcodes/microblaze-opc.h   |   4 +-
- opcodes/microblaze-opcm.h  |   4 +-
- 9 files changed, 243 insertions(+), 40 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 3fdbf8ed755..c55092c9ec7 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5438,11 +5438,21 @@ value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64_NONE,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imml instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_64,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- PC-relative GOT offset  */
-   BFD_RELOC_MICROBLAZE_64_GOTPC,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imml instruction).  The relocation is
-+PC-relative GOT offset  */
-+  BFD_RELOC_MICROBLAZE_64_GPC,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- GOT offset  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cf4a7fdba33..e1a66f57e79 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  TRUE),		/* PC relative offset?  */
- 
-+   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_IMML_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,	/* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  TRUE),		/* PC relative offset?  */
- 
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit GOT relocation.  Table-entry not really used.  */
-    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64:
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+      microblaze_reloc = R_MICROBLAZE_GPC_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-       microblaze_reloc = R_MICROBLAZE_GOT_64;
-       break;
-@@ -1929,6 +1964,28 @@ microblaze_elf_relax_section (bfd *abfd,
- 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
- 		}
- 	      break;
-+	    case R_MICROBLAZE_IMML_64:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
- 	    case R_MICROBLAZE_NONE:
- 	    case R_MICROBLAZE_32_NONE:
- 	      {
-@@ -2034,9 +2091,9 @@ microblaze_elf_relax_section (bfd *abfd,
-                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-                                                      irelscan->r_addend);
-               }
--	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
--		{
--		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+             if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
-+               {
-+	          isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
- 
- 		  /* Look at the reloc only if the value has been resolved.  */
- 		  if (isym->st_shndx == shndx
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index fa4b95e47e0..d55700fc513 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0x0000ffff,		/* Dest Mask.  */
-           TRUE), 		/* PC relative offset?  */
- 
-+   /* A 64 bit relocation.  Table entry not really used.  */
-+   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          64,			/* Bitsize.  */
-+          TRUE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_IMML_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-           0,			/* Rightshift.  */
-@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0x0000ffff,		/* Dest Mask.  */
-           TRUE), 		/* PC relative offset?  */
- 
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit GOT relocation.  Table-entry not really used.  */
-    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
-           0,			/* Rightshift.  */
-@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64:
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+      microblaze_reloc = R_MICROBLAZE_GPC_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-       microblaze_reloc = R_MICROBLAZE_GOT_64;
-       break;
-@@ -1162,6 +1198,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 	      break; /* Do nothing.  */
- 
- 	    case (int) R_MICROBLAZE_GOTPC_64:
-+	    case (int) R_MICROBLAZE_GPC_64:
- 	      relocation = htab->sgotplt->output_section->vma
- 		+ htab->sgotplt->output_offset;
- 	      relocation -= (input_section->output_section->vma
-@@ -1863,6 +1900,28 @@ microblaze_elf_relax_section (bfd *abfd,
- 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
- 	        }
- 	      break;
-+	    case R_MICROBLAZE_IMML_64:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
- 	    case R_MICROBLAZE_NONE:
- 	    case R_MICROBLAZE_32_NONE:
- 	      {
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index c1551b92405..b4aace6a70d 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2969,7 +2969,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-   "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
-+  "BFD_RELOC_MICROBLAZE_64",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
-+  "BFD_RELOC_MICROBLAZE_64_GPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-   "BFD_RELOC_MICROBLAZE_64_PLT",
-   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 9b39b419415..0e8a24e9cb0 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6866,12 +6866,24 @@ ENUMDOC
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
-+ENUMDOC
-+  This is a 32 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imml instruction).  No relocation is
-+  done here - only used for relaxing
-+ENUM
-+  BFD_RELOC_MICROBLAZE_64
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  No relocation is
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_GOTPC
-+ENUMDOC
-+  This is a 64 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imml instruction).  No relocation is
-+  done here - only used for relaxing
-+ENUM
-+  BFD_RELOC_MICROBLAZE_64_GPC
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  The relocation is
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index ffbb843d33e..b8250e4cded 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -94,6 +94,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
- #define TLSTPREL_OFFSET      16
- #define TEXT_OFFSET	     17
- #define TEXT_PC_OFFSET       18
-+#define DEFINED_64_OFFSET   19
- 
- /* Initialize the relax table.  */
- const relax_typeS md_relax_table[] =
-@@ -116,7 +117,8 @@ const relax_typeS md_relax_table[] =
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 15: TLSGOTTPREL_OFFSET.  */
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 16: TLSTPREL_OFFSET.  */
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
--  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 18: TEXT_PC_OFFSET.  */
-+  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 18: TEXT_PC_OFFSET.  */
-+  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }   /* 19: DEFINED_64_OFFSET.  */
- };
- 
- static struct hash_control * opcode_hash_control;	/* Opcode mnemonics.  */
-@@ -396,7 +398,8 @@ const pseudo_typeS md_pseudo_table[] =
-   {"data32", cons, 4},     /* Same as word.  */
-   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
-   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
--  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
-+  {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
-+  {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
-   {"weakext", microblaze_s_weakext, 0},
-   {"rodata", microblaze_s_rdata, 0},
-   {"sdata2", microblaze_s_rdata, 1},
-@@ -405,6 +408,7 @@ const pseudo_typeS md_pseudo_table[] =
-   {"sbss", microblaze_s_bss, 1},
-   {"text", microblaze_s_text, 0},
-   {"word", cons, 4},
-+  {"dword", cons, 8},
-   {"frame", s_ignore, 0},
-   {"mask", s_ignore, 0}, /* Emitted by gcc.  */
-   {NULL, NULL, 0}
-@@ -898,7 +902,7 @@ check_got (int * got_type, int * got_len)
- extern bfd_reloc_code_real_type
- parse_cons_expression_microblaze (expressionS *exp, int size)
- {
--  if (size == 4)
-+  if (size == 4 || (microblaze_arch_size == 64 && size == 8))
-     {
-       /* Handle @GOTOFF et.al.  */
-       char *save, *gotfree_copy;
-@@ -930,6 +934,7 @@ parse_cons_expression_microblaze (expressionS *exp, int size)
- 
- static const char * str_microblaze_ro_anchor = "RO";
- static const char * str_microblaze_rw_anchor = "RW";
-+static const char * str_microblaze_64 = "64";
- 
- static bfd_boolean
- check_spl_reg (unsigned * reg)
-@@ -1926,6 +1931,7 @@ md_assemble (char * str)
-       if (exp.X_op != O_constant)
- 	{
- 	  char *opc = NULL;
-+	  //char *opc = str_microblaze_64;
- 	  relax_substateT subtype;
- 
- 	  if (exp.X_md != 0)
-@@ -1939,7 +1945,7 @@ md_assemble (char * str)
- 			     subtype,   /* PC-relative or not.  */
- 			     exp.X_add_symbol,
- 			     exp.X_add_number,
--			     opc);
-+			     (char *) opc);
- 	  immedl = 0L;
-         }
-       else
-@@ -1977,7 +1983,7 @@ md_assemble (char * str)
-           reg1 = 0;
-         }
-       if (strcmp (op_end, ""))
--        op_end = parse_imml (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-       else
-         as_fatal (_("Error in statement syntax"));
- 
-@@ -1987,7 +1993,8 @@ md_assemble (char * str)
- 
-       if (exp.X_op != O_constant)
- 	{
--          char *opc = NULL;
-+	  //char *opc = NULL;
-+          char *opc = strdup(str_microblaze_64);
-           relax_substateT subtype;
- 
- 	  if (exp.X_md != 0)
-@@ -2001,14 +2008,13 @@ md_assemble (char * str)
- 			     subtype,   /* PC-relative or not.  */
- 			     exp.X_add_symbol,
- 			     exp.X_add_number,
--			     opc);
-+			     (char *) opc);
- 	  immedl = 0L;
- 	}
-       else
- 	{
-           output = frag_more (isize);
-           immedl = exp.X_add_number;
--
- 	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
- 	  if (opcode1 == NULL)
- 	    {
-@@ -2184,13 +2190,23 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
-       fragP->fr_fix += INST_WORD_SIZE * 2;
-       fragP->fr_var = 0;
-       break;
-+    case DEFINED_64_OFFSET:
-+      if (fragP->fr_symbol == GOT_symbol)
-+        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
-+	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC);
-+      else
-+        fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
-+	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64);
-+      fragP->fr_fix += INST_WORD_SIZE * 2;
-+      fragP->fr_var = 0;
-+      break;
-     case DEFINED_ABS_SEGMENT:
-       if (fragP->fr_symbol == GOT_symbol)
-         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
- 	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
-       else
-         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
--	         fragP->fr_offset, FALSE, BFD_RELOC_64);
-+	         fragP->fr_offset, TRUE, BFD_RELOC_64);
-       fragP->fr_fix += INST_WORD_SIZE * 2;
-       fragP->fr_var = 0;
-       break;
-@@ -2412,22 +2428,38 @@ md_apply_fix (fixS *   fixP,
-     case BFD_RELOC_64_PCREL:
-     case BFD_RELOC_64:
-     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
-+    case BFD_RELOC_MICROBLAZE_64:
-       /* Add an imm instruction.  First save the current instruction.  */
-       for (i = 0; i < INST_WORD_SIZE; i++)
- 	buf[i + INST_WORD_SIZE] = buf[i];
-+      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+        {
-+          /* Generate the imm instruction.  */
-+          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+          if (opcode1 == NULL)
-+	    {
-+	      as_bad (_("unknown opcode \"%s\""), "imml");
-+	      return;
-+	    }
- 
--      /* Generate the imm instruction.  */
--      opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
--      if (opcode1 == NULL)
--	{
--	  as_bad (_("unknown opcode \"%s\""), "imm");
--	  return;
--	}
--
--      inst1 = opcode1->bit_sequence;
--      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
--	inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
--
-+           inst1 = opcode1->bit_sequence;
-+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+         }
-+      else
-+        {
-+          /* Generate the imm instruction.  */
-+          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+          if (opcode1 == NULL)
-+	    {
-+	      as_bad (_("unknown opcode \"%s\""), "imm");
-+	      return;
-+	    }
-+     
-+          inst1 = opcode1->bit_sequence;
-+          if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
-+         }
-       buf[0] = INST_BYTE0 (inst1);
-       buf[1] = INST_BYTE1 (inst1);
-       buf[2] = INST_BYTE2 (inst1);
-@@ -2456,6 +2488,7 @@ md_apply_fix (fixS *   fixP,
-       /* Fall through.  */
- 
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-     case BFD_RELOC_MICROBLAZE_64_PLT:
-     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
-@@ -2463,12 +2496,16 @@ md_apply_fix (fixS *   fixP,
-       /* Add an imm instruction.  First save the current instruction.  */
-       for (i = 0; i < INST_WORD_SIZE; i++)
- 	buf[i + INST_WORD_SIZE] = buf[i];
--
--      /* Generate the imm instruction.  */
--      opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
-+        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+      else
-+        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-       if (opcode1 == NULL)
- 	{
--	  as_bad (_("unknown opcode \"%s\""), "imm");
-+      	  if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
-+	    as_bad (_("unknown opcode \"%s\""), "imml");
-+          else
-+	    as_bad (_("unknown opcode \"%s\""), "imm");
- 	  return;
- 	}
- 
-@@ -2490,7 +2527,7 @@ md_apply_fix (fixS *   fixP,
-     {
-       /* This fixup has been resolved.  Create a reloc in case the linker
- 	 moves code around due to relaxing.  */
--      if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
-+      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-       else if (fixP->fx_r_type == BFD_RELOC_32)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
-@@ -2535,12 +2572,30 @@ md_estimate_size_before_relax (fragS * fragP,
-           as_bad (_("Absolute PC-relative value in relaxation code.  Assembler error....."));
-           abort ();
-         }
--      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
--               !S_IS_WEAK (fragP->fr_symbol))
-+      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type
-+               && !S_IS_WEAK (fragP->fr_symbol))
-         {
--          fragP->fr_subtype = DEFINED_PC_OFFSET;
--          /* Don't know now whether we need an imm instruction.  */
--          fragP->fr_var = INST_WORD_SIZE;
-+           if (fragP->fr_opcode != NULL) {
-+	     if(streq (fragP->fr_opcode, str_microblaze_64)) 
-+             {
-+               /* Used as an absolute value.  */
-+              fragP->fr_subtype = DEFINED_64_OFFSET;
-+               /* Variable part does not change.  */
-+              fragP->fr_var = INST_WORD_SIZE;
-+	     }
-+	   else
-+	     {
-+               fragP->fr_subtype = DEFINED_PC_OFFSET;
-+      	       /* Don't know now whether we need an imm instruction.  */
-+               fragP->fr_var = INST_WORD_SIZE;
-+	     }
-+	   }  
-+	   else
-+	     {
-+               fragP->fr_subtype = DEFINED_PC_OFFSET;
-+      	       /* Don't know now whether we need an imm instruction.  */
-+               fragP->fr_var = INST_WORD_SIZE;
-+	     }
-         }
-       else if (S_IS_DEFINED (fragP->fr_symbol)
- 	       && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0))
-@@ -2644,6 +2699,7 @@ md_estimate_size_before_relax (fragS * fragP,
-     case TLSLD_OFFSET:
-     case TLSTPREL_OFFSET:
-     case TLSDTPREL_OFFSET:
-+    case DEFINED_64_OFFSET:
-       fragP->fr_var = INST_WORD_SIZE*2;
-       break;
-     case DEFINED_RO_SEGMENT:
-@@ -2697,7 +2753,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
-   else
-     {
-       /* The case where we are going to resolve things... */
--      if (fixp->fx_r_type == BFD_RELOC_64_PCREL)
-+      if (fixp->fx_r_type == BFD_RELOC_64_PCREL || fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
-       else
-         return  fixp->fx_where + fixp->fx_frag->fr_address;
-@@ -2730,6 +2786,8 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
-     case BFD_RELOC_MICROBLAZE_32_RWSDA:
-     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+    case BFD_RELOC_MICROBLAZE_64:
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-     case BFD_RELOC_MICROBLAZE_64_PLT:
-     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
-@@ -2872,7 +2930,10 @@ cons_fix_new_microblaze (fragS * frag,
-           r = BFD_RELOC_32;
-           break;
-         case 8:
--          r = BFD_RELOC_64;
-+          if (microblaze_arch_size == 64)
-+            r = BFD_RELOC_32;
-+          else
-+            r = BFD_RELOC_64;
-           break;
-         default:
-           as_bad (_("unsupported BFD relocation size %u"), size);
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 55f34f72b0d..8576e55cb8a 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
-+  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
-+  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
- 
- /* Global base address names.  */
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 61eaa39b3eb..f2139a6839b 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -538,8 +538,8 @@ struct op_code_struct
-   {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
-   {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
-   {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
--  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
--  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-+  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
-+  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-   {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
-   {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
-   {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 1dcd3dca3d1..ad8b8ce345b 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -40,8 +40,8 @@ enum microblaze_instr
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
-   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
--  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
--  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-+  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
-+  sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
-   fint, fsqrt,
-   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
new file mode 100644
index 0000000000..6a3e34c428
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
@@ -0,0 +1,36 @@
+From 5b9a1079eefbfbe23992f231ad69af488040e302 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 11 Sep 2018 13:48:33 +0530
+Subject: [PATCH 16/52] [Patch,Microblaze] : negl instruction is overriding
+ rsubl,fixed it by changing the instruction order...
+
+---
+ opcodes/microblaze-opc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f2139a6839..f970941209 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -275,9 +275,7 @@ struct op_code_struct
+   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
+   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
+   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
+-  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
+   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
+-  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
+   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+@@ -555,6 +553,8 @@ struct op_code_struct
+   {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
+   {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
+   {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
++  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+ 
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Added-relocations-for-MB-X.patch
new file mode 100644
index 0000000000..3e0773b0f7
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Added-relocations-for-MB-X.patch
@@ -0,0 +1,346 @@
+From 442430f1010a9e16821e68ca2842579538ff564b Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 17/52] Added relocations for MB-X
+
+Conflicts:
+	bfd/bfd-in2.h
+	gas/config/tc-microblaze.c
+---
+ bfd/bfd-in2.h              |  9 +++-
+ bfd/libbfd.h               |  4 +-
+ bfd/reloc.c                | 26 ++++++-----
+ gas/config/tc-microblaze.c | 90 ++++++++++++++++----------------------
+ 4 files changed, 61 insertions(+), 68 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index a335182ba1..57ea4f6132 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5436,13 +5436,18 @@ done here - only used for relaxing  */
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+-  BFD_RELOC_MICROBLAZE_64_NONE,
++  BFD_RELOC_MICROBLAZE_64_PCREL,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit relative
+  *  +value in two words (with an imml instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64,
+ 
++/* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imm instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index b4aace6a70..b4b7ee29a3 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -2969,14 +2969,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+-  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+-  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 0e8a24e9cb..b5c97da3ff 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6866,24 +6866,12 @@ ENUMDOC
+   done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+-ENUMDOC
+-  This is a 32 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+@@ -6969,6 +6957,20 @@ ENUMDOC
+   value in two words (with an imm instruction).  The relocation is
+   relative offset from start of TEXT.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_AARCH64_RELOC_START
+ ENUMDOC
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 33eda2a4da..5e11a77e70 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -95,6 +95,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
+ #define TEXT_OFFSET	     17
+ #define TEXT_PC_OFFSET       18
+ #define DEFINED_64_OFFSET   19
++#define DEFINED_64_PC_OFFSET 20 
+ 
+ /* Initialize the relax table.  */
+ const relax_typeS md_relax_table[] =
+@@ -119,7 +120,8 @@ const relax_typeS md_relax_table[] =
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
+   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },   /* 18: TEXT_PC_OFFSET.  */
+ //  { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 }   /* 16: TLSTPREL_OFFSET.  */
+-  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }   /* 17: DEFINED_64_OFFSET.  */
++  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 },   /* 19: DEFINED_64_OFFSET.  */
++  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 }   /* 20: DEFINED_64_PC_OFFSET.  */
+ };
+ 
+ static struct hash_control * opcode_hash_control;	/* Opcode mnemonics.  */
+@@ -1180,33 +1182,6 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+ 	}
+-#if 0 //revisit
+-      else if (streq (name, "lli") || streq (name, "sli"))
+-	{
+-          temp = immed & 0xFFFFFFFFFFFF8000;
+-          if ((temp != 0) && (temp != 0xFFFFFFFFFFFF8000))
+-	    {
+-              /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+-              if (opcode1 == NULL)
+-                {
+-                  as_bad (_("unknown opcode \"%s\""), "imml");
+-                  return;
+-                }
+-
+-              inst1 = opcode1->bit_sequence;
+-	      inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+-              output[0] = INST_BYTE0 (inst1);
+-              output[1] = INST_BYTE1 (inst1);
+-              output[2] = INST_BYTE2 (inst1);
+-              output[3] = INST_BYTE3 (inst1);
+-              output = frag_more (isize);
+-	    }
+-	  inst |= (reg1 << RD_LOW) & RD_MASK;
+-	  inst |= (reg2 << RA_LOW) & RA_MASK;
+-	  inst |= (immed << IMM_LOW) & IMM_MASK;
+-        }
+-#endif
+       else
+ 	{
+           temp = immed & 0xFFFF8000;
+@@ -1958,8 +1933,8 @@ md_assemble (char * str)
+ 
+       if (exp.X_op != O_constant)
+ 	{
+-	  char *opc = NULL;
+-	  //char *opc = str_microblaze_64;
++	  //char *opc = NULL;
++	  char *opc = str_microblaze_64;
+ 	  relax_substateT subtype;
+ 
+ 	  if (exp.X_md != 0)
+@@ -2218,13 +2193,19 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
++    case DEFINED_64_PC_OFFSET:
++      fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
++	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL);
++      fragP->fr_fix += INST_WORD_SIZE * 2;
++      fragP->fr_var = 0;
++      break;
+     case DEFINED_64_OFFSET:
+       if (fragP->fr_symbol == GOT_symbol)
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
+-	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC);
++	         fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
+-	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64);
++	         fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+@@ -2234,7 +2215,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+ 	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
+       else
+         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
+-	         fragP->fr_offset, TRUE, BFD_RELOC_64);
++	         fragP->fr_offset, FALSE, BFD_RELOC_64);
+       fragP->fr_fix += INST_WORD_SIZE * 2;
+       fragP->fr_var = 0;
+       break;
+@@ -2453,14 +2434,17 @@ md_apply_fix (fixS *   fixP,
+ 	    }
+ 	}
+       break;
++
+     case BFD_RELOC_64_PCREL:
+     case BFD_RELOC_64:
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+     case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_64_PCREL:
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+ 	buf[i + INST_WORD_SIZE] = buf[i];
+-      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
++            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         {
+           /* Generate the imm instruction.  */
+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+@@ -2473,6 +2457,10 @@ md_apply_fix (fixS *   fixP,
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ 	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64; 
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
+          }
+       else
+         {
+@@ -2483,7 +2471,7 @@ md_apply_fix (fixS *   fixP,
+ 	      as_bad (_("unknown opcode \"%s\""), "imm");
+ 	      return;
+ 	    }
+-     
++
+           inst1 = opcode1->bit_sequence;
+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ 	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+@@ -2530,7 +2518,7 @@ md_apply_fix (fixS *   fixP,
+         opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+       if (opcode1 == NULL)
+ 	{
+-      	  if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
++          if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+ 	    as_bad (_("unknown opcode \"%s\""), "imml");
+           else
+ 	    as_bad (_("unknown opcode \"%s\""), "imm");
+@@ -2557,8 +2545,6 @@ md_apply_fix (fixS *   fixP,
+ 	 moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+-      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+-	    fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+@@ -2609,33 +2595,24 @@ md_estimate_size_before_relax (fragS * fragP,
+ 	     if(streq (fragP->fr_opcode, str_microblaze_64)) 
+              {
+                /* Used as an absolute value.  */
+-              fragP->fr_subtype = DEFINED_64_OFFSET;
++              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
+                /* Variable part does not change.  */
+-              fragP->fr_var = INST_WORD_SIZE;
++              fragP->fr_var = INST_WORD_SIZE*2;
+ 	     }
+ 	   else
+ 	     {
+                fragP->fr_subtype = DEFINED_PC_OFFSET;
+-      	       /* Don't know now whether we need an imm instruction.  */
++               /* Don't know now whether we need an imm instruction.  */
+                fragP->fr_var = INST_WORD_SIZE;
+ 	     }
+ 	   }  
+ 	   else
+ 	     {
+                fragP->fr_subtype = DEFINED_PC_OFFSET;
+-      	       /* Don't know now whether we need an imm instruction.  */
++               /* Don't know now whether we need an imm instruction.  */
+                fragP->fr_var = INST_WORD_SIZE;
+ 	     }
+         }
+-    #if 0
+-      else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
+-               !S_IS_WEAK (fragP->fr_symbol))
+-        {
+-          fragP->fr_subtype = DEFINED_PC_OFFSET;
+-          /* Don't know now whether we need an imm instruction.  */
+-          fragP->fr_var = INST_WORD_SIZE;
+-        }
+-#endif
+       else if (S_IS_DEFINED (fragP->fr_symbol)
+ 	       && (((S_GET_SEGMENT (fragP->fr_symbol))->flags & SEC_CODE) == 0))
+         {
+@@ -2665,6 +2642,13 @@ md_estimate_size_before_relax (fragS * fragP,
+ 	      /* Variable part does not change.  */
+ 	      fragP->fr_var = INST_WORD_SIZE*2;
+ 	    }
++	  else if (streq (fragP->fr_opcode, str_microblaze_64))
++	    {
++              /* Used as an absolute value.  */
++              fragP->fr_subtype = DEFINED_64_OFFSET;
++              /* Variable part does not change.  */
++              fragP->fr_var = INST_WORD_SIZE;
++            }
+ 	  else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor))
+ 	    {
+               /* It is accessed using the small data read only anchor.  */
+@@ -2739,6 +2723,7 @@ md_estimate_size_before_relax (fragS * fragP,
+     case TLSTPREL_OFFSET:
+     case TLSDTPREL_OFFSET:
+     case DEFINED_64_OFFSET:
++    case DEFINED_64_PC_OFFSET:
+       fragP->fr_var = INST_WORD_SIZE*2;
+       break;
+     case DEFINED_RO_SEGMENT:
+@@ -2792,7 +2777,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
+   else
+     {
+       /* The case where we are going to resolve things... */
+-      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++      if (fixp->fx_r_type == BFD_RELOC_64_PCREL ||fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
+       else
+         return  fixp->fx_where + fixp->fx_frag->fr_address;
+@@ -2827,6 +2812,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+     case BFD_RELOC_MICROBLAZE_64_GPC:
+     case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_64_PCREL:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+     case BFD_RELOC_MICROBLAZE_64_PLT:
+     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
deleted file mode 100644
index 067d926655..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From 48f658aba97d74c702b2fc5f1577d63c800b91f5 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 11 Sep 2018 13:48:33 +0530
-Subject: [PATCH 17/40] [Patch,Microblaze] : negl instruction is overriding
- rsubl
-
-fixed it by changing the instruction order...
----
- opcodes/microblaze-opc.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index f2139a6839b..f9709412097 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -275,9 +275,7 @@ struct op_code_struct
-   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
-   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
-   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
--  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
--  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
-   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
-   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
-   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
-@@ -555,6 +553,8 @@ struct op_code_struct
-   {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
-   {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
-   {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
-+  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-+  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
- 
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
- };
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Added-relocations-for-MB-X.patch
deleted file mode 100644
index 0ed01b795d..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Added-relocations-for-MB-X.patch
+++ /dev/null
@@ -1,300 +0,0 @@
-From 90d732c25cb6b55b33837e1d23d6850e4cbe10f7 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 11 Sep 2018 17:30:17 +0530
-Subject: [PATCH 18/40] Added relocations for MB-X
-
----
- bfd/bfd-in2.h              | 11 +++++---
- bfd/libbfd.h               |  4 +--
- bfd/reloc.c                | 26 +++++++++---------
- gas/config/tc-microblaze.c | 54 +++++++++++++++++++++++++++-----------
- 4 files changed, 63 insertions(+), 32 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index c55092c9ec7..88f89bcdbcd 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5434,15 +5434,20 @@ done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_32_NONE,
- 
- /* This is a 64 bit reloc that stores the 32 bit pc relative
--value in two words (with an imm instruction).  No relocation is
-+value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
--  BFD_RELOC_MICROBLAZE_64_NONE,
-+  BFD_RELOC_MICROBLAZE_64_PCREL,
- 
--/* This is a 64 bit reloc that stores the 32 bit pc relative
-+/* This is a 64 bit reloc that stores the 32 bit relative
- value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imm instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_64_NONE,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- PC-relative GOT offset  */
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index b4aace6a70d..b4b7ee29a30 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2969,14 +2969,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-   "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
--  "BFD_RELOC_MICROBLAZE_64",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
--  "BFD_RELOC_MICROBLAZE_64_GPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-   "BFD_RELOC_MICROBLAZE_64_PLT",
-   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_COPY",
-+  "BFD_RELOC_MICROBLAZE_64",
-+  "BFD_RELOC_MICROBLAZE_64_PCREL",
-   "BFD_RELOC_MICROBLAZE_64_TLS",
-   "BFD_RELOC_MICROBLAZE_64_TLSGD",
-   "BFD_RELOC_MICROBLAZE_64_TLSLD",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 0e8a24e9cb0..b5c97da3ffd 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6866,24 +6866,12 @@ ENUMDOC
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
--ENUMDOC
--  This is a 32 bit reloc that stores the 32 bit pc relative
--  value in two words (with an imml instruction).  No relocation is
--  done here - only used for relaxing
--ENUM
--  BFD_RELOC_MICROBLAZE_64
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  No relocation is
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_GOTPC
--ENUMDOC
--  This is a 64 bit reloc that stores the 32 bit pc relative
--  value in two words (with an imml instruction).  No relocation is
--  done here - only used for relaxing
--ENUM
--  BFD_RELOC_MICROBLAZE_64_GPC
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  The relocation is
-@@ -6969,6 +6957,20 @@ ENUMDOC
-   value in two words (with an imm instruction).  The relocation is
-   relative offset from start of TEXT.
- 
-+  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
-+  to two words (uses imml instruction).
-+ENUM
-+BFD_RELOC_MICROBLAZE_64,
-+ENUMDOC
-+ This is a 64 bit reloc that stores the 64 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
-+ENUM
-+BFD_RELOC_MICROBLAZE_64_PCREL,
-+ENUMDOC
-+ This is a 32 bit reloc that stores the 32 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
- ENUM
-   BFD_RELOC_AARCH64_RELOC_START
- ENUMDOC
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index b8250e4cded..9c8b6284fb1 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -95,6 +95,7 @@ const char FLT_CHARS[] = "rRsSfFdDxXpP";
- #define TEXT_OFFSET	     17
- #define TEXT_PC_OFFSET       18
- #define DEFINED_64_OFFSET   19
-+#define DEFINED_64_PC_OFFSET 20 
- 
- /* Initialize the relax table.  */
- const relax_typeS md_relax_table[] =
-@@ -118,7 +119,8 @@ const relax_typeS md_relax_table[] =
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 16: TLSTPREL_OFFSET.  */
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 17: TEXT_OFFSET.  */
-   { 0x7fffffff, 0x80000000, INST_WORD_SIZE*2, 0 },  /* 18: TEXT_PC_OFFSET.  */
--  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 }   /* 19: DEFINED_64_OFFSET.  */
-+  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE, 0 },   /* 19: DEFINED_64_OFFSET.  */
-+  { 0x7fffffffffffffff, 0x8000000000000000, INST_WORD_SIZE*2, 0 }  /* 20: DEFINED_64_PC_OFFSET.  */
- };
- 
- static struct hash_control * opcode_hash_control;	/* Opcode mnemonics.  */
-@@ -1930,8 +1932,8 @@ md_assemble (char * str)
- 
-       if (exp.X_op != O_constant)
- 	{
--	  char *opc = NULL;
--	  //char *opc = str_microblaze_64;
-+	  //char *opc = NULL;
-+	  char *opc = strdup(str_microblaze_64);
- 	  relax_substateT subtype;
- 
- 	  if (exp.X_md != 0)
-@@ -2190,13 +2192,19 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
-       fragP->fr_fix += INST_WORD_SIZE * 2;
-       fragP->fr_var = 0;
-       break;
-+    case DEFINED_64_PC_OFFSET:
-+      fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
-+	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_PCREL);
-+      fragP->fr_fix += INST_WORD_SIZE * 2;
-+      fragP->fr_var = 0;
-+      break;
-     case DEFINED_64_OFFSET:
-       if (fragP->fr_symbol == GOT_symbol)
-         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
--	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GPC);
-+	         fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64_GPC);
-       else
-         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE, fragP->fr_symbol,
--	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64);
-+	         fragP->fr_offset, FALSE, BFD_RELOC_MICROBLAZE_64);
-       fragP->fr_fix += INST_WORD_SIZE * 2;
-       fragP->fr_var = 0;
-       break;
-@@ -2206,7 +2214,7 @@ md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
- 	         fragP->fr_offset, TRUE, BFD_RELOC_MICROBLAZE_64_GOTPC);
-       else
-         fix_new (fragP, fragP->fr_fix, INST_WORD_SIZE * 2, fragP->fr_symbol,
--	         fragP->fr_offset, TRUE, BFD_RELOC_64);
-+	         fragP->fr_offset, FALSE, BFD_RELOC_64);
-       fragP->fr_fix += INST_WORD_SIZE * 2;
-       fragP->fr_var = 0;
-       break;
-@@ -2425,14 +2433,17 @@ md_apply_fix (fixS *   fixP,
- 	    }
- 	}
-       break;
-+
-     case BFD_RELOC_64_PCREL:
-     case BFD_RELOC_64:
-     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
-     case BFD_RELOC_MICROBLAZE_64:
-+    case BFD_RELOC_MICROBLAZE_64_PCREL:
-       /* Add an imm instruction.  First save the current instruction.  */
-       for (i = 0; i < INST_WORD_SIZE; i++)
- 	buf[i + INST_WORD_SIZE] = buf[i];
--      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
-+            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-         {
-           /* Generate the imm instruction.  */
-           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-@@ -2445,6 +2456,10 @@ md_apply_fix (fixS *   fixP,
-            inst1 = opcode1->bit_sequence;
-            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- 	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+             fixP->fx_r_type = BFD_RELOC_64; 
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-+             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
-          }
-       else
-         {
-@@ -2455,7 +2470,7 @@ md_apply_fix (fixS *   fixP,
- 	      as_bad (_("unknown opcode \"%s\""), "imm");
- 	      return;
- 	    }
--     
-+
-           inst1 = opcode1->bit_sequence;
-           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- 	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
-@@ -2502,7 +2517,7 @@ md_apply_fix (fixS *   fixP,
-         opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-       if (opcode1 == NULL)
- 	{
--      	  if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
-+          if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
- 	    as_bad (_("unknown opcode \"%s\""), "imml");
-           else
- 	    as_bad (_("unknown opcode \"%s\""), "imm");
-@@ -2527,7 +2542,7 @@ md_apply_fix (fixS *   fixP,
-     {
-       /* This fixup has been resolved.  Create a reloc in case the linker
- 	 moves code around due to relaxing.  */
--      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+      if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-       else if (fixP->fx_r_type == BFD_RELOC_32)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
-@@ -2579,21 +2594,21 @@ md_estimate_size_before_relax (fragS * fragP,
- 	     if(streq (fragP->fr_opcode, str_microblaze_64)) 
-              {
-                /* Used as an absolute value.  */
--              fragP->fr_subtype = DEFINED_64_OFFSET;
-+              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
-                /* Variable part does not change.  */
--              fragP->fr_var = INST_WORD_SIZE;
-+              fragP->fr_var = INST_WORD_SIZE*2;
- 	     }
- 	   else
- 	     {
-                fragP->fr_subtype = DEFINED_PC_OFFSET;
--      	       /* Don't know now whether we need an imm instruction.  */
-+               /* Don't know now whether we need an imm instruction.  */
-                fragP->fr_var = INST_WORD_SIZE;
- 	     }
- 	   }  
- 	   else
- 	     {
-                fragP->fr_subtype = DEFINED_PC_OFFSET;
--      	       /* Don't know now whether we need an imm instruction.  */
-+               /* Don't know now whether we need an imm instruction.  */
-                fragP->fr_var = INST_WORD_SIZE;
- 	     }
-         }
-@@ -2626,6 +2641,13 @@ md_estimate_size_before_relax (fragS * fragP,
- 	      /* Variable part does not change.  */
- 	      fragP->fr_var = INST_WORD_SIZE*2;
- 	    }
-+	  else if (streq (fragP->fr_opcode, str_microblaze_64))
-+	    {
-+              /* Used as an absolute value.  */
-+              fragP->fr_subtype = DEFINED_64_OFFSET;
-+              /* Variable part does not change.  */
-+              fragP->fr_var = INST_WORD_SIZE;
-+            }
- 	  else if (streq (fragP->fr_opcode, str_microblaze_ro_anchor))
- 	    {
-               /* It is accessed using the small data read only anchor.  */
-@@ -2700,6 +2722,7 @@ md_estimate_size_before_relax (fragS * fragP,
-     case TLSTPREL_OFFSET:
-     case TLSDTPREL_OFFSET:
-     case DEFINED_64_OFFSET:
-+    case DEFINED_64_PC_OFFSET:
-       fragP->fr_var = INST_WORD_SIZE*2;
-       break;
-     case DEFINED_RO_SEGMENT:
-@@ -2753,7 +2776,7 @@ md_pcrel_from_section (fixS * fixp, segT sec ATTRIBUTE_UNUSED)
-   else
-     {
-       /* The case where we are going to resolve things... */
--      if (fixp->fx_r_type == BFD_RELOC_64_PCREL || fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+      if (fixp->fx_r_type == BFD_RELOC_64_PCREL || fixp->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-         return  fixp->fx_where + fixp->fx_frag->fr_address + INST_WORD_SIZE;
-       else
-         return  fixp->fx_where + fixp->fx_frag->fr_address;
-@@ -2788,6 +2811,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-     case BFD_RELOC_MICROBLAZE_64_GPC:
-     case BFD_RELOC_MICROBLAZE_64:
-+    case BFD_RELOC_MICROBLAZE_64_PCREL:
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-     case BFD_RELOC_MICROBLAZE_64_PLT:
-     case BFD_RELOC_MICROBLAZE_64_GOTOFF:
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Fixed-MB-x-relocation-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Fixed-MB-x-relocation-issues.patch
new file mode 100644
index 0000000000..315d044508
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0018-Fixed-MB-x-relocation-issues.patch
@@ -0,0 +1,373 @@
+From 5b1793fe6dfb16755f584821023145bdfc4b55d7 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 28 Sep 2018 12:04:55 +0530
+Subject: [PATCH 18/52] -Fixed MB-x relocation issues -Added imml for required
+ MB-x instructions
+
+---
+ bfd/elf64-microblaze.c     |  68 ++++++++++++++---
+ gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++----------
+ gas/tc.h                   |   2 +-
+ 3 files changed, 167 insertions(+), 55 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 6b1f47d00d..6676d9f93d 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1488,8 +1488,17 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 			  relocation -= (input_section->output_section->vma
+ 					 + input_section->output_offset
+ 					 + offset + INST_WORD_SIZE);
+-			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
++			  {
++        		    insn &= ~0x00ffffff;
++			    insn |= (relocation >> 16) & 0xffffff;
++			    bfd_put_32 (input_bfd, insn,
+ 			            contents + offset + endian);
++			  }
++			else
++			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			              contents + offset + endian);
+ 			bfd_put_16 (input_bfd, relocation & 0xffff,
+ 			            contents + offset + endian + INST_WORD_SIZE);
+ 		      }
+@@ -1580,11 +1589,28 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 		    else
+ 		      {
+ 			if (r_type == R_MICROBLAZE_64_PCREL)
+-			  relocation -= (input_section->output_section->vma
+-					 + input_section->output_offset
+-					 + offset + INST_WORD_SIZE);
+-			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			  {
++			    if (!input_section->output_section->vma &&
++				 !input_section->output_offset && !offset)	
++			      relocation -= (input_section->output_section->vma
++			                     + input_section->output_offset
++					     + offset);
++			    else
++			      relocation -= (input_section->output_section->vma
++			                     + input_section->output_offset
++					     + offset + INST_WORD_SIZE);
++			  }
++			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
++			  {
++        		    insn &= ~0x00ffffff;
++			    insn |= (relocation >> 16) & 0xffffff;
++			    bfd_put_32 (input_bfd, insn,
+ 			            contents + offset + endian);
++			  }
++			else
++			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			              contents + offset + endian);
+ 			bfd_put_16 (input_bfd, relocation & 0xffff,
+ 			            contents + offset + endian + INST_WORD_SIZE);
+ 		      }
+@@ -1703,9 +1729,19 @@ static void
+ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ {
+     unsigned long instr = bfd_get_32 (abfd, bfd_addr);
+-    instr &= ~0x0000ffff;
+-    instr |= (val & 0x0000ffff);
+-    bfd_put_32 (abfd, instr, bfd_addr);
++
++    if (instr == 0xb2000000 || instr == 0xb2ffffff)
++      {
++        instr &= ~0x00ffffff;
++        instr |= (val & 0xffffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
++    else
++      {
++        instr &= ~0x0000ffff;
++        instr |= (val & 0x0000ffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
+ }
+ 
+ /* Read-modify-write into the bfd, an immediate value into appropriate fields of
+@@ -1717,10 +1753,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+     unsigned long instr_lo;
+ 
+     instr_hi = bfd_get_32 (abfd, bfd_addr);
+-    instr_hi &= ~0x0000ffff;
+-    instr_hi |= ((val >> 16) & 0x0000ffff);
+-    bfd_put_32 (abfd, instr_hi, bfd_addr);
+-
++    if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
++      {
++        instr_hi &= ~0x00ffffff;
++        instr_hi |= (val >> 16) & 0xffffff;
++        bfd_put_32 (abfd, instr_hi,bfd_addr);
++      }
++    else
++      {
++        instr_hi &= ~0x0000ffff;
++        instr_hi |= ((val >> 16) & 0x0000ffff);
++        bfd_put_32 (abfd, instr_hi, bfd_addr);
++      }
+     instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
+     instr_lo &= ~0x0000ffff;
+     instr_lo |= (val & 0x0000ffff);
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 5e11a77e70..48f306ef41 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -392,7 +392,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+    Integer arg to pass to the function.  */
+ /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
+    and then in the read.c table.  */
+-const pseudo_typeS md_pseudo_table[] =
++pseudo_typeS md_pseudo_table[] =
+ {
+   {"lcomm", microblaze_s_lcomm, 1},
+   {"data", microblaze_s_data, 0},
+@@ -401,7 +401,7 @@ const pseudo_typeS md_pseudo_table[] =
+   {"data32", cons, 4},     /* Same as word.  */
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+-  {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
++  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
+   {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+@@ -996,7 +996,7 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned int immed, immed2, temp;
++  unsigned long immed, immed2, temp;
+   expressionS exp;
+   char name[20];
+   long immedl;
+@@ -1118,8 +1118,9 @@ md_assemble (char * str)
+ 	    as_fatal (_("lmi pseudo instruction should not use a label in imm field"));
+ 	  else if (streq (name, "smi"))
+ 	    as_fatal (_("smi pseudo instruction should not use a label in imm field"));
+-
+-	  if (reg2 == REG_ROSDP)
++          if(streq (name, "lli") || streq (name, "sli"))
++            opc = str_microblaze_64;
++	  else if (reg2 == REG_ROSDP)
+ 	    opc = str_microblaze_ro_anchor;
+ 	  else if (reg2 == REG_RWSDP)
+ 	    opc = str_microblaze_rw_anchor;
+@@ -1182,31 +1183,55 @@ md_assemble (char * str)
+               inst |= (immed << IMM_LOW) & IMM_MASK;
+             }
+ 	}
+-      else
+-	{
+-          temp = immed & 0xFFFF8000;
+-          if ((temp != 0) && (temp != 0xFFFF8000))
+-	    {
++      else if (streq (name, "lli") || streq (name, "sli"))
++        {
++          temp = immed & 0xFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFF8000)
++            {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+               if (opcode1 == NULL)
+                 {
+-                  as_bad (_("unknown opcode \"%s\""), "imm");
++                  as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+-
+               inst1 = opcode1->bit_sequence;
+-              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+-	    }
+-	  inst |= (reg1 << RD_LOW) & RD_MASK;
+-	  inst |= (reg2 << RA_LOW) & RA_MASK;
+-	  inst |= (immed << IMM_LOW) & IMM_MASK;
+-	}
++            }
++          inst |= (reg1 << RD_LOW) & RD_MASK;
++          inst |= (reg2 << RA_LOW) & RA_MASK;
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++         }
++       else 
++	 {
++           temp = immed & 0xFFFF8000;
++           if ((temp != 0) && (temp != 0xFFFF8000))
++	     {
++               /* Needs an immediate inst.  */
++               opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++               if (opcode1 == NULL)
++                 {
++                   as_bad (_("unknown opcode \"%s\""), "imm");
++                   return;
++                 }
++
++               inst1 = opcode1->bit_sequence;
++               inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++               output[0] = INST_BYTE0 (inst1);
++               output[1] = INST_BYTE1 (inst1);
++               output[2] = INST_BYTE2 (inst1);
++               output[3] = INST_BYTE3 (inst1);
++               output = frag_more (isize);
++	     }
++	   inst |= (reg1 << RD_LOW) & RD_MASK;
++	   inst |= (reg2 << RA_LOW) & RA_MASK;
++	   inst |= (immed << IMM_LOW) & IMM_MASK;
++	 }
+       break;
+ 
+     case INST_TYPE_RD_R1_IMMS:
+@@ -1832,12 +1857,20 @@ md_assemble (char * str)
+     case INST_TYPE_IMM:
+       if (streq (name, "imm"))
+         as_fatal (_("An IMM instruction should not be present in the .s file"));
+-
+-      op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++      if (microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
+ 
+       if (exp.X_op != O_constant)
+ 	{
+-          char *opc = NULL;
++	  char *opc;
++          if (microblaze_arch_size == 64 && (streq (name, "breai") || 
++		 streq (name, "breaid") || 
++	         streq (name, "brai") || streq (name, "braid")))
++            opc = str_microblaze_64;
++	  else
++            opc = NULL;
+           relax_substateT subtype;
+ 
+ 	  if (exp.X_md != 0)
+@@ -1860,27 +1893,54 @@ md_assemble (char * str)
+           immed = exp.X_add_number;
+         }
+ 
++      if (microblaze_arch_size == 64 && (streq (name, "breai") || 
++            streq (name, "breaid") || 
++	    streq (name, "brai") || streq (name, "braid")))
++        {
++          temp = immed & 0xFFFFFF8000;
++          if (temp != 0)
++	    {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
+ 
+-      temp = immed & 0xFFFF8000;
+-      if ((temp != 0) && (temp != 0xFFFF8000))
+-	{
+-          /* Needs an immediate inst.  */
+-          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+-          if (opcode1 == NULL)
+-            {
+-              as_bad (_("unknown opcode \"%s\""), "imm");
+-              return;
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
+             }
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++	}
++      else
++	{
++          temp = immed & 0xFFFF8000;
++          if ((temp != 0) && (temp != 0xFFFF8000))
++	    {
++              /* Needs an immediate inst.  */
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imm");
++                  return;
++                }
+ 
+-          inst1 = opcode1->bit_sequence;
+-          inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
+-          output[0] = INST_BYTE0 (inst1);
+-          output[1] = INST_BYTE1 (inst1);
+-          output[2] = INST_BYTE2 (inst1);
+-          output[3] = INST_BYTE3 (inst1);
+-          output = frag_more (isize);
+-        }
+-      inst |= (immed << IMM_LOW) & IMM_MASK;
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++          inst |= (immed << IMM_LOW) & IMM_MASK;
++	}
+       break;
+ 
+     case INST_TYPE_NONE:
+@@ -2456,7 +2516,7 @@ md_apply_fix (fixS *   fixP,
+ 
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++	     inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+              fixP->fx_r_type = BFD_RELOC_64; 
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+@@ -2624,7 +2684,14 @@ md_estimate_size_before_relax (fragS * fragP,
+         }
+       else
+ 	{
+-	  fragP->fr_subtype = UNDEFINED_PC_OFFSET;
++	  if (fragP->fr_opcode != NULL) {
++	    if (streq (fragP->fr_opcode, str_microblaze_64)) 
++              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
++	    else
++	      fragP->fr_subtype = UNDEFINED_PC_OFFSET;
++	    }
++	  else
++	    fragP->fr_subtype = UNDEFINED_PC_OFFSET;
+ 	  fragP->fr_var = INST_WORD_SIZE*2;
+ 	}
+       break;
+@@ -2901,6 +2968,7 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_M64:
+       //if (arg != NULL && strcmp (arg, "64") == 0)
+       microblaze_arch_size = 64;
++      md_pseudo_table[7].poc_val = 8;
+       break;
+     default:
+       return 0;
+diff --git a/gas/tc.h b/gas/tc.h
+index da1738d67a..5bdfe5c347 100644
+--- a/gas/tc.h
++++ b/gas/tc.h
+@@ -22,7 +22,7 @@
+ /* In theory (mine, at least!) the machine dependent part of the assembler
+    should only have to include one file.  This one.  -- JF */
+ 
+-extern const pseudo_typeS md_pseudo_table[];
++extern pseudo_typeS md_pseudo_table[];
+ 
+ const char * md_atof (int, char *, int *);
+ int    md_parse_option (int, const char *);
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Fixing-the-branch-related-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Fixing-the-branch-related-issues.patch
new file mode 100644
index 0000000000..027b8e8357
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Fixing-the-branch-related-issues.patch
@@ -0,0 +1,28 @@
+From 33081da0bb8820f3c695d8f865582436b16002bf Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 17:06:58 +0530
+Subject: [PATCH 19/52] Fixing the branch related issues
+
+Conflicts:
+	bfd/elf64-microblaze.c
+---
+ bfd/elf64-microblaze.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 6676d9f93d..d7b7d9f5e7 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -2545,6 +2545,9 @@ microblaze_elf_check_relocs (bfd * abfd,
+ 	  while (h->root.type == bfd_link_hash_indirect
+ 		 || h->root.type == bfd_link_hash_warning)
+ 	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
++	  /* PR15323, ref flags aren't set for references in the same
++	     object.  */
++	  h->root.non_ir_ref_regular = 1;
+ 	}
+ 
+       switch (r_type)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Update-MB-x.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Update-MB-x.patch
deleted file mode 100644
index a621fb05a1..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0019-Update-MB-x.patch
+++ /dev/null
@@ -1,478 +0,0 @@
-From c3e194e231529c1b642f7f1a19a2a7b1ea644bd9 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 28 Sep 2018 12:04:55 +0530
-Subject: [PATCH 19/40] Update MB-x
-
--Fixed MB-x relocation issues
--Added imml for required MB-x instructions
----
- bfd/elf64-microblaze.c     |  68 ++++++++++--
- gas/config/tc-microblaze.c | 221 +++++++++++++++++++++++++------------
- gas/tc.h                   |   2 +-
- 3 files changed, 209 insertions(+), 82 deletions(-)
-
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index d55700fc513..f8f52870639 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -1478,8 +1478,17 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 			  relocation -= (input_section->output_section->vma
- 					 + input_section->output_offset
- 					 + offset + INST_WORD_SIZE);
--			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
-+			if (insn == 0xb2000000 || insn == 0xb2ffffff)
-+			  {
-+			    insn &= ~0x00ffffff;
-+			    insn |= (relocation >> 16) & 0xffffff;
-+			    bfd_put_32 (input_bfd, insn,
- 			            contents + offset + endian);
-+			  }
-+			else
-+			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			              contents + offset + endian);
- 			bfd_put_16 (input_bfd, relocation & 0xffff,
- 			            contents + offset + endian + INST_WORD_SIZE);
- 		      }
-@@ -1569,11 +1578,28 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 		    else
- 		      {
- 			if (r_type == R_MICROBLAZE_64_PCREL)
--			  relocation -= (input_section->output_section->vma
--					 + input_section->output_offset
--					 + offset + INST_WORD_SIZE);
--			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			  {
-+			    if (!input_section->output_section->vma &&
-+				 !input_section->output_offset && !offset)
-+			      relocation -= (input_section->output_section->vma
-+			                     + input_section->output_offset
-+					     + offset);
-+			    else
-+			      relocation -= (input_section->output_section->vma
-+			                     + input_section->output_offset
-+					     + offset + INST_WORD_SIZE);
-+			  }
-+			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
-+			if (insn == 0xb2000000 || insn == 0xb2ffffff)
-+			  {
-+			    insn &= ~0x00ffffff;
-+			    insn |= (relocation >> 16) & 0xffffff;
-+			    bfd_put_32 (input_bfd, insn,
- 			            contents + offset + endian);
-+			  }
-+			else
-+			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			              contents + offset + endian);
- 			bfd_put_16 (input_bfd, relocation & 0xffff,
- 			            contents + offset + endian + INST_WORD_SIZE);
- 		      }
-@@ -1677,9 +1703,19 @@ static void
- microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
- {
-     unsigned long instr = bfd_get_32 (abfd, bfd_addr);
--    instr &= ~0x0000ffff;
--    instr |= (val & 0x0000ffff);
--    bfd_put_32 (abfd, instr, bfd_addr);
-+
-+    if (instr == 0xb2000000 || instr == 0xb2ffffff)
-+      {
-+        instr &= ~0x00ffffff;
-+        instr |= (val & 0xffffff);
-+        bfd_put_32 (abfd, instr, bfd_addr);
-+      }
-+    else
-+      {
-+        instr &= ~0x0000ffff;
-+        instr |= (val & 0x0000ffff);
-+        bfd_put_32 (abfd, instr, bfd_addr);
-+      }
- }
- 
- /* Read-modify-write into the bfd, an immediate value into appropriate fields of
-@@ -1691,10 +1727,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-     unsigned long instr_lo;
- 
-     instr_hi = bfd_get_32 (abfd, bfd_addr);
--    instr_hi &= ~0x0000ffff;
--    instr_hi |= ((val >> 16) & 0x0000ffff);
--    bfd_put_32 (abfd, instr_hi, bfd_addr);
--
-+    if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
-+      {
-+        instr_hi &= ~0x00ffffff;
-+        instr_hi |= (val >> 16) & 0xffffff;
-+        bfd_put_32 (abfd, instr_hi,bfd_addr);
-+      }
-+    else
-+      {
-+        instr_hi &= ~0x0000ffff;
-+        instr_hi |= ((val >> 16) & 0x0000ffff);
-+        bfd_put_32 (abfd, instr_hi, bfd_addr);
-+      }
-     instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
-     instr_lo &= ~0x0000ffff;
-     instr_lo |= (val & 0x0000ffff);
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 9c8b6284fb1..f61fdf3b90a 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -391,7 +391,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
-    Integer arg to pass to the function.  */
- /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
-    and then in the read.c table.  */
--const pseudo_typeS md_pseudo_table[] =
-+pseudo_typeS md_pseudo_table[] =
- {
-   {"lcomm", microblaze_s_lcomm, 1},
-   {"data", microblaze_s_data, 0},
-@@ -400,7 +400,7 @@ const pseudo_typeS md_pseudo_table[] =
-   {"data32", cons, 4},     /* Same as word.  */
-   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
-   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
--  {"gpword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
-+  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
-   {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
-   {"weakext", microblaze_s_weakext, 0},
-   {"rodata", microblaze_s_rdata, 0},
-@@ -538,30 +538,6 @@ parse_reg (char * s, unsigned * reg)
-       *reg = REG_SP;
-       return s + 3;
-     }
--  else if (strncasecmp (s, "rfsl", 4) == 0)
--    {
--      if (ISDIGIT (s[4]) && ISDIGIT (s[5]))
--        {
--          tmpreg = (s[4] - '0') * 10 + s[5] - '0';
--          s += 6;
--        }
--      else if (ISDIGIT (s[4]))
--        {
--          tmpreg = s[4] - '0';
--          s += 5;
--        }
--      else
--	as_bad (_("register expected, but saw '%.6s'"), s);
--
--      if ((int) tmpreg >= MIN_REGNUM && tmpreg <= MAX_REGNUM)
--        *reg = tmpreg;
--      else
--	{
--          as_bad (_("Invalid register number at '%.6s'"), s);
--          *reg = 0;
--	}
--      return s;
--    }
-   /* Stack protection registers.  */
-   else if (strncasecmp (s, "rshr", 4) == 0)
-     {
-@@ -605,6 +581,45 @@ parse_reg (char * s, unsigned * reg)
-   return s;
- }
- 
-+/* Same as above, but with long(er) register */
-+static char *
-+parse_regl (char * s, unsigned long * reg)
-+{
-+  unsigned long tmpreg = 0;
-+
-+  /* Strip leading whitespace.  */
-+  while (ISSPACE (* s))
-+    ++ s;
-+
-+  if (strncasecmp (s, "rfsl", 4) == 0)
-+    {
-+      if (ISDIGIT (s[4]) && ISDIGIT (s[5]))
-+	{
-+	  tmpreg = (s[4] - '0') * 10 + s[5] - '0';
-+	  s += 6;
-+	}
-+      else if (ISDIGIT (s[4]))
-+	{
-+	  tmpreg = s[4] - '0';
-+	  s += 5;
-+	}
-+      else
-+	as_bad (_("register expected, but saw '%.6s'"), s);
-+
-+      if ((int) tmpreg >= MIN_REGNUM && tmpreg <= MAX_REGNUM)
-+	*reg = tmpreg;
-+      else
-+	{
-+	  as_bad (_("Invalid register number at '%.6s'"), s);
-+	  *reg = 0;
-+	}
-+      return s;
-+    }
-+  as_bad (_("register expected, but saw '%.6s'"), s);
-+  *reg = 0;
-+  return s;
-+}
-+
- static char *
- parse_exp (char *s, expressionS *e)
- {
-@@ -995,7 +1010,7 @@ md_assemble (char * str)
-   unsigned reg2;
-   unsigned reg3;
-   unsigned isize;
--  unsigned int immed, immed2, temp;
-+  unsigned long immed, immed2, temp;
-   expressionS exp;
-   char name[20];
-   long immedl;
-@@ -1117,8 +1132,9 @@ md_assemble (char * str)
- 	    as_fatal (_("lmi pseudo instruction should not use a label in imm field"));
- 	  else if (streq (name, "smi"))
- 	    as_fatal (_("smi pseudo instruction should not use a label in imm field"));
--
--	  if (reg2 == REG_ROSDP)
-+          if(streq (name, "lli") || streq (name, "sli"))
-+            opc = str_microblaze_64;
-+	  else if (reg2 == REG_ROSDP)
- 	    opc = str_microblaze_ro_anchor;
- 	  else if (reg2 == REG_RWSDP)
- 	    opc = str_microblaze_rw_anchor;
-@@ -1181,31 +1197,55 @@ md_assemble (char * str)
-               inst |= (immed << IMM_LOW) & IMM_MASK;
-             }
- 	}
--      else
--	{
--          temp = immed & 0xFFFF8000;
--          if ((temp != 0) && (temp != 0xFFFF8000))
--	    {
-+      else if (streq (name, "lli") || streq (name, "sli"))
-+        {
-+          temp = immed & 0xFFFFFF8000;
-+          if (temp != 0 && temp != 0xFFFFFF8000)
-+            {
-               /* Needs an immediate inst.  */
--              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-               if (opcode1 == NULL)
-                 {
--                  as_bad (_("unknown opcode \"%s\""), "imm");
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-                   return;
-                 }
--
-               inst1 = opcode1->bit_sequence;
--              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-+	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-               output[0] = INST_BYTE0 (inst1);
-               output[1] = INST_BYTE1 (inst1);
-               output[2] = INST_BYTE2 (inst1);
-               output[3] = INST_BYTE3 (inst1);
-               output = frag_more (isize);
--	    }
--	  inst |= (reg1 << RD_LOW) & RD_MASK;
--	  inst |= (reg2 << RA_LOW) & RA_MASK;
--	  inst |= (immed << IMM_LOW) & IMM_MASK;
--	}
-+            }
-+          inst |= (reg1 << RD_LOW) & RD_MASK;
-+          inst |= (reg2 << RA_LOW) & RA_MASK;
-+          inst |= (immed << IMM_LOW) & IMM_MASK;
-+         }
-+       else
-+	 {
-+           temp = immed & 0xFFFF8000;
-+           if ((temp != 0) && (temp != 0xFFFF8000))
-+	     {
-+               /* Needs an immediate inst.  */
-+               opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+               if (opcode1 == NULL)
-+                 {
-+                   as_bad (_("unknown opcode \"%s\""), "imm");
-+                   return;
-+                 }
-+
-+               inst1 = opcode1->bit_sequence;
-+               inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-+               output[0] = INST_BYTE0 (inst1);
-+               output[1] = INST_BYTE1 (inst1);
-+               output[2] = INST_BYTE2 (inst1);
-+               output[3] = INST_BYTE3 (inst1);
-+               output = frag_more (isize);
-+	     }
-+	   inst |= (reg1 << RD_LOW) & RD_MASK;
-+	   inst |= (reg2 << RA_LOW) & RA_MASK;
-+	   inst |= (immed << IMM_LOW) & IMM_MASK;
-+	 }
-       break;
- 
-     case INST_TYPE_RD_R1_IMMS:
-@@ -1400,7 +1440,7 @@ md_assemble (char * str)
-           reg1 = 0;
-         }
-       if (strcmp (op_end, ""))
--        op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
-+        op_end = parse_regl (op_end + 1, &immed);  /* Get rfslN.  */
-       else
- 	{
-           as_fatal (_("Error in statement syntax"));
-@@ -1454,7 +1494,7 @@ md_assemble (char * str)
-           reg1 = 0;
-         }
-       if (strcmp (op_end, ""))
--        op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
-+        op_end = parse_regl (op_end + 1, &immed);  /* Get rfslN.  */
-       else
- 	{
-           as_fatal (_("Error in statement syntax"));
-@@ -1472,7 +1512,7 @@ md_assemble (char * str)
- 
-     case INST_TYPE_RFSL:
-       if (strcmp (op_end, ""))
--        op_end = parse_reg (op_end + 1, &immed);  /* Get rfslN.  */
-+        op_end = parse_regl (op_end + 1, &immed);  /* Get rfslN.  */
-       else
- 	{
-           as_fatal (_("Error in statement syntax"));
-@@ -1831,12 +1871,20 @@ md_assemble (char * str)
-     case INST_TYPE_IMM:
-       if (streq (name, "imm"))
-         as_fatal (_("An IMM instruction should not be present in the .s file"));
--
--      op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+      if (microblaze_arch_size == 64)
-+        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-+      else
-+        op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
- 
-       if (exp.X_op != O_constant)
- 	{
--          char *opc = NULL;
-+	  char *opc;
-+          if (microblaze_arch_size == 64 && (streq (name, "breai") ||
-+		 streq (name, "breaid") ||
-+	         streq (name, "brai") || streq (name, "braid")))
-+            opc = strdup(str_microblaze_64);
-+	  else
-+            opc = NULL;
-           relax_substateT subtype;
- 
- 	  if (exp.X_md != 0)
-@@ -1859,27 +1907,54 @@ md_assemble (char * str)
-           immed = exp.X_add_number;
-         }
- 
-+      if (microblaze_arch_size == 64 && (streq (name, "breai") ||
-+            streq (name, "breaid") ||
-+	    streq (name, "brai") || streq (name, "braid")))
-+        {
-+          temp = immed & 0xFFFFFF8000;
-+          if (temp != 0)
-+	    {
-+              /* Needs an immediate inst.  */
-+              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
- 
--      temp = immed & 0xFFFF8000;
--      if ((temp != 0) && (temp != 0xFFFF8000))
--	{
--          /* Needs an immediate inst.  */
--          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
--          if (opcode1 == NULL)
--            {
--              as_bad (_("unknown opcode \"%s\""), "imm");
--              return;
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-             }
-+          inst |= (immed << IMM_LOW) & IMM_MASK;
-+	}
-+      else
-+	{
-+          temp = immed & 0xFFFF8000;
-+          if ((temp != 0) && (temp != 0xFFFF8000))
-+	    {
-+              /* Needs an immediate inst.  */
-+              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+              if (opcode1 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imm");
-+                  return;
-+                }
- 
--          inst1 = opcode1->bit_sequence;
--          inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
--          output[0] = INST_BYTE0 (inst1);
--          output[1] = INST_BYTE1 (inst1);
--          output[2] = INST_BYTE2 (inst1);
--          output[3] = INST_BYTE3 (inst1);
--          output = frag_more (isize);
--        }
--      inst |= (immed << IMM_LOW) & IMM_MASK;
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+            }
-+          inst |= (immed << IMM_LOW) & IMM_MASK;
-+	}
-       break;
- 
-     case INST_TYPE_NONE:
-@@ -2455,7 +2530,7 @@ md_apply_fix (fixS *   fixP,
- 
-            inst1 = opcode1->bit_sequence;
-            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
--	     inst1 |= ((val & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+	     inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
-            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-              fixP->fx_r_type = BFD_RELOC_64; 
-            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-@@ -2623,7 +2698,14 @@ md_estimate_size_before_relax (fragS * fragP,
-         }
-       else
- 	{
--	  fragP->fr_subtype = UNDEFINED_PC_OFFSET;
-+	  if (fragP->fr_opcode != NULL) {
-+	    if (streq (fragP->fr_opcode, str_microblaze_64))
-+              fragP->fr_subtype = DEFINED_64_PC_OFFSET;
-+	    else
-+	      fragP->fr_subtype = UNDEFINED_PC_OFFSET;
-+	    }
-+	  else
-+	    fragP->fr_subtype = UNDEFINED_PC_OFFSET;
- 	  fragP->fr_var = INST_WORD_SIZE*2;
- 	}
-       break;
-@@ -2900,6 +2982,7 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
-     case OPTION_M64:
-       //if (arg != NULL && strcmp (arg, "64") == 0)
-       microblaze_arch_size = 64;
-+      md_pseudo_table[7].poc_val = 8;
-       break;
-     default:
-       return 0;
-diff --git a/gas/tc.h b/gas/tc.h
-index da1738d67a8..5bdfe5c3475 100644
---- a/gas/tc.h
-+++ b/gas/tc.h
-@@ -22,7 +22,7 @@
- /* In theory (mine, at least!) the machine dependent part of the assembler
-    should only have to include one file.  This one.  -- JF */
- 
--extern const pseudo_typeS md_pseudo_table[];
-+extern pseudo_typeS md_pseudo_table[];
- 
- const char * md_atof (int, char *, int *);
- int    md_parse_option (int, const char *);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Fixed-address-computation-issues-with-64bit-address.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Fixed-address-computation-issues-with-64bit-address.patch
new file mode 100644
index 0000000000..d9de811d74
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Fixed-address-computation-issues-with-64bit-address.patch
@@ -0,0 +1,223 @@
+From 22b1b41a7873fa117642cad6b150f465eb9b60cb Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:14:22 +0530
+Subject: [PATCH 20/52] - Fixed address computation issues with 64bit address -
+ Fixed imml dissassamble issue
+
+Conflicts:
+	gas/config/tc-microblaze.c
+	opcodes/microblaze-dis.c
+---
+ bfd/bfd-in2.h              |  5 +++
+ bfd/elf64-microblaze.c     | 14 ++++----
+ gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
+ opcodes/microblaze-dis.c   |  2 +-
+ 4 files changed, 79 insertions(+), 16 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 57ea4f6132..05fbeb9b3a 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -5443,6 +5443,11 @@ done here - only used for relaxing  */
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64,
+ 
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_EA64,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+  *  +value in two words (with an imm instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index d7b7d9f5e7..f42d7f429b 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+           0,			/* Rightshift.  */
+           4,			/* Size (0 = byte, 1 = short, 2 = long).  */
+           64,			/* Bitsize.  */
+-          TRUE,		/* PC_relative.  */
++          FALSE,		/* PC_relative.  */
+           0,			/* Bitpos.  */
+           complain_overflow_dont, /* Complain on overflow.  */
+           bfd_elf_generic_reloc,/* Special Function.  */
+           "R_MICROBLAZE_IMML_64",   	/* Name.  */
+           FALSE,		/* Partial Inplace.  */
+           0,			/* Source Mask.  */
+-          0x0000ffff,		/* Dest Mask.  */
+-          TRUE), 		/* PC relative offset?  */
++          0xffffffffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
+ 
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
+@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_32:
+       microblaze_reloc = R_MICROBLAZE_32;
+       break;
+-      /* RVA is treated the same as 32 */
++      /* RVA is treated the same as 64 */
+     case BFD_RELOC_RVA:
+-      microblaze_reloc = R_MICROBLAZE_32;
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
+       break;
+     case BFD_RELOC_32_PCREL:
+       microblaze_reloc = R_MICROBLAZE_32_PCREL;
+@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_EA64:
+       microblaze_reloc = R_MICROBLAZE_IMML_64;
+       break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+@@ -1982,7 +1982,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	        efix = calc_fixup (target_address, 0, sec);
+ 
+             /* Validate the in-band val.  */
+-            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            val = bfd_get_64 (abfd, contents + irel->r_offset);
+             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+             }
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 48f306ef41..bfb3104720 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -402,7 +402,6 @@ pseudo_typeS md_pseudo_table[] =
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+   {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
+-  {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -2475,18 +2474,74 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_RVA:
+     case BFD_RELOC_32_PCREL:
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++      /* Don't do anything if the symbol is not defined.  */
++      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++	{
++	  if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64))
++            {
++	      if (target_big_endian)
++	        {
++	          buf[0] |= ((val >> 56) & 0xff);
++	          buf[1] |= ((val >> 48) & 0xff);
++	          buf[2] |= ((val >> 40) & 0xff);
++	          buf[3] |= ((val >> 32) & 0xff);
++	          buf[4] |= ((val >> 24) & 0xff);
++	          buf[5] |= ((val >> 16) & 0xff);
++	          buf[6] |= ((val >> 8) & 0xff);
++	          buf[7] |= (val & 0xff);
++	        }
++	      else
++	        {
++	          buf[7] |= ((val >> 56) & 0xff);
++	          buf[6] |= ((val >> 48) & 0xff);
++	          buf[5] |= ((val >> 40) & 0xff);
++	          buf[4] |= ((val >> 32) & 0xff);
++	          buf[3] |= ((val >> 24) & 0xff);
++	          buf[2] |= ((val >> 16) & 0xff);
++	          buf[1] |= ((val >> 8) & 0xff);
++	          buf[0] |= (val & 0xff);
++	        }
++	    }
++	  else {
++	    if (target_big_endian)
++	      {
++	        buf[0] |= ((val >> 24) & 0xff);
++	        buf[1] |= ((val >> 16) & 0xff);
++	        buf[2] |= ((val >> 8) & 0xff);
++	        buf[3] |= (val & 0xff);
++	      }
++	    else
++	      {
++	        buf[3] |= ((val >> 24) & 0xff);
++	        buf[2] |= ((val >> 16) & 0xff);
++	        buf[1] |= ((val >> 8) & 0xff);
++	        buf[0] |= (val & 0xff);
++	      }
++	  }
++	}
++      break;
++    
++    case BFD_RELOC_MICROBLAZE_EA64:
+       /* Don't do anything if the symbol is not defined.  */
+       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ 	{
+ 	  if (target_big_endian)
+ 	    {
+-	      buf[0] |= ((val >> 24) & 0xff);
+-	      buf[1] |= ((val >> 16) & 0xff);
+-	      buf[2] |= ((val >> 8) & 0xff);
+-	      buf[3] |= (val & 0xff);
++	      buf[0] |= ((val >> 56) & 0xff);
++	      buf[1] |= ((val >> 48) & 0xff);
++	      buf[2] |= ((val >> 40) & 0xff);
++	      buf[3] |= ((val >> 32) & 0xff);
++	      buf[4] |= ((val >> 24) & 0xff);
++	      buf[5] |= ((val >> 16) & 0xff);
++	      buf[6] |= ((val >> 8) & 0xff);
++	      buf[7] |= (val & 0xff);
+ 	    }
+ 	  else
+ 	    {
++	      buf[7] |= ((val >> 56) & 0xff);
++	      buf[6] |= ((val >> 48) & 0xff);
++	      buf[5] |= ((val >> 40) & 0xff);
++	      buf[4] |= ((val >> 32) & 0xff);
+ 	      buf[3] |= ((val >> 24) & 0xff);
+ 	      buf[2] |= ((val >> 16) & 0xff);
+ 	      buf[1] |= ((val >> 8) & 0xff);
+@@ -2607,6 +2662,8 @@ md_apply_fix (fixS *   fixP,
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
+       else if (fixP->fx_r_type == BFD_RELOC_32)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
++      else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64)
++        fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64;
+       else
+ 	fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2878,6 +2935,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+     case BFD_RELOC_MICROBLAZE_64_GPC:
++    case BFD_RELOC_MICROBLAZE_EA64:
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+@@ -3023,10 +3081,10 @@ cons_fix_new_microblaze (fragS * frag,
+           r = BFD_RELOC_32;
+           break;
+         case 8:
+-          if (microblaze_arch_size == 64)
++          /*if (microblaze_arch_size == 64)
+             r = BFD_RELOC_32;
+-          else
+-            r = BFD_RELOC_64;
++          else*/
++            r = BFD_RELOC_MICROBLAZE_EA64;
+           break;
+         default:
+           as_bad (_("unsupported BFD relocation size %u"), size);
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index f643f2600d..1dc11a2653 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -77,7 +77,7 @@ static char *
+ get_field_imml (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+-  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Various-fixes.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Various-fixes.patch
deleted file mode 100644
index ad2fd5fe3a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0020-Various-fixes.patch
+++ /dev/null
@@ -1,221 +0,0 @@
-From 1594b2f497822ebdb923b4ae55e81a10bfd4817d Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 9 Oct 2018 10:14:22 +0530
-Subject: [PATCH 20/40] Various fixes
-
-- Fixed address computation issues with 64bit address
-- Fixed imml dissassamble issue
----
- bfd/bfd-in2.h              |  5 +++
- bfd/elf64-microblaze.c     | 14 ++++----
- gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
- opcodes/microblaze-dis.c   |  2 +-
- 4 files changed, 79 insertions(+), 16 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 88f89bcdbcd..8902d9c7939 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5443,6 +5443,11 @@ value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64,
- 
-+/* This is a 64 bit reloc that stores the 32 bit relative
-+value in two words (with an imml instruction).  No relocation is
-+done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_EA64,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index f8f52870639..17e58748a0b 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0,			/* Rightshift.  */
-           4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-           64,			/* Bitsize.  */
--          TRUE,		/* PC_relative.  */
-+          FALSE,		/* PC_relative.  */
-           0,			/* Bitpos.  */
-           complain_overflow_dont, /* Complain on overflow.  */
-           bfd_elf_generic_reloc,/* Special Function.  */
-           "R_MICROBLAZE_IMML_64",   	/* Name.  */
-           FALSE,		/* Partial Inplace.  */
-           0,			/* Source Mask.  */
--          0x0000ffff,		/* Dest Mask.  */
--          TRUE), 		/* PC relative offset?  */
-+          0xffffffffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
- 
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_32:
-       microblaze_reloc = R_MICROBLAZE_32;
-       break;
--      /* RVA is treated the same as 32 */
-+      /* RVA is treated the same as 64 */
-     case BFD_RELOC_RVA:
--      microblaze_reloc = R_MICROBLAZE_32;
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-       break;
-     case BFD_RELOC_32_PCREL:
-       microblaze_reloc = R_MICROBLAZE_32_PCREL;
-@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
--    case BFD_RELOC_MICROBLAZE_64:
-+    case BFD_RELOC_MICROBLAZE_EA64:
-       microblaze_reloc = R_MICROBLAZE_IMML_64;
-       break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-@@ -1956,7 +1956,7 @@ microblaze_elf_relax_section (bfd *abfd,
- 	        efix = calc_fixup (target_address, 0, sec);
- 
-             /* Validate the in-band val.  */
--            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            val = bfd_get_64 (abfd, contents + irel->r_offset);
-             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-             }
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index f61fdf3b90a..0dfb59ffe8b 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -401,7 +401,6 @@ pseudo_typeS md_pseudo_table[] =
-   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
-   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
-   {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
--  {"gpdword", s_rva, 8}, /* gpword label => store resolved label address in data section.  */
-   {"weakext", microblaze_s_weakext, 0},
-   {"rodata", microblaze_s_rdata, 0},
-   {"sdata2", microblaze_s_rdata, 1},
-@@ -2489,18 +2488,74 @@ md_apply_fix (fixS *   fixP,
-     case BFD_RELOC_RVA:
-     case BFD_RELOC_32_PCREL:
-     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
-+      /* Don't do anything if the symbol is not defined.  */
-+      if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+	{
-+	  if ((fixP->fx_r_type == BFD_RELOC_RVA) && (microblaze_arch_size == 64))
-+            {
-+	      if (target_big_endian)
-+	        {
-+	          buf[0] |= ((val >> 56) & 0xff);
-+	          buf[1] |= ((val >> 48) & 0xff);
-+	          buf[2] |= ((val >> 40) & 0xff);
-+	          buf[3] |= ((val >> 32) & 0xff);
-+	          buf[4] |= ((val >> 24) & 0xff);
-+	          buf[5] |= ((val >> 16) & 0xff);
-+	          buf[6] |= ((val >> 8) & 0xff);
-+	          buf[7] |= (val & 0xff);
-+	        }
-+	      else
-+	        {
-+	          buf[7] |= ((val >> 56) & 0xff);
-+	          buf[6] |= ((val >> 48) & 0xff);
-+	          buf[5] |= ((val >> 40) & 0xff);
-+	          buf[4] |= ((val >> 32) & 0xff);
-+	          buf[3] |= ((val >> 24) & 0xff);
-+	          buf[2] |= ((val >> 16) & 0xff);
-+	          buf[1] |= ((val >> 8) & 0xff);
-+	          buf[0] |= (val & 0xff);
-+	        }
-+	    }
-+	  else {
-+	    if (target_big_endian)
-+	      {
-+	        buf[0] |= ((val >> 24) & 0xff);
-+	        buf[1] |= ((val >> 16) & 0xff);
-+	        buf[2] |= ((val >> 8) & 0xff);
-+	        buf[3] |= (val & 0xff);
-+	      }
-+	    else
-+	      {
-+	        buf[3] |= ((val >> 24) & 0xff);
-+	        buf[2] |= ((val >> 16) & 0xff);
-+	        buf[1] |= ((val >> 8) & 0xff);
-+	        buf[0] |= (val & 0xff);
-+	      }
-+	  }
-+	}
-+      break;
-+
-+    case BFD_RELOC_MICROBLAZE_EA64:
-       /* Don't do anything if the symbol is not defined.  */
-       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- 	{
- 	  if (target_big_endian)
- 	    {
--	      buf[0] |= ((val >> 24) & 0xff);
--	      buf[1] |= ((val >> 16) & 0xff);
--	      buf[2] |= ((val >> 8) & 0xff);
--	      buf[3] |= (val & 0xff);
-+	      buf[0] |= ((val >> 56) & 0xff);
-+	      buf[1] |= ((val >> 48) & 0xff);
-+	      buf[2] |= ((val >> 40) & 0xff);
-+	      buf[3] |= ((val >> 32) & 0xff);
-+	      buf[4] |= ((val >> 24) & 0xff);
-+	      buf[5] |= ((val >> 16) & 0xff);
-+	      buf[6] |= ((val >> 8) & 0xff);
-+	      buf[7] |= (val & 0xff);
- 	    }
- 	  else
- 	    {
-+	      buf[7] |= ((val >> 56) & 0xff);
-+	      buf[6] |= ((val >> 48) & 0xff);
-+	      buf[5] |= ((val >> 40) & 0xff);
-+	      buf[4] |= ((val >> 32) & 0xff);
- 	      buf[3] |= ((val >> 24) & 0xff);
- 	      buf[2] |= ((val >> 16) & 0xff);
- 	      buf[1] |= ((val >> 8) & 0xff);
-@@ -2621,6 +2676,8 @@ md_apply_fix (fixS *   fixP,
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
-       else if (fixP->fx_r_type == BFD_RELOC_32)
- 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
-+      else if(fixP->fx_r_type == BFD_RELOC_MICROBLAZE_EA64)
-+	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_EA64;
-       else
- 	fixP->fx_r_type = BFD_RELOC_NONE;
-       fixP->fx_addsy = section_symbol (absolute_section);
-@@ -2892,6 +2949,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
-     case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-     case BFD_RELOC_MICROBLAZE_64_GPC:
-+    case BFD_RELOC_MICROBLAZE_EA64:
-     case BFD_RELOC_MICROBLAZE_64:
-     case BFD_RELOC_MICROBLAZE_64_PCREL:
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-@@ -3037,10 +3095,10 @@ cons_fix_new_microblaze (fragS * frag,
-           r = BFD_RELOC_32;
-           break;
-         case 8:
--          if (microblaze_arch_size == 64)
-+          /*if (microblaze_arch_size == 64)
-             r = BFD_RELOC_32;
--          else
--            r = BFD_RELOC_64;
-+          else*/
-+            r = BFD_RELOC_MICROBLAZE_EA64;
-           break;
-         default:
-           as_bad (_("unsupported BFD relocation size %u"), size);
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index a03f5b7a55b..fc8e79b19cf 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -78,7 +78,7 @@ get_field_imml (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
--  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
-+  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
-   return p;
- }
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0021-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0021-Adding-new-relocation-to-support-64bit-rodata.patch
index 99f285f268..908f757276 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0021-Adding-new-relocation-to-support-64bit-rodata.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0021-Adding-new-relocation-to-support-64bit-rodata.patch
@@ -1,7 +1,7 @@
-From b33fdfda4af069859ebe6588a5b9774cb5a2f14d Mon Sep 17 00:00:00 2001
+From 9880b06269a176c0b5c4f0ecb9e3784f630a76be Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Sat, 13 Oct 2018 21:17:01 +0530
-Subject: [PATCH 21/40] Adding new relocation to support 64bit rodata
+Subject: [PATCH 21/52] Adding new relocation to support 64bit rodata
 
 ---
  bfd/elf64-microblaze.c     | 11 +++++++--
@@ -9,10 +9,10 @@ Subject: [PATCH 21/40] Adding new relocation to support 64bit rodata
  2 files changed, 54 insertions(+), 6 deletions(-)
 
 diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 17e58748a0b..b62c47e8514 100644
+index f42d7f429b..ddcb5baf74 100644
 --- a/bfd/elf64-microblaze.c
 +++ b/bfd/elf64-microblaze.c
-@@ -1463,6 +1463,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1473,6 +1473,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  	    case (int) R_MICROBLAZE_64_PCREL :
  	    case (int) R_MICROBLAZE_64:
  	    case (int) R_MICROBLAZE_32:
@@ -20,16 +20,16 @@ index 17e58748a0b..b62c47e8514 100644
  	      {
  		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
  		   from removed linkonce sections, or sections discarded by
-@@ -1472,6 +1473,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1482,6 +1483,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  		    relocation += addend;
- 		    if (r_type == R_MICROBLAZE_32)
+ 		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
  		      bfd_put_32 (input_bfd, relocation, contents + offset);
 +		    else if (r_type == R_MICROBLAZE_IMML_64)
 +		      bfd_put_64 (input_bfd, relocation, contents + offset);
  		    else
  		      {
  			if (r_type == R_MICROBLAZE_64_PCREL)
-@@ -1549,7 +1552,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1560,7 +1563,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  		      }
  		    else
  		      {
@@ -38,7 +38,7 @@ index 17e58748a0b..b62c47e8514 100644
  			  {
  			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
  			    outrel.r_addend = relocation + addend;
-@@ -1575,6 +1578,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1586,6 +1589,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  		    relocation += addend;
  		    if (r_type == R_MICROBLAZE_32)
  		      bfd_put_32 (input_bfd, relocation, contents + offset);
@@ -47,7 +47,7 @@ index 17e58748a0b..b62c47e8514 100644
  		    else
  		      {
  			if (r_type == R_MICROBLAZE_64_PCREL)
-@@ -2072,7 +2077,8 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2098,7 +2103,8 @@ microblaze_elf_relax_section (bfd *abfd,
                    microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
                                                       irelscan->r_addend);
                }
@@ -57,7 +57,7 @@ index 17e58748a0b..b62c47e8514 100644
                  {
  	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
  
-@@ -2568,6 +2574,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+@@ -2606,6 +2612,7 @@ microblaze_elf_check_relocs (bfd * abfd,
          case R_MICROBLAZE_64:
          case R_MICROBLAZE_64_PCREL:
          case R_MICROBLAZE_32:
@@ -66,10 +66,10 @@ index 17e58748a0b..b62c47e8514 100644
              if (h != NULL && !bfd_link_pic (info))
  	      {
 diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 0dfb59ffe8b..4bd71557ca2 100644
+index bfb3104720..532a26eaa5 100644
 --- a/gas/config/tc-microblaze.c
 +++ b/gas/config/tc-microblaze.c
-@@ -1133,6 +1133,13 @@ md_assemble (char * str)
+@@ -1119,6 +1119,13 @@ md_assemble (char * str)
  	    as_fatal (_("smi pseudo instruction should not use a label in imm field"));
            if(streq (name, "lli") || streq (name, "sli"))
              opc = str_microblaze_64;
@@ -83,7 +83,7 @@ index 0dfb59ffe8b..4bd71557ca2 100644
  	  else if (reg2 == REG_ROSDP)
  	    opc = str_microblaze_ro_anchor;
  	  else if (reg2 == REG_RWSDP)
-@@ -1196,7 +1203,10 @@ md_assemble (char * str)
+@@ -1182,7 +1189,10 @@ md_assemble (char * str)
                inst |= (immed << IMM_LOW) & IMM_MASK;
              }
  	}
@@ -95,19 +95,19 @@ index 0dfb59ffe8b..4bd71557ca2 100644
          {
            temp = immed & 0xFFFFFF8000;
            if (temp != 0 && temp != 0xFFFFFF8000)
-@@ -1808,6 +1818,11 @@ md_assemble (char * str)
+@@ -1794,6 +1804,11 @@ md_assemble (char * str)
  
  	  if (exp.X_md != 0)
  	    subtype = get_imm_otype(exp.X_md);
 +          else if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
 +            {
-+              opc = strdup(str_microblaze_64);
++              opc = str_microblaze_64;
 +	      subtype = opcode->inst_offset_type;
 +	    }
  	  else
  	    subtype = opcode->inst_offset_type;
  
-@@ -1825,6 +1840,31 @@ md_assemble (char * str)
+@@ -1811,6 +1826,31 @@ md_assemble (char * str)
            output = frag_more (isize);
            immed = exp.X_add_number;
          }
@@ -139,7 +139,7 @@ index 0dfb59ffe8b..4bd71557ca2 100644
  
        temp = immed & 0xFFFF8000;
        if ((temp != 0) && (temp != 0xFFFF8000))
-@@ -1848,6 +1888,7 @@ md_assemble (char * str)
+@@ -1834,6 +1874,7 @@ md_assemble (char * str)
  
        inst |= (reg1 << RD_LOW) & RD_MASK;
        inst |= (immed << IMM_LOW) & IMM_MASK;
@@ -147,7 +147,7 @@ index 0dfb59ffe8b..4bd71557ca2 100644
        break;
  
      case INST_TYPE_R2:
-@@ -3095,10 +3136,10 @@ cons_fix_new_microblaze (fragS * frag,
+@@ -3081,10 +3122,10 @@ cons_fix_new_microblaze (fragS * frag,
            r = BFD_RELOC_32;
            break;
          case 8:
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0022-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0022-fixing-the-.bss-relocation-issue.patch
index 48b89d64e3..6c144b8ad3 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0022-fixing-the-.bss-relocation-issue.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0022-fixing-the-.bss-relocation-issue.patch
@@ -1,35 +1,35 @@
-From 118e1717ef8421bc86bcf56c9186f065bd607efd Mon Sep 17 00:00:00 2001
+From e7b6ab1b28fc3ca13ed25687d5e851795ed6e1a3 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 24 Oct 2018 12:34:37 +0530
-Subject: [PATCH 22/40] fixing the .bss relocation issue
+Subject: [PATCH 22/52] fixing the .bss relocation issue
 
 ---
  bfd/elf64-microblaze.c | 18 ++++++++++++------
  1 file changed, 12 insertions(+), 6 deletions(-)
 
 diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index b62c47e8514..cb3b40b574c 100644
+index ddcb5baf74..861420789b 100644
 --- a/bfd/elf64-microblaze.c
 +++ b/bfd/elf64-microblaze.c
-@@ -1482,7 +1482,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1492,7 +1492,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  					 + input_section->output_offset
  					 + offset + INST_WORD_SIZE);
  			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
--			if (insn == 0xb2000000 || insn == 0xb2ffffff)
+-    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
 +			if ((insn & 0xff000000) == 0xb2000000)
  			  {
- 			    insn &= ~0x00ffffff;
+         		    insn &= ~0x00ffffff;
  			    insn |= (relocation >> 16) & 0xffffff;
-@@ -1595,7 +1595,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1606,7 +1606,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
  					     + offset + INST_WORD_SIZE);
  			  }
  			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
--			if (insn == 0xb2000000 || insn == 0xb2ffffff)
+-    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
 +			if ((insn & 0xff000000) == 0xb2000000)
  			  {
- 			    insn &= ~0x00ffffff;
+         		    insn &= ~0x00ffffff;
  			    insn |= (relocation >> 16) & 0xffffff;
-@@ -1709,7 +1709,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+@@ -1735,7 +1735,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
  {
      unsigned long instr = bfd_get_32 (abfd, bfd_addr);
  
@@ -38,7 +38,7 @@ index b62c47e8514..cb3b40b574c 100644
        {
          instr &= ~0x00ffffff;
          instr |= (val & 0xffffff);
-@@ -1732,7 +1732,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+@@ -1758,7 +1758,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
      unsigned long instr_lo;
  
      instr_hi = bfd_get_32 (abfd, bfd_addr);
@@ -47,7 +47,7 @@ index b62c47e8514..cb3b40b574c 100644
        {
          instr_hi &= ~0x00ffffff;
          instr_hi |= (val >> 16) & 0xffffff;
-@@ -2225,7 +2225,10 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2251,7 +2251,10 @@ microblaze_elf_relax_section (bfd *abfd,
            unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
                                                  + irelscan->r_offset
                                                  + INST_WORD_SIZE);
@@ -59,7 +59,7 @@ index b62c47e8514..cb3b40b574c 100644
            immediate |= (instr_lo & 0x0000ffff);
  		      offset = calc_fixup (irelscan->r_addend, 0, sec);
  		      immediate -= offset;
-@@ -2269,7 +2272,10 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2295,7 +2298,10 @@ microblaze_elf_relax_section (bfd *abfd,
            unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
                                                  + irelscan->r_offset
                                                  + INST_WORD_SIZE);
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
index c84767fa00..98f05ac828 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
@@ -1,7 +1,7 @@
-From 04d4e164cec91078b1b1155bae6ae4b508758969 Mon Sep 17 00:00:00 2001
+From 9b9f53c95e5b1fbccd4de2dd579c6cfae34c191d Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 28 Nov 2018 14:00:29 +0530
-Subject: [PATCH 23/40] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
+Subject: [PATCH 23/52] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
  It was adjusting only lower 16bits.
 
 ---
@@ -10,7 +10,7 @@ Subject: [PATCH 23/40] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
  2 files changed, 4 insertions(+), 4 deletions(-)
 
 diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index e1a66f57e79..bf09c68afd9 100644
+index 14bb6de052..d77710b1f3 100644
 --- a/bfd/elf32-microblaze.c
 +++ b/bfd/elf32-microblaze.c
 @@ -2019,8 +2019,8 @@ microblaze_elf_relax_section (bfd *abfd,
@@ -25,10 +25,10 @@ index e1a66f57e79..bf09c68afd9 100644
  	      break;
  	    }
 diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index cb3b40b574c..b002b414d64 100644
+index 861420789b..338f16eeee 100644
 --- a/bfd/elf64-microblaze.c
 +++ b/bfd/elf64-microblaze.c
-@@ -2004,8 +2004,8 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2030,8 +2030,8 @@ microblaze_elf_relax_section (bfd *abfd,
  		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
  		efix = calc_fixup (target_address, 0, sec);
  		irel->r_addend -= (efix - sfix);
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0024-Revert-ld-Remove-unused-expression-state.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0024-Revert-ld-Remove-unused-expression-state.patch
index 9a8e799c6f..25d0d7eb1f 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0024-Revert-ld-Remove-unused-expression-state.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0024-Revert-ld-Remove-unused-expression-state.patch
@@ -1,7 +1,7 @@
-From 7d26e7f32769e1a324a8dfd3bc3eaa2a5fbfe62a Mon Sep 17 00:00:00 2001
+From 70fcc4fe0635bdc871bc2ec1087173e3f93cab86 Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 27 Feb 2019 15:12:32 +0530
-Subject: [PATCH 24/40] Revert "ld: Remove unused expression state"
+Subject: [PATCH 24/52] Revert "ld: Remove unused expression state"
 
 This reverts commit 65f14869fd3fbee8ed4c4ca49de8aaa86dbc66cb.
 
@@ -13,7 +13,7 @@ Conflicts:
  2 files changed, 6 insertions(+), 3 deletions(-)
 
 diff --git a/ld/ldexp.c b/ld/ldexp.c
-index b4e7c41209d..dd3b058110a 100644
+index b4e7c41209..dd3b058110 100644
 --- a/ld/ldexp.c
 +++ b/ld/ldexp.c
 @@ -1360,6 +1360,7 @@ static etree_type *
@@ -60,7 +60,7 @@ index b4e7c41209d..dd3b058110a 100644
  
  /* Handle ASSERT.  */
 diff --git a/ld/ldexp.h b/ld/ldexp.h
-index 717e839bd41..852ac6c5889 100644
+index 717e839bd4..852ac6c588 100644
 --- a/ld/ldexp.h
 +++ b/ld/ldexp.h
 @@ -66,6 +66,7 @@ typedef union etree_union {
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
deleted file mode 100644
index 97d75650f1..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 8293b0cf15d4411402a2b0b50e4c532093c5d952 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 11 Mar 2019 14:23:58 +0530
-Subject: [PATCH 25/40] [Patch,Microblaze] : Binutils security check is causing
- build error for windows builds.commenting for now.
-
----
- bfd/elf-attrs.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c
-index 070104c2734..8331c8759d5 100644
---- a/bfd/elf-attrs.c
-+++ b/bfd/elf-attrs.c
-@@ -442,6 +442,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
-   if (hdr->sh_size == 0)
-     return;
- 
-+  #if 0
-   filesize = bfd_get_file_size (abfd);
-   if (filesize != 0 && hdr->sh_size > filesize)
-     {
-@@ -451,6 +452,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
-       bfd_set_error (bfd_error_invalid_operation);
-       return;
-     }
-+  #endif
- 
-   contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
-   if (!contents)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 0000000000..9d1b17941f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,57 @@
+From 49fdaa5a4f0ed7e20b82ccb8d0db53075777abe9 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:59:25 +0530
+Subject: [PATCH 25/52] fixing the long & long long mingw toolchain issue
+
+---
+ gas/config/tc-microblaze.c | 10 +++++-----
+ opcodes/microblaze-opc.h   |  4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 532a26eaa5..b00b759893 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -783,7 +783,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
+ }
+ 
+  static char *
+-parse_imml (char * s, expressionS * e, long min, long max)
++parse_imml (char * s, expressionS * e, long long min, long long max)
+ {
+   char *new_pointer;
+   char *atp;
+@@ -834,11 +834,11 @@ parse_imml (char * s, expressionS * e, long min, long max)
+     ; /* An error message has already been emitted.  */
+   else if ((e->X_op != O_constant && e->X_op != O_symbol) )
+     as_fatal (_("operand must be a constant or a label"));
+-  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
+-				       || (long) e->X_add_number > max))
++  else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min
++				       || (long long) e->X_add_number > max))
+     {
+-      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
+-                min, max, (long) e->X_add_number);
++      as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"),
++                min, max, (long long) e->X_add_number);
+     }
+ 
+   if (atp)
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index f970941209..77d74c17f3 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) 0xffffff8000000000L)
++#define MAX_IMML  ((long long) 0x0000007fffffffffL)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 0000000000..6379a5c41b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,364 @@
+From b29e6a15c9f65837dbb560aa6c41c49e591915e9 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 26/52] Added support to new arithmetic single register
+ instructions
+
+Conflicts:
+	opcodes/microblaze-dis.c
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   |  13 +++-
+ opcodes/microblaze-opc.h   |  43 ++++++++++-
+ opcodes/microblaze-opcm.h  |   5 +-
+ 4 files changed, 201 insertions(+), 7 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index b00b759893..eca060b262 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -423,12 +423,33 @@ void
+ md_begin (void)
+ {
+   struct op_code_struct * opcode;
++  const char *prev_name = "";
+ 
+   opcode_hash_control = hash_new ();
+ 
+   /* Insert unique names into hash table.  */
+-  for (opcode = opcodes; opcode->name; opcode ++)
+-    hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++  for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++)
++    {
++      if (strcmp (prev_name, opcode->name))
++	{
++	  prev_name = (char *) opcode->name;
++          hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
++        }
++    }
++}
++
++static int
++is_reg (char * s)
++{
++  int is_reg = 0; 
++  /* Strip leading whitespace.  */
++  while (ISSPACE (* s))
++    ++ s;
++  if (TOLOWER (s[0]) == 'r')
++    {
++	 is_reg =1;
++    }
++  return is_reg;
+ }
+ 
+ /* Try to parse a reg name.  */
+@@ -986,6 +1007,7 @@ md_assemble (char * str)
+ {
+   char * op_start;
+   char * op_end;
++  char * temp_op_end;
+   struct op_code_struct * opcode, *opcode1;
+   char * output = NULL;
+   int nlen = 0;
+@@ -996,9 +1018,10 @@ md_assemble (char * str)
+   unsigned reg3;
+   unsigned isize;
+   unsigned long immed, immed2, temp;
+-  expressionS exp;
++  expressionS exp,exp1;
+   char name[20];
+   long immedl;
++  int reg=0;
+ 
+   /* Drop leading whitespace.  */
+   while (ISSPACE (* str))
+@@ -1029,7 +1052,78 @@ md_assemble (char * str)
+       as_bad (_("unknown opcode \"%s\""), name);
+       return;
+     }
+-
++   
++  if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
++        streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli") 
++	|| streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc") 
++	|| streq (name, "andli") || streq (name, "andnli") || streq (name, "orli") 
++	|| streq (name, "xorli")))
++    {
++      temp_op_end = op_end;
++      if (strcmp (temp_op_end, ""))
++        temp_op_end = parse_reg (temp_op_end + 1, &reg1);  /* Get rd.  */
++      if (strcmp (temp_op_end, ""))
++        reg  = is_reg (temp_op_end + 1);
++      if (reg) 
++	{
++          
++ 	  opcode->inst_type=INST_TYPE_RD_R1_IMML;
++          opcode->inst_offset_type = OPCODE_MASK_H;
++          if (streq (name, "addli"))
++ 	    opcode->bit_sequence = ADDLI_MASK;
++          else if (streq (name, "addlic"))
++ 	    opcode->bit_sequence = ADDLIC_MASK;
++          else if (streq (name, "addlik"))
++ 	    opcode->bit_sequence = ADDLIK_MASK;
++          else if (streq (name, "addlikc"))
++ 	    opcode->bit_sequence = ADDLIKC_MASK;
++          else if (streq (name, "rsubli"))
++ 	    opcode->bit_sequence = RSUBLI_MASK;
++          else if (streq (name, "rsublic"))
++ 	    opcode->bit_sequence = RSUBLIC_MASK;
++          else if (streq (name, "rsublik"))
++ 	    opcode->bit_sequence = RSUBLIK_MASK;
++          else if (streq (name, "rsublikc"))
++ 	    opcode->bit_sequence = RSUBLIKC_MASK;
++          else if (streq (name, "andli"))
++ 	    opcode->bit_sequence = ANDLI_MASK;
++          else if (streq (name, "andnli"))
++ 	    opcode->bit_sequence = ANDLNI_MASK;
++          else if (streq (name, "orli"))
++ 	    opcode->bit_sequence = ORLI_MASK;
++          else if (streq (name, "xorli"))
++ 	    opcode->bit_sequence = XORLI_MASK;
++	}
++      else
++        {
++	  opcode->inst_type=INST_TYPE_RD_IMML;
++          opcode->inst_offset_type = OPCODE_MASK_LIMM;
++          if (streq (name, "addli"))
++ 	    opcode->bit_sequence = ADDLI_ONE_REG_MASK;
++          else if (streq (name, "addlic"))
++ 	    opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
++          else if (streq (name, "addlik"))
++ 	    opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
++          else if (streq (name, "addlikc"))
++ 	    opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
++          else if (streq (name, "rsubli"))
++ 	    opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
++          else if (streq (name, "rsublic"))
++ 	    opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
++          else if (streq (name, "rsublik"))
++ 	    opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
++          else if (streq (name, "rsublikc"))
++ 	    opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
++          else if (streq (name, "andli"))
++ 	    opcode->bit_sequence = ANDLI_ONE_REG_MASK;
++          else if (streq (name, "andnli"))
++ 	    opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
++          else if (streq (name, "orli"))
++ 	    opcode->bit_sequence = ORLI_ONE_REG_MASK;
++          else if (streq (name, "xorli"))
++ 	    opcode->bit_sequence = XORLI_ONE_REG_MASK;
++        }
++    }
+   inst = opcode->bit_sequence;
+   isize = 4;
+ 
+@@ -1480,6 +1574,51 @@ md_assemble (char * str)
+       inst |= (immed << IMM_LOW) & IMM15_MASK;
+       break;
+ 
++    case INST_TYPE_RD_IMML:
++      if (strcmp (op_end, ""))
++        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++        {
++          as_fatal (_("Error in statement syntax"));
++          reg1 = 0;
++        }
++
++      if (strcmp (op_end, ""))
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++      else
++        as_fatal (_("Error in statement syntax"));
++
++      /* Check for spl registers. */
++      if (check_spl_reg (&reg1))
++        as_fatal (_("Cannot use special register with this instruction"));
++      if (exp.X_op != O_constant)
++	{
++          char *opc = NULL;
++          relax_substateT subtype;
++
++          if (exp.X_md != 0)
++            subtype = get_imm_otype(exp.X_md);
++          else
++            subtype = opcode->inst_offset_type;
++
++          output = frag_var (rs_machine_dependent,
++                             isize * 2, 
++                             isize * 2,
++                             subtype,   
++                             exp.X_add_symbol,
++                             exp.X_add_number,
++                             (char *) opc);
++          immedl = 0L;
++	}		
++      else
++        {
++          output = frag_more (isize);
++          immed = exp.X_add_number;
++        }
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (immed << IMM_LOW) & IMM16_MASK;
++      break;
++	
+     case INST_TYPE_R1_RFSL:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 1dc11a2653..90d2328659 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -130,9 +130,17 @@ get_field_imm15 (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++get_field_imm16 (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++  return p;
++}
++
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+-		   struct op_code_struct *op)
++                   struct op_code_struct *op)
+ {
+   char *p = strbuf (buf);
+   char *spr;
+@@ -456,6 +464,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
++	case INST_TYPE_RD_IMML:
++	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++          break;
+         /* For bit field insns.  */
+ 	case INST_TYPE_RD_R1_IMMW_IMMS:
+           print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 77d74c17f3..c1b453c95e 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -69,6 +69,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+ 
+ 
+ 
+@@ -84,6 +85,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+ #define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
+ #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
+ #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
+@@ -106,6 +108,33 @@
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ #define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
+ 
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+ /* Mask for mbar insn.  */
+@@ -114,7 +143,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+ 
+ struct op_code_struct
+ {
+@@ -444,13 +473,21 @@ struct op_code_struct
+   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -501,9 +538,13 @@ struct op_code_struct
+   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index fcf259a362..eca247c63b 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -61,7 +61,9 @@ enum microblaze_instr
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+ 
+   /* 64-bit instructions */
+-  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  andli, andnli, orli, xorli,
+   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -166,5 +168,6 @@ enum microblaze_instr_type
+ 
+ /* Imm mask for msrset, msrclr instructions.  */
+ #define  IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+ 
+ #endif /* MICROBLAZE-OPCM */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
deleted file mode 100644
index ebd1fa4cba..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 987bd08638fab099dcfdce412448734182be51e6 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 29 Nov 2018 17:59:25 +0530
-Subject: [PATCH 26/40] fixing the long & long long mingw toolchain issue
-
----
- gas/config/tc-microblaze.c | 10 +++++-----
- opcodes/microblaze-opc.h   |  4 ++--
- 2 files changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 4bd71557ca2..83e17c60fa0 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -797,7 +797,7 @@ parse_imm (char * s, expressionS * e, offsetT min, offsetT max)
- }
- 
-  static char *
--parse_imml (char * s, expressionS * e, long min, long max)
-+parse_imml (char * s, expressionS * e, long long min, long long max)
- {
-   char *new_pointer;
-   char *atp;
-@@ -848,11 +848,11 @@ parse_imml (char * s, expressionS * e, long min, long max)
-     ; /* An error message has already been emitted.  */
-   else if ((e->X_op != O_constant && e->X_op != O_symbol) )
-     as_fatal (_("operand must be a constant or a label"));
--  else if ((e->X_op == O_constant) && ((long) e->X_add_number < min
--				       || (long) e->X_add_number > max))
-+  else if ((e->X_op == O_constant) && ((long long) e->X_add_number < min
-+				       || (long long) e->X_add_number > max))
-     {
--      as_fatal (_("operand must be absolute in range %ld..%ld, not %ld"),
--                min, max, (long) e->X_add_number);
-+      as_fatal (_("operand must be absolute in range %lld..%lld, not %lld"),
-+                min, max, (long long) e->X_add_number);
-     }
- 
-   if (atp)
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index f9709412097..77d74c17f3a 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM6_WIDTH  ((int) 0x00000001)
- #define MAX_IMM6_WIDTH  ((int) 0x00000040)
- 
--#define MIN_IMML  ((long) 0xffffff8000000000L)
--#define MAX_IMML  ((long) 0x0000007fffffffffL)
-+#define MIN_IMML  ((long long) 0xffffff8000000000L)
-+#define MAX_IMML  ((long long) 0x0000007fffffffffL)
- 
- #endif /* MICROBLAZE_OPC */
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Added-support-to-new-arithmetic-single-register-inst.patch
deleted file mode 100644
index 12f44a6dd4..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Added-support-to-new-arithmetic-single-register-inst.patch
+++ /dev/null
@@ -1,370 +0,0 @@
-From dde3395588ca91a7c484cc4a003f72f80848c534 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Fri, 23 Aug 2019 16:18:43 +0530
-Subject: [PATCH 27/40] Added support to new arithmetic single register
- instructions
-
----
- gas/config/tc-microblaze.c | 145 ++++++++++++++++++++++++++++++++++++-
- opcodes/microblaze-dis.c   |  13 +++-
- opcodes/microblaze-opc.h   |  45 +++++++++++-
- opcodes/microblaze-opcm.h  |   5 +-
- 4 files changed, 201 insertions(+), 7 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 83e17c60fa0..b4330652758 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -422,12 +422,33 @@ void
- md_begin (void)
- {
-   struct op_code_struct * opcode;
-+  const char *prev_name = "";
- 
-   opcode_hash_control = hash_new ();
- 
-   /* Insert unique names into hash table.  */
--  for (opcode = opcodes; opcode->name; opcode ++)
--    hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
-+  for (opcode = (struct op_code_struct *)opcodes; opcode->name; opcode ++)
-+    {
-+      if (strcmp (prev_name, opcode->name))
-+	{
-+	  prev_name = (char *) opcode->name;
-+          hash_insert (opcode_hash_control, opcode->name, (char *) opcode);
-+        }
-+    }
-+}
-+
-+static int
-+is_reg (char * s)
-+{
-+  int is_reg = 0; 
-+  /* Strip leading whitespace.  */
-+  while (ISSPACE (* s))
-+    ++ s;
-+  if (TOLOWER (s[0]) == 'r')
-+    {
-+	 is_reg =1;
-+    }
-+  return is_reg;
- }
- 
- /* Try to parse a reg name.  */
-@@ -1000,6 +1021,7 @@ md_assemble (char * str)
- {
-   char * op_start;
-   char * op_end;
-+  char * temp_op_end;
-   struct op_code_struct * opcode, *opcode1;
-   char * output = NULL;
-   int nlen = 0;
-@@ -1013,6 +1035,7 @@ md_assemble (char * str)
-   expressionS exp;
-   char name[20];
-   long immedl;
-+  int reg=0;
- 
-   /* Drop leading whitespace.  */
-   while (ISSPACE (* str))
-@@ -1043,7 +1066,78 @@ md_assemble (char * str)
-       as_bad (_("unknown opcode \"%s\""), name);
-       return;
-     }
--
-+   
-+  if ((microblaze_arch_size == 64) && (streq (name, "addli") || streq (name, "addlic") ||
-+        streq (name, "addlik") || streq (name, "addlikc") || streq (name, "rsubli") 
-+	|| streq (name, "rsublic") || streq (name, "rsublik") || streq (name, "rsublikc") 
-+	|| streq (name, "andli") || streq (name, "andnli") || streq (name, "orli") 
-+	|| streq (name, "xorli")))
-+    {
-+      temp_op_end = op_end;
-+      if (strcmp (temp_op_end, ""))
-+        temp_op_end = parse_reg (temp_op_end + 1, &reg1);  /* Get rd.  */
-+      if (strcmp (temp_op_end, ""))
-+        reg  = is_reg (temp_op_end + 1);
-+      if (reg) 
-+	{
-+          
-+ 	  opcode->inst_type=INST_TYPE_RD_R1_IMML;
-+          opcode->inst_offset_type = OPCODE_MASK_H;
-+          if (streq (name, "addli"))
-+ 	    opcode->bit_sequence = ADDLI_MASK;
-+          else if (streq (name, "addlic"))
-+ 	    opcode->bit_sequence = ADDLIC_MASK;
-+          else if (streq (name, "addlik"))
-+ 	    opcode->bit_sequence = ADDLIK_MASK;
-+          else if (streq (name, "addlikc"))
-+ 	    opcode->bit_sequence = ADDLIKC_MASK;
-+          else if (streq (name, "rsubli"))
-+ 	    opcode->bit_sequence = RSUBLI_MASK;
-+          else if (streq (name, "rsublic"))
-+ 	    opcode->bit_sequence = RSUBLIC_MASK;
-+          else if (streq (name, "rsublik"))
-+ 	    opcode->bit_sequence = RSUBLIK_MASK;
-+          else if (streq (name, "rsublikc"))
-+ 	    opcode->bit_sequence = RSUBLIKC_MASK;
-+          else if (streq (name, "andli"))
-+ 	    opcode->bit_sequence = ANDLI_MASK;
-+          else if (streq (name, "andnli"))
-+ 	    opcode->bit_sequence = ANDLNI_MASK;
-+          else if (streq (name, "orli"))
-+ 	    opcode->bit_sequence = ORLI_MASK;
-+          else if (streq (name, "xorli"))
-+ 	    opcode->bit_sequence = XORLI_MASK;
-+	}
-+      else
-+        {
-+	  opcode->inst_type=INST_TYPE_RD_IMML;
-+          opcode->inst_offset_type = OPCODE_MASK_LIMM;
-+          if (streq (name, "addli"))
-+ 	    opcode->bit_sequence = ADDLI_ONE_REG_MASK;
-+          else if (streq (name, "addlic"))
-+ 	    opcode->bit_sequence = ADDLIC_ONE_REG_MASK;
-+          else if (streq (name, "addlik"))
-+ 	    opcode->bit_sequence = ADDLIK_ONE_REG_MASK;
-+          else if (streq (name, "addlikc"))
-+ 	    opcode->bit_sequence = ADDLIKC_ONE_REG_MASK;
-+          else if (streq (name, "rsubli"))
-+ 	    opcode->bit_sequence = RSUBLI_ONE_REG_MASK;
-+          else if (streq (name, "rsublic"))
-+ 	    opcode->bit_sequence = RSUBLIC_ONE_REG_MASK;
-+          else if (streq (name, "rsublik"))
-+ 	    opcode->bit_sequence = RSUBLIK_ONE_REG_MASK;
-+          else if (streq (name, "rsublikc"))
-+ 	    opcode->bit_sequence = RSUBLIKC_ONE_REG_MASK;
-+          else if (streq (name, "andli"))
-+ 	    opcode->bit_sequence = ANDLI_ONE_REG_MASK;
-+          else if (streq (name, "andnli"))
-+ 	    opcode->bit_sequence = ANDLNI_ONE_REG_MASK;
-+          else if (streq (name, "orli"))
-+ 	    opcode->bit_sequence = ORLI_ONE_REG_MASK;
-+          else if (streq (name, "xorli"))
-+ 	    opcode->bit_sequence = XORLI_ONE_REG_MASK;
-+        }
-+    }
-   inst = opcode->bit_sequence;
-   isize = 4;
- 
-@@ -1494,6 +1588,51 @@ md_assemble (char * str)
-       inst |= (immed << IMM_LOW) & IMM15_MASK;
-       break;
- 
-+    case INST_TYPE_RD_IMML:
-+      if (strcmp (op_end, ""))
-+        op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
-+      else
-+        {
-+          as_fatal (_("Error in statement syntax"));
-+          reg1 = 0;
-+        }
-+
-+      if (strcmp (op_end, ""))
-+        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-+      else
-+        as_fatal (_("Error in statement syntax"));
-+
-+      /* Check for spl registers. */
-+      if (check_spl_reg (&reg1))
-+        as_fatal (_("Cannot use special register with this instruction"));
-+      if (exp.X_op != O_constant)
-+	{
-+          char *opc = NULL;
-+          relax_substateT subtype;
-+
-+          if (exp.X_md != 0)
-+            subtype = get_imm_otype(exp.X_md);
-+          else
-+            subtype = opcode->inst_offset_type;
-+
-+          output = frag_var (rs_machine_dependent,
-+                             isize * 2, 
-+                             isize * 2,
-+                             subtype,   
-+                             exp.X_add_symbol,
-+                             exp.X_add_number,
-+                             (char *) opc);
-+          immedl = 0L;
-+	}		
-+      else
-+        {
-+          output = frag_more (isize);
-+          immed = exp.X_add_number;
-+        }
-+      inst |= (reg1 << RD_LOW) & RD_MASK;
-+      inst |= (immed << IMM_LOW) & IMM16_MASK;
-+      break;
-+	
-     case INST_TYPE_R1_RFSL:
-       if (strcmp (op_end, ""))
-         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index fc8e79b19cf..f5db1189240 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -131,6 +131,15 @@ get_field_imm15 (struct string_buf *buf, long instr)
-   return p;
- }
- 
-+static char *
-+get_field_imm16 (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
-+  return p;
-+}
-+
- static char *
- get_field_special (struct string_buf *buf, long instr,
- 		   struct op_code_struct *op)
-@@ -450,6 +459,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
- 		      get_field_imm15 (&buf, inst));
- 	  break;
-+	case INST_TYPE_RD_IMML:
-+	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
-+	  break;
- 	  /* For mbar insn.  */
- 	case INST_TYPE_IMM5:
- 	  print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
-@@ -457,7 +469,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  /* For mbar 16 or sleep insn.  */
- 	case INST_TYPE_NONE:
- 	  break;
--	  /* For tuqula instruction */
-         /* For bit field insns.  */
- 	case INST_TYPE_RD_R1_IMMW_IMMS:
- 	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 77d74c17f3a..bd1cc90bff6 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -69,6 +69,7 @@
- #define INST_TYPE_RD_R1_IMMW_IMMS  21
- 
- #define INST_TYPE_NONE 25
-+#define INST_TYPE_RD_IMML 26
- 
- 
- 
-@@ -84,6 +85,7 @@
- #define IMMVAL_MASK_MFS 0x0000
- 
- #define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
-+#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
- #define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
- #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
- #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
-@@ -106,6 +108,33 @@
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
- #define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
- 
-+/*Defines to identify 64-bit single reg instructions */
-+#define ADDLI_ONE_REG_MASK 0x68000000
-+#define ADDLIC_ONE_REG_MASK 0x68020000
-+#define ADDLIK_ONE_REG_MASK 0x68040000
-+#define ADDLIKC_ONE_REG_MASK 0x68060000
-+#define RSUBLI_ONE_REG_MASK 0x68010000
-+#define RSUBLIC_ONE_REG_MASK 0x68030000
-+#define RSUBLIK_ONE_REG_MASK 0x68050000
-+#define RSUBLIKC_ONE_REG_MASK 0x68070000
-+#define ORLI_ONE_REG_MASK 0x68100000
-+#define ANDLI_ONE_REG_MASK 0x68110000
-+#define XORLI_ONE_REG_MASK 0x68120000
-+#define ANDLNI_ONE_REG_MASK 0x68130000
-+#define ADDLI_MASK 0x20000000
-+#define ADDLIC_MASK 0x28000000
-+#define ADDLIK_MASK 0x30000000
-+#define ADDLIKC_MASK 0x38000000
-+#define RSUBLI_MASK 0x24000000
-+#define RSUBLIC_MASK 0x2C000000
-+#define RSUBLIK_MASK 0x34000000
-+#define RSUBLIKC_MASK 0x3C000000
-+#define ANDLI_MASK 0xA4000000
-+#define ANDLNI_MASK 0xAC000000
-+#define ORLI_MASK 0xA0000000
-+#define XORLI_MASK 0xA8000000
-+
-+
- /* New Mask for msrset, msrclr insns.  */
- #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
- /* Mask for mbar insn.  */
-@@ -114,13 +143,13 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 412
-+#define MAX_OPCODES 424
- 
- struct op_code_struct
- {
-   const char * name;
-   short inst_type;            /* Registers and immediate values involved.  */
--  short inst_offset_type;     /* Immediate vals offset from PC? (= 1 for branches).  */
-+  int inst_offset_type;     /* Immediate vals offset from PC? (= 1 for branches).  */
-   short delay_slots;          /* Info about delay slots needed after this instr. */
-   short immval_mask;
-   unsigned long bit_sequence; /* All the fixed bits for the op are set and
-@@ -444,13 +473,21 @@ struct op_code_struct
-   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
-   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
-   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
-   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
-   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
-   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
-   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
-   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
-   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
-   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
-+  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
-   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
-   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
-   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
-@@ -501,9 +538,13 @@ struct op_code_struct
-   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
-   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
-   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
-   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
-   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
-   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
-   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
-   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
-   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index ad8b8ce345b..86cdb3b0715 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -61,7 +61,9 @@ enum microblaze_instr
-   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
- 
-   /* 64-bit instructions */
--  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
-+  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  andli, andnli, orli, xorli,
-   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
-   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
-   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
-@@ -166,5 +168,6 @@ enum microblaze_instr_type
- 
- /* Imm mask for msrset, msrclr instructions.  */
- #define  IMM15_MASK 0x00007FFF
-+#define IMM16_MASK 0x0000FFFF
- 
- #endif /* MICROBLAZE-OPCM */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
new file mode 100644
index 0000000000..e3826d6f47
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
@@ -0,0 +1,551 @@
+From 653712c23456574468c426aebbeb5ee8dae7237e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 27/52] [Patch,MicroBlaze] : double imml generation for 64 bit
+ values.
+
+---
+ gas/config/tc-microblaze.c | 322 ++++++++++++++++++++++++++++++-------
+ opcodes/microblaze-opc.h   |   4 +-
+ 2 files changed, 263 insertions(+), 63 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index eca060b262..aef54ad83f 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1008,7 +1008,7 @@ md_assemble (char * str)
+   char * op_start;
+   char * op_end;
+   char * temp_op_end;
+-  struct op_code_struct * opcode, *opcode1;
++  struct op_code_struct * opcode, *opcode1, *opcode2;
+   char * output = NULL;
+   int nlen = 0;
+   int i;
+@@ -1192,7 +1192,12 @@ md_assemble (char * str)
+           reg2 = 0;
+         }
+       if (strcmp (op_end, ""))
++        {
++        if(microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++	else
+ 	op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++	}
+       else
+ 	as_fatal (_("Error in statement syntax"));
+ 
+@@ -1288,24 +1293,51 @@ md_assemble (char * str)
+ 		|| streq (name, "lwi") || streq (name, "sbi")
+                 || streq (name, "shi") || streq (name, "swi"))))
+         {
+-          temp = immed & 0xFFFFFF8000;
+-          if (temp != 0 && temp != 0xFFFFFF8000)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+             {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+-              if (opcode1 == NULL)
++	   if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++	     {
++             opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++             if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++	  else 
++           {
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
+               inst1 = opcode1->bit_sequence;
+-	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++	  }
+           inst |= (reg1 << RD_LOW) & RD_MASK;
+           inst |= (reg2 << RA_LOW) & RA_MASK;
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+@@ -1316,14 +1348,13 @@ md_assemble (char * str)
+            if ((temp != 0) && (temp != 0xFFFF8000))
+ 	     {
+                /* Needs an immediate inst.  */
+-               opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+                if (opcode1 == NULL)
+                  {
+                    as_bad (_("unknown opcode \"%s\""), "imm");
+                    return;
+                  }
+-
+-               inst1 = opcode1->bit_sequence;
++	       inst1 = opcode1->bit_sequence;
+                inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
+                output[0] = INST_BYTE0 (inst1);
+                output[1] = INST_BYTE1 (inst1);
+@@ -1564,7 +1595,7 @@ md_assemble (char * str)
+         as_fatal (_("Cannot use special register with this instruction"));
+ 
+       if (exp.X_op != O_constant)
+-        as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions"));
++        as_fatal (_("Symbol used as immediate value for arithmetic long instructions"));
+       else
+ 	{
+           output = frag_more (isize);
+@@ -1898,8 +1929,9 @@ md_assemble (char * str)
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+ 	{
++
+           /* Needs an immediate inst.  */
+-          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
++              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+           if (opcode1 == NULL)
+             {
+               as_bad (_("unknown opcode \"%s\""), "imm");
+@@ -1928,7 +1960,12 @@ md_assemble (char * str)
+           reg1 = 0;
+         }
+       if (strcmp (op_end, ""))
++      {
++        if(microblaze_arch_size == 64)
++        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
++        else
+         op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
++      }
+       else
+         as_fatal (_("Error in statement syntax"));
+ 
+@@ -1967,30 +2004,55 @@ md_assemble (char * str)
+         }
+       if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
+         {
+-          temp = immed & 0xFFFFFF8000;
+-          if (temp != 0 && temp != 0xFFFFFF8000)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
+             {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++	    {
++            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+               if (opcode1 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+               inst1 = opcode1->bit_sequence;
+-	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++          else {
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++          }
++	  }
+       	  inst |= (reg1 << RD_LOW) & RD_MASK;
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+          }
+        else 
+ 	 {
+-
+       temp = immed & 0xFFFF8000;
+       if ((temp != 0) && (temp != 0xFFFF8000))
+ 	{
+@@ -2076,25 +2138,50 @@ md_assemble (char * str)
+             streq (name, "breaid") || 
+ 	    streq (name, "brai") || streq (name, "braid")))
+         {
+-          temp = immed & 0xFFFFFF8000;
++          temp = immed & 0xFFFFFFFFFFFF8000;
+           if (temp != 0)
+ 	    {
+               /* Needs an immediate inst.  */
+-              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++	  if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++	   {
++            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+               if (opcode1 == NULL)
+                 {
+                   as_bad (_("unknown opcode \"%s\""), "imml");
+                   return;
+                 }
+-
+               inst1 = opcode1->bit_sequence;
+-              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++           else {
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+               output[0] = INST_BYTE0 (inst1);
+               output[1] = INST_BYTE1 (inst1);
+               output[2] = INST_BYTE2 (inst1);
+               output[3] = INST_BYTE3 (inst1);
+               output = frag_more (isize);
+             }
++            }
+           inst |= (immed << IMM_LOW) & IMM_MASK;
+ 	}
+       else
+@@ -2194,21 +2281,45 @@ md_assemble (char * str)
+ 	{
+ 	  output = frag_more (isize);
+ 	  immedl = exp.X_add_number;
+-
+-	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+-	  if (opcode1 == NULL)
+-	    {
+-	      as_bad (_("unknown opcode \"%s\""), "imml");
+-	      return;
+-	    }
+-
+-	  inst1 = opcode1->bit_sequence;
+-	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
+-	  output[0] = INST_BYTE0 (inst1);
+-	  output[1] = INST_BYTE1 (inst1);
+-	  output[2] = INST_BYTE2 (inst1);
+-	  output[3] = INST_BYTE3 (inst1);
+-	  output = frag_more (isize);
++	   if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++            {
++             opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++          if (opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
++           else {
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++        }
+         }
+ 
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+@@ -2257,21 +2368,46 @@ md_assemble (char * str)
+ 	{
+           output = frag_more (isize);
+           immedl = exp.X_add_number;
+-	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+-	  if (opcode1 == NULL)
+-	    {
+-	      as_bad (_("unknown opcode \"%s\""), "imml");
+-	      return;
+-	    }
+-
++	   if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
++             {
++            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           if (opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode1->bit_sequence;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
++          }
++           else {
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++       if (opcode2 == NULL || opcode1 == NULL)
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
++          inst1 = opcode2->bit_sequence;
++          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++          output[0] = INST_BYTE0 (inst1);
++          output[1] = INST_BYTE1 (inst1);
++          output[2] = INST_BYTE2 (inst1);
++          output[3] = INST_BYTE3 (inst1);
++          output = frag_more (isize);
+           inst1 = opcode1->bit_sequence;
+-	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
++          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+           output[0] = INST_BYTE0 (inst1);
+           output[1] = INST_BYTE1 (inst1);
+           output[2] = INST_BYTE2 (inst1);
+           output[3] = INST_BYTE3 (inst1);
+           output = frag_more (isize);
+         }
++        }
+ 
+       inst |= (reg1 << RA_LOW) & RA_MASK;
+       inst |= (immedl << IMM_LOW) & IMM_MASK;
+@@ -2551,8 +2687,8 @@ md_apply_fix (fixS *   fixP,
+   /* Note: use offsetT because it is signed, valueT is unsigned.  */
+   offsetT      val  = (offsetT) * valp;
+   int          i;
+-  struct op_code_struct * opcode1;
+-  unsigned long inst1;
++  struct op_code_struct * opcode1, * opcode2;
++  unsigned long inst1,inst2;
+ 
+   symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>");
+ 
+@@ -2735,30 +2871,75 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+-      /* Add an imm instruction.  First save the current instruction.  */
+-      for (i = 0; i < INST_WORD_SIZE; i++)
+-	buf[i + INST_WORD_SIZE] = buf[i];
+       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+             || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+         {
+           /* Generate the imm instruction.  */
++           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++	   {
++        /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
+           if (opcode1 == NULL)
+-	    {
+-	      as_bad (_("unknown opcode \"%s\""), "imml");
+-	      return;
+-	    }
++            {
++              as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++            }
+ 
+            inst1 = opcode1->bit_sequence;
+            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+-	     inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++      buf[0] = INST_BYTE0 (inst1);
++      buf[1] = INST_BYTE1 (inst1);
++      buf[2] = INST_BYTE2 (inst1);
++      buf[3] = INST_BYTE3 (inst1);
++	 }
++           else {
++      /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE + 4] = buf[i];
++
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++	   if (opcode1 == NULL || opcode2 ==NULL)
++              {
++	      as_bad (_("unknown opcode \"%s\""), "imml");
++              return;
++	      }
++           inst1 = opcode2->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
++             fixP->fx_r_type = BFD_RELOC_64;
++           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++           inst2 = opcode1->bit_sequence;
++           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
++             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
+-             fixP->fx_r_type = BFD_RELOC_64; 
++             fixP->fx_r_type = BFD_RELOC_64;
+            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
+-             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
++             fixP->fx_r_type = BFD_RELOC_64_PCREL;
++	buf[0] = INST_BYTE0 (inst1);
++	buf[1] = INST_BYTE1 (inst1);
++	buf[2] = INST_BYTE2 (inst1);
++	buf[3] = INST_BYTE3 (inst1);
++	buf[4] = INST_BYTE0 (inst2);
++	buf[5] = INST_BYTE1 (inst2);
++	buf[6] = INST_BYTE2 (inst2);
++	buf[7] = INST_BYTE3 (inst2);
++           }
+          }
+       else
+         {
++      /* Add an imm instruction.  First save the current instruction.  */
++        for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
+           /* Generate the imm instruction.  */
+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+           if (opcode1 == NULL)
+@@ -2770,12 +2951,11 @@ md_apply_fix (fixS *   fixP,
+           inst1 = opcode1->bit_sequence;
+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ 	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
+-         }
+       buf[0] = INST_BYTE0 (inst1);
+       buf[1] = INST_BYTE1 (inst1);
+       buf[2] = INST_BYTE2 (inst1);
+       buf[3] = INST_BYTE3 (inst1);
+-
++         }
+       /* Add the value only if the symbol is defined.  */
+       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
+ 	{
+@@ -2807,21 +2987,41 @@ md_apply_fix (fixS *   fixP,
+       /* Add an imm instruction.  First save the current instruction.  */
+       for (i = 0; i < INST_WORD_SIZE; i++)
+ 	buf[i + INST_WORD_SIZE] = buf[i];
+-      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+-        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) {
++           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
++           {
++           for (i = 0; i < INST_WORD_SIZE; i++)
++            buf[i + INST_WORD_SIZE] = buf[i];
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++	   }
++           else {
++       for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE + 4] = buf[i]; 
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++      inst2 = opcode2->bit_sequence;
++
++      /* We can fixup call to a defined non-global address
++ *          within the same section only.  */
++      buf[4] = INST_BYTE0 (inst2);
++      buf[5] = INST_BYTE1 (inst2);
++      buf[6] = INST_BYTE2 (inst2);
++      buf[7] = INST_BYTE3 (inst2);
++           }
++	}
+       else
+         opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
+       if (opcode1 == NULL)
+ 	{
++      for (i = 0; i < INST_WORD_SIZE; i++)
++        buf[i + INST_WORD_SIZE] = buf[i];
+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
+ 	    as_bad (_("unknown opcode \"%s\""), "imml");
+           else
+ 	    as_bad (_("unknown opcode \"%s\""), "imm");
+ 	  return;
+ 	}
+-
+       inst1 = opcode1->bit_sequence;
+-
+       /* We can fixup call to a defined non-global address
+ 	 within the same section only.  */
+       buf[0] = INST_BYTE0 (inst1);
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index c1b453c95e..ba0b3f8b62 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) -9223372036854775808)
++#define MAX_IMML  ((long long) 9223372036854775807)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
new file mode 100644
index 0000000000..e8c55106f5
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
@@ -0,0 +1,86 @@
+From 2c051a6d5326e34cb4a3170073cda17e7269055d Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 22 Jan 2020 16:31:12 +0530
+Subject: [PATCH 28/52] Fixed bug in generation of IMML instruction for the new
+ MB-64 instructions with single register.
+
+---
+ gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 3 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index aef54ad83f..647cfb6869 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -1639,12 +1639,56 @@ md_assemble (char * str)
+                              exp.X_add_symbol,
+                              exp.X_add_number,
+                              (char *) opc);
+-          immedl = 0L;
++          immed = 0L;
+ 	}		
+       else
+         {
+           output = frag_more (isize);
+           immed = exp.X_add_number;
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
++            {
++              /* Needs an immediate inst.  */
++           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
++	    {
++            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++            }
++          else {
++           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
++              if (opcode1 == NULL || opcode2 == NULL)
++                {
++                  as_bad (_("unknown opcode \"%s\""), "imml");
++                  return;
++                }
++              inst1 = opcode2->bit_sequence;
++              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++              inst1 = opcode1->bit_sequence;
++              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
++              output[0] = INST_BYTE0 (inst1);
++              output[1] = INST_BYTE1 (inst1);
++              output[2] = INST_BYTE2 (inst1);
++              output[3] = INST_BYTE3 (inst1);
++              output = frag_more (isize);
++          }
++	  }
+         }
+       inst |= (reg1 << RD_LOW) & RD_MASK;
+       inst |= (immed << IMM_LOW) & IMM16_MASK;
+@@ -2138,8 +2182,8 @@ md_assemble (char * str)
+             streq (name, "breaid") || 
+ 	    streq (name, "brai") || streq (name, "braid")))
+         {
+-          temp = immed & 0xFFFFFFFFFFFF8000;
+-          if (temp != 0)
++          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
++          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
+ 	    {
+               /* Needs an immediate inst.  */
+ 	  if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
deleted file mode 100644
index a8d5a3852f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
+++ /dev/null
@@ -1,552 +0,0 @@
-From 623f4e7ea6c18bec0e141c7471c7bd609bd9a6d7 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 26 Aug 2019 15:29:42 +0530
-Subject: [PATCH 28/40] [Patch,MicroBlaze] : double imml generation for 64 bit
- values.
-
----
- gas/config/tc-microblaze.c | 324 ++++++++++++++++++++++++++++++-------
- opcodes/microblaze-opc.h   |   4 +-
- 2 files changed, 264 insertions(+), 64 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index b4330652758..f5cc1e05f7e 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -1022,7 +1022,7 @@ md_assemble (char * str)
-   char * op_start;
-   char * op_end;
-   char * temp_op_end;
--  struct op_code_struct * opcode, *opcode1;
-+  struct op_code_struct * opcode, *opcode1, *opcode2;
-   char * output = NULL;
-   int nlen = 0;
-   int i;
-@@ -1206,7 +1206,12 @@ md_assemble (char * str)
-           reg2 = 0;
-         }
-       if (strcmp (op_end, ""))
--	op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+        {
-+          if (microblaze_arch_size == 64)
-+            op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-+	  else
-+	    op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+	}
-       else
- 	as_fatal (_("Error in statement syntax"));
- 
-@@ -1302,24 +1307,51 @@ md_assemble (char * str)
- 		|| streq (name, "lwi") || streq (name, "sbi")
-                 || streq (name, "shi") || streq (name, "swi"))))
-         {
--          temp = immed & 0xFFFFFF8000;
--          if (temp != 0 && temp != 0xFFFFFF8000)
-+          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
-+          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
-             {
-               /* Needs an immediate inst.  */
--              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
--              if (opcode1 == NULL)
-+	   if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
-+	     {
-+             opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+             if (opcode1 == NULL)
-                 {
-                   as_bad (_("unknown opcode \"%s\""), "imml");
-                   return;
-                 }
-               inst1 = opcode1->bit_sequence;
--	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-               output[0] = INST_BYTE0 (inst1);
-               output[1] = INST_BYTE1 (inst1);
-               output[2] = INST_BYTE2 (inst1);
-               output[3] = INST_BYTE3 (inst1);
-               output = frag_more (isize);
-             }
-+	  else 
-+           {
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL || opcode2 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
-+              inst1 = opcode2->bit_sequence;
-+              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+            }
-+	  }
-           inst |= (reg1 << RD_LOW) & RD_MASK;
-           inst |= (reg2 << RA_LOW) & RA_MASK;
-           inst |= (immed << IMM_LOW) & IMM_MASK;
-@@ -1330,14 +1362,13 @@ md_assemble (char * str)
-            if ((temp != 0) && (temp != 0xFFFF8000))
- 	     {
-                /* Needs an immediate inst.  */
--               opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-                if (opcode1 == NULL)
-                  {
-                    as_bad (_("unknown opcode \"%s\""), "imm");
-                    return;
-                  }
--
--               inst1 = opcode1->bit_sequence;
-+	       inst1 = opcode1->bit_sequence;
-                inst1 |= ((immed & 0xFFFF0000) >> 16) & IMM_MASK;
-                output[0] = INST_BYTE0 (inst1);
-                output[1] = INST_BYTE1 (inst1);
-@@ -1578,7 +1609,7 @@ md_assemble (char * str)
-         as_fatal (_("Cannot use special register with this instruction"));
- 
-       if (exp.X_op != O_constant)
--        as_fatal (_("Symbol used as immediate value for msrset/msrclr instructions"));
-+        as_fatal (_("Symbol used as immediate value for arithmetic long instructions"));
-       else
- 	{
-           output = frag_more (isize);
-@@ -1912,8 +1943,9 @@ md_assemble (char * str)
-       temp = immed & 0xFFFF8000;
-       if ((temp != 0) && (temp != 0xFFFF8000))
- 	{
-+
-           /* Needs an immediate inst.  */
--          opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-+              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-           if (opcode1 == NULL)
-             {
-               as_bad (_("unknown opcode \"%s\""), "imm");
-@@ -1942,7 +1974,12 @@ md_assemble (char * str)
-           reg1 = 0;
-         }
-       if (strcmp (op_end, ""))
-+      {
-+        if(microblaze_arch_size == 64)
-+        op_end = parse_imml (op_end + 1, & exp, MIN_IMML, MAX_IMML);
-+        else
-         op_end = parse_imm (op_end + 1, & exp, MIN_IMM, MAX_IMM);
-+      }
-       else
-         as_fatal (_("Error in statement syntax"));
- 
-@@ -1981,30 +2018,55 @@ md_assemble (char * str)
-         }
-       if (streq (name, "brealid") || streq (name, "breaid") || streq (name, "breai"))
-         {
--          temp = immed & 0xFFFFFF8000;
--          if (temp != 0 && temp != 0xFFFFFF8000)
-+          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
-+          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000)
-             {
-               /* Needs an immediate inst.  */
--              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
-+	    {
-+            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-               if (opcode1 == NULL)
-                 {
-                   as_bad (_("unknown opcode \"%s\""), "imml");
-                   return;
-                 }
-               inst1 = opcode1->bit_sequence;
--	      inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-               output[0] = INST_BYTE0 (inst1);
-               output[1] = INST_BYTE1 (inst1);
-               output[2] = INST_BYTE2 (inst1);
-               output[3] = INST_BYTE3 (inst1);
-               output = frag_more (isize);
-             }
-+          else {
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL || opcode2 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
-+              inst1 = opcode2->bit_sequence;
-+              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+          }
-+	  }
-       	  inst |= (reg1 << RD_LOW) & RD_MASK;
-           inst |= (immed << IMM_LOW) & IMM_MASK;
-          }
-        else 
- 	 {
--
-       temp = immed & 0xFFFF8000;
-       if ((temp != 0) && (temp != 0xFFFF8000))
- 	{
-@@ -2090,25 +2152,50 @@ md_assemble (char * str)
-             streq (name, "breaid") ||
- 	    streq (name, "brai") || streq (name, "braid")))
-         {
--          temp = immed & 0xFFFFFF8000;
-+          temp = immed & 0xFFFFFFFFFFFF8000;
-           if (temp != 0)
- 	    {
-               /* Needs an immediate inst.  */
--              opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+	  if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
-+	   {
-+            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-               if (opcode1 == NULL)
-                 {
-                   as_bad (_("unknown opcode \"%s\""), "imml");
-                   return;
-                 }
--
-               inst1 = opcode1->bit_sequence;
--              inst1 |= ((immed & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+            }
-+           else {
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL || opcode2 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
-+              inst1 = opcode2->bit_sequence;
-+              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-               output[0] = INST_BYTE0 (inst1);
-               output[1] = INST_BYTE1 (inst1);
-               output[2] = INST_BYTE2 (inst1);
-               output[3] = INST_BYTE3 (inst1);
-               output = frag_more (isize);
-             }
-+            }
-           inst |= (immed << IMM_LOW) & IMM_MASK;
- 	}
-       else
-@@ -2208,21 +2295,45 @@ md_assemble (char * str)
- 	{
- 	  output = frag_more (isize);
- 	  immedl = exp.X_add_number;
--
--	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
--	  if (opcode1 == NULL)
--	    {
--	      as_bad (_("unknown opcode \"%s\""), "imml");
--	      return;
--	    }
--
--	  inst1 = opcode1->bit_sequence;
--	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
--	  output[0] = INST_BYTE0 (inst1);
--	  output[1] = INST_BYTE1 (inst1);
--	  output[2] = INST_BYTE2 (inst1);
--	  output[3] = INST_BYTE3 (inst1);
--	  output = frag_more (isize);
-+	   if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
-+            {
-+             opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+          if (opcode1 == NULL)
-+            {
-+              as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+            }
-+          inst1 = opcode1->bit_sequence;
-+          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-+        }
-+           else {
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+       if (opcode2 == NULL || opcode1 == NULL)
-+            {
-+              as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+            }
-+          inst1 = opcode2->bit_sequence;
-+          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-+          inst1 = opcode1->bit_sequence;
-+          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-+        }
-         }
- 
-       inst |= (reg1 << RD_LOW) & RD_MASK;
-@@ -2271,21 +2382,46 @@ md_assemble (char * str)
- 	{
-           output = frag_more (isize);
-           immedl = exp.X_add_number;
--	  opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
--	  if (opcode1 == NULL)
--	    {
--	      as_bad (_("unknown opcode \"%s\""), "imml");
--	      return;
--	    }
--
-+	   if (((long long)immedl) > (long long)-549755813888 && ((long long)immedl) < (long long)549755813887)
-+             {
-+            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           if (opcode1 == NULL)
-+            {
-+              as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+            }
-+          inst1 = opcode1->bit_sequence;
-+          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-+          }
-+           else {
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+       if (opcode2 == NULL || opcode1 == NULL)
-+            {
-+              as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+            }
-+          inst1 = opcode2->bit_sequence;
-+          inst1 |= ((immedl & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+          output[0] = INST_BYTE0 (inst1);
-+          output[1] = INST_BYTE1 (inst1);
-+          output[2] = INST_BYTE2 (inst1);
-+          output[3] = INST_BYTE3 (inst1);
-+          output = frag_more (isize);
-           inst1 = opcode1->bit_sequence;
--	  inst1 |= ((immedl & 0xFFFFFFFFFFFF0000L) >> 16) & IMML_MASK;
-+          inst1 |= ((immedl & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-           output[0] = INST_BYTE0 (inst1);
-           output[1] = INST_BYTE1 (inst1);
-           output[2] = INST_BYTE2 (inst1);
-           output[3] = INST_BYTE3 (inst1);
-           output = frag_more (isize);
-         }
-+        }
- 
-       inst |= (reg1 << RA_LOW) & RA_MASK;
-       inst |= (immedl << IMM_LOW) & IMM_MASK;
-@@ -2565,8 +2701,8 @@ md_apply_fix (fixS *   fixP,
-   /* Note: use offsetT because it is signed, valueT is unsigned.  */
-   offsetT      val  = (offsetT) * valp;
-   int          i;
--  struct op_code_struct * opcode1;
--  unsigned long inst1;
-+  struct op_code_struct * opcode1, * opcode2;
-+  unsigned long inst1,inst2;
- 
-   symname = fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : _("<unknown>");
- 
-@@ -2749,30 +2885,75 @@ md_apply_fix (fixS *   fixP,
-     case BFD_RELOC_MICROBLAZE_64_TEXTREL:
-     case BFD_RELOC_MICROBLAZE_64:
-     case BFD_RELOC_MICROBLAZE_64_PCREL:
--      /* Add an imm instruction.  First save the current instruction.  */
--      for (i = 0; i < INST_WORD_SIZE; i++)
--	buf[i + INST_WORD_SIZE] = buf[i];
-       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
-             || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-         {
-           /* Generate the imm instruction.  */
-+           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
-+	   {
-+        /* Add an imm instruction.  First save the current instruction.  */
-+        for (i = 0; i < INST_WORD_SIZE; i++)
-+        buf[i + INST_WORD_SIZE] = buf[i];
-           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-           if (opcode1 == NULL)
--	    {
--	      as_bad (_("unknown opcode \"%s\""), "imml");
--	      return;
--	    }
-+            {
-+              as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+            }
- 
-            inst1 = opcode1->bit_sequence;
-            if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
--	     inst1 |= ((val & 0xFFFFFF0000L) >> 16) & IMML_MASK;
-+             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+             fixP->fx_r_type = BFD_RELOC_64;
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-+             fixP->fx_r_type = BFD_RELOC_64_PCREL;
-+      buf[0] = INST_BYTE0 (inst1);
-+      buf[1] = INST_BYTE1 (inst1);
-+      buf[2] = INST_BYTE2 (inst1);
-+      buf[3] = INST_BYTE3 (inst1);
-+	 }
-+           else {
-+      /* Add an imm instruction.  First save the current instruction.  */
-+        for (i = 0; i < INST_WORD_SIZE; i++)
-+        buf[i + INST_WORD_SIZE + 4] = buf[i];
-+
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+	   if (opcode1 == NULL || opcode2 ==NULL)
-+              {
-+	      as_bad (_("unknown opcode \"%s\""), "imml");
-+              return;
-+	      }
-+           inst1 = opcode2->bit_sequence;
-+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+             inst1 |= ((val & 0x000000FFFFFF0000L) >> 40) & IMML_MASK;
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
-+             fixP->fx_r_type = BFD_RELOC_64;
-+           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-+             fixP->fx_r_type = BFD_RELOC_64_PCREL;
-+           inst2 = opcode1->bit_sequence;
-+           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
-+             inst1 |= ((val & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64)
--             fixP->fx_r_type = BFD_RELOC_64; 
-+             fixP->fx_r_type = BFD_RELOC_64;
-            if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
--             fixP->fx_r_type = BFD_RELOC_64_PCREL; 
-+             fixP->fx_r_type = BFD_RELOC_64_PCREL;
-+	buf[0] = INST_BYTE0 (inst1);
-+	buf[1] = INST_BYTE1 (inst1);
-+	buf[2] = INST_BYTE2 (inst1);
-+	buf[3] = INST_BYTE3 (inst1);
-+	buf[4] = INST_BYTE0 (inst2);
-+	buf[5] = INST_BYTE1 (inst2);
-+	buf[6] = INST_BYTE2 (inst2);
-+	buf[7] = INST_BYTE3 (inst2);
-+           }
-          }
-       else
-         {
-+      /* Add an imm instruction.  First save the current instruction.  */
-+        for (i = 0; i < INST_WORD_SIZE; i++)
-+        buf[i + INST_WORD_SIZE] = buf[i];
-           /* Generate the imm instruction.  */
-           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-           if (opcode1 == NULL)
-@@ -2784,12 +2965,11 @@ md_apply_fix (fixS *   fixP,
-           inst1 = opcode1->bit_sequence;
-           if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- 	    inst1 |= ((val & 0xFFFF0000) >> 16) & IMM_MASK;
--         }
-       buf[0] = INST_BYTE0 (inst1);
-       buf[1] = INST_BYTE1 (inst1);
-       buf[2] = INST_BYTE2 (inst1);
-       buf[3] = INST_BYTE3 (inst1);
--
-+         }
-       /* Add the value only if the symbol is defined.  */
-       if (fixP->fx_addsy == NULL || S_IS_DEFINED (fixP->fx_addsy))
- 	{
-@@ -2821,21 +3001,41 @@ md_apply_fix (fixS *   fixP,
-       /* Add an imm instruction.  First save the current instruction.  */
-       for (i = 0; i < INST_WORD_SIZE; i++)
- 	buf[i + INST_WORD_SIZE] = buf[i];
--      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
--        opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+      if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC) {
-+           if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
-+           {
-+           for (i = 0; i < INST_WORD_SIZE; i++)
-+            buf[i + INST_WORD_SIZE] = buf[i];
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+	   }
-+           else {
-+       for (i = 0; i < INST_WORD_SIZE; i++)
-+        buf[i + INST_WORD_SIZE + 4] = buf[i]; 
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+      inst2 = opcode2->bit_sequence;
-+
-+      /* We can fixup call to a defined non-global address
-+ *          within the same section only.  */
-+      buf[4] = INST_BYTE0 (inst2);
-+      buf[5] = INST_BYTE1 (inst2);
-+      buf[6] = INST_BYTE2 (inst2);
-+      buf[7] = INST_BYTE3 (inst2);
-+           }
-+	}
-       else
-         opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imm");
-       if (opcode1 == NULL)
- 	{
-+      for (i = 0; i < INST_WORD_SIZE; i++)
-+        buf[i + INST_WORD_SIZE] = buf[i];
-           if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_GPC)
- 	    as_bad (_("unknown opcode \"%s\""), "imml");
-           else
- 	    as_bad (_("unknown opcode \"%s\""), "imm");
- 	  return;
- 	}
--
-       inst1 = opcode1->bit_sequence;
--
-       /* We can fixup call to a defined non-global address
- 	 within the same section only.  */
-       buf[0] = INST_BYTE0 (inst1);
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index bd1cc90bff6..cf5b5920921 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM6_WIDTH  ((int) 0x00000001)
- #define MAX_IMM6_WIDTH  ((int) 0x00000040)
- 
--#define MIN_IMML  ((long long) 0xffffff8000000000L)
--#define MAX_IMML  ((long long) 0x0000007fffffffffL)
-+#define MIN_IMML  ((long long) -9223372036854775807)
-+#define MAX_IMML  ((long long) 9223372036854775807)
- 
- #endif /* MICROBLAZE_OPC */
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
deleted file mode 100644
index 3720f2dcba..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Fixed-bug-in-generation-of-IMML-instruction-for-the.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From b7b5caa314177cfe8aeb0fb6d748f6e52fe51a83 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Wed, 22 Jan 2020 16:31:12 +0530
-Subject: [PATCH 29/40] Fixed bug in generation of IMML instruction for the new
- MB-64 instructions with single register.
-
----
- gas/config/tc-microblaze.c | 50 +++++++++++++++++++++++++++++++++++---
- 1 file changed, 47 insertions(+), 3 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index f5cc1e05f7e..efd1a42769e 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -1653,12 +1653,56 @@ md_assemble (char * str)
-                              exp.X_add_symbol,
-                              exp.X_add_number,
-                              (char *) opc);
--          immedl = 0L;
-+          immed = 0L;
- 	}		
-       else
-         {
-           output = frag_more (isize);
-           immed = exp.X_add_number;
-+          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
-+          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
-+            {
-+              /* Needs an immediate inst.  */
-+           if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
-+	    {
-+            opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+            }
-+          else {
-+           opcode2 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+           opcode1 = (struct op_code_struct *) hash_find (opcode_hash_control, "imml");
-+              if (opcode1 == NULL || opcode2 == NULL)
-+                {
-+                  as_bad (_("unknown opcode \"%s\""), "imml");
-+                  return;
-+                }
-+              inst1 = opcode2->bit_sequence;
-+              inst1 |= ((immed & 0xFFFFFF0000000000L) >> 40) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+              inst1 = opcode1->bit_sequence;
-+              inst1 |= ((immed & 0x000000FFFFFF0000L) >> 16) & IMML_MASK;
-+              output[0] = INST_BYTE0 (inst1);
-+              output[1] = INST_BYTE1 (inst1);
-+              output[2] = INST_BYTE2 (inst1);
-+              output[3] = INST_BYTE3 (inst1);
-+              output = frag_more (isize);
-+          }
-+	  }
-         }
-       inst |= (reg1 << RD_LOW) & RD_MASK;
-       inst |= (immed << IMM_LOW) & IMM16_MASK;
-@@ -2152,8 +2196,8 @@ md_assemble (char * str)
-             streq (name, "breaid") ||
- 	    streq (name, "brai") || streq (name, "braid")))
-         {
--          temp = immed & 0xFFFFFFFFFFFF8000;
--          if (temp != 0)
-+          temp = ((long long)immed) & 0xFFFFFFFFFFFF8000;
-+          if (temp != 0 && temp != 0xFFFFFFFFFFFF8000 && temp != 0x8000)
- 	    {
-               /* Needs an immediate inst.  */
- 	  if (((long long)immed) > (long long)-549755813888 && ((long long)immed) < (long long)549755813887)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch
new file mode 100644
index 0000000000..abfcdabc4b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0029-Patch-MicroBlaze-m64-This-patch-will-remove-imml-0-a.patch
@@ -0,0 +1,38 @@
+From 77751e719ba1470f3dc869ae309485adb02819b6 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 16 Apr 2020 18:08:58 +0530
+Subject: [PATCH 29/52]  [Patch,MicroBlaze m64] : This patch will remove imml 0
+ and imml -1 instructions when the offset is less than 16 bit for Type A
+ branch EA instructions.
+
+---
+ gas/config/tc-microblaze.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index 647cfb6869..e565b2a99d 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2150,9 +2150,7 @@ md_assemble (char * str)
+       if (exp.X_op != O_constant)
+ 	{
+ 	  char *opc;
+-          if (microblaze_arch_size == 64 && (streq (name, "breai") || 
+-		 streq (name, "breaid") || 
+-	         streq (name, "brai") || streq (name, "braid")))
++          if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid")))
+             opc = str_microblaze_64;
+ 	  else
+             opc = NULL;
+@@ -2916,7 +2914,7 @@ md_apply_fix (fixS *   fixP,
+     case BFD_RELOC_MICROBLAZE_64:
+     case BFD_RELOC_MICROBLAZE_64_PCREL:
+       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
+-            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
++            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64))
+         {
+           /* Generate the imm instruction.  */
+            if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-improper-address-mapping-of-PROVIDE.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-improper-address-mapping-of-PROVIDE.patch
new file mode 100644
index 0000000000..b8f8b8bdad
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-improper-address-mapping-of-PROVIDE.patch
@@ -0,0 +1,39 @@
+From 2a43e06f14cac633d87f5b213a6bacd16085967f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 17 Jun 2020 21:20:26 +0530
+Subject: [PATCH 30/52] [Patch,MicroBlaze] : improper address mapping of
+ PROVIDE directive symbols[DTOR_END] are causing runtime loops and we don't
+ need to override PROVIDE symbols if symbols are defined in libraries and
+ linker so I am disabling override for PROVIDE symbols.
+
+---
+ ld/ldlang.c | 12 +++++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/ld/ldlang.c b/ld/ldlang.c
+index 9977195074..a2c44cf719 100644
+--- a/ld/ldlang.c
++++ b/ld/ldlang.c
+@@ -3657,10 +3657,16 @@ open_input_bfds (lang_statement_union_type *s, enum open_bfd_mode mode)
+ 	    plugin_insert = NULL;
+ #endif
+ 	  break;
++         /* This is from a --defsym on the command line.  */
+ 	case lang_assignment_statement_enum:
+-	  if (s->assignment_statement.exp->type.node_class != etree_assert)
+-	    exp_fold_tree_no_dot (s->assignment_statement.exp);
+-	  break;
++          if (s->assignment_statement.exp->type.node_class != etree_assert)
++          {
++          if(!(s->assignment_statement.exp->assign.defsym) && (s->assignment_statement.exp->type.node_class == etree_provide))
++          ;
++          else
++          exp_fold_tree_no_dot (s->assignment_statement.exp);
++          }
++          break;
+ 	default:
+ 	  break;
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-m64-Update-imml-instructions-for-Ty.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-m64-Update-imml-instructions-for-Ty.patch
deleted file mode 100644
index 8cd3563bc0..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0030-Patch-MicroBlaze-m64-Update-imml-instructions-for-Ty.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 0afa4ba2af8d63cb70771f1c7e235af920603533 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 16 Apr 2020 18:08:58 +0530
-Subject: [PATCH 30/40] [Patch,MicroBlaze m64]: Update imml instructions for
- Type A branch EA
-
-This patch will remove imml 0 and imml -1 instructions when the offset is less than 16 bit for Type A branch EA instructions.
----
- gas/config/tc-microblaze.c | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index efd1a42769e..1d838abfefa 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -2164,13 +2164,13 @@ md_assemble (char * str)
-       if (exp.X_op != O_constant)
- 	{
- 	  char *opc;
--          if (microblaze_arch_size == 64 && (streq (name, "breai") ||
--		 streq (name, "breaid") ||
--	         streq (name, "brai") || streq (name, "braid")))
--            opc = strdup(str_microblaze_64);
-+	   /* removal of imml 0 and imml -1 for bea type A insns.
-+	      if offset is 16 bit then imml instructions are redundant */
-+	  if (microblaze_arch_size == 64 && (streq (name, "brai") || streq (name, "braid")))
-+	    opc = strdup(str_microblaze_64);
- 	  else
--            opc = NULL;
--          relax_substateT subtype;
-+	    opc = NULL;
-+	  relax_substateT subtype;
- 
- 	  if (exp.X_md != 0)
- 	    subtype = get_imm_otype(exp.X_md);
-@@ -2930,7 +2930,7 @@ md_apply_fix (fixS *   fixP,
-     case BFD_RELOC_MICROBLAZE_64:
-     case BFD_RELOC_MICROBLAZE_64_PCREL:
-       if (fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64
--            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL)
-+            || fixP->fx_r_type == BFD_RELOC_MICROBLAZE_64_PCREL || (fixP->fx_r_type == BFD_RELOC_64_PCREL && microblaze_arch_size == 64))
-         {
-           /* Generate the imm instruction.  */
-            if (((long long)val) > (long long)-549755813888 && ((long long)val) < (long long)549755813887)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-gas-revert-moving-of-md_pseudo_table-from-const.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-gas-revert-moving-of-md_pseudo_table-from-const.patch
new file mode 100644
index 0000000000..83b293f3f9
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-gas-revert-moving-of-md_pseudo_table-from-const.patch
@@ -0,0 +1,83 @@
+From c45a69deeb210ebdb80cf055cef9e62bd0bda053 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Thu, 16 Jul 2020 12:38:11 -0500
+Subject: [PATCH 31/52] gas: revert moving of md_pseudo_table from const
+
+The base system expect md_pseudo_table to be constant, Changing the
+definition will break other architectures when compiled with a
+unified source code.
+
+Patch reverts the change away from const, and implements a newer
+dynamic handler that passes the correct argument value based on word
+size.
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ gas/config/tc-microblaze.c | 16 +++++++++++++---
+ gas/tc.h                   |  2 +-
+ 2 files changed, 14 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index e565b2a99d..c6ca913f8b 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -385,6 +385,17 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+   demand_empty_rest_of_line ();
+ }
+ 
++/* Handle the .gpword pseudo-op, Pass to s_rva */
++
++static void
++microblaze_s_gpword (int ignore ATTRIBUTE_UNUSED)
++{
++  int size = 4;
++  if (microblaze_arch_size == 64)
++    size = 8;
++  s_rva(size);
++}
++
+ /* This table describes all the machine specific pseudo-ops the assembler
+    has to support.  The fields are:
+    Pseudo-op name without dot
+@@ -392,7 +403,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
+    Integer arg to pass to the function.  */
+ /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
+    and then in the read.c table.  */
+-pseudo_typeS md_pseudo_table[] =
++const pseudo_typeS md_pseudo_table[] =
+ {
+   {"lcomm", microblaze_s_lcomm, 1},
+   {"data", microblaze_s_data, 0},
+@@ -401,7 +412,7 @@ pseudo_typeS md_pseudo_table[] =
+   {"data32", cons, 4},     /* Same as word.  */
+   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
+   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
+-  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
++  {"gpword", microblaze_s_gpword, 0}, /* gpword label => store resolved label address in data section.  */
+   {"weakext", microblaze_s_weakext, 0},
+   {"rodata", microblaze_s_rdata, 0},
+   {"sdata2", microblaze_s_rdata, 1},
+@@ -3448,7 +3459,6 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
+     case OPTION_M64:
+       //if (arg != NULL && strcmp (arg, "64") == 0)
+       microblaze_arch_size = 64;
+-      md_pseudo_table[7].poc_val = 8;
+       break;
+     default:
+       return 0;
+diff --git a/gas/tc.h b/gas/tc.h
+index 5bdfe5c347..da1738d67a 100644
+--- a/gas/tc.h
++++ b/gas/tc.h
+@@ -22,7 +22,7 @@
+ /* In theory (mine, at least!) the machine dependent part of the assembler
+    should only have to include one file.  This one.  -- JF */
+ 
+-extern pseudo_typeS md_pseudo_table[];
++extern const pseudo_typeS md_pseudo_table[];
+ 
+ const char * md_atof (int, char *, int *);
+ int    md_parse_option (int, const char *);
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-ldlang.c-Workaround-for-improper-address-mapping-cau.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-ldlang.c-Workaround-for-improper-address-mapping-cau.patch
deleted file mode 100644
index fda23a1a5f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0031-ldlang.c-Workaround-for-improper-address-mapping-cau.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 23f0f6e8281b5cd481ef7636739c07b446828f7e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 17 Jun 2020 21:20:26 +0530
-Subject: [PATCH 31/40] ldlang.c: Workaround for improper address mapping
- causing runtime loops
-
-[Patch,MicroBlaze] : improper address mapping of PROVIDE directive
-symbols[DTOR_END] are causing runtime loops and we don't need to override
-PROVIDE symbols if symbols are defined in libraries and linker so I am
-disabling override for PROVIDE symbols.
----
- ld/ldlang.c | 8 +++++++-
- 1 file changed, 7 insertions(+), 1 deletion(-)
-
-diff --git a/ld/ldlang.c b/ld/ldlang.c
-index 9977195074a..9e2c1da066e 100644
---- a/ld/ldlang.c
-+++ b/ld/ldlang.c
-@@ -3657,9 +3657,15 @@ open_input_bfds (lang_statement_union_type *s, enum open_bfd_mode mode)
- 	    plugin_insert = NULL;
- #endif
- 	  break;
-+	/* This is from a --defsym on the command line.  */
- 	case lang_assignment_statement_enum:
- 	  if (s->assignment_statement.exp->type.node_class != etree_assert)
--	    exp_fold_tree_no_dot (s->assignment_statement.exp);
-+	    {
-+	      if(!(s->assignment_statement.exp->assign.defsym) && (s->assignment_statement.exp->type.node_class == etree_provide))
-+		;
-+	      else
-+		exp_fold_tree_no_dot (s->assignment_statement.exp);
-+	    }
- 	  break;
- 	default:
- 	  break;
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-gas-revert-moving-of-md_pseudo_table-from-const.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-gas-revert-moving-of-md_pseudo_table-from-const.patch
deleted file mode 100644
index 0e813f9680..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-gas-revert-moving-of-md_pseudo_table-from-const.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 4d0c68ffb688c23f984de8c0a22af824c3902d83 Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Thu, 16 Jul 2020 12:38:11 -0500
-Subject: [PATCH 32/40] gas: revert moving of md_pseudo_table from const
-
-The base system expect md_pseudo_table to be constant, Changing the
-definition will break other architectures when compiled with a
-unified source code.
-
-Patch reverts the change away from const, and implements a newer
-dynamic handler that passes the correct argument value based on word
-size.
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- gas/config/tc-microblaze.c | 16 +++++++++++++---
- gas/tc.h                   |  2 +-
- 2 files changed, 14 insertions(+), 4 deletions(-)
-
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 1d838abfefa..da99d4ef482 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -384,6 +384,17 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
-   demand_empty_rest_of_line ();
- }
- 
-+/* Handle the .gpword pseudo-op, Pass to s_rva */
-+
-+static void
-+microblaze_s_gpword (int ignore ATTRIBUTE_UNUSED)
-+{
-+  int size = 4;
-+  if (microblaze_arch_size == 64)
-+    size = 8;
-+  s_rva(size);
-+}
-+
- /* This table describes all the machine specific pseudo-ops the assembler
-    has to support.  The fields are:
-    Pseudo-op name without dot
-@@ -391,7 +402,7 @@ microblaze_s_weakext (int ignore ATTRIBUTE_UNUSED)
-    Integer arg to pass to the function.  */
- /* If the pseudo-op is not found in this table, it searches in the obj-elf.c,
-    and then in the read.c table.  */
--pseudo_typeS md_pseudo_table[] =
-+const pseudo_typeS md_pseudo_table[] =
- {
-   {"lcomm", microblaze_s_lcomm, 1},
-   {"data", microblaze_s_data, 0},
-@@ -400,7 +411,7 @@ pseudo_typeS md_pseudo_table[] =
-   {"data32", cons, 4},     /* Same as word.  */
-   {"ent", s_func, 0}, /* Treat ent as function entry point.  */
-   {"end", microblaze_s_func, 1}, /* Treat end as function end point.  */
--  {"gpword", s_rva, 4}, /* gpword label => store resolved label address in data section.  */
-+  {"gpword", microblaze_s_gpword, 0}, /* gpword label => store resolved label address in data section.  */
-   {"weakext", microblaze_s_weakext, 0},
-   {"rodata", microblaze_s_rdata, 0},
-   {"sdata2", microblaze_s_rdata, 1},
-@@ -3464,7 +3475,6 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
-     case OPTION_M64:
-       //if (arg != NULL && strcmp (arg, "64") == 0)
-       microblaze_arch_size = 64;
--      md_pseudo_table[7].poc_val = 8;
-       break;
-     default:
-       return 0;
-diff --git a/gas/tc.h b/gas/tc.h
-index 5bdfe5c3475..da1738d67a8 100644
---- a/gas/tc.h
-+++ b/gas/tc.h
-@@ -22,7 +22,7 @@
- /* In theory (mine, at least!) the machine dependent part of the assembler
-    should only have to include one file.  This one.  -- JF */
- 
--extern pseudo_typeS md_pseudo_table[];
-+extern const pseudo_typeS md_pseudo_table[];
- 
- const char * md_atof (int, char *, int *);
- int    md_parse_option (int, const char *);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
new file mode 100644
index 0000000000..8891a77fb7
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
@@ -0,0 +1,43 @@
+From 7b285c827edbc34cf79d4ed0f46cdfd4916b687c Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Mon, 30 Nov 2020 16:17:36 -0800
+Subject: [PATCH 32/52] ld/emulparams/elf64microblaze: Fix emulation generation
+
+Compilation fails when building ld-new with:
+
+ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation'
+ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation'
+
+The error appears to be that the elf64 files were referencing the elf32 emulation.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 2 +-
+ ld/emulparams/elf64microblazeel.sh | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/ld/emulparams/elf64microblaze.sh b/ld/emulparams/elf64microblaze.sh
+index 9c7b0eb708..7b4c7c411b 100644
+--- a/ld/emulparams/elf64microblaze.sh
++++ b/ld/emulparams/elf64microblaze.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+diff --git a/ld/emulparams/elf64microblazeel.sh b/ld/emulparams/elf64microblazeel.sh
+index 9c7b0eb708..7b4c7c411b 100644
+--- a/ld/emulparams/elf64microblazeel.sh
++++ b/ld/emulparams/elf64microblazeel.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
new file mode 100644
index 0000000000..b296e1b14d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -0,0 +1,435 @@
+From 3f506a7c6a8f7b746102276f3c41a7b11bd7ac3c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 23 Jan 2017 19:07:44 +0530
+Subject: [PATCH 33/52] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/configure.host                |   3 +
+ gdb/microblaze-linux-tdep.c       |  29 ++++-
+ gdb/microblaze-tdep.c             |  35 +++++-
+ gdb/microblaze-tdep.h             |   4 +-
+ gdb/regformats/reg-microblaze.dat |  41 +++++++
+ gdbserver/linux-microblaze-low.c  | 189 ++++++++++++++++++++++++++++++
+ 6 files changed, 298 insertions(+), 3 deletions(-)
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+ create mode 100644 gdbserver/linux-microblaze-low.c
+
+diff --git a/gdb/configure.host b/gdb/configure.host
+index ce52823729..cf1a08e8b2 100644
+--- a/gdb/configure.host
++++ b/gdb/configure.host
+@@ -65,6 +65,7 @@ hppa*)			gdb_host_cpu=pa ;;
+ i[34567]86*)		gdb_host_cpu=i386 ;;
+ m68*)			gdb_host_cpu=m68k ;;
+ mips*)			gdb_host_cpu=mips ;;
++microblaze*)		gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000)	gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64)	gdb_host_cpu=sparc ;;
+ s390*)			gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ mips*-*-freebsd*)	gdb_host=fbsd ;;
+ mips64*-*-openbsd*)	gdb_host=obsd64 ;;
+ 
++microblaze*-*linux*)	gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ 			gdb_host=aix ;;
+ powerpc*-*-freebsd*)	gdb_host=fbsd ;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index be710bedb6..fb8241884b 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+ 
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++  if (microblaze_debug_flag)
++    {
++       va_list args;
++
++       va_start (args, fmt);
++       printf_unfiltered ("MICROBLAZE LINUX: ");
++       vprintf_unfiltered (fmt, args);
++       va_end (args);
++    }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+ 					   struct bp_target_info *bp_tgt)
+@@ -46,18 +62,25 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   int val;
+   int bplen;
+   gdb_byte old_contents[BREAKPOINT_MAX];
++  struct cleanup *cleanup;
+ 
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ 
++  /* Make sure we see the memory breakpoints.  */
++  cleanup = make_show_memory_breakpoints_cleanup (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+      program modified the code on us, so it is wrong to put back the
+      old value.  */
+   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+-    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++  {
++      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
+ 
++  do_cleanups (cleanup);
+   return val;
+ }
+ 
+@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   /* Trampolines.  */
+   tramp_frame_prepend_unwinder (gdbarch,
+ 				&microblaze_linux_sighandler_tramp_frame);
++
++  /* Enable TLS support.  */
++  set_gdbarch_fetch_tls_load_module_address (gdbarch,
++                                             svr4_fetch_objfile_link_map);
+ }
+ 
+ void _initialize_microblaze_linux_tdep ();
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 5c80413304..443adfb364 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++				    struct bp_target_info *bp_tgt)
++{
++  CORE_ADDR addr = bp_tgt->placed_address;
++  const unsigned char *bp;
++  int val;
++  int bplen;
++  gdb_byte old_contents[BREAKPOINT_MAX];
++  struct cleanup *cleanup;
++
++  /* Determine appropriate breakpoint contents and size for this address.  */
++  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++  if (bp == NULL)
++    error (_("Software breakpoints not implemented for this target."));
++
++  /* Make sure we see the memory breakpoints.  */
++  cleanup = make_show_memory_breakpoints_cleanup (1);
++  val = target_read_memory (addr, old_contents, bplen);
++
++  /* If our breakpoint is no longer at the address, this means that the
++     program modified the code on us, so it is wrong to put back the
++     old value.  */
++  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++  {
++    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
++
++  do_cleanups (cleanup);
++  return val;
++}
+ 
+ /* Allocate and initialize a frame cache.  */
+ 
+@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 				       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ 				       microblaze_breakpoint::bp_from_kind);
++  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+@@ -771,4 +803,5 @@ When non-zero, microblaze specific debugging is enabled."),
+ 			     NULL,
+ 			     &setdebuglist, &showdebuglist);
+ 
++
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 4fbdf9933f..db0772643d 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -117,6 +117,8 @@ struct microblaze_frame_cache
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
++
+ 
+ #endif /* microblaze-tdep.h */
+diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
+new file mode 100644
+index 0000000000..bd8a438442
+--- /dev/null
++++ b/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,41 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
++32:slr
++32:shr
+diff --git a/gdbserver/linux-microblaze-low.c b/gdbserver/linux-microblaze-low.c
+new file mode 100644
+index 0000000000..cba5d6fc58
+--- /dev/null
++++ b/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,189 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++   GDB.
++   Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
++  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
++  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
++  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
++  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
++  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
++  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
++  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
++  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
++  PT_FSR
++  };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c.  */
++void init_registers_microblaze (void);
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++  if (microblaze_regmap[regno] == -1 || regno == 0)
++    return 1;
++
++  return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++  return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++  unsigned long pc;
++
++  collect_register_by_name (regcache, "pc", &pc);
++  return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  unsigned long newpc = pc;
++
++  supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++  unsigned long insn;
++
++  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++  if (insn == microblaze_breakpoint)
++    return 1;
++  /* If necessary, recognize more trap instructions here.  GDB only uses the
++     one.  */
++  return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++  unsigned long pc;
++  collect_register_by_name (regcache, "r15", &pc);
++  return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++  int size = register_size (regno);
++
++  memset (buf, 0, sizeof (long));
++
++  if (size < sizeof (long))
++    collect_register (regcache, regno, buf + sizeof (long) - size);
++  else
++    collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++			    int regno, const char *buf)
++{
++  int size = register_size (regno);
++
++  if (regno == 0) {
++    unsigned long regbuf_0 = 0;
++    /* clobbering r0 so that it is always 0 as enforced by hardware */
++    supply_register (regcache, regno, (const char*)&regbuf_0);
++  } else {
++      if (size < sizeof (long))
++        supply_register (regcache, regno, buf + sizeof (long) - size);
++      else
++        supply_register (regcache, regno, buf);
++  }
++}
++
++/* Provide only a fill function for the general register set.  ps_lgetregs
++   will use this for NPTL support.  */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++struct regset_info target_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++  { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++  { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++struct linux_target_ops the_low_target = {
++  init_registers_microblaze,
++  microblaze_num_regs,
++  microblaze_regmap,
++  NULL,
++  microblaze_cannot_fetch_register,
++  microblaze_cannot_store_register,
++  NULL, /* fetch_register */
++  microblaze_get_pc,
++  microblaze_set_pc,
++  (const unsigned char *) &microblaze_breakpoint,
++  microblaze_breakpoint_len,
++  microblaze_reinsert_addr,
++  0,
++  microblaze_breakpoint_at,
++  NULL,
++  NULL,
++  NULL,
++  NULL,
++  microblaze_collect_ptrace_register,
++  microblaze_supply_ptrace_register,
++};
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Fix-various-compile-warnings.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Fix-various-compile-warnings.patch
deleted file mode 100644
index 7339995e7c..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0033-Fix-various-compile-warnings.patch
+++ /dev/null
@@ -1,105 +0,0 @@
-From d9114e764eb42ae1daaf6af7c2a5e48fc764109d Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Fri, 17 Jul 2020 09:20:54 -0500
-Subject: [PATCH 33/40] Fix various compile warnings
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- bfd/elf64-microblaze.c     |  9 +++++----
- gas/config/tc-microblaze.c | 11 +++++------
- 2 files changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index b002b414d64..8308f1ebd09 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -692,7 +692,7 @@ microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
- /* Set the howto pointer for a RCE ELF reloc.  */
- 
- static bfd_boolean
--microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-+microblaze_elf_info_to_howto (bfd * abfd,
- 			      arelent * cache_ptr,
- 			      Elf_Internal_Rela * dst)
- {
-@@ -705,14 +705,14 @@ microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-   r_type = ELF64_R_TYPE (dst->r_info);
-   if (r_type >= R_MICROBLAZE_max)
-     {
--      (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
-+      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
- 			     abfd, r_type);
-       bfd_set_error (bfd_error_bad_value);
-       return FALSE;
-     }
- 
-   cache_ptr->howto = microblaze_elf_howto_table [r_type];
-- return TRUE;
-+  return TRUE;
- }
- 
- /* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
-@@ -1560,7 +1560,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 			else
- 			  {
- 			    BFD_FAIL ();
--			    (*_bfd_error_handler)
-+			    _bfd_error_handler
- 			      (_("%pB: probably compiled without -fPIC?"),
- 			       input_bfd);
- 			    bfd_set_error (bfd_error_bad_value);
-@@ -2554,6 +2554,7 @@ microblaze_elf_check_relocs (bfd * abfd,
-           goto dogottls;
-         case R_MICROBLAZE_TLSLD:
-           tls_type |= (TLS_TLS | TLS_LD);
-+          /* Fall through. */
-         dogottls:
-           sec->has_tls_reloc = 1;
-           /* Fall through. */
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index da99d4ef482..62daa56b47a 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -1091,7 +1091,6 @@ md_assemble (char * str)
-         reg  = is_reg (temp_op_end + 1);
-       if (reg) 
- 	{
--          
-  	  opcode->inst_type=INST_TYPE_RD_R1_IMML;
-           opcode->inst_offset_type = OPCODE_MASK_H;
-           if (streq (name, "addli"))
-@@ -1242,18 +1241,18 @@ md_assemble (char * str)
- 	  else if (streq (name, "smi"))
- 	    as_fatal (_("smi pseudo instruction should not use a label in imm field"));
-           if(streq (name, "lli") || streq (name, "sli"))
--            opc = str_microblaze_64;
-+            opc = strdup(str_microblaze_64);
-           else if ((microblaze_arch_size == 64) && ((streq (name, "lbui")
- 			|| streq (name, "lhui") || streq (name, "lwi") || streq (name, "sbi")
- 			|| streq (name, "shi") || streq (name, "swi"))))
- 	    {
--              opc = str_microblaze_64;
-+              opc = strdup(str_microblaze_64);
- 	      subtype = opcode->inst_offset_type;
- 	    }
- 	  else if (reg2 == REG_ROSDP)
--	    opc = str_microblaze_ro_anchor;
-+	    opc = strdup(str_microblaze_ro_anchor);
- 	  else if (reg2 == REG_RWSDP)
--	    opc = str_microblaze_rw_anchor;
-+	    opc = strdup(str_microblaze_rw_anchor);
- 	  else
- 	    opc = NULL;
- 	  if (exp.X_md != 0)
-@@ -1718,7 +1717,7 @@ md_assemble (char * str)
-       inst |= (reg1 << RD_LOW) & RD_MASK;
-       inst |= (immed << IMM_LOW) & IMM16_MASK;
-       break;
--	
-+
-     case INST_TYPE_R1_RFSL:
-       if (strcmp (op_end, ""))
-         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Add-initial-port-of-linux-gdbserver.patch
deleted file mode 100644
index 00e5410c31..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Add-initial-port-of-linux-gdbserver.patch
+++ /dev/null
@@ -1,500 +0,0 @@
-From c466a54f6ac8fae44f3e79e33bb782086dc08a2b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 23 Jan 2017 19:07:44 +0530
-Subject: [PATCH 34/40] Add initial port of linux gdbserver add
- gdb_proc_service_h to gdbserver microblaze-linux
-
-gdbserver needs to initialise the microblaze registers
-
-other archs use this step to run a *_arch_setup() to carry out all
-architecture specific setup - may need to add in future
-
- * add linux-ptrace.o to gdbserver configure
- * Update breakpoint opcode
- * fix segfault on connecting gdbserver
- * add microblaze_linux_memory_remove_breakpoint
- * add set_solib_svr4_fetch_link_map_offsets
- * add set_gdbarch_fetch_tls_load_module_address
- * Force reading of r0 as 0, prevent stores
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- gdb/configure.host                   |   3 +
- gdb/features/microblaze-linux.xml    |  12 ++
- gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++
- gdb/microblaze-linux-tdep.c          |  29 +++-
- gdb/microblaze-tdep.c                |  35 ++++-
- gdb/microblaze-tdep.h                |   4 +-
- gdb/regformats/reg-microblaze.dat    |  41 ++++++
- gdbserver/Makefile.in                |   4 +
- gdbserver/configure.srv              |   8 ++
- 9 files changed, 322 insertions(+), 3 deletions(-)
- create mode 100644 gdb/features/microblaze-linux.xml
- create mode 100644 gdb/gdbserver/linux-microblaze-low.c
- create mode 100644 gdb/regformats/reg-microblaze.dat
-
-diff --git a/gdb/configure.host b/gdb/configure.host
-index ce528237291..cf1a08e8b28 100644
---- a/gdb/configure.host
-+++ b/gdb/configure.host
-@@ -65,6 +65,7 @@ hppa*)			gdb_host_cpu=pa ;;
- i[34567]86*)		gdb_host_cpu=i386 ;;
- m68*)			gdb_host_cpu=m68k ;;
- mips*)			gdb_host_cpu=mips ;;
-+microblaze*)		gdb_host_cpu=microblaze ;;
- powerpc* | rs6000)	gdb_host_cpu=powerpc ;;
- sparcv9 | sparc64)	gdb_host_cpu=sparc ;;
- s390*)			gdb_host_cpu=s390 ;;
-@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
- mips*-*-freebsd*)	gdb_host=fbsd ;;
- mips64*-*-openbsd*)	gdb_host=obsd64 ;;
- 
-+microblaze*-*linux*)	gdb_host=linux ;;
-+
- powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
- 			gdb_host=aix ;;
- powerpc*-*-freebsd*)	gdb_host=fbsd ;;
-diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
-new file mode 100644
-index 00000000000..8983e66eb3d
---- /dev/null
-+++ b/gdb/features/microblaze-linux.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <osabi>GNU/Linux</osabi>
-+  <xi:include href="microblaze-core.xml"/>
-+</target>
-diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
-new file mode 100644
-index 00000000000..cba5d6fc585
---- /dev/null
-+++ b/gdb/gdbserver/linux-microblaze-low.c
-@@ -0,0 +1,189 @@
-+/* GNU/Linux/Microblaze specific low level interface, for the remote server for
-+   GDB.
-+   Copyright (C) 1995-2013 Free Software Foundation, Inc.
-+
-+   This file is part of GDB.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
-+
-+#include "server.h"
-+#include "linux-low.h"
-+
-+#include <asm/ptrace.h>
-+#include <sys/procfs.h>
-+#include <sys/ptrace.h>
-+
-+#include "gdb_proc_service.h"
-+
-+static int microblaze_regmap[] =
-+ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
-+  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
-+  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
-+  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
-+  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
-+  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
-+  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
-+  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
-+  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
-+  PT_FSR
-+  };
-+
-+#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
-+
-+/* Defined in auto-generated file microblaze-linux.c.  */
-+void init_registers_microblaze (void);
-+
-+static int
-+microblaze_cannot_store_register (int regno)
-+{
-+  if (microblaze_regmap[regno] == -1 || regno == 0)
-+    return 1;
-+
-+  return 0;
-+}
-+
-+static int
-+microblaze_cannot_fetch_register (int regno)
-+{
-+  return 0;
-+}
-+
-+static CORE_ADDR
-+microblaze_get_pc (struct regcache *regcache)
-+{
-+  unsigned long pc;
-+
-+  collect_register_by_name (regcache, "pc", &pc);
-+  return (CORE_ADDR) pc;
-+}
-+
-+static void
-+microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
-+{
-+  unsigned long newpc = pc;
-+
-+  supply_register_by_name (regcache, "pc", &newpc);
-+}
-+
-+/* dbtrap insn */
-+/* brki r16, 0x18; */
-+static const unsigned long microblaze_breakpoint = 0xba0c0018;
-+#define microblaze_breakpoint_len 4
-+
-+static int
-+microblaze_breakpoint_at (CORE_ADDR where)
-+{
-+  unsigned long insn;
-+
-+  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
-+  if (insn == microblaze_breakpoint)
-+    return 1;
-+  /* If necessary, recognize more trap instructions here.  GDB only uses the
-+     one.  */
-+  return 0;
-+}
-+
-+static CORE_ADDR
-+microblaze_reinsert_addr (struct regcache *regcache)
-+{
-+  unsigned long pc;
-+  collect_register_by_name (regcache, "r15", &pc);
-+  return pc;
-+}
-+
-+#ifdef HAVE_PTRACE_GETREGS
-+
-+static void
-+microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
-+{
-+  int size = register_size (regno);
-+
-+  memset (buf, 0, sizeof (long));
-+
-+  if (size < sizeof (long))
-+    collect_register (regcache, regno, buf + sizeof (long) - size);
-+  else
-+    collect_register (regcache, regno, buf);
-+}
-+
-+static void
-+microblaze_supply_ptrace_register (struct regcache *regcache,
-+			    int regno, const char *buf)
-+{
-+  int size = register_size (regno);
-+
-+  if (regno == 0) {
-+    unsigned long regbuf_0 = 0;
-+    /* clobbering r0 so that it is always 0 as enforced by hardware */
-+    supply_register (regcache, regno, (const char*)&regbuf_0);
-+  } else {
-+      if (size < sizeof (long))
-+        supply_register (regcache, regno, buf + sizeof (long) - size);
-+      else
-+        supply_register (regcache, regno, buf);
-+  }
-+}
-+
-+/* Provide only a fill function for the general register set.  ps_lgetregs
-+   will use this for NPTL support.  */
-+
-+static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
-+{
-+  int i;
-+
-+  for (i = 0; i < 32; i++)
-+    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
-+}
-+
-+static void
-+microblaze_store_gregset (struct regcache *regcache, const void *buf)
-+{
-+  int i;
-+
-+  for (i = 0; i < 32; i++)
-+    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
-+}
-+
-+#endif /* HAVE_PTRACE_GETREGS */
-+
-+struct regset_info target_regsets[] = {
-+#ifdef HAVE_PTRACE_GETREGS
-+  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
-+  { 0, 0, 0, -1, -1, NULL, NULL },
-+#endif /* HAVE_PTRACE_GETREGS */
-+  { 0, 0, 0, -1, -1, NULL, NULL }
-+};
-+
-+struct linux_target_ops the_low_target = {
-+  init_registers_microblaze,
-+  microblaze_num_regs,
-+  microblaze_regmap,
-+  NULL,
-+  microblaze_cannot_fetch_register,
-+  microblaze_cannot_store_register,
-+  NULL, /* fetch_register */
-+  microblaze_get_pc,
-+  microblaze_set_pc,
-+  (const unsigned char *) &microblaze_breakpoint,
-+  microblaze_breakpoint_len,
-+  microblaze_reinsert_addr,
-+  0,
-+  microblaze_breakpoint_at,
-+  NULL,
-+  NULL,
-+  NULL,
-+  NULL,
-+  microblaze_collect_ptrace_register,
-+  microblaze_supply_ptrace_register,
-+};
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index be710bedb64..d15b24d619e 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -37,6 +37,22 @@
- #include "tramp-frame.h"
- #include "linux-tdep.h"
- 
-+static int microblaze_debug_flag = 0;
-+
-+static void
-+microblaze_debug (const char *fmt, ...)
-+{
-+  if (microblaze_debug_flag)
-+    {
-+       va_list args;
-+
-+       va_start (args, fmt);
-+       printf_unfiltered ("MICROBLAZE LINUX: ");
-+       vprintf_unfiltered (fmt, args);
-+       va_end (args);
-+    }
-+}
-+
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
- 					   struct bp_target_info *bp_tgt)
-@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-   /* Determine appropriate breakpoint contents and size for this address.  */
-   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
- 
-+  /* Make sure we see the memory breakpoints.  */
-+  scoped_restore restore_memory
-+    = make_scoped_restore_show_memory_breakpoints (1);
-+
-   val = target_read_memory (addr, old_contents, bplen);
- 
-   /* If our breakpoint is no longer at the address, this means that the
-      program modified the code on us, so it is wrong to put back the
-      old value.  */
-   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
--    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+  {
-+      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
-+  }
- 
-   return val;
- }
-@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
-   /* Trampolines.  */
-   tramp_frame_prepend_unwinder (gdbarch,
- 				&microblaze_linux_sighandler_tramp_frame);
-+
-+  /* Enable TLS support.  */
-+  set_gdbarch_fetch_tls_load_module_address (gdbarch,
-+                                             svr4_fetch_objfile_link_map);
- }
- 
- void _initialize_microblaze_linux_tdep ();
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 5c804133040..5972a69eb5f 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
- constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
- 
- typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
--
-+static int
-+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-+				    struct bp_target_info *bp_tgt)
-+{
-+  CORE_ADDR addr = bp_tgt->placed_address;
-+  const unsigned char *bp;
-+  int val;
-+  int bplen;
-+  gdb_byte old_contents[BREAKPOINT_MAX];
-+
-+  /* Determine appropriate breakpoint contents and size for this address.  */
-+  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
-+  if (bp == NULL)
-+    error (_("Software breakpoints not implemented for this target."));
-+
-+  /* Make sure we see the memory breakpoints.  */
-+  scoped_restore restore_memory
-+    = make_scoped_restore_show_memory_breakpoints (1);
-+
-+  val = target_read_memory (addr, old_contents, bplen);
-+
-+  /* If our breakpoint is no longer at the address, this means that the
-+     program modified the code on us, so it is wrong to put back the
-+     old value.  */
-+  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
-+  {
-+    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
-+  }
-+
-+  return val;
-+}
- 
- /* Allocate and initialize a frame cache.  */
- 
-@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- 				       microblaze_breakpoint::kind_from_pc);
-   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
- 				       microblaze_breakpoint::bp_from_kind);
-+  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
- 
-   set_gdbarch_frame_args_skip (gdbarch, 8);
- 
-@@ -771,4 +803,5 @@ When non-zero, microblaze specific debugging is enabled."),
- 			     NULL,
- 			     &setdebuglist, &showdebuglist);
- 
-+
- }
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 4fbdf9933f0..db0772643dc 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -117,6 +117,8 @@ struct microblaze_frame_cache
- 
- /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
-    Only used for native debugging.  */
--#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
-+#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
-+#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
-+
- 
- #endif /* microblaze-tdep.h */
-diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
-new file mode 100644
-index 00000000000..bd8a4384424
---- /dev/null
-+++ b/gdb/regformats/reg-microblaze.dat
-@@ -0,0 +1,41 @@
-+name:microblaze
-+expedite:r1,pc
-+32:r0
-+32:r1
-+32:r2
-+32:r3
-+32:r4
-+32:r5
-+32:r6
-+32:r7
-+32:r8
-+32:r9
-+32:r10
-+32:r11
-+32:r12
-+32:r13
-+32:r14
-+32:r15
-+32:r16
-+32:r17
-+32:r18
-+32:r19
-+32:r20
-+32:r21
-+32:r22
-+32:r23
-+32:r24
-+32:r25
-+32:r26
-+32:r27
-+32:r28
-+32:r29
-+32:r30
-+32:r31
-+32:pc
-+32:msr
-+32:ear
-+32:esr
-+32:fsr
-+32:slr
-+32:shr
-diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
-index 9d7687be534..8195ccb8ad2 100644
---- a/gdbserver/Makefile.in
-+++ b/gdbserver/Makefile.in
-@@ -183,6 +183,7 @@ SFILES = \
- 	$(srcdir)/linux-ia64-low.cc \
- 	$(srcdir)/linux-low.cc \
- 	$(srcdir)/linux-m68k-low.cc \
-+	$(srcdir)/linux-microblaze-low.c \
- 	$(srcdir)/linux-mips-low.cc \
- 	$(srcdir)/linux-nios2-low.cc \
- 	$(srcdir)/linux-ppc-low.cc \
-@@ -216,6 +217,7 @@ SFILES = \
- 	$(srcdir)/../gdb/nat/linux-namespaces.c \
- 	$(srcdir)/../gdb/nat/linux-osdata.c \
- 	$(srcdir)/../gdb/nat/linux-personality.c \
-+	$(srcdir)/../gdb/nat/microblaze-linux.c \
- 	$(srcdir)/../gdb/nat/mips-linux-watch.c \
- 	$(srcdir)/../gdb/nat/ppc-linux.c \
- 	$(srcdir)/../gdb/nat/riscv-linux-tdesc.c \
-@@ -557,6 +559,8 @@ target/%.o: ../gdb/target/%.c
- 
- %-generated.cc: ../gdb/regformats/rs6000/%.dat $(regdat_sh)
- 	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
-+microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
-+	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
- 
- #
- # Dependency tracking.
-diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
-index 5e33bd9c54d..13d5c6aff87 100644
---- a/gdbserver/configure.srv
-+++ b/gdbserver/configure.srv
-@@ -155,6 +155,14 @@ case "${gdbserver_host}" in
- 			srv_linux_usrregs=yes
- 			srv_linux_thread_db=yes
- 			;;
-+  microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
-+			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
-+			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
-+			srv_xmlfiles="microblaze-linux.xml"
-+			srv_linux_regsets=yes
-+			srv_linux_usrregs=yes
-+			srv_linux_thread_db=yes
-+			;;
-   powerpc*-*-linux*)	srv_regobj="powerpc-32l.o"
- 			srv_regobj="${srv_regobj} powerpc-altivec32l.o"
- 			srv_regobj="${srv_regobj} powerpc-vsx32l.o"
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Initial-port-of-core-reading-support-Added-support-f.patch
new file mode 100644
index 0000000000..3d5f7ae2e1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0034-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -0,0 +1,388 @@
+From bcb8a5479a617eea7b4da869bee5e00d4b750c73 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 24 Jan 2017 14:55:56 +0530
+Subject: [PATCH 34/52] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ bfd/elf32-microblaze.c      | 84 ++++++++++++++++++++++++++++++++++
+ gdb/configure.tgt           |  2 +-
+ gdb/microblaze-linux-tdep.c | 57 +++++++++++++++++++++++
+ gdb/microblaze-tdep.c       | 90 +++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h       | 27 +++++++++++
+ 5 files changed, 259 insertions(+), 1 deletion(-)
+
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index d77710b1f3..7a27e50111 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
+   return _bfd_elf_is_local_label_name (abfd, name);
+ }
+ 
++/* Support for core dump NOTE sections.  */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++  int offset;
++  unsigned int size;
++
++  switch (note->descsz)
++    {
++      default:
++        return FALSE;
++
++      case 228:         /* Linux/MicroBlaze */
++        /* pr_cursig */
++        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++        /* pr_pid */
++        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++        /* pr_reg */
++        offset = 72;
++        size = 50 * 4;
++
++        break;
++    }
++
++  /* Make a ".reg/999" section.  */
++  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++                                          size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++  switch (note->descsz)
++    {
++      default:
++        return FALSE;
++
++      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
++        elf_tdata (abfd)->core->program
++         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++        elf_tdata (abfd)->core->command
++         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++    }
++
++  /* Note that for some reason, a spurious space is tacked
++     onto the end of the args in some (at least one anyway)
++     implementations, so strip it off if it exists.  */
++
++  {
++    char *command = elf_tdata (abfd)->core->command;
++    int n = strlen (command);
++
++    if (0 < n && command[n - 1] == ' ')
++      command[n - 1] = '\0';
++  }
++
++  return TRUE;
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf32_mb_dyn_relocs
++{
++  struct elf32_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
+ /* ELF linker hash entry.  */
+ 
+ struct elf32_mb_link_hash_entry
+@@ -3576,4 +3657,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define elf_backend_size_dynamic_sections	microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
+ 
++#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index d66f01bb9f..2938fddfe8 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -389,7 +389,7 @@ mep-*-*)
+ 
+ microblaze*-linux-*|microblaze*-*-linux*)
+ 	# Target: Xilinx MicroBlaze running Linux
+-	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
++	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
+ 			symfile-mem.o linux-tdep.o"
+ 	gdb_sim=../sim/microblaze/libsim.a
+ 	;;
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index fb8241884b..2725ce1789 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -135,11 +135,54 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
+   microblaze_linux_sighandler_cache_init
+ };
+ 
++const struct microblaze_gregset microblaze_linux_core_gregset;
++
++static void
++microblaze_linux_supply_core_gregset (const struct regset *regset,
++                                   struct regcache *regcache,
++                                   int regnum, const void *gregs, size_t len)
++{
++  microblaze_supply_gregset (&microblaze_linux_core_gregset, regcache,
++                             regnum, gregs);
++}
++
++static void
++microblaze_linux_collect_core_gregset (const struct regset *regset,
++                                    const struct regcache *regcache,
++                                    int regnum, void *gregs, size_t len)
++{
++  microblaze_collect_gregset (&microblaze_linux_core_gregset, regcache,
++                              regnum, gregs);
++}
++
++static void
++microblaze_linux_supply_core_fpregset (const struct regset *regset,
++                                    struct regcache *regcache,
++                                    int regnum, const void *fpregs, size_t len)
++{
++  /* FIXME.  */
++  microblaze_supply_fpregset (regcache, regnum, fpregs);
++}
++
++static void
++microblaze_linux_collect_core_fpregset (const struct regset *regset,
++                                     const struct regcache *regcache,
++                                     int regnum, void *fpregs, size_t len)
++{
++  /* FIXME.  */
++  microblaze_collect_fpregset (regcache, regnum, fpregs);
++}
+ 
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+ 			   struct gdbarch *gdbarch)
+ {
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++  tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
++                                microblaze_linux_collect_core_gregset);
++  tdep->sizeof_gregset = 200;
++
+   linux_init_abi (info, gdbarch);
+ 
+   set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -153,6 +196,20 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   tramp_frame_prepend_unwinder (gdbarch,
+ 				&microblaze_linux_sighandler_tramp_frame);
+ 
++  /* BFD target for core files.  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++  else
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++  /* Shared library handling.  */
++  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
++  set_gdbarch_regset_from_core_section (gdbarch,
++					microblaze_regset_from_core_section);
++
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 443adfb364..1b5cf38e45 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -137,6 +137,14 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++			    struct value **args, CORE_ADDR sp,
++			    int struct_return, CORE_ADDR struct_addr)
++{
++  error (_("store_arguments not implemented"));
++  return sp;
++}
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ 				    struct bp_target_info *bp_tgt)
+@@ -541,6 +549,12 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+   return cache->base;
+ }
+ 
++static const struct frame_unwind *
++microblaze_frame_sniffer (struct frame_info *next_frame)
++{
++  return &microblaze_frame_unwind;
++}
++
+ static const struct frame_base microblaze_frame_base =
+ {
+   &microblaze_frame_unwind,
+@@ -677,6 +691,71 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+                                   tdesc_microblaze_with_stack_protect);
+ }
+ 
++void
++microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++                        struct regcache *regcache,
++                        int regnum, const void *gregs)
++{
++  unsigned int *regs = gregs;
++  if (regnum >= 0)
++    regcache_raw_supply (regcache, regnum, regs + regnum);
++
++  if (regnum == -1) {
++    int i;
++
++    for (i = 0; i < 50; i++) {
++      regcache_raw_supply (regcache, i, regs + i);
++    }
++  }
++}
++
++
++void
++microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++                         const struct regcache *regcache,
++                         int regnum, void *gregs)
++{
++   /* FIXME.  */
++}
++
++void
++microblaze_supply_fpregset (struct regcache *regcache,
++                         int regnum, const void *fpregs)
++{
++   /* FIXME.  */
++}
++
++void
++microblaze_collect_fpregset (const struct regcache *regcache,
++                          int regnum, void *fpregs)
++{
++   /* FIXME.  */
++}
++
++
++/* Return the appropriate register set for the core section identified
++   by SECT_NAME and SECT_SIZE.  */
++
++const struct regset *
++microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++                                     const char *sect_name, size_t sect_size)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++  microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
++
++  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
++    return tdep->gregset;
++
++  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
++    return tdep->fpregset;
++
++  microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
++  return NULL;
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -733,6 +812,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   tdep = XCNEW (struct gdbarch_tdep);
+   gdbarch = gdbarch_alloc (&info, tdep);
+ 
++  tdep->gregset = NULL;
++  tdep->sizeof_gregset = 0;
++  tdep->fpregset = NULL;
++  tdep->sizeof_fpregset = 0;
+   set_gdbarch_long_double_bit (gdbarch, 128);
+ 
+   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -781,6 +864,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+   if (tdesc_data != NULL)
+     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
++  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++
++  /* If we have register sets, enable the generic core file support.  */
++  if (tdep->gregset) {
++      set_gdbarch_regset_from_core_section (gdbarch,
++                                          microblaze_regset_from_core_section);
++  }
+ 
+   return gdbarch;
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index db0772643d..de66a05cab 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+ 
+ 
+ /* Microblaze architecture-specific information.  */
++struct microblaze_gregset
++{
++   unsigned int gregs[32];
++   unsigned int fpregs[32];
++   unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++  int dummy;		// declare something.
++
++  /* Register sets.  */
++  struct regset *gregset;
++  size_t sizeof_gregset;
++  struct regset *fpregset;
++  size_t sizeof_fpregset;
+ };
+ 
+ /* Register numbers.  */
+@@ -120,5 +134,18 @@ struct microblaze_frame_cache
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+ 
++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++                                    struct regcache *regcache,
++                                    int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++                                     const struct regcache *regcache,
++                                     int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++                                     int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++                                      int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++                                     const char *sect_name, size_t sect_size);
+ 
+ #endif /* microblaze-tdep.h */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 0000000000..4c26f25967
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,40 @@
+From bc2b702d7f73a231bd67c60465137fe37f67479a Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 35/52] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+diff --git a/gdb/frame.c b/gdb/frame.c
+index ff27b9f00e..bf931b370c 100644
+--- a/gdb/frame.c
++++ b/gdb/frame.c
+@@ -1263,12 +1263,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
+ 	  else
+ 	    {
+ 	      int i;
+-	      const gdb_byte *buf = value_contents (value);
++	      const gdb_byte *buf = NULL;
++	      if (value_entirely_available(value)) {
++	        buf = value_contents (value);
++	      }
+ 
+ 	      fprintf_unfiltered (gdb_stdlog, " bytes=");
+ 	      fprintf_unfiltered (gdb_stdlog, "[");
+-	      for (i = 0; i < register_size (gdbarch, regnum); i++)
+-		fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++	      if (buf != NULL) {
++	        for (i = 0; i < register_size (gdbarch, regnum); i++)
++		  fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++	      } else {
++	        fprintf_unfiltered (gdb_stdlog, "unavailable");
++	      }
+ 	      fprintf_unfiltered (gdb_stdlog, "]");
+ 	    }
+ 	}
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Initial-port-of-core-reading-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Initial-port-of-core-reading-support.patch
deleted file mode 100644
index 4eeeb7da7a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0035-Initial-port-of-core-reading-support.patch
+++ /dev/null
@@ -1,298 +0,0 @@
-From b6c01467951b83f9cca621ffeb89151eba1d73a1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 24 Jan 2017 14:55:56 +0530
-Subject: [PATCH 35/40] Initial port of core reading support Added support for
- reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
- information for rebuilding ".reg" sections of core dumps at run time.
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- bfd/elf32-microblaze.c      | 84 +++++++++++++++++++++++++++++++++++++
- gdb/configure.tgt           |  2 +-
- gdb/microblaze-linux-tdep.c | 17 +++++++-
- gdb/microblaze-tdep.c       | 48 +++++++++++++++++++++
- gdb/microblaze-tdep.h       | 27 ++++++++++++
- 5 files changed, 176 insertions(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index bf09c68afd9..a4b15882d77 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
-   return _bfd_elf_is_local_label_name (abfd, name);
- }
- 
-+/* Support for core dump NOTE sections.  */
-+static bfd_boolean
-+microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
-+{
-+  int offset;
-+  unsigned int size;
-+
-+  switch (note->descsz)
-+    {
-+      default:
-+        return FALSE;
-+
-+      case 228:         /* Linux/MicroBlaze */
-+        /* pr_cursig */
-+        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
-+
-+        /* pr_pid */
-+        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
-+
-+        /* pr_reg */
-+        offset = 72;
-+        size = 50 * 4;
-+
-+        break;
-+    }
-+
-+  /* Make a ".reg/999" section.  */
-+  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
-+                                          size, note->descpos + offset);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
-+{
-+  switch (note->descsz)
-+    {
-+      default:
-+        return FALSE;
-+
-+      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
-+        elf_tdata (abfd)->core->program
-+         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
-+        elf_tdata (abfd)->core->command
-+         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
-+    }
-+
-+  /* Note that for some reason, a spurious space is tacked
-+     onto the end of the args in some (at least one anyway)
-+     implementations, so strip it off if it exists.  */
-+
-+  {
-+    char *command = elf_tdata (abfd)->core->command;
-+    int n = strlen (command);
-+
-+    if (0 < n && command[n - 1] == ' ')
-+      command[n - 1] = '\0';
-+  }
-+
-+  return TRUE;
-+}
-+
-+/* The microblaze linker (like many others) needs to keep track of
-+   the number of relocs that it decides to copy as dynamic relocs in
-+   check_relocs for each symbol. This is so that it can later discard
-+   them if they are found to be unnecessary.  We store the information
-+   in a field extending the regular ELF linker hash table.  */
-+
-+struct elf32_mb_dyn_relocs
-+{
-+  struct elf32_mb_dyn_relocs *next;
-+
-+  /* The input section of the reloc.  */
-+  asection *sec;
-+
-+  /* Total number of relocs copied for the input section.  */
-+  bfd_size_type count;
-+
-+  /* Number of pc-relative relocs copied for the input section.  */
-+  bfd_size_type pc_count;
-+};
-+
- /* ELF linker hash entry.  */
- 
- struct elf32_mb_link_hash_entry
-@@ -3574,4 +3655,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
- #define elf_backend_size_dynamic_sections	microblaze_elf_size_dynamic_sections
- #define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
- 
-+#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
-+#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
-+
- #include "elf32-target.h"
-diff --git a/gdb/configure.tgt b/gdb/configure.tgt
-index d66f01bb9f7..2938fddfe82 100644
---- a/gdb/configure.tgt
-+++ b/gdb/configure.tgt
-@@ -389,7 +389,7 @@ mep-*-*)
- 
- microblaze*-linux-*|microblaze*-*-linux*)
- 	# Target: Xilinx MicroBlaze running Linux
--	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
-+	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
- 			symfile-mem.o linux-tdep.o"
- 	gdb_sim=../sim/microblaze/libsim.a
- 	;;
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index d15b24d619e..0d5c08d24f6 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -36,6 +36,7 @@
- #include "frame-unwind.h"
- #include "tramp-frame.h"
- #include "linux-tdep.h"
-+#include "glibc-tdep.h"
- 
- static int microblaze_debug_flag = 0;
- 
-@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
-   microblaze_linux_sighandler_cache_init
- };
- 
--
- static void
- microblaze_linux_init_abi (struct gdbarch_info info,
- 			   struct gdbarch *gdbarch)
- {
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+
-+  tdep->sizeof_gregset = 200;
-+
-   linux_init_abi (info, gdbarch);
- 
-   set_gdbarch_memory_remove_breakpoint (gdbarch,
-@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
-   tramp_frame_prepend_unwinder (gdbarch,
- 				&microblaze_linux_sighandler_tramp_frame);
- 
-+  /* BFD target for core files.  */
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+  else
-+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+
-+
-+  /* Shared library handling.  */
-+  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
-+  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
-+
-   /* Enable TLS support.  */
-   set_gdbarch_fetch_tls_load_module_address (gdbarch,
-                                              svr4_fetch_objfile_link_map);
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 5972a69eb5f..7462a1f7ce6 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -677,6 +677,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
-                                   tdesc_microblaze_with_stack_protect);
- }
- 
-+void
-+microblaze_supply_gregset (const struct regset *regset,
-+                        struct regcache *regcache,
-+                        int regnum, const void *gregs)
-+{
-+  const unsigned int *regs = (const unsigned int *)gregs;
-+  if (regnum >= 0)
-+    regcache->raw_supply (regnum, regs + regnum);
-+
-+  if (regnum == -1) {
-+    int i;
-+
-+    for (i = 0; i < 50; i++) {
-+      regcache->raw_supply (i, regs + i);
-+    }
-+  }
-+}
-+
-+
-+/* Return the appropriate register set for the core section identified
-+   by SECT_NAME and SECT_SIZE.  */
-+
-+static void
-+microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
-+                                     iterate_over_regset_sections_cb *cb,
-+                                     void *cb_data,
-+                                     const struct regcache *regcache)
-+{
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+
-+  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
-+
-+  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
-+}
-+
-+
-+
- static struct gdbarch *
- microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- {
-@@ -733,6 +770,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   tdep = XCNEW (struct gdbarch_tdep);
-   gdbarch = gdbarch_alloc (&info, tdep);
- 
-+  tdep->gregset = NULL;
-+  tdep->sizeof_gregset = 0;
-+  tdep->fpregset = NULL;
-+  tdep->sizeof_fpregset = 0;
-   set_gdbarch_long_double_bit (gdbarch, 128);
- 
-   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
-@@ -781,6 +822,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
-   if (tdesc_data != NULL)
-     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
-+  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
-+
-+  /* If we have register sets, enable the generic core file support.  */
-+  if (tdep->gregset) {
-+    set_gdbarch_iterate_over_regset_sections (gdbarch,
-+                                          microblaze_iterate_over_regset_sections);
-+  }
- 
-   return gdbarch;
- }
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index db0772643dc..8f41ba19351 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -22,8 +22,22 @@
- 
- 
- /* Microblaze architecture-specific information.  */
-+struct microblaze_gregset
-+{
-+   unsigned int gregs[32];
-+   unsigned int fpregs[32];
-+   unsigned int pregs[16];
-+};
-+
- struct gdbarch_tdep
- {
-+  int dummy;		// declare something.
-+
-+  /* Register sets.  */
-+  struct regset *gregset;
-+  size_t sizeof_gregset;
-+  struct regset *fpregset;
-+  size_t sizeof_fpregset;
- };
- 
- /* Register numbers.  */
-@@ -120,5 +134,18 @@ struct microblaze_frame_cache
- #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
- #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
- 
-+extern void microblaze_supply_gregset (const struct regset *regset,
-+                                    struct regcache *regcache,
-+                                    int regnum, const void *gregs);
-+extern void microblaze_collect_gregset (const struct regset *regset,
-+                                     const struct regcache *regcache,
-+                                     int regnum, void *gregs);
-+extern void microblaze_supply_fpregset (struct regcache *regcache,
-+                                     int regnum, const void *fpregs);
-+extern void microblaze_collect_fpregset (const struct regcache *regcache,
-+                                      int regnum, void *fpregs);
-+
-+extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
-+                                     const char *sect_name, size_t sect_size);
- 
- #endif /* microblaze-tdep.h */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-Fix-debug-message-when-register-is-unavailable.patch
deleted file mode 100644
index 79d08da929..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-Fix-debug-message-when-register-is-unavailable.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From dc76254a84fa1086983aefe9db4d8f94b42efb9b Mon Sep 17 00:00:00 2001
-From: Nathan Rossi <nathan.rossi@petalogix.com>
-Date: Tue, 8 May 2012 18:11:17 +1000
-Subject: [PATCH 36/40] Fix debug message when register is unavailable
-
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- gdb/frame.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
-diff --git a/gdb/frame.c b/gdb/frame.c
-index ff27b9f00e9..bf931b370c9 100644
---- a/gdb/frame.c
-+++ b/gdb/frame.c
-@@ -1263,12 +1263,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
- 	  else
- 	    {
- 	      int i;
--	      const gdb_byte *buf = value_contents (value);
-+	      const gdb_byte *buf = NULL;
-+	      if (value_entirely_available(value)) {
-+	        buf = value_contents (value);
-+	      }
- 
- 	      fprintf_unfiltered (gdb_stdlog, " bytes=");
- 	      fprintf_unfiltered (gdb_stdlog, "[");
--	      for (i = 0; i < register_size (gdbarch, regnum); i++)
--		fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
-+	      if (buf != NULL) {
-+	        for (i = 0; i < register_size (gdbarch, regnum); i++)
-+		  fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
-+	      } else {
-+	        fprintf_unfiltered (gdb_stdlog, "unavailable");
-+	      }
- 	      fprintf_unfiltered (gdb_stdlog, "]");
- 	    }
- 	}
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver.patch
new file mode 100644
index 0000000000..81f55f765f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0036-revert-master-rebase-changes-to-gdbserver.patch
@@ -0,0 +1,31 @@
+From c84c1a62142bcd18c242ec476539f0c505285d6c Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 22 Jul 2013 11:16:05 +1000
+Subject: [PATCH 36/52] revert master-rebase changes to gdbserver
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdbserver/configure.srv | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
+index 5e33bd9c54..7e81388850 100644
+--- a/gdbserver/configure.srv
++++ b/gdbserver/configure.srv
+@@ -155,6 +155,13 @@ case "${gdbserver_host}" in
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+ 			;;
++  microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
++			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
++			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++			srv_linux_regsets=yes
++			srv_linux_usrregs=yes
++			srv_linux_thread_db=yes
++			;;
+   powerpc*-*-linux*)	srv_regobj="powerpc-32l.o"
+ 			srv_regobj="${srv_regobj} powerpc-altivec32l.o"
+ 			srv_regobj="${srv_regobj} powerpc-vsx32l.o"
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
deleted file mode 100644
index 80b70fcc4e..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 23376adc47cf72e46a1edf99e7fbc40164d39cd6 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Mon, 16 Dec 2013 16:37:32 +1000
-Subject: [PATCH 37/40] microblaze: Add build_gdbserver=yes to top level
- configure.tgt
-
-For Microblaze linux toolchains, set the build_gdbserver=yes
-to allow driving gdbserver configuration from the upper level
-
-This patch has been absorbed into the original patch to add
-linux gdbserver support for Microblaze.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gdb/configure.tgt | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gdb/configure.tgt b/gdb/configure.tgt
-index 2938fddfe82..ac2d35a9917 100644
---- a/gdb/configure.tgt
-+++ b/gdb/configure.tgt
-@@ -397,6 +397,7 @@ microblaze*-*-*)
- 	# Target: Xilinx MicroBlaze running standalone
- 	gdb_target_obs="microblaze-tdep.o"
- 	gdb_sim=../sim/microblaze/libsim.a
-+	build_gdbserver=yes
- 	;;
- 
- mips*-*-linux*)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
new file mode 100644
index 0000000000..24ae7a8c5d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
@@ -0,0 +1,36 @@
+From 06f1e66daaa1c8a2e1e43254a66f35840945e63b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 30 Apr 2018 17:09:55 +0530
+Subject: [PATCH 37/52] revert master-rebase changes to gdbserver , previous
+ commit typo's
+
+Note: This _WILL NOT WORK_, the format of the files in gdbserver have changed!
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ gdbserver/Makefile.in | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
+index 9d7687be53..df354d636c 100644
+--- a/gdbserver/Makefile.in
++++ b/gdbserver/Makefile.in
+@@ -183,6 +183,7 @@ SFILES = \
+ 	$(srcdir)/linux-ia64-low.cc \
+ 	$(srcdir)/linux-low.cc \
+ 	$(srcdir)/linux-m68k-low.cc \
++	$(srcdir)/linux-microblaze-low.c \
+ 	$(srcdir)/linux-mips-low.cc \
+ 	$(srcdir)/linux-nios2-low.cc \
+ 	$(srcdir)/linux-ppc-low.cc \
+@@ -217,6 +218,7 @@ SFILES = \
+ 	$(srcdir)/../gdb/nat/linux-osdata.c \
+ 	$(srcdir)/../gdb/nat/linux-personality.c \
+ 	$(srcdir)/../gdb/nat/mips-linux-watch.c \
++	$(srcdir)/../gdb/nat/microblaze-linux.c \
+ 	$(srcdir)/../gdb/nat/ppc-linux.c \
+ 	$(srcdir)/../gdb/nat/riscv-linux-tdesc.c \
+ 	$(srcdir)/../gdb/nat/fork-inferior.c \
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-Initial-support-for-native-gdb.patch
deleted file mode 100644
index 9360bc5aed..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-Initial-support-for-native-gdb.patch
+++ /dev/null
@@ -1,492 +0,0 @@
-From f34017e4cec8ad571accfd964187ab1f2db8de7f Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@petalogix.com>
-Date: Fri, 20 Jul 2012 15:18:35 +1000
-Subject: [PATCH 38/40] Initial support for native gdb
-
-microblaze: Follow PPC method of getting setting registers
-using PTRACE PEEK/POKE
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
----
- gdb/Makefile.in                |   2 +
- gdb/config/microblaze/linux.mh |   9 +
- gdb/microblaze-linux-nat.c     | 431 +++++++++++++++++++++++++++++++++
- 3 files changed, 442 insertions(+)
- create mode 100644 gdb/config/microblaze/linux.mh
- create mode 100644 gdb/microblaze-linux-nat.c
-
-diff --git a/gdb/Makefile.in b/gdb/Makefile.in
-index 9ae9fe2d1e1..a44464b9830 100644
---- a/gdb/Makefile.in
-+++ b/gdb/Makefile.in
-@@ -1328,6 +1328,7 @@ HFILES_NO_SRCDIR = \
- 	memory-map.h \
- 	memrange.h \
- 	microblaze-tdep.h \
-+	microblaze-linux-tdep.h \
- 	mips-linux-tdep.h \
- 	mips-nbsd-tdep.h \
- 	mips-tdep.h \
-@@ -2207,6 +2208,7 @@ ALLDEPFILES = \
- 	m68k-tdep.c \
- 	microblaze-linux-tdep.c \
- 	microblaze-tdep.c \
-+	microblaze-linux-nat.c \
- 	mingw-hdep.c \
- 	mips-fbsd-nat.c \
- 	mips-fbsd-tdep.c \
-diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
-new file mode 100644
-index 00000000000..a4eaf540e1d
---- /dev/null
-+++ b/gdb/config/microblaze/linux.mh
-@@ -0,0 +1,9 @@
-+# Host: Microblaze, running Linux
-+
-+NAT_FILE= config/nm-linux.h
-+NATDEPFILES= inf-ptrace.o fork-child.o \
-+	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
-+	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
-+NAT_CDEPS = $(srcdir)/proc-service.list
-+
-+LOADLIBES = -ldl $(RDYNAMIC)
-diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
-new file mode 100644
-index 00000000000..e9b8c9c5221
---- /dev/null
-+++ b/gdb/microblaze-linux-nat.c
-@@ -0,0 +1,431 @@
-+/* Microblaze GNU/Linux native support.
-+
-+   Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
-+   Software Foundation, Inc.
-+
-+   This file is part of GDB.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
-+
-+#include "defs.h"
-+#include "arch-utils.h"
-+#include "dis-asm.h"
-+#include "frame.h"
-+#include "trad-frame.h"
-+#include "symtab.h"
-+#include "value.h"
-+#include "gdbcmd.h"
-+#include "breakpoint.h"
-+#include "inferior.h"
-+#include "regcache.h"
-+#include "target.h"
-+#include "frame.h"
-+#include "frame-base.h"
-+#include "frame-unwind.h"
-+#include "dwarf2-frame.h"
-+#include "osabi.h"
-+
-+#include "gdb_assert.h"
-+#include "gdb_string.h"
-+#include "target-descriptions.h"
-+#include "opcodes/microblaze-opcm.h"
-+#include "opcodes/microblaze-dis.h"
-+
-+#include "linux-nat.h"
-+#include "target-descriptions.h"
-+
-+#include <sys/user.h>
-+#include <sys/utsname.h>
-+#include <sys/procfs.h>
-+#include <sys/ptrace.h>
-+
-+/* Prototypes for supply_gregset etc. */
-+#include "gregset.h"
-+
-+#include "microblaze-tdep.h"
-+
-+#include <elf/common.h>
-+#include "auxv.h"
-+
-+/* Defines ps_err_e, struct ps_prochandle.  */
-+#include "gdb_proc_service.h"
-+
-+/* On GNU/Linux, threads are implemented as pseudo-processes, in which
-+   case we may be tracing more than one process at a time.  In that
-+   case, inferior_ptid will contain the main process ID and the
-+   individual thread (process) ID.  get_thread_id () is used to get
-+   the thread id if it's available, and the process id otherwise.  */
-+
-+int
-+get_thread_id (ptid_t ptid)
-+{
-+  int tid = TIDGET (ptid);
-+  if (0 == tid)
-+    tid = PIDGET (ptid);
-+  return tid;
-+}
-+
-+#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
-+
-+/* Non-zero if our kernel may support the PTRACE_GETREGS and
-+   PTRACE_SETREGS requests, for reading and writing the
-+   general-purpose registers.  Zero if we've tried one of
-+   them and gotten an error.  */
-+int have_ptrace_getsetregs = 1;
-+
-+static int
-+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
-+{
-+  int u_addr = -1;
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
-+     interface, and not the wordsize of the program's ABI.  */
-+  int wordsize = sizeof (long);
-+
-+  /* General purpose registers occupy 1 slot each in the buffer.  */
-+  if (regno >= MICROBLAZE_R0_REGNUM
-+      && regno <= MICROBLAZE_FSR_REGNUM)
-+    u_addr = (regno * wordsize);
-+
-+  return u_addr;
-+}
-+
-+
-+static void
-+fetch_register (struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* This isn't really an address.  But ptrace thinks of it as one.  */
-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
-+  int bytes_transferred;
-+  unsigned int offset;         /* Offset of registers within the u area.  */
-+  char buf[MAX_REGISTER_SIZE];
-+
-+  if (regaddr == -1)
-+  {
-+    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
-+    regcache_raw_supply (regcache, regno, buf);
-+    return;
-+  }
-+
-+  /* Read the raw register using sizeof(long) sized chunks.  On a
-+     32-bit platform, 64-bit floating-point registers will require two
-+     transfers.  */
-+  for (bytes_transferred = 0;
-+       bytes_transferred < register_size (gdbarch, regno);
-+       bytes_transferred += sizeof (long))
-+  {
-+    long l;
-+
-+    errno = 0;
-+    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
-+    regaddr += sizeof (long);
-+    if (errno != 0)
-+    {
-+      char message[128];
-+      sprintf (message, "reading register %s (#%d)",
-+               gdbarch_register_name (gdbarch, regno), regno);
-+      perror_with_name (message);
-+    }
-+    memcpy (&buf[bytes_transferred], &l, sizeof (l));
-+  }
-+
-+  /* Now supply the register.  Keep in mind that the regcache's idea
-+     of the register's size may not be a multiple of sizeof
-+     (long).  */
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
-+  {
-+    /* Little-endian values are always found at the left end of the
-+       bytes transferred.  */
-+    regcache_raw_supply (regcache, regno, buf);
-+  }
-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+  {
-+    /* Big-endian values are found at the right end of the bytes
-+       transferred.  */
-+    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
-+    regcache_raw_supply (regcache, regno, buf + padding);
-+  }
-+  else
-+    internal_error (__FILE__, __LINE__,
-+                    _("fetch_register: unexpected byte order: %d"),
-+                    gdbarch_byte_order (gdbarch));
-+}
-+
-+/* This function actually issues the request to ptrace, telling
-+   it to get all general-purpose registers and put them into the
-+   specified regset.
-+
-+   If the ptrace request does not exist, this function returns 0
-+   and properly sets the have_ptrace_* flag.  If the request fails,
-+   this function calls perror_with_name.  Otherwise, if the request
-+   succeeds, then the regcache gets filled and 1 is returned.  */
-+static int
-+fetch_all_gp_regs (struct regcache *regcache, int tid)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  gdb_gregset_t gregset;
-+
-+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
-+  {
-+    if (errno == EIO)
-+    {
-+      have_ptrace_getsetregs = 0;
-+      return 0;
-+    }
-+    perror_with_name (_("Couldn't get general-purpose registers."));
-+  }
-+
-+  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
-+
-+  return 1;
-+}
-+
-+
-+/* This is a wrapper for the fetch_all_gp_regs function.  It is
-+   responsible for verifying if this target has the ptrace request
-+   that can be used to fetch all general-purpose registers at one
-+   shot.  If it doesn't, then we should fetch them using the
-+   old-fashioned way, which is to iterate over the registers and
-+   request them one by one.  */
-+static void
-+fetch_gp_regs (struct regcache *regcache, int tid)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  int i;
-+
-+  if (have_ptrace_getsetregs)
-+    if (fetch_all_gp_regs (regcache, tid))
-+      return;
-+
-+  /* If we've hit this point, it doesn't really matter which
-+     architecture we are using.  We just need to read the
-+     registers in the "old-fashioned way".  */
-+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
-+    fetch_register (regcache, tid, i);
-+}
-+
-+
-+static void
-+store_register (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* This isn't really an address.  But ptrace thinks of it as one.  */
-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
-+  int i;
-+  size_t bytes_to_transfer;
-+  char buf[MAX_REGISTER_SIZE];
-+
-+  if (regaddr == -1)
-+    return;
-+
-+  /* First collect the register.  Keep in mind that the regcache's
-+     idea of the register's size may not be a multiple of sizeof
-+     (long).  */
-+  memset (buf, 0, sizeof buf);
-+  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
-+  {
-+    /* Little-endian values always sit at the left end of the buffer.  */
-+    regcache_raw_collect (regcache, regno, buf);
-+  }
-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+  {
-+    /* Big-endian values sit at the right end of the buffer.  */
-+    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
-+    regcache_raw_collect (regcache, regno, buf + padding);
-+  }
-+
-+  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
-+  {
-+    long l;
-+
-+    memcpy (&l, &buf[i], sizeof (l));
-+    errno = 0;
-+    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
-+    regaddr += sizeof (long);
-+
-+    if (errno != 0)
-+    {
-+      char message[128];
-+      sprintf (message, "writing register %s (#%d)",
-+               gdbarch_register_name (gdbarch, regno), regno);
-+      perror_with_name (message);
-+    }
-+  }
-+}
-+
-+/* This function actually issues the request to ptrace, telling
-+   it to store all general-purpose registers present in the specified
-+   regset.
-+
-+   If the ptrace request does not exist, this function returns 0
-+   and properly sets the have_ptrace_* flag.  If the request fails,
-+   this function calls perror_with_name.  Otherwise, if the request
-+   succeeds, then the regcache is stored and 1 is returned.  */
-+static int
-+store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  gdb_gregset_t gregset;
-+
-+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
-+    {
-+      if (errno == EIO)
-+      {
-+        have_ptrace_getsetregs = 0;
-+        return 0;
-+      }
-+      perror_with_name (_("Couldn't get general-purpose registers."));
-+    }
-+
-+  fill_gregset (regcache, &gregset, regno);
-+
-+  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
-+    {
-+      if (errno == EIO)
-+      {
-+        have_ptrace_getsetregs = 0;
-+        return 0;
-+      }
-+      perror_with_name (_("Couldn't set general-purpose registers."));
-+    }
-+
-+  return 1;
-+}
-+
-+/* This is a wrapper for the store_all_gp_regs function.  It is
-+   responsible for verifying if this target has the ptrace request
-+   that can be used to store all general-purpose registers at one
-+   shot.  If it doesn't, then we should store them using the
-+   old-fashioned way, which is to iterate over the registers and
-+   store them one by one.  */
-+static void
-+store_gp_regs (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  int i;
-+
-+  if (have_ptrace_getsetregs)
-+    if (store_all_gp_regs (regcache, tid, regno))
-+      return;
-+
-+  /* If we hit this point, it doesn't really matter which
-+     architecture we are using.  We just need to store the
-+     registers in the "old-fashioned way".  */
-+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
-+    store_register (regcache, tid, i);
-+}
-+
-+
-+/* Fetch registers from the child process.  Fetch all registers if
-+   regno == -1, otherwise fetch all general registers or all floating
-+   point registers depending upon the value of regno.  */
-+
-+static void
-+microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
-+				    struct regcache *regcache, int regno)
-+{
-+  /* Get the thread id for the ptrace call.  */
-+  int tid = GET_THREAD_ID (inferior_ptid);
-+
-+  if (regno == -1)
-+    fetch_gp_regs (regcache, tid);
-+  else
-+    fetch_register (regcache, tid, regno);
-+}
-+
-+/* Store registers back into the inferior.  Store all registers if
-+   regno == -1, otherwise store all general registers or all floating
-+   point registers depending upon the value of regno.  */
-+
-+static void
-+microblaze_linux_store_inferior_registers (struct target_ops *ops,
-+				    struct regcache *regcache, int regno)
-+{
-+  /* Get the thread id for the ptrace call.  */
-+  int tid = GET_THREAD_ID (inferior_ptid);
-+
-+  if (regno >= 0)
-+    store_register (regcache, tid, regno);
-+  else
-+    store_gp_regs (regcache, tid, -1);
-+}
-+
-+/* Wrapper functions for the standard regset handling, used by
-+   thread debugging.  */
-+
-+void
-+fill_gregset (const struct regcache *regcache,
-+	      gdb_gregset_t *gregsetp, int regno)
-+{
-+  microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
-+}
-+
-+void
-+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
-+{
-+  microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
-+}
-+
-+void
-+fill_fpregset (const struct regcache *regcache,
-+	      gdb_fpregset_t *fpregsetp, int regno)
-+{
-+  /* FIXME. */
-+}
-+
-+void
-+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
-+{
-+  /* FIXME. */
-+}
-+
-+static const struct target_desc *
-+microblaze_linux_read_description (struct target_ops *ops)
-+{
-+  CORE_ADDR microblaze_hwcap = 0;
-+
-+  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
-+    return NULL;
-+
-+  return NULL;
-+}
-+
-+
-+void _initialize_microblaze_linux_nat (void);
-+
-+void
-+_initialize_microblaze_linux_nat (void)
-+{
-+  struct target_ops *t;
-+
-+  /* Fill in the generic GNU/Linux methods.  */
-+  t = linux_target ();
-+
-+  /* Add our register access methods.  */
-+  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
-+  t->to_store_registers = microblaze_linux_store_inferior_registers;
-+
-+  t->to_read_description = microblaze_linux_read_description;
-+
-+  /* Register the target.  */
-+  linux_nat_add_target (t);
-+}
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
new file mode 100644
index 0000000000..dede70e8fc
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
@@ -0,0 +1,32 @@
+From 463a2d331ab68484913a2957614e852eac793583 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 16 Dec 2013 16:37:32 +1000
+Subject: [PATCH 38/52] microblaze: Add build_gdbserver=yes to top level
+ configure.tgt
+
+For Microblaze linux toolchains, set the build_gdbserver=yes
+to allow driving gdbserver configuration from the upper level
+
+This patch has been absorbed into the original patch to add
+linux gdbserver support for Microblaze.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/configure.tgt | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gdb/configure.tgt b/gdb/configure.tgt
+index 2938fddfe8..ac2d35a991 100644
+--- a/gdb/configure.tgt
++++ b/gdb/configure.tgt
+@@ -397,6 +397,7 @@ microblaze*-*-*)
+ 	# Target: Xilinx MicroBlaze running standalone
+ 	gdb_target_obs="microblaze-tdep.o"
+ 	gdb_sim=../sim/microblaze/libsim.a
++	build_gdbserver=yes
+ 	;;
+ 
+ mips*-*-linux*)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch
deleted file mode 100644
index 136291f268..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Fixing-the-issues-related-to-GDB-7.12.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From 1a493a6fc3bebb50d9679a4d11709676f933ab04 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 17 Feb 2017 14:09:40 +0530
-Subject: [PATCH 39/40] Fixing the issues related to GDB-7.12
-
-added all the required function which are new in 7.12 and removed
-few deprecated functions from 7.6
----
- gdb/config/microblaze/linux.mh       |  4 +-
- gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++----
- gdb/microblaze-tdep.h                |  1 +
- gdbserver/configure.srv              |  3 +-
- 4 files changed, 89 insertions(+), 16 deletions(-)
-
-diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
-index a4eaf540e1d..74a53b854a4 100644
---- a/gdb/config/microblaze/linux.mh
-+++ b/gdb/config/microblaze/linux.mh
-@@ -1,9 +1,11 @@
- # Host: Microblaze, running Linux
- 
-+#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
- NAT_FILE= config/nm-linux.h
- NATDEPFILES= inf-ptrace.o fork-child.o \
- 	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
--	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
-+	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
-+	linux-waitpid.o linux-personality.o linux-namespaces.o
- NAT_CDEPS = $(srcdir)/proc-service.list
- 
- LOADLIBES = -ldl $(RDYNAMIC)
-diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
-index cba5d6fc585..a2733f3c21c 100644
---- a/gdb/gdbserver/linux-microblaze-low.c
-+++ b/gdb/gdbserver/linux-microblaze-low.c
-@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
-   PT_FSR
-   };
- 
--#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
-+#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
- 
- /* Defined in auto-generated file microblaze-linux.c.  */
- void init_registers_microblaze (void);
-+extern const struct target_desc *tdesc_microblaze;
- 
- static int
- microblaze_cannot_store_register (int regno)
-@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
- static const unsigned long microblaze_breakpoint = 0xba0c0018;
- #define microblaze_breakpoint_len 4
- 
-+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
-+
-+static const gdb_byte *
-+microblaze_sw_breakpoint_from_kind (int kind, int *size)
-+{
-+  *size = microblaze_breakpoint_len;
-+  return (const gdb_byte *) &microblaze_breakpoint;
-+}
-+
- static int
- microblaze_breakpoint_at (CORE_ADDR where)
- {
-@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
- static void
- microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
- {
--  int size = register_size (regno);
-+  int size = register_size (regcache->tdesc, regno);
- 
-   memset (buf, 0, sizeof (long));
- 
-@@ -121,7 +131,7 @@ static void
- microblaze_supply_ptrace_register (struct regcache *regcache,
- 			    int regno, const char *buf)
- {
--  int size = register_size (regno);
-+  int size = register_size (regcache->tdesc, regno);
- 
-   if (regno == 0) {
-     unsigned long regbuf_0 = 0;
-@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
- 
- #endif /* HAVE_PTRACE_GETREGS */
- 
--struct regset_info target_regsets[] = {
-+static struct regset_info microblaze_regsets[] = {
- #ifdef HAVE_PTRACE_GETREGS
-   { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
--  { 0, 0, 0, -1, -1, NULL, NULL },
-+  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
- #endif /* HAVE_PTRACE_GETREGS */
--  { 0, 0, 0, -1, -1, NULL, NULL }
-+  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
-+  NULL_REGSET
- };
- 
-+static struct usrregs_info microblaze_usrregs_info =
-+  {
-+    microblaze_num_regs,
-+    microblaze_regmap,
-+  };
-+
-+static struct regsets_info microblaze_regsets_info =
-+  {
-+    microblaze_regsets, /* regsets */
-+    0, /* num_regsets */
-+    NULL, /* disabled_regsets */
-+  };
-+
-+static struct regs_info regs_info =
-+  {
-+    NULL, /* regset_bitmap */
-+    &microblaze_usrregs_info,
-+    &microblaze_regsets_info
-+  };
-+
-+static const struct regs_info *
-+microblaze_regs_info (void)
-+{
-+  return &regs_info;
-+}
-+
-+/* Support for hardware single step.  */
-+
-+static int
-+microblaze_supports_hardware_single_step (void)
-+{
-+  return 1;
-+}
-+
-+
-+static void
-+microblaze_arch_setup (void)
-+{
-+  current_process ()->tdesc = tdesc_microblaze;
-+}
-+
- struct linux_target_ops the_low_target = {
--  init_registers_microblaze,
--  microblaze_num_regs,
--  microblaze_regmap,
--  NULL,
-+  microblaze_arch_setup,
-+  microblaze_regs_info,
-   microblaze_cannot_fetch_register,
-   microblaze_cannot_store_register,
-   NULL, /* fetch_register */
-   microblaze_get_pc,
-   microblaze_set_pc,
--  (const unsigned char *) &microblaze_breakpoint,
--  microblaze_breakpoint_len,
--  microblaze_reinsert_addr,
-+  NULL,
-+  microblaze_sw_breakpoint_from_kind,
-+  NULL,
-   0,
-   microblaze_breakpoint_at,
-   NULL,
-   NULL,
-   NULL,
-   NULL,
-+  NULL,
-   microblaze_collect_ptrace_register,
-   microblaze_supply_ptrace_register,
-+  NULL, /* siginfo_fixup */
-+  NULL, /* new_process */
-+  NULL, /* new_thread */
-+  NULL, /* new_fork */
-+  NULL, /* prepare_to_resume */
-+  NULL, /* process_qsupported */
-+  NULL, /* supports_tracepoints */
-+  NULL, /* get_thread_area */
-+  NULL, /* install_fast_tracepoint_jump_pad */
-+  NULL, /* emit_ops */
-+  NULL, /* get_min_fast_tracepoint_insn_len */
-+  NULL, /* supports_range_stepping */
-+  NULL, /* breakpoint_kind_from_current_state */
-+  microblaze_supports_hardware_single_step,
- };
-+
-+void
-+initialize_low_arch (void)
-+{
-+  init_registers_microblaze ();
-+}
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 8f41ba19351..d2112dc07e1 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -24,6 +24,7 @@
- /* Microblaze architecture-specific information.  */
- struct microblaze_gregset
- {
-+   microblaze_gregset() {}
-    unsigned int gregs[32];
-    unsigned int fpregs[32];
-    unsigned int pregs[16];
-diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
-index 13d5c6aff87..ff9ada71b0d 100644
---- a/gdbserver/configure.srv
-+++ b/gdbserver/configure.srv
-@@ -156,8 +156,7 @@ case "${gdbserver_host}" in
- 			srv_linux_thread_db=yes
- 			;;
-   microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
--			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
--			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
-+			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
- 			srv_xmlfiles="microblaze-linux.xml"
- 			srv_linux_regsets=yes
- 			srv_linux_usrregs=yes
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000000..646914a43f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0039-Initial-support-for-native-gdb.patch
@@ -0,0 +1,495 @@
+From eef1384ec08bbbac893e4a564981517f92f90b57 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 39/52] Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+
+Conflicts:
+	gdb/Makefile.in
+---
+ gdb/Makefile.in                |   2 +
+ gdb/config/microblaze/linux.mh |   9 +
+ gdb/microblaze-linux-nat.c     | 431 +++++++++++++++++++++++++++++++++
+ 3 files changed, 442 insertions(+)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+diff --git a/gdb/Makefile.in b/gdb/Makefile.in
+index 9ae9fe2d1e..a44464b983 100644
+--- a/gdb/Makefile.in
++++ b/gdb/Makefile.in
+@@ -1328,6 +1328,7 @@ HFILES_NO_SRCDIR = \
+ 	memory-map.h \
+ 	memrange.h \
+ 	microblaze-tdep.h \
++	microblaze-linux-tdep.h \
+ 	mips-linux-tdep.h \
+ 	mips-nbsd-tdep.h \
+ 	mips-tdep.h \
+@@ -2207,6 +2208,7 @@ ALLDEPFILES = \
+ 	m68k-tdep.c \
+ 	microblaze-linux-tdep.c \
+ 	microblaze-tdep.c \
++	microblaze-linux-nat.c \
+ 	mingw-hdep.c \
+ 	mips-fbsd-nat.c \
+ 	mips-fbsd-tdep.c \
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+new file mode 100644
+index 0000000000..a4eaf540e1
+--- /dev/null
++++ b/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,9 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+new file mode 100644
+index 0000000000..e9b8c9c522
+--- /dev/null
++++ b/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++   Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++   Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include "gdb_string.h"
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle.  */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++   case we may be tracing more than one process at a time.  In that
++   case, inferior_ptid will contain the main process ID and the
++   individual thread (process) ID.  get_thread_id () is used to get
++   the thread id if it's available, and the process id otherwise.  */
++
++int
++get_thread_id (ptid_t ptid)
++{
++  int tid = TIDGET (ptid);
++  if (0 == tid)
++    tid = PIDGET (ptid);
++  return tid;
++}
++
++#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++   PTRACE_SETREGS requests, for reading and writing the
++   general-purpose registers.  Zero if we've tried one of
++   them and gotten an error.  */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++  int u_addr = -1;
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++     interface, and not the wordsize of the program's ABI.  */
++  int wordsize = sizeof (long);
++
++  /* General purpose registers occupy 1 slot each in the buffer.  */
++  if (regno >= MICROBLAZE_R0_REGNUM
++      && regno <= MICROBLAZE_FSR_REGNUM)
++    u_addr = (regno * wordsize);
++
++  return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int bytes_transferred;
++  unsigned int offset;         /* Offset of registers within the u area.  */
++  char buf[MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++  {
++    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
++    regcache_raw_supply (regcache, regno, buf);
++    return;
++  }
++
++  /* Read the raw register using sizeof(long) sized chunks.  On a
++     32-bit platform, 64-bit floating-point registers will require two
++     transfers.  */
++  for (bytes_transferred = 0;
++       bytes_transferred < register_size (gdbarch, regno);
++       bytes_transferred += sizeof (long))
++  {
++    long l;
++
++    errno = 0;
++    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++    regaddr += sizeof (long);
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "reading register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++    memcpy (&buf[bytes_transferred], &l, sizeof (l));
++  }
++
++  /* Now supply the register.  Keep in mind that the regcache's idea
++     of the register's size may not be a multiple of sizeof
++     (long).  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values are always found at the left end of the
++       bytes transferred.  */
++    regcache_raw_supply (regcache, regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values are found at the right end of the bytes
++       transferred.  */
++    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++    regcache_raw_supply (regcache, regno, buf + padding);
++  }
++  else
++    internal_error (__FILE__, __LINE__,
++                    _("fetch_register: unexpected byte order: %d"),
++                    gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++   it to get all general-purpose registers and put them into the
++   specified regset.
++
++   If the ptrace request does not exist, this function returns 0
++   and properly sets the have_ptrace_* flag.  If the request fails,
++   this function calls perror_with_name.  Otherwise, if the request
++   succeeds, then the regcache gets filled and 1 is returned.  */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  gdb_gregset_t gregset;
++
++  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++  {
++    if (errno == EIO)
++    {
++      have_ptrace_getsetregs = 0;
++      return 0;
++    }
++    perror_with_name (_("Couldn't get general-purpose registers."));
++  }
++
++  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++  return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function.  It is
++   responsible for verifying if this target has the ptrace request
++   that can be used to fetch all general-purpose registers at one
++   shot.  If it doesn't, then we should fetch them using the
++   old-fashioned way, which is to iterate over the registers and
++   request them one by one.  */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  int i;
++
++  if (have_ptrace_getsetregs)
++    if (fetch_all_gp_regs (regcache, tid))
++      return;
++
++  /* If we've hit this point, it doesn't really matter which
++     architecture we are using.  We just need to read the
++     registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int i;
++  size_t bytes_to_transfer;
++  char buf[MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++    return;
++
++  /* First collect the register.  Keep in mind that the regcache's
++     idea of the register's size may not be a multiple of sizeof
++     (long).  */
++  memset (buf, 0, sizeof buf);
++  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values always sit at the left end of the buffer.  */
++    regcache_raw_collect (regcache, regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values sit at the right end of the buffer.  */
++    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++    regcache_raw_collect (regcache, regno, buf + padding);
++  }
++
++  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++  {
++    long l;
++
++    memcpy (&l, &buf[i], sizeof (l));
++    errno = 0;
++    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++    regaddr += sizeof (long);
++
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "writing register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++  }
++}
++
++/* This function actually issues the request to ptrace, telling
++   it to store all general-purpose registers present in the specified
++   regset.
++
++   If the ptrace request does not exist, this function returns 0
++   and properly sets the have_ptrace_* flag.  If the request fails,
++   this function calls perror_with_name.  Otherwise, if the request
++   succeeds, then the regcache is stored and 1 is returned.  */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  gdb_gregset_t gregset;
++
++  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++    {
++      if (errno == EIO)
++      {
++        have_ptrace_getsetregs = 0;
++        return 0;
++      }
++      perror_with_name (_("Couldn't get general-purpose registers."));
++    }
++
++  fill_gregset (regcache, &gregset, regno);
++
++  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++    {
++      if (errno == EIO)
++      {
++        have_ptrace_getsetregs = 0;
++        return 0;
++      }
++      perror_with_name (_("Couldn't set general-purpose registers."));
++    }
++
++  return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function.  It is
++   responsible for verifying if this target has the ptrace request
++   that can be used to store all general-purpose registers at one
++   shot.  If it doesn't, then we should store them using the
++   old-fashioned way, which is to iterate over the registers and
++   store them one by one.  */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  int i;
++
++  if (have_ptrace_getsetregs)
++    if (store_all_gp_regs (regcache, tid, regno))
++      return;
++
++  /* If we hit this point, it doesn't really matter which
++     architecture we are using.  We just need to store the
++     registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process.  Fetch all registers if
++   regno == -1, otherwise fetch all general registers or all floating
++   point registers depending upon the value of regno.  */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++				    struct regcache *regcache, int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = GET_THREAD_ID (inferior_ptid);
++
++  if (regno == -1)
++    fetch_gp_regs (regcache, tid);
++  else
++    fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior.  Store all registers if
++   regno == -1, otherwise store all general registers or all floating
++   point registers depending upon the value of regno.  */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++				    struct regcache *regcache, int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = GET_THREAD_ID (inferior_ptid);
++
++  if (regno >= 0)
++    store_register (regcache, tid, regno);
++  else
++    store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++   thread debugging.  */
++
++void
++fill_gregset (const struct regcache *regcache,
++	      gdb_gregset_t *gregsetp, int regno)
++{
++  microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++  microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++	      gdb_fpregset_t *fpregsetp, int regno)
++{
++  /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++  /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++  CORE_ADDR microblaze_hwcap = 0;
++
++  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
++    return NULL;
++
++  return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++  struct target_ops *t;
++
++  /* Fill in the generic GNU/Linux methods.  */
++  t = linux_target ();
++
++  /* Add our register access methods.  */
++  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++  t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++  t->to_read_description = microblaze_linux_read_description;
++
++  /* Register the target.  */
++  linux_nat_add_target (t);
++}
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
new file mode 100644
index 0000000000..e08f16df97
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
@@ -0,0 +1,309 @@
+From 976a0e2664559cc194eee8040280cd29e2672d26 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 17 Feb 2017 14:09:40 +0530
+Subject: [PATCH 40/52] Fixing the issues related to GDB-7.12 added all the
+ required function which are new in 7.12 and removed few deprecated functions
+ from 7.6
+
+---
+ gdb/config/microblaze/linux.mh   |  4 +-
+ gdb/microblaze-linux-tdep.c      | 68 ++++++++++++++++++++--
+ gdb/microblaze-tdep.h            |  1 +
+ gdbserver/configure.srv          |  3 +-
+ gdbserver/linux-microblaze-low.c | 97 +++++++++++++++++++++++++++-----
+ 5 files changed, 153 insertions(+), 20 deletions(-)
+
+diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
+index a4eaf540e1..74a53b854a 100644
+--- a/gdb/config/microblaze/linux.mh
++++ b/gdb/config/microblaze/linux.mh
+@@ -1,9 +1,11 @@
+ # Host: Microblaze, running Linux
+ 
++#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
+ NAT_FILE= config/nm-linux.h
+ NATDEPFILES= inf-ptrace.o fork-child.o \
+ 	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
+-	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++	linux-waitpid.o linux-personality.o linux-namespaces.o
+ NAT_CDEPS = $(srcdir)/proc-service.list
+ 
+ LOADLIBES = -ldl $(RDYNAMIC)
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index 2725ce1789..a2e858d10f 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -29,13 +29,76 @@
+ #include "regcache.h"
+ #include "value.h"
+ #include "osabi.h"
+-#include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
++#include "glibc-tdep.h"
++
++#include "gdb_assert.h"
++
++#ifndef REGSET_H
++#define REGSET_H 1
++
++struct gdbarch;
++struct regcache;
++
++/* Data structure for the supported register notes in a core file.  */
++struct core_regset_section
++{
++  const char *sect_name;
++  int size;
++  const char *human_name;
++};
++
++/* Data structure describing a register set.  */
++
++typedef void (supply_regset_ftype) (const struct regset *, struct regcache *,
++                                    int, const void *, size_t);
++typedef void (collect_regset_ftype) (const struct regset *,
++                                     const struct regcache *,
++                                     int, void *, size_t);
++
++struct regset
++{
++  /* Data pointer for private use by the methods below, presumably
++     providing some sort of description of the register set.  */
++  const void *descr;
++
++  /* Function supplying values in a register set to a register cache.  */
++  supply_regset_ftype *supply_regset;
++
++  /* Function collecting values in a register set from a register cache.  */
++  collect_regset_ftype *collect_regset;
++
++  /* Architecture associated with the register set.  */
++  struct gdbarch *arch;
++};
++
++#endif
++
++/* Allocate a fresh 'struct regset' whose supply_regset function is
++   SUPPLY_REGSET, and whose collect_regset function is COLLECT_REGSET.
++   If the regset has no collect_regset function, pass NULL for
++   COLLECT_REGSET.
++
++   The object returned is allocated on ARCH's obstack.  */
++
++struct regset *
++regset_alloc (struct gdbarch *arch,
++              supply_regset_ftype *supply_regset,
++              collect_regset_ftype *collect_regset)
++{
++  struct regset *regset = GDBARCH_OBSTACK_ZALLOC (arch, struct regset);
++
++  regset->arch = arch;
++  regset->supply_regset = supply_regset;
++  regset->collect_regset = collect_regset;
++
++  return regset;
++}
+ 
+ static int microblaze_debug_flag = 0;
+ 
+@@ -207,9 +270,6 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+   set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+ 
+-  set_gdbarch_regset_from_core_section (gdbarch,
+-					microblaze_regset_from_core_section);
+-
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index de66a05cab..1234f8a36f 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -24,6 +24,7 @@
+ /* Microblaze architecture-specific information.  */
+ struct microblaze_gregset
+ {
++   microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+    unsigned int pregs[16];
+diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
+index 7e81388850..456f4b3349 100644
+--- a/gdbserver/configure.srv
++++ b/gdbserver/configure.srv
+@@ -156,8 +156,7 @@ case "${gdbserver_host}" in
+ 			srv_linux_thread_db=yes
+ 			;;
+   microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
+-			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
+-			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
+ 			srv_linux_regsets=yes
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+diff --git a/gdbserver/linux-microblaze-low.c b/gdbserver/linux-microblaze-low.c
+index cba5d6fc58..a2733f3c21 100644
+--- a/gdbserver/linux-microblaze-low.c
++++ b/gdbserver/linux-microblaze-low.c
+@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
+   PT_FSR
+   };
+ 
+-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
+ 
+ /* Defined in auto-generated file microblaze-linux.c.  */
+ void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
+ 
+ static int
+ microblaze_cannot_store_register (int regno)
+@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
+ static const unsigned long microblaze_breakpoint = 0xba0c0018;
+ #define microblaze_breakpoint_len 4
+ 
++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
++
++static const gdb_byte *
++microblaze_sw_breakpoint_from_kind (int kind, int *size)
++{
++  *size = microblaze_breakpoint_len;
++  return (const gdb_byte *) &microblaze_breakpoint;
++}
++
+ static int
+ microblaze_breakpoint_at (CORE_ADDR where)
+ {
+@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
+ static void
+ microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+ {
+-  int size = register_size (regno);
++  int size = register_size (regcache->tdesc, regno);
+ 
+   memset (buf, 0, sizeof (long));
+ 
+@@ -121,7 +131,7 @@ static void
+ microblaze_supply_ptrace_register (struct regcache *regcache,
+ 			    int regno, const char *buf)
+ {
+-  int size = register_size (regno);
++  int size = register_size (regcache->tdesc, regno);
+ 
+   if (regno == 0) {
+     unsigned long regbuf_0 = 0;
+@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
+ 
+ #endif /* HAVE_PTRACE_GETREGS */
+ 
+-struct regset_info target_regsets[] = {
++static struct regset_info microblaze_regsets[] = {
+ #ifdef HAVE_PTRACE_GETREGS
+   { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+-  { 0, 0, 0, -1, -1, NULL, NULL },
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
+ #endif /* HAVE_PTRACE_GETREGS */
+-  { 0, 0, 0, -1, -1, NULL, NULL }
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++  NULL_REGSET
+ };
+ 
++static struct usrregs_info microblaze_usrregs_info =
++  {
++    microblaze_num_regs,
++    microblaze_regmap,
++  };
++
++static struct regsets_info microblaze_regsets_info =
++  {
++    microblaze_regsets, /* regsets */
++    0, /* num_regsets */
++    NULL, /* disabled_regsets */
++  };
++
++static struct regs_info regs_info =
++  {
++    NULL, /* regset_bitmap */
++    &microblaze_usrregs_info,
++    &microblaze_regsets_info
++  };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++  return &regs_info;
++}
++
++/* Support for hardware single step.  */
++
++static int
++microblaze_supports_hardware_single_step (void)
++{
++  return 1;
++}
++
++
++static void
++microblaze_arch_setup (void)
++{
++  current_process ()->tdesc = tdesc_microblaze;
++}
++
+ struct linux_target_ops the_low_target = {
+-  init_registers_microblaze,
+-  microblaze_num_regs,
+-  microblaze_regmap,
+-  NULL,
++  microblaze_arch_setup,
++  microblaze_regs_info,
+   microblaze_cannot_fetch_register,
+   microblaze_cannot_store_register,
+   NULL, /* fetch_register */
+   microblaze_get_pc,
+   microblaze_set_pc,
+-  (const unsigned char *) &microblaze_breakpoint,
+-  microblaze_breakpoint_len,
+-  microblaze_reinsert_addr,
++  NULL,
++  microblaze_sw_breakpoint_from_kind,
++  NULL,
+   0,
+   microblaze_breakpoint_at,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
++  NULL,
+   microblaze_collect_ptrace_register,
+   microblaze_supply_ptrace_register,
++  NULL, /* siginfo_fixup */
++  NULL, /* new_process */
++  NULL, /* new_thread */
++  NULL, /* new_fork */
++  NULL, /* prepare_to_resume */
++  NULL, /* process_qsupported */
++  NULL, /* supports_tracepoints */
++  NULL, /* get_thread_area */
++  NULL, /* install_fast_tracepoint_jump_pad */
++  NULL, /* emit_ops */
++  NULL, /* get_min_fast_tracepoint_insn_len */
++  NULL, /* supports_range_stepping */
++  NULL, /* breakpoint_kind_from_current_state */
++  microblaze_supports_hardware_single_step,
+ };
++
++void
++initialize_low_arch (void)
++{
++  init_registers_microblaze ();
++}
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
deleted file mode 100644
index 1dc6b695e5..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
+++ /dev/null
@@ -1,998 +0,0 @@
-From 928d8d1f05274ab6029e4da7d659312c769beded Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 31 Jan 2019 14:36:00 +0530
-Subject: [PATCH 40/40] [Patch, microblaze]: Adding 64 bit MB support
-
-Added new architecture to Microblaze 64-bit support to GDB
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- bfd/archures.c                                |   2 +
- bfd/bfd-in2.h                                 |   2 +
- bfd/cpu-microblaze.c                          |  16 +-
- bfd/elf32-microblaze.c                        |   9 +
- gas/config/tc-microblaze.c                    |  14 ++
- gas/config/tc-microblaze.h                    |   4 +
- gdb/features/Makefile                         |   3 +
- gdb/features/microblaze-core.xml              |   6 +-
- gdb/features/microblaze-with-stack-protect.c  |   4 +-
- gdb/features/microblaze.c                     |   6 +-
- gdb/features/microblaze64-core.xml            |  69 +++++++
- gdb/features/microblaze64-stack-protect.xml   |  12 ++
- .../microblaze64-with-stack-protect.c         |  79 ++++++++
- .../microblaze64-with-stack-protect.xml       |  12 ++
- gdb/features/microblaze64.c                   |  77 ++++++++
- gdb/features/microblaze64.xml                 |  11 ++
- gdb/microblaze-linux-tdep.c                   |  29 ++-
- gdb/microblaze-tdep.c                         | 176 ++++++++++++++++--
- gdb/microblaze-tdep.h                         |   9 +-
- .../microblaze-with-stack-protect.dat         |   4 +-
- 20 files changed, 504 insertions(+), 40 deletions(-)
- create mode 100644 gdb/features/microblaze64-core.xml
- create mode 100644 gdb/features/microblaze64-stack-protect.xml
- create mode 100644 gdb/features/microblaze64-with-stack-protect.c
- create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
- create mode 100644 gdb/features/microblaze64.c
- create mode 100644 gdb/features/microblaze64.xml
-
-diff --git a/bfd/archures.c b/bfd/archures.c
-index 551ec8732f0..627d81261da 100644
---- a/bfd/archures.c
-+++ b/bfd/archures.c
-@@ -522,6 +522,8 @@ DESCRIPTION
- .  bfd_arch_lm32,      {* Lattice Mico32.  *}
- .#define bfd_mach_lm32		1
- .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
-+.#define bfd_mach_microblaze	1
-+.#define bfd_mach_microblaze64	2
- .  bfd_arch_tilepro,   {* Tilera TILEPro.  *}
- .  bfd_arch_tilegx,    {* Tilera TILE-Gx.  *}
- .#define bfd_mach_tilepro	1
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 8902d9c7939..0e5071c235d 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -1922,6 +1922,8 @@ enum bfd_architecture
-   bfd_arch_lm32,      /* Lattice Mico32.  */
- #define bfd_mach_lm32          1
-   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
-+#define bfd_mach_microblaze    1
-+#define bfd_mach_microblaze64  2
-   bfd_arch_tilepro,   /* Tilera TILEPro.  */
-   bfd_arch_tilegx,    /* Tilera TILE-Gx.  */
- #define bfd_mach_tilepro       1
-diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index f94dc2c177b..4dbc149155e 100644
---- a/bfd/cpu-microblaze.c
-+++ b/bfd/cpu-microblaze.c
-@@ -30,8 +30,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   64,		  		/* 32 bits in a word.  */
-   64,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
--  bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_arch_microblaze,		/* Architecture.  */
-+  bfd_mach_microblaze64,	/* 64 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-@@ -43,11 +43,11 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   0 /* Maximum offset of a reloc from the start of an insn.  */
- },
- {
--  32,				/* Bits in a word.  */
--  32,				/* Bits in an address.  */
--  8,				/* Bits in a byte.  */
-+  32,				/* 32 bits in a word.  */
-+  32,				/* 32 bits in an address.  */
-+  8,				/* 8 bits in a byte.  */
-   bfd_arch_microblaze,		/* Architecture number.  */
--  0,				/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze,		/* 32 bit Machine */
-   "microblaze",			/* Architecture name.  */
-   "MicroBlaze",			/* Printable name.  */
-   3,				/* Section align power.  */
-@@ -64,7 +64,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   32,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
-   bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze,		/* 32 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-@@ -80,7 +80,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   64,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
-   bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze64,	/* 64 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index a4b15882d77..d33f709b8b3 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -3585,6 +3585,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-   return TRUE;
- }
- 
-+
-+static bfd_boolean
-+elf_microblaze_object_p (bfd *abfd)
-+{
-+  /* Set the right machine number for an s390 elf32 file.  */
-+  return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
-+}
-+
- /* Hook called by the linker routine which adds symbols from an object
-    file.  We use it to put .comm items in .sbss, and not .bss.  */
- 
-@@ -3657,5 +3665,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
- 
- #define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
- #define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
-+#define elf_backend_object_p			elf_microblaze_object_p
- 
- #include "elf32-target.h"
-diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
-index 62daa56b47a..b22f6de2df6 100644
---- a/gas/config/tc-microblaze.c
-+++ b/gas/config/tc-microblaze.c
-@@ -437,6 +437,11 @@ md_begin (void)
- 
-   opcode_hash_control = hash_new ();
- 
-+  if (microblaze_arch_size == 64)
-+    bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze64);
-+  else
-+    bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze);
-+
-   /* Insert unique names into hash table.  */
-   for (opcode = (struct op_code_struct *)opcodes; opcode->name; opcode ++)
-     {
-@@ -3494,6 +3499,15 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
- }
- 
- 
-+unsigned long
-+microblaze_mach (void)
-+{
-+  if (microblaze_arch_size == 64)
-+    return bfd_mach_microblaze64;
-+  else
-+    return bfd_mach_microblaze;
-+}
-+
- /* Create a fixup for a cons expression.  If parse_cons_expression_microblaze
-    found a machine specific op in an expression,
-    then we create relocs accordingly.  */
-diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
-index 7435a70ef5e..90c2a4a5558 100644
---- a/gas/config/tc-microblaze.h
-+++ b/gas/config/tc-microblaze.h
-@@ -23,6 +23,10 @@
- #define TC_MICROBLAZE 1
- 
- #define TARGET_ARCH	bfd_arch_microblaze
-+#define TARGET_MACH (microblaze_mach ())
-+#define DEFAULT_MACHINE bfd_mach_microblaze64
-+extern unsigned long microblaze_mach (void);
-+
- #ifndef TARGET_BYTES_BIG_ENDIAN
- /* Used to initialise target_big_endian.  */
- #define TARGET_BYTES_BIG_ENDIAN 1
-diff --git a/gdb/features/Makefile b/gdb/features/Makefile
-index d0af9a47b48..2c3cf91b69f 100644
---- a/gdb/features/Makefile
-+++ b/gdb/features/Makefile
-@@ -46,6 +46,7 @@
- # List of .dat files to create in ../regformats/
- WHICH = mips-linux mips-dsp-linux \
- 	microblaze-with-stack-protect \
-+	microblaze64-with-stack-protect \
- 	mips64-linux mips64-dsp-linux \
- 	nios2-linux \
- 	rs6000/powerpc-32 \
-@@ -107,7 +108,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
- # to make on the command line.
- XMLTOC = \
- 	microblaze-with-stack-protect.xml \
-+	microblaze64-with-stack-protect.xml \
- 	microblaze.xml \
-+	microblaze64.xml \
- 	mips-dsp-linux.xml \
- 	mips-linux.xml \
- 	mips64-dsp-linux.xml \
-diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
-index f272650a41b..d1f2282fd1e 100644
---- a/gdb/features/microblaze-core.xml
-+++ b/gdb/features/microblaze-core.xml
-@@ -8,7 +8,7 @@
- <!DOCTYPE feature SYSTEM "gdb-target.dtd">
- <feature name="org.gnu.gdb.microblaze.core">
-   <reg name="r0" bitsize="32" regnum="0"/>
--  <reg name="r1" bitsize="32" type="data_ptr"/>
-+  <reg name="r1" bitsize="32"/>
-   <reg name="r2" bitsize="32"/>
-   <reg name="r3" bitsize="32"/>
-   <reg name="r4" bitsize="32"/>
-@@ -39,7 +39,7 @@
-   <reg name="r29" bitsize="32"/>
-   <reg name="r30" bitsize="32"/>
-   <reg name="r31" bitsize="32"/>
--  <reg name="rpc" bitsize="32" type="code_ptr"/>
-+  <reg name="rpc" bitsize="32"/>
-   <reg name="rmsr" bitsize="32"/>
-   <reg name="rear" bitsize="32"/>
-   <reg name="resr" bitsize="32"/>
-@@ -64,4 +64,6 @@
-   <reg name="rtlbsx" bitsize="32"/>
-   <reg name="rtlblo" bitsize="32"/>
-   <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="rslr" bitsize="32"/>
-+  <reg name="rshr" bitsize="32"/>
- </feature>
-diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
-index b39aa198874..ab162fd2588 100644
---- a/gdb/features/microblaze-with-stack-protect.c
-+++ b/gdb/features/microblaze-with-stack-protect.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
- 
-   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
-index 6c86fc07700..7919ac96e62 100644
---- a/gdb/features/microblaze.c
-+++ b/gdb/features/microblaze.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
- 
-   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
- 
-   tdesc_microblaze = result;
- }
-diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
-new file mode 100644
-index 00000000000..b9adadfade6
---- /dev/null
-+++ b/gdb/features/microblaze64-core.xml
-@@ -0,0 +1,69 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.core">
-+  <reg name="r0" bitsize="64" regnum="0"/>
-+  <reg name="r1" bitsize="64"/>
-+  <reg name="r2" bitsize="64"/>
-+  <reg name="r3" bitsize="64"/>
-+  <reg name="r4" bitsize="64"/>
-+  <reg name="r5" bitsize="64"/>
-+  <reg name="r6" bitsize="64"/>
-+  <reg name="r7" bitsize="64"/>
-+  <reg name="r8" bitsize="64"/>
-+  <reg name="r9" bitsize="64"/>
-+  <reg name="r10" bitsize="64"/>
-+  <reg name="r11" bitsize="64"/>
-+  <reg name="r12" bitsize="64"/>
-+  <reg name="r13" bitsize="64"/>
-+  <reg name="r14" bitsize="64"/>
-+  <reg name="r15" bitsize="64"/>
-+  <reg name="r16" bitsize="64"/>
-+  <reg name="r17" bitsize="64"/>
-+  <reg name="r18" bitsize="64"/>
-+  <reg name="r19" bitsize="64"/>
-+  <reg name="r20" bitsize="64"/>
-+  <reg name="r21" bitsize="64"/>
-+  <reg name="r22" bitsize="64"/>
-+  <reg name="r23" bitsize="64"/>
-+  <reg name="r24" bitsize="64"/>
-+  <reg name="r25" bitsize="64"/>
-+  <reg name="r26" bitsize="64"/>
-+  <reg name="r27" bitsize="64"/>
-+  <reg name="r28" bitsize="64"/>
-+  <reg name="r29" bitsize="64"/>
-+  <reg name="r30" bitsize="64"/>
-+  <reg name="r31" bitsize="64"/>
-+  <reg name="rpc" bitsize="64"/>
-+  <reg name="rmsr" bitsize="32"/>
-+  <reg name="rear" bitsize="64"/>
-+  <reg name="resr" bitsize="32"/>
-+  <reg name="rfsr" bitsize="32"/>
-+  <reg name="rbtr" bitsize="64"/>
-+  <reg name="rpvr0" bitsize="32"/>
-+  <reg name="rpvr1" bitsize="32"/>
-+  <reg name="rpvr2" bitsize="32"/>
-+  <reg name="rpvr3" bitsize="32"/>
-+  <reg name="rpvr4" bitsize="32"/>
-+  <reg name="rpvr5" bitsize="32"/>
-+  <reg name="rpvr6" bitsize="32"/>
-+  <reg name="rpvr7" bitsize="32"/>
-+  <reg name="rpvr8" bitsize="64"/>
-+  <reg name="rpvr9" bitsize="64"/>
-+  <reg name="rpvr10" bitsize="32"/>
-+  <reg name="rpvr11" bitsize="32"/>
-+  <reg name="redr" bitsize="32"/>
-+  <reg name="rpid" bitsize="32"/>
-+  <reg name="rzpr" bitsize="32"/>
-+  <reg name="rtlbx" bitsize="32"/>
-+  <reg name="rtlbsx" bitsize="32"/>
-+  <reg name="rtlblo" bitsize="32"/>
-+  <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="rslr" bitsize="64"/>
-+  <reg name="rshr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
-new file mode 100644
-index 00000000000..9d7ea8b9fd7
---- /dev/null
-+++ b/gdb/features/microblaze64-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.stack-protect">
-+  <reg name="rslr" bitsize="64"/>
-+  <reg name="rshr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
-new file mode 100644
-index 00000000000..249cb534daa
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.c
-@@ -0,0 +1,79 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze-with-stack-protect.xml */
-+
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
-+
-+struct target_desc *tdesc_microblaze64_with_stack_protect;
-+static void
-+initialize_tdesc_microblaze64_with_stack_protect (void)
-+{
-+  struct target_desc *result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64_with_stack_protect = result;
-+}
-diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
-new file mode 100644
-index 00000000000..0e9f01611f3
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+  <xi:include href="microblaze64-stack-protect.xml"/>
-+</target>
-diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
-new file mode 100644
-index 00000000000..5d3e2c8cd91
---- /dev/null
-+++ b/gdb/features/microblaze64.c
-@@ -0,0 +1,77 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze.xml */
-+
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
-+
-+struct target_desc *tdesc_microblaze64;
-+static void
-+initialize_tdesc_microblaze64 (void)
-+{
-+  struct target_desc *result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64 = result;
-+}
-diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
-new file mode 100644
-index 00000000000..515d18e65cf
---- /dev/null
-+++ b/gdb/features/microblaze64.xml
-@@ -0,0 +1,11 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+</target>
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index 0d5c08d24f6..a9a0eef3854 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -159,9 +159,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
- 
-   /* BFD target for core files.  */
-   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
-+          MICROBLAZE_REGISTER_SIZE=8;
-+        }
-+      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    }
-   else
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
-+          MICROBLAZE_REGISTER_SIZE=8;
-+        }
-+      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    }
-+
-+  switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
- 
-   /* Shared library handling.  */
-@@ -177,6 +198,8 @@ void _initialize_microblaze_linux_tdep ();
- void
- _initialize_microblaze_linux_tdep ()
- {
--  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
-+			  microblaze_linux_init_abi);
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
- 			  microblaze_linux_init_abi);
- }
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 7462a1f7ce6..5dd0b3ea532 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -40,7 +40,9 @@
- #include "remote.h"
- 
- #include "features/microblaze-with-stack-protect.c"
-+#include "features/microblaze64-with-stack-protect.c"
- #include "features/microblaze.c"
-+#include "features/microblaze64.c"
- 
- /* Instruction macros used for analyzing the prologue.  */
- /* This set of instruction macros need to be changed whenever the
-@@ -79,8 +81,9 @@ static const char *microblaze_register_names[] =
- };
- 
- #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
--
-+
- static unsigned int microblaze_debug_flag = 0;
-+int MICROBLAZE_REGISTER_SIZE = 4;
- 
- static void ATTRIBUTE_PRINTF (1, 2)
- microblaze_debug (const char *fmt, ...)
-@@ -137,6 +140,7 @@ microblaze_fetch_instruction (CORE_ADDR pc)
- constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
- 
- typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
-+#if 0
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
- 				    struct bp_target_info *bp_tgt)
-@@ -169,6 +173,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
- 
-   return val;
- }
-+#endif
- 
- /* Allocate and initialize a frame cache.  */
- 
-@@ -556,7 +561,6 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
- 				 gdb_byte *valbuf)
- {
-   gdb_byte buf[8];
--
-   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
-   switch (TYPE_LENGTH (type))
-     {
-@@ -633,7 +637,113 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
-   return (TYPE_LENGTH (type) == 16);
- }
- 
--
-+#if 0
-+static std::vector<CORE_ADDR>
-+microblaze_software_single_step (struct regcache *regcache)
-+{
-+//  struct gdbarch *arch = get_frame_arch(frame);
-+  struct gdbarch *arch = get_regcache_arch (regcache);
-+  struct address_space *aspace = get_regcache_aspace (regcache);
-+//  struct address_space *aspace = get_frame_address_space (frame);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
-+  static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
-+  static char be_breakp[] = MICROBLAZE_BREAKPOINT;
-+  enum bfd_endian byte_order = gdbarch_byte_order (arch);
-+  char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
-+  std::vector<CORE_ADDR> ret = 0;
-+
-+ /* Save the address and the values of the next_pc and the target */
-+  static struct sstep_breaks
-+  {
-+    CORE_ADDR address;
-+    bfd_boolean valid;
-+    /* Shadow contents.  */
-+    char data[INST_WORD_SIZE];
-+  } stepbreaks[2];
-+ int ii;
-+
-+  if (1)
-+    {
-+      CORE_ADDR pc;
-+      std::vector<CORE_ADDR> *next_pcs = NULL;
-+      long insn;
-+      enum microblaze_instr minstr;
-+      bfd_boolean isunsignednum;
-+      enum microblaze_instr_type insn_type;
-+      short delay_slots;
-+      int imm;
-+      bfd_boolean immfound = FALSE;
-+
-+     /* Set a breakpoint at the next instruction */
-+      /* If the current instruction is an imm, set it at the inst after */
-+      /* If the instruction has a delay slot, skip the delay slot */
-+      pc = regcache_read_pc (regcache);
-+      insn = microblaze_fetch_instruction (pc);
-+      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
-+      if (insn_type == immediate_inst)
-+	{
-+	  int rd, ra, rb;
-+	  immfound = TRUE;
-+	  minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
-+	  pc = pc + INST_WORD_SIZE;
-+	  insn = microblaze_fetch_instruction (pc);
-+	  minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
-+	}
-+      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
-+      if (insn_type != return_inst) {
-+	stepbreaks[0].valid = TRUE;
-+      } else {
-+	stepbreaks[0].valid = FALSE;
-+      }
-+
-+      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
-+      /* Now check for branch or return instructions */
-+      if (insn_type == branch_inst || insn_type == return_inst) {
-+	int limm;
-+	int lrd, lra, lrb;
-+	int ra, rb;
-+	bfd_boolean targetvalid;
-+	bfd_boolean unconditionalbranch;
-+	microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
-+	if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
-+	  ra = regcache_raw_get_unsigned(regcache, lra);
-+	else
-+	  ra = 0;
-+	if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
-+	  rb = regcache_raw_get_unsigned(regcache, lrb);
-+	else
-+	  rb = 0;
-+	stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
-+        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
-+	if (unconditionalbranch)
-+	  stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
-+	if (targetvalid && (stepbreaks[0].valid == FALSE ||
-+			    (stepbreaks[0].address != stepbreaks[1].address))
-+	                && (stepbreaks[1].address != pc)) {
-+	  stepbreaks[1].valid = TRUE;
-+	} else {
-+	  stepbreaks[1].valid = FALSE;
-+	}
-+      } else {
-+	stepbreaks[1].valid = FALSE;
-+      }
-+
-+      /* Insert the breakpoints */
-+      for (ii = 0; ii < 2; ++ii)
-+        {
-+
-+          /* ignore invalid breakpoint. */
-+          if (stepbreaks[ii].valid) {
-+            VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
-+//            insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
-+            ret = next_pcs;
-+	  }
-+	}
-+    }
-+    return ret;
-+}
-+#endif
-+
- static int dwarf2_to_reg_map[78] =
- { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
-   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
-@@ -665,24 +775,27 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
-   return -1;
- }
- 
-+#if 0
- static void
- microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
- {
-+
-   register_remote_g_packet_guess (gdbarch,
--                                  4 * MICROBLAZE_NUM_CORE_REGS,
--                                  tdesc_microblaze);
-+                                  4 * MICROBLAZE_NUM_REGS,
-+                                  tdesc_microblaze64);
- 
-   register_remote_g_packet_guess (gdbarch,
-                                   4 * MICROBLAZE_NUM_REGS,
--                                  tdesc_microblaze_with_stack_protect);
-+                                  tdesc_microblaze64_with_stack_protect);
- }
-+#endif
- 
- void
- microblaze_supply_gregset (const struct regset *regset,
-                         struct regcache *regcache,
-                         int regnum, const void *gregs)
- {
--  const unsigned int *regs = (const unsigned int *)gregs;
-+  const gdb_byte *regs = (const gdb_byte *) gregs;
-   if (regnum >= 0)
-     regcache->raw_supply (regnum, regs + regnum);
- 
-@@ -713,7 +826,6 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
- }
- 
- 
--
- static struct gdbarch *
- microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- {
-@@ -727,8 +839,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   if (arches != NULL)
-     return arches->gdbarch;
-   if (tdesc == NULL)
--    tdesc = tdesc_microblaze;
--
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
-+        {
-+    	  tdesc = tdesc_microblaze64;
-+          MICROBLAZE_REGISTER_SIZE = 8;
-+   	}
-+      else
-+    	tdesc = tdesc_microblaze;
-+    }
-   /* Check any target description for validity.  */
-   if (tdesc_has_registers (tdesc))
-     {
-@@ -736,27 +855,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-       int valid_p;
-       int i;
- 
--      feature = tdesc_find_feature (tdesc,
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.core");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze.core");
-       if (feature == NULL)
-         return NULL;
-       tdesc_data = tdesc_data_alloc ();
- 
-       valid_p = 1;
--      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
-+      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
-         valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
-                                             microblaze_register_names[i]);
--      feature = tdesc_find_feature (tdesc,
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.stack-protect");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze.stack-protect");
-       if (feature != NULL)
-         {
-           valid_p = 1;
-           valid_p &= tdesc_numbered_register (feature, tdesc_data,
-                                               MICROBLAZE_SLR_REGNUM,
--                                              "rslr");
-+                                              "slr");
-           valid_p &= tdesc_numbered_register (feature, tdesc_data,
-                                               MICROBLAZE_SHR_REGNUM,
--                                              "rshr");
-+                                              "shr");
-         }
- 
-       if (!valid_p)
-@@ -764,6 +891,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-           tdesc_data_cleanup (tdesc_data);
-           return NULL;
-         }
-+      
-     }
- 
-   /* Allocate space for the new architecture.  */
-@@ -783,7 +911,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   /* Register numbers of various important registers.  */
-   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
-   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
-+  
-+  /* Register set.  
-+  make_regs (gdbarch); */
-+  switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
-+  
-   /* Map Dwarf2 registers to GDB registers.  */
-   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
- 
-@@ -803,13 +941,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- 				       microblaze_breakpoint::kind_from_pc);
-   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
- 				       microblaze_breakpoint::bp_from_kind);
--  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+
-+//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
- 
-   set_gdbarch_frame_args_skip (gdbarch, 8);
- 
-   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
- 
--  microblaze_register_g_packet_guesses (gdbarch);
-+  //microblaze_register_g_packet_guesses (gdbarch);
- 
-   frame_base_set_default (gdbarch, &microblaze_frame_base);
- 
-@@ -841,6 +981,8 @@ _initialize_microblaze_tdep ()
- 
-   initialize_tdesc_microblaze_with_stack_protect ();
-   initialize_tdesc_microblaze ();
-+  initialize_tdesc_microblaze64_with_stack_protect ();
-+  initialize_tdesc_microblaze64 ();
-   /* Debug this files internals.  */
-   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
- 			     &microblaze_debug_flag, _("\
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index d2112dc07e1..bd03e969b9b 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -27,7 +27,7 @@ struct microblaze_gregset
-    microblaze_gregset() {}
-    unsigned int gregs[32];
-    unsigned int fpregs[32];
--   unsigned int pregs[16];
-+   unsigned int pregs[18];
- };
- 
- struct gdbarch_tdep
-@@ -101,9 +101,9 @@ enum microblaze_regnum
-   MICROBLAZE_RTLBSX_REGNUM,
-   MICROBLAZE_RTLBLO_REGNUM,
-   MICROBLAZE_RTLBHI_REGNUM,
--  MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
-+  MICROBLAZE_SLR_REGNUM,
-   MICROBLAZE_SHR_REGNUM,
--  MICROBLAZE_NUM_REGS
-+  MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
- };
- 
- struct microblaze_frame_cache
-@@ -128,7 +128,8 @@ struct microblaze_frame_cache
-   struct trad_frame_saved_reg *saved_regs;
- };
- /* All registers are 32 bits.  */
--#define MICROBLAZE_REGISTER_SIZE 4
-+extern int microblaze_reg_size;
-+#define MICROBLAZE_REGISTER_SIZE microblaze_reg_size
- 
- /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
-    Only used for native debugging.  */
-diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat
-index 8040a7b3fd0..450e321d49e 100644
---- a/gdb/regformats/microblaze-with-stack-protect.dat
-+++ b/gdb/regformats/microblaze-with-stack-protect.dat
-@@ -60,5 +60,5 @@ expedite:r1,rpc
- 32:rtlbsx
- 32:rtlblo
- 32:rtlbhi
--32:rslr
--32:rshr
-+32:slr
-+32:shr
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
new file mode 100644
index 0000000000..2cb1cc816b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
@@ -0,0 +1,1008 @@
+From 90412eba37c683e0526470c39926318ae7f5bd27 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 41/52] Adding 64 bit MB support Added new architecture to
+ Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala
+ <nmekala@xilix.com>
+
+Conflicts:
+	gdb/Makefile.in
+---
+ bfd/archures.c                                |   2 +
+ bfd/bfd-in2.h                                 |   2 +
+ bfd/cpu-microblaze.c                          |   8 +-
+ gas/config/tc-microblaze.c                    |  13 ++
+ gas/config/tc-microblaze.h                    |   4 +
+ gdb/features/Makefile                         |   3 +
+ gdb/features/microblaze-core.xml              |   6 +-
+ gdb/features/microblaze-stack-protect.xml     |   4 +-
+ gdb/features/microblaze-with-stack-protect.c  |   8 +-
+ gdb/features/microblaze.c                     |   6 +-
+ gdb/features/microblaze64-core.xml            |  69 ++++++
+ gdb/features/microblaze64-stack-protect.xml   |  12 +
+ .../microblaze64-with-stack-protect.c         |  79 +++++++
+ .../microblaze64-with-stack-protect.xml       |  12 +
+ gdb/features/microblaze64.c                   |  77 +++++++
+ gdb/features/microblaze64.xml                 |  11 +
+ gdb/microblaze-tdep.c                         | 207 ++++++++++++++++--
+ gdb/microblaze-tdep.h                         |   8 +-
+ .../microblaze-with-stack-protect.dat         |   4 +-
+ 19 files changed, 491 insertions(+), 44 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 551ec8732f..627d81261d 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -522,6 +522,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32		1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
++.#define bfd_mach_microblaze	1
++.#define bfd_mach_microblaze64	2
+ .  bfd_arch_tilepro,   {* Tilera TILEPro.  *}
+ .  bfd_arch_tilegx,    {* Tilera TILE-Gx.  *}
+ .#define bfd_mach_tilepro	1
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index 05fbeb9b3a..788fb2b48b 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -1922,6 +1922,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
++#define bfd_mach_microblaze    1
++#define bfd_mach_microblaze64  2
+   bfd_arch_tilepro,   /* Tilera TILEPro.  */
+   bfd_arch_tilegx,    /* Tilera TILE-Gx.  */
+ #define bfd_mach_tilepro       1
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index 194920b20b..f3e8bbda75 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -31,7 +31,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   64,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze64, 	/* 64 bit Machine  */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+@@ -46,7 +46,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   32,				/* Bits in an address.  */
+   8,				/* Bits in a byte.  */
+   bfd_arch_microblaze,		/* Architecture number.  */
+-  0,				/* Machine number - 0 for now.  */
++  bfd_mach_microblaze,		/* 32 bit Machine  */
+   "microblaze",			/* Architecture name.  */
+   "MicroBlaze",			/* Printable name.  */
+   3,				/* Section align power.  */
+@@ -63,7 +63,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   32,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze,		/* 32 bit Machine */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+@@ -78,7 +78,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   64,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze64,	/* 64 bit Machine */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index c6ca913f8b..df7088d6c3 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -438,6 +438,11 @@ md_begin (void)
+ 
+   opcode_hash_control = hash_new ();
+ 
++  if (microblaze_arch_size == 64)
++    bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze64);
++  else
++    bfd_set_arch_mach (stdoutput, bfd_arch_microblaze, bfd_mach_microblaze);
++
+   /* Insert unique names into hash table.  */
+   for (opcode = (struct opcodes *)opcodes; opcode->name; opcode ++)
+     {
+@@ -3478,6 +3483,14 @@ md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+   fprintf (stream, "  -%-23s%s\n", "m64", N_("generate 64-bit elf"));
+ }
+ 
++unsigned long
++microblaze_mach (void)
++{
++  if (microblaze_arch_size == 64)
++    return bfd_mach_microblaze64;
++  else
++    return bfd_mach_microblaze;
++}
+ 
+ /* Create a fixup for a cons expression.  If parse_cons_expression_microblaze
+    found a machine specific op in an expression,
+diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h
+index 7435a70ef5..90c2a4a555 100644
+--- a/gas/config/tc-microblaze.h
++++ b/gas/config/tc-microblaze.h
+@@ -23,6 +23,10 @@
+ #define TC_MICROBLAZE 1
+ 
+ #define TARGET_ARCH	bfd_arch_microblaze
++#define TARGET_MACH (microblaze_mach ())
++#define DEFAULT_MACHINE bfd_mach_microblaze64
++extern unsigned long microblaze_mach (void);
++
+ #ifndef TARGET_BYTES_BIG_ENDIAN
+ /* Used to initialise target_big_endian.  */
+ #define TARGET_BYTES_BIG_ENDIAN 1
+diff --git a/gdb/features/Makefile b/gdb/features/Makefile
+index d0af9a47b4..2c3cf91b69 100644
+--- a/gdb/features/Makefile
++++ b/gdb/features/Makefile
+@@ -46,6 +46,7 @@
+ # List of .dat files to create in ../regformats/
+ WHICH = mips-linux mips-dsp-linux \
+ 	microblaze-with-stack-protect \
++	microblaze64-with-stack-protect \
+ 	mips64-linux mips64-dsp-linux \
+ 	nios2-linux \
+ 	rs6000/powerpc-32 \
+@@ -107,7 +108,9 @@ OUTPUTS = $(patsubst %,$(outdir)/%.dat,$(WHICH))
+ # to make on the command line.
+ XMLTOC = \
+ 	microblaze-with-stack-protect.xml \
++	microblaze64-with-stack-protect.xml \
+ 	microblaze.xml \
++	microblaze64.xml \
+ 	mips-dsp-linux.xml \
+ 	mips-linux.xml \
+ 	mips64-dsp-linux.xml \
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index f272650a41..a87f0f2319 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32" type="data_ptr"/>
++  <reg name="r1" bitsize="32"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32" type="code_ptr"/>
++  <reg name="rpc" bitsize="32"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index 1b16223406..1a67f88c18 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="rslr" bitsize="32"/>
+-  <reg name="rshr" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index b39aa19887..609934e2b4 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index 6c86fc0770..ceb98ca8b8 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result;
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+new file mode 100644
+index 0000000000..96e99e2fb2
+--- /dev/null
++++ b/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++  <reg name="r0" bitsize="64" regnum="0"/>
++  <reg name="r1" bitsize="64"/>
++  <reg name="r2" bitsize="64"/>
++  <reg name="r3" bitsize="64"/>
++  <reg name="r4" bitsize="64"/>
++  <reg name="r5" bitsize="64"/>
++  <reg name="r6" bitsize="64"/>
++  <reg name="r7" bitsize="64"/>
++  <reg name="r8" bitsize="64"/>
++  <reg name="r9" bitsize="64"/>
++  <reg name="r10" bitsize="64"/>
++  <reg name="r11" bitsize="64"/>
++  <reg name="r12" bitsize="64"/>
++  <reg name="r13" bitsize="64"/>
++  <reg name="r14" bitsize="64"/>
++  <reg name="r15" bitsize="64"/>
++  <reg name="r16" bitsize="64"/>
++  <reg name="r17" bitsize="64"/>
++  <reg name="r18" bitsize="64"/>
++  <reg name="r19" bitsize="64"/>
++  <reg name="r20" bitsize="64"/>
++  <reg name="r21" bitsize="64"/>
++  <reg name="r22" bitsize="64"/>
++  <reg name="r23" bitsize="64"/>
++  <reg name="r24" bitsize="64"/>
++  <reg name="r25" bitsize="64"/>
++  <reg name="r26" bitsize="64"/>
++  <reg name="r27" bitsize="64"/>
++  <reg name="r28" bitsize="64"/>
++  <reg name="r29" bitsize="64"/>
++  <reg name="r30" bitsize="64"/>
++  <reg name="r31" bitsize="64"/>
++  <reg name="rpc" bitsize="64"/>
++  <reg name="rmsr" bitsize="32"/>
++  <reg name="rear" bitsize="64"/>
++  <reg name="resr" bitsize="32"/>
++  <reg name="rfsr" bitsize="32"/>
++  <reg name="rbtr" bitsize="64"/>
++  <reg name="rpvr0" bitsize="32"/>
++  <reg name="rpvr1" bitsize="32"/>
++  <reg name="rpvr2" bitsize="32"/>
++  <reg name="rpvr3" bitsize="32"/>
++  <reg name="rpvr4" bitsize="32"/>
++  <reg name="rpvr5" bitsize="32"/>
++  <reg name="rpvr6" bitsize="32"/>
++  <reg name="rpvr7" bitsize="32"/>
++  <reg name="rpvr8" bitsize="64"/>
++  <reg name="rpvr9" bitsize="64"/>
++  <reg name="rpvr10" bitsize="32"/>
++  <reg name="rpvr11" bitsize="32"/>
++  <reg name="redr" bitsize="32"/>
++  <reg name="rpid" bitsize="32"/>
++  <reg name="rzpr" bitsize="32"/>
++  <reg name="rtlbx" bitsize="32"/>
++  <reg name="rtlbsx" bitsize="32"/>
++  <reg name="rtlblo" bitsize="32"/>
++  <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+new file mode 100644
+index 0000000000..1bbf5fc3ce
+--- /dev/null
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+new file mode 100644
+index 0000000000..f448c9a749
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++  struct target_desc *result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64_with_stack_protect = result;
++}
+diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
+new file mode 100644
+index 0000000000..0e9f01611f
+--- /dev/null
++++ b/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++  <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+new file mode 100644
+index 0000000000..1aa37c4512
+--- /dev/null
++++ b/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++  struct target_desc *result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64 = result;
++}
+diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
+new file mode 100644
+index 0000000000..515d18e65c
+--- /dev/null
++++ b/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 1b5cf38e45..f4ea3cc342 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+ 
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+ 
+ /* Instruction macros used for analyzing the prologue.  */
+ /* This set of instruction macros need to be changed whenever the
+@@ -75,12 +77,13 @@ static const char *microblaze_register_names[] =
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "rslr", "rshr"
++  "slr", "shr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+ 
+ static unsigned int microblaze_debug_flag = 0;
++int reg_size = 4;
+ 
+ static void ATTRIBUTE_PRINTF (1, 2)
+ microblaze_debug (const char *fmt, ...)
+@@ -145,6 +148,7 @@ microblaze_store_arguments (struct regcache *regcache, int nargs,
+   error (_("store_arguments not implemented"));
+   return sp;
+ }
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ 				    struct bp_target_info *bp_tgt)
+@@ -154,7 +158,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   int val;
+   int bplen;
+   gdb_byte old_contents[BREAKPOINT_MAX];
+-  struct cleanup *cleanup;
++  //struct cleanup *cleanup;
+ 
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+@@ -162,7 +166,8 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+     error (_("Software breakpoints not implemented for this target."));
+ 
+   /* Make sure we see the memory breakpoints.  */
+-  cleanup = make_show_memory_breakpoints_cleanup (1);
++  scoped_restore 
++    cleanup = make_scoped_restore_show_memory_breakpoints (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -178,6 +183,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   return val;
+ }
+ 
++#endif
+ /* Allocate and initialize a frame cache.  */
+ 
+ static struct microblaze_frame_cache *
+@@ -570,17 +576,16 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
+ 				 gdb_byte *valbuf)
+ {
+   gdb_byte buf[8];
+-
+   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
+   switch (TYPE_LENGTH (type))
+     {
+       case 1:	/* return last byte in the register.  */
+ 	regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-	memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
++	memcpy(valbuf, buf + reg_size - 1, 1);
+ 	return;
+       case 2:	/* return last 2 bytes in register.  */
+ 	regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-	memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
++	memcpy(valbuf, buf + reg_size - 2, 2);
+ 	return;
+       case 4:	/* for sizes 4 or 8, copy the required length.  */
+       case 8:
+@@ -647,7 +652,119 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
+   return (TYPE_LENGTH (type) == 16);
+ }
+ 
+-
++#if 0
++static std::vector<CORE_ADDR>
++microblaze_software_single_step (struct regcache *regcache)
++{
++//  struct gdbarch *arch = get_frame_arch(frame);
++  struct gdbarch *arch = get_regcache_arch (regcache);
++  struct address_space *aspace = get_regcache_aspace (regcache);
++//  struct address_space *aspace = get_frame_address_space (frame);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++  static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++  enum bfd_endian byte_order = gdbarch_byte_order (arch);
++  char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++  std::vector<CORE_ADDR> ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++  static struct sstep_breaks
++  {
++    CORE_ADDR address;
++    bfd_boolean valid;
++    /* Shadow contents.  */
++    char data[INST_WORD_SIZE];
++  } stepbreaks[2];
++ int ii;
++
++  if (1)
++    {
++      CORE_ADDR pc;
++      std::vector<CORE_ADDR> *next_pcs = NULL;
++      long insn;
++      enum microblaze_instr minstr;
++      bfd_boolean isunsignednum;
++      enum microblaze_instr_type insn_type;
++      short delay_slots;
++      int imm;
++      bfd_boolean immfound = FALSE;
++
++     /* Set a breakpoint at the next instruction */
++      /* If the current instruction is an imm, set it at the inst after */
++      /* If the instruction has a delay slot, skip the delay slot */
++      pc = regcache_read_pc (regcache);
++      insn = microblaze_fetch_instruction (pc);
++      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++      if (insn_type == immediate_inst)
++	{
++	  int rd, ra, rb;
++	  immfound = TRUE;
++	  minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++	  pc = pc + INST_WORD_SIZE;
++	  insn = microblaze_fetch_instruction (pc);
++	  minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++	}
++      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++      if (insn_type != return_inst) {
++	stepbreaks[0].valid = TRUE;
++      } else {
++	stepbreaks[0].valid = FALSE;
++      }
++
++      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++      /* Now check for branch or return instructions */
++      if (insn_type == branch_inst || insn_type == return_inst) {
++	int limm;
++	int lrd, lra, lrb;
++	int ra, rb;
++	bfd_boolean targetvalid;
++	bfd_boolean unconditionalbranch;
++	microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++	if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++	  ra = regcache_raw_get_unsigned(regcache, lra);
++	else
++	  ra = 0;
++	if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++	  rb = regcache_raw_get_unsigned(regcache, lrb);
++	else
++	  rb = 0;
++	stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++	if (unconditionalbranch)
++	  stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++	if (targetvalid && (stepbreaks[0].valid == FALSE ||
++			    (stepbreaks[0].address != stepbreaks[1].address))
++	                && (stepbreaks[1].address != pc)) {
++	  stepbreaks[1].valid = TRUE;
++	} else {
++	  stepbreaks[1].valid = FALSE;
++	}
++      } else {
++	stepbreaks[1].valid = FALSE;
++      }
++
++      /* Insert the breakpoints */
++      for (ii = 0; ii < 2; ++ii)
++        {
++
++          /* ignore invalid breakpoint. */
++          if (stepbreaks[ii].valid) {
++            VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
++//            insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++            ret = next_pcs;
++	  }
++	}
++    }
++    return ret;
++}
++#endif
++
++static void
++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++}
++
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -682,13 +799,14 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+   register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_CORE_REGS,
+-                                  tdesc_microblaze);
++                                  4 * MICROBLAZE_NUM_REGS,
++                                  tdesc_microblaze64);
+ 
+   register_remote_g_packet_guess (gdbarch,
+                                   4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze_with_stack_protect);
++                                  tdesc_microblaze64_with_stack_protect);
+ }
+ 
+ void
+@@ -696,15 +814,15 @@ microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+                         struct regcache *regcache,
+                         int regnum, const void *gregs)
+ {
+-  unsigned int *regs = gregs;
++  const gdb_byte *regs = (const gdb_byte *) gregs;
+   if (regnum >= 0)
+-    regcache_raw_supply (regcache, regnum, regs + regnum);
++    regcache->raw_supply (regnum, regs + regnum);
+ 
+   if (regnum == -1) {
+     int i;
+ 
+     for (i = 0; i < 50; i++) {
+-      regcache_raw_supply (regcache, i, regs + i);
++      regcache->raw_supply (regnum, regs + i);
+     }
+   }
+ }
+@@ -755,6 +873,17 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+ }
+ 
+ 
++static void
++make_regs (struct gdbarch *arch)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  int mach = gdbarch_bfd_arch_info (arch)->mach;
++  
++  if (mach == bfd_mach_microblaze64)
++    {
++      set_gdbarch_ptr_bit (arch, 64);
++    }
++}
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -769,8 +898,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   if (arches != NULL)
+     return arches->gdbarch;
+   if (tdesc == NULL)
+-    tdesc = tdesc_microblaze;
+-
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++        {
++    	  tdesc = tdesc_microblaze64;
++          reg_size = 8;
++   	}
++      else
++    	tdesc = tdesc_microblaze;
++    }
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -778,27 +914,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+       int valid_p;
+       int i;
+ 
+-      feature = tdesc_find_feature (tdesc,
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.core");
++      else
++        feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze.core");
+       if (feature == NULL)
+         return NULL;
+       tdesc_data = tdesc_data_alloc ();
+ 
+       valid_p = 1;
+-      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
++      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+                                             microblaze_register_names[i]);
+-      feature = tdesc_find_feature (tdesc,
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.stack-protect");
++      else
++        feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze.stack-protect");
+       if (feature != NULL)
+         {
+           valid_p = 1;
+           valid_p &= tdesc_numbered_register (feature, tdesc_data,
+                                               MICROBLAZE_SLR_REGNUM,
+-                                              "rslr");
++                                              "slr");
+           valid_p &= tdesc_numbered_register (feature, tdesc_data,
+                                               MICROBLAZE_SHR_REGNUM,
+-                                              "rshr");
++                                              "shr");
+         }
+ 
+       if (!valid_p)
+@@ -806,6 +950,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+           tdesc_data_cleanup (tdesc_data);
+           return NULL;
+         }
++      
+     }
+ 
+   /* Allocate space for the new architecture.  */
+@@ -825,7 +970,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+   /* Register numbers of various important registers.  */
+   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
+   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
++  
++  /* Register set.  
++  make_regs (gdbarch); */
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
++  
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -845,13 +1000,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ 				       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ 				       microblaze_breakpoint::bp_from_kind);
+-  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  microblaze_register_g_packet_guesses (gdbarch);
++  //microblaze_register_g_packet_guesses (gdbarch);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+@@ -866,11 +1023,11 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
+   //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+ 
+-  /* If we have register sets, enable the generic core file support.  */
++  /* If we have register sets, enable the generic core file support.  
+   if (tdep->gregset) {
+       set_gdbarch_regset_from_core_section (gdbarch,
+                                           microblaze_regset_from_core_section);
+-  }
++  }*/
+ 
+   return gdbarch;
+ }
+@@ -883,6 +1040,8 @@ _initialize_microblaze_tdep ()
+ 
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
++  initialize_tdesc_microblaze64_with_stack_protect ();
++  initialize_tdesc_microblaze64 ();
+   /* Debug this files internals.  */
+   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+ 			     &microblaze_debug_flag, _("\
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index 1234f8a36f..c0fc900733 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -27,7 +27,7 @@ struct microblaze_gregset
+    microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+-   unsigned int pregs[16];
++   unsigned int pregs[18];
+ };
+ 
+ struct gdbarch_tdep
+@@ -101,9 +101,9 @@ enum microblaze_regnum
+   MICROBLAZE_RTLBSX_REGNUM,
+   MICROBLAZE_RTLBLO_REGNUM,
+   MICROBLAZE_RTLBHI_REGNUM,
+-  MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
++  MICROBLAZE_SLR_REGNUM,
+   MICROBLAZE_SHR_REGNUM,
+-  MICROBLAZE_NUM_REGS
++  MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+ 
+ struct microblaze_frame_cache
+@@ -128,7 +128,7 @@ struct microblaze_frame_cache
+   struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits.  */
+-#define MICROBLAZE_REGISTER_SIZE 4
++//#define MICROBLAZE_REGISTER_SIZE 8
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat
+index 8040a7b3fd..450e321d49 100644
+--- a/gdb/regformats/microblaze-with-stack-protect.dat
++++ b/gdb/regformats/microblaze-with-stack-protect.dat
+@@ -60,5 +60,5 @@ expedite:r1,rpc
+ 32:rtlbsx
+ 32:rtlblo
+ 32:rtlbhi
+-32:rslr
+-32:rshr
++32:slr
++32:shr
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0042-porting-GDB-for-linux.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0042-porting-GDB-for-linux.patch
new file mode 100644
index 0000000000..e115666c2b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0042-porting-GDB-for-linux.patch
@@ -0,0 +1,155 @@
+From c810c6e2a6ae66426444580d04659e8b2d0b2daa Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Dec 2019 14:56:17 +0530
+Subject: [PATCH 42/52] porting GDB for linux
+
+---
+ gdb/features/microblaze-linux.xml | 12 ++++++++++
+ gdb/microblaze-linux-tdep.c       | 39 ++++++++++++++++++++++++-------
+ gdbserver/Makefile.in             |  2 ++
+ gdbserver/configure.srv           |  3 ++-
+ 4 files changed, 47 insertions(+), 9 deletions(-)
+ create mode 100644 gdb/features/microblaze-linux.xml
+
+diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
+new file mode 100644
+index 0000000000..8983e66eb3
+--- /dev/null
++++ b/gdb/features/microblaze-linux.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <osabi>GNU/Linux</osabi>
++  <xi:include href="microblaze-core.xml"/>
++</target>
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index a2e858d10f..a37c4c86f4 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -41,7 +41,7 @@
+ 
+ #ifndef REGSET_H
+ #define REGSET_H 1
+-
++int MICROBLAZE_REGISTER_SIZE=4;
+ struct gdbarch;
+ struct regcache;
+ 
+@@ -115,7 +115,7 @@ microblaze_debug (const char *fmt, ...)
+        va_end (args);
+     }
+ }
+-
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+ 					   struct bp_target_info *bp_tgt)
+@@ -131,7 +131,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ 
+   /* Make sure we see the memory breakpoints.  */
+-  cleanup = make_show_memory_breakpoints_cleanup (1);
++  cleanup = make_scoped_restore_show_memory_breakpoints (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -146,6 +146,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+   do_cleanups (cleanup);
+   return val;
+ }
++#endif
+ 
+ static void
+ microblaze_linux_sigtramp_cache (struct frame_info *next_frame,
+@@ -248,8 +249,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   linux_init_abi (info, gdbarch);
+ 
+-  set_gdbarch_memory_remove_breakpoint (gdbarch,
+-					microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch,
++//					microblaze_linux_memory_remove_breakpoint);
+ 
+   /* Shared library handling.  */
+   set_solib_svr4_fetch_link_map_offsets (gdbarch,
+@@ -261,10 +262,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
+ 
+   /* BFD target for core files.  */
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    }
+   else
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    }
+ 
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
+   /* Shared library handling.  */
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+@@ -279,6 +300,8 @@ void _initialize_microblaze_linux_tdep ();
+ void
+ _initialize_microblaze_linux_tdep ()
+ {
+-  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
++			  microblaze_linux_init_abi);
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
+ 			  microblaze_linux_init_abi);
+ }
+diff --git a/gdbserver/Makefile.in b/gdbserver/Makefile.in
+index df354d636c..680f536c06 100644
+--- a/gdbserver/Makefile.in
++++ b/gdbserver/Makefile.in
+@@ -559,6 +559,8 @@ target/%.o: ../gdb/target/%.c
+ 
+ %-generated.cc: ../gdb/regformats/rs6000/%.dat $(regdat_sh)
+ 	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+ 
+ #
+ # Dependency tracking.
+diff --git a/gdbserver/configure.srv b/gdbserver/configure.srv
+index 456f4b3349..ff9ada71b0 100644
+--- a/gdbserver/configure.srv
++++ b/gdbserver/configure.srv
+@@ -155,8 +155,9 @@ case "${gdbserver_host}" in
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+ 			;;
+-  microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
++  microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
+ 			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
++			srv_xmlfiles="microblaze-linux.xml"
+ 			srv_linux_regsets=yes
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0043-Binutils-security-check-is-causing-build-error-for-w.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0043-Binutils-security-check-is-causing-build-error-for-w.patch
new file mode 100644
index 0000000000..969ac2c07c
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0043-Binutils-security-check-is-causing-build-error-for-w.patch
@@ -0,0 +1,41 @@
+From 27c8f7f202ea66cd0f4745ca3a77b4f33b6f5990 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 11 Mar 2019 13:57:42 +0530
+Subject: [PATCH 43/52] Binutils security check is causing build error for
+ windows builds.commenting for now.
+
+---
+ bfd/elf-attrs.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c
+index 070104c273..b135ac8f11 100644
+--- a/bfd/elf-attrs.c
++++ b/bfd/elf-attrs.c
+@@ -436,12 +436,15 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
+   bfd_byte *p_end;
+   bfd_vma len;
+   const char *std_sec;
++#if 0
+   ufile_ptr filesize;
++#endif
+ 
+   /* PR 17512: file: 2844a11d.  */
+   if (hdr->sh_size == 0)
+     return;
+ 
++#if 0
+   filesize = bfd_get_file_size (abfd);
+   if (filesize != 0 && hdr->sh_size > filesize)
+     {
+@@ -451,6 +454,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
+       bfd_set_error (bfd_error_invalid_operation);
+       return;
+     }
++#endif
+ 
+   contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
+   if (!contents)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
new file mode 100644
index 0000000000..48c9c2c96b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
@@ -0,0 +1,146 @@
+From ba70b41346a8d5c9c1a4435f70edbb06e117564d Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 19 Dec 2019 12:22:04 +0530
+Subject: [PATCH 44/52] Correcting the register names from slr & shr to rslr &
+ rshr
+
+---
+ gdb/features/microblaze-core.xml               | 4 ++--
+ gdb/features/microblaze-stack-protect.xml      | 4 ++--
+ gdb/features/microblaze-with-stack-protect.c   | 4 ++--
+ gdb/features/microblaze.c                      | 4 ++--
+ gdb/features/microblaze64-core.xml             | 4 ++--
+ gdb/features/microblaze64-stack-protect.xml    | 4 ++--
+ gdb/features/microblaze64-with-stack-protect.c | 4 ++--
+ gdb/features/microblaze64.c                    | 4 ++--
+ gdb/microblaze-tdep.c                          | 2 +-
+ 9 files changed, 17 insertions(+), 17 deletions(-)
+
+diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
+index a87f0f2319..d1f2282fd1 100644
+--- a/gdb/features/microblaze-core.xml
++++ b/gdb/features/microblaze-core.xml
+@@ -64,6 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
+-  <reg name="slr" bitsize="32"/>
+-  <reg name="shr" bitsize="32"/>
++  <reg name="rslr" bitsize="32"/>
++  <reg name="rshr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-stack-protect.xml b/gdb/features/microblaze-stack-protect.xml
+index 1a67f88c18..1b16223406 100644
+--- a/gdb/features/microblaze-stack-protect.xml
++++ b/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="slr" bitsize="32"/>
+-  <reg name="shr" bitsize="32"/>
++  <reg name="rslr" bitsize="32"/>
++  <reg name="rshr" bitsize="32"/>
+ </feature>
+diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
+index 609934e2b4..ab162fd258 100644
+--- a/gdb/features/microblaze-with-stack-protect.c
++++ b/gdb/features/microblaze-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
+index ceb98ca8b8..7919ac96e6 100644
+--- a/gdb/features/microblaze.c
++++ b/gdb/features/microblaze.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result;
+ }
+diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
+index 96e99e2fb2..b9adadfade 100644
+--- a/gdb/features/microblaze64-core.xml
++++ b/gdb/features/microblaze64-core.xml
+@@ -64,6 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
+-  <reg name="slr" bitsize="64"/>
+-  <reg name="shr" bitsize="64"/>
++  <reg name="rslr" bitsize="64"/>
++  <reg name="rshr" bitsize="64"/>
+ </feature>
+diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
+index 1bbf5fc3ce..9d7ea8b9fd 100644
+--- a/gdb/features/microblaze64-stack-protect.xml
++++ b/gdb/features/microblaze64-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze64.stack-protect">
+-  <reg name="slr" bitsize="64"/>
+-  <reg name="shr" bitsize="64"/>
++  <reg name="rslr" bitsize="64"/>
++  <reg name="rshr" bitsize="64"/>
+ </feature>
+diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
+index f448c9a749..249cb534da 100644
+--- a/gdb/features/microblaze64-with-stack-protect.c
++++ b/gdb/features/microblaze64-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze64_with_stack_protect (void)
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze64_with_stack_protect = result;
+ }
+diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
+index 1aa37c4512..5d3e2c8cd9 100644
+--- a/gdb/features/microblaze64.c
++++ b/gdb/features/microblaze64.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze64 (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze64 = result;
+ }
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index f4ea3cc342..041ebf1fca 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -77,7 +77,7 @@ static const char *microblaze_register_names[] =
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "slr", "shr"
++  "rslr", "rshr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
new file mode 100644
index 0000000000..46124c12a7
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
@@ -0,0 +1,24 @@
+From 5fac707a9894ec9d0fcac14bbf0eb3ff631d0499 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 17 Jan 2020 15:45:48 +0530
+Subject: [PATCH 45/52] Removing the header "gdb_assert.h" from MB target file
+
+---
+ gdb/microblaze-linux-tdep.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
+index a37c4c86f4..68e73d2e56 100644
+--- a/gdb/microblaze-linux-tdep.c
++++ b/gdb/microblaze-linux-tdep.c
+@@ -37,7 +37,6 @@
+ #include "linux-tdep.h"
+ #include "glibc-tdep.h"
+ 
+-#include "gdb_assert.h"
+ 
+ #ifndef REGSET_H
+ #define REGSET_H 1
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
new file mode 100644
index 0000000000..46d51dd672
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
@@ -0,0 +1,39 @@
+From 1751b6fbc3170d29a3e2873b4394d058f8cb7d36 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 10:08:53 -0800
+Subject: [PATCH 46/52] bfd/cpu-microblaze.c: Enhance disassembler
+
+See commit aebcfb76fc165795e67917cb67cf985c4dfdc577 for why this is needed.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/cpu-microblaze.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
+index f3e8bbda75..f3501df0e2 100644
+--- a/bfd/cpu-microblaze.c
++++ b/bfd/cpu-microblaze.c
+@@ -39,7 +39,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   bfd_default_compatible,	/* Architecture comparison function.  */
+   bfd_default_scan,	   	/* String to architecture conversion.  */
+   bfd_arch_default_fill,	/* Default fill.  */
+-  &bfd_microblaze_arch[1]  	/* Next in list.  */
++  &bfd_microblaze_arch[1],  	/* Next in list.  */
++  0 /* Maximum offset of a reloc from the start of an insn.  */
+ },
+ {
+   32,				/* Bits in a word.  */
+@@ -71,7 +72,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
+   bfd_default_compatible,	/* Architecture comparison function.  */
+   bfd_default_scan,	   	/* String to architecture conversion.  */
+   bfd_arch_default_fill,	/* Default fill.  */
+-  &bfd_microblaze_arch[1]   	/* Next in list.  */
++  &bfd_microblaze_arch[1],   	/* Next in list.  */
++  0 /* Maximum offset of a reloc from the start of an insn.  */
+ },
+ {
+   64,		  		/* 32 bits in a word.  */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
new file mode 100644
index 0000000000..3bc5f04d96
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
@@ -0,0 +1,87 @@
+From 4500a281317093e78b7029e3dcb0037e7c628347 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 11:02:11 -0800
+Subject: [PATCH 47/52] bfd/elf64-microblaze.c: Fix build failures
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 338f16eeee..cf84e0db4e 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1572,7 +1572,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 			  {
+ 			    BFD_FAIL ();
+ 			    (*_bfd_error_handler)
+-			      (_("%B: probably compiled without -fPIC?"),
++			      (_("%pB: probably compiled without -fPIC?"),
+ 			       input_bfd);
+ 			    bfd_set_error (bfd_error_bad_value);
+ 			    return FALSE;
+@@ -2691,7 +2691,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+ 		/* If this is a global symbol, we count the number of
+ 		   relocations we need for this symbol.  */
+ 		if (h != NULL)
+-		  head = &h->dyn_relocs;
++		  head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs;
+ 		else
+ 		  {
+ 		    /* Track dynamic relocs needed for local syms too.
+@@ -2911,7 +2911,7 @@ microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
+ 
+   /* If we didn't find any dynamic relocs in read-only sections, then
+      we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
+-  if (!_bfd_elf_readonly_dynrelocs (h))
++  if (p == NULL)
+     {
+       h->non_got_ref = 0;
+       return TRUE;
+@@ -3096,7 +3096,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
+   else
+     h->got.offset = (bfd_vma) -1;
+ 
+-  if (h->dyn_relocs == NULL)
++  if (eh->dyn_relocs == NULL)
+     return TRUE;
+ 
+   /* In the shared -Bsymbolic case, discard space allocated for
+@@ -3113,7 +3113,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
+ 	{
+ 	  struct elf64_mb_dyn_relocs **pp;
+ 
+-	  for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
++	  for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
+ 	    {
+ 	      p->count -= p->pc_count;
+ 	      p->pc_count = 0;
+@@ -3124,7 +3124,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
+ 	    }
+ 	}
+       else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
+-	h->dyn_relocs = NULL;
++	eh->dyn_relocs = NULL;
+     }
+   else
+     {
+@@ -3154,13 +3154,13 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
+ 	    goto keep;
+ 	}
+ 
+-      h->dyn_relocs = NULL;
++      eh->dyn_relocs = NULL;
+ 
+     keep: ;
+     }
+ 
+   /* Finally, allocate space.  */
+-  for (p = h->dyn_relocs; p != NULL; p = p->next)
++  for (p = eh->dyn_relocs; p != NULL; p = p->next)
+     {
+       asection *sreloc = elf_section_data (p->sec)->sreloc;
+       sreloc->size += p->count * sizeof (Elf64_External_Rela);
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
new file mode 100644
index 0000000000..7feaceb944
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
@@ -0,0 +1,75 @@
+From 2f07425ca330dd357c374acdc30a27c6647454c9 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 11:23:26 -0800
+Subject: [PATCH 48/52] bfd/elf*-microblaze.c: Remove obsolete entries
+
+Replace microblaze_elf_merge_private_bfd_data with a direct call to
+_bfd_generic_verify_endian_match, this simplifies the implementation.
+
+Remove microblaze_elf_gc_sweep_hook, removed in 2017.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 29 +----------------------------
+ 1 file changed, 1 insertion(+), 28 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index cf84e0db4e..786f659232 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1690,21 +1690,6 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+   return ret;
+ }
+ 
+-/* Merge backend specific data from an object file to the output
+-   object file when linking.
+-
+-   Note: We only use this hook to catch endian mismatches.  */
+-static bfd_boolean
+-microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+-{
+-  /* Check if we have the same endianess.  */
+-  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
+-    return FALSE;
+-
+-  return TRUE;
+-}
+-
+-
+ /* Calculate fixup value for reference.  */
+ 
+ static int
+@@ -2427,17 +2412,6 @@ microblaze_elf_gc_mark_hook (asection *sec,
+   return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
+ }
+ 
+-/* Update the got entry reference counts for the section being removed.  */
+-
+-static bfd_boolean
+-microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
+-     			      struct bfd_link_info * info ATTRIBUTE_UNUSED,
+-     			      asection * sec ATTRIBUTE_UNUSED,
+-     			      const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
+-{
+-  return TRUE;
+-}
+-
+ /* PIC support.  */
+ 
+ #define PLT_ENTRY_SIZE 16
+@@ -3704,11 +3678,10 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
+ #define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
+ #define elf_backend_relocate_section		microblaze_elf_relocate_section
+ #define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
+-#define bfd_elf64_bfd_merge_private_bfd_data    microblaze_elf_merge_private_bfd_data
++#define bfd_elf64_bfd_merge_private_bfd_data    _bfd_generic_verify_endian_match
+ #define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
+ 
+ #define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
+-#define elf_backend_gc_sweep_hook		microblaze_elf_gc_sweep_hook
+ #define elf_backend_check_relocs                microblaze_elf_check_relocs
+ #define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
+ #define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
new file mode 100644
index 0000000000..5f4a27146f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
@@ -0,0 +1,45 @@
+From a86506136a738c3ab64d42a876fbfdfa1d46ad64 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 12:02:25 -0800
+Subject: [PATCH 49/52] bfd/elf64-microblaze.c: Resolve various compiler
+ warnings
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
+index 786f659232..70cd80cdf2 100644
+--- a/bfd/elf64-microblaze.c
++++ b/bfd/elf64-microblaze.c
+@@ -1258,6 +1258,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+ 	      goto dogot;
+ 	    case (int) R_MICROBLAZE_TLSLD:
+ 	      tls_type = (TLS_TLS | TLS_LD);
++              /* Fall through. */
+ 	    dogot:
+ 	    case (int) R_MICROBLAZE_GOT_64:
+ 	      {
+@@ -2569,6 +2570,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+           tls_type |= (TLS_TLS | TLS_LD);
+         dogottls:
+           sec->has_tls_reloc = 1;
++          /* Fall through. */
+         case R_MICROBLAZE_GOT_64:
+           if (htab->sgot == NULL)
+             {
+@@ -2802,10 +2804,8 @@ microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
+   struct elf64_mb_link_hash_table *htab;
+   struct elf64_mb_link_hash_entry * eh;
+   struct elf64_mb_dyn_relocs *p;
+-  asection *sdynbss;
+   asection *s, *srel;
+   unsigned int power_of_two;
+-  bfd *dynobj;
+ 
+   htab = elf64_mb_hash_table (info);
+   if (htab == NULL)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
new file mode 100644
index 0000000000..475a53ba1a
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
@@ -0,0 +1,37 @@
+From de38a354e40a9dcc486c93faf02bee4b059fa34a Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 12:30:09 -0800
+Subject: [PATCH 50/52] opcodes/microblaze-dis.c: Fix compile warnings
+
+Two compiler warnings were evident, it appears both are likely real bugs.
+
+Missing type declaration for a function, and a case statement without a break.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ opcodes/microblaze-dis.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 90d2328659..f1c33dca14 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -130,6 +130,7 @@ get_field_imm15 (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++static char *
+ get_field_imm16 (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+@@ -329,6 +330,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+ 		      get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
+           /* TODO: Also print symbol */
++          break;
+ 	case INST_TYPE_RD_R1_IMMS:
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+ 	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
new file mode 100644
index 0000000000..263f0a9bd2
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
@@ -0,0 +1,99 @@
+From f1686db8735972637d2bbcc6e2fbf391c1e848d9 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 14:51:37 -0800
+Subject: [PATCH 51/52] gdb/microblaze-tdep.c: Remove unused functions
+
+Compiler warns the removed functions are not referenced anywhere.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ gdb/microblaze-tdep.c | 45 -------------------------------------------
+ 1 file changed, 45 deletions(-)
+
+diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
+index 041ebf1fca..28f79f9ffc 100644
+--- a/gdb/microblaze-tdep.c
++++ b/gdb/microblaze-tdep.c
+@@ -140,14 +140,6 @@ microblaze_fetch_instruction (CORE_ADDR pc)
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-static CORE_ADDR
+-microblaze_store_arguments (struct regcache *regcache, int nargs,
+-			    struct value **args, CORE_ADDR sp,
+-			    int struct_return, CORE_ADDR struct_addr)
+-{
+-  error (_("store_arguments not implemented"));
+-  return sp;
+-}
+ #if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+@@ -555,12 +547,6 @@ microblaze_frame_base_address (struct frame_info *next_frame,
+   return cache->base;
+ }
+ 
+-static const struct frame_unwind *
+-microblaze_frame_sniffer (struct frame_info *next_frame)
+-{
+-  return &microblaze_frame_unwind;
+-}
+-
+ static const struct frame_base microblaze_frame_base =
+ {
+   &microblaze_frame_unwind,
+@@ -759,12 +745,6 @@ microblaze_software_single_step (struct regcache *regcache)
+ }
+ #endif
+ 
+-static void
+-microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
+-{
+-  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
+-}
+-
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -796,19 +776,6 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
+   return -1;
+ }
+ 
+-static void
+-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+-{
+-
+-  register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze64);
+-
+-  register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze64_with_stack_protect);
+-}
+-
+ void
+ microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+                         struct regcache *regcache,
+@@ -873,18 +840,6 @@ microblaze_regset_from_core_section (struct gdbarch *gdbarch,
+ }
+ 
+ 
+-static void
+-make_regs (struct gdbarch *arch)
+-{
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+-  int mach = gdbarch_bfd_arch_info (arch)->mach;
+-  
+-  if (mach == bfd_mach_microblaze64)
+-    {
+-      set_gdbarch_ptr_bit (arch, 64);
+-    }
+-}
+-
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0052-sim-Allow-microblaze-architecture.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0052-sim-Allow-microblaze-architecture.patch
new file mode 100644
index 0000000000..ee5caf0a63
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0052-sim-Allow-microblaze-architecture.patch
@@ -0,0 +1,40 @@
+From 5fa859e73662f96c9cfaf21bd2cf01b92afc9c1c Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Thu, 6 Aug 2020 15:37:52 -0500
+Subject: [PATCH 52/52] sim: Allow microblaze* architecture
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ sim/configure     | 2 +-
+ sim/configure.tgt | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/sim/configure b/sim/configure
+index 72f95cd5c7..9e28cc7868 100755
+--- a/sim/configure
++++ b/sim/configure
+@@ -3795,7 +3795,7 @@ subdirs="$subdirs aarch64"
+ 
+ 
+        ;;
+-   microblaze-*-*)
++   microblaze*-*-*)
+ 
+   sim_arch=microblaze
+   subdirs="$subdirs microblaze"
+diff --git a/sim/configure.tgt b/sim/configure.tgt
+index 8a8e03d96f..f6743fe8d4 100644
+--- a/sim/configure.tgt
++++ b/sim/configure.tgt
+@@ -59,7 +59,7 @@ case "${target}" in
+    mcore-*-*)
+        SIM_ARCH(mcore)
+        ;;
+-   microblaze-*-*)
++   microblaze*-*-*)
+        SIM_ARCH(microblaze)
+        ;;
+    mips*-*-*)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0053-gdb-Fix-microblaze-target-compilation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0053-gdb-Fix-microblaze-target-compilation.patch
new file mode 100644
index 0000000000..af0e326889
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/binutils/binutils/0053-gdb-Fix-microblaze-target-compilation.patch
@@ -0,0 +1,288 @@
+From efa3750ffda1ae16caf071b8b8ea31f752a3324a Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Mon, 7 Dec 2020 12:03:25 -0600
+Subject: [PATCH] gdb: Fix microblaze target compilation
+
+Add microblaze-linux-nat.c to configure.nat
+
+Transition microblaze-linux-nat.c to use the new gdb C++ style functions.
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ gdb/configure.nat          |  5 ++
+ gdb/microblaze-linux-nat.c | 96 ++++++++++++++------------------------
+ gdb/microblaze-tdep.h      |  3 ++
+ 3 files changed, 43 insertions(+), 61 deletions(-)
+
+diff --git a/gdb/configure.nat b/gdb/configure.nat
+index 6ea2583495..1fba80f6c9 100644
+--- a/gdb/configure.nat
++++ b/gdb/configure.nat
+@@ -261,6 +261,11 @@ case ${gdb_host} in
+ 		# Host: Motorola m68k running GNU/Linux.
+ 		NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o"
+ 		;;
++	    microblaze)
++		# Host: Microblaze running GNU/Linux.
++		NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o"
++		NAT_CDEPS=
++		;;
+ 	    mips)
+ 		# Host: Linux/MIPS
+ 		NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+index e9b8c9c522..bac4697e1e 100644
+--- a/gdb/microblaze-linux-nat.c
++++ b/gdb/microblaze-linux-nat.c
+@@ -36,13 +36,14 @@
+ #include "dwarf2-frame.h"
+ #include "osabi.h"
+ 
+-#include "gdb_assert.h"
+-#include "gdb_string.h"
++#include "gdbsupport/gdb_assert.h"
++#include <string.h>
+ #include "target-descriptions.h"
+ #include "opcodes/microblaze-opcm.h"
+ #include "opcodes/microblaze-dis.h"
+ 
+ #include "linux-nat.h"
++#include "linux-tdep.h"
+ #include "target-descriptions.h"
+ 
+ #include <sys/user.h>
+@@ -61,22 +62,17 @@
+ /* Defines ps_err_e, struct ps_prochandle.  */
+ #include "gdb_proc_service.h"
+ 
+-/* On GNU/Linux, threads are implemented as pseudo-processes, in which
+-   case we may be tracing more than one process at a time.  In that
+-   case, inferior_ptid will contain the main process ID and the
+-   individual thread (process) ID.  get_thread_id () is used to get
+-   the thread id if it's available, and the process id otherwise.  */
+-
+-int
+-get_thread_id (ptid_t ptid)
++class microblaze_linux_nat_target final : public linux_nat_target
+ {
+-  int tid = TIDGET (ptid);
+-  if (0 == tid)
+-    tid = PIDGET (ptid);
+-  return tid;
+-}
++public:
++  /* Add our register access methods.  */
++  void fetch_registers (struct regcache *, int) override;
++  void store_registers (struct regcache *, int) override;
++
++  const struct target_desc *read_description () override;
++};
+ 
+-#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
++static microblaze_linux_nat_target the_microblaze_linux_nat_target;
+ 
+ /* Non-zero if our kernel may support the PTRACE_GETREGS and
+    PTRACE_SETREGS requests, for reading and writing the
+@@ -88,7 +84,6 @@ static int
+ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ {
+   int u_addr = -1;
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
+      interface, and not the wordsize of the program's ABI.  */
+   int wordsize = sizeof (long);
+@@ -105,18 +100,16 @@ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ static void
+ fetch_register (struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  struct gdbarch *gdbarch = regcache->arch ();
+   /* This isn't really an address.  But ptrace thinks of it as one.  */
+   CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+   int bytes_transferred;
+-  unsigned int offset;         /* Offset of registers within the u area.  */
+-  char buf[MAX_REGISTER_SIZE];
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
+ 
+   if (regaddr == -1)
+   {
+     memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
+-    regcache_raw_supply (regcache, regno, buf);
++    regcache->raw_supply (regno, buf);
+     return;
+   }
+ 
+@@ -149,14 +142,14 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+   {
+     /* Little-endian values are always found at the left end of the
+        bytes transferred.  */
+-    regcache_raw_supply (regcache, regno, buf);
++    regcache->raw_supply (regno, buf);
+   }
+   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+   {
+     /* Big-endian values are found at the right end of the bytes
+        transferred.  */
+     size_t padding = (bytes_transferred - register_size (gdbarch, regno));
+-    regcache_raw_supply (regcache, regno, buf + padding);
++    regcache->raw_supply (regno, buf + padding);
+   }
+   else
+     internal_error (__FILE__, __LINE__,
+@@ -175,8 +168,6 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+ static int
+ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   gdb_gregset_t gregset;
+ 
+   if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -204,8 +195,6 @@ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ static void
+ fetch_gp_regs (struct regcache *regcache, int tid)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   int i;
+ 
+   if (have_ptrace_getsetregs)
+@@ -223,13 +212,12 @@ fetch_gp_regs (struct regcache *regcache, int tid)
+ static void
+ store_register (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  struct gdbarch *gdbarch = regcache->arch ();
+   /* This isn't really an address.  But ptrace thinks of it as one.  */
+   CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+   int i;
+   size_t bytes_to_transfer;
+-  char buf[MAX_REGISTER_SIZE];
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
+ 
+   if (regaddr == -1)
+     return;
+@@ -242,13 +230,13 @@ store_register (const struct regcache *regcache, int tid, int regno)
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+   {
+     /* Little-endian values always sit at the left end of the buffer.  */
+-    regcache_raw_collect (regcache, regno, buf);
++    regcache->raw_collect (regno, buf);
+   }
+   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+   {
+     /* Big-endian values sit at the right end of the buffer.  */
+     size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
+-    regcache_raw_collect (regcache, regno, buf + padding);
++    regcache->raw_collect (regno, buf + padding);
+   }
+ 
+   for (i = 0; i < bytes_to_transfer; i += sizeof (long))
+@@ -281,8 +269,6 @@ store_register (const struct regcache *regcache, int tid, int regno)
+ static int
+ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   gdb_gregset_t gregset;
+ 
+   if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -319,8 +305,6 @@ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ static void
+ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   int i;
+ 
+   if (have_ptrace_getsetregs)
+@@ -339,12 +323,12 @@ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+    regno == -1, otherwise fetch all general registers or all floating
+    point registers depending upon the value of regno.  */
+ 
+-static void
+-microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+-				    struct regcache *regcache, int regno)
++void
++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache,
++                                              int regno)
+ {
+   /* Get the thread id for the ptrace call.  */
+-  int tid = GET_THREAD_ID (inferior_ptid);
++  int tid = regcache->ptid ().lwp ();
+ 
+   if (regno == -1)
+     fetch_gp_regs (regcache, tid);
+@@ -356,12 +340,12 @@ microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+    regno == -1, otherwise store all general registers or all floating
+    point registers depending upon the value of regno.  */
+ 
+-static void
+-microblaze_linux_store_inferior_registers (struct target_ops *ops,
+-				    struct regcache *regcache, int regno)
++void
++microblaze_linux_nat_target::store_registers (struct regcache *regcache,
++                                              int regno)
+ {
+   /* Get the thread id for the ptrace call.  */
+-  int tid = GET_THREAD_ID (inferior_ptid);
++  int tid = regcache->ptid ().lwp ();
+ 
+   if (regno >= 0)
+     store_register (regcache, tid, regno);
+@@ -398,12 +382,12 @@ supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+   /* FIXME. */
+ }
+ 
+-static const struct target_desc *
+-microblaze_linux_read_description (struct target_ops *ops)
++const struct target_desc *
++microblaze_linux_nat_target::read_description ()
+ {
+-  CORE_ADDR microblaze_hwcap = 0;
++  CORE_ADDR microblaze_hwcap = linux_get_hwcap (this);
+ 
+-  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
++  if (microblaze_hwcap != 1)
+     return NULL;
+ 
+   return NULL;
+@@ -415,17 +399,7 @@ void _initialize_microblaze_linux_nat (void);
+ void
+ _initialize_microblaze_linux_nat (void)
+ {
+-  struct target_ops *t;
+-
+-  /* Fill in the generic GNU/Linux methods.  */
+-  t = linux_target ();
+-
+-  /* Add our register access methods.  */
+-  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
+-  t->to_store_registers = microblaze_linux_store_inferior_registers;
+-
+-  t->to_read_description = microblaze_linux_read_description;
+-
+   /* Register the target.  */
+-  linux_nat_add_target (t);
++  linux_target = &the_microblaze_linux_nat_target;
++  add_inf_child_target (&the_microblaze_linux_nat_target);
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index c0fc900733..c777d93a95 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -106,6 +106,9 @@ enum microblaze_regnum
+   MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+ 
++/* Big enough to hold the size of the largest register in bytes.  */
++#define MICROBLAZE_MAX_REGISTER_SIZE   64
++
+ struct microblaze_frame_cache
+ {
+   /* Base address.  */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
index af5a65cbac..e0f7b12e91 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch
@@ -1,26 +1,32 @@
-From d2ebb14b318166dd91fe35bf3531d758dcbc995a Mon Sep 17 00:00:00 2001
+From e3f148dff6d6d926d1f39802f54abd59bd9e887c Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 13:13:57 +0530
-Subject: [PATCH 01/58] [LOCAL]: Testsuite - builtins tests require fpic
+Subject: [PATCH 01/54] LOCAL]: Testsuite - builtins tests require fpic
+ Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
 
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+Conflicts:
+
+	gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 ---
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 5 +++++
- 1 file changed, 5 insertions(+)
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 8 ++++++++
+ 1 file changed, 8 insertions(+)
 
 diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 594c9297958..4103d43748d 100644
+index 594c9297958..8350d9401d2 100644
 --- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
 +++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -48,6 +48,11 @@ if { [istarget *-*-eabi*]
+@@ -48,6 +48,14 @@ if { [istarget *-*-eabi*]
     lappend additional_flags "-Wl,--allow-multiple-definition"
  }
  
++<<<<<<< HEAD
++=======
 +if [istarget "microblaze*-*-linux*"] {
 +   lappend additional_flags "-Wl,-zmuldefs"
 +   lappend additional_flags "-fPIC"
 +}
 +
++>>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
  foreach src [lsort [find $srcdir/$subdir *.c]] {
      if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
  	c-torture-execute [list $src \
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
index 976896da26..431dc7ef27 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch
@@ -1,11 +1,10 @@
-From 54394232ffbaa9474f8a78c6882f08a48842242e Mon Sep 17 00:00:00 2001
+From bef1a4116efded9972e693ded5152f1d8670862e Mon Sep 17 00:00:00 2001
 From: Mahesh Bodapati <mbodapat@xilinx.com>
 Date: Wed, 11 Jan 2017 14:31:10 +0530
-Subject: [PATCH 02/58] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C
-
-This particular testcase fails with a timeout. Instead, fail it
-at compile-time for microblaze. This speeds up the testsuite without
-removing it from the FAIL reports.
+Subject: [PATCH 02/54] [LOCAL]: Quick fail g++.dg/opt/memcpy1.C This
+ particular testcase fails with a timeout. Instead, fail it at compile-time
+ for microblaze. This speeds up the testsuite without removing it from the
+ FAIL reports.
 
 Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 ---
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
new file mode 100644
index 0000000000..a2dc7cccfe
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
@@ -0,0 +1,35 @@
+From a063597f875142af49003e2f28b6c0f56e3b914d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:46:28 +0530
+Subject: [PATCH 03/54] [LOCAL]: For dejagnu static testing on qemu, suppress
+ warnings about multiple definitions from the test function and libc in line
+ with method used by powerpc. Dynamic linking and using a qemu binary which
+ understands sysroot resolves all test failures with builtins
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 4 ----
+ 1 file changed, 4 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+index 8350d9401d2..d7c9b281d01 100644
+--- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
++++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
+@@ -48,14 +48,10 @@ if { [istarget *-*-eabi*]
+    lappend additional_flags "-Wl,--allow-multiple-definition"
+ }
+ 
+-<<<<<<< HEAD
+-=======
+ if [istarget "microblaze*-*-linux*"] {
+    lappend additional_flags "-Wl,-zmuldefs"
+-   lappend additional_flags "-fPIC"
+ }
+ 
+->>>>>>> 6ef6e5b... [LOCAL]: Testsuite - builtins tests require fpic
+ foreach src [lsort [find $srcdir/$subdir *.c]] {
+     if {![string match *-lib.c $src] && [runtest_file_p $runtests $src]} {
+ 	c-torture-execute [list $src \
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
deleted file mode 100644
index 8e6d22dbcf..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch
+++ /dev/null
@@ -1,117 +0,0 @@
-From f0a446bcb453630d8116b30f542aee79407228ea Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:28:38 +0530
-Subject: [PATCH 03/58] [LOCAL]: Testsuite - explicitly add -fivopts for tests
- that depend on it
-
-(test gcc/testsuite/gcc.dg/tree-ssa/ivopts-lt.c doesnt exist in 4.6 branch)
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C   | 2 +-
- gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C   | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-2.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-4.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/loop-5.c     | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c  | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/pr19590.c    | 2 +-
- gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c | 2 +-
- 8 files changed, 8 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-index 438db882043..ede883eb284 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-2.C
-@@ -1,5 +1,5 @@
- /* { dg-do compile { target { i?86-*-* x86_64-*-*  } } } */
--/* { dg-options "-O2 -fdump-tree-ivopts-details" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" } */
- 
- void test (int *b, int *e, int stride)
-   {
-diff --git a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-index cbb6c850baa..34248021c23 100644
---- a/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-+++ b/gcc/testsuite/g++.dg/tree-ssa/ivopts-3.C
-@@ -1,5 +1,5 @@
- // { dg-do compile }
--// { dg-options "-O2 -fdump-tree-ivopts-details" }
-+// { dg-options "-O2 -fivopts -fdump-tree-ivopts-details" }
- 
- class MinimalVec3
- {
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-index bda25167353..22c8a5dcffe 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-2.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-index f0770abdbbc..65d74c8e620 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-4.c
-@@ -1,7 +1,7 @@
- /* A test for strength reduction and induction variable elimination.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- /* { dg-require-effective-target size32plus } */
- 
- /* Size of this structure should be sufficiently weird so that no memory
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-index 5f42857fe13..9bc86ee0d23 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/loop-5.c
-@@ -1,7 +1,7 @@
- /* A test for induction variable merging.  */
- 
- /* { dg-do compile } */
--/* { dg-options "-O1 -fdump-tree-optimized" } */
-+/* { dg-options "-O1 -fivopts -fdump-tree-optimized" } */
- 
- void foo(long);
- 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-index 50d86a00485..1e3eacd33d1 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19210-1.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fopt-info-loop-missed" } */
-+/* { dg-options "-O2 -fivopts -fopt-info-loop-missed" } */
- extern void g(void);
- 
- void
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-index 2c6cfc6f831..648e6e67e80 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr19590.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-O2 -fdump-tree-ivopts" } */
-+/* { dg-options "-O2 -fivopts -fdump-tree-ivopts" } */
- 
- void vnum_test8(int *data) 
- { 
-diff --git a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-index e911bfcd521..5d3e7e0801a 100644
---- a/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-+++ b/gcc/testsuite/gcc.dg/tree-ssa/reassoc-19.c
-@@ -1,5 +1,5 @@
- /* { dg-do compile } */
--/* { dg-options "-Os -fdump-tree-optimized" } */
-+/* { dg-options "-Os -fivopts -fdump-tree-optimized" } */
- 
- /* Slightly changed testcase from PR middle-end/40815.  */
- void bar(char*, char*, int);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
deleted file mode 100644
index 4974462c16..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From f8809fdebc3ef3927695c84224d3446fa13447d6 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:46:28 +0530
-Subject: [PATCH 04/58] [LOCAL]: For dejagnu static testing on qemu, suppress
- warnings
-
-about multiple definitions from the test function and libc in line
-with method used by powerpc. Dynamic linking and using a qemu binary
-which understands sysroot resolves all test failures with builtins
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-index 4103d43748d..d7c9b281d01 100644
---- a/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-+++ b/gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp
-@@ -50,7 +50,6 @@ if { [istarget *-*-eabi*]
- 
- if [istarget "microblaze*-*-linux*"] {
-    lappend additional_flags "-Wl,-zmuldefs"
--   lappend additional_flags "-fPIC"
- }
- 
- foreach src [lsort [find $srcdir/$subdir *.c]] {
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
new file mode 100644
index 0000000000..661417d781
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
@@ -0,0 +1,35 @@
+From c1028bcb40ccd8d61afc1ab798198948fbf74aa0 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 15:50:35 +0530
+Subject: [PATCH 04/54] [Patch, testsuite]: Add MicroBlaze to target-supports
+ for atomic buil. .tin tests
+
+MicroBlaze added to supported targets for atomic builtin tests.
+
+Changelog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/lib/target-supports.exp: Add microblaze to
+   check_effective_target_sync_int_long.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 0dfe3ae0651..86caf6db9a9 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -7468,6 +7468,7 @@ proc check_effective_target_sync_int_long { } {
+ 		 && [check_effective_target_arm_acq_rel])
+ 	     || [istarget bfin*-*linux*]
+ 	     || [istarget hppa*-*linux*]
++	     || [istarget microblaze*-*linux*]
+ 	     || [istarget s390*-*-*] 
+ 	     || [istarget powerpc*-*-*]
+ 	     || [istarget crisv32-*-*] || [istarget cris-*-*]
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
deleted file mode 100644
index c21492e837..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 802078fa3e76ea7fdb29f3baf1d4d9baae42bc0b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 15:50:35 +0530
-Subject: [PATCH 05/58] [Patch, testsuite]: Add MicroBlaze to target-supports
- for atomic builtin tests
-
-MicroBlaze added to supported targets for atomic builtin tests.
-
-Changelog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/lib/target-supports.exp: Add microblaze to
-   check_effective_target_sync_int_long.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/lib/target-supports.exp | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index 13761491e63..d2f65dac32c 100644
---- a/gcc/testsuite/lib/target-supports.exp
-+++ b/gcc/testsuite/lib/target-supports.exp
-@@ -7581,6 +7581,7 @@ proc check_effective_target_sync_int_long { } {
- 		 && [check_effective_target_arm_acq_rel])
- 	     || [istarget bfin*-*linux*]
- 	     || [istarget hppa*-*linux*]
-+	     || [istarget microblaze*-*linux*]
- 	     || [istarget s390*-*-*] 
- 	     || [istarget powerpc*-*-*]
- 	     || [istarget crisv32-*-*] || [istarget cris-*-*]
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
new file mode 100644
index 0000000000..d34988c553
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch
@@ -0,0 +1,43 @@
+From ae5ce07a67df89dabba61414ba7dabbdabc1ee1b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 11 Jan 2017 16:20:01 +0530
+Subject: [PATCH 05/54] [Patch, testsuite]: Update MicroBlaze strings test for
+ new scan-assembly output resulting in use of $LC label
+
+ChangeLog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
+   to include $LC label.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+index 7a63faf79f2..0403b7bdca9 100644
+--- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
++++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
+@@ -1,13 +1,15 @@
+ /* { dg-options "-O3" } */
+ 
++/* { dg-final { scan-assembler "\.rodata*" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
++/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
++
+ #include <string.h>
+ 
+-/* { dg-final { scan-assembler "\.rodata*" } } */
+ extern void somefunc (char *);
+ int testfunc ()
+ {
+     char string2[80];
+-/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
+     strcpy (string2, "hello");
+     somefunc (string2);
+ }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
new file mode 100644
index 0000000000..4b45fcf1e9
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
@@ -0,0 +1,67 @@
+From 49cf9cd3fedce80a63e9d03d42482dd4596c27a7 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:14:15 +0530
+Subject: [PATCH 06/54] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
+ in regex match Extend regex pattern to include optional ext at the end of
+ .weak to match the MicroBlaze weak label .weakext
+
+ChangeLog/testsuite
+
+2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
+   pattern to take optional ext after .weak.
+ * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+
+	gcc/testsuite/g++.dg/abi/rtti3.C
+---
+ gcc/testsuite/g++.dg/abi/rtti3.C  | 4 ++--
+ gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
+ gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
+index 0cc7d3e79d0..f284cd9255c 100644
+--- a/gcc/testsuite/g++.dg/abi/rtti3.C
++++ b/gcc/testsuite/g++.dg/abi/rtti3.C
+@@ -3,8 +3,8 @@
+ 
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
+-// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
+ 
+diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
+index f2347f79ecd..dcec8a771a1 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk3.C
++++ b/gcc/testsuite/g++.dg/abi/thunk3.C
+@@ -1,5 +1,5 @@
+ // { dg-require-weak "" }
+-// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+ 
+ struct Base 
+diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
+index 6e8f124bc5e..d1d34fe1e4a 100644
+--- a/gcc/testsuite/g++.dg/abi/thunk4.C
++++ b/gcc/testsuite/g++.dg/abi/thunk4.C
+@@ -1,6 +1,6 @@
+ // { dg-require-weak "" }
+ // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
+-// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
++// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
+ // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
+ 
+ struct Base 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
deleted file mode 100644
index 9c8cce92dc..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 8c24cb4f95f46793ac7500a5d6181d93f2b0d2c5 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 11 Jan 2017 16:20:01 +0530
-Subject: [PATCH 06/58] [Patch, testsuite]: Update MicroBlaze strings test
-
-for new scan-assembly output resulting in use of $LC label
-
-ChangeLog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update
-   to include $LC label.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/gcc.target/microblaze/others/strings1.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/testsuite/gcc.target/microblaze/others/strings1.c b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-index 7a63faf79f2..0403b7bdca9 100644
---- a/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-+++ b/gcc/testsuite/gcc.target/microblaze/others/strings1.c
-@@ -1,13 +1,15 @@
- /* { dg-options "-O3" } */
- 
-+/* { dg-final { scan-assembler "\.rodata*" } } */
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),\\\$LC.*" } } */
-+/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),*" } } */
-+
- #include <string.h>
- 
--/* { dg-final { scan-assembler "\.rodata*" } } */
- extern void somefunc (char *);
- int testfunc ()
- {
-     char string2[80];
--/* { dg-final { scan-assembler "\lwi\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,.LC*" } } */    
-     strcpy (string2, "hello");
-     somefunc (string2);
- }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
new file mode 100644
index 0000000000..8fa324ad7e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
@@ -0,0 +1,28 @@
+From dc6cbb4e18a3f31441403146b8f159554c329897 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:34:27 +0530
+Subject: [PATCH 07/54] [Patch, testsuite]: Add MicroBlaze to
+ check_profiling_available Testsuite, add microblaze*-*-* target in
+ check_profiling_available inline with other archs setting
+ profiling_available_saved to 0
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/testsuite/lib/target-supports.exp | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
+index 86caf6db9a9..cbd9024ece9 100644
+--- a/gcc/testsuite/lib/target-supports.exp
++++ b/gcc/testsuite/lib/target-supports.exp
+@@ -707,6 +707,7 @@ proc check_profiling_available { test_what } {
+ 	     || [istarget m68k-*-elf]
+ 	     || [istarget m68k-*-uclinux*]
+ 	     || [istarget mips*-*-elf*]
++	     || [istarget microblaze*-*-*]
+ 	     || [istarget mmix-*-*]
+ 	     || [istarget mn10300-*-elf*]
+ 	     || [istarget moxie-*-elf*]
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
deleted file mode 100644
index 4d1e2017bf..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 38ece4b2dc5d34c1b88b6ea8dd8e62a0986f8f6c Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:14:15 +0530
-Subject: [PATCH 07/58] [Patch, testsuite]: Allow MicroBlaze .weakext pattern
- in regex match
-
-Extend regex pattern to include optional ext at the end of
-.weak to match the MicroBlaze weak label .weakext
-
-ChangeLog/testsuite
-
-2014-02-14  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler
-   pattern to take optional ext after .weak.
- * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
-Conflicts:
-
-	gcc/testsuite/g++.dg/abi/rtti3.C
----
- gcc/testsuite/g++.dg/abi/rtti3.C  | 4 ++--
- gcc/testsuite/g++.dg/abi/thunk3.C | 2 +-
- gcc/testsuite/g++.dg/abi/thunk4.C | 2 +-
- 3 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/testsuite/g++.dg/abi/rtti3.C b/gcc/testsuite/g++.dg/abi/rtti3.C
-index 0cc7d3e79d0..f284cd9255c 100644
---- a/gcc/testsuite/g++.dg/abi/rtti3.C
-+++ b/gcc/testsuite/g++.dg/abi/rtti3.C
-@@ -3,8 +3,8 @@
- 
- // { dg-require-weak "" }
- // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
--// { dg-final { scan-assembler ".weak\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* hppa*-*-hpux* } } } } }
--// { dg-final { scan-assembler-not ".weak\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZTSPP1A" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler-not ".weak(ext)?\[ \t\]_?_ZTIPP1A" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZTSPP1A" { target { *-*-darwin* } } } }
- // { dg-final { scan-assembler-not ".weak_definition\[ \t\]_?_ZTIPP1A" { target { *-*-darwin* } } } }
- 
-diff --git a/gcc/testsuite/g++.dg/abi/thunk3.C b/gcc/testsuite/g++.dg/abi/thunk3.C
-index f2347f79ecd..dcec8a771a1 100644
---- a/gcc/testsuite/g++.dg/abi/thunk3.C
-+++ b/gcc/testsuite/g++.dg/abi/thunk3.C
-@@ -1,5 +1,5 @@
- // { dg-require-weak "" }
--// { dg-final { scan-assembler-not ".weak\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler-not ".weak(ext)?\[\t \]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler-not ".weak_definition\[\t \]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
- 
- struct Base 
-diff --git a/gcc/testsuite/g++.dg/abi/thunk4.C b/gcc/testsuite/g++.dg/abi/thunk4.C
-index 6e8f124bc5e..d1d34fe1e4a 100644
---- a/gcc/testsuite/g++.dg/abi/thunk4.C
-+++ b/gcc/testsuite/g++.dg/abi/thunk4.C
-@@ -1,6 +1,6 @@
- // { dg-require-weak "" }
- // { dg-skip-if "Linkonce not weak" { *-*-mingw* *-*-cygwin } }
--// { dg-final { scan-assembler ".weak\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
-+// { dg-final { scan-assembler ".weak(ext)?\[ \t\]_?_ZThn._N7Derived3FooEv" { target { ! { *-*-darwin* } } } } }
- // { dg-final { scan-assembler ".weak_definition\[ \t\]_?_ZThn._N7Derived3FooEv" { target { *-*-darwin* } } } }
- 
- struct Base 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch
new file mode 100644
index 0000000000..1fa5572996
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-microblaze-Fix-atomic-side-effects.patch
@@ -0,0 +1,68 @@
+From 602713d07d2e1b3a33a7f097baff270266aa4254 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:41:43 +0530
+Subject: [PATCH 08/54] [Patch, microblaze]: Fix atomic side effects. In
+ atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions
+ during optimization. Previously, the outputs were considered unused; this
+ generated assembly code with undefined side effects after invocation of the
+ atomic.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
+---
+ gcc/config/microblaze/microblaze.md |  3 +++
+ gcc/config/microblaze/sync.md       | 21 +++++++++++++--------
+ 2 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7049acd1dcd..eba2776ae56 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -43,6 +43,9 @@
+   (UNSPEC_TLS           106)    ;; jump table
+   (UNSPEC_SET_TEXT      107)    ;; set text start
+   (UNSPEC_TEXT          108)    ;; data text relative
++  (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
++  (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
++  (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
+ ])
+ 
+ (define_c_enum "unspec" [
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 76f530b9d3b..24cd67e1fdb 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -18,14 +18,19 @@
+ ;; <http://www.gnu.org/licenses/>.
+ 
+ (define_insn "atomic_compare_and_swapsi"
+-  [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
+-   (match_operand:SI 1 "register_operand" "=&d")	;; val output
+-   (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
+-   (match_operand:SI 3 "register_operand" "d")		;; expected value
+-   (match_operand:SI 4 "register_operand" "d")		;; desired value
+-   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
+-   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
+-   (match_operand:SI 7 "const_int_operand" "")		;; mod_f
++  [(set (match_operand:SI 0 "register_operand" "=&d")		;; bool output
++        (unspec_volatile:SI
++          [(match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
++           (match_operand:SI 3 "register_operand" "d")		;; expected value
++           (match_operand:SI 4 "register_operand" "d")]		;; desired value
++          UNSPECV_CAS_BOOL))
++   (set (match_operand:SI 1 "register_operand" "=&d")		;; val output
++        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
++   (set (match_dup 2)
++        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
++   (match_operand:SI 5 "const_int_operand" "")			;; is_weak
++   (match_operand:SI 6 "const_int_operand" "")			;; mod_s
++   (match_operand:SI 7 "const_int_operand" "")			;; mod_f
+    (clobber (match_scratch:SI 8 "=&d"))]
+   ""
+   {
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
deleted file mode 100644
index f96d7d57fd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From bc5f423bcfa24aa8c15548379bfc6b3f49e57c15 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:34:27 +0530
-Subject: [PATCH 08/58] [Patch, testsuite]: Add MicroBlaze to
- check_profiling_available
-
-Testsuite, add microblaze*-*-* target in check_profiling_available
-inline with other archs setting profiling_available_saved to 0
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/testsuite/lib/target-supports.exp | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
-index d2f65dac32c..d949fbd8464 100644
---- a/gcc/testsuite/lib/target-supports.exp
-+++ b/gcc/testsuite/lib/target-supports.exp
-@@ -707,6 +707,7 @@ proc check_profiling_available { test_what } {
- 	     || [istarget m68k-*-elf]
- 	     || [istarget m68k-*-uclinux*]
- 	     || [istarget mips*-*-elf*]
-+	     || [istarget microblaze*-*-*]
- 	     || [istarget mmix-*-*]
- 	     || [istarget mn10300-*-elf*]
- 	     || [istarget moxie-*-elf*]
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
new file mode 100644
index 0000000000..666d344f37
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch
@@ -0,0 +1,40 @@
+From d3d065c9645d795e03dab6db827c08231e011a1f Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:45:45 +0530
+Subject: [PATCH 09/54] [Patch, microblaze]: Fix atomic boolean return value.
+ In atomic_compare_and_swapsi, fix boolean return value. Previously, it
+ contained zero if successful and non-zero if unsuccessful.
+
+Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/sync.md | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
+index 24cd67e1fdb..76c3616c992 100644
+--- a/gcc/config/microblaze/sync.md
++++ b/gcc/config/microblaze/sync.md
+@@ -34,15 +34,16 @@
+    (clobber (match_scratch:SI 8 "=&d"))]
+   ""
+   {
+-    output_asm_insn ("addc \tr0,r0,r0", operands);
++    output_asm_insn ("add  \t%0,r0,r0", operands);
+     output_asm_insn ("lwx  \t%1,%y2,r0", operands);
+     output_asm_insn ("addic\t%8,r0,0", operands);
+     output_asm_insn ("bnei \t%8,.-8", operands);
+-    output_asm_insn ("cmp  \t%0,%1,%3", operands);
+-    output_asm_insn ("bnei \t%0,.+16", operands);
++    output_asm_insn ("cmp  \t%8,%1,%3", operands);
++    output_asm_insn ("bnei \t%8,.+20", operands);
+     output_asm_insn ("swx  \t%4,%y2,r0", operands);
+     output_asm_insn ("addic\t%8,r0,0", operands);
+     output_asm_insn ("bnei \t%8,.-28", operands);
++    output_asm_insn ("addi \t%0,r0,1", operands);
+     return "";
+   }
+ )
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
deleted file mode 100644
index 45d93ceef0..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0009-Patch-microblaze-Fix-atomic-side-effects.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From eeeb8ecda7cb71c033c850ce36162c92c7d0b781 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:41:43 +0530
-Subject: [PATCH 09/58] [Patch, microblaze]: Fix atomic side effects.
-
-In atomic_compare_and_swapsi, add side effects to prevent incorrect
-assumptions during optimization. Previously, the outputs were
-considered unused; this generated assembly code with
-undefined side effects after invocation of the atomic.
-
-Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
-
-Conflicts:
-	gcc/config/microblaze/microblaze.md
----
- gcc/config/microblaze/microblaze.md |  3 +++
- gcc/config/microblaze/sync.md       | 21 +++++++++++++--------
- 2 files changed, 16 insertions(+), 8 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7049acd1dcd..eba2776ae56 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -43,6 +43,9 @@
-   (UNSPEC_TLS           106)    ;; jump table
-   (UNSPEC_SET_TEXT      107)    ;; set text start
-   (UNSPEC_TEXT          108)    ;; data text relative
-+  (UNSPECV_CAS_BOOL     201)    ;; compare and swap (bool)
-+  (UNSPECV_CAS_VAL      202)    ;; compare and swap (val)
-+  (UNSPECV_CAS_MEM      203)    ;; compare and swap (mem)
- ])
- 
- (define_c_enum "unspec" [
-diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 76f530b9d3b..24cd67e1fdb 100644
---- a/gcc/config/microblaze/sync.md
-+++ b/gcc/config/microblaze/sync.md
-@@ -18,14 +18,19 @@
- ;; <http://www.gnu.org/licenses/>.
- 
- (define_insn "atomic_compare_and_swapsi"
--  [(match_operand:SI 0 "register_operand" "=&d")	;; bool output
--   (match_operand:SI 1 "register_operand" "=&d")	;; val output
--   (match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
--   (match_operand:SI 3 "register_operand" "d")		;; expected value
--   (match_operand:SI 4 "register_operand" "d")		;; desired value
--   (match_operand:SI 5 "const_int_operand" "")		;; is_weak
--   (match_operand:SI 6 "const_int_operand" "")		;; mod_s
--   (match_operand:SI 7 "const_int_operand" "")		;; mod_f
-+  [(set (match_operand:SI 0 "register_operand" "=&d")		;; bool output
-+        (unspec_volatile:SI
-+          [(match_operand:SI 2 "nonimmediate_operand" "+Q")	;; memory
-+           (match_operand:SI 3 "register_operand" "d")		;; expected value
-+           (match_operand:SI 4 "register_operand" "d")]		;; desired value
-+          UNSPECV_CAS_BOOL))
-+   (set (match_operand:SI 1 "register_operand" "=&d")		;; val output
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_VAL))
-+   (set (match_dup 2)
-+        (unspec_volatile:SI [(const_int 0)] UNSPECV_CAS_MEM))
-+   (match_operand:SI 5 "const_int_operand" "")			;; is_weak
-+   (match_operand:SI 6 "const_int_operand" "")			;; mod_s
-+   (match_operand:SI 7 "const_int_operand" "")			;; mod_f
-    (clobber (match_scratch:SI 8 "=&d"))]
-   ""
-   {
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
deleted file mode 100644
index 48f77215dc..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch
+++ /dev/null
@@ -1,42 +0,0 @@
-From 834448fc3493be56cc6a4f6b504569142f7f6070 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:45:45 +0530
-Subject: [PATCH 10/58] [Patch, microblaze]: Fix atomic boolean return value.
-
-In atomic_compare_and_swapsi, fix boolean return value.
-Previously, it contained zero if successful and non-zero
-if unsuccessful.
-
-Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/sync.md | 7 ++++---
- 1 file changed, 4 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/sync.md b/gcc/config/microblaze/sync.md
-index 24cd67e1fdb..76c3616c992 100644
---- a/gcc/config/microblaze/sync.md
-+++ b/gcc/config/microblaze/sync.md
-@@ -34,15 +34,16 @@
-    (clobber (match_scratch:SI 8 "=&d"))]
-   ""
-   {
--    output_asm_insn ("addc \tr0,r0,r0", operands);
-+    output_asm_insn ("add  \t%0,r0,r0", operands);
-     output_asm_insn ("lwx  \t%1,%y2,r0", operands);
-     output_asm_insn ("addic\t%8,r0,0", operands);
-     output_asm_insn ("bnei \t%8,.-8", operands);
--    output_asm_insn ("cmp  \t%0,%1,%3", operands);
--    output_asm_insn ("bnei \t%0,.+16", operands);
-+    output_asm_insn ("cmp  \t%8,%1,%3", operands);
-+    output_asm_insn ("bnei \t%8,.+20", operands);
-     output_asm_insn ("swx  \t%4,%y2,r0", operands);
-     output_asm_insn ("addic\t%8,r0,0", operands);
-     output_asm_insn ("bnei \t%8,.-28", operands);
-+    output_asm_insn ("addi \t%0,r0,1", operands);
-     return "";
-   }
- )
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
new file mode 100644
index 0000000000..22bf521d9e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
@@ -0,0 +1,33 @@
+From 8d9d1f457e1e270250d8a6700d4a1e1fa09465df Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:50:17 +0530
+Subject: [PATCH 10/54] [Patch, microblaze]: Fix the Microblaze crash with
+ msmall-divides flag Compiler is crashing when we use msmall-divides and
+ mxl-barrel-shift flag. This is because when use above flags
+ microblaze_expand_divide function will be called for division operation. In
+ microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't
+ have subreg register due to this compiler was crashing. Changed the logic to
+ avoid sub_reg call
+
+Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index a0f81b71391..0186171c04c 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3709,8 +3709,7 @@ microblaze_expand_divide (rtx operands[])
+   mem_rtx = gen_rtx_MEM (QImode,
+                             gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
+ 
+-  insn = emit_insn (gen_movqi (regqi, mem_rtx)); 
+-  insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
++  insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+   JUMP_LABEL (jump) = div_end_label;
+   LABEL_NUSES (div_end_label) = 1; 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
new file mode 100644
index 0000000000..cce812bbc6
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
@@ -0,0 +1,48 @@
+From 03429c91d1db134e1deda4c8e58bc0939d5fedf9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 16:52:56 +0530
+Subject: [PATCH 11/54] [Patch, microblaze]: Added ashrsi3_with_size_opt Added
+ ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os
+ optimization is used. lshrsi3_with_size_opt is being removed as it has
+ conflicts with unsigned int variables
+
+Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index eba2776ae56..187ad522dcc 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1508,6 +1508,27 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++(define_insn "*ashrsi3_with_size_opt"
++  [(set (match_operand:SI 0 "register_operand" "=&d")
++       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
++                   (match_operand:SI 2 "immediate_operand" "I")))]
++  "(INTVAL (operands[2]) > 5 && optimize_size)"
++  {
++    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("ori\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addik\t%3,%3,-1", operands);
++    output_asm_insn ("bneid\t%3,.-4", operands);
++    return "sra\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "SI")
++  (set_attr "length"  "20")]
++)
++
+ (define_insn "*ashrsi_inline"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
deleted file mode 100644
index e60e6f2fdf..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 19457459592123c41c3ce9e084e165525e4d7bb0 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:50:17 +0530
-Subject: [PATCH 11/58] [Patch, microblaze]: Fix the Microblaze crash with
- msmall-divides flag
-
-Compiler is crashing when we use msmall-divides and mxl-barrel-shift flag.
-This is because when use above flags microblaze_expand_divide function will be
-called for division operation. In microblaze_expand_divide function we are
-using sub_reg but MicroBlaze doesn't have subreg register due to this compiler
-was crashing. Changed the logic to avoid sub_reg call
-
-Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a0f81b71391..0186171c04c 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3709,8 +3709,7 @@ microblaze_expand_divide (rtx operands[])
-   mem_rtx = gen_rtx_MEM (QImode,
-                             gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
- 
--  insn = emit_insn (gen_movqi (regqi, mem_rtx)); 
--  insn = emit_insn (gen_movsi (operands[0], gen_rtx_SUBREG (SImode, regqi, 0)));
-+  insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
-   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-   JUMP_LABEL (jump) = div_end_label;
-   LABEL_NUSES (div_end_label) = 1; 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
deleted file mode 100644
index b9e39928db..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From 9da28a01ffb778fc5cb5df27332cef21f890a63f Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 16:52:56 +0530
-Subject: [PATCH 12/58] [Patch, microblaze]: Added ashrsi3_with_size_opt
-
-Added ashrsi3_with_size_opt pattern to optimize the sra instructions
-when the -Os optimization is used. lshrsi3_with_size_opt is
-being removed as it has conflicts with unsigned int variables
-
-Signed-off-by:Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.md | 21 +++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index eba2776ae56..187ad522dcc 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1508,6 +1508,27 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+(define_insn "*ashrsi3_with_size_opt"
-+  [(set (match_operand:SI 0 "register_operand" "=&d")
-+       (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-+                   (match_operand:SI 2 "immediate_operand" "I")))]
-+  "(INTVAL (operands[2]) > 5 && optimize_size)"
-+  {
-+    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("ori\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addik\t%3,%3,-1", operands);
-+    output_asm_insn ("bneid\t%3,.-4", operands);
-+    return "sra\t%0,%0";
-+  }
-+  [(set_attr "type"    "arith")
-+  (set_attr "mode"    "SI")
-+  (set_attr "length"  "20")]
-+)
-+
- (define_insn "*ashrsi_inline"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (ashiftrt:SI (match_operand:SI 1 "register_operand"  "d")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
new file mode 100644
index 0000000000..e393f0fe21
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch
@@ -0,0 +1,26 @@
+From 6803fbc540db39865037994daa122cf10c0eb33a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 10:57:19 +0530
+Subject: [PATCH 12/54] [Patch, microblaze]: Use bralid for profiler calls
+ Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index dc112f5301f..8aa3f155790 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -486,7 +486,7 @@ typedef struct microblaze_args
+ 
+ #define FUNCTION_PROFILER(FILE, LABELNO) { \
+   {                                        \
+-    fprintf (FILE, "\tbrki\tr16,_mcount\n");           \
++    fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n");         \
+   }                                                    \
+  }
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch
new file mode 100644
index 0000000000..b601c98a96
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Removed-moddi3-routinue.patch
@@ -0,0 +1,157 @@
+From 5de3888c460a341667150d569548b3309188e7e8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Jan 2017 17:36:16 +0530
+Subject: [PATCH 13/54] [Patch, microblaze]: Removed moddi3 routinue Using the
+ default moddi3 function as the existing implementation has many bugs
+
+Signed-off-by:Nagaraju <nmekala@xilix.com>
+---
+ libgcc/config/microblaze/moddi3.S     | 121 --------------------------
+ libgcc/config/microblaze/t-microblaze |   3 +-
+ 2 files changed, 1 insertion(+), 123 deletions(-)
+ delete mode 100644 libgcc/config/microblaze/moddi3.S
+
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+deleted file mode 100644
+index d0e24fdb89d..00000000000
+--- a/libgcc/config/microblaze/moddi3.S
++++ /dev/null
+@@ -1,121 +0,0 @@
+-###################################
+-# 
+-#  Copyright (C) 2009-2020 Free Software Foundation, Inc.
+-#
+-#  Contributed by Michael Eager <eager@eagercon.com>.
+-#
+-#  This file is free software; you can redistribute it and/or modify it
+-#  under the terms of the GNU General Public License as published by the
+-#  Free Software Foundation; either version 3, or (at your option) any
+-#  later version.
+-#
+-#  GCC is distributed in the hope that it will be useful, but WITHOUT
+-#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+-#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+-#  License for more details.
+-#
+-#  Under Section 7 of GPL version 3, you are granted additional
+-#  permissions described in the GCC Runtime Library Exception, version
+-#  3.1, as published by the Free Software Foundation.
+-#
+-#  You should have received a copy of the GNU General Public License and
+-#  a copy of the GCC Runtime Library Exception along with this program;
+-#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+-#  <http://www.gnu.org/licenses/>. 
+-#
+-#  modsi3.S
+-# 
+-#  modulo operation for 64 bit integers.
+-# 
+-#######################################
+-
+-
+-/* An executable stack is *not* required for these functions.  */
+-#ifdef __linux__
+-.section .note.GNU-stack,"",%progbits
+-.previous
+-#endif
+-
+-	.globl	__moddi3
+-	.ent	__moddi3
+-__moddi3:
+-	.frame	r1,0,r15	
+-
+-#Change the stack pointer value and Save callee saved regs
+-	addik	r1,r1,-24
+-	swi	r25,r1,0
+-	swi	r26,r1,4
+-	swi	r27,r1,8	# used for sign
+-	swi	r28,r1,12	# used for loop count
+-	swi	r29,r1,16	# Used for div value High
+-	swi	r30,r1,20	# Used for div value Low
+-
+-#Check for Zero Value in the divisor/dividend
+-	OR	r9,r5,r6			# Check for the op1 being zero
+-	BEQID	r9,$LaResult_Is_Zero		# Result is zero
+-	OR	r9,r7,r8			# Check for the dividend being zero
+-	BEQI	r9,$LaDiv_By_Zero	        # Div_by_Zero   # Division Error
+-	BGEId	r5,$La1_Pos 
+-	XOR	r27,r5,r7			# Get the sign of the result
+-	RSUBI	r6,r6,0				# Make dividend positive
+-	RSUBIC	r5,r5,0				# Make dividend positive
+-$La1_Pos:
+-	BGEI	r7,$La2_Pos
+-	RSUBI	r8,r8,0				# Make Divisor Positive
+-	RSUBIC	r9,r9,0				# Make Divisor Positive
+-$La2_Pos:
+-	ADDIK	r4,r0,0				# Clear mod low
+-	ADDIK	r3,r0,0                	        # Clear mod high
+-	ADDIK	r29,r0,0			# clear div high
+-	ADDIK	r30,r0,0			# clear div low
+-	ADDIK	r28,r0,64			# Initialize the loop count
+-   # First part try to find the first '1' in the r5/r6
+-$LaDIV1:
+-	ADD	r6,r6,r6
+-	ADDC	r5,r5,r5			# left shift logical r5
+-	BGEID	r5,$LaDIV1			
+-	ADDIK	r28,r28,-1
+-$LaDIV2:
+-	ADD	r6,r6,r6
+-	ADDC	r5,r5,r5	# left shift logical r5/r6 get the '1' into the Carry
+-	ADDC	r4,r4,r4	# Move that bit into the Mod register
+-	ADDC	r3,r3,r3	# Move carry into high mod register
+-	rsub	r18,r7,r3	# Compare the High Parts of Mod and Divisor
+-	bnei	r18,$L_High_EQ
+-	rsub	r18,r6,r4	# Compare Low Parts only if Mod[h] == Divisor[h]
+-$L_High_EQ:	
+-	rSUB	r26,r8,r4	# Subtract divisor[L] from Mod[L]
+-	rsubc	r25,r7,r3	# Subtract divisor[H] from Mod[H]
+-	BLTi	r25,$LaMOD_TOO_SMALL
+-	OR	r3,r0,r25	# move r25 to mod [h]
+-	OR	r4,r0,r26	# move r26 to mod [l]
+-	ADDI	r30,r30,1
+-	ADDC	r29,r29,r0
+-$LaMOD_TOO_SMALL:
+-	ADDIK	r28,r28,-1
+-	BEQi	r28,$LaLOOP_END
+-	ADD	r30,r30,r30		# Shift in the '1' into div [low]
+-	ADDC	r29,r29,r29		# Move the carry generated into high
+-	BRI	$LaDIV2   # Div2
+-$LaLOOP_END:
+-	BGEI	r27,$LaRETURN_HERE
+-	rsubi	r30,r30,0
+-	rsubc	r29,r29,r0
+-	BRI	$LaRETURN_HERE
+-$LaDiv_By_Zero:
+-$LaResult_Is_Zero:
+-	or	r29,r0,r0	# set result to 0 [High]
+-	or	r30,r0,r0	# set result to 0 [Low]
+-$LaRETURN_HERE:
+-# Restore values of CSRs and that of r29 and the divisor and the dividend
+-	
+-	lwi	r25,r1,0
+-	lwi	r26,r1,4
+-	lwi	r27,r1,8
+-	lwi	r28,r1,12
+-	lwi	r29,r1,16
+-	lwi	r30,r1,20
+-	rtsd	r15,8
+-	addik r1,r1,24
+-        .end __moddi3
+-	
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 96959f0292b..8d954a49575 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,8 +1,7 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
+-        $(srcdir)/config/microblaze/moddi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+         $(srcdir)/config/microblaze/muldi3_hard.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch
deleted file mode 100644
index 36af2652b7..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 07a5c8b22a1cef99b2d4570ea080c503260161e4 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 10:57:19 +0530
-Subject: [PATCH 13/58] [Patch, microblaze]: Use bralid for profiler calls
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- gcc/config/microblaze/microblaze.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index dc112f5301f..8aa3f155790 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -486,7 +486,7 @@ typedef struct microblaze_args
- 
- #define FUNCTION_PROFILER(FILE, LABELNO) { \
-   {                                        \
--    fprintf (FILE, "\tbrki\tr16,_mcount\n");           \
-+    fprintf (FILE, "\tbralid\tr15,_mcount\nnop\n");         \
-   }                                                    \
-  }
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
new file mode 100644
index 0000000000..3bd6efd556
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch
@@ -0,0 +1,101 @@
+From b9a9e8f9d0994c76819ec605a0b7cd113f3b2cf0 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 14:41:58 +0530
+Subject: [PATCH 14/54] [Patch, microblaze]: Add INIT_PRIORITY support Added
+ TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
+
+These macros allows users to control the order of initialization
+of objects defined at namespace scope with the init_priority
+attribute by specifying a relative priority, a constant integral
+expression currently bounded between 101 and 65535 inclusive.
+
+Lower numbers indicate a higher priority.
+
+Changelog
+
+2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
+   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
+   TARGET_ASM_DESTRUCTOR.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 0186171c04c..9eae5515c60 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2634,6 +2634,53 @@ print_operand_address (FILE * file, rtx addr)
+     }
+ }
+ 
++/* Output an element in the table of global constructors. */
++void
++microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
++{
++    const char *section = ".ctors";
++    char buf[16];
++
++    if (priority != DEFAULT_INIT_PRIORITY)
++      {
++        sprintf (buf, ".ctors.%.5u",
++                /* Invert the numbering so the linker puts us in the proper
++                   order; constructors are run from right to left, and the
++                   linker sorts in increasing order.  */
++                MAX_INIT_PRIORITY - priority);
++        section = buf;
++      }
++
++    switch_to_section (get_section (section, 0, NULL));
++    assemble_align (POINTER_SIZE);
++    fputs ("\t.word\t", asm_out_file);
++    output_addr_const (asm_out_file, symbol);
++    fputs ("\n", asm_out_file);
++}
++
++/* Output an element in the table of global destructors. */
++void
++microblaze_asm_destructor (rtx symbol, int priority)
++{
++    const char *section = ".dtors";
++    char buf[16];
++    if (priority != DEFAULT_INIT_PRIORITY)
++      {
++        sprintf (buf, ".dtors.%.5u",
++                 /* Invert the numbering so the linker puts us in the proper
++                    order; constructors are run from right to left, and the
++                    linker sorts in increasing order.  */
++                MAX_INIT_PRIORITY - priority);
++        section = buf;
++      }
++
++    switch_to_section (get_section (section, 0, NULL));
++    assemble_align (POINTER_SIZE);
++    fputs ("\t.word\t", asm_out_file);
++    output_addr_const (asm_out_file, symbol);
++    fputs ("\n", asm_out_file);
++}
++
+ /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
+    is used, so that we don't emit an .extern for it in 
+    microblaze_asm_file_end.  */
+@@ -3975,6 +4022,12 @@ microblaze_starting_frame_offset (void)
+ #undef TARGET_ATTRIBUTE_TABLE
+ #define TARGET_ATTRIBUTE_TABLE          microblaze_attribute_table
+ 
++#undef TARGET_ASM_CONSTRUCTOR
++#define TARGET_ASM_CONSTRUCTOR          microblaze_asm_constructor
++
++#undef TARGET_ASM_DESTRUCTOR
++#define TARGET_ASM_DESTRUCTOR           microblaze_asm_destructor
++
+ #undef TARGET_IN_SMALL_DATA_P
+ #define TARGET_IN_SMALL_DATA_P          microblaze_elf_in_small_data_p
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch
deleted file mode 100644
index 51563ecb93..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0014-Patch-microblaze-Disable-fivopts-by-default.patch
+++ /dev/null
@@ -1,43 +0,0 @@
-From 616f16089f0b01ab02008d7291df0972a99782e0 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 11:10:21 +0530
-Subject: [PATCH 14/58] [Patch, microblaze]: Disable fivopts by default
-
-Turn off ivopts by default. Interferes with cse.
-
-Changelog
-
-2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-
- * gcc/common/config/microblaze/microblaze-common.c
-   (microblaze_option_optimization_table): Disable fivopts by default.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/common/config/microblaze/microblaze-common.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 4391f939626..0b9d5a1b453 100644
---- a/gcc/common/config/microblaze/microblaze-common.c
-+++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -24,6 +24,15 @@
- #include "common/common-target.h"
- #include "common/common-target-def.h"
- 
-+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
-+static const struct default_options microblaze_option_optimization_table[] =
-+  {
-+    /* Turn off ivopts by default. It messes up cse. */
-+    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
-+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-+    { OPT_LEVELS_NONE, 0, NULL, 0 }
-+  };
-+
- #undef TARGET_DEFAULT_TARGET_FLAGS
- #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
new file mode 100644
index 0000000000..ba20cf0784
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Add-optimized-lshrsi3.patch
@@ -0,0 +1,81 @@
+From f448485f5e0507a7ab8be7f83c08f807200a3501 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 15:23:57 +0530
+Subject: [PATCH 15/54] [Patch, microblaze]: Add optimized lshrsi3 When barrel
+ shifter is not present, the immediate value is greater than #5 and
+ optimization is -OS, the compiler will generate shift operation using loop.
+
+Changelog
+
+2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
+
+ChangeLog/testsuite
+
+2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>
+
+ * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
+
+Signed-off-by:Nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.md           | 21 +++++++++++++++++++
+ .../microblaze/others/lshrsi_Os_1.c           | 13 ++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 187ad522dcc..8f9baec826b 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1618,6 +1618,27 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++(define_insn "*lshrsi3_with_size_opt"
++  [(set (match_operand:SI 0 "register_operand" "=&d")
++       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
++                   (match_operand:SI 2 "immediate_operand" "I")))]
++  "(INTVAL (operands[2]) > 5 && optimize_size)"
++  {
++    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("ori\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addik\t%3,%3,-1", operands);
++    output_asm_insn ("bneid\t%3,.-4", operands);
++    return "srl\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "SI")
++  (set_attr "length"  "20")]
++)
++
+ (define_insn "*lshrsi_inline"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+new file mode 100644
+index 00000000000..32a3be7c76a
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
+@@ -0,0 +1,13 @@
++/* { dg-options "-Os -mno-xl-barrel-shift" } */
++
++void testfunc(void)
++{
++    unsigned volatile int z = 8192;
++    z >>= 8;
++}
++/* { dg-final { scan-assembler-not "\bsrli" } } */
++/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
++/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
++/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
++/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
++/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch
deleted file mode 100644
index e7fb93930a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0015-Patch-microblaze-Removed-moddi3-routinue.patch
+++ /dev/null
@@ -1,161 +0,0 @@
-From c2a6652176751bc95e2f990179e90cfe58026feb Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Thu, 12 Jan 2017 17:36:16 +0530
-Subject: [PATCH 15/58] [Patch, microblaze]: Removed moddi3 routinue
-
-Using the default moddi3 function as the existing implementation has many bugs
-
-Signed-off-by:Nagaraju <nmekala@xilix.com>
-
-Conflicts:
-	libgcc/config/microblaze/moddi3.S
----
- libgcc/config/microblaze/moddi3.S     | 121 --------------------------
- libgcc/config/microblaze/t-microblaze |   3 +-
- 2 files changed, 1 insertion(+), 123 deletions(-)
- delete mode 100644 libgcc/config/microblaze/moddi3.S
-
-diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
-deleted file mode 100644
-index d0e24fdb89d..00000000000
---- a/libgcc/config/microblaze/moddi3.S
-+++ /dev/null
-@@ -1,121 +0,0 @@
--###################################
--# 
--#  Copyright (C) 2009-2020 Free Software Foundation, Inc.
--#
--#  Contributed by Michael Eager <eager@eagercon.com>.
--#
--#  This file is free software; you can redistribute it and/or modify it
--#  under the terms of the GNU General Public License as published by the
--#  Free Software Foundation; either version 3, or (at your option) any
--#  later version.
--#
--#  GCC is distributed in the hope that it will be useful, but WITHOUT
--#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
--#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
--#  License for more details.
--#
--#  Under Section 7 of GPL version 3, you are granted additional
--#  permissions described in the GCC Runtime Library Exception, version
--#  3.1, as published by the Free Software Foundation.
--#
--#  You should have received a copy of the GNU General Public License and
--#  a copy of the GCC Runtime Library Exception along with this program;
--#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
--#  <http://www.gnu.org/licenses/>. 
--#
--#  modsi3.S
--# 
--#  modulo operation for 64 bit integers.
--# 
--#######################################
--
--
--/* An executable stack is *not* required for these functions.  */
--#ifdef __linux__
--.section .note.GNU-stack,"",%progbits
--.previous
--#endif
--
--	.globl	__moddi3
--	.ent	__moddi3
--__moddi3:
--	.frame	r1,0,r15	
--
--#Change the stack pointer value and Save callee saved regs
--	addik	r1,r1,-24
--	swi	r25,r1,0
--	swi	r26,r1,4
--	swi	r27,r1,8	# used for sign
--	swi	r28,r1,12	# used for loop count
--	swi	r29,r1,16	# Used for div value High
--	swi	r30,r1,20	# Used for div value Low
--
--#Check for Zero Value in the divisor/dividend
--	OR	r9,r5,r6			# Check for the op1 being zero
--	BEQID	r9,$LaResult_Is_Zero		# Result is zero
--	OR	r9,r7,r8			# Check for the dividend being zero
--	BEQI	r9,$LaDiv_By_Zero	        # Div_by_Zero   # Division Error
--	BGEId	r5,$La1_Pos 
--	XOR	r27,r5,r7			# Get the sign of the result
--	RSUBI	r6,r6,0				# Make dividend positive
--	RSUBIC	r5,r5,0				# Make dividend positive
--$La1_Pos:
--	BGEI	r7,$La2_Pos
--	RSUBI	r8,r8,0				# Make Divisor Positive
--	RSUBIC	r9,r9,0				# Make Divisor Positive
--$La2_Pos:
--	ADDIK	r4,r0,0				# Clear mod low
--	ADDIK	r3,r0,0                	        # Clear mod high
--	ADDIK	r29,r0,0			# clear div high
--	ADDIK	r30,r0,0			# clear div low
--	ADDIK	r28,r0,64			# Initialize the loop count
--   # First part try to find the first '1' in the r5/r6
--$LaDIV1:
--	ADD	r6,r6,r6
--	ADDC	r5,r5,r5			# left shift logical r5
--	BGEID	r5,$LaDIV1			
--	ADDIK	r28,r28,-1
--$LaDIV2:
--	ADD	r6,r6,r6
--	ADDC	r5,r5,r5	# left shift logical r5/r6 get the '1' into the Carry
--	ADDC	r4,r4,r4	# Move that bit into the Mod register
--	ADDC	r3,r3,r3	# Move carry into high mod register
--	rsub	r18,r7,r3	# Compare the High Parts of Mod and Divisor
--	bnei	r18,$L_High_EQ
--	rsub	r18,r6,r4	# Compare Low Parts only if Mod[h] == Divisor[h]
--$L_High_EQ:	
--	rSUB	r26,r8,r4	# Subtract divisor[L] from Mod[L]
--	rsubc	r25,r7,r3	# Subtract divisor[H] from Mod[H]
--	BLTi	r25,$LaMOD_TOO_SMALL
--	OR	r3,r0,r25	# move r25 to mod [h]
--	OR	r4,r0,r26	# move r26 to mod [l]
--	ADDI	r30,r30,1
--	ADDC	r29,r29,r0
--$LaMOD_TOO_SMALL:
--	ADDIK	r28,r28,-1
--	BEQi	r28,$LaLOOP_END
--	ADD	r30,r30,r30		# Shift in the '1' into div [low]
--	ADDC	r29,r29,r29		# Move the carry generated into high
--	BRI	$LaDIV2   # Div2
--$LaLOOP_END:
--	BGEI	r27,$LaRETURN_HERE
--	rsubi	r30,r30,0
--	rsubc	r29,r29,r0
--	BRI	$LaRETURN_HERE
--$LaDiv_By_Zero:
--$LaResult_Is_Zero:
--	or	r29,r0,r0	# set result to 0 [High]
--	or	r30,r0,r0	# set result to 0 [Low]
--$LaRETURN_HERE:
--# Restore values of CSRs and that of r29 and the divisor and the dividend
--	
--	lwi	r25,r1,0
--	lwi	r26,r1,4
--	lwi	r27,r1,8
--	lwi	r28,r1,12
--	lwi	r29,r1,16
--	lwi	r30,r1,20
--	rtsd	r15,8
--	addik r1,r1,24
--        .end __moddi3
--	
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 96959f0292b..8d954a49575 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,8 +1,7 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _moddi3 _mulsi3 _udivsi3 _umodsi3
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
--        $(srcdir)/config/microblaze/moddi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
-         $(srcdir)/config/microblaze/muldi3_hard.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch
deleted file mode 100644
index 13c3ccd95d..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch
+++ /dev/null
@@ -1,102 +0,0 @@
-From 9a4253a92a5e1811693ea1707b5fc272908ec556 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 14:41:58 +0530
-Subject: [PATCH 16/58] [Patch, microblaze]: Add INIT_PRIORITY support
-
-Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.
-
-These macros allows users to control the order of initialization
-of objects defined at namespace scope with the init_priority
-attribute by specifying a relative priority, a constant integral
-expression currently bounded between 101 and 65535 inclusive.
-
-Lower numbers indicate a higher priority.
-
-Changelog
-
-2013-11-26  Nagaraju Mekala <nagaraju.mekala@xilinx.com>
-
- * gcc/config/microblaze/microblaze.c: Add microblaze_asm_constructor,
-   microblaze_asm_destructor. Define TARGET_ASM_CONSTRUCTOR and
-   TARGET_ASM_DESTRUCTOR.
-
-Signed-off-by:nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.c | 53 ++++++++++++++++++++++++++++++
- 1 file changed, 53 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0186171c04c..9eae5515c60 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2634,6 +2634,53 @@ print_operand_address (FILE * file, rtx addr)
-     }
- }
- 
-+/* Output an element in the table of global constructors. */
-+void
-+microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
-+{
-+    const char *section = ".ctors";
-+    char buf[16];
-+
-+    if (priority != DEFAULT_INIT_PRIORITY)
-+      {
-+        sprintf (buf, ".ctors.%.5u",
-+                /* Invert the numbering so the linker puts us in the proper
-+                   order; constructors are run from right to left, and the
-+                   linker sorts in increasing order.  */
-+                MAX_INIT_PRIORITY - priority);
-+        section = buf;
-+      }
-+
-+    switch_to_section (get_section (section, 0, NULL));
-+    assemble_align (POINTER_SIZE);
-+    fputs ("\t.word\t", asm_out_file);
-+    output_addr_const (asm_out_file, symbol);
-+    fputs ("\n", asm_out_file);
-+}
-+
-+/* Output an element in the table of global destructors. */
-+void
-+microblaze_asm_destructor (rtx symbol, int priority)
-+{
-+    const char *section = ".dtors";
-+    char buf[16];
-+    if (priority != DEFAULT_INIT_PRIORITY)
-+      {
-+        sprintf (buf, ".dtors.%.5u",
-+                 /* Invert the numbering so the linker puts us in the proper
-+                    order; constructors are run from right to left, and the
-+                    linker sorts in increasing order.  */
-+                MAX_INIT_PRIORITY - priority);
-+        section = buf;
-+      }
-+
-+    switch_to_section (get_section (section, 0, NULL));
-+    assemble_align (POINTER_SIZE);
-+    fputs ("\t.word\t", asm_out_file);
-+    output_addr_const (asm_out_file, symbol);
-+    fputs ("\n", asm_out_file);
-+}
-+
- /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
-    is used, so that we don't emit an .extern for it in 
-    microblaze_asm_file_end.  */
-@@ -3975,6 +4022,12 @@ microblaze_starting_frame_offset (void)
- #undef TARGET_ATTRIBUTE_TABLE
- #define TARGET_ATTRIBUTE_TABLE          microblaze_attribute_table
- 
-+#undef TARGET_ASM_CONSTRUCTOR
-+#define TARGET_ASM_CONSTRUCTOR          microblaze_asm_constructor
-+
-+#undef TARGET_ASM_DESTRUCTOR
-+#define TARGET_ASM_DESTRUCTOR           microblaze_asm_destructor
-+
- #undef TARGET_IN_SMALL_DATA_P
- #define TARGET_IN_SMALL_DATA_P          microblaze_elf_in_small_data_p
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
new file mode 100644
index 0000000000..0c86522479
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0016-Patch-microblaze-Add-cbranchsi4_reg.patch
@@ -0,0 +1,147 @@
+From 386b8dcef2d774e9138515814be0fd579ade5af5 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 17:04:37 +0530
+Subject: [PATCH 16/54] [Patch, microblaze]: Add cbranchsi4_reg This patch
+ optimizes the generation of  pcmpne/pcmpeq instruction if the compare
+ instruction has no immediate values.For the immediate values the xor
+ instruction is generated
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
+Signed-off-by: Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2015-01-13 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+  *microblaze.md (cbranchsi4_reg): New
+  *microblaze.c (microblaze_expand_conditional_branch_reg): New
+
+Conflicts:
+
+	gcc/config/microblaze/microblaze-protos.h
+---
+ gcc/config/microblaze/microblaze-protos.h         |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c   |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c   |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c   |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c   |  2 +-
+ gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c  | 14 +++++++-------
+ gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------
+ 7 files changed, 18 insertions(+), 18 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index 982b2abd2d4..c2f88813a8d 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
+ extern bool microblaze_expand_move (machine_mode, rtx *);
+ extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
+ extern void microblaze_expand_divide (rtx *);
+-extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
++extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_sf (rtx *); 
+ extern int microblaze_can_use_return_insn (void);
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
+index 4041a241391..ccc6a461cd9 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 <= f3) 
+-        print ("le");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
+index 3902b839db9..1dd5fe6c539 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 < f3) 
+-        print ("lt");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
+index 8555974dda5..d6f80fb0ec3 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
+@@ -6,5 +6,5 @@ void float_func ()
+ {
+   /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if (f2 == f3) 
+-        print ("eq");
++        f1 = f2 + f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
+index 79cc5f9dd8e..d1177249552 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
+@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
+   /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+   /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
+     if(f1==f2 && f1<=f3)
+-        print ("f1 eq f2 && f1 le f3");
++        f2 = f3;
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
+index ebfb170ecee..75822977ef8 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
+@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
+ void float_func () 
+ {
+     /* { dg-final { scan-assembler-not "fcmp" } } */
+-    if (f2 <= f3) 
+-        print ("le");
++    if (f2 <= f3)
++        f1 = f3;
+     else if (f2 == f3) 
+-        print ("eq");
++        f1 = f3;
+     else if (f2 < f3) 
+-        print ("lt");
++        f1 = f3;
+     else if (f2 > f3) 
+-        print ("gt");
++        f1 = f3;
+     else if (f2 >= f3) 
+-        print ("ge");
++        f1 = f3;
+     else if (f2 != f3) 
+-        print ("ne");
++        f1 = f3;
+     
+ }
+diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
+index 1d6ba807b12..532c035adfd 100644
+--- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
++++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
+@@ -74,16 +74,16 @@ void float_cmp_func ()
+ {
+     /* { dg-final { scan-assembler-not "fcmp" } } */
+     if (f2 <= f3) 
+-        print ("le");
++        f1 = f3;
+     else if (f2 == f3) 
+-        print ("eq");
++        f1 = f3;
+     else if (f2 < f3) 
+-        print ("lt");
++        f1 = f3;
+     else if (f2 > f3) 
+-        print ("gt");
++        f1 = f3;
+     else if (f2 >= f3) 
+-        print ("ge");
++        f1 = f3;
+     else if (f2 != f3) 
+-        print ("ne");
++        f1 = f3;
+     
+ }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch
deleted file mode 100644
index cfc06f7471..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Add-optimized-lshrsi3.patch
+++ /dev/null
@@ -1,83 +0,0 @@
-From 27c27a8876152bac78059a1b2d5a6f0ac9b8cee2 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 15:23:57 +0530
-Subject: [PATCH 17/58] [Patch, microblaze]: Add optimized lshrsi3
-
-When barrel shifter is not present, the immediate value
-is greater than #5 and optimization is -OS, the
-compiler will generate shift operation using loop.
-
-Changelog
-
-2013-11-26  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn
-
-ChangeLog/testsuite
-
-2014-02-12  David Holsgrove <david.holsgrove@xilinx.com>
-
- * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test.
-
-Signed-off-by:Nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gcc/config/microblaze/microblaze.md           | 21 +++++++++++++++++++
- .../microblaze/others/lshrsi_Os_1.c           | 13 ++++++++++++
- 2 files changed, 34 insertions(+)
- create mode 100644 gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 187ad522dcc..8f9baec826b 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1618,6 +1618,27 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+(define_insn "*lshrsi3_with_size_opt"
-+  [(set (match_operand:SI 0 "register_operand" "=&d")
-+       (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-+                   (match_operand:SI 2 "immediate_operand" "I")))]
-+  "(INTVAL (operands[2]) > 5 && optimize_size)"
-+  {
-+    operands[3] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("ori\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addik\t%3,%3,-1", operands);
-+    output_asm_insn ("bneid\t%3,.-4", operands);
-+    return "srl\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"    "SI")
-+  (set_attr "length"  "20")]
-+)
-+
- (define_insn "*lshrsi_inline"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (lshiftrt:SI (match_operand:SI 1 "register_operand"  "d")
-diff --git a/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-new file mode 100644
-index 00000000000..32a3be7c76a
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c
-@@ -0,0 +1,13 @@
-+/* { dg-options "-Os -mno-xl-barrel-shift" } */
-+
-+void testfunc(void)
-+{
-+    unsigned volatile int z = 8192;
-+    z >>= 8;
-+}
-+/* { dg-final { scan-assembler-not "\bsrli" } } */
-+/* { dg-final { scan-assembler "\ori\tr18,r0" } } */
-+/* { dg-final { scan-assembler "addk\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0" } } */
-+/* { dg-final { scan-assembler "addik\tr18,r18,-1" } } */
-+/* { dg-final { scan-assembler "bneid\tr18,.-4" } } */
-+/* { dg-final { scan-assembler "\srl\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])" } } */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
new file mode 100644
index 0000000000..504083f3e1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
@@ -0,0 +1,58 @@
+From b6298861681965533c9b6dac5e26fbd62b52839d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 17:11:04 +0530
+Subject: [PATCH 17/54] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
+ The changes are made in the patch for the inline expansion of the fsqrt
+ builtin with fqrt instruction. The sqrt math function takes double as
+ argument and return double as argument. The pattern is selected while
+ expanding the unary op through expand_unop which passes DFmode and the DFmode
+ pattern was not there returning zero. Thus the sqrt math function is not
+ inlined and expanded. The pattern with DFmode argument is added. Also the
+ source and destination argument is not same the DF through two different
+ consecutive registers with lower 32 bit is the argument passed to sqrt and
+ the higher 32 bit is zero. If the source and destinations are different the
+ DFmode 64 bits registers is not set properly giving the problem in runtime.
+ Such changes are taken care in the implementation of the pattern for DFmode
+ for inline expansion of the sqrt.
+
+ChangeLog:
+2015-06-16  Ajit Agarwal  <ajitkum@xilinx.com>
+            Nagaraju Mekala <nmekala@xilinx.com>
+
+	* config/microblaze/microblaze.md (sqrtdf2): New
+	pattern.
+
+Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
+              Nagaraju Mekala nmekala@xilinx.com
+---
+ gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8f9baec826b..986d9c3aa25 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -451,6 +451,20 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "sqrtdf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
++  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
++  {
++    if (REGNO (operands[0]) == REGNO (operands[1]))
++      return "fsqrt\t%0,%1";
++    else
++      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
++  }
++  [(set_attr "type"     "fsqrt")
++   (set_attr "mode"      "SF")
++   (set_attr "length"    "4")])
++
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
new file mode 100644
index 0000000000..14095d8332
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
@@ -0,0 +1,63 @@
+From a8c6c13cc322ecc300bb2cdf22e3d6f1680e56be Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 18:07:24 +0530
+Subject: [PATCH 18/54] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
+ insn definitions Change adddi3 to handle DI immediates as the second operand,
+ this requires modification to the output template however reduces the need to
+ specify seperate templates for 16-bit positive/negative immediate operands.
+ The use of 32-bit immediates for the addi and addic instructions is handled
+ by the assembler, which will emit the imm instructions when required. This
+ conveniently handles the optimizable cases where the immediate constant value
+ does not need the higher half words of the operands upper/lower words.
+
+Change the constraints of the subdi3 instruction definition such that it
+does not match the second operand as an immediate value. This is because
+there is no definition to handle this case nor is it possible to
+implement purely with instructions as microblaze does not provide an
+instruction to perform a forward arithmetic subtraction (it only
+provides reverse 'rD = IMM - rA').
+
+Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
+---
+ gcc/config/microblaze/microblaze.md | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 986d9c3aa25..efd2c34e0b7 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -502,17 +502,16 @@
+ ;; Adding 2 DI operands in register or reg/imm
+ 
+ (define_insn "adddi3"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+-	(plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
+-		 (match_operand:DI 2 "arith_operand32" "d,P,N")))]
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
++		 (match_operand:DI 2 "arith_operand" "d,i")))]
+   ""
+   "@
+   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+-  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
+-  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
++  addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+   [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+-  (set_attr "length"	"8,8,12")])
++  (set_attr "length"	"8,8")])
+ 
+ ;;----------------------------------------------------------------
+ ;; Subtraction
+@@ -549,7 +548,7 @@
+ (define_insn "subdi3"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+-		  (match_operand:DI 2 "arith_operand32" "d")))]
++		  (match_operand:DI 2 "register_operand" "d")))]
+   ""
+   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+   [(set_attr "type"	"darith")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
deleted file mode 100644
index 1f8decc77a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 59273a71f1f180456d87eb4a1a5f95fcc6d17003 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 16:42:44 +0530
-Subject: [PATCH 18/58] [Patch, microblaze]: Reducing Stack space for arguments
-
-Currently in Microblaze target stack space for arguments in register is being
-allocated even if there are no arguments in the function.
-This patch will optimize the extra 24 bytes that are being allocated.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-              :Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2015-04-17 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-    *microblaze.c (microblaze_parm_needs_stack, microblaze_function_parms_need_stack): New
-    *microblaze.c (REG_PARM_STACK_SPACE): Modify
----
- gcc/config/microblaze/microblaze-protos.h |   1 +
- gcc/config/microblaze/microblaze.c        | 132 +++++++++++++++++++++-
- gcc/config/microblaze/microblaze.h        |   4 +-
- 3 files changed, 134 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 982b2abd2d4..96f7bb67f6c 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -59,6 +59,7 @@ extern int symbol_mentioned_p (rtx);
- extern int label_mentioned_p (rtx);
- extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
- extern void microblaze_eh_return (rtx op0);
-+int  microblaze_reg_parm_stack_space(tree fun);
- #endif  /* RTX_CODE */
- 
- /* Declare functions in microblaze-c.c.  */
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 9eae5515c60..a4bdf66f045 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2057,6 +2057,136 @@ microblaze_must_save_register (int regno)
-   return 0;
- }
- 
-+static bool
-+microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
-+{
-+  int unsignedp;
-+  rtx entry_parm;
-+
-+  /* Catch errors.  */
-+  if (type == NULL || type == error_mark_node)
-+    return true;
-+
-+  if (TREE_CODE (type) == POINTER_TYPE)
-+    return true;
-+
-+  /* Handle types with no storage requirement.  */
-+  if (TYPE_MODE (type) == VOIDmode)
-+    return false;
-+
-+   /* Handle complex types.  */
-+  if (TREE_CODE (type) == COMPLEX_TYPE)
-+    return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
-+             || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
-+
-+  /* Handle transparent aggregates.  */
-+  if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
-+     && TYPE_TRANSPARENT_AGGR (type))
-+  type = TREE_TYPE (first_field (type));
-+
-+  /* See if this arg was passed by invisible reference.  */
-+  function_arg_info arg (type, /*named=*/true);
-+  apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
-+
-+  /* Find mode as it is passed by the ABI.  */
-+  unsignedp = TYPE_UNSIGNED (type);
-+  arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
-+
-+  /* If there is no incoming register, we need a stack.  */
-+  entry_parm = microblaze_function_arg (args_so_far, arg);
-+  if (entry_parm == NULL)
-+    return true;
-+
-+  /* Likewise if we need to pass both in registers and on the stack.  */
-+  if (GET_CODE (entry_parm) == PARALLEL
-+     && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
-+   return true;
-+
-+  /* Also true if we're partially in registers and partially not.  */
-+  if (function_arg_partial_bytes (args_so_far, arg) != 0)
-+     return true;
-+
-+  /* Update info on where next arg arrives in registers.  */
-+  microblaze_function_arg_advance (args_so_far, arg);
-+  return false;
-+}
-+
-+static bool
-+microblaze_function_parms_need_stack (tree fun, bool incoming)
-+{
-+  tree fntype, result;
-+  CUMULATIVE_ARGS args_so_far_v;
-+  cumulative_args_t args_so_far;
-+  int num_of_args = 0;
-+
-+  /* Must be a libcall, all of which only use reg parms.  */
-+  if (!fun)
-+    return true;
-+
-+  fntype = fun;
-+  if (!TYPE_P (fun))
-+    fntype = TREE_TYPE (fun);
-+
-+  /* Varargs functions need the parameter save area.  */
-+  if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
-+    return true;
-+
-+  INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
-+  args_so_far = pack_cumulative_args (&args_so_far_v);
-+
-+  /* When incoming, we will have been passed the function decl.
-+   *      It is necessary to use the decl to handle K&R style functions,
-+   *      where TYPE_ARG_TYPES may not be available.  */
-+  if (incoming)
-+    {
-+      gcc_assert (DECL_P (fun));
-+      result = DECL_RESULT (fun);
-+    }
-+  else
-+    result = TREE_TYPE (fntype);
-+
-+  if (result && aggregate_value_p (result, fntype))
-+    {
-+      if (!TYPE_P (result))
-+        result = build_pointer_type (result);
-+        microblaze_parm_needs_stack (args_so_far, result);
-+    }
-+
-+  if (incoming)
-+    {
-+      tree parm;
-+      for (parm = DECL_ARGUMENTS (fun);
-+           parm && parm != void_list_node;
-+           parm = TREE_CHAIN (parm))
-+         if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
-+           return true;
-+    }
-+  else
-+    {
-+      function_args_iterator args_iter;
-+      tree arg_type;
-+
-+      FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
-+      {
-+        num_of_args++;
-+        if (microblaze_parm_needs_stack (args_so_far, arg_type))
-+         return true;
-+      }
-+    }
-+
-+  if (num_of_args > 3) return true;
-+
-+  return false;
-+}
-+
-+int  microblaze_reg_parm_stack_space(tree fun)
-+{
-+  if (microblaze_function_parms_need_stack (fun,false))
-+    return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
-+  else
-+    return 0;
-+}
-+
- /* Return the bytes needed to compute the frame pointer from the current
-    stack pointer.
- 
-@@ -3403,7 +3533,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-   emit_insn (gen_indirect_jump (temp2));
- 
-   /* Run just enough of rest_of_compilation.  This sequence was
--     "borrowed" from rs6000.c.  */
-+     "borrowed" from microblaze.c.  */
-   insn = get_insns ();
-   shorten_branches (insn);
-   assemble_start_function (thunk_fndecl, fnname);
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8aa3f155790..1e155e4041c 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -434,9 +434,9 @@ extern struct microblaze_frame_info current_frame_info;
- 
- #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
- 
--#define REG_PARM_STACK_SPACE(FNDECL)  		(MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
-+#define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
- 
--#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)	1
-+#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
- 
- #define STACK_BOUNDARY				32
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch
deleted file mode 100644
index b78a981440..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Add-cbranchsi4_reg.patch
+++ /dev/null
@@ -1,148 +0,0 @@
-From f43cb8572131074c7ce43a1d39c7ba6c85611e18 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:04:37 +0530
-Subject: [PATCH 19/58] [Patch, microblaze]: Add cbranchsi4_reg
-
-This patch optimizes the generation of  pcmpne/pcmpeq instruction if the
-compare instruction has no immediate values.For the immediate values the
-xor instruction is generated
-
-Signed-off-by: Nagaraju Mekala <nmekala@xilix.com>
-Signed-off-by: Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2015-01-13 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-  *microblaze.md (cbranchsi4_reg): New
-  *microblaze.c (microblaze_expand_conditional_branch_reg): New
-
-Conflicts:
-
-	gcc/config/microblaze/microblaze-protos.h
----
- gcc/config/microblaze/microblaze-protos.h         |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c   |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c   |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c   |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c   |  2 +-
- gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c  | 14 +++++++-------
- gcc/testsuite/gcc.target/microblaze/isa/vanilla.c | 12 ++++++------
- 7 files changed, 18 insertions(+), 18 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 96f7bb67f6c..76ffc682df2 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -33,7 +33,7 @@ extern int microblaze_expand_shift (rtx *);
- extern bool microblaze_expand_move (machine_mode, rtx *);
- extern bool microblaze_expand_block_move (rtx, rtx, rtx, rtx);
- extern void microblaze_expand_divide (rtx *);
--extern void microblaze_expand_conditional_branch (machine_mode, rtx *);
-+extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_sf (rtx *); 
- extern int microblaze_can_use_return_insn (void);
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-index 4041a241391..ccc6a461cd9 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp1.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(le|gt)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 <= f3) 
--        print ("le");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-index 3902b839db9..1dd5fe6c539 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp2.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(lt|ge)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 < f3) 
--        print ("lt");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-index 8555974dda5..d6f80fb0ec3 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp3.c
-@@ -6,5 +6,5 @@ void float_func ()
- {
-   /* { dg-final { scan-assembler "fcmp\.(eq|ne)\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if (f2 == f3) 
--        print ("eq");
-+        f1 = f2 + f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-index 79cc5f9dd8e..d1177249552 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c
-@@ -5,5 +5,5 @@ void float_func(float f1, float f2, float f3)
-   /* { dg-final { scan-assembler "fcmp\.eq\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-   /* { dg-final { scan-assembler "fcmp\.le\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r(\[0-9]\|\[1-2]\[0-9]\|3\[0-1])\[^0-9]" } } */
-     if(f1==f2 && f1<=f3)
--        print ("f1 eq f2 && f1 le f3");
-+        f2 = f3;
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-index ebfb170ecee..75822977ef8 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/nofcmp.c
-@@ -5,17 +5,17 @@ volatile float f1, f2, f3;
- void float_func () 
- {
-     /* { dg-final { scan-assembler-not "fcmp" } } */
--    if (f2 <= f3) 
--        print ("le");
-+    if (f2 <= f3)
-+        f1 = f3;
-     else if (f2 == f3) 
--        print ("eq");
-+        f1 = f3;
-     else if (f2 < f3) 
--        print ("lt");
-+        f1 = f3;
-     else if (f2 > f3) 
--        print ("gt");
-+        f1 = f3;
-     else if (f2 >= f3) 
--        print ("ge");
-+        f1 = f3;
-     else if (f2 != f3) 
--        print ("ne");
-+        f1 = f3;
-     
- }
-diff --git a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-index 1d6ba807b12..532c035adfd 100644
---- a/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-+++ b/gcc/testsuite/gcc.target/microblaze/isa/vanilla.c
-@@ -74,16 +74,16 @@ void float_cmp_func ()
- {
-     /* { dg-final { scan-assembler-not "fcmp" } } */
-     if (f2 <= f3) 
--        print ("le");
-+        f1 = f3;
-     else if (f2 == f3) 
--        print ("eq");
-+        f1 = f3;
-     else if (f2 < f3) 
--        print ("lt");
-+        f1 = f3;
-     else if (f2 > f3) 
--        print ("gt");
-+        f1 = f3;
-     else if (f2 >= f3) 
--        print ("ge");
-+        f1 = f3;
-     else if (f2 != f3) 
--        print ("ne");
-+        f1 = f3;
-     
- }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
new file mode 100644
index 0000000000..4a49011993
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
@@ -0,0 +1,72 @@
+From 3a9ee185eb462f880ceb4ddd125d4a98e0759873 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 17 Jan 2017 18:18:41 +0530
+Subject: [PATCH 19/54] [Patch, microblaze]: Update ashlsi3 & movsf patterns
+ This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand
+ of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal
+ patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our
+ instruction doesn't support so using gen_int_mode function
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+              :Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2016-01-07 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+  *microblaze.md (ashlsi3_with_mul_nodelay,
+                  ashlsi3_with_mul_delay,
+                  movsf_internal):
+    Updated the patterns to use gen_int_mode function
+  *microblaze.c (print_operand):
+     updated the 'F' case to use "unsinged int" instead
+     of HOST_WIDE_INT_PRINT_HEX
+---
+ gcc/config/microblaze/microblaze.c  |  2 +-
+ gcc/config/microblaze/microblaze.md | 10 ++++++++--
+ 2 files changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 9eae5515c60..0a4619eec0c 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2468,7 +2468,7 @@ print_operand (FILE * file, rtx op, int letter)
+ 	  unsigned long value_long;
+ 	  REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op),
+ 				       value_long);
+-	  fprintf (file, "0x%lx", value_long);
++	  fprintf (file, "0x%08x", (unsigned int) value_long);
+ 	}
+       else
+ 	{
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index efd2c34e0b7..be8bbda2bfb 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1368,7 +1368,10 @@
+                    (match_operand:SI 2 "immediate_operand" "I")))] 
+   "!TARGET_SOFT_MUL 
+    && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
+-  "muli\t%0,%1,%m2"
++  {
++    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++    return "muli\t%0,%1,%2";
++  }
+   ;; This MUL will not generate an imm. Can go into a delay slot.
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"SI")
+@@ -1380,7 +1383,10 @@
+ 	(ashift:SI (match_operand:SI 1 "register_operand"  "d")
+                    (match_operand:SI 2 "immediate_operand" "I")))] 
+   "!TARGET_SOFT_MUL"
+-  "muli\t%0,%1,%m2"
++  {
++    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
++    return "muli\t%0,%1,%2";
++  }
+   ;; This MUL will generate an IMM. Cannot go into a delay slot
+   [(set_attr "type"	"no_delay_arith")
+    (set_attr "mode"	"SI")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
new file mode 100644
index 0000000000..07cf635de4
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
@@ -0,0 +1,178 @@
+From bfdb38133201f7df01d09dc7e7ee3043a35c1d3e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 9 Nov 2020 19:54:39 +0530
+Subject: [PATCH 20/54] [Patch, microblaze]: 8-stage pipeline for microblaze
+
+This patch adds the support for the 8-stage pipeline. The new 8-stage
+pipeline reduces the latencies of float & integer division drastically
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c   | 11 ++++
+ gcc/config/microblaze/microblaze.h   |  3 +-
+ gcc/config/microblaze/microblaze.md  | 79 +++++++++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt |  4 ++
+ 4 files changed, 94 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 0a4619eec0c..0dc96e481b7 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -1840,6 +1840,17 @@ microblaze_option_override (void)
+ 		   "%<-mcpu=v8.30.a%>");
+         TARGET_REORDER = 0;
+     }
++  ver = microblaze_version_to_int("v10.0");
++  if (ver < 0)
++    {
++        if (TARGET_AREA_OPTIMIZED_2)
++          warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
++    }
++  else
++    {
++        if (TARGET_AREA_OPTIMIZED_2)
++          microblaze_pipe = MICROBLAZE_PIPE_8;
++    }
+ 
+   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+     error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 8aa3f155790..8a668278337 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -27,7 +27,8 @@
+ enum pipeline_type
+ {
+   MICROBLAZE_PIPE_3 = 0,
+-  MICROBLAZE_PIPE_5 = 1
++  MICROBLAZE_PIPE_5 = 1,
++  MICROBLAZE_PIPE_8 = 2
+ };
+ 
+ #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index be8bbda2bfb..c407a81c51e 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -35,6 +35,7 @@
+   (R_GOT      20)       ;; GOT ptr reg
+   (MB_PIPE_3   0)       ;; Microblaze 3-stage pipeline 
+   (MB_PIPE_5   1)       ;; Microblaze 5-stage pipeline 
++  (MB_PIPE_8   2)       ;; Microblaze 8-stage pipeline
+   (UNSPEC_SET_GOT       101)    ;;
+   (UNSPEC_GOTOFF        102)    ;; GOT offset
+   (UNSPEC_PLT           103)    ;; jump table
+@@ -82,7 +83,7 @@
+ ;; bshift 	Shift operations
+ 
+ (define_attr "type"
+-  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
++  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
+   (const_string "unknown"))
+ 
+ ;; Main data type used by the insn
+@@ -224,6 +225,80 @@
+ ;;-----------------------------------------------------------------
+ 
+ 
++
++;;----------------------------------------------------------------
++;; Microblaze 8-stage pipeline description (v10.0 and later)
++;;----------------------------------------------------------------
++
++(define_automaton   "mbpipe_8")
++(define_cpu_unit    "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
++
++(define_insn_reservation "mb8-integer" 1
++  (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-special-move" 2
++  (and (eq_attr "type" "move")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu*2,mb8_wb")
++
++(define_insn_reservation "mb8-mem-load" 3
++  (and (eq_attr "type" "load,no_delay_load")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mem-store" 1
++  (and (eq_attr "type" "store,no_delay_store")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_iu,mb8_wb")
++
++(define_insn_reservation "mb8-mul" 3
++  (and (eq_attr "type" "imul,no_delay_imul")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
++
++(define_insn_reservation "mb8-div" 30
++  (and (eq_attr "type" "idiv")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++    "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
++
++(define_insn_reservation "mb8-bs" 2
++  (and (eq_attr "type" "bshift")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++   "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-add-sub-mul" 1
++  (and (eq_attr "type" "fadd,frsub,fmul")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcmp" 3
++  (and (eq_attr "type" "fcmp")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-div" 24
++  (and (eq_attr "type" "fdiv")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-sqrt" 23
++  (and (eq_attr "type" "fsqrt")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fcvt" 1
++  (and (eq_attr "type" "fcvt")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++(define_insn_reservation "mb8-fpu-fint" 2
++  (and (eq_attr "type" "fint")
++       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
++  "mb8_issue,mb8_fpu,mb8_wb")
++
++
+ ;;----------------------------------------------------------------
+ ;; Microblaze 5-stage pipeline description (v5.00.a and later)
+ ;;----------------------------------------------------------------                 
+@@ -470,7 +545,7 @@
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+   "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "fint\t%0,%1"
+-  [(set_attr "type"     "fcvt")
++  [(set_attr "type"     "fint")
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index 725c2fab52a..a29c6f8df90 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
+ 
+ mxl-mode-xilkernel
+ Target
++
++mxl-frequency
++Target Mask(AREA_OPTIMIZED_2)
++Use 8 stage pipeline (frequency optimization)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
deleted file mode 100644
index cc1c3d7eee..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch
+++ /dev/null
@@ -1,61 +0,0 @@
-From 1bbf48097cf2da98e03139b499a5a74bc68e6abc Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:11:04 +0530
-Subject: [PATCH 20/58] [Patch,microblaze]: Inline Expansion of fsqrt builtin.
-
-The changes are made in the patch for the inline expansion of
-the fsqrt builtin with fqrt instruction. The sqrt math function
-takes double as argument and return double as argument. The
-pattern is selected while expanding the unary op through
-expand_unop which passes DFmode and the DFmode pattern was
-not there returning zero. Thus the sqrt math function is not
-inlined and expanded. The pattern with DFmode argument is added.
-Also the source and destination argument is not same the DF
-through two different consecutive registers with lower 32 bit
-is the argument passed to sqrt and the higher 32 bit is zero.
-If the source and destinations are different the DFmode 64 bits
-registers is not set properly giving the problem in runtime. Such
-changes are taken care in the implementation of the pattern for
-DFmode for inline expansion of the sqrt.
-
-ChangeLog:
-2015-06-16  Ajit Agarwal  <ajitkum@xilinx.com>
-            Nagaraju Mekala <nmekala@xilinx.com>
-
-	* config/microblaze/microblaze.md (sqrtdf2): New
-	pattern.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
-              Nagaraju Mekala nmekala@xilinx.com
----
- gcc/config/microblaze/microblaze.md | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 8f9baec826b..986d9c3aa25 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -451,6 +451,20 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "sqrtdf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
-+  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
-+  {
-+    if (REGNO (operands[0]) == REGNO (operands[1]))
-+      return "fsqrt\t%0,%1";
-+    else
-+      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
-+  }
-+  [(set_attr "type"     "fsqrt")
-+   (set_attr "mode"      "SF")
-+   (set_attr "length"    "4")])
-+
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
deleted file mode 100644
index b4d03172cd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From fe7962c6cc54a5d5f80db90ccc06b8603ddeb74f Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 17:33:31 +0530
-Subject: [PATCH 21/58] [Patch] OPT: Update heuristics for loop-invariant for
- address arithmetic
-
-The changes are made in the patch to update the heuristics
-for loop invariant for address arithmetic. The heuristics is
-changed to calculate the estimated register pressure cost when
-ira based register pressure is not enabled. The estimated
-register pressure cost modifies the existing calculation cost
-associated to perform the Loop invariant code motion for address
-arithmetic.
-
-ChangeLog:
-2015-06-17  Ajit Agarwal  <ajitkum@xilinx.com>
-            Nagaraju Mekala <nmekala@xilinx.com>
-
-	* loop-invariant.c (gain_for_invariant): update the
-	heuristics for estimate_reg_pressure_cost.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com
-              Nagaraju Mekala nmekala@xilinx.com
----
- gcc/loop-invariant.c | 6 ++----
- 1 file changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index 37ae6549e56..f6385d6cf43 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1465,10 +1465,8 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- 
-   if (! flag_ira_loop_pressure)
-     {
--      size_cost = (estimate_reg_pressure_cost (new_regs[0] + regs_needed[0],
--					       regs_used, speed, call_p)
--		   - estimate_reg_pressure_cost (new_regs[0],
--						 regs_used, speed, call_p));
-+      size_cost = estimate_reg_pressure_cost (regs_needed[0],
-+					       regs_used, speed, call_p);
-     }
-   else if (ret < 0)
-     return -1;
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
new file mode 100644
index 0000000000..f362cea858
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0021-Patch-microblaze-Correct-the-const-high-double-immed.patch
@@ -0,0 +1,58 @@
+From af01da22797795408d45dcf03076dc8153c7029e Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 9 Nov 2020 21:14:54 +0530
+Subject: [PATCH 21/54] [Patch, microblaze]: Correct the const high double
+ immediate value with this patch the loading of the DI mode immediate values
+ will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
+ functions, as CONST_DOUBLE_HIGH was returning the sign extension value even
+ of the unsigned long long constants also
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.c                | 6 ++++--
+ gcc/testsuite/gcc.target/microblaze/others/long.c | 9 +++++++++
+ 2 files changed, 13 insertions(+), 2 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/microblaze/others/long.c
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 0dc96e481b7..5d395f047f7 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2452,14 +2452,16 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
++      long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+ 	  if (GET_MODE (op) == DFmode)
+ 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
+ 	  else
+ 	    {
+-	      val[0] = CONST_DOUBLE_HIGH (op);
+-	      val[1] = CONST_DOUBLE_LOW (op);
++	      REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
++	      val[1] = l[WORDS_BIG_ENDIAN == 0];
++	      val[0] = l[WORDS_BIG_ENDIAN != 0];
+ 	    }
+ 	}
+       else if (code == CONST_INT)
+diff --git a/gcc/testsuite/gcc.target/microblaze/others/long.c b/gcc/testsuite/gcc.target/microblaze/others/long.c
+new file mode 100644
+index 00000000000..b6b55d5ad65
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/microblaze/others/long.c
+@@ -0,0 +1,9 @@
++#define BASEADDR 0xF0000000ULL
++int main ()
++{
++  unsigned long long start;
++  start = (unsigned long long) BASEADDR;
++  return 0;
++}
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
++/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
new file mode 100644
index 0000000000..3faef052b4
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
@@ -0,0 +1,36 @@
+From 7349def8102c09fd09e735daa9fc890bee323e79 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 11:49:58 +0530
+Subject: [PATCH 22/54] [Fix, microblaze]: Fix internal compiler error with
+ msmall-divides This patch will fix the internal error
+ microblaze_expand_divide function which comes because of rtx PLUS where the
+ mem_rtx is of type SI and the operand is of type QImode. This patch modifies
+ the mem_rtx as QImode and Plus as QImode to fix the error.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+ChangeLog:
+  2016-02-23 Nagaraju Mekala <nmekala@xilix.com>
+             Ajit Agarwal  <ajitkum@xilinx.com>
+
+                                  *microblaze.c (microblaze_expand_divide): Update
+---
+ gcc/config/microblaze/microblaze.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 5d395f047f7..29b2f6b016b 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3767,7 +3767,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+   emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
+   mem_rtx = gen_rtx_MEM (QImode,
+-                            gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
++                            gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
deleted file mode 100644
index 2e5afed8b1..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch
+++ /dev/null
@@ -1,66 +0,0 @@
-From b066cb189302814fcd91b38f2f9da830a2c5b8fe Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 18:07:24 +0530
-Subject: [PATCH 22/58] [PATCH] microblaze.md: Improve 'adddi3' and 'subdi3'
- insn definitions
-
-Change adddi3 to handle DI immediates as the second operand, this
-requires modification to the output template however reduces the need to
-specify seperate templates for 16-bit positive/negative immediate
-operands. The use of 32-bit immediates for the addi and addic
-instructions is handled by the assembler, which will emit the imm
-instructions when required. This conveniently handles the optimizable
-cases where the immediate constant value does not need the higher half
-words of the operands upper/lower words.
-
-Change the constraints of the subdi3 instruction definition such that it
-does not match the second operand as an immediate value. This is because
-there is no definition to handle this case nor is it possible to
-implement purely with instructions as microblaze does not provide an
-instruction to perform a forward arithmetic subtraction (it only
-provides reverse 'rD = IMM - rA').
-
-Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
----
- gcc/config/microblaze/microblaze.md | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 986d9c3aa25..efd2c34e0b7 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -502,17 +502,16 @@
- ;; Adding 2 DI operands in register or reg/imm
- 
- (define_insn "adddi3"
--  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
--	(plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
--		 (match_operand:DI 2 "arith_operand32" "d,P,N")))]
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-+		 (match_operand:DI 2 "arith_operand" "d,i")))]
-   ""
-   "@
-   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
--  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0
--  addi\t%L0,%L1,%2\;addc\t%M0,%M1,r0\;addi\t%M0,%M0,-1"
-+  addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
-   [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
--  (set_attr "length"	"8,8,12")])
-+  (set_attr "length"	"8,8")])
- 
- ;;----------------------------------------------------------------
- ;; Subtraction
-@@ -549,7 +548,7 @@
- (define_insn "subdi3"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
--		  (match_operand:DI 2 "arith_operand32" "d")))]
-+		  (match_operand:DI 2 "register_operand" "d")))]
-   ""
-   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
-   [(set_attr "type"	"darith")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
deleted file mode 100644
index fa16749ed2..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 98018d020d9fbae38ea19627dec64d03d7f21fac Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 18:18:41 +0530
-Subject: [PATCH 23/58] [Patch, microblaze]: Update ashlsi3 & movsf patterns
-
-This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in
-print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay
-and movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX
-is generating 64-bit value which our instruction doesn't support
-so using gen_int_mode function
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-              :Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-01-07 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-  *microblaze.md (ashlsi3_with_mul_nodelay,
-                  ashlsi3_with_mul_delay,
-                  movsf_internal):
-    Updated the patterns to use gen_int_mode function
-  *microblaze.c (print_operand):
-     updated the 'F' case to use "unsinged int" instead
-     of HOST_WIDE_INT_PRINT_HEX
----
- gcc/config/microblaze/microblaze.md | 10 ++++++++--
- 1 file changed, 8 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index efd2c34e0b7..be8bbda2bfb 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1368,7 +1368,10 @@
-                    (match_operand:SI 2 "immediate_operand" "I")))] 
-   "!TARGET_SOFT_MUL 
-    && ((1 << INTVAL (operands[2])) <= 32767 && (1 << INTVAL (operands[2])) >= -32768)"
--  "muli\t%0,%1,%m2"
-+  {
-+    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
-+    return "muli\t%0,%1,%2";
-+  }
-   ;; This MUL will not generate an imm. Can go into a delay slot.
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"SI")
-@@ -1380,7 +1383,10 @@
- 	(ashift:SI (match_operand:SI 1 "register_operand"  "d")
-                    (match_operand:SI 2 "immediate_operand" "I")))] 
-   "!TARGET_SOFT_MUL"
--  "muli\t%0,%1,%m2"
-+  {
-+    operands[2] = gen_int_mode (1 << INTVAL (operands[2]), SImode);
-+    return "muli\t%0,%1,%2";
-+  }
-   ;; This MUL will generate an IMM. Cannot go into a delay slot
-   [(set_attr "type"	"no_delay_arith")
-    (set_attr "mode"	"SI")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
new file mode 100644
index 0000000000..1c4f8ca9e2
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
@@ -0,0 +1,45 @@
+From ad3d0a29a4895351008ce959138c13b8f5924464 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 12:03:39 +0530
+Subject: [PATCH 23/54] [patch,microblaze]: Fix the calculation of high word in
+ a long long 6. .4-bit
+
+This patch will change the calculation of high word in a long long 64-bit.
+Earlier to this patch the high word of long long word (0xF0000000ULL) is
+coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
+should be 0x00000000 and the low word should be 0xF0000000. This patch
+removes the condition of checking high word = 0 & low word < 0.
+This check is not required for the correctness of calculating 32-bit high
+and low words in a 64-bit long long.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+               Ajit Agarwal  <ajitkum@xilinx.com>
+
+ChangeLog:
+2016-03-01 Nagaraju Mekala <nmekala@xilix.com>
+           Ajit Agarwal  <ajitkum@xilinx.com>
+
+    *config/microblaze/microblaze.c (print_operand): Remove the condition of checking
+    high word = 0 & low word < 0.
+    *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
+---
+ gcc/config/microblaze/microblaze.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 29b2f6b016b..4710def18cf 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2468,9 +2468,6 @@ print_operand (FILE * file, rtx op, int letter)
+         {
+ 	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+ 	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+-	  if (val[0] == 0 && val[1] < 0)
+-	    val[0] = -1;
+-	    
+         }
+       fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+     }
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
deleted file mode 100644
index 8e0eda3c1a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch
+++ /dev/null
@@ -1,213 +0,0 @@
-From 3f98e90620e0ae6d76a1ba18e97389feb095c3e4 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 17 Jan 2017 19:50:34 +0530
-Subject: [PATCH 24/58] [Patch, microblaze]: 8-stage pipeline for microblaze
-
-This patch adds the support for the 8-stage pipeline. The new 8-stage
-pipeline reduces the latencies of float & integer division drastically
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (define_automaton mbpipe_8): New
-
-  *microblaze.c (microblaze_option_override): Update
-    Updated the logic to generate only when MB version is 10.0
-
-  *microblaze.h (pipeline_type): Update
-          Update the enum with MICROBLAZE_PIPE_8
-
-  *microblaze.opt (mxl-frequency): New
-         New flag added for 8-stage pipeline
----
- gcc/config/microblaze/microblaze.c   | 18 ++++++-
- gcc/config/microblaze/microblaze.h   |  3 +-
- gcc/config/microblaze/microblaze.md  | 79 +++++++++++++++++++++++++++-
- gcc/config/microblaze/microblaze.opt |  4 ++
- 4 files changed, 100 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a4bdf66f045..a3996119bd7 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
- /* Set to one if the targeted core has the CLZ insn.  */
- int microblaze_has_clz = 0;
- 
-+/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
-+int microblaze_has_bitfield = 0;
-+
- /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
-    version having only a particular type of pipeline. There can still be 
-    options on the CPU to scale pipeline features up or down. :( 
-@@ -1739,7 +1742,7 @@ microblaze_option_override (void)
-   register int i, start;
-   register int regno;
-   register machine_mode mode;
--  int ver;
-+  int ver,ver_int;
- 
-   microblaze_section_threshold = (global_options_set.x_g_switch_value
- 				  ? g_switch_value
-@@ -1840,6 +1843,19 @@ microblaze_option_override (void)
- 		   "%<-mcpu=v8.30.a%>");
-         TARGET_REORDER = 0;
-     }
-+  ver = ver_int - microblaze_version_to_int("v10.0");
-+  if (ver < 0)
-+    {
-+        if (TARGET_AREA_OPTIMIZED_2)
-+          warning (0, "-mxl-frequency can be used only with -mcpu=v10.0 or greater");
-+    }
-+  else
-+    {
-+        if (TARGET_AREA_OPTIMIZED_2)
-+          microblaze_pipe = MICROBLAZE_PIPE_8;
-+        if (TARGET_BARREL_SHIFT)
-+          microblaze_has_bitfield = 1;
-+    }
- 
-   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
-     error ("%<-mxl-multiply-high%> requires %<-mno-xl-soft-mul%>");
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1e155e4041c..8b0db2c1718 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -27,7 +27,8 @@
- enum pipeline_type
- {
-   MICROBLAZE_PIPE_3 = 0,
--  MICROBLAZE_PIPE_5 = 1
-+  MICROBLAZE_PIPE_5 = 1,
-+  MICROBLAZE_PIPE_8 = 2
- };
- 
- #define MICROBLAZE_MASK_NO_UNSAFE_DELAY         0x00000001
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index be8bbda2bfb..c407a81c51e 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -35,6 +35,7 @@
-   (R_GOT      20)       ;; GOT ptr reg
-   (MB_PIPE_3   0)       ;; Microblaze 3-stage pipeline 
-   (MB_PIPE_5   1)       ;; Microblaze 5-stage pipeline 
-+  (MB_PIPE_8   2)       ;; Microblaze 8-stage pipeline
-   (UNSPEC_SET_GOT       101)    ;;
-   (UNSPEC_GOTOFF        102)    ;; GOT offset
-   (UNSPEC_PLT           103)    ;; jump table
-@@ -82,7 +83,7 @@
- ;; bshift 	Shift operations
- 
- (define_attr "type"
--  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,trap"
-+  "unknown,branch,jump,call,load,store,move,arith,darith,imul,idiv,icmp,multi,nop,no_delay_arith,no_delay_load,no_delay_store,no_delay_imul,no_delay_move,bshift,fadd,frsub,fmul,fdiv,fcmp,fsl,fsqrt,fcvt,fint,trap"
-   (const_string "unknown"))
- 
- ;; Main data type used by the insn
-@@ -224,6 +225,80 @@
- ;;-----------------------------------------------------------------
- 
- 
-+
-+;;----------------------------------------------------------------
-+;; Microblaze 8-stage pipeline description (v10.0 and later)
-+;;----------------------------------------------------------------
-+
-+(define_automaton   "mbpipe_8")
-+(define_cpu_unit    "mb8_issue,mb8_iu,mb8_wb,mb8_fpu,mb8_fpu_2,mb8_mul,mb8_mul_2,mb8_div,mb8_div_2,mb8_bs,mb8_bs_2" "mbpipe_8")
-+
-+(define_insn_reservation "mb8-integer" 1
-+  (and (eq_attr "type" "branch,jump,call,arith,darith,icmp,nop,no_delay_arith")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-special-move" 2
-+  (and (eq_attr "type" "move")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-mem-load" 3
-+  (and (eq_attr "type" "load,no_delay_load")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-mem-store" 1
-+  (and (eq_attr "type" "store,no_delay_store")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_iu,mb8_wb")
-+
-+(define_insn_reservation "mb8-mul" 3
-+  (and (eq_attr "type" "imul,no_delay_imul")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_mul,mb8_mul_2*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-div" 30
-+  (and (eq_attr "type" "idiv")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+    "mb8_issue,mb8_div,mb8_div_2*29,mb8_wb")
-+
-+(define_insn_reservation "mb8-bs" 2
-+  (and (eq_attr "type" "bshift")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+   "mb8_issue,mb8_bs,mb8_bs_2,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-add-sub-mul" 1
-+  (and (eq_attr "type" "fadd,frsub,fmul")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fcmp" 3
-+  (and (eq_attr "type" "fcmp")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu*2,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-div" 24
-+  (and (eq_attr "type" "fdiv")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu_2*23,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-sqrt" 23
-+  (and (eq_attr "type" "fsqrt")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_fpu_2*22,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fcvt" 1
-+  (and (eq_attr "type" "fcvt")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+(define_insn_reservation "mb8-fpu-fint" 2
-+  (and (eq_attr "type" "fint")
-+       (eq (symbol_ref  "microblaze_pipe") (const_int MB_PIPE_8)))
-+  "mb8_issue,mb8_fpu,mb8_wb")
-+
-+
- ;;----------------------------------------------------------------
- ;; Microblaze 5-stage pipeline description (v5.00.a and later)
- ;;----------------------------------------------------------------                 
-@@ -470,7 +545,7 @@
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-   "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "fint\t%0,%1"
--  [(set_attr "type"     "fcvt")
-+  [(set_attr "type"     "fint")
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index 725c2fab52a..a29c6f8df90 100644
---- a/gcc/config/microblaze/microblaze.opt
-+++ b/gcc/config/microblaze/microblaze.opt
-@@ -133,3 +133,7 @@ Data referenced by offset from start of text instead of GOT (with -fPIC/-fPIE).
- 
- mxl-mode-xilkernel
- Target
-+
-+mxl-frequency
-+Target Mask(AREA_OPTIMIZED_2)
-+Use 8 stage pipeline (frequency optimization)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000000..590cb38cba
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0024-Patch-microblaze-Add-new-bit-field-instructions.patch
@@ -0,0 +1,162 @@
+From 50f5f8341ba39f2e12eef4a149e59f71f032f7d3 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 10 Nov 2020 09:51:24 +0530
+Subject: [PATCH 24/54] [Patch, microblaze]: Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c  |  5 ++
+ gcc/config/microblaze/microblaze.h  |  2 +
+ gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++
+ 3 files changed, 80 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 4710def18cf..14c652325a8 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -164,6 +164,9 @@ int microblaze_no_unsafe_delay;
+ /* Set to one if the targeted core has the CLZ insn.  */
+ int microblaze_has_clz = 0;
+ 
++/* Set to one if the targeted core has barrel-shift and cpu > 10.0 */
++int microblaze_has_bitfield = 0;
++
+ /* Which CPU pipeline do we use. We haven't really standardized on a CPU 
+    version having only a particular type of pipeline. There can still be 
+    options on the CPU to scale pipeline features up or down. :( 
+@@ -1850,6 +1853,8 @@ microblaze_option_override (void)
+     {
+         if (TARGET_AREA_OPTIMIZED_2)
+           microblaze_pipe = MICROBLAZE_PIPE_8;
++        if (TARGET_BARREL_SHIFT)
++          microblaze_has_bitfield = 1;
+     }
+ 
+   if (TARGET_MULTIPLY_HIGH && TARGET_SOFT_MUL)
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 8a668278337..857cb1cd9d0 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
+ 
+ extern int microblaze_no_unsafe_delay;
+ extern int microblaze_has_clz;
++extern int microblaze_has_bitfield;
+ extern enum pipeline_type microblaze_pipe;
+ 
+ #define OBJECT_FORMAT_ELF
+@@ -63,6 +64,7 @@ extern enum pipeline_type microblaze_pipe;
+ /* Do we have CLZ?  */
+ #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
+ 
++#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
+ /* The default is to support PIC.  */
+ #define TARGET_SUPPORTS_PIC 1
+ 
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index c407a81c51e..3e6e2b9276d 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -982,6 +982,8 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"20,20,20")])
+ 
++
++
+ ;;----------------------------------------------------------------
+ ;; Data movement
+ ;;----------------------------------------------------------------
+@@ -1776,6 +1778,7 @@
+   (set_attr "length"   "28")]
+ )
+ 
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an integer comparison. 
+ ;;----------------------------------------------------------------
+@@ -2489,4 +2492,74 @@
+   DONE;
+ }")
+ 
++(define_expand "extvsi"
++  [(set (match_operand:SI 0 "register_operand" "r")
++	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++			 (match_operand:SI 2 "immediate_operand" "I")
++			 (match_operand:SI 3 "immediate_operand" "I")))]
++""
++"
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++  if ((len == 0) || (pos + len > 32) )
++    FAIL;
++
++  ;;if (!register_operand (operands[1], VOIDmode))
++  ;;  FAIL;
++  if (operands[0] == operands[1])
++  FAIL;
++  if (GET_CODE (operands[1]) == ASHIFT)
++  FAIL;
++;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "extv_32"
++  [(set (match_operand:SI 0 "register_operand" "=r")
++	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
++			 (match_operand:SI 2 "immediate_operand" "I")
++			 (match_operand:SI 3 "immediate_operand" "I")))]
++ "TARGET_BARREL_SHIFT && (UINTVAL (operands[2]) > 0)
++   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
++  "bsefi %0,%1,%2,%3"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
++(define_expand "insvsi"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++			 (match_operand:SI 1 "immediate_operand" "I")
++			 (match_operand:SI 2 "immediate_operand" "I"))
++	(match_operand:SI 3 "register_operand" "r"))]
++ ""
++  "
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++  if (len <= 0 || pos + len > 32)
++    FAIL;
++
++  ;;if (!register_operand (operands[0], VOIDmode))
++  ;;  FAIL;
++
++  emit_insn (gen_insv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
++
++(define_insn "insv_32"
++  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
++			 (match_operand:SI 1 "immediate_operand" "I")
++			 (match_operand:SI 2 "immediate_operand" "I"))
++	(match_operand:SI 3 "register_operand" "r"))]
++ "TARGET_BARREL_SHIFT && UINTVAL (operands[1]) > 0
++   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
++  "bsifi %0, %3, %1, %2"
++  [(set_attr "type" "bshift")
++   (set_attr "length" "4")])
++
+ (include "sync.md")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
new file mode 100644
index 0000000000..da24f11397
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
@@ -0,0 +1,247 @@
+From cb67b2e64c0d5bd32d36cb32def5f889122fc37a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 18 Jan 2017 12:42:10 +0530
+Subject: [PATCH 25/54] [Patch, microblaze]: Fix bug in MB version calculation
+ This patch fixes the bug in microblaze_version_to_int function. Earlier the
+ conversion of vXX.YY.Z to int has a bug which is fixed now.
+
+Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
+                Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c | 147 ++++++++++++++---------------
+ 1 file changed, 70 insertions(+), 77 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 14c652325a8..451db9c79b0 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -242,6 +242,63 @@ section *sdata2_section;
+ #define TARGET_HAVE_TLS true
+ #endif
+ 
++/*  Convert a version number of the form "vX.YY.Z" to an integer encoding
++    for easier range comparison.  */
++static int
++microblaze_version_to_int (const char *version)
++{
++  const char *p, *v;
++  const char *tmpl = "vXX.YY.Z";
++  int iver1 =0, iver2 =0, iver3 =0;
++
++  p = version;
++  v = tmpl;
++
++  while (*p)
++    {
++      if (*v == 'X')
++	{			/* Looking for major  */
++          if (*p == '.')
++            {
++              *v++;
++            }
++          else
++            {
++	      if (!(*p >= '0' && *p <= '9'))
++	        return -1;
++	      iver1 += (int) (*p - '0');
++              iver1 *= 1000;
++	     }
++        }
++      else if (*v == 'Y')
++	{			/* Looking for minor  */
++	  if (!(*p >= '0' && *p <= '9'))
++	    return -1;
++	  iver2 += (int) (*p - '0');
++	  iver2 *= 10;
++	}
++      else if (*v == 'Z')
++	{			/* Looking for compat  */
++	  if (!(*p >= 'a' && *p <= 'z'))
++	    return -1;
++      iver3 = ((int) (*p)) - 96;
++	}
++      else
++	{
++	  if (*p != *v)
++	    return -1;
++	}
++
++      v++;
++      p++;
++    }
++
++  if (*p)
++    return -1;
++
++  return iver1 + iver2 + iver3;
++}
++
+ /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
+ static bool
+ microblaze_const_double_ok (rtx op, machine_mode mode)
+@@ -1341,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+       {
+ 	if (TARGET_BARREL_SHIFT)
+ 	  {
+-	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+-		>= 0)
++	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ 	      *total = COSTS_N_INSNS (1);
+ 	    else
+ 	      *total = COSTS_N_INSNS (2);
+@@ -1403,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
+ 	  }
+ 	else if (!TARGET_SOFT_MUL)
+ 	  {
+-	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
+-		>= 0)
++	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
+ 	      *total = COSTS_N_INSNS (1);
+ 	    else
+ 	      *total = COSTS_N_INSNS (3);
+@@ -1677,72 +1732,13 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
+   return 0;
+ }
+ 
+-/*  Convert a version number of the form "vX.YY.Z" to an integer encoding 
+-    for easier range comparison.  */
+-static int
+-microblaze_version_to_int (const char *version)
+-{
+-  const char *p, *v;
+-  const char *tmpl = "vXX.YY.Z";
+-  int iver = 0;
+-
+-  p = version;
+-  v = tmpl;
+-
+-  while (*p)
+-    {
+-      if (*v == 'X')
+-	{			/* Looking for major  */
+-          if (*p == '.')
+-            {
+-              v++;
+-            }
+-          else
+-            {
+-	      if (!(*p >= '0' && *p <= '9'))
+-	        return -1;
+-	      iver += (int) (*p - '0');
+-              iver *= 10;
+-	     }
+-        }
+-      else if (*v == 'Y')
+-	{			/* Looking for minor  */
+-	  if (!(*p >= '0' && *p <= '9'))
+-	    return -1;
+-	  iver += (int) (*p - '0');
+-	  iver *= 10;
+-	}
+-      else if (*v == 'Z')
+-	{			/* Looking for compat  */
+-	  if (!(*p >= 'a' && *p <= 'z'))
+-	    return -1;
+-	  iver *= 10;
+-	  iver += (int) (*p - 'a');
+-	}
+-      else
+-	{
+-	  if (*p != *v)
+-	    return -1;
+-	}
+-
+-      v++;
+-      p++;
+-    }
+-
+-  if (*p)
+-    return -1;
+-
+-  return iver;
+-}
+-
+-
+ static void
+ microblaze_option_override (void)
+ {
+   register int i, start;
+   register int regno;
+   register machine_mode mode;
+-  int ver;
++  int ver,ver_int;
+ 
+   microblaze_section_threshold = (global_options_set.x_g_switch_value
+ 				  ? g_switch_value
+@@ -1763,13 +1759,13 @@ microblaze_option_override (void)
+   /* Check the MicroBlaze CPU version for any special action to be done.  */
+   if (microblaze_select_cpu == NULL)
+     microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
+-  ver = microblaze_version_to_int (microblaze_select_cpu);
+-  if (ver == -1)
++  ver_int = microblaze_version_to_int (microblaze_select_cpu);
++  if (ver_int == -1)
+     {
+       error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
++  ver = ver_int - microblaze_version_to_int("v3.00.a");
+   if (ver < 0)
+     {
+       /* No hardware exceptions in earlier versions. So no worries.  */
+@@ -1780,8 +1776,7 @@ microblaze_option_override (void)
+       microblaze_pipe = MICROBLAZE_PIPE_3;
+     }
+   else if (ver == 0
+-	   || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
+-	       == 0))
++	   || (ver_int ==  microblaze_version_to_int("v4.00.b")))
+     {
+ #if 0
+       microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
+@@ -1798,11 +1793,9 @@ microblaze_option_override (void)
+ #endif
+       microblaze_no_unsafe_delay = 0;
+       microblaze_pipe = MICROBLAZE_PIPE_5;
+-      if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
+-	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+-					 "v5.00.b") == 0
+-	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
+-					 "v5.00.c") == 0)
++      if ((ver_int == microblaze_version_to_int("v5.00.a"))
++	  || (ver_int == microblaze_version_to_int("v5.00.b"))
++	  || (ver_int == microblaze_version_to_int("v5.00.c")))
+ 	{
+ 	  /* Pattern compares are to be turned on by default only when 
+  	     compiling for MB v5.00.'z'.  */
+@@ -1810,7 +1803,7 @@ microblaze_option_override (void)
+ 	}
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
++  ver = ver_int - microblaze_version_to_int("v6.00.a");
+   if (ver < 0)
+     {
+       if (TARGET_MULTIPLY_HIGH)
+@@ -1819,7 +1812,7 @@ microblaze_option_override (void)
+ 		 "%<-mcpu=v6.00.a%> or greater");
+     }
+ 
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
++  ver = ver_int - microblaze_version_to_int("v8.10.a");
+   microblaze_has_clz = 1;
+   if (ver < 0)
+     {
+@@ -1828,7 +1821,7 @@ microblaze_option_override (void)
+     }
+ 
+   /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
+-  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
++  ver = ver_int - microblaze_version_to_int("v8.30.a");
+   if (ver < 0)
+     {
+         if (TARGET_REORDER == 1)
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch
deleted file mode 100644
index f1b793f346..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch
+++ /dev/null
@@ -1,142 +0,0 @@
-From eca67041b3d6e20663313732df0038d75fd2da8d Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:08:40 +0530
-Subject: [PATCH 25/58] [Patch,rtl Optimization]: Better register pressure
- estimate for loop invariant code motion
-
-Calculate the loop liveness used for regs for calculating the register pressure
-in the cost estimation.  Loop liveness is based on the following properties.
-We only need to find the set of objects that are live at the birth or the header
-of the loop. We don't need to calculate the live through the loop by considering
-live in and live out of all the basic blocks of the loop. This is based on the
-point that the set of objects that are live-in at the birth or header of the loop
-will be live-in at every node in the loop.
-
-If a v live is out at the header of the loop then the variable is live-in at every node
-in the loop. To prove this, consider a loop L with header h such that the variable v
-defined at d is live-in at h. Since v is live at h, d is not part of L. This follows i
-from the dominance property, i.e. h is strictly dominated by d. Furthermore, there
-exists a path from h to a use of v which does not go through d. For every node p in
-the loop, since the loop is strongly connected and node is a component of the CFG,
-there exists a path, consisting only of nodes of L from p to h. Concatenating these
-two paths proves that v is live-in and live-out of p.
-
-Calculate the live-out and live-in for the exit edge of the loop. This patch considers
-liveness for not only the loop latch but also the liveness outside the loops.
-
-ChangeLog:
-2016-01-22  Ajit Agarwal  <ajitkum@xilinx.com>
-
-	* loop-invariant.c
-	(find_invariants_to_move): Add the logic of regs_used based
-	on liveness.
-	* cfgloopanal.c
-	(estimate_reg_pressure_cost): Update the heuristics in presence
-	of call_p.
-
-Signed-off-by:Ajit Agarwal ajitkum@xilinx.com.
----
- gcc/cfgloopanal.c    |  4 ++-
- gcc/loop-invariant.c | 63 +++++++++++++++++++++++++++++++++-----------
- 2 files changed, 50 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/cfgloopanal.c b/gcc/cfgloopanal.c
-index 0b33e8272a7..7be8606e4f0 100644
---- a/gcc/cfgloopanal.c
-+++ b/gcc/cfgloopanal.c
-@@ -418,7 +418,9 @@ estimate_reg_pressure_cost (unsigned n_new, unsigned n_old, bool speed,
-   if (regs_needed + target_res_regs <= available_regs)
-     return 0;
- 
--  if (regs_needed <= available_regs)
-+  if ((regs_needed <= available_regs)
-+      || (call_p && (regs_needed <=
-+          (available_regs + target_clobbered_regs))))
-     /* If we are close to running out of registers, try to preserve
-        them.  */
-     cost = target_reg_cost [speed] * n_new;
-diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
-index f6385d6cf43..8596b5c984d 100644
---- a/gcc/loop-invariant.c
-+++ b/gcc/loop-invariant.c
-@@ -1519,7 +1519,7 @@ gain_for_invariant (struct invariant *inv, unsigned *regs_needed,
- 	size_cost = 0;
-     }
- 
--  return comp_cost - size_cost;
-+  return comp_cost - size_cost + 1;
- }
- 
- /* Finds invariant with best gain for moving.  Returns the gain, stores
-@@ -1613,22 +1613,53 @@ find_invariants_to_move (bool speed, bool call_p)
-     /* REGS_USED is actually never used when the flag is on.  */
-     regs_used = 0;
-   else
--    /* We do not really do a good job in estimating number of
--       registers used; we put some initial bound here to stand for
--       induction variables etc.  that we do not detect.  */
-+    /* The logic used in estimating the number of regs_used is changed.
-+       Now it will be based on liveness of the loop. */
-     {
--      unsigned int n_regs = DF_REG_SIZE (df);
--
--      regs_used = 2;
--
--      for (i = 0; i < n_regs; i++)
--	{
--	  if (!DF_REGNO_FIRST_DEF (i) && DF_REGNO_LAST_USE (i))
--	    {
--	      /* This is a value that is used but not changed inside loop.  */
--	      regs_used++;
--	    }
--	}
-+      int  i;
-+      edge e;
-+      vec<edge> edges;
-+      bitmap_head regs_live;
-+
-+      bitmap_initialize (&regs_live, &reg_obstack);
-+      edges = get_loop_exit_edges (curr_loop);
-+
-+      /* Loop liveness is based on the following properties.
-+         We only need to find the set of objects that are live at the
-+         birth or the header of the loop.
-+         We don't need to calculate the live through the loop considering
-+         live-in and live-out of all the basic blocks of the loop. This is
-+         based on the point that the set of objects that are live-in at the
-+         birth or header of the loop will be live-in at every block in the
-+         loop.
-+
-+         If a v live out at the header of the loop then the variable is
-+         live-in at every node in the Loop. To prove this, consider a loop
-+         L with header h such that the variable v defined at d is live-in
-+         at h. Since v is live at h, d is not part of L. This follows from
-+         the dominance property, i.e. h is strictly dominated by d. Furthermore,
-+         there exists a path from h to a use of v which does not go through d.
-+         For every node of the loop, p, since the loop is strongly connected
-+         component of the CFG, there exists a path, consisting only of nodes
-+         of L from p to h. Concatenating these two paths prove that v is
-+         live-in and live-out of p.  */
-+
-+       bitmap_ior_into (&regs_live, DF_LR_IN (curr_loop->header));
-+       bitmap_ior_into (&regs_live, DF_LR_OUT (curr_loop->header));
-+
-+       /* Calculate the live-out and live-in for the exit edge of the loop.
-+          This considers liveness for not only the loop latch but also the
-+          liveness outside the loops.  */
-+
-+       FOR_EACH_VEC_ELT (edges, i, e)
-+         {
-+           bitmap_ior_into (&regs_live, DF_LR_OUT (e->src));
-+           bitmap_ior_into (&regs_live, DF_LR_IN (e->dest));
-+         }
-+
-+       regs_used = bitmap_count_bits (&regs_live) + 2;
-+       bitmap_clear (&regs_live);
-+       edges.release ();
-     }
- 
-   if (! flag_ira_loop_pressure)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch
new file mode 100644
index 0000000000..c0719f6e07
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Fixing-the-issue-with-the-builtin_alloc.patch
@@ -0,0 +1,44 @@
+From fdb2f23a69182da516c7bf89a9e0011e55120f94 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 23 Feb 2017 17:09:04 +0530
+Subject: [PATCH 26/54] Fixing the issue with the builtin_alloc. register r18
+ was not properly handling the stack pattern which was resolved by using free
+ available register
+
+signed-off-by:nagaraju mekala <nmekala@xilinx.com>
+---
+ gcc/config/microblaze/microblaze.md | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 3e6e2b9276d..d938efcd762 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2078,10 +2078,10 @@
+   ""
+   { 
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+-    rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
++    rtx reg = gen_reg_rtx (Pmode);
+     rtx neg_op0;
+ 
+-    emit_move_insn (rtmp, retaddr);
++    emit_move_insn (reg, retaddr);
+     if (GET_CODE (operands[1]) != CONST_INT)
+     {
+         neg_op0 = gen_reg_rtx (Pmode);
+@@ -2090,9 +2090,9 @@
+         neg_op0 = GEN_INT (- INTVAL (operands[1]));
+ 
+     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
+-    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
++    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
+     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
+-    emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
++    emit_insn (gen_rtx_CLOBBER (SImode, reg));
+     DONE;
+   }
+ )
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch
deleted file mode 100644
index cbc1b7b826..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0026-Patch-microblaze-Correct-the-const-high-double-immed.patch
+++ /dev/null
@@ -1,69 +0,0 @@
-From 711652dd187e5b8d7aa12ecc9f569f10b1521bd1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:25:48 +0530
-Subject: [PATCH 26/58] [Patch, microblaze]: Correct the const high double
- immediate value
-
-With this patch the loading of the DI mode immediate values will be
-using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE
-functions, as CONST_DOUBLE_HIGH was returning the sign extension value
-even of the unsigned long long constants also
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
- *microblaze.c (print_operand): Use REAL_VALUE_FROM_CONST_DOUBLE &
-        REAL_VALUE_TO_TARGET_DOUBLE
- *long.c (new): Added new testcase
----
- gcc/config/microblaze/microblaze.c         |  6 ++++--
- gcc/testsuite/gcc.target/microblaze/long.c | 10 ++++++++++
- 2 files changed, 14 insertions(+), 2 deletions(-)
- create mode 100644 gcc/testsuite/gcc.target/microblaze/long.c
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index a3996119bd7..73d0e010cda 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2587,14 +2587,16 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
-+      long l[2];
-       if (code == CONST_DOUBLE)
- 	{
- 	  if (GET_MODE (op) == DFmode)
- 	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
- 	  else
- 	    {
--	      val[0] = CONST_DOUBLE_HIGH (op);
--	      val[1] = CONST_DOUBLE_LOW (op);
-+              REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-+              val[1] = l[WORDS_BIG_ENDIAN == 0];
-+              val[0] = l[WORDS_BIG_ENDIAN != 0];
- 	    }
- 	}
-       else if (code == CONST_INT)
-diff --git a/gcc/testsuite/gcc.target/microblaze/long.c b/gcc/testsuite/gcc.target/microblaze/long.c
-new file mode 100644
-index 00000000000..4d4518619d1
---- /dev/null
-+++ b/gcc/testsuite/gcc.target/microblaze/long.c
-@@ -0,0 +1,10 @@
-+/* { dg-options "-O0" } */
-+#define BASEADDR 0xF0000000ULL
-+int main ()
-+{
-+  unsigned long long start;
-+  start = (unsigned long long) BASEADDR;
-+  return 0;
-+}
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0x00000000" } } */
-+/* { dg-final { scan-assembler "addik\tr(\[0-9]\|\[1-2]\[0-9]\|3\[0-1]),r0,0xf0000000" } } */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
deleted file mode 100644
index 3869db1573..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From ea79d97f430d554921d94d30cb8db851cce6664b Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 11:49:58 +0530
-Subject: [PATCH 27/58] [Fix, microblaze]: Fix internal compiler error with
- msmall-divides
-
-This patch will fix the internal error microblaze_expand_divide function which comes because
-of rtx PLUS where the mem_rtx is of type SI and the operand is of type QImode.
-This patch modifies the mem_rtx as QImode and Plus as QImode to fix the error.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-ChangeLog:
-  2016-02-23 Nagaraju Mekala <nmekala@xilix.com>
-             Ajit Agarwal  <ajitkum@xilinx.com>
-
-                                  *microblaze.c (microblaze_expand_divide): Update
----
- gcc/config/microblaze/microblaze.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 73d0e010cda..f7c29ef28f5 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3902,7 +3902,7 @@ microblaze_expand_divide (rtx operands[])
-   emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
-   emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-   mem_rtx = gen_rtx_MEM (QImode,
--                            gen_rtx_PLUS (Pmode, regt1, div_table_rtx));
-+                            gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
-   jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
new file mode 100644
index 0000000000..7627b76515
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
@@ -0,0 +1,84 @@
+From 336d984c580345eccdeb889af8ef8c986afc1dad Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 19 Feb 2018 18:06:16 +0530
+Subject: [PATCH 27/54] [Patch,Microblaze]: update in constraints for bitfield
+ insert and extract instructions.
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
+---
+ gcc/config/microblaze/microblaze.md | 45 +++++------------------------
+ 1 file changed, 8 insertions(+), 37 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index d938efcd762..63ad94b972f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2492,33 +2492,17 @@
+   DONE;
+ }")
+ 
+-(define_expand "extvsi"
++(define_expand "extzvsi"
+   [(set (match_operand:SI 0 "register_operand" "r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+ 			 (match_operand:SI 3 "immediate_operand" "I")))]
++"TARGET_HAS_BITFIELD"
+ ""
+-"
+-{
+-  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
+-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
+-
+-  if ((len == 0) || (pos + len > 32) )
+-    FAIL;
+-
+-  ;;if (!register_operand (operands[1], VOIDmode))
+-  ;;  FAIL;
+-  if (operands[0] == operands[1])
+-  FAIL;
+-  if (GET_CODE (operands[1]) == ASHIFT)
+-  FAIL;
+-;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
+- emit_insn (gen_extv_32 (operands[0], operands[1],
+-			  operands[2], operands[3]));
+-  DONE;
+-}")
++)
+ 
+-(define_insn "extv_32"
++
++(define_insn "extzv_32"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+@@ -2534,22 +2518,9 @@
+ 			 (match_operand:SI 1 "immediate_operand" "I")
+ 			 (match_operand:SI 2 "immediate_operand" "I"))
+ 	(match_operand:SI 3 "register_operand" "r"))]
+- ""
+-  "
+-{
+-  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
+-  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
+-
+-  if (len <= 0 || pos + len > 32)
+-    FAIL;
+-
+-  ;;if (!register_operand (operands[0], VOIDmode))
+-  ;;  FAIL;
+-
+-  emit_insn (gen_insv_32 (operands[0], operands[1],
+-			  operands[2], operands[3]));
+-  DONE;
+-}")
++ "TARGET_HAS_BITFIELD"
++""
++)
+ 
+ (define_insn "insv_32"
+   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
new file mode 100644
index 0000000000..f12cea242a
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
@@ -0,0 +1,38 @@
+From e4f5435e6e77afe0150bf36ec9d3d055cf25a089 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 4 Jun 2018 10:10:18 +0530
+Subject: [PATCH 28/54] [Patch,Microblaze] : Removed fsqrt generation for
+ double values.
+
+---
+ gcc/config/microblaze/microblaze.md | 14 --------------
+ 1 file changed, 14 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 63ad94b972f..7695b105baa 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -526,20 +526,6 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "sqrtdf2"
+-  [(set (match_operand:DF 0 "register_operand" "=d")
+-        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
+-  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
+-  {
+-    if (REGNO (operands[0]) == REGNO (operands[1]))
+-      return "fsqrt\t%0,%1";
+-    else
+-      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
+-  }
+-  [(set_attr "type"     "fsqrt")
+-   (set_attr "mode"      "SF")
+-   (set_attr "length"    "4")])
+-
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
deleted file mode 100644
index 3f9dd69b03..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From fa067a4b7b65aae3671bb02d77c580c9e35fc384 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:03:39 +0530
-Subject: [PATCH 28/58] [patch,microblaze]: Fix the calculation of high word in
- a long long 64-bit
-
-This patch will change the calculation of high word in a long long 64-bit.
-Earlier to this patch the high word of long long word (0xF0000000ULL) is
-coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word
-should be 0x00000000 and the low word should be 0xF0000000. This patch
-removes the condition of checking high word = 0 & low word < 0.
-This check is not required for the correctness of calculating 32-bit high
-and low words in a 64-bit long long.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-               Ajit Agarwal  <ajitkum@xilinx.com>
-
-ChangeLog:
-2016-03-01 Nagaraju Mekala <nmekala@xilix.com>
-           Ajit Agarwal  <ajitkum@xilinx.com>
-
-    *config/microblaze/microblaze.c (print_operand): Remove the condition of checking
-    high word = 0 & low word < 0.
-    *testsuite/gcc.target/microblaze/others/long.c: Add -O0 option.
----
- gcc/config/microblaze/microblaze.c | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index f7c29ef28f5..0a73a6c32b4 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2603,9 +2603,6 @@ print_operand (FILE * file, rtx op, int letter)
-         {
- 	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
- 	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
--	  if (val[0] == 0 && val[1] < 0)
--	    val[0] = -1;
--	    
-         }
-       fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-     }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
new file mode 100644
index 0000000000..d9603721a9
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch
@@ -0,0 +1,845 @@
+From 1a7fda96cb247bad0a4df61cd8fd3e65c0e6f35d Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 10 Nov 2020 12:52:54 +0530
+Subject: [PATCH 29/54] [Patch,MicroBlaze]: Intial commit of 64-bit Microblaze
+
+---
+ gcc/config/microblaze/constraints.md      |   6 +
+ gcc/config/microblaze/microblaze-protos.h |   1 +
+ gcc/config/microblaze/microblaze.c        | 109 ++++--
+ gcc/config/microblaze/microblaze.h        |   4 +-
+ gcc/config/microblaze/microblaze.md       | 395 +++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.opt      |   7 +-
+ gcc/config/microblaze/t-microblaze        |   7 +-
+ 7 files changed, 492 insertions(+), 37 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index b9fc6e3fae2..123395717e0 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -52,6 +52,12 @@
+   (and (match_code "const_int")
+        (match_test "ival > 0 && ival < 0x10000")))
+ 
++(define_constraint "K"
++  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
++  (and (match_code "const_int")
++       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
++
++
+ ;; Define floating point constraints
+ 
+ (define_constraint "G"
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index c2f88813a8d..460feac4ac5 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
+ extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
+ extern void microblaze_expand_conditional_branch_sf (rtx *); 
++extern void microblaze_expand_conditional_branch_df (rtx *); 
+ extern int microblaze_can_use_return_insn (void);
+ extern void print_operand (FILE *, rtx, int);
+ extern void print_operand_address (FILE *, rtx);
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 451db9c79b0..99a1cd5c0be 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3432,11 +3432,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+   op0 = operands[0];
+   op1 = operands[1];
+ 
+-  if (!register_operand (op0, SImode)
+-      && !register_operand (op1, SImode)
++  if (!register_operand (op0, mode)
++      && !register_operand (op1, mode)
+       && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
+     {
+-      rtx temp = force_reg (SImode, op1);
++      rtx temp = force_reg (mode, op1);
+       emit_move_insn (op0, temp);
+       return true;
+     }
+@@ -3501,12 +3501,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
+ 	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
+ 		      || !SMALL_INT (p1)))))
+ 	{
+-	  rtx temp = force_reg (SImode, p0);
++	  rtx temp = force_reg (mode, p0);
+ 	  rtx temp2 = p1;
+ 
+ 	  if (flag_pic && reload_in_progress)
+ 	    df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
+-	  emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
++	  emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
+ 	  return true;
+ 	}
+     }
+@@ -3637,7 +3637,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+   rtx cmp_op0 = operands[1];
+   rtx cmp_op1 = operands[2];
+   rtx label1 = operands[3];
+-  rtx comp_reg = gen_reg_rtx (SImode);
++  rtx comp_reg = gen_reg_rtx (mode);
+   rtx condition;
+ 
+   gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
+@@ -3646,23 +3646,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+   if (cmp_op1 == const0_rtx)
+     {
+       comp_reg = cmp_op0;
+-      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
++
+     }
+ 
+   else if (code == EQ || code == NE)
+     {
+       /* Use xor for equal/not-equal comparison.  */
+-      emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
+-      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
++      else
++        emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
++      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else
+     {
+       /* Generate compare and branch in single instruction. */
+       cmp_op1 = force_reg (mode, cmp_op1);
+       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
+-      emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
++      if (mode == SImode)
++        emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
++      else
++        emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
+     }
+ }
+ 
+@@ -3673,7 +3686,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+   rtx cmp_op0 = operands[1];
+   rtx cmp_op1 = operands[2];
+   rtx label1 = operands[3];
+-  rtx comp_reg = gen_reg_rtx (SImode);
++  rtx comp_reg = gen_reg_rtx (mode);
+   rtx condition;
+ 
+   gcc_assert ((GET_CODE (cmp_op0) == REG)
+@@ -3684,30 +3697,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code),
+-                                  SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++                                  mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else if (code == EQ)
+     {
+-      emit_insn (gen_seq_internal_pat (comp_reg,
+-                                       cmp_op0, cmp_op1));
+-      condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        {
++          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      else
++        {
++          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
++ 
+     }
+   else if (code == NE)
+     {
+-      emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
+-                                       cmp_op1));
+-      condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-      emit_jump_insn (gen_condjump (condition, label1));
++      if (mode == SImode)
++        {
++          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      else
++        {
++          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
++                                           cmp_op1));
++	}
++      condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
++      if (mode == SImode)
++        emit_jump_insn (gen_condjump (condition, label1));
++      else
++        emit_jump_insn (gen_long_condjump (condition, label1));
+     }
+   else
+     {
+       /* Generate compare and branch in single instruction. */
+       cmp_op1 = force_reg (mode, cmp_op1);
+       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
+-      emit_jump_insn (gen_branch_compare (condition, cmp_op0,
+-                                         cmp_op1, label1));
++      if (mode == SImode)
++        emit_jump_insn (gen_branch_compare (condition, cmp_op0,
++                                           cmp_op1, label1));
++      else 
++	{
++          emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
++                                             cmp_op1, label1));
++        }	
++
+     }
+ }
+ 
+@@ -3724,6 +3770,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+   emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
++void
++microblaze_expand_conditional_branch_df (rtx operands[])
++{
++  rtx condition;
++  rtx cmp_op0 = XEXP (operands[0], 0);
++  rtx cmp_op1 = XEXP (operands[0], 1);
++  rtx comp_reg = gen_reg_rtx (DImode);
++
++  emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
++  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
++  emit_jump_insn (gen_long_condjump (condition, operands[3]));
++}
++
+ /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
+ 
+ static bool
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 857cb1cd9d0..c0358603380 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define ASM_SPEC "\
+ %(target_asm_spec) \
+ %{mbig-endian:-EB} \
++%{m64:-m64} \
+ %{mlittle-endian:-EL}"
+ 
+ /* Extra switches sometimes passed to the linker.  */
+@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define LINK_SPEC "%{shared:-shared} -N -relax \
+   %{mbig-endian:-EB --oformat=elf32-microblaze} \
+   %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
++  %{m64:-EL --oformat=elf64-microblazeel} \
+   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
+   %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
+@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
+ #define MIN_UNITS_PER_WORD      4
+ #define INT_TYPE_SIZE           32
+ #define SHORT_TYPE_SIZE         16
+-#define LONG_TYPE_SIZE          32
++#define LONG_TYPE_SIZE          64
+ #define LONG_LONG_TYPE_SIZE     64
+ #define FLOAT_TYPE_SIZE         32
+ #define DOUBLE_TYPE_SIZE        64
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 7695b105baa..4d8429d9a90 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -497,7 +497,6 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
+-
+ (define_insn "divsf3"
+   [(set (match_operand:SF 0 "register_operand" "=d")
+         (div:SF (match_operand:SF 1 "register_operand" "d")
+@@ -508,6 +507,7 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++
+ (define_insn "sqrtsf2"
+   [(set (match_operand:SF 0 "register_operand" "=d")
+         (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
+@@ -562,6 +562,18 @@
+ 
+ ;; Adding 2 DI operands in register or reg/imm
+ 
++(define_insn "adddi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
++		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   addlk\t%0,%z1,%2
++   addlik\t%0,%z1,%2"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "adddi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+@@ -606,6 +618,18 @@
+ ;; Double Precision Subtraction
+ ;;----------------------------------------------------------------
+ 
++(define_insn "subdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
++		  (match_operand:DI 2 "register_operand" "d,n")))]
++  "TARGET_MB_64"
++  "@
++   rsubl\t%0,%2,%1
++   addlik\t%0,%z1,-%2"
++  [(set_attr "type"	"darith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "subdi3"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+@@ -795,6 +819,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "negdi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "rsubl\t%0,%1,r0"
++  [(set_attr "type"	"darith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
+ (define_insn "negdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -814,6 +847,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "one_cmpldi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(not:DI (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "xorli\t%0,%1,-1"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
+ (define_insn "*one_cmpldi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -840,6 +882,20 @@
+ ;; Logical
+ ;;----------------------------------------------------------------
+ 
++(define_insn "anddi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   andl\t%0,%1,%2
++   andli\t%0,%1,%2 #andl1"
++  ;; andli\t%0,%1,%2 #andl3
++  ;; andli\t%0,%1,%2 #andl2
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "andsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ 	(and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
+@@ -855,6 +911,18 @@
+   (set_attr "length"	"4,8,8,8")])
+ 
+ 
++(define_insn "iordi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ior:DI (match_operand:DI 1 "arith_operand" "d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   orl\t%0,%1,%2
++   orli\t%0,%1,%2 #andl1"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
+ (define_insn "iorsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+ 	(ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
+@@ -869,6 +937,19 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "xordi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
++		(match_operand:DI 2 "arith_operand" "d,K")))]
++  "TARGET_MB_64"
++  "@
++   xorl\t%0,%1,%2
++   xorli\t%0,%1,%2 #andl1"
++  [(set_attr "type"	"arith,arith")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")])
++
++
+ (define_insn "xorsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ 	(xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
+@@ -937,6 +1018,26 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++;;(define_expand "extendqidi2"
++;;  [(set (match_operand:DI 0 "register_operand" "=d")
++;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
++;;  "TARGET_MB_64"
++;;  {
++;;	if (GET_CODE (operands[1]) != REG)
++;;	FAIL;
++;;   }
++;;)
++    
++
++;;(define_insn "extendqidi2"
++;;  [(set (match_operand:DI 0 "register_operand" "=d")
++;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
++;;  "TARGET_MB_64"
++;;  "sextl8\t%0,%1"
++;;  [(set_attr "type"	"arith")
++;;  (set_attr "mode"	"DI")
++;;  (set_attr "length"	"4")])
++
+ (define_insn "extendhisi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
+@@ -946,6 +1047,16 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "extendhidi2"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "sextl16\t%0,%1"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++
+ ;; Those for integer source operand are ordered
+ ;; widest source type first.
+ 
+@@ -1011,6 +1122,32 @@
+ )
+ 
+ 
++(define_insn "*movdi_internal_64"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
++	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
++  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
++  { 
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1";
++      case 1:
++	return "addlik\t%0,r0,%1";
++      case 2:
++	  return "addlk\t%0,r0,r0";
++      case 3:
++      case 4:
++	  return "lli\t%0,%1";
++      case 5:
++      case 6:
++        return "sli\t%1,%0";
++    }
++    return "unreachable";
++  }
++  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"   "8,8,8,8,12,8,12")])
++
+ 
+ (define_insn "*movdi_internal"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+@@ -1423,6 +1560,36 @@
+   (set_attr "length"	"4,4")]
+ )
+ 
++;; Barrel shift left
++(define_expand "ashldi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(ashift:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "ashldi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++  bsllli\t%0,%1,%2
++  bslll\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++)
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1548,6 +1715,36 @@
+ ;;----------------------------------------------------------------
+ ;; 32-bit right shifts
+ ;;----------------------------------------------------------------
++;; Barrel shift left
++(define_expand "ashrdi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "ashrdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++   bslrai\t%0,%1,%2
++   bslra\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++  )
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -1657,6 +1854,36 @@
+ ;;----------------------------------------------------------------
+ ;; 32-bit right shifts (logical)
+ ;;----------------------------------------------------------------
++;; Barrel shift left
++(define_expand "lshrdi3"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
++                   (match_operand:DI 2 "arith_operand"    "")))]
++"TARGET_MB_64"
++{
++;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++  {
++    emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else
++  FAIL;
++}    
++)
++
++(define_insn "lshrdi3_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
++                   (match_operand:DI 2 "arith_operand"    "I,d")))]
++  "TARGET_MB_64"
++  "@
++   bslrli\t%0,%1,%2
++   bslrl\t%0,%1,%2"
++  [(set_attr "type"	"bshift,bshift")
++  (set_attr "mode"	"DI,DI")
++  (set_attr "length"	"4,4")]
++  )
+ 
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+@@ -1803,6 +2030,8 @@
+   (set_attr "length"	"4")]
+ )              
+ 
++
++
+ ;;----------------------------------------------------------------
+ ;; Setting a register from an floating point comparison. 
+ ;;----------------------------------------------------------------
+@@ -1818,6 +2047,18 @@
+    (set_attr "length"    "4")]
+ )
+ 
++(define_insn "cstoredf4"
++   [(set (match_operand:DI 0 "register_operand" "=r")
++        (match_operator:DI 1 "ordered_comparison_operator"
++	      [(match_operand:DF 2 "register_operand" "r")
++	       (match_operand:DF 3 "register_operand" "r")]))]
++  "TARGET_MB_64"
++  "dcmp.%C1\t%0,%3,%2"
++  [(set_attr "type"     "fcmp")
++   (set_attr "mode"      "DF")
++   (set_attr "length"    "4")]
++)
++
+ ;;----------------------------------------------------------------
+ ;; Conditional branches
+ ;;----------------------------------------------------------------
+@@ -1930,6 +2171,115 @@
+    (set_attr "length"   "12")]
+ )
+ 
++
++(define_expand "cbranchdi4"
++  [(set (pc)
++        (if_then_else (match_operator 0 "ordered_comparison_operator"
++                       [(match_operand:DI 1 "register_operand")
++                        (match_operand:DI 2 "arith_operand" "I,i")])
++                      (label_ref (match_operand 3 ""))
++                      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch (DImode, operands);
++  DONE;
++})
++
++(define_expand "cbranchdi4_reg"
++  [(set (pc)
++        (if_then_else (match_operator 0 "ordered_comparison_operator"
++                       [(match_operand:DI 1 "register_operand")
++                        (match_operand:DI 2 "register_operand")])
++                      (label_ref (match_operand 3 ""))
++                      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch_reg (DImode, operands);
++  DONE;
++})
++
++(define_expand "cbranchdf4"
++  [(set (pc)
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
++		       [(match_operand:DF 1 "register_operand")
++		        (match_operand:DF 2 "register_operand")])
++		      (label_ref (match_operand 3 ""))
++		      (pc)))]
++  "TARGET_MB_64"
++{
++  microblaze_expand_conditional_branch_df (operands);
++  DONE;
++
++})
++
++;; Used to implement comparison instructions
++(define_expand "long_condjump"
++  [(set (pc)
++	(if_then_else (match_operand 0)
++		      (label_ref (match_operand 1))
++		      (pc)))])
++
++(define_insn "long_branch_zero"
++  [(set (pc)
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++  				 [(match_operand:DI 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "beal%C0i%?\t%z1,%2";
++    else 
++      return "beal%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
++(define_insn "long_branch_compare"
++  [(set (pc)
++        (if_then_else (match_operator:DI 0 "cmp_op"
++                                         [(match_operand:DI 1 "register_operand" "d")
++                                          (match_operand:DI 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:DI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
++    return "beal%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
+@@ -2478,17 +2828,33 @@
+   DONE;
+ }")
+ 
+-(define_expand "extzvsi"
++(define_expand "extvsi"
+   [(set (match_operand:SI 0 "register_operand" "r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+ 			 (match_operand:SI 3 "immediate_operand" "I")))]
+ "TARGET_HAS_BITFIELD"
+-""
+-)
+-
++"
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
++
++  if ((len == 0) || (pos + len > 32) )
++    FAIL;
++
++  ;;if (!register_operand (operands[1], VOIDmode))
++  ;;  FAIL;
++  if (operands[0] == operands[1])
++  FAIL;
++  if (GET_CODE (operands[1]) == ASHIFT)
++  FAIL;
++;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
++ emit_insn (gen_extv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
+ 
+-(define_insn "extzv_32"
++(define_insn "extv_32"
+   [(set (match_operand:SI 0 "register_operand" "=r")
+ 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
+ 			 (match_operand:SI 2 "immediate_operand" "I")
+@@ -2505,8 +2871,21 @@
+ 			 (match_operand:SI 2 "immediate_operand" "I"))
+ 	(match_operand:SI 3 "register_operand" "r"))]
+  "TARGET_HAS_BITFIELD"
+-""
+-)
++  "
++{
++  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
++  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
++
++  if (len <= 0 || pos + len > 32)
++    FAIL;
++
++  ;;if (!register_operand (operands[0], VOIDmode))
++  ;;  FAIL;
++
++  emit_insn (gen_insv_32 (operands[0], operands[1],
++			  operands[2], operands[3]));
++  DONE;
++}")
+ 
+ (define_insn "insv_32"
+   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
+diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
+index a29c6f8df90..bbe48b06da6 100644
+--- a/gcc/config/microblaze/microblaze.opt
++++ b/gcc/config/microblaze/microblaze.opt
+@@ -136,4 +136,9 @@ Target
+ 
+ mxl-frequency
+ Target Mask(AREA_OPTIMIZED_2)
+-Use 8 stage pipeline (frequency optimization)
++Use 8 stage pipeline (frequency optimization).
++
++m64
++Target Mask(MB_64)
++MicroBlaze 64-bit mode.
++
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 41fa9a92081..e9a1921ae26 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,8 +1,11 @@
+-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
+-MULTILIB_DIRNAMES = bs m mh le
++MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
++MULTILIB_DIRNAMES = bs m mh le m64
+ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
++MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch
deleted file mode 100644
index dfdb479cd5..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0029-Patch-microblaze-Add-new-bit-field-instructions.patch
+++ /dev/null
@@ -1,143 +0,0 @@
-From 341bf8ad4e55693d00d4d8c916f4c347e7186dd4 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:14:51 +0530
-Subject: [PATCH 29/58] [Patch, microblaze]: Add new bit-field instructions
-
-This patches adds new bsefi and bsifi instructions.
-BSEFI- The instruction shall extract a bit field from a
-register and place it right-adjusted in the destination register.
-The other bits in the destination register shall be set to zero
-BSIFI- The instruction shall insert a right-adjusted bit field
-from a register at another position in the destination register.
-The rest of the bits in the destination register shall be unchanged
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-  2016-02-03 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze.md (Update): Added new patterns
----
- gcc/config/microblaze/microblaze.h  |  2 +
- gcc/config/microblaze/microblaze.md | 73 +++++++++++++++++++++++++++++
- 2 files changed, 75 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8b0db2c1718..b5b7b22cec9 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -44,6 +44,7 @@ extern int microblaze_dbx_regno[];
- 
- extern int microblaze_no_unsafe_delay;
- extern int microblaze_has_clz;
-+extern int microblaze_has_bitfield;
- extern enum pipeline_type microblaze_pipe;
- 
- #define OBJECT_FORMAT_ELF
-@@ -62,6 +63,7 @@ extern enum pipeline_type microblaze_pipe;
- 
- /* Do we have CLZ?  */
- #define TARGET_HAS_CLZ      (TARGET_PATTERN_COMPARE && microblaze_has_clz)
-+#define TARGET_HAS_BITFIELD      (TARGET_BARREL_SHIFT && microblaze_has_bitfield)
- 
- /* The default is to support PIC.  */
- #define TARGET_SUPPORTS_PIC 1
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index c407a81c51e..fa6aabdb9d4 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -982,6 +982,8 @@
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"20,20,20")])
- 
-+
-+
- ;;----------------------------------------------------------------
- ;; Data movement
- ;;----------------------------------------------------------------
-@@ -1776,6 +1778,7 @@
-   (set_attr "length"   "28")]
- )
- 
-+
- ;;----------------------------------------------------------------
- ;; Setting a register from an integer comparison. 
- ;;----------------------------------------------------------------
-@@ -2489,4 +2492,74 @@
-   DONE;
- }")
- 
-+(define_expand "extvsi"
-+  [(set (match_operand:SI 0 "register_operand" "r")
-+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+			 (match_operand:SI 2 "immediate_operand" "I")
-+			 (match_operand:SI 3 "immediate_operand" "I")))]
-+"TARGET_HAS_BITFIELD"
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "extv_32"
-+  [(set (match_operand:SI 0 "register_operand" "=r")
-+	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-+			 (match_operand:SI 2 "immediate_operand" "I")
-+			 (match_operand:SI 3 "immediate_operand" "I")))]
-+ "TARGET_HAS_BITFIELD && (UINTVAL (operands[2]) > 0)
-+   && ((UINTVAL (operands[2]) + UINTVAL (operands[3])) <= 32)"
-+  "bsefi %0,%1,%2,%3"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
-+(define_expand "insvsi"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+			 (match_operand:SI 1 "immediate_operand" "I")
-+			 (match_operand:SI 2 "immediate_operand" "I"))
-+	(match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD"
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
-+
-+(define_insn "insv_32"
-+  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-+			 (match_operand:SI 1 "immediate_operand" "I")
-+			 (match_operand:SI 2 "immediate_operand" "I"))
-+	(match_operand:SI 3 "register_operand" "r"))]
-+ "TARGET_HAS_BITFIELD && UINTVAL (operands[1]) > 0
-+   && UINTVAL (operands[1]) + UINTVAL (operands[2]) <= 32"
-+  "bsifi %0, %3, %1, %2"
-+  [(set_attr "type" "bshift")
-+   (set_attr "length" "4")])
-+
- (include "sync.md")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch
new file mode 100644
index 0000000000..88a0d0ba10
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Intial-commit-for-64bit-MB-sources.patch
@@ -0,0 +1,2459 @@
+From 53799d63bd26a04265a55f68ca57e3462ed6eeb7 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 27 Jul 2018 15:23:41 +0530
+Subject: [PATCH 30/54] Intial commit for 64bit-MB sources. Need to cleanup the
+ code later.
+
+---
+ gcc/config/microblaze/constraints.md    |   2 +-
+ gcc/config/microblaze/microblaze-c.c    |   6 +
+ gcc/config/microblaze/microblaze.c      | 218 ++++++---
+ gcc/config/microblaze/microblaze.h      |  63 ++-
+ gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++------
+ gcc/config/microblaze/t-microblaze      |   3 +-
+ libgcc/config/microblaze/crti.S         |   4 +-
+ libgcc/config/microblaze/crtn.S         |   4 +-
+ libgcc/config/microblaze/divdi3.S       |  98 ++++
+ libgcc/config/microblaze/divdi3_table.c |  62 +++
+ libgcc/config/microblaze/moddi3.S       |  97 ++++
+ libgcc/config/microblaze/muldi3.S       |  73 +++
+ libgcc/config/microblaze/t-microblaze   |  11 +-
+ libgcc/config/microblaze/udivdi3.S      | 107 +++++
+ libgcc/config/microblaze/umoddi3.S      | 110 +++++
+ 15 files changed, 1230 insertions(+), 234 deletions(-)
+ create mode 100644 libgcc/config/microblaze/divdi3.S
+ create mode 100644 libgcc/config/microblaze/divdi3_table.c
+ create mode 100644 libgcc/config/microblaze/moddi3.S
+ create mode 100644 libgcc/config/microblaze/muldi3.S
+ create mode 100644 libgcc/config/microblaze/udivdi3.S
+ create mode 100644 libgcc/config/microblaze/umoddi3.S
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 123395717e0..b8ef1650f92 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -55,7 +55,7 @@
+ (define_constraint "K"
+   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
++       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
+ 
+ 
+ ;; Define floating point constraints
+diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
+index d8c88e510e5..dbcd21fc6ee 100644
+--- a/gcc/config/microblaze/microblaze-c.c
++++ b/gcc/config/microblaze/microblaze-c.c
+@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
+         builtin_define ("HAVE_HW_FPU_SQRT");
+       builtin_define ("__HAVE_HW_FPU_SQRT__");
+     }
++  if (TARGET_MB_64)
++    {
++      builtin_define ("__arch64__");
++      builtin_define ("__microblaze64__");
++      builtin_define ("__MICROBLAZE64__");
++    }
+ }  
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 99a1cd5c0be..3c815444574 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
+ 	{
+ 	  return 1;
+ 	}
+-      else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
++      /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
+ 	{
+ 	  return 1;
+-	}
++	}*/
+       else
+ 	return 0;
+ 
+@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode)
+     return 1;
+ 
+   return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
+-			    ? E_SImode : E_SFmode),
++			    ? Pmode : E_SFmode),
+ 			   plus_constant (Pmode, addr, 4));
+ }
+ 
+@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
+          /* Load the addend.  */
+          addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
+ 				  UNSPEC_TLS);
+-         addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
++         addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
+          dest = gen_rtx_PLUS (Pmode, dest, addend);
+          break;
+ 
+@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
+ 
+   if (XINT (x, 1) == UNSPEC_GOTOFF)
+     {
+-      info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
++      info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
+       info->type = ADDRESS_GOTOFF;
+     }
+   else if (XINT (x, 1) == UNSPEC_PLT)
+@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
+   emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
+ 
+   /* Emit the test & branch.  */
+-  emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
++
++  if (TARGET_MB_64) {
++    emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
++			     src_reg, final_src, label));
++    }
++  else {
++    emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
+ 			     src_reg, final_src, label));
++  
++    }
+ 
+   /* Mop up any left-over bytes.  */
+   if (leftover)
+@@ -1633,14 +1641,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
+       break;
+ 
+     case E_DFmode:
+-      cum->arg_words += 2;
++      if (TARGET_MB_64)
++       cum->arg_words++;
++      else
++       cum->arg_words += 2;
+       if (!cum->gp_reg_found && cum->arg_number <= 2)
+ 	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
+       break;
+ 
+     case E_DImode:
+       cum->gp_reg_found = 1;
+-      cum->arg_words += 2;
++      if (TARGET_MB_64)
++       cum->arg_words++;
++      else
++       cum->arg_words += 2;
+       break;
+ 
+     case E_QImode:
+@@ -2155,7 +2169,7 @@ compute_frame_size (HOST_WIDE_INT size)
+ 
+ 	  if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
+ 	    /* Don't account for link register. It is accounted specially below.  */
+-	    gp_reg_size += GET_MODE_SIZE (SImode);
++	    gp_reg_size += GET_MODE_SIZE (Pmode);
+ 
+ 	  mask |= (1L << (regno - GP_REG_FIRST));
+ 	}
+@@ -2424,7 +2438,7 @@ print_operand (FILE * file, rtx op, int letter)
+ 
+       if ((letter == 'M' && !WORDS_BIG_ENDIAN)
+ 	  || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
+-	regnum++;
++	regnum++; 
+ 
+       fprintf (file, "%s", reg_names[regnum]);
+     }
+@@ -2450,6 +2464,7 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
++      int val1[2];
+       long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+@@ -2462,12 +2477,12 @@ print_operand (FILE * file, rtx op, int letter)
+ 	      val[0] = l[WORDS_BIG_ENDIAN != 0];
+ 	    }
+ 	}
+-      else if (code == CONST_INT)
++      else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
+         {
+-	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+-	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
++	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
++	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
+         }
+-      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
++      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
+     }
+   else if (code == CONST_DOUBLE)
+     {
+@@ -2661,7 +2676,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
+ 
+     switch_to_section (get_section (section, 0, NULL));
+     assemble_align (POINTER_SIZE);
+-    fputs ("\t.word\t", asm_out_file);
++    if (TARGET_MB_64)
++      fputs ("\t.dword\t", asm_out_file);
++    else
++      fputs ("\t.word\t", asm_out_file);
+     output_addr_const (asm_out_file, symbol);
+     fputs ("\n", asm_out_file);
+ }
+@@ -2684,7 +2702,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
+ 
+     switch_to_section (get_section (section, 0, NULL));
+     assemble_align (POINTER_SIZE);
+-    fputs ("\t.word\t", asm_out_file);
++    if (TARGET_MB_64)
++      fputs ("\t.dword\t", asm_out_file);
++    else
++     fputs ("\t.word\t", asm_out_file);
+     output_addr_const (asm_out_file, symbol);
+     fputs ("\n", asm_out_file);
+ }
+@@ -2750,7 +2771,7 @@ save_restore_insns (int prologue)
+   /* For interrupt_handlers, need to save/restore the MSR.  */
+   if (microblaze_is_interrupt_variant ())
+     {
+-      isr_mem_rtx = gen_rtx_MEM (SImode,
++      isr_mem_rtx = gen_rtx_MEM (Pmode,
+ 				 gen_rtx_PLUS (Pmode, base_reg_rtx,
+ 					       GEN_INT (current_frame_info.
+ 							gp_offset -
+@@ -2758,8 +2779,8 @@ save_restore_insns (int prologue)
+ 
+       /* Do not optimize in flow analysis.  */
+       MEM_VOLATILE_P (isr_mem_rtx) = 1;
+-      isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
+-      isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
++      isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
++      isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
+     }
+ 
+   if (microblaze_is_interrupt_variant () && !prologue)
+@@ -2767,8 +2788,8 @@ save_restore_insns (int prologue)
+       emit_move_insn (isr_reg_rtx, isr_mem_rtx);
+       emit_move_insn (isr_msr_rtx, isr_reg_rtx);
+       /* Do not optimize in flow analysis.  */
+-      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
+-      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
+     }
+ 
+   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
+@@ -2779,9 +2800,9 @@ save_restore_insns (int prologue)
+ 	    /* Don't handle here. Already handled as the first register.  */
+ 	    continue;
+ 
+-	  reg_rtx = gen_rtx_REG (SImode, regno);
++	  reg_rtx = gen_rtx_REG (Pmode, regno);
+ 	  insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
+-	  mem_rtx = gen_rtx_MEM (SImode, insn);
++	  mem_rtx = gen_rtx_MEM (Pmode, insn);
+ 	  if (microblaze_is_interrupt_variant () || save_volatiles)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+@@ -2796,7 +2817,7 @@ save_restore_insns (int prologue)
+ 	      insn = emit_move_insn (reg_rtx, mem_rtx);
+ 	    }
+ 
+-	  gp_offset += GET_MODE_SIZE (SImode);
++	  gp_offset += GET_MODE_SIZE (Pmode);
+ 	}
+     }
+ 
+@@ -2806,8 +2827,8 @@ save_restore_insns (int prologue)
+       emit_move_insn (isr_mem_rtx, isr_reg_rtx);
+ 
+       /* Do not optimize in flow analysis.  */
+-      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
+-      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
++      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
+     }
+ 
+   /* Done saving and restoring */
+@@ -2897,7 +2918,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
+ 
+   switch_to_section (s);
+   assemble_align (POINTER_SIZE);
+-  fputs ("\t.word\t", asm_out_file);
++  if (TARGET_MB_64)
++    fputs ("\t.dword\t", asm_out_file);
++  else
++    fputs ("\t.word\t", asm_out_file);
+   output_addr_const (asm_out_file, symbol);
+   fputs ("\n", asm_out_file);
+ }
+@@ -3041,10 +3065,10 @@ microblaze_expand_prologue (void)
+ 	{
+ 	  if (offset != 0)
+ 	    ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
+-	  emit_move_insn (gen_rtx_MEM (SImode, ptr),
+-			  gen_rtx_REG (SImode, regno));
++	  emit_move_insn (gen_rtx_MEM (Pmode, ptr),
++			  gen_rtx_REG (Pmode, regno));
+ 
+-	  offset += GET_MODE_SIZE (SImode);
++	  offset += GET_MODE_SIZE (Pmode);
+ 	}
+     }
+ 
+@@ -3053,15 +3077,23 @@ microblaze_expand_prologue (void)
+       rtx fsiz_rtx = GEN_INT (fsiz);
+ 
+       rtx_insn *insn = NULL;
+-      insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
++         if (TARGET_MB_64)
++           {
++              
++             insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
+ 				    fsiz_rtx));
++           }
++         else { 
++             insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
++				    fsiz_rtx));
++           }
+       if (insn)
+ 	RTX_FRAME_RELATED_P (insn) = 1;
+ 
+       /* Handle SUB_RETURN_ADDR_REGNUM specially at first.  */
+       if (!crtl->is_leaf || interrupt_handler)
+ 	{
+-	  mem_rtx = gen_rtx_MEM (SImode,
++	  mem_rtx = gen_rtx_MEM (Pmode,
+ 				 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+ 					       const0_rtx));
+ 
+@@ -3069,7 +3101,7 @@ microblaze_expand_prologue (void)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+ 
+-	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
++	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ 	  insn = emit_move_insn (mem_rtx, reg_rtx);
+ 	  RTX_FRAME_RELATED_P (insn) = 1;
+ 	}
+@@ -3179,12 +3211,12 @@ microblaze_expand_epilogue (void)
+       if (!crtl->is_leaf || interrupt_handler)
+ 	{
+ 	  mem_rtx =
+-	    gen_rtx_MEM (SImode,
++	    gen_rtx_MEM (Pmode,
+ 			 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
+ 	  if (interrupt_handler)
+ 	    /* Do not optimize in flow analysis.  */
+ 	    MEM_VOLATILE_P (mem_rtx) = 1;
+-	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
++	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
+ 	  emit_move_insn (reg_rtx, mem_rtx);
+ 	}
+ 
+@@ -3200,15 +3232,25 @@ microblaze_expand_epilogue (void)
+       /* _restore_ registers for epilogue.  */
+       save_restore_insns (0);
+       emit_insn (gen_blockage ());
+-      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
++      if (TARGET_MB_64)
++        emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
++      else
++        emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
+     }
+ 
+   if (crtl->calls_eh_return)
+-    emit_insn (gen_addsi3 (stack_pointer_rtx,
++      if (TARGET_MB_64) {
++          emit_insn (gen_adddi3 (stack_pointer_rtx,
+                            stack_pointer_rtx,
+-                           gen_raw_REG (SImode,
++                           gen_raw_REG (Pmode,
+ 					MB_EH_STACKADJ_REGNUM)));
+-
++        }
++      else {
++          emit_insn (gen_addsi3 (stack_pointer_rtx,
++                           stack_pointer_rtx,
++                           gen_raw_REG (Pmode,
++					MB_EH_STACKADJ_REGNUM)));
++        }
+   emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
+ 						    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ }
+@@ -3375,9 +3417,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+   else
+     this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
+ 
+-  /* Apply the constant offset, if required.  */
++  /* Apply the constant offset, if required. */ 
+   if (delta)
+-    emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
++    {
++      if (TARGET_MB_64)
++        emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); 
++      else
++        emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
++    } 
+ 
+   /* Apply the offset from the vtable, if required.  */
+   if (vcall_offset)
+@@ -3390,7 +3437,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+     rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
+     emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
+ 
+-    emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
++    if (TARGET_MB_64)
++      emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
++    else
++      emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
+   }
+ 
+   /* Generate a tail call to the target function.  */
+@@ -3566,7 +3616,7 @@ microblaze_eh_return (rtx op0)
+ /* Queue an .ident string in the queue of top-level asm statements.
+    If the string size is below the threshold, put it into .sdata2.
+    If the front-end is done, we must be being called from toplev.c.
+-   In that case, do nothing.  */
++   In that case, do nothing. */ 
+ void 
+ microblaze_asm_output_ident (const char *string)
+ {
+@@ -3621,9 +3671,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
+   emit_block_move (m_tramp, assemble_trampoline_template (),
+ 		   GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
+ 
+-  mem = adjust_address (m_tramp, SImode, 16);
++  mem = adjust_address (m_tramp, Pmode, 16);
+   emit_move_insn (mem, chain_value);
+-  mem = adjust_address (m_tramp, SImode, 20);
++  mem = adjust_address (m_tramp, Pmode, 20);
+   emit_move_insn (mem, fnaddr);
+ }
+ 
+@@ -3647,7 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
++      if (mode == Pmode)
+         emit_jump_insn (gen_condjump (condition, label1));
+       else
+         emit_jump_insn (gen_long_condjump (condition, label1));
+@@ -3766,7 +3816,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
+   rtx comp_reg = gen_reg_rtx (SImode);
+ 
+   emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+-  condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+   emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
+@@ -3776,10 +3826,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+   rtx condition;
+   rtx cmp_op0 = XEXP (operands[0], 0);
+   rtx cmp_op1 = XEXP (operands[0], 1);
+-  rtx comp_reg = gen_reg_rtx (DImode);
++  rtx comp_reg = gen_reg_rtx (Pmode);
+ 
+   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+-  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
++  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+   emit_jump_insn (gen_long_condjump (condition, operands[3]));
+ }
+ 
+@@ -3800,8 +3850,8 @@ microblaze_expand_divide (rtx operands[])
+ {
+   /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
+ 
+-  rtx regt1 = gen_reg_rtx (SImode); 
+-  rtx reg18 = gen_rtx_REG (SImode, R_TMP);
++  rtx regt1 = gen_reg_rtx (Pmode); 
++  rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
+   rtx regqi = gen_reg_rtx (QImode);
+   rtx_code_label *div_label = gen_label_rtx ();
+   rtx_code_label *div_end_label = gen_label_rtx ();
+@@ -3809,17 +3859,31 @@ microblaze_expand_divide (rtx operands[])
+   rtx mem_rtx;
+   rtx ret;
+   rtx_insn *jump, *cjump, *insn;
+-
+-  insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
+-  cjump = emit_jump_insn_after (gen_cbranchsi4 (
+-					gen_rtx_GTU (SImode, regt1, GEN_INT (15)), 
++ 
++  if (TARGET_MB_64) {
++      insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
++      cjump = emit_jump_insn_after (gen_cbranchdi4 (
++					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
++					regt1, GEN_INT (15), div_label), insn);
++    }
++  else {
++      insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
++      cjump = emit_jump_insn_after (gen_cbranchsi4 (
++					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
+ 					regt1, GEN_INT (15), div_label), insn);
++    }
+   LABEL_NUSES (div_label) = 1; 
+   JUMP_LABEL (cjump) = div_label;
+-  emit_insn (gen_rtx_CLOBBER (SImode, reg18));
++  emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+-  emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
+-  emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
++  if (TARGET_MB_64) {
++      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
++    }
++  else  {
++      emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
++    }
+   mem_rtx = gen_rtx_MEM (QImode,
+                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+@@ -3966,7 +4030,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+               {
+                 insn =
+                   emit_insn_before (gen_iprefetch
+-                                    (gen_int_mode (addr_offset, SImode)),
++                                    (gen_int_mode (addr_offset, Pmode)),
+                                     before_4);
+                 recog_memoized (insn);
+                 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
+@@ -3976,7 +4040,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
+            }
+        }
+ }
+-
++  
++/* Set the names for various arithmetic operations according to the
++ *    MICROBLAZE ABI.  */
++static void
++microblaze_init_libfuncs (void)
++{ 
++  set_optab_libfunc (smod_optab,     SImode, "__modsi3");
++  set_optab_libfunc (sdiv_optab,     SImode, "__divsi3");
++  set_optab_libfunc (smul_optab,     SImode, "__mulsi3");
++  set_optab_libfunc (umod_optab,     SImode, "__umodsi3");
++  set_optab_libfunc (udiv_optab,     SImode, "__udivsi3");
++  
++  if (TARGET_MB_64)
++    {
++      set_optab_libfunc (smod_optab,     DImode, "__moddi3");
++      set_optab_libfunc (sdiv_optab,     DImode, "__divdi3");
++      set_optab_libfunc (smul_optab,     DImode, "__muldi3");
++      set_optab_libfunc (umod_optab,     DImode, "__umoddi3");
++      set_optab_libfunc (udiv_optab,     DImode, "__udivdi3");
++    }
++}       
+ /* Insert instruction prefetch instruction at the fall
+    through path of the function call.  */
+ 
+@@ -4129,6 +4213,17 @@ microblaze_starting_frame_offset (void)
+ #undef TARGET_LRA_P
+ #define TARGET_LRA_P hook_bool_void_false
+ 
++#ifdef TARGET_MB_64
++#undef TARGET_ASM_ALIGNED_DI_OP
++#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
++
++#undef TARGET_ASM_ALIGNED_HI_OP
++#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
++
++#undef TARGET_ASM_ALIGNED_SI_OP
++#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
++#endif
++
+ #undef TARGET_FRAME_POINTER_REQUIRED
+ #define TARGET_FRAME_POINTER_REQUIRED	microblaze_frame_pointer_required
+ 
+@@ -4138,6 +4233,9 @@ microblaze_starting_frame_offset (void)
+ #undef  TARGET_TRAMPOLINE_INIT
+ #define TARGET_TRAMPOLINE_INIT		microblaze_trampoline_init
+ 
++#undef TARGET_INIT_LIBFUNCS
++#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
++
+ #undef  TARGET_PROMOTE_FUNCTION_MODE
+ #define TARGET_PROMOTE_FUNCTION_MODE 	default_promote_function_mode_always_promote
+ 
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index c0358603380..f6ad4d9fc21 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
+ 
+ /* Generate DWARF exception handling info.  */
+ #define DWARF2_UNWIND_INFO 1
+-
+ /* Don't generate .loc operations.  */
+ #define DWARF2_ASM_LINE_DEBUG_INFO 0
+ 
+@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
+   ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
+ 
+ /* Use DWARF 2 debugging information by default.  */
+-#define DWARF2_DEBUGGING_INFO
++#define DWARF2_DEBUGGING_INFO 1
+ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
++#define DWARF2_ADDR_SIZE 4
+ 
+ /* Target machine storage layout */
+ 
+ #define BITS_BIG_ENDIAN 0
+ #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
+ #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
+-#define BITS_PER_WORD           32
+-#define UNITS_PER_WORD          4
++//#define BITS_PER_WORD           64
++//Revisit
++#define MAX_BITS_PER_WORD	64
++#define UNITS_PER_WORD          (TARGET_MB_64 ? 8 : 4)
++//#define MIN_UNITS_PER_WORD      (TARGET_MB_64 ? 8 : 4)
++//#define UNITS_PER_WORD          4
+ #define MIN_UNITS_PER_WORD      4
+ #define INT_TYPE_SIZE           32
+ #define SHORT_TYPE_SIZE         16
+-#define LONG_TYPE_SIZE          64
++#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
+ #define LONG_LONG_TYPE_SIZE     64
+ #define FLOAT_TYPE_SIZE         32
+ #define DOUBLE_TYPE_SIZE        64
+ #define LONG_DOUBLE_TYPE_SIZE   64
+-#define POINTER_SIZE            32
+-#define PARM_BOUNDARY           32
+-#define FUNCTION_BOUNDARY       32
+-#define EMPTY_FIELD_BOUNDARY    32
++#define POINTER_SIZE            (TARGET_MB_64 ? 64 : 32)
++//#define WIDEST_HARDWARE_FP_SIZE 64
++//#define POINTERS_EXTEND_UNSIGNED 1
++#define PARM_BOUNDARY           (TARGET_MB_64 ? 64 : 32)
++#define FUNCTION_BOUNDARY       (TARGET_MB_64 ? 64 : 32)
++#define EMPTY_FIELD_BOUNDARY    (TARGET_MB_64 ? 64 : 32)
+ #define STRUCTURE_SIZE_BOUNDARY 8
+-#define BIGGEST_ALIGNMENT       32
++#define BIGGEST_ALIGNMENT       (TARGET_MB_64 ? 64 : 32) 
+ #define STRICT_ALIGNMENT        1
+ #define PCC_BITFIELD_TYPE_MATTERS 1
+ 
++//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
+ #undef SIZE_TYPE
+-#define SIZE_TYPE "unsigned int"
++#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
+ 
+ #undef PTRDIFF_TYPE
+-#define PTRDIFF_TYPE "int"
++#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
++
++/*#undef INTPTR_TYPE
++#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
++#undef UINTPTR_TYPE
++#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
+ 
+ #define DATA_ALIGNMENT(TYPE, ALIGN)					\
+   ((((ALIGN) < BITS_PER_WORD)						\
+@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
+ #define WORD_REGISTER_OPERATIONS 1
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+-
++/*
+ #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+   if (GET_MODE_CLASS (MODE) == MODE_INT		\
+-      && GET_MODE_SIZE (MODE) < 4)		\
+-    (MODE) = SImode;
+-
++      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
++    (MODE) = TARGET_MB_64 ? DImode : SImode;
++*/
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
+ #define FIRST_PARM_OFFSET(FNDECL)		(UNITS_PER_WORD)
+ 
+ #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
++#define DWARF_CIE_DATA_ALIGNMENT -1
+ 
+ #define REG_PARM_STACK_SPACE(FNDECL)  		(MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
+ 
+ #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)	1
+ 
+-#define STACK_BOUNDARY				32
++#define STACK_BOUNDARY				(TARGET_MB_64 ? 64 : 32)
+ 
++#define PREFERRED_STACK_BOUNDARY		(TARGET_MB_64 ? 64 : 32)
++ 
+ #define NUM_OF_ARGS				6
+ 
+ #define GP_RETURN				(GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
+@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
+ #define LIBCALL_VALUE(MODE)						\
++  gen_rtx_REG (MODE,GP_RETURN)
++								
++/*#define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (								\
+ 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+ 	     || GET_MODE_SIZE (MODE) >= 4)				\
+ 	    ? (MODE)							\
+ 	    : SImode), GP_RETURN)
+-
++*/
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+@@ -500,7 +518,7 @@ typedef struct microblaze_args
+ /* 4 insns + 2 words of data.  */
+ #define TRAMPOLINE_SIZE				(6 * 4)
+ 
+-#define TRAMPOLINE_ALIGNMENT			32
++#define TRAMPOLINE_ALIGNMENT			64
+ 
+ #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
+ 
+@@ -529,13 +547,13 @@ typedef struct microblaze_args
+    addresses which require two reload registers.  */
+ #define LEGITIMATE_PIC_OPERAND_P(X)  microblaze_legitimate_pic_operand (X)
+ 
+-#define CASE_VECTOR_MODE			(SImode)
++#define CASE_VECTOR_MODE			(TARGET_MB_64? DImode:SImode)
+ 
+ #ifndef DEFAULT_SIGNED_CHAR
+ #define DEFAULT_SIGNED_CHAR			1
+ #endif
+ 
+-#define MOVE_MAX				4
++#define MOVE_MAX				(TARGET_MB_64 ? 8 : 4)
+ #define MAX_MOVE_MAX				8
+ 
+ #define SLOW_BYTE_ACCESS			1
+@@ -545,7 +563,7 @@ typedef struct microblaze_args
+ 
+ #define SHIFT_COUNT_TRUNCATED			1
+ 
+-#define Pmode SImode
++#define Pmode (TARGET_MB_64? DImode:SImode)
+ 
+ #define FUNCTION_MODE   SImode
+ 
+@@ -707,6 +725,7 @@ do {									\
+ 
+ #undef TARGET_ASM_OUTPUT_IDENT
+ #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
++//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
+ 
+ /* Default to -G 8 */
+ #ifndef MICROBLAZE_DEFAULT_GVALUE
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 4d8429d9a90..33a8b12ef3b 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -26,6 +26,7 @@
+ ;; Constants
+ ;;----------------------------------------------------
+ (define_constants [
++  (R_Z         0)       ;; For reg r0
+   (R_SP        1)       ;; Stack pointer reg
+   (R_SR       15)       ;; Sub-routine return addr reg
+   (R_IR       14)       ;; Interrupt return addr reg
+@@ -541,6 +542,7 @@
+ 
+ ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
+ ;; Leave carry as is
++
+ (define_insn "addsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
+ 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
+@@ -562,23 +564,38 @@
+ 
+ ;; Adding 2 DI operands in register or reg/imm
+ 
+-(define_insn "adddi3_long"
++(define_expand "adddi3"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(plus:DI (match_operand:DI 1 "register_operand" "")
++		 (match_operand:DI 2 "arith_plus_operand" "")))]
++""
++{
++  if (TARGET_MB_64) 
++   {
++     if (GET_CODE (operands[2]) == CONST_INT &&
++       INTVAL(operands[2]) < (long)-549755813888 &&
++	INTVAL(operands[2]) > (long)549755813887)
++      FAIL;
++   }
++})
++
++(define_insn "*adddi3_long"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
++	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+ 		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
+   "TARGET_MB_64"
+   "@
+-   addlk\t%0,%z1,%2
+-   addlik\t%0,%z1,%2"
+-  [(set_attr "type"	"arith,arith")
+-  (set_attr "mode"	"DI,DI")
++   addlk\t%0,%1,%2
++   addlik\t%0,%1,%2 #N10"
++  [(set_attr "type"	"darith,no_delay_arith")
++  (set_attr "mode"	"DI")
+   (set_attr "length"	"4,4")])
+ 
+-(define_insn "adddi3"
++(define_insn "*adddi3_all"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+ 		 (match_operand:DI 2 "arith_operand" "d,i")))]
+-  ""
++  "!TARGET_MB_64"
+   "@
+   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
+   addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
+@@ -605,7 +622,7 @@
+ (define_insn "iprefetch"
+   [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
+    (clobber (mem:BLK (scratch)))]
+-   "TARGET_PREFETCH"
++   "TARGET_PREFETCH && !TARGET_MB_64"
+   {
+     operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+     return "mfs\t%2,rpc\n\twic\t%2,r0";
+@@ -618,23 +635,33 @@
+ ;; Double Precision Subtraction
+ ;;----------------------------------------------------------------
+ 
+-(define_insn "subdi3_long"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
+-		  (match_operand:DI 2 "register_operand" "d,n")))]
++(define_expand "subdi3"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(minus:DI (match_operand:DI 1 "register_operand" "")
++		  (match_operand:DI 2 "arith_operand" "")))]
++""
++"
++{
++}")
++
++(define_insn "subsidi3"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
++		  (match_operand:DI 2 "arith_operand" "d,K,n")))]
+   "TARGET_MB_64"
+   "@
+    rsubl\t%0,%2,%1
+-   addlik\t%0,%z1,-%2"
+-  [(set_attr "type"	"darith")
+-  (set_attr "mode"	"DI,DI")
+-  (set_attr "length"	"4,4")])
++   addik\t%0,%z1,-%2
++   addik\t%0,%z1,-%2"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,4")])
+ 
+-(define_insn "subdi3"
++(define_insn "subdi3_small"
+   [(set (match_operand:DI 0 "register_operand" "=&d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d")
+ 		  (match_operand:DI 2 "register_operand" "d")))]
+-  ""
++  "!TARGET_MB_64"
+   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
+   [(set_attr "type"	"darith")
+   (set_attr "mode"	"DI")
+@@ -663,7 +690,7 @@
+         (mult:DI
+          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -674,7 +701,7 @@
+         (mult:DI
+          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -685,7 +712,7 @@
+         (mult:DI
+          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
+          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
+-  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
++  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
+   "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
+   [(set_attr "type"     "no_delay_arith")
+    (set_attr "mode"     "DI")
+@@ -789,7 +816,7 @@
+                         (match_operand:SI 4 "arith_operand")])
+                       (label_ref (match_operand 5))
+                       (pc)))]
+-   "TARGET_HARD_FLOAT"
++   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+    [(set (match_dup 1) (match_dup 3))]
+ 
+   {
+@@ -819,6 +846,15 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "negsi_long"
++  [(set (match_operand:SI 0 "register_operand" "=d")
++	(neg:SI (match_operand:DI 1 "register_operand" "d")))]
++  ""
++  "rsubk\t%0,%1,r0"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"SI")
++  (set_attr "length"	"4")])
++
+ (define_insn "negdi2_long"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
+@@ -847,16 +883,24 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_insn "one_cmpldi2_long"
++(define_expand "one_cmpldi2"
++  [(set (match_operand:DI 0 "register_operand" "")
++	(not:DI (match_operand:DI 1 "register_operand" "")))]
++  ""
++  "
++{
++}")
++
++(define_insn ""
+   [(set (match_operand:DI 0 "register_operand" "=d")
+-	(not:DI (match_operand:DI 1 "register_operand" "d")))]
++	(not:DI (match_operand:DI 1 "arith_operand" "d")))]
+   "TARGET_MB_64"
+   "xorli\t%0,%1,-1"
+-  [(set_attr "type"	"arith")
++  [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
+-(define_insn "*one_cmpldi2"
++(define_insn ""
+   [(set (match_operand:DI 0 "register_operand" "=d")
+ 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
+   ""
+@@ -871,7 +915,8 @@
+ 	(not:DI (match_operand:DI 1 "register_operand" "")))]
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
++   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
++   && !TARGET_MB_64"
+ 
+   [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
+   (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
+@@ -883,18 +928,17 @@
+ ;;----------------------------------------------------------------
+ 
+ (define_insn "anddi3"
+-  [(set (match_operand:DI 0 "register_operand" "=d,d")
+-	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
+-		(match_operand:DI 2 "arith_operand" "d,K")))]
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
++		(match_operand:DI 2 "arith_operand" "d,K,I")))]
+   "TARGET_MB_64"
+   "@
+    andl\t%0,%1,%2
+-   andli\t%0,%1,%2 #andl1"
+-  ;; andli\t%0,%1,%2 #andl3
+-  ;; andli\t%0,%1,%2 #andl2
+-  [(set_attr "type"	"arith,arith")
+-  (set_attr "mode"	"DI,DI")
+-  (set_attr "length"	"4,4")])
++   andli\t%0,%1,%2 #andl2
++   andli\t%0,%1,%2 #andl3"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI,DI,DI")
++  (set_attr "length"	"4,4,4")])
+ 
+ (define_insn "andsi3"
+   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
+@@ -919,7 +963,7 @@
+   "@
+    orl\t%0,%1,%2
+    orli\t%0,%1,%2 #andl1"
+-  [(set_attr "type"	"arith,arith")
++  [(set_attr "type"	"arith,no_delay_arith")
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")])
+ 
+@@ -945,7 +989,7 @@
+   "@
+    xorl\t%0,%1,%2
+    xorli\t%0,%1,%2 #andl1"
+-  [(set_attr "type"	"arith,arith")
++  [(set_attr "type"	"arith,no_delay_arith")
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")])
+ 
+@@ -1018,26 +1062,6 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-;;(define_expand "extendqidi2"
+-;;  [(set (match_operand:DI 0 "register_operand" "=d")
+-;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
+-;;  "TARGET_MB_64"
+-;;  {
+-;;	if (GET_CODE (operands[1]) != REG)
+-;;	FAIL;
+-;;   }
+-;;)
+-    
+-
+-;;(define_insn "extendqidi2"
+-;;  [(set (match_operand:DI 0 "register_operand" "=d")
+-;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
+-;;  "TARGET_MB_64"
+-;;  "sextl8\t%0,%1"
+-;;  [(set_attr "type"	"arith")
+-;;  (set_attr "mode"	"DI")
+-;;  (set_attr "length"	"4")])
+-
+ (define_insn "extendhisi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
+@@ -1060,6 +1084,27 @@
+ ;; Those for integer source operand are ordered
+ ;; widest source type first.
+ 
++(define_insn "extendsidi2_long"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
++	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
++  "TARGET_MB_64"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "sextl32\t%0,%1";
++      case 1:
++      case 2:
++        {
++          output_asm_insn ("ll%i1\t%0,%1", operands);
++          return "sextl32\t%0,%0";
++        }
++    } 
++  }
++  [(set_attr "type"	"multi,multi,multi")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,8,8")])
++
+ (define_insn "extendsidi2"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
+@@ -1090,69 +1135,118 @@
+ ;; Unlike most other insns, the move insns can't be split with
+ ;; different predicates, because register spilling and other parts of
+ ;; the compiler, have memoized the insn number already.
++;;    //}
+ 
+ (define_expand "movdi"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "")
+ 	(match_operand:DI 1 "general_operand" ""))]
+   ""
+   {
+-    /* If operands[1] is a constant address illegal for pic, then we need to
+-       handle it just like microblaze_legitimize_address does.  */
+-    if (flag_pic && pic_address_needs_scratch (operands[1]))
++    if (TARGET_MB_64)
++    {
++      if (microblaze_expand_move (DImode, operands)) DONE;
++    }
++    else
+     {
++      /* If operands[1] is a constant address illegal for pic, then we need to
++         handle it just like microblaze_legitimize_address does. */ 
++      if (flag_pic && pic_address_needs_scratch (operands[1]))
++      {
+         rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
+         rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
+         emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
+         DONE;
+-    }
+-
+-
+-    if ((reload_in_progress | reload_completed) == 0
+-        && !register_operand (operands[0], DImode)
+-        && !register_operand (operands[1], DImode)
+-        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+-	       && operands[1] != CONST0_RTX (DImode))))
+-    {
++      }
+ 
+-      rtx temp = force_reg (DImode, operands[1]);
+-      emit_move_insn (operands[0], temp);
+-      DONE;
++      if ((reload_in_progress | reload_completed) == 0
++          && !register_operand (operands[0], DImode)
++          && !register_operand (operands[1], DImode)
++          && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
++  	       && operands[1] != CONST0_RTX (DImode))))
++      {
++        rtx temp = force_reg (DImode, operands[1]);
++        emit_move_insn (operands[0], temp);
++        DONE;
++      }
+     }
+   }
+ )
+ 
++;; Added for status registers
++(define_insn "movdi_status"
++  [(set (match_operand:DI 0 "register_operand" "=d,d,z")
++        (match_operand:DI 1 "register_operand" "z,d,d"))]
++  "microblaze_is_interrupt_variant () && TARGET_MB_64"
++  "@
++	mfs\t%0,%1  #mfs
++	addlk\t%0,%1,r0 #add movdi
++	mts\t%0,%1  #mts"	
++  [(set_attr "type" "move")
++  (set_attr "mode" "DI")
++  (set_attr "length" "12")])
+ 
+-(define_insn "*movdi_internal_64"
+-  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+-	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
+-  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
++;; This move will be not be moved to delay slot.	
++(define_insn "*movdi_internal3"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
++	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
++  "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
++           (GET_CODE (operands[1]) == CONST_INT && 
++                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
++  "@
++   addlk\t%0,r0,r0\t
++   addlik\t%0,r0,%1\t #N1 %X1
++   addlik\t%0,r0,%1\t #N2 %X1"
++  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++;; This move may be used for PLT label operand
++(define_insn "*movdi_internal5_pltop"
++  [(set (match_operand:DI 0 "register_operand" "=d,d")
++	(match_operand:DI 1 "call_insn_operand" ""))]
++  "TARGET_MB_64 && (register_operand (operands[0], Pmode) && 
++           PLT_ADDR_P (operands[1]))"
++  { 
++     gcc_unreachable ();
++  }
++  [(set_attr "type"	"load")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")])
++
++(define_insn "*movdi_internal2"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64"
+   { 
+     switch (which_alternative)
+     {
+       case 0:
+-        return "addlk\t%0,%1";
+-      case 1:
+-	return "addlik\t%0,r0,%1";
+-      case 2:
+-	  return "addlk\t%0,r0,r0";
+-      case 3:
+-      case 4:
+-	  return "lli\t%0,%1";
+-      case 5:
+-      case 6:
+-        return "sli\t%1,%0";
+-    }
+-    return "unreachable";
+-  }
+-  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT && 
++	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
++ 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else	
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
+   (set_attr "mode"	"DI")
+-  (set_attr "length"   "8,8,8,8,12,8,12")])
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ 
+ 
+ (define_insn "*movdi_internal"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
+ 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
+-  ""
++  "!TARGET_MB_64"
+   { 
+     switch (which_alternative)
+     {
+@@ -1184,7 +1278,8 @@
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
+-   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
++   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
++   && !(TARGET_MB_64)"
+ 
+   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
+   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
+@@ -1196,12 +1291,22 @@
+   "reload_completed 
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
+-   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
++   && !(TARGET_MB_64)"
+ 
+   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
+   "")
+ 
++(define_insn "movdi_long_int"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
++	(match_operand:DI 1 "general_operand"      "i"))]
++  ""
++  "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++  [(set_attr "type"	"no_delay_arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"12")])
++
+ ;; Unlike most other insns, the move insns can't be split with
+ ;; different predicates, because register spilling and other parts of
+ ;; the compiler, have memoized the insn number already.
+@@ -1273,6 +1378,8 @@
+   (set_attr "length"	"4,4,8,4,8,4,8")])
+ 
+ 
++
++
+ ;; 16-bit Integer moves
+ 
+ ;; Unlike most other insns, the move insns can't be split with
+@@ -1305,8 +1412,8 @@
+   "@
+    addik\t%0,r0,%1\t# %X1
+    addk\t%0,%1,r0
+-   lhui\t%0,%1
+-   lhui\t%0,%1
++   lhu%i1\t%0,%1
++   lhu%i1\t%0,%1
+    sh%i0\t%z1,%0
+    sh%i0\t%z1,%0"
+   [(set_attr "type"	"arith,move,load,no_delay_load,store,no_delay_store")
+@@ -1349,7 +1456,7 @@
+    lbu%i1\t%0,%1
+    lbu%i1\t%0,%1
+    sb%i0\t%z1,%0
+-   sbi\t%z1,%0"
++   sb%i0\t%z1,%0"
+   [(set_attr "type"	"arith,arith,move,load,no_delay_load,store,no_delay_store")
+   (set_attr "mode"	"QI")
+   (set_attr "length"	"4,4,8,4,8,4,8")])
+@@ -1422,7 +1529,7 @@
+    addik\t%0,r0,%F1
+    lw%i1\t%0,%1
+    sw%i0\t%z1,%0
+-   swi\t%z1,%0"
++   sw%i0\t%z1,%0"
+   [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4,4,4,4,4,4,4")])
+@@ -1461,6 +1568,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
+         (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
+@@ -1495,7 +1629,8 @@
+   "reload_completed
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+-   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
++   && !TARGET_MB_64"
+   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
+   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
+   "")
+@@ -1506,7 +1641,8 @@
+   "reload_completed
+    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
+    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+-   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
++   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
++   && !TARGET_MB_64"
+   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
+   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
+   "")
+@@ -2006,6 +2142,31 @@ else
+   "
+ )
+ 
++
++(define_insn "seq_internal_pat_long" 
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(eq:DI 
++	       (match_operand:DI 1 "register_operand" "d")
++	       (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "pcmpleq\t%0,%1,%2"
++  [(set_attr "type"	"arith")
++   (set_attr "mode"	"DI")
++   (set_attr "length"	"4")]
++)              
++
++(define_insn "sne_internal_pat_long" 
++  [(set (match_operand:DI 0 "register_operand" "=d")
++	(ne:DI 
++	       (match_operand:DI 1 "register_operand" "d")
++	       (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "pcmplne\t%0,%1,%2"
++  [(set_attr "type"	"arith")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4")]
++)              
++
+ (define_insn "seq_internal_pat" 
+   [(set (match_operand:SI 0 "register_operand" "=d")
+ 	(eq:SI 
+@@ -2066,8 +2227,8 @@ else
+ (define_expand "cbranchsi4"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand:SI 1 "register_operand")
+-                        (match_operand:SI 2 "arith_operand" "I,i")])
++                       [(match_operand 1 "register_operand")
++                        (match_operand 2 "arith_operand" "I,i")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+@@ -2079,13 +2240,13 @@ else
+ (define_expand "cbranchsi4_reg"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand:SI 1 "register_operand")
+-                        (match_operand:SI 2 "register_operand")])
++                       [(match_operand 1 "register_operand")
++                        (match_operand 2 "register_operand")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+ {
+-  microblaze_expand_conditional_branch_reg (SImode, operands);
++  microblaze_expand_conditional_branch_reg (Pmode, operands);
+   DONE;
+ })
+ 
+@@ -2110,6 +2271,26 @@ else
+ 		      (label_ref (match_operand 1))
+ 		      (pc)))])
+ 
++(define_insn "branch_zero64"
++  [(set (pc)
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
++  				 [(match_operand 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "bea%C0i%?\t%z1,%2";
++    else 
++      return "bea%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
+ (define_insn "branch_zero"
+   [(set (pc)
+ 	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
+@@ -2130,6 +2311,47 @@ else
+    (set_attr "length"	"4")]
+ )
+ 
++(define_insn "branch_compare64"
++  [(set (pc)
++        (if_then_else (match_operator 0 "cmp_op"
++                                         [(match_operand 1 "register_operand" "d")
++                                          (match_operand 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:SI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmp\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmp\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
++    return "bea%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ (define_insn "branch_compare"
+   [(set (pc)
+         (if_then_else (match_operator:SI 0 "cmp_op"
+@@ -2313,7 +2535,7 @@ else
+ ;; Indirect jumps. Jump to register values. Assuming absolute jumps
+ 
+ (define_insn "indirect_jump_internal1"
+-  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
++  [(set (pc) (match_operand 0 "register_operand" "d"))]
+   ""
+   "bra%?\t%0"
+   [(set_attr "type"	"jump")
+@@ -2326,7 +2548,7 @@ else
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   {
+-    gcc_assert (GET_MODE (operands[0]) == Pmode);
++    //gcc_assert (GET_MODE (operands[0]) == Pmode);
+ 
+     if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
+       emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+@@ -2338,7 +2560,7 @@ else
+ 
+ (define_insn "tablejump_internal1"
+   [(set (pc)
+-	(match_operand:SI 0 "register_operand" "d"))
++	(match_operand 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   "bra%?\t%0 "
+@@ -2348,9 +2570,9 @@ else
+ 
+ (define_expand "tablejump_internal3"
+   [(parallel [(set (pc)
+-		   (plus:SI (match_operand:SI 0 "register_operand" "d")
+-			    (label_ref:SI (match_operand:SI 1 "" ""))))
+-             (use (label_ref:SI (match_dup 1)))])]
++		   (plus (match_operand 0 "register_operand" "d")
++			    (label_ref (match_operand:SI 1 "" ""))))
++             (use (label_ref (match_dup 1)))])]
+   ""
+   ""
+ )
+@@ -2411,7 +2633,7 @@ else
+ 	(minus (reg 1) (match_operand 1 "register_operand" "")))
+    (set (reg 1)
+ 	(minus (reg 1) (match_dup 1)))]
+-  ""
++  "!TARGET_MB_64"
+   { 
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+     rtx reg = gen_reg_rtx (Pmode);
+@@ -2436,7 +2658,7 @@ else
+ (define_expand "save_stack_block"
+   [(match_operand 0 "register_operand" "")
+    (match_operand 1 "register_operand" "")]
+-  ""
++  "!TARGET_MB_64"
+   {
+     emit_move_insn (operands[0], operands[1]);
+     DONE;
+@@ -2446,7 +2668,7 @@ else
+ (define_expand "restore_stack_block"
+   [(match_operand 0 "register_operand" "")
+    (match_operand 1 "register_operand" "")]
+-  ""
++  "!TARGET_MB_64"
+   {
+     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
+     rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
+@@ -2493,7 +2715,7 @@ else
+ 
+ (define_insn "<optab>_internal"
+   [(any_return)
+-   (use (match_operand:SI 0 "register_operand" ""))]
++   (use (match_operand 0 "register_operand" ""))]
+   ""
+   {
+     if (microblaze_is_break_handler ())
+@@ -2526,7 +2748,7 @@ else
+ (define_expand "call"
+   [(parallel [(call (match_operand 0 "memory_operand" "m")
+ 		    (match_operand 1 "" "i"))
+-             (clobber (reg:SI R_SR))
++             (clobber (reg R_SR))
+              (use (match_operand 2 "" ""))
+              (use (match_operand 3 "" ""))])]
+   ""
+@@ -2547,12 +2769,12 @@ else
+ 
+     if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
+       emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
+                                	     pic_offset_table_rtx));
+     else
+       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ 
+         DONE;
+@@ -2562,7 +2784,7 @@ else
+ (define_expand "call_internal0"
+   [(parallel [(call (match_operand 0 "" "")
+ 		    (match_operand 1 "" ""))
+-             (clobber (match_operand:SI 2 "" ""))])]
++             (clobber (match_operand 2 "" ""))])]
+   ""
+   {
+   }
+@@ -2571,18 +2793,34 @@ else
+ (define_expand "call_internal_plt0"
+   [(parallel [(call (match_operand 0 "" "")
+ 		    (match_operand 1 "" ""))
+-             (clobber (match_operand:SI 2 "" ""))
+-             (use (match_operand:SI 3 "" ""))])]
++             (clobber (match_operand 2 "" ""))
++             (use (match_operand 3 "" ""))])]
+   ""
+   {
+   }
+ )
+  
++(define_insn "call_internal_plt_64"
++  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))
++  (use (reg R_GOT))]
++  "flag_pic && TARGET_MB_64"
++  {
++    register rtx target2 = gen_rtx_REG (Pmode, 
++			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++    gen_rtx_CLOBBER (VOIDmode, target2);
++    return "brealid\tr15,%0\;%#";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_internal_plt"
+-  [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
+-	 (match_operand:SI 1 "" "i"))
+-  (clobber (reg:SI R_SR))
+-  (use (reg:SI R_GOT))]
++  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))
++  (use (reg R_GOT))]
+   "flag_pic"
+   {
+     register rtx target2 = gen_rtx_REG (Pmode, 
+@@ -2594,10 +2832,41 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "call_internal1_64"
++  [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))]
++  "TARGET_MB_64"
++  {
++    register rtx target = operands[0];
++    register rtx target2 = gen_rtx_REG (Pmode,
++			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++    if (GET_CODE (target) == SYMBOL_REF) {
++        if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
++            gen_rtx_CLOBBER (VOIDmode, target2);
++            return "breaki\tr16,%0\;%#";
++        }
++        else {
++            gen_rtx_CLOBBER (VOIDmode, target2);
++            return "brealid\tr15,%0\;%#";
++        }
++    } else if (GET_CODE (target) == CONST_INT)
++        return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
++    else if (GET_CODE (target) == REG)
++        return "brald\tr15,%0\;%#";	
++    else {
++        fprintf (stderr,"Unsupported call insn\n");
++        return NULL;
++    }
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_internal1"
+   [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
+-	 (match_operand:SI 1 "" "i"))
+-  (clobber (reg:SI R_SR))]
++	 (match_operand 1 "" "i"))
++  (clobber (reg R_SR))]
+   ""
+   {
+     register rtx target = operands[0];
+@@ -2631,7 +2900,7 @@ else
+   [(parallel [(set (match_operand 0 "register_operand" "=d")
+ 		   (call (match_operand 1 "memory_operand" "m")
+ 			 (match_operand 2 "" "i")))
+-             (clobber (reg:SI R_SR))
++             (clobber (reg R_SR))
+              (use (match_operand 3 "" ""))])] ;; next_arg_reg
+   ""
+   {
+@@ -2652,13 +2921,13 @@ else
+     if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
+       emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
+ 			operands[2],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
+ 				     pic_offset_table_rtx));
+     else
+       emit_call_insn (gen_call_value_internal (operands[0], operands[1], 
+ 			operands[2],
+-                        gen_rtx_REG (SImode, 
++                        gen_rtx_REG (Pmode, 
+ 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
+ 
+     DONE;
+@@ -2670,7 +2939,7 @@ else
+   [(parallel [(set (match_operand 0 "" "")
+ 		   (call (match_operand 1 "" "")
+ 			 (match_operand 2 "" "")))
+-             (clobber (match_operand:SI 3 "" ""))
++             (clobber (match_operand 3 "" ""))
+              ])]
+   ""
+   {}
+@@ -2680,18 +2949,35 @@ else
+   [(parallel[(set (match_operand 0 "" "")
+                   (call (match_operand 1 "" "")
+                         (match_operand 2 "" "")))
+-             (clobber (match_operand:SI 3 "" ""))
+-             (use (match_operand:SI 4 "" ""))])]
++             (clobber (match_operand 3 "" ""))
++             (use (match_operand 4 "" ""))])]
+   "flag_pic"
+   {}
+ )
+ 
++(define_insn "call_value_intern_plt_64"
++  [(set (match_operand:VOID 0 "register_operand" "=d")
++        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))
++   (use (match_operand 4 "register_operand"))]
++  "flag_pic && TARGET_MB_64"
++  { 
++    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++
++    gen_rtx_CLOBBER (VOIDmode,target2);
++    return "brealid\tr15,%1\;%#";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_value_intern_plt"
+   [(set (match_operand:VOID 0 "register_operand" "=d")
+-        (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
+-              (match_operand:SI 2 "" "i")))
+-   (clobber (match_operand:SI 3 "register_operand" "=d"))
+-   (use (match_operand:SI 4 "register_operand"))]
++        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))
++   (use (match_operand 4 "register_operand"))]
+   "flag_pic"
+   { 
+     register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
+@@ -2703,11 +2989,46 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "call_value_intern_64"
++  [(set (match_operand:VOID 0 "register_operand" "=d")
++        (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))]
++  "TARGET_MB_64"
++  { 
++    register rtx target = operands[1];
++    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
++
++    if (GET_CODE (target) == SYMBOL_REF)
++    {
++      gen_rtx_CLOBBER (VOIDmode,target2);
++      if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
++        return "breaki\tr16,%1\;%#";
++      else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
++        {
++	  return "brealid\tr15,%1\;%#";
++        }
++      else
++        {
++	    return "bralid\tr15,%1\;%#";
++        }
++    }
++    else if (GET_CODE (target) == CONST_INT)
++        return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
++    else if (GET_CODE (target) == REG)
++        return "brald\tr15,%1\;%#";	
++    else 
++        return "Unsupported call insn\n";
++  }
++  [(set_attr "type"	"call")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "call_value_intern"
+   [(set (match_operand:VOID 0 "register_operand" "=d")
+         (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
+-              (match_operand:SI 2 "" "i")))
+-   (clobber (match_operand:SI 3 "register_operand" "=d"))]
++              (match_operand 2 "" "i")))
++   (clobber (match_operand 3 "register_operand" "=d"))]
+   ""
+   { 
+     register rtx target = operands[1];
+@@ -2881,7 +3202,6 @@ else
+ 
+   ;;if (!register_operand (operands[0], VOIDmode))
+   ;;  FAIL;
+-
+   emit_insn (gen_insv_32 (operands[0], operands[1],
+ 			  operands[2], operands[3]));
+   DONE;
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index e9a1921ae26..9fc80b142ce 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -2,7 +2,8 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
+ MULTILIB_DIRNAMES = bs m mh le m64
+ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
+ MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+ MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
+diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
+index d0146083db6..005825f1ec5 100644
+--- a/libgcc/config/microblaze/crti.S
++++ b/libgcc/config/microblaze/crti.S
+@@ -40,7 +40,7 @@
+ 
+     .align 2
+ __init: 
+-    addik   r1, r1, -8
++    addik   r1, r1, -16
+     sw      r15, r0, r1
+     la      r11, r0, _stack
+     mts     rshr, r11
+@@ -51,5 +51,5 @@ __init:
+     .global __fini
+     .align 2
+ __fini: 
+-    addik   r1, r1, -8
++    addik   r1, r1, -16
+     sw      r15, r0, r1
+diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
+index 2fff5ac04c7..5705eff9a4a 100644
+--- a/libgcc/config/microblaze/crtn.S
++++ b/libgcc/config/microblaze/crtn.S
+@@ -33,9 +33,9 @@
+     .section .init, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+-    addik   r1, r1, 8
++    addik   r1, r1, 16
+ 
+     .section .fini, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+-    addik   r1, r1, 8    
++    addik   r1, r1, 16   
+diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
+new file mode 100644
+index 00000000000..d37bf5165c6
+--- /dev/null
++++ b/libgcc/config/microblaze/divdi3.S
+@@ -0,0 +1,98 @@
++###################################-
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++#
++#  divdi3.S
++# 
++#  Divide operation for 32 bit integers.
++#	Input :	Dividend in Reg r5
++#		Divisor in Reg r6
++#	Output: Result in Reg r3
++# 
++#######################################
++
++#ifdef __arch64__	
++	.globl	__divdi3
++	.ent	__divdi3
++	.type	__divdi3,@function
++__divdi3:
++	.frame	r1,0,r15	
++
++	ADDLIK   r1,r1,-32
++	SLI     r28,r1,0
++	SLI     r29,r1,8
++	SLI     r30,r1,16
++	SLI     r31,r1,24
++
++	BEALEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEALEQI    r5,$LaResult_Is_Zero    # Result is Zero 
++	XORL     r28,r5,r6               # Get the sign of the result
++	BEALGEI   r5,$LaR5_Pos 
++	RSUBLI   r5,r5,0                 # Make r5 positive
++$LaR5_Pos:
++	BEALGEI    r6,$LaR6_Pos
++	RSUBLI   r6,r6,0                 # Make r6 positive
++$LaR6_Pos:
++	ADDLIK   r30,r0,0                # Clear mod
++	ADDLIK   r3,r0,0                 # clear div
++	ADDLIK   r29,r0,64               # Initialize the loop count
++
++        # First part try to find the first '1' in the r5
++$LaDIV0: 
++        BEALLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++$LaDIV1:
++	ADDL     r5,r5,r5                # left shift logical r5
++	ADDLIK   r29,r29,-1
++	BEALGTI   r5,$LaDIV1       
++$LaDIV2:
++	ADDL     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
++	ADDLC    r30,r30,r30             # Move that bit into the Mod register
++	RSUBL    r31,r6,r30              # Try to subtract (r30 a r6)
++	BEALLTI    r31,$LaMOD_TOO_SMALL
++	ORL      r30,r0,r31              # Move the r31 to mod since the result was positive
++	ADDLIK   r3,r3,1
++$LaMOD_TOO_SMALL:
++	ADDLIK   r29,r29,-1
++	BEALEQi    r29,$LaLOOP_END
++	ADDL     r3,r3,r3                # Shift in the '1' into div
++	BREAI     $LaDIV2                 # Div2
++$LaLOOP_END:
++	BEALGEI    r28,$LaRETURN_HERE
++	RSUBLI   r3,r3,0                 # Negate the result
++	BREAI    $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	ORL      r3,r0,r0 # set result to 0
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r28,r1,0
++	LLI     r29,r1,8
++	LLI     r30,r1,16
++	LLI     r31,r1,24
++	ADDLIK   r1,r1,32
++	RTSD    r15,8
++        nop
++.end __divdi3
++	.size	__divdi3, . - __divdi3
++#endif
+diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
+new file mode 100644
+index 00000000000..80962597ea5
+--- /dev/null
++++ b/libgcc/config/microblaze/divdi3_table.c
+@@ -0,0 +1,62 @@
++/*  Table for software lookup divide for Xilinx MicroBlaze.
++ 
++   Copyright (C) 2009-2017 Free Software Foundation, Inc.
++
++   Contributed by Michael Eager <eager@eagercon.com>.
++
++   This file is free software; you can redistribute it and/or modify it
++   under the terms of the GNU General Public License as published by the
++   Free Software Foundation; either version 3, or (at your option) any
++   later version.
++
++   GCC is distributed in the hope that it will be useful, but WITHOUT
++   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++   License for more details.
++
++   Under Section 7 of GPL version 3, you are granted additional
++   permissions described in the GCC Runtime Library Exception, version
++   3.1, as published by the Free Software Foundation.
++
++   You should have received a copy of the GNU General Public License and
++   a copy of the GCC Runtime Library Exception along with this program;
++   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++   <http://www.gnu.org/licenses/>.  */
++
++ 
++unsigned char _divdi3_table[] =
++{
++       0,   0/1,   0/2,   0/3,   0/4,   0/5,   0/6,   0/7, 
++     0/8,   0/9,  0/10,  0/11,  0/12,  0/13,  0/14,  0/15,
++       0,   1/1,   1/2,   1/3,   1/4,   1/5,   1/6,   1/7, 
++     1/8,   1/9,  1/10,  1/11,  1/12,  1/13,  1/14,  1/15,
++       0,   2/1,   2/2,   2/3,   2/4,   2/5,   2/6,   2/7, 
++     2/8,   2/9,  2/10,  2/11,  2/12,  2/13,  2/14,  2/15,
++       0,   3/1,   3/2,   3/3,   3/4,   3/5,   3/6,   3/7, 
++     3/8,   3/9,  3/10,  3/11,  3/12,  3/13,  3/14,  3/15,
++       0,   4/1,   4/2,   4/3,   4/4,   4/5,   4/6,   4/7, 
++     4/8,   4/9,  4/10,  4/11,  4/12,  4/13,  4/14,  4/15,
++       0,   5/1,   5/2,   5/3,   5/4,   5/5,   5/6,   5/7, 
++     5/8,   5/9,  5/10,  5/11,  5/12,  5/13,  5/14,  5/15,
++       0,   6/1,   6/2,   6/3,   6/4,   6/5,   6/6,   6/7, 
++     6/8,   6/9,  6/10,  6/11,  6/12,  6/13,  6/14,  6/15,
++       0,   7/1,   7/2,   7/3,   7/4,   7/5,   7/6,   7/7, 
++     7/8,   7/9,  7/10,  7/11,  7/12,  7/13,  7/14,  7/15,
++       0,   8/1,   8/2,   8/3,   8/4,   8/5,   8/6,   8/7, 
++     8/8,   8/9,  8/10,  8/11,  8/12,  8/13,  8/14,  8/15,
++       0,   9/1,   9/2,   9/3,   9/4,   9/5,   9/6,   9/7, 
++     9/8,   9/9,  9/10,  9/11,  9/12,  9/13,  9/14,  9/15,
++       0,  10/1,  10/2,  10/3,  10/4,  10/5,  10/6,  10/7, 
++    10/8,  10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
++       0,  11/1,  11/2,  11/3,  11/4,  11/5,  11/6,  11/7, 
++    11/8,  11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
++       0,  12/1,  12/2,  12/3,  12/4,  12/5,  12/6,  12/7, 
++    12/8,  12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
++       0,  13/1,  13/2,  13/3,  13/4,  13/5,  13/6,  13/7, 
++    13/8,  13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
++       0,  14/1,  14/2,  14/3,  14/4,  14/5,  14/6,  14/7, 
++    14/8,  14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
++       0,  15/1,  15/2,  15/3,  15/4,  15/5,  15/6,  15/7, 
++    15/8,  15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
++};
++
+diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
+new file mode 100644
+index 00000000000..5d3f7c03fc8
+--- /dev/null
++++ b/libgcc/config/microblaze/moddi3.S
+@@ -0,0 +1,97 @@
++###################################
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  moddi3.S
++# 
++#  modulo operation for 32 bit integers.
++#	Input :	op1 in Reg r5
++#		op2 in Reg r6
++#	Output: op1 mod op2 in Reg r3
++# 
++#######################################
++
++#ifdef __arch64__
++	.globl	__moddi3
++	.ent	__moddi3
++	.type	__moddi3,@function
++__moddi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-32
++	sli	r28,r1,0
++	sli	r29,r1,8
++	sli	r30,r1,16
++	sli	r31,r1,32
++
++	BEALEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEALEQI	r5,$LaResult_Is_Zero    # Result is Zero 
++	ADDL	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
++	BEALGEI	r5,$LaR5_Pos 
++	RSUBLI	r5,r5,0	                # Make r5 positive
++$LaR5_Pos:
++	BEALGEI	r6,$LaR6_Pos
++	RSUBLI	r6,r6,0	    # Make r6 positive
++$LaR6_Pos:
++	ADDLIK	r3,r0,0      # Clear mod
++	ADDLIK	r30,r0,0     # clear div
++	ADDLIK	r29,r0,64    # Initialize the loop count
++	BEALLTI	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++			     # the first bit search.
++   # First part try to find the first '1' in the r5
++$LaDIV1:
++	ADDL	r5,r5,r5         # left shift logical r5
++	ADDLIK	r29,r29,-1
++	BEALGEI	r5,$LaDIV1       #
++$LaDIV2:
++	ADDL	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
++	ADDLC	r3,r3,r3         # Move that bit into the Mod register
++	rSUBL	r31,r6,r3        # Try to subtract (r30 a r6)
++	BEALLTi	r31,$LaMOD_TOO_SMALL
++	ORL	r3,r0,r31       # Move the r31 to mod since the result was positive
++	ADDLIK	r30,r30,1
++$LaMOD_TOO_SMALL:
++	ADDLIK	r29,r29,-1
++	BEALEQi	r29,$LaLOOP_END
++	ADDL	r30,r30,r30         # Shift in the '1' into div
++	BREAI	$LaDIV2          # Div2
++$LaLOOP_END:
++	BEALGEI	r28,$LaRETURN_HERE
++	rsubli	r3,r3,0 # Negate the result
++	BREAI	$LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	orl	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli	r28,r1,0
++	lli	r29,r1,8
++	lli	r30,r1,16
++	lli	r31,r1,24
++	addlik	r1,r1,32
++	rtsd	r15,8
++        nop
++        .end __moddi3
++	.size	__moddi3, . - __moddi3
++#endif
+diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
+new file mode 100644
+index 00000000000..567784197d3
+--- /dev/null
++++ b/libgcc/config/microblaze/muldi3.S
+@@ -0,0 +1,73 @@
++/*###################################-*-asm*- 
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  muldi3.S
++# 
++#  Multiply operation for 32 bit integers.
++#	Input :	Operand1 in Reg r5
++#		Operand2 in Reg r6
++#	Output: Result [op1 * op2] in Reg r3
++# 
++#######################################*/
++
++#ifdef __arch64__
++	.globl	__muldi3
++	.ent	__muldi3
++	.type	__muldi3,@function
++__muldi3:
++	.frame	r1,0,r15
++	addl	r3,r0,r0
++	BEALEQI	r5,$L_Result_Is_Zero      # Multiply by Zero
++	BEALEQI	r6,$L_Result_Is_Zero      # Multiply by Zero
++	XORL	r4,r5,r6                  # Get the sign of the result
++	BEALGEI	r5,$L_R5_Pos 
++	RSUBLI	r5,r5,0	                  # Make r5 positive
++$L_R5_Pos:
++	BEALGEI	r6,$L_R6_Pos
++	RSUBLI	r6,r6,0	                  # Make r6 positive
++$L_R6_Pos:	
++	breai	$L1
++$L2:	
++	addl	r5,r5,r5
++$L1:	
++	srll	r6,r6
++	addlc	r7,r0,r0
++	bealeqi	r7,$L2
++	addl	r3,r3,r5	
++	bealnei	r6,$L2
++	beallti	r4,$L_NegateResult			
++	rtsd	r15,8
++	nop
++$L_NegateResult:
++	rsubl	r3,r3,r0
++	rtsd	r15,8
++	nop
++$L_Result_Is_Zero:
++	addli	r3,r0,0
++	rtsd	r15,8
++	nop
++	.end __muldi3
++	.size	__muldi3, . - __muldi3
++#endif
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 8d954a49575..35021b24b7d 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,11 +1,16 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
++			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
++        $(srcdir)/config/microblaze/divdi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+-        $(srcdir)/config/microblaze/muldi3_hard.S \
++        $(srcdir)/config/microblaze/moddi3.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
++        $(srcdir)/config/microblaze/muldi3.S \
+         $(srcdir)/config/microblaze/stack_overflow_exit.S \
+         $(srcdir)/config/microblaze/udivsi3.S \
++        $(srcdir)/config/microblaze/udivdi3.S \
+         $(srcdir)/config/microblaze/umodsi3.S \
+-        $(srcdir)/config/microblaze/divsi3_table.c
++        $(srcdir)/config/microblaze/umoddi3.S \
++        $(srcdir)/config/microblaze/divsi3_table.c \
+diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
+new file mode 100644
+index 00000000000..c210fbc7128
+--- /dev/null
++++ b/libgcc/config/microblaze/udivdi3.S
+@@ -0,0 +1,107 @@
++###################################-
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  udivdi3.S
++# 
++#  Unsigned divide operation.
++#	Input :	Divisor in Reg r5
++#		Dividend in Reg r6
++#	Output: Result in Reg r3
++# 
++#######################################
++	
++#ifdef __arch64__
++	.globl	__udivdi3
++	.ent	__udivdi3
++	.type	__udivdi3,@function
++__udivdi3:
++	.frame	r1,0,r15	
++
++	ADDlIK   r1,r1,-24
++    	SLI     r29,r1,0
++	SLI     r30,r1,8
++	SLI     r31,r1,16
++
++	BEALEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++	ADDLIK   r30,r0,0                    # Clear mod
++	BEALEQI   r5,$LaResult_Is_Zero        # Result is Zero 
++	ADDLIK   r29,r0,64                   # Initialize the loop count
++
++        # Check if r6 and r5 are equal # if yes, return 1
++	RSUBL 	r18,r5,r6
++	ADDLIK	r3,r0,1
++	BEALEQI	r18,$LaRETURN_HERE
++
++        # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
++	XORL	r18,r5,r6
++	ADDL	r3,r0,r0                    # We would anyways clear r3
++	BEALGEI	r18,$LRSUBL
++	BEALLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++	BREAI	$LCheckr6
++$LRSUBL:
++	RSUBL	r18,r6,r5                   # MICROBLAZEcmp
++	BEALLTI	r18,$LaRETURN_HERE
++
++        # If r6 [bit 31] is set, then return result as 1
++$LCheckr6:
++	BEALGTI	r6,$LaDIV0
++	ADDLIK	r3,r0,1
++	BREAI	$LaRETURN_HERE
++
++        # First part try to find the first '1' in the r5
++$LaDIV0:
++	BEALLTI    r5,$LaDIV2	
++$LaDIV1:
++	ADDL     r5,r5,r5                    # left shift logical r5
++	ADDLIK   r29,r29,-1
++	BEALGTI   r5,$LaDIV1       
++$LaDIV2:
++	ADDL     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
++	ADDLC    r30,r30,r30                 # Move that bit into the Mod register
++	RSUBL    r31,r6,r30                  # Try to subtract (r30 a r6)
++    	BEALLTI    r31,$LaMOD_TOO_SMALL
++	ORL      r30,r0,r31                  # Move the r31 to mod since the result was positive
++	ADDLIK   r3,r3,1
++$LaMOD_TOO_SMALL:
++	ADDLIK   r29,r29,-1
++	BEALEQi    r29,$LaLOOP_END
++	ADDL     r3,r3,r3 # Shift in the '1' into div
++	BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++	BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	ORL      r3,r0,r0 # set result to 0
++$LaRETURN_HERE:
++        # Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r29,r1,0
++	LLI     r30,r1,8
++	LLI     r31,r1,16
++	ADDLIK   r1,r1,24
++	RTSD    r15,8
++        NOP
++        .end __udivdi3
++	.size	__udivdi3, . - __udivdi3
++#endif
+diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
+new file mode 100644
+index 00000000000..7f5cd23f9a1
+--- /dev/null
++++ b/libgcc/config/microblaze/umoddi3.S
+@@ -0,0 +1,110 @@
++###################################
++# 
++#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
++#
++#  Contributed by Michael Eager <eager@eagercon.com>.
++#
++#  This file is free software; you can redistribute it and/or modify it
++#  under the terms of the GNU General Public License as published by the
++#  Free Software Foundation; either version 3, or (at your option) any
++#  later version.
++#
++#  GCC is distributed in the hope that it will be useful, but WITHOUT
++#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
++#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
++#  License for more details.
++#
++#  Under Section 7 of GPL version 3, you are granted additional
++#  permissions described in the GCC Runtime Library Exception, version
++#  3.1, as published by the Free Software Foundation.
++#
++#  You should have received a copy of the GNU General Public License and
++#  a copy of the GCC Runtime Library Exception along with this program;
++#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
++#  <http://www.gnu.org/licenses/>. 
++# 
++#  umoddi3.S
++#
++#  Unsigned modulo operation for 32 bit integers.
++#	Input :	op1 in Reg r5
++#		op2 in Reg r6
++#	Output: op1 mod op2 in Reg r3
++# 
++#######################################
++	
++#ifdef __arch64__
++	.globl	__umoddi3
++	.ent	__umoddi3
++	.type	__umoddi3,@function
++__umoddi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-24
++	sli	r29,r1,0
++	sli	r30,r1,8
++	sli	r31,r1,16
++
++	BEALEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++	ADDLIK 	r3,r0,0                  # Clear div
++	BEALEQI	r5,$LaResult_Is_Zero     # Result is Zero 
++	ADDLIK 	r30,r0,0     	# clear mod
++	ADDLIK 	r29,r0,64       # Initialize the loop count
++
++# Check if r6 and r5 are equal # if yes, return 0
++	rsubl 	r18,r5,r6
++	bealeqi	r18,$LaRETURN_HERE
++
++# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
++	xorl	r18,r5,r6
++	addlik	r3,r5,0
++	bealgei	r18,$LRSUB
++	beallti	r6,$LaRETURN_HERE
++	breai	$LCheckr6
++$LRSUB:
++	rsubl	r18,r5,r6 # MICROBLAZEcmp
++	bealgti	r18,$LaRETURN_HERE
++
++# If r6 [bit 31] is set, then return result as r5-r6
++$LCheckr6:
++	addlik	r3,r0,0
++	bealgti	r6,$LaDIV0
++	addlik	r18,r0,0x7fffffff
++	andl	r5,r5,r18
++	andl 	r6,r6,r18
++	breaid	$LaRETURN_HERE
++	rsubl	r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++	BEALLTI	r5,$LaDIV2
++$LaDIV1:
++	ADDL 	r5,r5,r5     # left shift logical r5
++	ADDLIK 	r29,r29,-1
++	BEALGEI 	r5,$LaDIV1   #
++$LaDIV2:
++	ADDL 	r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++	ADDLC 	r3,r3,r3     # Move that bit into the Mod register
++	rSUBL 	r31,r6,r3    # Try to subtract (r3 a r6)
++	BEALLTi 	r31,$LaMOD_TOO_SMALL
++	ORL  	r3,r0,r31    # Move the r31 to mod since the result was positive
++	ADDLIK 	r30,r30,1
++$LaMOD_TOO_SMALL:
++	ADDLIK 	r29,r29,-1
++	BEALEQi 	r29,$LaLOOP_END
++	ADDL 	r30,r30,r30 # Shift in the '1' into div
++	BREAI 	$LaDIV2     # Div2
++$LaLOOP_END:
++	BREAI 	$LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++	orl 	r3,r0,r0   # set result to 0
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli 	r29,r1,0
++	lli 	r30,r1,8
++	lli 	r31,r1,16
++	addlik 	r1,r1,24
++	rtsd 	r15,8
++        nop
++.end __umoddi3
++	.size	__umoddi3, . - __umoddi3
++#endif
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
deleted file mode 100644
index bb7732399c..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch
+++ /dev/null
@@ -1,241 +0,0 @@
-From df38540af411564f428079335c8d1e695dc1d723 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 18 Jan 2017 12:42:10 +0530
-Subject: [PATCH 30/58] [Patch, microblaze]: Fix bug in MB version calculation
-
-This patch fixes the bug in microblaze_version_to_int function.
-Earlier the conversion of vXX.YY.Z to int has a bug which is
-fixed now.
-
-Signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com>
-                Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c | 145 ++++++++++++++---------------
- 1 file changed, 69 insertions(+), 76 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 0a73a6c32b4..4b5699671e8 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -242,6 +242,63 @@ section *sdata2_section;
- #define TARGET_HAVE_TLS true
- #endif
- 
-+/*  Convert a version number of the form "vX.YY.Z" to an integer encoding
-+    for easier range comparison.  */
-+static int
-+microblaze_version_to_int (const char *version)
-+{
-+  const char *p, *v;
-+  const char *tmpl = "vXX.YY.Z";
-+  int iver1 =0, iver2 =0, iver3 =0;
-+
-+  p = version;
-+  v = tmpl;
-+
-+  while (*p)
-+    {
-+      if (*v == 'X')
-+	{			/* Looking for major  */
-+          if (*p == '.')
-+            {
-+              *v++;
-+            }
-+          else
-+            {
-+	      if (!(*p >= '0' && *p <= '9'))
-+	        return -1;
-+	      iver1 += (int) (*p - '0');
-+              iver1 *= 1000;
-+	     }
-+        }
-+      else if (*v == 'Y')
-+	{			/* Looking for minor  */
-+	  if (!(*p >= '0' && *p <= '9'))
-+	    return -1;
-+	  iver2 += (int) (*p - '0');
-+	  iver2 *= 10;
-+	}
-+      else if (*v == 'Z')
-+	{			/* Looking for compat  */
-+	  if (!(*p >= 'a' && *p <= 'z'))
-+	    return -1;
-+      iver3 = ((int) (*p)) - 96;
-+	}
-+      else
-+	{
-+	  if (*p != *v)
-+	    return -1;
-+	}
-+
-+      v++;
-+      p++;
-+    }
-+
-+  if (*p)
-+    return -1;
-+
-+  return iver1 + iver2 + iver3;
-+}
-+
- /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant.  */
- static bool
- microblaze_const_double_ok (rtx op, machine_mode mode)
-@@ -1341,8 +1398,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
-       {
- 	if (TARGET_BARREL_SHIFT)
- 	  {
--	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
--		>= 0)
-+	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
- 	      *total = COSTS_N_INSNS (1);
- 	    else
- 	      *total = COSTS_N_INSNS (2);
-@@ -1403,8 +1459,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
- 	  }
- 	else if (!TARGET_SOFT_MUL)
- 	  {
--	    if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a")
--		>= 0)
-+	    if (microblaze_version_to_int(microblaze_select_cpu) >= microblaze_version_to_int("v5.00.a"))
- 	      *total = COSTS_N_INSNS (1);
- 	    else
- 	      *total = COSTS_N_INSNS (3);
-@@ -1677,65 +1732,6 @@ function_arg_partial_bytes (cumulative_args_t cum_v,
-   return 0;
- }
- 
--/*  Convert a version number of the form "vX.YY.Z" to an integer encoding 
--    for easier range comparison.  */
--static int
--microblaze_version_to_int (const char *version)
--{
--  const char *p, *v;
--  const char *tmpl = "vXX.YY.Z";
--  int iver = 0;
--
--  p = version;
--  v = tmpl;
--
--  while (*p)
--    {
--      if (*v == 'X')
--	{			/* Looking for major  */
--          if (*p == '.')
--            {
--              v++;
--            }
--          else
--            {
--	      if (!(*p >= '0' && *p <= '9'))
--	        return -1;
--	      iver += (int) (*p - '0');
--              iver *= 10;
--	     }
--        }
--      else if (*v == 'Y')
--	{			/* Looking for minor  */
--	  if (!(*p >= '0' && *p <= '9'))
--	    return -1;
--	  iver += (int) (*p - '0');
--	  iver *= 10;
--	}
--      else if (*v == 'Z')
--	{			/* Looking for compat  */
--	  if (!(*p >= 'a' && *p <= 'z'))
--	    return -1;
--	  iver *= 10;
--	  iver += (int) (*p - 'a');
--	}
--      else
--	{
--	  if (*p != *v)
--	    return -1;
--	}
--
--      v++;
--      p++;
--    }
--
--  if (*p)
--    return -1;
--
--  return iver;
--}
--
--
- static void
- microblaze_option_override (void)
- {
-@@ -1763,13 +1759,13 @@ microblaze_option_override (void)
-   /* Check the MicroBlaze CPU version for any special action to be done.  */
-   if (microblaze_select_cpu == NULL)
-     microblaze_select_cpu = MICROBLAZE_DEFAULT_CPU;
--  ver = microblaze_version_to_int (microblaze_select_cpu);
--  if (ver == -1)
-+  ver_int = microblaze_version_to_int (microblaze_select_cpu);
-+  if (ver_int == -1)
-     {
-       error ("%qs is an invalid argument to %<-mcpu=%>", microblaze_select_cpu);
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v3.00.a");
-+  ver = ver_int - microblaze_version_to_int("v3.00.a");
-   if (ver < 0)
-     {
-       /* No hardware exceptions in earlier versions. So no worries.  */
-@@ -1780,8 +1776,7 @@ microblaze_option_override (void)
-       microblaze_pipe = MICROBLAZE_PIPE_3;
-     }
-   else if (ver == 0
--	   || (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v4.00.b")
--	       == 0))
-+	   || (ver_int ==  microblaze_version_to_int("v4.00.b")))
-     {
- #if 0
-       microblaze_select_flags |= (MICROBLAZE_MASK_NO_UNSAFE_DELAY);
-@@ -1798,11 +1793,9 @@ microblaze_option_override (void)
- #endif
-       microblaze_no_unsafe_delay = 0;
-       microblaze_pipe = MICROBLAZE_PIPE_5;
--      if (MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v5.00.a") == 0
--	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
--					 "v5.00.b") == 0
--	  || MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu,
--					 "v5.00.c") == 0)
-+      if ((ver_int == microblaze_version_to_int("v5.00.a"))
-+	  || (ver_int == microblaze_version_to_int("v5.00.b"))
-+	  || (ver_int == microblaze_version_to_int("v5.00.c")))
- 	{
- 	  /* Pattern compares are to be turned on by default only when 
-  	     compiling for MB v5.00.'z'.  */
-@@ -1810,7 +1803,7 @@ microblaze_option_override (void)
- 	}
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v6.00.a");
-+  ver = ver_int - microblaze_version_to_int("v6.00.a");
-   if (ver < 0)
-     {
-       if (TARGET_MULTIPLY_HIGH)
-@@ -1819,7 +1812,7 @@ microblaze_option_override (void)
- 		 "%<-mcpu=v6.00.a%> or greater");
-     }
- 
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.10.a");
-+  ver = ver_int - microblaze_version_to_int("v8.10.a");
-   microblaze_has_clz = 1;
-   if (ver < 0)
-     {
-@@ -1828,7 +1821,7 @@ microblaze_option_override (void)
-     }
- 
-   /* TARGET_REORDER defaults to 2 if -mxl-reorder not specified.  */
--  ver = MICROBLAZE_VERSION_COMPARE (microblaze_select_cpu, "v8.30.a");
-+  ver = ver_int - microblaze_version_to_int("v8.30.a");
-   if (ver < 0)
-     {
-         if (TARGET_REORDER == 1)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch
deleted file mode 100644
index 0c80cf8164..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-Fixing-the-issue-with-the-builtin_alloc.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From 87da245d89fffe6a025037b4a53f66dafa7e1f84 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 23 Feb 2017 17:09:04 +0530
-Subject: [PATCH 31/58] Fixing the issue with the builtin_alloc.
-
-register r18 was not properly handling the stack pattern
-which was resolved by using free available register
-
-signed-off-by:nagaraju mekala <nmekala@xilinx.com>
----
- gcc/config/microblaze/microblaze.md | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fa6aabdb9d4..9de46d0ce24 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2078,10 +2078,10 @@
-   ""
-   { 
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
--    rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-+    rtx reg = gen_reg_rtx (Pmode);
-     rtx neg_op0;
- 
--    emit_move_insn (rtmp, retaddr);
-+    emit_move_insn (reg, retaddr);
-     if (GET_CODE (operands[1]) != CONST_INT)
-     {
-         neg_op0 = gen_reg_rtx (Pmode);
-@@ -2090,9 +2090,9 @@
-         neg_op0 = GEN_INT (- INTVAL (operands[1]));
- 
-     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
--    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), rtmp);
-+    emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), reg);
-     emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
--    emit_insn (gen_rtx_CLOBBER (SImode, rtmp));
-+    emit_insn (gen_rtx_CLOBBER (SImode, reg));
-     DONE;
-   }
- )
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch
new file mode 100644
index 0000000000..0113c65dc1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0031-re-arrangement-of-the-compare-branches.patch
@@ -0,0 +1,268 @@
+From 67d89be9ace8f658354fb1378e986451ef435d60 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 3 Aug 2018 15:41:39 +0530
+Subject: [PATCH 31/54] re-arrangement of the compare branches
+
+---
+ gcc/config/microblaze/microblaze.c  |  28 ++----
+ gcc/config/microblaze/microblaze.md | 141 +++++++++++++---------------
+ 2 files changed, 73 insertions(+), 96 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 3c815444574..046bfd05558 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3697,11 +3697,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+     {
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == Pmode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
+-
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+ 
+   else if (code == EQ || code == NE)
+@@ -3712,10 +3708,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
+       else
+         emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
+       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else
+     {
+@@ -3748,10 +3741,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+       comp_reg = cmp_op0;
+       condition = gen_rtx_fmt_ee (signed_condition (code),
+                                   mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else if (code == EQ)
+     {
+@@ -3766,10 +3756,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+                                            cmp_op1));
+ 	}
+       condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+  
+     }
+   else if (code == NE)
+@@ -3785,10 +3772,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
+                                            cmp_op1));
+ 	}
+       condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
+-      if (mode == SImode)
+-        emit_jump_insn (gen_condjump (condition, label1));
+-      else
+-        emit_jump_insn (gen_long_condjump (condition, label1));
++      emit_jump_insn (gen_condjump (condition, label1));
+     }
+   else
+     {
+@@ -3830,7 +3814,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
+ 
+   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
+   condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
+-  emit_jump_insn (gen_long_condjump (condition, operands[3]));
++  emit_jump_insn (gen_condjump (condition, operands[3]));
+ }
+ 
+ /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 33a8b12ef3b..cfe9e5312d1 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2271,7 +2271,27 @@ else
+ 		      (label_ref (match_operand 1))
+ 		      (pc)))])
+ 
+-(define_insn "branch_zero64"
++(define_insn "branch_zero_64"
++  [(set (pc)
++	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++  				 [(match_operand:SI 1 "register_operand" "d")
++                                  (const_int 0)])
++                      (match_operand:SI 2 "pc_or_label_operand" "")
++                      (match_operand:SI 3 "pc_or_label_operand" "")))
++  ]
++  "TARGET_MB_64"
++  {
++    if (operands[3] == pc_rtx) 
++      return "bea%C0i%?\t%z1,%2";
++    else 
++      return "bea%N0i%?\t%z1,%3";
++  }
++  [(set_attr "type"	"branch")
++   (set_attr "mode"	"none")
++   (set_attr "length"	"4")]
++)
++
++(define_insn "long_branch_zero"
+   [(set (pc)
+ 	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand 1 "register_operand" "d")
+@@ -2282,9 +2302,9 @@ else
+   "TARGET_MB_64"
+   {
+     if (operands[3] == pc_rtx) 
+-      return "bea%C0i%?\t%z1,%2";
++      return "beal%C0i%?\t%z1,%2";
+     else 
+-      return "bea%N0i%?\t%z1,%3";
++      return "beal%N0i%?\t%z1,%3";
+   }
+   [(set_attr "type"	"branch")
+    (set_attr "mode"	"none")
+@@ -2313,9 +2333,9 @@ else
+ 
+ (define_insn "branch_compare64"
+   [(set (pc)
+-        (if_then_else (match_operator 0 "cmp_op"
+-                                         [(match_operand 1 "register_operand" "d")
+-                                          (match_operand 2 "register_operand" "d")
++        (if_then_else (match_operator:SI 0 "cmp_op"
++                                         [(match_operand:SI 1 "register_operand" "d")
++                                          (match_operand:SI 2 "register_operand" "d")
+                                          ])
+                       (label_ref (match_operand 3))
+                       (pc)))
+@@ -2352,6 +2372,47 @@ else
+    (set_attr "length"   "12")]
+ )
+ 
++(define_insn "long_branch_compare"
++  [(set (pc)
++        (if_then_else (match_operator 0 "cmp_op"
++                                         [(match_operand 1 "register_operand" "d")
++                                          (match_operand 2 "register_operand" "d")
++                                         ])
++                      (label_ref (match_operand 3))
++                      (pc)))
++  (clobber(reg:DI R_TMP))]
++  "TARGET_MB_64"
++  {
++    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    enum rtx_code code = GET_CODE (operands[0]);
++
++    if (code == GT || code == LE)
++      {
++        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GTU || code == LEU)
++      {
++        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
++        code = swap_condition (code);
++      }
++    else if (code == GE || code == LT)
++      {
++        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
++      }
++    else if (code == GEU || code == LTU)
++      {
++        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
++      }
++
++    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
++    return "beal%C0i%?\tr18,%3";
++  }
++  [(set_attr "type"     "branch")
++   (set_attr "mode"     "none")
++   (set_attr "length"   "12")]
++)
++
+ (define_insn "branch_compare"
+   [(set (pc)
+         (if_then_else (match_operator:SI 0 "cmp_op"
+@@ -2434,74 +2495,6 @@ else
+ 
+ })
+ 
+-;; Used to implement comparison instructions
+-(define_expand "long_condjump"
+-  [(set (pc)
+-	(if_then_else (match_operand 0)
+-		      (label_ref (match_operand 1))
+-		      (pc)))])
+-
+-(define_insn "long_branch_zero"
+-  [(set (pc)
+-	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
+-  				 [(match_operand:DI 1 "register_operand" "d")
+-                                  (const_int 0)])
+-                      (match_operand:DI 2 "pc_or_label_operand" "")
+-                      (match_operand:DI 3 "pc_or_label_operand" "")))
+-  ]
+-  "TARGET_MB_64"
+-  {
+-    if (operands[3] == pc_rtx) 
+-      return "beal%C0i%?\t%z1,%2";
+-    else 
+-      return "beal%N0i%?\t%z1,%3";
+-  }
+-  [(set_attr "type"	"branch")
+-   (set_attr "mode"	"none")
+-   (set_attr "length"	"4")]
+-)
+-
+-(define_insn "long_branch_compare"
+-  [(set (pc)
+-        (if_then_else (match_operator:DI 0 "cmp_op"
+-                                         [(match_operand:DI 1 "register_operand" "d")
+-                                          (match_operand:DI 2 "register_operand" "d")
+-                                         ])
+-                      (label_ref (match_operand 3))
+-                      (pc)))
+-  (clobber(reg:DI R_TMP))]
+-  "TARGET_MB_64"
+-  {
+-    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
+-    enum rtx_code code = GET_CODE (operands[0]);
+-
+-    if (code == GT || code == LE)
+-      {
+-        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
+-        code = swap_condition (code);
+-      }
+-    else if (code == GTU || code == LEU)
+-      {
+-        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
+-        code = swap_condition (code);
+-      }
+-    else if (code == GE || code == LT)
+-      {
+-        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
+-      }
+-    else if (code == GEU || code == LTU)
+-      {
+-        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
+-      }
+-
+-    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
+-    return "beal%C0i%?\tr18,%3";
+-  }
+-  [(set_attr "type"     "branch")
+-   (set_attr "mode"     "none")
+-   (set_attr "length"   "12")]
+-)
+-
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
new file mode 100644
index 0000000000..b74c79ec64
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch
@@ -0,0 +1,28 @@
+From 410348f4fd9b641afa24e6c6b6a62a4c74d18862 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 8 Aug 2018 17:37:26 +0530
+Subject: [PATCH 32/54] [Patch,Microblaze] :  previous commit broke the
+ handling of SI Branch compare for Microblaze 32-bit..
+
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index cfe9e5312d1..592757baf2f 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2227,8 +2227,8 @@ else
+ (define_expand "cbranchsi4"
+   [(set (pc)
+         (if_then_else (match_operator 0 "ordered_comparison_operator"
+-                       [(match_operand 1 "register_operand")
+-                        (match_operand 2 "arith_operand" "I,i")])
++                       [(match_operand:SI 1 "register_operand")
++                        (match_operand:SI 2 "arith_operand" "I,i")])
+                       (label_ref (match_operand 3 ""))
+                       (pc)))]
+   ""
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
deleted file mode 100644
index 458af563bb..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 3e8779308d1901b273b2b360bea719aa72d24ab9 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 19 Feb 2018 18:06:16 +0530
-Subject: [PATCH 32/58] [Patch,Microblaze]: update in constraints for bitfield
- insert and extract instructions.
-
----
- gcc/config/microblaze/microblaze.md | 43 +++++------------------------
- 1 file changed, 7 insertions(+), 36 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 9de46d0ce24..fe94807182b 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2492,33 +2492,17 @@
-   DONE;
- }")
- 
--(define_expand "extvsi"
-+(define_expand "extzvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
- 			 (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
--"
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
--
--  if ((len == 0) || (pos + len > 32) )
--    FAIL;
--
--  ;;if (!register_operand (operands[1], VOIDmode))
--  ;;  FAIL;
--  if (operands[0] == operands[1])
--  FAIL;
--  if (GET_CODE (operands[1]) == ASHIFT)
--  FAIL;
--;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-- emit_insn (gen_extv_32 (operands[0], operands[1],
--			  operands[2], operands[3]));
--  DONE;
--}")
-+""
-+)
- 
--(define_insn "extv_32"
-+
-+(define_insn "extzv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2535,21 +2519,8 @@
- 			 (match_operand:SI 2 "immediate_operand" "I"))
- 	(match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
--  "
--{
--  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
--  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
--
--  if (len <= 0 || pos + len > 32)
--    FAIL;
--
--  ;;if (!register_operand (operands[0], VOIDmode))
--  ;;  FAIL;
--
--  emit_insn (gen_insv_32 (operands[0], operands[1],
--			  operands[2], operands[3]));
--  DONE;
--}")
-+""
-+)
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
deleted file mode 100644
index 32433470d8..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From eb90da1d616dfb7481b3f7c74a2be40e921a24f2 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 4 Jun 2018 10:10:18 +0530
-Subject: [PATCH 33/58] [Patch,Microblaze] : Removed fsqrt generation for
- double values.
-
----
- gcc/config/microblaze/microblaze.md | 14 --------------
- 1 file changed, 14 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index fe94807182b..a527da70f8a 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -526,20 +526,6 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
--(define_insn "sqrtdf2"
--  [(set (match_operand:DF 0 "register_operand" "=d")
--        (sqrt:DF (match_operand:DF 1 "register_operand" "dG")))]
--  "TARGET_HARD_FLOAT && TARGET_FLOAT_SQRT"
--  {
--    if (REGNO (operands[0]) == REGNO (operands[1]))
--      return "fsqrt\t%0,%1";
--    else
--      return "fsqrt\t%0,%1\n\taddk\t%D0,%D1,r0";
--  }
--  [(set_attr "type"     "fsqrt")
--   (set_attr "mode"      "SF")
--   (set_attr "length"    "4")])
--
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
new file mode 100644
index 0000000000..353bfa9054
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch
@@ -0,0 +1,73 @@
+From 802c136f1a41ebfed3b25419e48331038f284e2b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 11 Sep 2018 13:43:48 +0530
+Subject: [PATCH 33/54] [Patch, Microblaze] : Support of multilibs with m64 ...
+
+---
+ gcc/config/microblaze/microblaze-c.c  |  1 +
+ gcc/config/microblaze/t-microblaze    | 15 ++++++---------
+ libgcc/config/microblaze/t-microblaze | 11 +++--------
+ 3 files changed, 10 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
+index dbcd21fc6ee..db543edcbe5 100644
+--- a/gcc/config/microblaze/microblaze-c.c
++++ b/gcc/config/microblaze/microblaze-c.c
+@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
+     }
+   if (TARGET_MB_64)
+     {
++      builtin_define ("__microblaze64");
+       builtin_define ("__arch64__");
+       builtin_define ("__microblaze64__");
+       builtin_define ("__MICROBLAZE64__");
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 9fc80b142ce..35ab9654052 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,12 +1,9 @@
+-MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
+-MULTILIB_DIRNAMES = bs m mh le m64
+-MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
+-MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
+-MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
+-MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
+-MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
++MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
++MULTILIB_DIRNAMES = m64 bs le m mh
++MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
+diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
+index 35021b24b7d..8d954a49575 100644
+--- a/libgcc/config/microblaze/t-microblaze
++++ b/libgcc/config/microblaze/t-microblaze
+@@ -1,16 +1,11 @@
+-LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
+-			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
++LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
+ 
+ LIB2ADD += \
+         $(srcdir)/config/microblaze/divsi3.S \
+-        $(srcdir)/config/microblaze/divdi3.S \
+         $(srcdir)/config/microblaze/modsi3.S \
+-        $(srcdir)/config/microblaze/moddi3.S \
++        $(srcdir)/config/microblaze/muldi3_hard.S \
+         $(srcdir)/config/microblaze/mulsi3.S \
+-        $(srcdir)/config/microblaze/muldi3.S \
+         $(srcdir)/config/microblaze/stack_overflow_exit.S \
+         $(srcdir)/config/microblaze/udivsi3.S \
+-        $(srcdir)/config/microblaze/udivdi3.S \
+         $(srcdir)/config/microblaze/umodsi3.S \
+-        $(srcdir)/config/microblaze/umoddi3.S \
+-        $(srcdir)/config/microblaze/divsi3_table.c \
++        $(srcdir)/config/microblaze/divsi3_table.c
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch
new file mode 100644
index 0000000000..c508b158db
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Fixed-issues-like.patch
@@ -0,0 +1,70 @@
+From 2b2c6e96c3aefc86c880be05d93685a4ce97c9f1 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 14:58:00 +0530
+Subject: [PATCH 34/54] Fixed issues like: 1 Interrupt alignment issue 2 Sign
+ extension issue
+
+---
+ gcc/config/microblaze/microblaze.c  | 16 ++++++++++------
+ gcc/config/microblaze/microblaze.md |  2 +-
+ 2 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 046bfd05558..498c8ca191f 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2177,9 +2177,14 @@ compute_frame_size (HOST_WIDE_INT size)
+ 
+   total_size += gp_reg_size;
+ 
+-  /* Add 4 bytes for MSR.  */
++  /* Add 4/8 bytes for MSR.  */
+   if (microblaze_is_interrupt_variant ())
+-    total_size += 4;
++    {
++      if (TARGET_MB_64)
++        total_size += 8;
++      else
++        total_size += 4;
++    }
+ 
+   /* No space to be allocated for link register in leaf functions with no other
+      stack requirements.  */
+@@ -2464,7 +2469,6 @@ print_operand (FILE * file, rtx op, int letter)
+   else if (letter == 'h' || letter == 'j')
+     {
+       long val[2];
+-      int val1[2];
+       long l[2];
+       if (code == CONST_DOUBLE)
+ 	{
+@@ -2479,10 +2483,10 @@ print_operand (FILE * file, rtx op, int letter)
+ 	}
+       else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
+         {
+-	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
+-	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
++	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
++	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
+         }
+-      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
++      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
+     }
+   else if (code == CONST_DOUBLE)
+     {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 592757baf2f..e7c7cf3e8b5 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1096,7 +1096,7 @@
+       case 1:
+       case 2:
+         {
+-          output_asm_insn ("ll%i1\t%0,%1", operands);
++          output_asm_insn ("lw%i1\t%0,%1", operands);
+           return "sextl32\t%0,%0";
+         }
+     } 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
deleted file mode 100644
index acf14b23ee..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0034-Intial-commit-of-64-bit-Microblaze.patch
+++ /dev/null
@@ -1,844 +0,0 @@
-From 9600049313b095d6d7d8ea46a7ab783fabae71a2 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 3 Apr 2018 16:48:39 +0530
-Subject: [PATCH 34/58] Intial commit of 64-bit Microblaze
-
-Added load store pattern movdi and also adding missing files
----
- gcc/config/microblaze/constraints.md      |   5 +
- gcc/config/microblaze/microblaze-protos.h |   1 +
- gcc/config/microblaze/microblaze.c        | 109 ++++--
- gcc/config/microblaze/microblaze.h        |   4 +-
- gcc/config/microblaze/microblaze.md       | 394 +++++++++++++++++++++-
- gcc/config/microblaze/microblaze.opt      |   7 +-
- gcc/config/microblaze/t-microblaze        |   7 +-
- 7 files changed, 490 insertions(+), 37 deletions(-)
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index b9fc6e3fae2..f636b035280 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -52,6 +52,11 @@
-   (and (match_code "const_int")
-        (match_test "ival > 0 && ival < 0x10000")))
- 
-+(define_constraint "K"
-+  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-+  (and (match_code "const_int")
-+       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
-+
- ;; Define floating point constraints
- 
- (define_constraint "G"
-diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
-index 76ffc682df2..b8a3321dbdf 100644
---- a/gcc/config/microblaze/microblaze-protos.h
-+++ b/gcc/config/microblaze/microblaze-protos.h
-@@ -36,6 +36,7 @@ extern void microblaze_expand_divide (rtx *);
- extern void microblaze_expand_conditional_branch (enum machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_reg (machine_mode, rtx *);
- extern void microblaze_expand_conditional_branch_sf (rtx *); 
-+extern void microblaze_expand_conditional_branch_df (rtx *); 
- extern int microblaze_can_use_return_insn (void);
- extern void print_operand (FILE *, rtx, int);
- extern void print_operand_address (FILE *, rtx);
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 4b5699671e8..8a3ccae558a 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3562,11 +3562,11 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
-   op0 = operands[0];
-   op1 = operands[1];
- 
--  if (!register_operand (op0, SImode)
--      && !register_operand (op1, SImode)
-+  if (!register_operand (op0, mode)
-+      && !register_operand (op1, mode)
-       && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
-     {
--      rtx temp = force_reg (SImode, op1);
-+      rtx temp = force_reg (mode, op1);
-       emit_move_insn (op0, temp);
-       return true;
-     }
-@@ -3631,12 +3631,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
- 	          && (flag_pic == 2 || microblaze_tls_symbol_p (p0)
- 		      || !SMALL_INT (p1)))))
- 	{
--	  rtx temp = force_reg (SImode, p0);
-+	  rtx temp = force_reg (mode, p0);
- 	  rtx temp2 = p1;
- 
- 	  if (flag_pic && reload_in_progress)
- 	    df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
--	  emit_move_insn (op0, gen_rtx_PLUS (SImode, temp, temp2));
-+	  emit_move_insn (op0, gen_rtx_PLUS (mode, temp, temp2));
- 	  return true;
- 	}
-     }
-@@ -3767,7 +3767,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-   rtx cmp_op0 = operands[1];
-   rtx cmp_op1 = operands[2];
-   rtx label1 = operands[3];
--  rtx comp_reg = gen_reg_rtx (SImode);
-+  rtx comp_reg = gen_reg_rtx (mode);
-   rtx condition;
- 
-   gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
-@@ -3776,23 +3776,36 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-   if (cmp_op1 == const0_rtx)
-     {
-       comp_reg = cmp_op0;
--      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-+
-     }
- 
-   else if (code == EQ || code == NE)
-     {
-       /* Use xor for equal/not-equal comparison.  */
--      emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
--      condition = gen_rtx_fmt_ee (signed_condition (code), SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        emit_insn (gen_xorsi3 (comp_reg, cmp_op0, cmp_op1));
-+      else
-+        emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
-+      condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else
-     {
-       /* Generate compare and branch in single instruction. */
-       cmp_op1 = force_reg (mode, cmp_op1);
-       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
--      emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
-+      if (mode == SImode)
-+        emit_jump_insn (gen_branch_compare(condition, cmp_op0, cmp_op1, label1));
-+      else
-+        emit_jump_insn (gen_long_branch_compare(condition, cmp_op0, cmp_op1, label1));
-     }
- }
- 
-@@ -3803,7 +3816,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-   rtx cmp_op0 = operands[1];
-   rtx cmp_op1 = operands[2];
-   rtx label1 = operands[3];
--  rtx comp_reg = gen_reg_rtx (SImode);
-+  rtx comp_reg = gen_reg_rtx (mode);
-   rtx condition;
- 
-   gcc_assert ((GET_CODE (cmp_op0) == REG)
-@@ -3814,30 +3827,63 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code),
--                                  SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+                                  mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else if (code == EQ)
-     {
--      emit_insn (gen_seq_internal_pat (comp_reg,
--                                       cmp_op0, cmp_op1));
--      condition = gen_rtx_EQ (SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        {
-+          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      else
-+        {
-+          emit_insn (gen_seq_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-+ 
-     }
-   else if (code == NE)
-     {
--      emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
--                                       cmp_op1));
--      condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
--      emit_jump_insn (gen_condjump (condition, label1));
-+      if (mode == SImode)
-+        {
-+          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      else
-+        {
-+          emit_insn (gen_sne_internal_pat (comp_reg, cmp_op0,
-+                                           cmp_op1));
-+	}
-+      condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
-+      if (mode == SImode)
-+        emit_jump_insn (gen_condjump (condition, label1));
-+      else
-+        emit_jump_insn (gen_long_condjump (condition, label1));
-     }
-   else
-     {
-       /* Generate compare and branch in single instruction. */
-       cmp_op1 = force_reg (mode, cmp_op1);
-       condition = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1);
--      emit_jump_insn (gen_branch_compare (condition, cmp_op0,
--                                         cmp_op1, label1));
-+      if (mode == SImode)
-+        emit_jump_insn (gen_branch_compare (condition, cmp_op0,
-+                                           cmp_op1, label1));
-+      else 
-+	{
-+          emit_jump_insn (gen_long_branch_compare (condition, cmp_op0,
-+                                             cmp_op1, label1));
-+        }	
-+
-     }
- }
- 
-@@ -3854,6 +3900,19 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
-   emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
-+void
-+microblaze_expand_conditional_branch_df (rtx operands[])
-+{
-+  rtx condition;
-+  rtx cmp_op0 = XEXP (operands[0], 0);
-+  rtx cmp_op1 = XEXP (operands[0], 1);
-+  rtx comp_reg = gen_reg_rtx (DImode);
-+
-+  emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
-+  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
-+  emit_jump_insn (gen_long_condjump (condition, operands[3]));
-+}
-+
- /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
- 
- static bool
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index b5b7b22cec9..4931895e650 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -102,6 +102,7 @@ extern enum pipeline_type microblaze_pipe;
- #define ASM_SPEC "\
- %(target_asm_spec) \
- %{mbig-endian:-EB} \
-+%{m64:-m64} \
- %{mlittle-endian:-EL}"
- 
- /* Extra switches sometimes passed to the linker.  */
-@@ -110,6 +111,7 @@ extern enum pipeline_type microblaze_pipe;
- #define LINK_SPEC "%{shared:-shared} -N -relax \
-   %{mbig-endian:-EB --oformat=elf32-microblaze} \
-   %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
-+  %{m64:-EL --oformat=elf64-microblazeel} \
-   %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
-   %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
-   %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
-@@ -217,7 +219,7 @@ extern enum pipeline_type microblaze_pipe;
- #define MIN_UNITS_PER_WORD      4
- #define INT_TYPE_SIZE           32
- #define SHORT_TYPE_SIZE         16
--#define LONG_TYPE_SIZE          32
-+#define LONG_TYPE_SIZE          64
- #define LONG_LONG_TYPE_SIZE     64
- #define FLOAT_TYPE_SIZE         32
- #define DOUBLE_TYPE_SIZE        64
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a527da70f8a..bcf2b9244f8 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -497,7 +497,6 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
--
- (define_insn "divsf3"
-   [(set (match_operand:SF 0 "register_operand" "=d")
-         (div:SF (match_operand:SF 1 "register_operand" "d")
-@@ -508,6 +507,7 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+
- (define_insn "sqrtsf2"
-   [(set (match_operand:SF 0 "register_operand" "=d")
-         (sqrt:SF (match_operand:SF 1 "register_operand" "d")))]
-@@ -562,6 +562,18 @@
- 
- ;; Adding 2 DI operands in register or reg/imm
- 
-+(define_insn "adddi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
-+		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   addlk\t%0,%z1,%2
-+   addlik\t%0,%z1,%2"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "adddi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-@@ -606,6 +618,18 @@
- ;; Double Precision Subtraction
- ;;----------------------------------------------------------------
- 
-+(define_insn "subdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
-+		  (match_operand:DI 2 "register_operand" "d,n")))]
-+  "TARGET_MB_64"
-+  "@
-+   rsubl\t%0,%2,%1
-+   addlik\t%0,%z1,-%2"
-+  [(set_attr "type"	"darith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "subdi3"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
-@@ -795,6 +819,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "negdi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "rsubl\t%0,%1,r0"
-+  [(set_attr "type"	"darith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "negdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -814,6 +847,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "one_cmpldi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "xorli\t%0,%1,-1"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "*one_cmpldi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -840,6 +882,20 @@
- ;; Logical
- ;;----------------------------------------------------------------
- 
-+(define_insn "anddi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   andl\t%0,%1,%2
-+   andli\t%0,%1,%2 #andl1"
-+  ;; andli\t%0,%1,%2 #andl3
-+  ;; andli\t%0,%1,%2 #andl2
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "andsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- 	(and:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -855,6 +911,18 @@
-   (set_attr "length"	"4,8,8,8")])
- 
- 
-+(define_insn "iordi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ior:DI (match_operand:DI 1 "arith_operand" "d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   orl\t%0,%1,%2
-+   orli\t%0,%1,%2 #andl1"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
- (define_insn "iorsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
- 	(ior:SI (match_operand:SI 1 "arith_operand" "%d,d,d,d")
-@@ -869,6 +937,19 @@
-   (set_attr "mode"	"SI,SI,SI,SI")
-   (set_attr "length"	"4,8,8,8")])
- 
-+(define_insn "xordi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  "TARGET_MB_64"
-+  "@
-+   xorl\t%0,%1,%2
-+   xorli\t%0,%1,%2 #andl1"
-+  [(set_attr "type"	"arith,arith")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")])
-+
-+
- (define_insn "xorsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- 	(xor:SI (match_operand:SI 1 "arith_operand" "%d,d,d")
-@@ -937,6 +1018,26 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+;;(define_expand "extendqidi2"
-+;;  [(set (match_operand:DI 0 "register_operand" "=d")
-+;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
-+;;  "TARGET_MB_64"
-+;;  {
-+;;	if (GET_CODE (operands[1]) != REG)
-+;;	FAIL;
-+;;   }
-+;;)
-+    
-+
-+;;(define_insn "extendqidi2"
-+;;  [(set (match_operand:DI 0 "register_operand" "=d")
-+;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
-+;;  "TARGET_MB_64"
-+;;  "sextl8\t%0,%1"
-+;;  [(set_attr "type"	"arith")
-+;;  (set_attr "mode"	"DI")
-+;;  (set_attr "length"	"4")])
-+
- (define_insn "extendhisi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -946,6 +1047,16 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "extendhidi2"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(sign_extend:DI (match_operand:HI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "sextl16\t%0,%1"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+
- ;; Those for integer source operand are ordered
- ;; widest source type first.
- 
-@@ -1011,6 +1122,31 @@
- )
- 
- 
-+(define_insn "*movdi_internal_64"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
-+	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
-+  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
-+  { 
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "addlk\t%0,%1";
-+      case 1:
-+	return "addlik\t%0,r0,%1";
-+      case 2:
-+	  return "addlk\t%0,r0,r0";
-+      case 3:
-+      case 4:
-+	  return "lli\t%0,%1";
-+      case 5:
-+      case 6:
-+        return "sli\t%1,%0";
-+    }
-+    return "unreachable";
-+  }
-+  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"   "8,8,8,8,12,8,12")])
- 
- (define_insn "*movdi_internal"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
-@@ -1423,6 +1559,36 @@
-   (set_attr "length"	"4,4")]
- )
- 
-+;; Barrel shift left
-+(define_expand "ashldi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(ashift:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "ashldi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+  bsllli\t%0,%1,%2
-+  bslll\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+)
- ;; The following patterns apply when there is no barrel shifter present
- 
- (define_insn "*ashlsi3_with_mul_delay"
-@@ -1548,6 +1714,36 @@
- ;;----------------------------------------------------------------
- ;; 32-bit right shifts
- ;;----------------------------------------------------------------
-+;; Barrel shift left
-+(define_expand "ashrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "ashrdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+   bslrai\t%0,%1,%2
-+   bslra\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+  )
- (define_expand "ashrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -1657,6 +1853,36 @@
- ;;----------------------------------------------------------------
- ;; 32-bit right shifts (logical)
- ;;----------------------------------------------------------------
-+;; Barrel shift left
-+(define_expand "lshrdi3"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
-+                   (match_operand:DI 2 "arith_operand"    "")))]
-+"TARGET_MB_64"
-+{
-+;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+  {
-+    emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else
-+  FAIL;
-+}    
-+)
-+
-+(define_insn "lshrdi3_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-+                   (match_operand:DI 2 "arith_operand"    "I,d")))]
-+  "TARGET_MB_64"
-+  "@
-+   bslrli\t%0,%1,%2
-+   bslrl\t%0,%1,%2"
-+  [(set_attr "type"	"bshift,bshift")
-+  (set_attr "mode"	"DI,DI")
-+  (set_attr "length"	"4,4")]
-+  )
- 
- (define_expand "lshrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
-@@ -1803,6 +2029,8 @@
-   (set_attr "length"	"4")]
- )              
- 
-+
-+
- ;;----------------------------------------------------------------
- ;; Setting a register from an floating point comparison. 
- ;;----------------------------------------------------------------
-@@ -1818,6 +2046,18 @@
-    (set_attr "length"    "4")]
- )
- 
-+(define_insn "cstoredf4"
-+   [(set (match_operand:DI 0 "register_operand" "=r")
-+        (match_operator:DI 1 "ordered_comparison_operator"
-+	      [(match_operand:DF 2 "register_operand" "r")
-+	       (match_operand:DF 3 "register_operand" "r")]))]
-+  "TARGET_MB_64"
-+  "dcmp.%C1\t%0,%3,%2"
-+  [(set_attr "type"     "fcmp")
-+   (set_attr "mode"      "DF")
-+   (set_attr "length"    "4")]
-+)
-+
- ;;----------------------------------------------------------------
- ;; Conditional branches
- ;;----------------------------------------------------------------
-@@ -1930,6 +2170,115 @@
-    (set_attr "length"   "12")]
- )
- 
-+
-+(define_expand "cbranchdi4"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "ordered_comparison_operator"
-+                       [(match_operand:DI 1 "register_operand")
-+                        (match_operand:DI 2 "arith_operand" "I,i")])
-+                      (label_ref (match_operand 3 ""))
-+                      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch (DImode, operands);
-+  DONE;
-+})
-+
-+(define_expand "cbranchdi4_reg"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "ordered_comparison_operator"
-+                       [(match_operand:DI 1 "register_operand")
-+                        (match_operand:DI 2 "register_operand")])
-+                      (label_ref (match_operand 3 ""))
-+                      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch_reg (DImode, operands);
-+  DONE;
-+})
-+
-+(define_expand "cbranchdf4"
-+  [(set (pc)
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-+		       [(match_operand:DF 1 "register_operand")
-+		        (match_operand:DF 2 "register_operand")])
-+		      (label_ref (match_operand 3 ""))
-+		      (pc)))]
-+  "TARGET_MB_64"
-+{
-+  microblaze_expand_conditional_branch_df (operands);
-+  DONE;
-+
-+})
-+
-+;; Used to implement comparison instructions
-+(define_expand "long_condjump"
-+  [(set (pc)
-+	(if_then_else (match_operand 0)
-+		      (label_ref (match_operand 1))
-+		      (pc)))])
-+
-+(define_insn "long_branch_zero"
-+  [(set (pc)
-+	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
-+  				 [(match_operand:DI 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand:DI 2 "pc_or_label_operand" "")
-+                      (match_operand:DI 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "beal%C0i%?\t%z1,%2";
-+    else 
-+      return "beal%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
-+(define_insn "long_branch_compare"
-+  [(set (pc)
-+        (if_then_else (match_operator:DI 0 "cmp_op"
-+                                         [(match_operand:DI 1 "register_operand" "d")
-+                                          (match_operand:DI 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:DI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
-+    return "beal%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
-@@ -2478,17 +2827,33 @@
-   DONE;
- }")
- 
--(define_expand "extzvsi"
-+(define_expand "extvsi"
-   [(set (match_operand:SI 0 "register_operand" "r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
- 			 (match_operand:SI 3 "immediate_operand" "I")))]
- "TARGET_HAS_BITFIELD"
--""
--)
--
-+"
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[2]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[3]);
-+
-+  if ((len == 0) || (pos + len > 32) )
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[1], VOIDmode))
-+  ;;  FAIL;
-+  if (operands[0] == operands[1])
-+  FAIL;
-+  if (GET_CODE (operands[1]) == ASHIFT)
-+  FAIL;
-+;;  operands[2] = GEN_INT(INTVAL(operands[2])+1 );
-+ emit_insn (gen_extv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
- 
--(define_insn "extzv_32"
-+(define_insn "extv_32"
-   [(set (match_operand:SI 0 "register_operand" "=r")
- 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- 			 (match_operand:SI 2 "immediate_operand" "I")
-@@ -2505,8 +2870,21 @@
- 			 (match_operand:SI 2 "immediate_operand" "I"))
- 	(match_operand:SI 3 "register_operand" "r"))]
-  "TARGET_HAS_BITFIELD"
--""
--)
-+  "
-+{
-+  unsigned HOST_WIDE_INT len = UINTVAL (operands[1]);
-+  unsigned HOST_WIDE_INT pos = UINTVAL (operands[2]);
-+
-+  if (len <= 0 || pos + len > 32)
-+    FAIL;
-+
-+  ;;if (!register_operand (operands[0], VOIDmode))
-+  ;;  FAIL;
-+
-+  emit_insn (gen_insv_32 (operands[0], operands[1],
-+			  operands[2], operands[3]));
-+  DONE;
-+}")
- 
- (define_insn "insv_32"
-   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
-diff --git a/gcc/config/microblaze/microblaze.opt b/gcc/config/microblaze/microblaze.opt
-index a29c6f8df90..bbe48b06da6 100644
---- a/gcc/config/microblaze/microblaze.opt
-+++ b/gcc/config/microblaze/microblaze.opt
-@@ -136,4 +136,9 @@ Target
- 
- mxl-frequency
- Target Mask(AREA_OPTIMIZED_2)
--Use 8 stage pipeline (frequency optimization)
-+Use 8 stage pipeline (frequency optimization).
-+
-+m64
-+Target Mask(MB_64)
-+MicroBlaze 64-bit mode.
-+
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 41fa9a92081..7671f63c5b5 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,8 +1,11 @@
--MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian
--MULTILIB_DIRNAMES = bs m mh le
-+MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
-+MULTILIB_DIRNAMES = bs m mh le m64
- MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
- MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
-+#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch
new file mode 100644
index 0000000000..61d352617f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Fixed-below-issues.patch
@@ -0,0 +1,307 @@
+From 051d744c06ed3f11f603e37768eece57784c2583 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 26 Nov 2019 17:26:15 +0530
+Subject: [PATCH 35/54] Fixed below issues:
+
+- Floating point print issues in 64bit mode
+- Dejagnu Jump related issues
+- Added dbl instruction
+
+Conflicts:
+	gcc/config/microblaze/microblaze.md
+---
+ gcc/config/microblaze/microblaze.c  | 12 +++-
+ gcc/config/microblaze/microblaze.h  |  7 +++
+ gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++-----
+ libgcc/config/microblaze/crti.S     | 24 +++++++-
+ libgcc/config/microblaze/crtn.S     | 13 +++++
+ 5 files changed, 125 insertions(+), 17 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 498c8ca191f..e32de46fa62 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2473,7 +2473,12 @@ print_operand (FILE * file, rtx op, int letter)
+       if (code == CONST_DOUBLE)
+ 	{
+ 	  if (GET_MODE (op) == DFmode)
+-	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++            {
++  	      if (TARGET_MB_64)
++	        REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++	      else
++	        REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
++	    }
+ 	  else
+ 	    {
+ 	      REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
+@@ -3876,7 +3881,10 @@ microblaze_expand_divide (rtx operands[])
+                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
+ 
+   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
+-  jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
++  if (TARGET_MB_64) 
++    jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
++  else 
++    jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
+   JUMP_LABEL (jump) = div_end_label;
+   LABEL_NUSES (div_end_label) = 1; 
+   emit_barrier ();
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index f6ad4d9fc21..60c552958b8 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -888,10 +888,17 @@ do {									 \
+ /* We do this to save a few 10s of code space that would be taken up
+    by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
+    definition in crtstuff.c.  */
++#ifdef __arch64__
++#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
++    asm ( SECTION_OP "\n"                               \
++          "\tbrealid   r15, " #FUNC "\n\t nop\n"         \
++          TEXT_SECTION_ASM_OP);
++#else
+ #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
+     asm ( SECTION_OP "\n"                               \
+           "\tbrlid   r15, " #FUNC "\n\t nop\n"         \
+           TEXT_SECTION_ASM_OP);
++#endif
+ 
+ /* We need to group -lm as well, since some Newlib math functions 
+    reference __errno!  */
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index e7c7cf3e8b5..74bb30cb9e8 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -527,6 +527,15 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "floatdidf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (float:DF (match_operand:DI 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dbl\t%0,%1"
++  [(set_attr "type"     "fcvt")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
+ (define_insn "fix_truncsfsi2"
+   [(set (match_operand:SI 0 "register_operand" "=d")
+         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+@@ -1301,7 +1310,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  ""
++  "TARGET_MB_64"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1584,7 +1593,7 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -2374,9 +2383,9 @@ else
+ 
+ (define_insn "long_branch_compare"
+   [(set (pc)
+-        (if_then_else (match_operator 0 "cmp_op"
+-                                         [(match_operand 1 "register_operand" "d")
+-                                          (match_operand 2 "register_operand" "d")
++        (if_then_else (match_operator:DI 0 "cmp_op"
++                                         [(match_operand:DI 1 "register_operand" "d")
++                                          (match_operand:DI 2 "register_operand" "d")
+                                          ])
+                       (label_ref (match_operand 3))
+                       (pc)))
+@@ -2498,6 +2507,20 @@ else
+ ;;----------------------------------------------------------------
+ ;; Unconditional branches
+ ;;----------------------------------------------------------------
++(define_insn "jump_64"
++  [(set (pc)
++	(label_ref (match_operand 0 "" "")))]
++  "TARGET_MB_64"
++  {
++    if (GET_CODE (operands[0]) == REG)
++        return "brea%?\t%0";
++    else	
++        return "breai%?\t%l0";
++  }
++  [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_insn "jump"
+   [(set (pc)
+ 	(label_ref (match_operand 0 "" "")))]
+@@ -2543,17 +2566,25 @@ else
+   {
+     //gcc_assert (GET_MODE (operands[0]) == Pmode);
+ 
+-    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
+-      emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+-    else
+-      emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
++    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
++        if (!TARGET_MB_64)
++          emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
++        else
++          emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
++      }
++    else {
++        if (!TARGET_MB_64)
++          emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
++        else
++          emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
++      }
+     DONE;
+   }
+ )
+ 
+ (define_insn "tablejump_internal1"
+   [(set (pc)
+-	(match_operand 0 "register_operand" "d"))
++	(match_operand:SI 0 "register_operand" "d"))
+   (use (label_ref (match_operand 1 "" "")))]
+   ""
+   "bra%?\t%0 "
+@@ -2561,11 +2592,21 @@ else
+   (set_attr "mode"	"none")
+   (set_attr "length"	"4")])
+ 
++(define_insn "tablejump_internal2"
++  [(set (pc)
++	(match_operand:DI 0 "register_operand" "d"))
++  (use (label_ref (match_operand 1 "" "")))]
++  "TARGET_MB_64"
++  "bra%?\t%0 "
++  [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
+ (define_expand "tablejump_internal3"
+   [(parallel [(set (pc)
+-		   (plus (match_operand 0 "register_operand" "d")
+-			    (label_ref (match_operand:SI 1 "" ""))))
+-             (use (label_ref (match_dup 1)))])]
++		   (plus:SI (match_operand:SI 0 "register_operand" "d")
++			    (label_ref:SI (match_operand:SI 1 "" ""))))
++             (use (label_ref:SI (match_dup 1)))])]
+   ""
+   ""
+ )
+@@ -2596,6 +2637,23 @@ else
+   ""
+ )
+ 
++(define_insn ""
++ [(set (pc)
++	(plus:DI (match_operand:DI 0 "register_operand" "d")
++		 (label_ref:DI (match_operand 1 "" ""))))
++  (use (label_ref:DI (match_dup 1)))]
++ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
++  && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
++  && flag_pic"
++  {
++    output_asm_insn ("addlk\t%0,%0,r20",operands);
++    return "bra%?\t%0";
++}
++ [(set_attr "type"	"jump")
++  (set_attr "mode"	"none")
++  (set_attr "length"	"4")])
++
++
+ ;;----------------------------------------------------------------
+ ;; Function prologue/epilogue and stack allocation
+ ;;----------------------------------------------------------------
+@@ -3102,7 +3160,7 @@ else
+ ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
+ ;; between "mfs" and "addik" instructions.
+ (define_insn "set_got"
+-  [(set (match_operand:SI 0 "register_operand" "=r")
++  [(set (match_operand 0 "register_operand" "=r")
+     (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
+   ""
+   "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
+diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
+index 005825f1ec5..b7436c7131f 100644
+--- a/libgcc/config/microblaze/crti.S
++++ b/libgcc/config/microblaze/crti.S
+@@ -33,11 +33,32 @@
+     .section .init, "ax"
+     .global __init
+ 
++#ifdef __arch64__
+     .weak _stack
+-    .set  _stack, 0xffffffff
++    .set  _stack, 0xffffffffffffffff
+     .weak _stack_end
+     .set  _stack_end, 0
+ 
++    .align 3
++__init: 
++    addlik  r1, r1, -32
++    sl      r15, r0, r1
++    addlik  r11, r0, _stack
++    mts     rshr, r11
++    addlik  r11, r0, _stack_end
++    mts     rslr, r11
++
++    .section .fini, "ax"
++    .global __fini
++    .align 3
++__fini: 
++    addlik   r1, r1, -32
++    sl       r15, r0, r1
++#else
++    .weak _stack
++    .set  _stack, 0xffffffff
++    .weak _stack_end
++    .set  _stack_end, 0
+     .align 2
+ __init: 
+     addik   r1, r1, -16
+@@ -53,3 +74,4 @@ __init:
+ __fini: 
+     addik   r1, r1, -16
+     sw      r15, r0, r1
++#endif
+diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
+index 5705eff9a4a..f1148ffebe4 100644
+--- a/libgcc/config/microblaze/crtn.S
++++ b/libgcc/config/microblaze/crtn.S
+@@ -29,7 +29,19 @@
+ .section .note.GNU-stack,"",%progbits
+ .previous
+ #endif
++#ifdef __arch64__
++    .section .init, "ax"
++    ll      r15, r0, r1
++    addlik   r1, r1, 32
++    rtsd    r15, 8
++    nop 
+ 
++    .section .fini, "ax"
++    ll      r15, r0, r1
++    addlik   r1, r1, 32   
++    rtsd    r15, 8
++    nop 
++#else
+     .section .init, "ax"
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+@@ -39,3 +51,4 @@
+     lw      r15, r0, r1
+     rtsd    r15, 8 
+     addik   r1, r1, 16   
++#endif
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch
deleted file mode 100644
index e7872d54e8..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0035-Intial-commit-for-64bit-MB-sources.patch
+++ /dev/null
@@ -1,2463 +0,0 @@
-From 8660e76d664ee4b42a83a4c15344b072d3c879df Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 27 Jul 2018 15:23:41 +0530
-Subject: [PATCH 35/58] Intial commit for 64bit-MB sources.
-
-Need to cleanup the code later.
----
- gcc/config/microblaze/constraints.md    |   2 +-
- gcc/config/microblaze/microblaze-c.c    |   6 +
- gcc/config/microblaze/microblaze.c      | 218 ++++++---
- gcc/config/microblaze/microblaze.h      |  63 ++-
- gcc/config/microblaze/microblaze.md     | 606 ++++++++++++++++++------
- gcc/config/microblaze/t-microblaze      |   7 +-
- libgcc/config/microblaze/crti.S         |   4 +-
- libgcc/config/microblaze/crtn.S         |   4 +-
- libgcc/config/microblaze/divdi3.S       |  98 ++++
- libgcc/config/microblaze/divdi3_table.c |  62 +++
- libgcc/config/microblaze/moddi3.S       |  97 ++++
- libgcc/config/microblaze/muldi3.S       |  73 +++
- libgcc/config/microblaze/t-microblaze   |  11 +-
- libgcc/config/microblaze/udivdi3.S      | 107 +++++
- libgcc/config/microblaze/umoddi3.S      | 110 +++++
- 15 files changed, 1232 insertions(+), 236 deletions(-)
- create mode 100644 libgcc/config/microblaze/divdi3.S
- create mode 100644 libgcc/config/microblaze/divdi3_table.c
- create mode 100644 libgcc/config/microblaze/moddi3.S
- create mode 100644 libgcc/config/microblaze/muldi3.S
- create mode 100644 libgcc/config/microblaze/udivdi3.S
- create mode 100644 libgcc/config/microblaze/umoddi3.S
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index f636b035280..c2b0a21c53b 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -55,7 +55,7 @@
- (define_constraint "K"
-   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-   (and (match_code "const_int")
--       (match_test "ival > (long)0xffffff8000000000L && ival < (long)0x0000007fffffffffL")))
-+       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
- 
- ;; Define floating point constraints
- 
-diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index d8c88e510e5..dbcd21fc6ee 100644
---- a/gcc/config/microblaze/microblaze-c.c
-+++ b/gcc/config/microblaze/microblaze-c.c
-@@ -100,4 +100,10 @@ microblaze_cpp_define (cpp_reader *pfile)
-         builtin_define ("HAVE_HW_FPU_SQRT");
-       builtin_define ("__HAVE_HW_FPU_SQRT__");
-     }
-+  if (TARGET_MB_64)
-+    {
-+      builtin_define ("__arch64__");
-+      builtin_define ("__microblaze64__");
-+      builtin_define ("__MICROBLAZE64__");
-+    }
- }  
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 8a3ccae558a..3ecda553fe6 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -383,10 +383,10 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
- 	{
- 	  return 1;
- 	}
--      else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
-+      /*else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
- 	{
- 	  return 1;
--	}
-+	}*/
-       else
- 	return 0;
- 
-@@ -434,7 +434,7 @@ double_memory_operand (rtx op, machine_mode mode)
-     return 1;
- 
-   return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
--			    ? E_SImode : E_SFmode),
-+			    ? Pmode : E_SFmode),
- 			   plus_constant (Pmode, addr, 4));
- }
- 
-@@ -681,7 +681,7 @@ microblaze_legitimize_tls_address(rtx x, rtx reg)
-          /* Load the addend.  */
-          addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_DTPREL)),
- 				  UNSPEC_TLS);
--         addend = force_reg (SImode, gen_rtx_CONST (SImode, addend));
-+         addend = force_reg (Pmode, gen_rtx_CONST (Pmode, addend));
-          dest = gen_rtx_PLUS (Pmode, dest, addend);
-          break;
- 
-@@ -699,7 +699,7 @@ microblaze_classify_unspec (struct microblaze_address_info *info, rtx x)
- 
-   if (XINT (x, 1) == UNSPEC_GOTOFF)
-     {
--      info->regA = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
-+      info->regA = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
-       info->type = ADDRESS_GOTOFF;
-     }
-   else if (XINT (x, 1) == UNSPEC_PLT)
-@@ -1302,8 +1302,16 @@ microblaze_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
-   emit_move_insn (dest_reg, plus_constant (Pmode, dest_reg, MAX_MOVE_BYTES));
- 
-   /* Emit the test & branch.  */
--  emit_insn (gen_cbranchsi4 (gen_rtx_NE (SImode, src_reg, final_src),
-+
-+  if (TARGET_MB_64) {
-+    emit_insn (gen_cbranchdi4 (gen_rtx_NE (Pmode, src_reg, final_src),
-+			     src_reg, final_src, label));
-+    }
-+  else {
-+    emit_insn (gen_cbranchsi4 (gen_rtx_NE (Pmode, src_reg, final_src),
- 			     src_reg, final_src, label));
-+  
-+    }
- 
-   /* Mop up any left-over bytes.  */
-   if (leftover)
-@@ -1633,14 +1641,20 @@ microblaze_function_arg_advance (cumulative_args_t cum_v,
-       break;
- 
-     case E_DFmode:
--      cum->arg_words += 2;
-+      if (TARGET_MB_64)
-+       cum->arg_words++;
-+      else
-+       cum->arg_words += 2;
-       if (!cum->gp_reg_found && cum->arg_number <= 2)
- 	cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
-       break;
- 
-     case E_DImode:
-       cum->gp_reg_found = 1;
--      cum->arg_words += 2;
-+      if (TARGET_MB_64)
-+       cum->arg_words++;
-+      else
-+       cum->arg_words += 2;
-       break;
- 
-     case E_QImode:
-@@ -2285,7 +2299,7 @@ compute_frame_size (HOST_WIDE_INT size)
- 
- 	  if (regno != MB_ABI_SUB_RETURN_ADDR_REGNUM)
- 	    /* Don't account for link register. It is accounted specially below.  */
--	    gp_reg_size += GET_MODE_SIZE (SImode);
-+	    gp_reg_size += GET_MODE_SIZE (Pmode);
- 
- 	  mask |= (1L << (regno - GP_REG_FIRST));
- 	}
-@@ -2554,7 +2568,7 @@ print_operand (FILE * file, rtx op, int letter)
- 
-       if ((letter == 'M' && !WORDS_BIG_ENDIAN)
- 	  || (letter == 'L' && WORDS_BIG_ENDIAN) || letter == 'D')
--	regnum++;
-+	regnum++; 
- 
-       fprintf (file, "%s", reg_names[regnum]);
-     }
-@@ -2580,6 +2594,7 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
-+      int val1[2];
-       long l[2];
-       if (code == CONST_DOUBLE)
- 	{
-@@ -2592,12 +2607,12 @@ print_operand (FILE * file, rtx op, int letter)
-               val[0] = l[WORDS_BIG_ENDIAN != 0];
- 	    }
- 	}
--      else if (code == CONST_INT)
-+      else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
-         {
--	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
--	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
-+	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
-+	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
-         }
--      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-+      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
-     }
-   else if (code == CONST_DOUBLE)
-     {
-@@ -2791,7 +2806,10 @@ microblaze_asm_constructor (rtx symbol ATTRIBUTE_UNUSED, int priority)
- 
-     switch_to_section (get_section (section, 0, NULL));
-     assemble_align (POINTER_SIZE);
--    fputs ("\t.word\t", asm_out_file);
-+    if (TARGET_MB_64)
-+      fputs ("\t.dword\t", asm_out_file);
-+    else
-+      fputs ("\t.word\t", asm_out_file);
-     output_addr_const (asm_out_file, symbol);
-     fputs ("\n", asm_out_file);
- }
-@@ -2814,7 +2832,10 @@ microblaze_asm_destructor (rtx symbol, int priority)
- 
-     switch_to_section (get_section (section, 0, NULL));
-     assemble_align (POINTER_SIZE);
--    fputs ("\t.word\t", asm_out_file);
-+    if (TARGET_MB_64)
-+      fputs ("\t.dword\t", asm_out_file);
-+    else
-+     fputs ("\t.word\t", asm_out_file);
-     output_addr_const (asm_out_file, symbol);
-     fputs ("\n", asm_out_file);
- }
-@@ -2880,7 +2901,7 @@ save_restore_insns (int prologue)
-   /* For interrupt_handlers, need to save/restore the MSR.  */
-   if (microblaze_is_interrupt_variant ())
-     {
--      isr_mem_rtx = gen_rtx_MEM (SImode,
-+      isr_mem_rtx = gen_rtx_MEM (Pmode,
- 				 gen_rtx_PLUS (Pmode, base_reg_rtx,
- 					       GEN_INT (current_frame_info.
- 							gp_offset -
-@@ -2888,8 +2909,8 @@ save_restore_insns (int prologue)
- 
-       /* Do not optimize in flow analysis.  */
-       MEM_VOLATILE_P (isr_mem_rtx) = 1;
--      isr_reg_rtx = gen_rtx_REG (SImode, MB_ABI_MSR_SAVE_REG);
--      isr_msr_rtx = gen_rtx_REG (SImode, ST_REG);
-+      isr_reg_rtx = gen_rtx_REG (Pmode, MB_ABI_MSR_SAVE_REG);
-+      isr_msr_rtx = gen_rtx_REG (Pmode, ST_REG);
-     }
- 
-   if (microblaze_is_interrupt_variant () && !prologue)
-@@ -2897,8 +2918,8 @@ save_restore_insns (int prologue)
-       emit_move_insn (isr_reg_rtx, isr_mem_rtx);
-       emit_move_insn (isr_msr_rtx, isr_reg_rtx);
-       /* Do not optimize in flow analysis.  */
--      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
--      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
-     }
- 
-   for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
-@@ -2909,9 +2930,9 @@ save_restore_insns (int prologue)
- 	    /* Don't handle here. Already handled as the first register.  */
- 	    continue;
- 
--	  reg_rtx = gen_rtx_REG (SImode, regno);
-+	  reg_rtx = gen_rtx_REG (Pmode, regno);
- 	  insn = gen_rtx_PLUS (Pmode, base_reg_rtx, GEN_INT (gp_offset));
--	  mem_rtx = gen_rtx_MEM (SImode, insn);
-+	  mem_rtx = gen_rtx_MEM (Pmode, insn);
- 	  if (microblaze_is_interrupt_variant () || save_volatiles)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
-@@ -2926,7 +2947,7 @@ save_restore_insns (int prologue)
- 	      insn = emit_move_insn (reg_rtx, mem_rtx);
- 	    }
- 
--	  gp_offset += GET_MODE_SIZE (SImode);
-+	  gp_offset += GET_MODE_SIZE (Pmode);
- 	}
-     }
- 
-@@ -2936,8 +2957,8 @@ save_restore_insns (int prologue)
-       emit_move_insn (isr_mem_rtx, isr_reg_rtx);
- 
-       /* Do not optimize in flow analysis.  */
--      emit_insn (gen_rtx_USE (SImode, isr_reg_rtx));
--      emit_insn (gen_rtx_USE (SImode, isr_msr_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_reg_rtx));
-+      emit_insn (gen_rtx_USE (Pmode, isr_msr_rtx));
-     }
- 
-   /* Done saving and restoring */
-@@ -3027,7 +3048,10 @@ microblaze_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
- 
-   switch_to_section (s);
-   assemble_align (POINTER_SIZE);
--  fputs ("\t.word\t", asm_out_file);
-+  if (TARGET_MB_64)
-+    fputs ("\t.dword\t", asm_out_file);
-+  else
-+    fputs ("\t.word\t", asm_out_file);
-   output_addr_const (asm_out_file, symbol);
-   fputs ("\n", asm_out_file);
- }
-@@ -3171,10 +3195,10 @@ microblaze_expand_prologue (void)
- 	{
- 	  if (offset != 0)
- 	    ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
--	  emit_move_insn (gen_rtx_MEM (SImode, ptr),
--			  gen_rtx_REG (SImode, regno));
-+	  emit_move_insn (gen_rtx_MEM (Pmode, ptr),
-+			  gen_rtx_REG (Pmode, regno));
- 
--	  offset += GET_MODE_SIZE (SImode);
-+	  offset += GET_MODE_SIZE (Pmode);
- 	}
-     }
- 
-@@ -3183,15 +3207,23 @@ microblaze_expand_prologue (void)
-       rtx fsiz_rtx = GEN_INT (fsiz);
- 
-       rtx_insn *insn = NULL;
--      insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-+         if (TARGET_MB_64)
-+           {
-+              
-+             insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
- 				    fsiz_rtx));
-+           }
-+         else { 
-+             insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-+				    fsiz_rtx));
-+           }
-       if (insn)
- 	RTX_FRAME_RELATED_P (insn) = 1;
- 
-       /* Handle SUB_RETURN_ADDR_REGNUM specially at first.  */
-       if (!crtl->is_leaf || interrupt_handler)
- 	{
--	  mem_rtx = gen_rtx_MEM (SImode,
-+	  mem_rtx = gen_rtx_MEM (Pmode,
- 				 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
- 					       const0_rtx));
- 
-@@ -3199,7 +3231,7 @@ microblaze_expand_prologue (void)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
- 
--	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
- 	  insn = emit_move_insn (mem_rtx, reg_rtx);
- 	  RTX_FRAME_RELATED_P (insn) = 1;
- 	}
-@@ -3309,12 +3341,12 @@ microblaze_expand_epilogue (void)
-       if (!crtl->is_leaf || interrupt_handler)
- 	{
- 	  mem_rtx =
--	    gen_rtx_MEM (SImode,
-+	    gen_rtx_MEM (Pmode,
- 			 gen_rtx_PLUS (Pmode, stack_pointer_rtx, const0_rtx));
- 	  if (interrupt_handler)
- 	    /* Do not optimize in flow analysis.  */
- 	    MEM_VOLATILE_P (mem_rtx) = 1;
--	  reg_rtx = gen_rtx_REG (SImode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+	  reg_rtx = gen_rtx_REG (Pmode, MB_ABI_SUB_RETURN_ADDR_REGNUM);
- 	  emit_move_insn (reg_rtx, mem_rtx);
- 	}
- 
-@@ -3330,15 +3362,25 @@ microblaze_expand_epilogue (void)
-       /* _restore_ registers for epilogue.  */
-       save_restore_insns (0);
-       emit_insn (gen_blockage ());
--      emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-+      if (TARGET_MB_64)
-+        emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-+      else
-+        emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, fsiz_rtx));
-     }
- 
-   if (crtl->calls_eh_return)
--    emit_insn (gen_addsi3 (stack_pointer_rtx,
-+      if (TARGET_MB_64) {
-+          emit_insn (gen_adddi3 (stack_pointer_rtx,
-                            stack_pointer_rtx,
--                           gen_raw_REG (SImode,
-+                           gen_raw_REG (Pmode,
- 					MB_EH_STACKADJ_REGNUM)));
--
-+        }
-+      else {
-+          emit_insn (gen_addsi3 (stack_pointer_rtx,
-+                           stack_pointer_rtx,
-+                           gen_raw_REG (Pmode,
-+					MB_EH_STACKADJ_REGNUM)));
-+        }
-   emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, GP_REG_FIRST +
- 						    MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- }
-@@ -3505,9 +3547,14 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-   else
-     this_rtx = gen_rtx_REG (Pmode, MB_ABI_FIRST_ARG_REGNUM);
- 
--  /* Apply the constant offset, if required.  */
-+  /* Apply the constant offset, if required. */ 
-   if (delta)
--    emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
-+    {
-+      if (TARGET_MB_64)
-+        emit_insn (gen_adddi3 (this_rtx, this_rtx, GEN_INT (delta))); 
-+      else
-+        emit_insn (gen_addsi3 (this_rtx, this_rtx, GEN_INT (delta)));
-+    } 
- 
-   /* Apply the offset from the vtable, if required.  */
-   if (vcall_offset)
-@@ -3520,7 +3567,10 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
-     rtx loc = gen_rtx_PLUS (Pmode, temp1, vcall_offset_rtx);
-     emit_move_insn (temp1, gen_rtx_MEM (Pmode, loc));
- 
--    emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
-+    if (TARGET_MB_64)
-+      emit_insn (gen_adddi3 (this_rtx, this_rtx, temp1));
-+    else
-+      emit_insn (gen_addsi3 (this_rtx, this_rtx, temp1));
-   }
- 
-   /* Generate a tail call to the target function.  */
-@@ -3696,7 +3746,7 @@ microblaze_eh_return (rtx op0)
- /* Queue an .ident string in the queue of top-level asm statements.
-    If the string size is below the threshold, put it into .sdata2.
-    If the front-end is done, we must be being called from toplev.c.
--   In that case, do nothing.  */
-+   In that case, do nothing. */ 
- void 
- microblaze_asm_output_ident (const char *string)
- {
-@@ -3751,9 +3801,9 @@ microblaze_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
-   emit_block_move (m_tramp, assemble_trampoline_template (),
- 		   GEN_INT (6*UNITS_PER_WORD), BLOCK_OP_NORMAL);
- 
--  mem = adjust_address (m_tramp, SImode, 16);
-+  mem = adjust_address (m_tramp, Pmode, 16);
-   emit_move_insn (mem, chain_value);
--  mem = adjust_address (m_tramp, SImode, 20);
-+  mem = adjust_address (m_tramp, Pmode, 20);
-   emit_move_insn (mem, fnaddr);
- }
- 
-@@ -3777,7 +3827,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == SImode)
-+      if (mode == Pmode)
-         emit_jump_insn (gen_condjump (condition, label1));
-       else
-         emit_jump_insn (gen_long_condjump (condition, label1));
-@@ -3896,7 +3946,7 @@ microblaze_expand_conditional_branch_sf (rtx operands[])
-   rtx comp_reg = gen_reg_rtx (SImode);
- 
-   emit_insn (gen_cstoresf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
--  condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
-+  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
-   emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
-@@ -3906,10 +3956,10 @@ microblaze_expand_conditional_branch_df (rtx operands[])
-   rtx condition;
-   rtx cmp_op0 = XEXP (operands[0], 0);
-   rtx cmp_op1 = XEXP (operands[0], 1);
--  rtx comp_reg = gen_reg_rtx (DImode);
-+  rtx comp_reg = gen_reg_rtx (Pmode);
- 
-   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
--  condition = gen_rtx_NE (DImode, comp_reg, const0_rtx);
-+  condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
-   emit_jump_insn (gen_long_condjump (condition, operands[3]));
- }
- 
-@@ -3930,8 +3980,8 @@ microblaze_expand_divide (rtx operands[])
- {
-   /* Table lookup software divides. Works for all (nr/dr) where (0 <= nr,dr <= 15).  */
- 
--  rtx regt1 = gen_reg_rtx (SImode); 
--  rtx reg18 = gen_rtx_REG (SImode, R_TMP);
-+  rtx regt1 = gen_reg_rtx (Pmode); 
-+  rtx reg18 = gen_rtx_REG (Pmode, R_TMP);
-   rtx regqi = gen_reg_rtx (QImode);
-   rtx_code_label *div_label = gen_label_rtx ();
-   rtx_code_label *div_end_label = gen_label_rtx ();
-@@ -3939,17 +3989,31 @@ microblaze_expand_divide (rtx operands[])
-   rtx mem_rtx;
-   rtx ret;
-   rtx_insn *jump, *cjump, *insn;
--
--  insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
--  cjump = emit_jump_insn_after (gen_cbranchsi4 (
--					gen_rtx_GTU (SImode, regt1, GEN_INT (15)), 
-+ 
-+  if (TARGET_MB_64) {
-+      insn = emit_insn (gen_iordi3 (regt1, operands[1], operands[2]));
-+      cjump = emit_jump_insn_after (gen_cbranchdi4 (
-+					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
-+					regt1, GEN_INT (15), div_label), insn);
-+    }
-+  else {
-+      insn = emit_insn (gen_iorsi3 (regt1, operands[1], operands[2]));
-+      cjump = emit_jump_insn_after (gen_cbranchsi4 (
-+					gen_rtx_GTU (Pmode, regt1, GEN_INT (15)), 
- 					regt1, GEN_INT (15), div_label), insn);
-+    }
-   LABEL_NUSES (div_label) = 1; 
-   JUMP_LABEL (cjump) = div_label;
--  emit_insn (gen_rtx_CLOBBER (SImode, reg18));
-+  emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
- 
--  emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
--  emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-+  if (TARGET_MB_64) {
-+      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
-+    }
-+  else  {
-+      emit_insn (gen_ashlsi3_bshift (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_addsi3 (regt1, regt1, operands[2]));
-+    }
-   mem_rtx = gen_rtx_MEM (QImode,
-                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-@@ -4096,7 +4160,7 @@ insert_wic_for_ilb_runout (rtx_insn *first)
-               {
-                 insn =
-                   emit_insn_before (gen_iprefetch
--                                    (gen_int_mode (addr_offset, SImode)),
-+                                    (gen_int_mode (addr_offset, Pmode)),
-                                     before_4);
-                 recog_memoized (insn);
-                 INSN_LOCATION (insn) = INSN_LOCATION (before_4);
-@@ -4106,7 +4170,27 @@ insert_wic_for_ilb_runout (rtx_insn *first)
-            }
-        }
- }
--
-+  
-+/* Set the names for various arithmetic operations according to the
-+ *    MICROBLAZE ABI.  */
-+static void
-+microblaze_init_libfuncs (void)
-+{ 
-+  set_optab_libfunc (smod_optab,     SImode, "__modsi3");
-+  set_optab_libfunc (sdiv_optab,     SImode, "__divsi3");
-+  set_optab_libfunc (smul_optab,     SImode, "__mulsi3");
-+  set_optab_libfunc (umod_optab,     SImode, "__umodsi3");
-+  set_optab_libfunc (udiv_optab,     SImode, "__udivsi3");
-+  
-+  if (TARGET_MB_64)
-+    {
-+      set_optab_libfunc (smod_optab,     DImode, "__moddi3");
-+      set_optab_libfunc (sdiv_optab,     DImode, "__divdi3");
-+      set_optab_libfunc (smul_optab,     DImode, "__muldi3");
-+      set_optab_libfunc (umod_optab,     DImode, "__umoddi3");
-+      set_optab_libfunc (udiv_optab,     DImode, "__udivdi3");
-+    }
-+}       
- /* Insert instruction prefetch instruction at the fall
-    through path of the function call.  */
- 
-@@ -4259,6 +4343,17 @@ microblaze_starting_frame_offset (void)
- #undef TARGET_LRA_P
- #define TARGET_LRA_P hook_bool_void_false
- 
-+#ifdef TARGET_MB_64
-+#undef TARGET_ASM_ALIGNED_DI_OP
-+#define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
-+
-+#undef TARGET_ASM_ALIGNED_HI_OP
-+#define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
-+
-+#undef TARGET_ASM_ALIGNED_SI_OP
-+#define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
-+#endif
-+
- #undef TARGET_FRAME_POINTER_REQUIRED
- #define TARGET_FRAME_POINTER_REQUIRED	microblaze_frame_pointer_required
- 
-@@ -4268,6 +4363,9 @@ microblaze_starting_frame_offset (void)
- #undef  TARGET_TRAMPOLINE_INIT
- #define TARGET_TRAMPOLINE_INIT		microblaze_trampoline_init
- 
-+#undef TARGET_INIT_LIBFUNCS
-+#define TARGET_INIT_LIBFUNCS microblaze_init_libfuncs
-+
- #undef  TARGET_PROMOTE_FUNCTION_MODE
- #define TARGET_PROMOTE_FUNCTION_MODE 	default_promote_function_mode_always_promote
- 
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 4931895e650..1f6e2059545 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -173,7 +173,6 @@ extern enum pipeline_type microblaze_pipe;
- 
- /* Generate DWARF exception handling info.  */
- #define DWARF2_UNWIND_INFO 1
--
- /* Don't generate .loc operations.  */
- #define DWARF2_ASM_LINE_DEBUG_INFO 0
- 
-@@ -206,38 +205,51 @@ extern enum pipeline_type microblaze_pipe;
-   ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
- 
- /* Use DWARF 2 debugging information by default.  */
--#define DWARF2_DEBUGGING_INFO
-+#define DWARF2_DEBUGGING_INFO 1
- #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-+#define DWARF2_ADDR_SIZE 4
- 
- /* Target machine storage layout */
- 
- #define BITS_BIG_ENDIAN 0
- #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
- #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
--#define BITS_PER_WORD           32
--#define UNITS_PER_WORD          4
-+//#define BITS_PER_WORD           64
-+//Revisit
-+#define MAX_BITS_PER_WORD	64
-+#define UNITS_PER_WORD          (TARGET_MB_64 ? 8 : 4)
-+//#define MIN_UNITS_PER_WORD      (TARGET_MB_64 ? 8 : 4)
-+//#define UNITS_PER_WORD          4
- #define MIN_UNITS_PER_WORD      4
- #define INT_TYPE_SIZE           32
- #define SHORT_TYPE_SIZE         16
--#define LONG_TYPE_SIZE          64
-+#define LONG_TYPE_SIZE (TARGET_MB_64 ? 64 : 32)
- #define LONG_LONG_TYPE_SIZE     64
- #define FLOAT_TYPE_SIZE         32
- #define DOUBLE_TYPE_SIZE        64
- #define LONG_DOUBLE_TYPE_SIZE   64
--#define POINTER_SIZE            32
--#define PARM_BOUNDARY           32
--#define FUNCTION_BOUNDARY       32
--#define EMPTY_FIELD_BOUNDARY    32
-+#define POINTER_SIZE            (TARGET_MB_64 ? 64 : 32)
-+//#define WIDEST_HARDWARE_FP_SIZE 64
-+//#define POINTERS_EXTEND_UNSIGNED 1
-+#define PARM_BOUNDARY           (TARGET_MB_64 ? 64 : 32)
-+#define FUNCTION_BOUNDARY       (TARGET_MB_64 ? 64 : 32)
-+#define EMPTY_FIELD_BOUNDARY    (TARGET_MB_64 ? 64 : 32)
- #define STRUCTURE_SIZE_BOUNDARY 8
--#define BIGGEST_ALIGNMENT       32
-+#define BIGGEST_ALIGNMENT       (TARGET_MB_64 ? 64 : 32) 
- #define STRICT_ALIGNMENT        1
- #define PCC_BITFIELD_TYPE_MATTERS 1
- 
-+//#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_MB_64 ? TImode : DImode)
- #undef SIZE_TYPE
--#define SIZE_TYPE "unsigned int"
-+#define SIZE_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
- 
- #undef PTRDIFF_TYPE
--#define PTRDIFF_TYPE "int"
-+#define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
-+
-+/*#undef INTPTR_TYPE
-+#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
-+#undef UINTPTR_TYPE
-+#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
- 
- #define DATA_ALIGNMENT(TYPE, ALIGN)					\
-   ((((ALIGN) < BITS_PER_WORD)						\
-@@ -253,12 +265,12 @@ extern enum pipeline_type microblaze_pipe;
- #define WORD_REGISTER_OPERATIONS 1
- 
- #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
--
-+/*
- #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
-   if (GET_MODE_CLASS (MODE) == MODE_INT		\
--      && GET_MODE_SIZE (MODE) < 4)		\
--    (MODE) = SImode;
--
-+      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
-+    (MODE) = TARGET_MB_64 ? DImode : SImode;
-+*/
- /* Standard register usage.  */
- 
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -438,13 +450,16 @@ extern struct microblaze_frame_info current_frame_info;
- #define FIRST_PARM_OFFSET(FNDECL)		(UNITS_PER_WORD)
- 
- #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
-+#define DWARF_CIE_DATA_ALIGNMENT -1
- 
- #define REG_PARM_STACK_SPACE(FNDECL)  		 microblaze_reg_parm_stack_space(FNDECL)
- 
- #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)  1
- 
--#define STACK_BOUNDARY				32
-+#define STACK_BOUNDARY				(TARGET_MB_64 ? 64 : 32)
- 
-+#define PREFERRED_STACK_BOUNDARY		(TARGET_MB_64 ? 64 : 32)
-+ 
- #define NUM_OF_ARGS				6
- 
- #define GP_RETURN				(GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
-@@ -455,12 +470,15 @@ extern struct microblaze_frame_info current_frame_info;
- #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
- 
- #define LIBCALL_VALUE(MODE)						\
-+  gen_rtx_REG (MODE,GP_RETURN)
-+								
-+/*#define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (								\
- 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
- 	     || GET_MODE_SIZE (MODE) >= 4)				\
- 	    ? (MODE)							\
- 	    : SImode), GP_RETURN)
--
-+*/
- /* 1 if N is a possible register number for a function value.
-    On the MicroBlaze, R2 R3 are the only register thus used.
-    Currently, R2 are only implemented  here (C has no complex type)  */
-@@ -500,7 +518,7 @@ typedef struct microblaze_args
- /* 4 insns + 2 words of data.  */
- #define TRAMPOLINE_SIZE				(6 * 4)
- 
--#define TRAMPOLINE_ALIGNMENT			32
-+#define TRAMPOLINE_ALIGNMENT			64
- 
- #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
- 
-@@ -529,13 +547,13 @@ typedef struct microblaze_args
-    addresses which require two reload registers.  */
- #define LEGITIMATE_PIC_OPERAND_P(X)  microblaze_legitimate_pic_operand (X)
- 
--#define CASE_VECTOR_MODE			(SImode)
-+#define CASE_VECTOR_MODE			(TARGET_MB_64? DImode:SImode)
- 
- #ifndef DEFAULT_SIGNED_CHAR
- #define DEFAULT_SIGNED_CHAR			1
- #endif
- 
--#define MOVE_MAX				4
-+#define MOVE_MAX				(TARGET_MB_64 ? 8 : 4)
- #define MAX_MOVE_MAX				8
- 
- #define SLOW_BYTE_ACCESS			1
-@@ -545,7 +563,7 @@ typedef struct microblaze_args
- 
- #define SHIFT_COUNT_TRUNCATED			1
- 
--#define Pmode SImode
-+#define Pmode (TARGET_MB_64? DImode:SImode)
- 
- #define FUNCTION_MODE   SImode
- 
-@@ -707,6 +725,7 @@ do {									\
- 
- #undef TARGET_ASM_OUTPUT_IDENT
- #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
-+//#define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
- 
- /* Default to -G 8 */
- #ifndef MICROBLAZE_DEFAULT_GVALUE
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bcf2b9244f8..bef750c026a 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -26,6 +26,7 @@
- ;; Constants
- ;;----------------------------------------------------
- (define_constants [
-+  (R_Z         0)       ;; For reg r0
-   (R_SP        1)       ;; Stack pointer reg
-   (R_SR       15)       ;; Sub-routine return addr reg
-   (R_IR       14)       ;; Interrupt return addr reg
-@@ -541,6 +542,7 @@
- 
- ;; Add 2 SImode integers [ src1 = reg ; src2 = arith ; dest = reg ]
- ;; Leave carry as is
-+
- (define_insn "addsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
- 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%dJ,dJ,dJ")
-@@ -562,23 +564,38 @@
- 
- ;; Adding 2 DI operands in register or reg/imm
- 
--(define_insn "adddi3_long"
-+(define_expand "adddi3"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(plus:DI (match_operand:DI 1 "register_operand" "")
-+		 (match_operand:DI 2 "arith_plus_operand" "")))]
-+""
-+{
-+  if (TARGET_MB_64) 
-+   {
-+     if (GET_CODE (operands[2]) == CONST_INT &&
-+       INTVAL(operands[2]) < (long)-549755813888 &&
-+	INTVAL(operands[2]) > (long)549755813887)
-+      FAIL;
-+   }
-+})
-+
-+(define_insn "*adddi3_long"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(plus:DI (match_operand:DI 1 "reg_or_0_operand" "%dJ,dJ")
-+	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
- 		 (match_operand:DI 2 "arith_plus_operand" "d,K")))]
-   "TARGET_MB_64"
-   "@
--   addlk\t%0,%z1,%2
--   addlik\t%0,%z1,%2"
--  [(set_attr "type"	"arith,arith")
--  (set_attr "mode"	"DI,DI")
-+   addlk\t%0,%1,%2
-+   addlik\t%0,%1,%2 #N10"
-+  [(set_attr "type"	"darith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-   (set_attr "length"	"4,4")])
- 
--(define_insn "adddi3"
-+(define_insn "*adddi3_all"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
- 		 (match_operand:DI 2 "arith_operand" "d,i")))]
--  ""
-+  "!TARGET_MB_64"
-   "@
-   add\t%L0,%L1,%L2\;addc\t%M0,%M1,%M2
-   addi\t%L0,%L1,%j2\;addic\t%M0,%M1,%h2"
-@@ -605,7 +622,7 @@
- (define_insn "iprefetch"
-   [(unspec [(match_operand:SI 0 "const_int_operand" "n")] UNSPEC_IPREFETCH)
-    (clobber (mem:BLK (scratch)))]
--   "TARGET_PREFETCH"
-+   "TARGET_PREFETCH && !TARGET_MB_64"
-   {
-     operands[2] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-     return "mfs\t%2,rpc\n\twic\t%2,r0";
-@@ -618,23 +635,33 @@
- ;; Double Precision Subtraction
- ;;----------------------------------------------------------------
- 
--(define_insn "subdi3_long"
--  [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(minus:DI (match_operand:DI 1 "register_operand" "d,d")
--		  (match_operand:DI 2 "register_operand" "d,n")))]
-+(define_expand "subdi3"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(minus:DI (match_operand:DI 1 "register_operand" "")
-+		  (match_operand:DI 2 "arith_operand" "")))]
-+""
-+"
-+{
-+}")
-+
-+(define_insn "subsidi3"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
-+		  (match_operand:DI 2 "arith_operand" "d,K,n")))]
-   "TARGET_MB_64"
-   "@
-    rsubl\t%0,%2,%1
--   addlik\t%0,%z1,-%2"
--  [(set_attr "type"	"darith")
--  (set_attr "mode"	"DI,DI")
--  (set_attr "length"	"4,4")])
-+   addik\t%0,%z1,-%2
-+   addik\t%0,%z1,-%2"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,4,4")])
- 
--(define_insn "subdi3"
-+(define_insn "subdi3_small"
-   [(set (match_operand:DI 0 "register_operand" "=&d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d")
- 		  (match_operand:DI 2 "register_operand" "d")))]
--  ""
-+  "!TARGET_MB_64"
-   "rsub\t%L0,%L2,%L1\;rsubc\t%M0,%M2,%M1"
-   [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-@@ -663,7 +690,7 @@
-         (mult:DI
-          (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulh\t%M0,%1,%2"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -674,7 +701,7 @@
-         (mult:DI
-          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulhu\t%M0,%1,%2"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -685,7 +712,7 @@
-         (mult:DI
-          (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
-          (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
--  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH"
-+  "!TARGET_SOFT_MUL && TARGET_MULTIPLY_HIGH && !TARGET_MB_64"
-   "mul\t%L0,%1,%2\;mulhsu\t%M0,%2,%1"
-   [(set_attr "type"     "no_delay_arith")
-    (set_attr "mode"     "DI")
-@@ -789,7 +816,7 @@
-                         (match_operand:SI 4 "arith_operand")])
-                       (label_ref (match_operand 5))
-                       (pc)))]
--   "TARGET_HARD_FLOAT"
-+   "TARGET_HARD_FLOAT && !TARGET_MB_64"
-    [(set (match_dup 1) (match_dup 3))]
- 
-   {
-@@ -819,6 +846,15 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "negsi_long"
-+  [(set (match_operand:SI 0 "register_operand" "=d")
-+	(neg:SI (match_operand:DI 1 "register_operand" "d")))]
-+  ""
-+  "rsubk\t%0,%1,r0"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"SI")
-+  (set_attr "length"	"4")])
-+
- (define_insn "negdi2_long"
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
-@@ -847,16 +883,24 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--(define_insn "one_cmpldi2_long"
-+(define_expand "one_cmpldi2"
-+  [(set (match_operand:DI 0 "register_operand" "")
-+	(not:DI (match_operand:DI 1 "register_operand" "")))]
-+  ""
-+  "
-+{
-+}")
-+
-+(define_insn ""
-   [(set (match_operand:DI 0 "register_operand" "=d")
--	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-+	(not:DI (match_operand:DI 1 "arith_operand" "d")))]
-   "TARGET_MB_64"
-   "xorli\t%0,%1,-1"
--  [(set_attr "type"	"arith")
-+  [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
- 
--(define_insn "*one_cmpldi2"
-+(define_insn ""
-   [(set (match_operand:DI 0 "register_operand" "=d")
- 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
-   ""
-@@ -871,7 +915,8 @@
- 	(not:DI (match_operand:DI 1 "register_operand" "")))]
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
--   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
-+   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-+   && !TARGET_MB_64"
- 
-   [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
-   (set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
-@@ -883,18 +928,17 @@
- ;;----------------------------------------------------------------
- 
- (define_insn "anddi3"
--  [(set (match_operand:DI 0 "register_operand" "=d,d")
--	(and:DI (match_operand:DI 1 "arith_operand" "d,d")
--		(match_operand:DI 2 "arith_operand" "d,K")))]
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
-+		(match_operand:DI 2 "arith_operand" "d,K,I")))]
-   "TARGET_MB_64"
-   "@
-    andl\t%0,%1,%2
--   andli\t%0,%1,%2 #andl1"
--  ;; andli\t%0,%1,%2 #andl3
--  ;; andli\t%0,%1,%2 #andl2
--  [(set_attr "type"	"arith,arith")
--  (set_attr "mode"	"DI,DI")
--  (set_attr "length"	"4,4")])
-+   andli\t%0,%1,%2 #andl2
-+   andli\t%0,%1,%2 #andl3"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI,DI,DI")
-+  (set_attr "length"	"4,4,4")])
- 
- (define_insn "andsi3"
-   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
-@@ -919,7 +963,7 @@
-   "@
-    orl\t%0,%1,%2
-    orli\t%0,%1,%2 #andl1"
--  [(set_attr "type"	"arith,arith")
-+  [(set_attr "type"	"arith,no_delay_arith")
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")])
- 
-@@ -945,7 +989,7 @@
-   "@
-    xorl\t%0,%1,%2
-    xorli\t%0,%1,%2 #andl1"
--  [(set_attr "type"	"arith,arith")
-+  [(set_attr "type"	"arith,no_delay_arith")
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")])
- 
-@@ -1018,26 +1062,6 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--;;(define_expand "extendqidi2"
--;;  [(set (match_operand:DI 0 "register_operand" "=d")
--;;        (sign_extend:DI (match_operand:QI 1 "general_operand" "d")))]
--;;  "TARGET_MB_64"
--;;  {
--;;	if (GET_CODE (operands[1]) != REG)
--;;	FAIL;
--;;   }
--;;)
--    
--
--;;(define_insn "extendqidi2"
--;;  [(set (match_operand:DI 0 "register_operand" "=d")
--;;	(sign_extend:DI (match_operand:QI 1 "register_operand" "d")))]
--;;  "TARGET_MB_64"
--;;  "sextl8\t%0,%1"
--;;  [(set_attr "type"	"arith")
--;;  (set_attr "mode"	"DI")
--;;  (set_attr "length"	"4")])
--
- (define_insn "extendhisi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(sign_extend:SI (match_operand:HI 1 "register_operand" "d")))]
-@@ -1060,6 +1084,27 @@
- ;; Those for integer source operand are ordered
- ;; widest source type first.
- 
-+(define_insn "extendsidi2_long"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-+	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-+  "TARGET_MB_64"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "sextl32\t%0,%1";
-+      case 1:
-+      case 2:
-+        {
-+          output_asm_insn ("ll%i1\t%0,%1", operands);
-+          return "sextl32\t%0,%0";
-+        }
-+    } 
-+  }
-+  [(set_attr "type"	"multi,multi,multi")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,8,8")])
-+
- (define_insn "extendsidi2"
-   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- 	(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
-@@ -1090,68 +1135,117 @@
- ;; Unlike most other insns, the move insns can't be split with
- ;; different predicates, because register spilling and other parts of
- ;; the compiler, have memoized the insn number already.
-+;;    //}
- 
- (define_expand "movdi"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "")
- 	(match_operand:DI 1 "general_operand" ""))]
-   ""
-   {
--    /* If operands[1] is a constant address illegal for pic, then we need to
--       handle it just like microblaze_legitimize_address does.  */
--    if (flag_pic && pic_address_needs_scratch (operands[1]))
-+    if (TARGET_MB_64)
-+    {
-+      if (microblaze_expand_move (DImode, operands)) DONE;
-+    }
-+    else
-     {
-+      /* If operands[1] is a constant address illegal for pic, then we need to
-+         handle it just like microblaze_legitimize_address does. */ 
-+      if (flag_pic && pic_address_needs_scratch (operands[1]))
-+      {
-         rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
-         rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
-         emit_move_insn (operands[0], gen_rtx_PLUS (DImode, temp, temp2));
-         DONE;
--    }
--
--
--    if ((reload_in_progress | reload_completed) == 0
--        && !register_operand (operands[0], DImode)
--        && !register_operand (operands[1], DImode)
--        && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
--	       && operands[1] != CONST0_RTX (DImode))))
--    {
-+      }
- 
--      rtx temp = force_reg (DImode, operands[1]);
--      emit_move_insn (operands[0], temp);
--      DONE;
-+      if ((reload_in_progress | reload_completed) == 0
-+          && !register_operand (operands[0], DImode)
-+          && !register_operand (operands[1], DImode)
-+          && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
-+  	       && operands[1] != CONST0_RTX (DImode))))
-+      {
-+        rtx temp = force_reg (DImode, operands[1]);
-+        emit_move_insn (operands[0], temp);
-+        DONE;
-+      }
-     }
-   }
- )
- 
-+;; Added for status registers
-+(define_insn "movdi_status"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d,z")
-+        (match_operand:DI 1 "register_operand" "z,d,d"))]
-+  "microblaze_is_interrupt_variant () && TARGET_MB_64"
-+  "@
-+	mfs\t%0,%1  #mfs
-+	addlk\t%0,%1,r0 #add movdi
-+	mts\t%0,%1  #mts"	
-+  [(set_attr "type" "move")
-+  (set_attr "mode" "DI")
-+  (set_attr "length" "12")])
- 
--(define_insn "*movdi_internal_64"
--  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
--	(match_operand:DI 1 "general_operand"      " d,K,J,R,o,d,d"))]
--  "TARGET_MB_64 && (INTVAL(operands[1]) < 0x7fffffffff) && (INTVAL(operands[1]) > 0xffffff8000000000)"
-+;; This move will be not be moved to delay slot.	
-+(define_insn "*movdi_internal3"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
-+	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
-+  "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
-+           (GET_CODE (operands[1]) == CONST_INT && 
-+                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
-+  "@
-+   addlk\t%0,r0,r0\t
-+   addlik\t%0,r0,%1\t #N1 %X1
-+   addlik\t%0,r0,%1\t #N2 %X1"
-+  [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+;; This move may be used for PLT label operand
-+(define_insn "*movdi_internal5_pltop"
-+  [(set (match_operand:DI 0 "register_operand" "=d,d")
-+	(match_operand:DI 1 "call_insn_operand" ""))]
-+  "TARGET_MB_64 && (register_operand (operands[0], Pmode) && 
-+           PLT_ADDR_P (operands[1]))"
-+  { 
-+     gcc_unreachable ();
-+  }
-+  [(set_attr "type"	"load")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")])
-+
-+(define_insn "*movdi_internal2"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
-+	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-+  "TARGET_MB_64"
-   { 
-     switch (which_alternative)
-     {
-       case 0:
--        return "addlk\t%0,%1";
--      case 1:
--	return "addlik\t%0,r0,%1";
--      case 2:
--	  return "addlk\t%0,r0,r0";
--      case 3:
--      case 4:
--	  return "lli\t%0,%1";
--      case 5:
--      case 6:
--        return "sli\t%1,%0";
--    }
--    return "unreachable";
--  }
--  [(set_attr "type"	"no_delay_move,no_delay_arith,no_delay_arith,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+        return "addlk\t%0,%1,r0";
-+     case 1:
-+     case 2:
-+        if (GET_CODE (operands[1]) == CONST_INT && 
-+	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
-+ 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+        else	
-+	  return "addlik\t%0,r0,%1";
-+     case 3:
-+     case 4:
-+       return "ll%i1\t%0,%1";
-+     case 5:
-+     case 6:
-+       return "sl%i0\t%z1,%0";
-+     }
-+   }
-+  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-   (set_attr "mode"	"DI")
--  (set_attr "length"   "8,8,8,8,12,8,12")])
-+  (set_attr "length"	"4,4,12,4,8,4,8")])
-+
- 
- (define_insn "*movdi_internal"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,R,o")
- 	(match_operand:DI 1 "general_operand"      " d,i,J,R,o,d,d"))]
--  ""
-+  "!TARGET_MB_64"
-   { 
-     switch (which_alternative)
-     {
-@@ -1183,7 +1277,8 @@
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
--   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
-+   && (REGNO(operands[0]) == (REGNO(operands[1]) + 1))
-+   && !(TARGET_MB_64)"
- 
-   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
-   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-@@ -1195,12 +1290,22 @@
-   "reload_completed 
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1])) 
--   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
-+   && !(TARGET_MB_64)"
- 
-   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
-   "")
- 
-+(define_insn "movdi_long_int"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
-+	(match_operand:DI 1 "general_operand"      "i"))]
-+  ""
-+  "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+  [(set_attr "type"	"no_delay_arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"12")])
-+
- ;; Unlike most other insns, the move insns can't be split with
- ;; different predicates, because register spilling and other parts of
- ;; the compiler, have memoized the insn number already.
-@@ -1272,6 +1377,8 @@
-   (set_attr "length"	"4,4,8,4,8,4,8")])
- 
- 
-+
-+
- ;; 16-bit Integer moves
- 
- ;; Unlike most other insns, the move insns can't be split with
-@@ -1304,8 +1411,8 @@
-   "@
-    addik\t%0,r0,%1\t# %X1
-    addk\t%0,%1,r0
--   lhui\t%0,%1
--   lhui\t%0,%1
-+   lhu%i1\t%0,%1
-+   lhu%i1\t%0,%1
-    sh%i0\t%z1,%0
-    sh%i0\t%z1,%0"
-   [(set_attr "type"	"arith,move,load,no_delay_load,store,no_delay_store")
-@@ -1348,7 +1455,7 @@
-    lbu%i1\t%0,%1
-    lbu%i1\t%0,%1
-    sb%i0\t%z1,%0
--   sbi\t%z1,%0"
-+   sb%i0\t%z1,%0"
-   [(set_attr "type"	"arith,arith,move,load,no_delay_load,store,no_delay_store")
-   (set_attr "mode"	"QI")
-   (set_attr "length"	"4,4,8,4,8,4,8")])
-@@ -1421,7 +1528,7 @@
-    addik\t%0,r0,%F1
-    lw%i1\t%0,%1
-    sw%i0\t%z1,%0
--   swi\t%z1,%0"
-+   sw%i0\t%z1,%0"
-   [(set_attr "type"     "move,no_delay_load,load,no_delay_load,no_delay_load,store,no_delay_store")
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4,4,4,4,4,4,4")])
-@@ -1460,6 +1567,33 @@
- ;; movdf_internal
- ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
- ;;
-+(define_insn "*movdf_internal_64"
-+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-+        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-+  "TARGET_MB_64"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+	return "addlk\t%0,%1,r0";
-+      case 1:
-+	return "addlk\t%0,r0,r0";
-+      case 2:
-+      case 4:
-+          return "ll%i1\t%0,%1";
-+      case 3:
-+      {
-+	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
-+      }
-+      case 5:
-+	return "sl%i0\t%1,%0";
-+    }
-+    gcc_unreachable ();
-+  }
-+  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4,4,4,16,4,4")])
-+
- (define_insn "*movdf_internal"
-   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,o")
-         (match_operand:DF 1 "general_operand" "dG,o,F,T,d"))]
-@@ -1494,7 +1628,8 @@
-   "reload_completed
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
--   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) == (REGNO (operands[1]) + 1))
-+   && !TARGET_MB_64"
-   [(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
-   (set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
-   "")
-@@ -1505,7 +1640,8 @@
-   "reload_completed
-    && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-    && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
--   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
-+   && (REGNO (operands[0]) != (REGNO (operands[1]) + 1))
-+   && !TARGET_MB_64"
-   [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
-   (set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
-   "")
-@@ -2005,6 +2141,31 @@ else
-   "
- )
- 
-+
-+(define_insn "seq_internal_pat_long" 
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(eq:DI 
-+	       (match_operand:DI 1 "register_operand" "d")
-+	       (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "pcmpleq\t%0,%1,%2"
-+  [(set_attr "type"	"arith")
-+   (set_attr "mode"	"DI")
-+   (set_attr "length"	"4")]
-+)              
-+
-+(define_insn "sne_internal_pat_long" 
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+	(ne:DI 
-+	       (match_operand:DI 1 "register_operand" "d")
-+	       (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "pcmplne\t%0,%1,%2"
-+  [(set_attr "type"	"arith")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4")]
-+)              
-+
- (define_insn "seq_internal_pat" 
-   [(set (match_operand:SI 0 "register_operand" "=d")
- 	(eq:SI 
-@@ -2065,8 +2226,8 @@ else
- (define_expand "cbranchsi4"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand:SI 1 "register_operand")
--                        (match_operand:SI 2 "arith_operand" "I,i")])
-+                       [(match_operand 1 "register_operand")
-+                        (match_operand 2 "arith_operand" "I,i")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
-@@ -2078,13 +2239,13 @@ else
- (define_expand "cbranchsi4_reg"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand:SI 1 "register_operand")
--                        (match_operand:SI 2 "register_operand")])
-+                       [(match_operand 1 "register_operand")
-+                        (match_operand 2 "register_operand")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
- {
--  microblaze_expand_conditional_branch_reg (SImode, operands);
-+  microblaze_expand_conditional_branch_reg (Pmode, operands);
-   DONE;
- })
- 
-@@ -2109,6 +2270,26 @@ else
- 		      (label_ref (match_operand 1))
- 		      (pc)))])
- 
-+(define_insn "branch_zero64"
-+  [(set (pc)
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-+  				 [(match_operand 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand 2 "pc_or_label_operand" "")
-+                      (match_operand 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "bea%C0i%?\t%z1,%2";
-+    else 
-+      return "bea%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
- (define_insn "branch_zero"
-   [(set (pc)
- 	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-@@ -2129,6 +2310,47 @@ else
-    (set_attr "length"	"4")]
- )
- 
-+(define_insn "branch_compare64"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "cmp_op"
-+                                         [(match_operand 1 "register_operand" "d")
-+                                          (match_operand 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:SI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmp\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmpu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmp\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmpu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), SImode, operands[4], const0_rtx);
-+    return "bea%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- (define_insn "branch_compare"
-   [(set (pc)
-         (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2312,7 +2534,7 @@ else
- ;; Indirect jumps. Jump to register values. Assuming absolute jumps
- 
- (define_insn "indirect_jump_internal1"
--  [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
-+  [(set (pc) (match_operand 0 "register_operand" "d"))]
-   ""
-   "bra%?\t%0"
-   [(set_attr "type"	"jump")
-@@ -2325,7 +2547,7 @@ else
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   {
--    gcc_assert (GET_MODE (operands[0]) == Pmode);
-+    //gcc_assert (GET_MODE (operands[0]) == Pmode);
- 
-     if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
-       emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-@@ -2337,7 +2559,7 @@ else
- 
- (define_insn "tablejump_internal1"
-   [(set (pc)
--	(match_operand:SI 0 "register_operand" "d"))
-+	(match_operand 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   "bra%?\t%0 "
-@@ -2347,9 +2569,9 @@ else
- 
- (define_expand "tablejump_internal3"
-   [(parallel [(set (pc)
--		   (plus:SI (match_operand:SI 0 "register_operand" "d")
--			    (label_ref:SI (match_operand:SI 1 "" ""))))
--             (use (label_ref:SI (match_dup 1)))])]
-+		   (plus (match_operand 0 "register_operand" "d")
-+			    (label_ref (match_operand:SI 1 "" ""))))
-+             (use (label_ref (match_dup 1)))])]
-   ""
-   ""
- )
-@@ -2410,7 +2632,7 @@ else
- 	(minus (reg 1) (match_operand 1 "register_operand" "")))
-    (set (reg 1)
- 	(minus (reg 1) (match_dup 1)))]
--  ""
-+  "!TARGET_MB_64"
-   { 
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
-     rtx reg = gen_reg_rtx (Pmode);
-@@ -2435,7 +2657,7 @@ else
- (define_expand "save_stack_block"
-   [(match_operand 0 "register_operand" "")
-    (match_operand 1 "register_operand" "")]
--  ""
-+  "!TARGET_MB_64"
-   {
-     emit_move_insn (operands[0], operands[1]);
-     DONE;
-@@ -2445,7 +2667,7 @@ else
- (define_expand "restore_stack_block"
-   [(match_operand 0 "register_operand" "")
-    (match_operand 1 "register_operand" "")]
--  ""
-+  "!TARGET_MB_64"
-   {
-     rtx retaddr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
-     rtx rtmp    = gen_rtx_REG (SImode, R_TMP);
-@@ -2492,7 +2714,7 @@ else
- 
- (define_insn "<optab>_internal"
-   [(any_return)
--   (use (match_operand:SI 0 "register_operand" ""))]
-+   (use (match_operand 0 "register_operand" ""))]
-   ""
-   {
-     if (microblaze_is_break_handler ())
-@@ -2525,7 +2747,7 @@ else
- (define_expand "call"
-   [(parallel [(call (match_operand 0 "memory_operand" "m")
- 		    (match_operand 1 "" "i"))
--             (clobber (reg:SI R_SR))
-+             (clobber (reg R_SR))
-              (use (match_operand 2 "" ""))
-              (use (match_operand 3 "" ""))])]
-   ""
-@@ -2546,12 +2768,12 @@ else
- 
-     if (GET_CODE (XEXP (operands[0], 0)) == UNSPEC)
-       emit_call_insn (gen_call_internal_plt0 (operands[0], operands[1],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
-                                	     pic_offset_table_rtx));
-     else
-       emit_call_insn (gen_call_internal0 (operands[0], operands[1],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- 
-         DONE;
-@@ -2561,7 +2783,7 @@ else
- (define_expand "call_internal0"
-   [(parallel [(call (match_operand 0 "" "")
- 		    (match_operand 1 "" ""))
--             (clobber (match_operand:SI 2 "" ""))])]
-+             (clobber (match_operand 2 "" ""))])]
-   ""
-   {
-   }
-@@ -2570,18 +2792,34 @@ else
- (define_expand "call_internal_plt0"
-   [(parallel [(call (match_operand 0 "" "")
- 		    (match_operand 1 "" ""))
--             (clobber (match_operand:SI 2 "" ""))
--             (use (match_operand:SI 3 "" ""))])]
-+             (clobber (match_operand 2 "" ""))
-+             (use (match_operand 3 "" ""))])]
-   ""
-   {
-   }
- )
-  
-+(define_insn "call_internal_plt_64"
-+  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))
-+  (use (reg R_GOT))]
-+  "flag_pic && TARGET_MB_64"
-+  {
-+    register rtx target2 = gen_rtx_REG (Pmode, 
-+			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+    gen_rtx_CLOBBER (VOIDmode, target2);
-+    return "brealid\tr15,%0\;%#";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_internal_plt"
--  [(call (mem (match_operand:SI 0 "call_insn_plt_operand" ""))
--	 (match_operand:SI 1 "" "i"))
--  (clobber (reg:SI R_SR))
--  (use (reg:SI R_GOT))]
-+  [(call (mem (match_operand 0 "call_insn_plt_operand" ""))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))
-+  (use (reg R_GOT))]
-   "flag_pic"
-   {
-     register rtx target2 = gen_rtx_REG (Pmode, 
-@@ -2593,10 +2831,41 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "call_internal1_64"
-+  [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))]
-+  "TARGET_MB_64"
-+  {
-+    register rtx target = operands[0];
-+    register rtx target2 = gen_rtx_REG (Pmode,
-+			      GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+    if (GET_CODE (target) == SYMBOL_REF) {
-+        if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
-+            gen_rtx_CLOBBER (VOIDmode, target2);
-+            return "breaki\tr16,%0\;%#";
-+        }
-+        else {
-+            gen_rtx_CLOBBER (VOIDmode, target2);
-+            return "brealid\tr15,%0\;%#";
-+        }
-+    } else if (GET_CODE (target) == CONST_INT)
-+        return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
-+    else if (GET_CODE (target) == REG)
-+        return "brald\tr15,%0\;%#";	
-+    else {
-+        fprintf (stderr,"Unsupported call insn\n");
-+        return NULL;
-+    }
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_internal1"
-   [(call (mem (match_operand:VOID 0 "call_insn_simple_operand" "ri"))
--	 (match_operand:SI 1 "" "i"))
--  (clobber (reg:SI R_SR))]
-+	 (match_operand 1 "" "i"))
-+  (clobber (reg R_SR))]
-   ""
-   {
-     register rtx target = operands[0];
-@@ -2630,7 +2899,7 @@ else
-   [(parallel [(set (match_operand 0 "register_operand" "=d")
- 		   (call (match_operand 1 "memory_operand" "m")
- 			 (match_operand 2 "" "i")))
--             (clobber (reg:SI R_SR))
-+             (clobber (reg R_SR))
-              (use (match_operand 3 "" ""))])] ;; next_arg_reg
-   ""
-   {
-@@ -2651,13 +2920,13 @@ else
-     if (GET_CODE (XEXP (operands[1], 0)) == UNSPEC)
-       emit_call_insn (gen_call_value_intern_plt0 (operands[0], operands[1], 
- 			operands[2],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM),
- 				     pic_offset_table_rtx));
-     else
-       emit_call_insn (gen_call_value_internal (operands[0], operands[1], 
- 			operands[2],
--                        gen_rtx_REG (SImode, 
-+                        gen_rtx_REG (Pmode, 
- 				     GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)));
- 
-     DONE;
-@@ -2669,7 +2938,7 @@ else
-   [(parallel [(set (match_operand 0 "" "")
- 		   (call (match_operand 1 "" "")
- 			 (match_operand 2 "" "")))
--             (clobber (match_operand:SI 3 "" ""))
-+             (clobber (match_operand 3 "" ""))
-              ])]
-   ""
-   {}
-@@ -2679,18 +2948,35 @@ else
-   [(parallel[(set (match_operand 0 "" "")
-                   (call (match_operand 1 "" "")
-                         (match_operand 2 "" "")))
--             (clobber (match_operand:SI 3 "" ""))
--             (use (match_operand:SI 4 "" ""))])]
-+             (clobber (match_operand 3 "" ""))
-+             (use (match_operand 4 "" ""))])]
-   "flag_pic"
-   {}
- )
- 
-+(define_insn "call_value_intern_plt_64"
-+  [(set (match_operand:VOID 0 "register_operand" "=d")
-+        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))
-+   (use (match_operand 4 "register_operand"))]
-+  "flag_pic && TARGET_MB_64"
-+  { 
-+    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+
-+    gen_rtx_CLOBBER (VOIDmode,target2);
-+    return "brealid\tr15,%1\;%#";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_value_intern_plt"
-   [(set (match_operand:VOID 0 "register_operand" "=d")
--        (call (mem (match_operand:SI 1 "call_insn_plt_operand" ""))
--              (match_operand:SI 2 "" "i")))
--   (clobber (match_operand:SI 3 "register_operand" "=d"))
--   (use (match_operand:SI 4 "register_operand"))]
-+        (call (mem (match_operand 1 "call_insn_plt_operand" ""))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))
-+   (use (match_operand 4 "register_operand"))]
-   "flag_pic"
-   { 
-     register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-@@ -2702,11 +2988,46 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "call_value_intern_64"
-+  [(set (match_operand:VOID 0 "register_operand" "=d")
-+        (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))]
-+  "TARGET_MB_64"
-+  { 
-+    register rtx target = operands[1];
-+    register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
-+
-+    if (GET_CODE (target) == SYMBOL_REF)
-+    {
-+      gen_rtx_CLOBBER (VOIDmode,target2);
-+      if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
-+        return "breaki\tr16,%1\;%#";
-+      else if (SYMBOL_REF_FLAGS (target) & SYMBOL_FLAG_FUNCTION)
-+        {
-+	  return "brealid\tr15,%1\;%#";
-+        }
-+      else
-+        {
-+	    return "bralid\tr15,%1\;%#";
-+        }
-+    }
-+    else if (GET_CODE (target) == CONST_INT)
-+        return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
-+    else if (GET_CODE (target) == REG)
-+        return "brald\tr15,%1\;%#";	
-+    else 
-+        return "Unsupported call insn\n";
-+  }
-+  [(set_attr "type"	"call")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "call_value_intern"
-   [(set (match_operand:VOID 0 "register_operand" "=d")
-         (call (mem (match_operand:VOID 1 "call_insn_operand" "ri"))
--              (match_operand:SI 2 "" "i")))
--   (clobber (match_operand:SI 3 "register_operand" "=d"))]
-+              (match_operand 2 "" "i")))
-+   (clobber (match_operand 3 "register_operand" "=d"))]
-   ""
-   { 
-     register rtx target = operands[1];
-@@ -2880,7 +3201,6 @@ else
- 
-   ;;if (!register_operand (operands[0], VOIDmode))
-   ;;  FAIL;
--
-   emit_insn (gen_insv_32 (operands[0], operands[1],
- 			  operands[2], operands[3]));
-   DONE;
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 7671f63c5b5..9fc80b142ce 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -2,10 +2,11 @@ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-en
- MULTILIB_DIRNAMES = bs m mh le m64
- MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
- MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--#MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--#MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
-+MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
-diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index d0146083db6..005825f1ec5 100644
---- a/libgcc/config/microblaze/crti.S
-+++ b/libgcc/config/microblaze/crti.S
-@@ -40,7 +40,7 @@
- 
-     .align 2
- __init: 
--    addik   r1, r1, -8
-+    addik   r1, r1, -16
-     sw      r15, r0, r1
-     la      r11, r0, _stack
-     mts     rshr, r11
-@@ -51,5 +51,5 @@ __init:
-     .global __fini
-     .align 2
- __fini: 
--    addik   r1, r1, -8
-+    addik   r1, r1, -16
-     sw      r15, r0, r1
-diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 2fff5ac04c7..5705eff9a4a 100644
---- a/libgcc/config/microblaze/crtn.S
-+++ b/libgcc/config/microblaze/crtn.S
-@@ -33,9 +33,9 @@
-     .section .init, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
--    addik   r1, r1, 8
-+    addik   r1, r1, 16
- 
-     .section .fini, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
--    addik   r1, r1, 8    
-+    addik   r1, r1, 16   
-diff --git a/libgcc/config/microblaze/divdi3.S b/libgcc/config/microblaze/divdi3.S
-new file mode 100644
-index 00000000000..d37bf5165c6
---- /dev/null
-+++ b/libgcc/config/microblaze/divdi3.S
-@@ -0,0 +1,98 @@
-+###################################-
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+#
-+#  divdi3.S
-+# 
-+#  Divide operation for 32 bit integers.
-+#	Input :	Dividend in Reg r5
-+#		Divisor in Reg r6
-+#	Output: Result in Reg r3
-+# 
-+#######################################
-+
-+#ifdef __arch64__	
-+	.globl	__divdi3
-+	.ent	__divdi3
-+	.type	__divdi3,@function
-+__divdi3:
-+	.frame	r1,0,r15	
-+
-+	ADDLIK   r1,r1,-32
-+	SLI     r28,r1,0
-+	SLI     r29,r1,8
-+	SLI     r30,r1,16
-+	SLI     r31,r1,24
-+
-+	BEALEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEALEQI    r5,$LaResult_Is_Zero    # Result is Zero 
-+	XORL     r28,r5,r6               # Get the sign of the result
-+	BEALGEI   r5,$LaR5_Pos 
-+	RSUBLI   r5,r5,0                 # Make r5 positive
-+$LaR5_Pos:
-+	BEALGEI    r6,$LaR6_Pos
-+	RSUBLI   r6,r6,0                 # Make r6 positive
-+$LaR6_Pos:
-+	ADDLIK   r30,r0,0                # Clear mod
-+	ADDLIK   r3,r0,0                 # clear div
-+	ADDLIK   r29,r0,64               # Initialize the loop count
-+
-+        # First part try to find the first '1' in the r5
-+$LaDIV0: 
-+        BEALLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
-+$LaDIV1:
-+	ADDL     r5,r5,r5                # left shift logical r5
-+	ADDLIK   r29,r29,-1
-+	BEALGTI   r5,$LaDIV1       
-+$LaDIV2:
-+	ADDL     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
-+	ADDLC    r30,r30,r30             # Move that bit into the Mod register
-+	RSUBL    r31,r6,r30              # Try to subtract (r30 a r6)
-+	BEALLTI    r31,$LaMOD_TOO_SMALL
-+	ORL      r30,r0,r31              # Move the r31 to mod since the result was positive
-+	ADDLIK   r3,r3,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK   r29,r29,-1
-+	BEALEQi    r29,$LaLOOP_END
-+	ADDL     r3,r3,r3                # Shift in the '1' into div
-+	BREAI     $LaDIV2                 # Div2
-+$LaLOOP_END:
-+	BEALGEI    r28,$LaRETURN_HERE
-+	RSUBLI   r3,r3,0                 # Negate the result
-+	BREAI    $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	ORL      r3,r0,r0 # set result to 0
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r28,r1,0
-+	LLI     r29,r1,8
-+	LLI     r30,r1,16
-+	LLI     r31,r1,24
-+	ADDLIK   r1,r1,32
-+	RTSD    r15,8
-+        nop
-+.end __divdi3
-+	.size	__divdi3, . - __divdi3
-+#endif
-diff --git a/libgcc/config/microblaze/divdi3_table.c b/libgcc/config/microblaze/divdi3_table.c
-new file mode 100644
-index 00000000000..80962597ea5
---- /dev/null
-+++ b/libgcc/config/microblaze/divdi3_table.c
-@@ -0,0 +1,62 @@
-+/*  Table for software lookup divide for Xilinx MicroBlaze.
-+ 
-+   Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+
-+   Contributed by Michael Eager <eager@eagercon.com>.
-+
-+   This file is free software; you can redistribute it and/or modify it
-+   under the terms of the GNU General Public License as published by the
-+   Free Software Foundation; either version 3, or (at your option) any
-+   later version.
-+
-+   GCC is distributed in the hope that it will be useful, but WITHOUT
-+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+   License for more details.
-+
-+   Under Section 7 of GPL version 3, you are granted additional
-+   permissions described in the GCC Runtime Library Exception, version
-+   3.1, as published by the Free Software Foundation.
-+
-+   You should have received a copy of the GNU General Public License and
-+   a copy of the GCC Runtime Library Exception along with this program;
-+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+   <http://www.gnu.org/licenses/>.  */
-+
-+ 
-+unsigned char _divdi3_table[] =
-+{
-+       0,   0/1,   0/2,   0/3,   0/4,   0/5,   0/6,   0/7, 
-+     0/8,   0/9,  0/10,  0/11,  0/12,  0/13,  0/14,  0/15,
-+       0,   1/1,   1/2,   1/3,   1/4,   1/5,   1/6,   1/7, 
-+     1/8,   1/9,  1/10,  1/11,  1/12,  1/13,  1/14,  1/15,
-+       0,   2/1,   2/2,   2/3,   2/4,   2/5,   2/6,   2/7, 
-+     2/8,   2/9,  2/10,  2/11,  2/12,  2/13,  2/14,  2/15,
-+       0,   3/1,   3/2,   3/3,   3/4,   3/5,   3/6,   3/7, 
-+     3/8,   3/9,  3/10,  3/11,  3/12,  3/13,  3/14,  3/15,
-+       0,   4/1,   4/2,   4/3,   4/4,   4/5,   4/6,   4/7, 
-+     4/8,   4/9,  4/10,  4/11,  4/12,  4/13,  4/14,  4/15,
-+       0,   5/1,   5/2,   5/3,   5/4,   5/5,   5/6,   5/7, 
-+     5/8,   5/9,  5/10,  5/11,  5/12,  5/13,  5/14,  5/15,
-+       0,   6/1,   6/2,   6/3,   6/4,   6/5,   6/6,   6/7, 
-+     6/8,   6/9,  6/10,  6/11,  6/12,  6/13,  6/14,  6/15,
-+       0,   7/1,   7/2,   7/3,   7/4,   7/5,   7/6,   7/7, 
-+     7/8,   7/9,  7/10,  7/11,  7/12,  7/13,  7/14,  7/15,
-+       0,   8/1,   8/2,   8/3,   8/4,   8/5,   8/6,   8/7, 
-+     8/8,   8/9,  8/10,  8/11,  8/12,  8/13,  8/14,  8/15,
-+       0,   9/1,   9/2,   9/3,   9/4,   9/5,   9/6,   9/7, 
-+     9/8,   9/9,  9/10,  9/11,  9/12,  9/13,  9/14,  9/15,
-+       0,  10/1,  10/2,  10/3,  10/4,  10/5,  10/6,  10/7, 
-+    10/8,  10/9, 10/10, 10/11, 10/12, 10/13, 10/14, 10/15,
-+       0,  11/1,  11/2,  11/3,  11/4,  11/5,  11/6,  11/7, 
-+    11/8,  11/9, 11/10, 11/11, 11/12, 11/13, 11/14, 11/15,
-+       0,  12/1,  12/2,  12/3,  12/4,  12/5,  12/6,  12/7, 
-+    12/8,  12/9, 12/10, 12/11, 12/12, 12/13, 12/14, 12/15,
-+       0,  13/1,  13/2,  13/3,  13/4,  13/5,  13/6,  13/7, 
-+    13/8,  13/9, 13/10, 13/11, 13/12, 13/13, 13/14, 13/15,
-+       0,  14/1,  14/2,  14/3,  14/4,  14/5,  14/6,  14/7, 
-+    14/8,  14/9, 14/10, 14/11, 14/12, 14/13, 14/14, 14/15,
-+       0,  15/1,  15/2,  15/3,  15/4,  15/5,  15/6,  15/7, 
-+    15/8,  15/9, 15/10, 15/11, 15/12, 15/13, 15/14, 15/15,
-+};
-+
-diff --git a/libgcc/config/microblaze/moddi3.S b/libgcc/config/microblaze/moddi3.S
-new file mode 100644
-index 00000000000..5d3f7c03fc8
---- /dev/null
-+++ b/libgcc/config/microblaze/moddi3.S
-@@ -0,0 +1,97 @@
-+###################################
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  moddi3.S
-+# 
-+#  modulo operation for 32 bit integers.
-+#	Input :	op1 in Reg r5
-+#		op2 in Reg r6
-+#	Output: op1 mod op2 in Reg r3
-+# 
-+#######################################
-+
-+#ifdef __arch64__
-+	.globl	__moddi3
-+	.ent	__moddi3
-+	.type	__moddi3,@function
-+__moddi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-32
-+	sli	r28,r1,0
-+	sli	r29,r1,8
-+	sli	r30,r1,16
-+	sli	r31,r1,32
-+
-+	BEALEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEALEQI	r5,$LaResult_Is_Zero    # Result is Zero 
-+	ADDL	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
-+	BEALGEI	r5,$LaR5_Pos 
-+	RSUBLI	r5,r5,0	                # Make r5 positive
-+$LaR5_Pos:
-+	BEALGEI	r6,$LaR6_Pos
-+	RSUBLI	r6,r6,0	    # Make r6 positive
-+$LaR6_Pos:
-+	ADDLIK	r3,r0,0      # Clear mod
-+	ADDLIK	r30,r0,0     # clear div
-+	ADDLIK	r29,r0,64    # Initialize the loop count
-+	BEALLTI	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+			     # the first bit search.
-+   # First part try to find the first '1' in the r5
-+$LaDIV1:
-+	ADDL	r5,r5,r5         # left shift logical r5
-+	ADDLIK	r29,r29,-1
-+	BEALGEI	r5,$LaDIV1       #
-+$LaDIV2:
-+	ADDL	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
-+	ADDLC	r3,r3,r3         # Move that bit into the Mod register
-+	rSUBL	r31,r6,r3        # Try to subtract (r30 a r6)
-+	BEALLTi	r31,$LaMOD_TOO_SMALL
-+	ORL	r3,r0,r31       # Move the r31 to mod since the result was positive
-+	ADDLIK	r30,r30,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK	r29,r29,-1
-+	BEALEQi	r29,$LaLOOP_END
-+	ADDL	r30,r30,r30         # Shift in the '1' into div
-+	BREAI	$LaDIV2          # Div2
-+$LaLOOP_END:
-+	BEALGEI	r28,$LaRETURN_HERE
-+	rsubli	r3,r3,0 # Negate the result
-+	BREAI	$LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	orl	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli	r28,r1,0
-+	lli	r29,r1,8
-+	lli	r30,r1,16
-+	lli	r31,r1,24
-+	addlik	r1,r1,32
-+	rtsd	r15,8
-+        nop
-+        .end __moddi3
-+	.size	__moddi3, . - __moddi3
-+#endif
-diff --git a/libgcc/config/microblaze/muldi3.S b/libgcc/config/microblaze/muldi3.S
-new file mode 100644
-index 00000000000..567784197d3
---- /dev/null
-+++ b/libgcc/config/microblaze/muldi3.S
-@@ -0,0 +1,73 @@
-+/*###################################-*-asm*- 
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  muldi3.S
-+# 
-+#  Multiply operation for 32 bit integers.
-+#	Input :	Operand1 in Reg r5
-+#		Operand2 in Reg r6
-+#	Output: Result [op1 * op2] in Reg r3
-+# 
-+#######################################*/
-+
-+#ifdef __arch64__
-+	.globl	__muldi3
-+	.ent	__muldi3
-+	.type	__muldi3,@function
-+__muldi3:
-+	.frame	r1,0,r15
-+	addl	r3,r0,r0
-+	BEALEQI	r5,$L_Result_Is_Zero      # Multiply by Zero
-+	BEALEQI	r6,$L_Result_Is_Zero      # Multiply by Zero
-+	XORL	r4,r5,r6                  # Get the sign of the result
-+	BEALGEI	r5,$L_R5_Pos 
-+	RSUBLI	r5,r5,0	                  # Make r5 positive
-+$L_R5_Pos:
-+	BEALGEI	r6,$L_R6_Pos
-+	RSUBLI	r6,r6,0	                  # Make r6 positive
-+$L_R6_Pos:	
-+	breai	$L1
-+$L2:	
-+	addl	r5,r5,r5
-+$L1:	
-+	srll	r6,r6
-+	addlc	r7,r0,r0
-+	bealeqi	r7,$L2
-+	addl	r3,r3,r5	
-+	bealnei	r6,$L2
-+	beallti	r4,$L_NegateResult			
-+	rtsd	r15,8
-+	nop
-+$L_NegateResult:
-+	rsubl	r3,r3,r0
-+	rtsd	r15,8
-+	nop
-+$L_Result_Is_Zero:
-+	addli	r3,r0,0
-+	rtsd	r15,8
-+	nop
-+	.end __muldi3
-+	.size	__muldi3, . - __muldi3
-+#endif
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 8d954a49575..35021b24b7d 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,11 +1,16 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
-+			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
-+        $(srcdir)/config/microblaze/divdi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
--        $(srcdir)/config/microblaze/muldi3_hard.S \
-+        $(srcdir)/config/microblaze/moddi3.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
-+        $(srcdir)/config/microblaze/muldi3.S \
-         $(srcdir)/config/microblaze/stack_overflow_exit.S \
-         $(srcdir)/config/microblaze/udivsi3.S \
-+        $(srcdir)/config/microblaze/udivdi3.S \
-         $(srcdir)/config/microblaze/umodsi3.S \
--        $(srcdir)/config/microblaze/divsi3_table.c
-+        $(srcdir)/config/microblaze/umoddi3.S \
-+        $(srcdir)/config/microblaze/divsi3_table.c \
-diff --git a/libgcc/config/microblaze/udivdi3.S b/libgcc/config/microblaze/udivdi3.S
-new file mode 100644
-index 00000000000..c210fbc7128
---- /dev/null
-+++ b/libgcc/config/microblaze/udivdi3.S
-@@ -0,0 +1,107 @@
-+###################################-
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  udivdi3.S
-+# 
-+#  Unsigned divide operation.
-+#	Input :	Divisor in Reg r5
-+#		Dividend in Reg r6
-+#	Output: Result in Reg r3
-+# 
-+#######################################
-+	
-+#ifdef __arch64__
-+	.globl	__udivdi3
-+	.ent	__udivdi3
-+	.type	__udivdi3,@function
-+__udivdi3:
-+	.frame	r1,0,r15	
-+
-+	ADDlIK   r1,r1,-24
-+    	SLI     r29,r1,0
-+	SLI     r30,r1,8
-+	SLI     r31,r1,16
-+
-+	BEALEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
-+	ADDLIK   r30,r0,0                    # Clear mod
-+	BEALEQI   r5,$LaResult_Is_Zero        # Result is Zero 
-+	ADDLIK   r29,r0,64                   # Initialize the loop count
-+
-+        # Check if r6 and r5 are equal # if yes, return 1
-+	RSUBL 	r18,r5,r6
-+	ADDLIK	r3,r0,1
-+	BEALEQI	r18,$LaRETURN_HERE
-+
-+        # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
-+	XORL	r18,r5,r6
-+	ADDL	r3,r0,r0                    # We would anyways clear r3
-+	BEALGEI	r18,$LRSUBL
-+	BEALLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
-+	BREAI	$LCheckr6
-+$LRSUBL:
-+	RSUBL	r18,r6,r5                   # MICROBLAZEcmp
-+	BEALLTI	r18,$LaRETURN_HERE
-+
-+        # If r6 [bit 31] is set, then return result as 1
-+$LCheckr6:
-+	BEALGTI	r6,$LaDIV0
-+	ADDLIK	r3,r0,1
-+	BREAI	$LaRETURN_HERE
-+
-+        # First part try to find the first '1' in the r5
-+$LaDIV0:
-+	BEALLTI    r5,$LaDIV2	
-+$LaDIV1:
-+	ADDL     r5,r5,r5                    # left shift logical r5
-+	ADDLIK   r29,r29,-1
-+	BEALGTI   r5,$LaDIV1       
-+$LaDIV2:
-+	ADDL     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
-+	ADDLC    r30,r30,r30                 # Move that bit into the Mod register
-+	RSUBL    r31,r6,r30                  # Try to subtract (r30 a r6)
-+    	BEALLTI    r31,$LaMOD_TOO_SMALL
-+	ORL      r30,r0,r31                  # Move the r31 to mod since the result was positive
-+	ADDLIK   r3,r3,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK   r29,r29,-1
-+	BEALEQi    r29,$LaLOOP_END
-+	ADDL     r3,r3,r3 # Shift in the '1' into div
-+	BREAI     $LaDIV2   # Div2
-+$LaLOOP_END:
-+	BREAI     $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	ORL      r3,r0,r0 # set result to 0
-+$LaRETURN_HERE:
-+        # Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r29,r1,0
-+	LLI     r30,r1,8
-+	LLI     r31,r1,16
-+	ADDLIK   r1,r1,24
-+	RTSD    r15,8
-+        NOP
-+        .end __udivdi3
-+	.size	__udivdi3, . - __udivdi3
-+#endif
-diff --git a/libgcc/config/microblaze/umoddi3.S b/libgcc/config/microblaze/umoddi3.S
-new file mode 100644
-index 00000000000..7f5cd23f9a1
---- /dev/null
-+++ b/libgcc/config/microblaze/umoddi3.S
-@@ -0,0 +1,110 @@
-+###################################
-+# 
-+#  Copyright (C) 2009-2017 Free Software Foundation, Inc.
-+#
-+#  Contributed by Michael Eager <eager@eagercon.com>.
-+#
-+#  This file is free software; you can redistribute it and/or modify it
-+#  under the terms of the GNU General Public License as published by the
-+#  Free Software Foundation; either version 3, or (at your option) any
-+#  later version.
-+#
-+#  GCC is distributed in the hope that it will be useful, but WITHOUT
-+#  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-+#  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
-+#  License for more details.
-+#
-+#  Under Section 7 of GPL version 3, you are granted additional
-+#  permissions described in the GCC Runtime Library Exception, version
-+#  3.1, as published by the Free Software Foundation.
-+#
-+#  You should have received a copy of the GNU General Public License and
-+#  a copy of the GCC Runtime Library Exception along with this program;
-+#  see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
-+#  <http://www.gnu.org/licenses/>. 
-+# 
-+#  umoddi3.S
-+#
-+#  Unsigned modulo operation for 32 bit integers.
-+#	Input :	op1 in Reg r5
-+#		op2 in Reg r6
-+#	Output: op1 mod op2 in Reg r3
-+# 
-+#######################################
-+	
-+#ifdef __arch64__
-+	.globl	__umoddi3
-+	.ent	__umoddi3
-+	.type	__umoddi3,@function
-+__umoddi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-24
-+	sli	r29,r1,0
-+	sli	r30,r1,8
-+	sli	r31,r1,16
-+
-+	BEALEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
-+	ADDLIK 	r3,r0,0                  # Clear div
-+	BEALEQI	r5,$LaResult_Is_Zero     # Result is Zero 
-+	ADDLIK 	r30,r0,0     	# clear mod
-+	ADDLIK 	r29,r0,64       # Initialize the loop count
-+
-+# Check if r6 and r5 are equal # if yes, return 0
-+	rsubl 	r18,r5,r6
-+	bealeqi	r18,$LaRETURN_HERE
-+
-+# Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
-+	xorl	r18,r5,r6
-+	addlik	r3,r5,0
-+	bealgei	r18,$LRSUB
-+	beallti	r6,$LaRETURN_HERE
-+	breai	$LCheckr6
-+$LRSUB:
-+	rsubl	r18,r5,r6 # MICROBLAZEcmp
-+	bealgti	r18,$LaRETURN_HERE
-+
-+# If r6 [bit 31] is set, then return result as r5-r6
-+$LCheckr6:
-+	addlik	r3,r0,0
-+	bealgti	r6,$LaDIV0
-+	addlik	r18,r0,0x7fffffff
-+	andl	r5,r5,r18
-+	andl 	r6,r6,r18
-+	breaid	$LaRETURN_HERE
-+	rsubl	r3,r6,r5
-+# First part: try to find the first '1' in the r5
-+$LaDIV0:
-+	BEALLTI	r5,$LaDIV2
-+$LaDIV1:
-+	ADDL 	r5,r5,r5     # left shift logical r5
-+	ADDLIK 	r29,r29,-1
-+	BEALGEI 	r5,$LaDIV1   #
-+$LaDIV2:
-+	ADDL 	r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
-+	ADDLC 	r3,r3,r3     # Move that bit into the Mod register
-+	rSUBL 	r31,r6,r3    # Try to subtract (r3 a r6)
-+	BEALLTi 	r31,$LaMOD_TOO_SMALL
-+	ORL  	r3,r0,r31    # Move the r31 to mod since the result was positive
-+	ADDLIK 	r30,r30,1
-+$LaMOD_TOO_SMALL:
-+	ADDLIK 	r29,r29,-1
-+	BEALEQi 	r29,$LaLOOP_END
-+	ADDL 	r30,r30,r30 # Shift in the '1' into div
-+	BREAI 	$LaDIV2     # Div2
-+$LaLOOP_END:
-+	BREAI 	$LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+	orl 	r3,r0,r0   # set result to 0
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli 	r29,r1,0
-+	lli 	r30,r1,8
-+	lli 	r31,r1,16
-+	addlik 	r1,r1,24
-+	rtsd 	r15,8
-+        nop
-+.end __umoddi3
-+	.size	__umoddi3, . - __umoddi3
-+#endif
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch
new file mode 100644
index 0000000000..3f52e87995
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-Added-double-arith-instructions.patch
@@ -0,0 +1,135 @@
+From 2bb5cef1a85d63ebf155bcb0070492b0ad298dd8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:07:08 +0530
+Subject: [PATCH 36/54] -Added double arith instructions -Fixed prologue stack
+ pointer decrement issue
+
+---
+ gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++----
+ gcc/config/microblaze/t-microblaze  |  7 +++
+ 2 files changed, 76 insertions(+), 9 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 74bb30cb9e8..1401d6b77ff 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -527,6 +527,66 @@
+   (set_attr "mode"      "SF")
+   (set_attr "length"    "4")])
+ 
++(define_insn "fix_truncsfsi2"
++  [(set (match_operand:SI 0 "register_operand" "=d")
++        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
++  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
++  "fint\t%0,%1"
++  [(set_attr "type"     "fint")
++  (set_attr "mode"      "SF")
++  (set_attr "length"    "4")])
++
++
++(define_insn "adddf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (plus:DF (match_operand:DF 1 "register_operand" "d")
++                 (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dadd\t%0,%1,%2"
++  [(set_attr "type"     "fadd")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "subdf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (minus:DF (match_operand:DF 1 "register_operand" "d")
++                  (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "drsub\t%0,%2,%1"
++  [(set_attr "type"     "frsub")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "muldf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (mult:DF (match_operand:DF 1 "register_operand" "d")
++                 (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dmul\t%0,%1,%2"
++  [(set_attr "type"     "fmul")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++(define_insn "divdf3"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (div:DF (match_operand:DF 1 "register_operand" "d")
++                (match_operand:DF 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "ddiv\t%0,%2,%1"
++  [(set_attr "type"     "fdiv")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
++
++(define_insn "sqrtdf2"
++  [(set (match_operand:DF 0 "register_operand" "=d")
++        (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dsqrt\t%0,%1"
++  [(set_attr "type"     "fsqrt")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4")])
++
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+@@ -536,13 +596,13 @@
+   (set_attr "mode"      "DF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "fix_truncsfsi2"
+-  [(set (match_operand:SI 0 "register_operand" "=d")
+-        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
+-  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+-  "fint\t%0,%1"
+-  [(set_attr "type"     "fint")
+-  (set_attr "mode"      "SF")
++(define_insn "floatdfdi2"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (float:DI (match_operand:DF 1 "register_operand" "d")))]
++  "TARGET_MB_64"
++  "dlong\t%0,%1"
++  [(set_attr "type"     "fcvt")
++  (set_attr "mode"      "DI")
+   (set_attr "length"    "4")])
+ 
+ ;;----------------------------------------------------------------
+@@ -660,8 +720,8 @@
+   "TARGET_MB_64"
+   "@
+    rsubl\t%0,%2,%1
+-   addik\t%0,%z1,-%2
+-   addik\t%0,%z1,-%2"
++   addlik\t%0,%z1,-%2
++   addlik\t%0,%z1,-%2"
+   [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4,4,4")])
+diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
+index 35ab9654052..dfef45c268e 100644
+--- a/gcc/config/microblaze/t-microblaze
++++ b/gcc/config/microblaze/t-microblaze
+@@ -1,6 +1,13 @@
+ MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
+ MULTILIB_DIRNAMES = m64 bs le m mh
+ MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
++MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
++MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch
deleted file mode 100644
index 6329012977..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0036-re-arrangement-of-the-compare-branches.patch
+++ /dev/null
@@ -1,268 +0,0 @@
-From e259b63769bf3cc437a665059add98d9480d942c Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 3 Aug 2018 15:41:39 +0530
-Subject: [PATCH 36/58] re-arrangement of the compare branches
-
----
- gcc/config/microblaze/microblaze.c  |  28 ++----
- gcc/config/microblaze/microblaze.md | 141 +++++++++++++---------------
- 2 files changed, 73 insertions(+), 96 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 3ecda553fe6..cba5d86225c 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -3827,11 +3827,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-     {
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == Pmode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
--
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
- 
-   else if (code == EQ || code == NE)
-@@ -3842,10 +3838,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
-       else
-         emit_insn (gen_xordi3 (comp_reg, cmp_op0, cmp_op1));
-       condition = gen_rtx_fmt_ee (signed_condition (code), mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else
-     {
-@@ -3878,10 +3871,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-       comp_reg = cmp_op0;
-       condition = gen_rtx_fmt_ee (signed_condition (code),
-                                   mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else if (code == EQ)
-     {
-@@ -3896,10 +3886,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-                                            cmp_op1));
- 	}
-       condition = gen_rtx_EQ (mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-  
-     }
-   else if (code == NE)
-@@ -3915,10 +3902,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
-                                            cmp_op1));
- 	}
-       condition = gen_rtx_NE (mode, comp_reg, const0_rtx);
--      if (mode == SImode)
--        emit_jump_insn (gen_condjump (condition, label1));
--      else
--        emit_jump_insn (gen_long_condjump (condition, label1));
-+      emit_jump_insn (gen_condjump (condition, label1));
-     }
-   else
-     {
-@@ -3960,7 +3944,7 @@ microblaze_expand_conditional_branch_df (rtx operands[])
- 
-   emit_insn (gen_cstoredf4 (comp_reg, operands[0], cmp_op0, cmp_op1));
-   condition = gen_rtx_NE (Pmode, comp_reg, const0_rtx);
--  emit_jump_insn (gen_long_condjump (condition, operands[3]));
-+  emit_jump_insn (gen_condjump (condition, operands[3]));
- }
- 
- /* Implement TARGET_FRAME_POINTER_REQUIRED.  */
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index bef750c026a..29ebbfc0c03 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2270,7 +2270,27 @@ else
- 		      (label_ref (match_operand 1))
- 		      (pc)))])
- 
--(define_insn "branch_zero64"
-+(define_insn "branch_zero_64"
-+  [(set (pc)
-+	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-+  				 [(match_operand:SI 1 "register_operand" "d")
-+                                  (const_int 0)])
-+                      (match_operand:SI 2 "pc_or_label_operand" "")
-+                      (match_operand:SI 3 "pc_or_label_operand" "")))
-+  ]
-+  "TARGET_MB_64"
-+  {
-+    if (operands[3] == pc_rtx) 
-+      return "bea%C0i%?\t%z1,%2";
-+    else 
-+      return "bea%N0i%?\t%z1,%3";
-+  }
-+  [(set_attr "type"	"branch")
-+   (set_attr "mode"	"none")
-+   (set_attr "length"	"4")]
-+)
-+
-+(define_insn "long_branch_zero"
-   [(set (pc)
- 	(if_then_else (match_operator 0 "ordered_comparison_operator"
-   				 [(match_operand 1 "register_operand" "d")
-@@ -2281,9 +2301,9 @@ else
-   "TARGET_MB_64"
-   {
-     if (operands[3] == pc_rtx) 
--      return "bea%C0i%?\t%z1,%2";
-+      return "beal%C0i%?\t%z1,%2";
-     else 
--      return "bea%N0i%?\t%z1,%3";
-+      return "beal%N0i%?\t%z1,%3";
-   }
-   [(set_attr "type"	"branch")
-    (set_attr "mode"	"none")
-@@ -2312,9 +2332,9 @@ else
- 
- (define_insn "branch_compare64"
-   [(set (pc)
--        (if_then_else (match_operator 0 "cmp_op"
--                                         [(match_operand 1 "register_operand" "d")
--                                          (match_operand 2 "register_operand" "d")
-+        (if_then_else (match_operator:SI 0 "cmp_op"
-+                                         [(match_operand:SI 1 "register_operand" "d")
-+                                          (match_operand:SI 2 "register_operand" "d")
-                                          ])
-                       (label_ref (match_operand 3))
-                       (pc)))
-@@ -2351,6 +2371,47 @@ else
-    (set_attr "length"   "12")]
- )
- 
-+(define_insn "long_branch_compare"
-+  [(set (pc)
-+        (if_then_else (match_operator 0 "cmp_op"
-+                                         [(match_operand 1 "register_operand" "d")
-+                                          (match_operand 2 "register_operand" "d")
-+                                         ])
-+                      (label_ref (match_operand 3))
-+                      (pc)))
-+  (clobber(reg:DI R_TMP))]
-+  "TARGET_MB_64"
-+  {
-+    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    enum rtx_code code = GET_CODE (operands[0]);
-+
-+    if (code == GT || code == LE)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GTU || code == LEU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
-+        code = swap_condition (code);
-+      }
-+    else if (code == GE || code == LT)
-+      {
-+        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
-+      }
-+    else if (code == GEU || code == LTU)
-+      {
-+        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
-+      }
-+
-+    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
-+    return "beal%C0i%?\tr18,%3";
-+  }
-+  [(set_attr "type"     "branch")
-+   (set_attr "mode"     "none")
-+   (set_attr "length"   "12")]
-+)
-+
- (define_insn "branch_compare"
-   [(set (pc)
-         (if_then_else (match_operator:SI 0 "cmp_op"
-@@ -2433,74 +2494,6 @@ else
- 
- })
- 
--;; Used to implement comparison instructions
--(define_expand "long_condjump"
--  [(set (pc)
--	(if_then_else (match_operand 0)
--		      (label_ref (match_operand 1))
--		      (pc)))])
--
--(define_insn "long_branch_zero"
--  [(set (pc)
--	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
--  				 [(match_operand:DI 1 "register_operand" "d")
--                                  (const_int 0)])
--                      (match_operand:DI 2 "pc_or_label_operand" "")
--                      (match_operand:DI 3 "pc_or_label_operand" "")))
--  ]
--  "TARGET_MB_64"
--  {
--    if (operands[3] == pc_rtx) 
--      return "beal%C0i%?\t%z1,%2";
--    else 
--      return "beal%N0i%?\t%z1,%3";
--  }
--  [(set_attr "type"	"branch")
--   (set_attr "mode"	"none")
--   (set_attr "length"	"4")]
--)
--
--(define_insn "long_branch_compare"
--  [(set (pc)
--        (if_then_else (match_operator:DI 0 "cmp_op"
--                                         [(match_operand:DI 1 "register_operand" "d")
--                                          (match_operand:DI 2 "register_operand" "d")
--                                         ])
--                      (label_ref (match_operand 3))
--                      (pc)))
--  (clobber(reg:DI R_TMP))]
--  "TARGET_MB_64"
--  {
--    operands[4] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
--    enum rtx_code code = GET_CODE (operands[0]);
--
--    if (code == GT || code == LE)
--      {
--        output_asm_insn ("cmpl\tr18,%z1,%z2", operands);
--        code = swap_condition (code);
--      }
--    else if (code == GTU || code == LEU)
--      {
--        output_asm_insn ("cmplu\tr18,%z1,%z2", operands);
--        code = swap_condition (code);
--      }
--    else if (code == GE || code == LT)
--      {
--        output_asm_insn ("cmpl\tr18,%z2,%z1", operands);
--      }
--    else if (code == GEU || code == LTU)
--      {
--        output_asm_insn ("cmplu\tr18,%z2,%z1", operands);
--      }
--
--    operands[0] = gen_rtx_fmt_ee (signed_condition (code), DImode, operands[4], const0_rtx);
--    return "beal%C0i%?\tr18,%3";
--  }
--  [(set_attr "type"     "branch")
--   (set_attr "mode"     "none")
--   (set_attr "length"   "12")]
--)
--
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
new file mode 100644
index 0000000000..2253b75997
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
@@ -0,0 +1,37 @@
+From 2feba7c8902be8d5c4cc99feca0581472c16de0c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 12 Oct 2018 16:07:36 +0530
+Subject: [PATCH 37/54] Fixed the issue in the delay slot with swap
+ instructions
+
+---
+ gcc/config/microblaze/microblaze.md | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 1401d6b77ff..a91108cf0e5 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -443,6 +443,9 @@
+         (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
+   "TARGET_REORDER"
+   "swapb %0, %1"
++  [(set_attr "type"	"no_delay_arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"4")]
+ )
+ 
+ (define_insn "bswaphi2"
+@@ -451,6 +454,9 @@
+   "TARGET_REORDER"
+   "swapb %0, %1
+    swaph %0, %0"
++  [(set_attr "type"	"no_delay_arith")
++   (set_attr "mode"	"SI")
++   (set_attr "length"	"8")]
+ )
+ 
+ ;;----------------------------------------------------------------
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch
deleted file mode 100644
index 9be04781bd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 589c4453ab01570d47e6e37e4e546d65398cf58e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 8 Aug 2018 17:37:26 +0530
-Subject: [PATCH 37/58] [Patch,Microblaze] :  previous commit broke the
- handling of SI Branch compare for Microblaze 32-bit..
-
----
- gcc/config/microblaze/microblaze.md | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 29ebbfc0c03..1a8853056d7 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2226,8 +2226,8 @@ else
- (define_expand "cbranchsi4"
-   [(set (pc)
-         (if_then_else (match_operator 0 "ordered_comparison_operator"
--                       [(match_operand 1 "register_operand")
--                        (match_operand 2 "arith_operand" "I,i")])
-+                       [(match_operand:SI 1 "register_operand")
-+                        (match_operand:SI 2 "arith_operand" "I,i")])
-                       (label_ref (match_operand 3 ""))
-                       (pc)))]
-   ""
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
new file mode 100644
index 0000000000..57905e66c6
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
@@ -0,0 +1,256 @@
+From 10d59c50195cff30c4e74959ef4cebc9065808a4 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sat, 13 Oct 2018 21:12:43 +0530
+Subject: [PATCH 38/54] Fixed the load store issue with the 32bit arith
+ libraries
+
+---
+ libgcc/config/microblaze/divsi3.S  | 25 ++++++++++++++++++++++++-
+ libgcc/config/microblaze/modsi3.S  | 26 +++++++++++++++++++++++++-
+ libgcc/config/microblaze/mulsi3.S  |  3 +++
+ libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
+ libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
+ 5 files changed, 98 insertions(+), 4 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index bb047094e2f..104243e35fe 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -41,6 +41,17 @@
+ 	.globl	__divsi3
+ 	.ent	__divsi3
+ 	.type	__divsi3,@function
++#ifdef __arch64__
++        .align 3
++__divsi3:
++	.frame	r1,0,r15	
++
++	ADDIK   r1,r1,-32
++	SLI     r28,r1,0
++	SLI     r29,r1,8
++	SLI     r30,r1,16
++	SLI     r31,r1,24
++#else
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -49,7 +60,7 @@ __divsi3:
+ 	SWI     r29,r1,4
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+-
++#endif
+ 	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEID   r5,$LaR5_Pos 
+@@ -89,6 +100,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r28,r1,0
++	LLI     r29,r1,8
++	LLI     r30,r1,16
++	LLI     r31,r1,24
++	ADDLIK  r1,r1,32
++	RTSD    r15,8
++	NOP
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	LWI     r28,r1,0
+@@ -97,6 +119,7 @@ $LaRETURN_HERE:
+ 	LWI     r31,r1,12
+ 	RTSD    r15,8
+ 	ADDIK   r1,r1,16
++#endif
+ .end __divsi3
+ 	.size	__divsi3, . - __divsi3
+ 
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 9692ff310ff..9500d64bdc0 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -41,6 +41,17 @@
+ 	.globl	__modsi3
+ 	.ent	__modsi3
+ 	.type	__modsi3,@function
++#ifdef __arch64__
++        .align 3
++__modsi3:
++	.frame	r1,0,r15	
++
++	addlik	r1,r1,-32
++	sli	r28,r1,0
++	sli	r29,r1,8
++	sli	r30,r1,16
++	sli	r31,r1,24
++#else
+ __modsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -49,6 +60,7 @@ __modsi3:
+ 	swi	r29,r1,4
+ 	swi	r30,r1,8
+ 	swi	r31,r1,12
++#endif
+ 
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+@@ -88,6 +100,18 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli	r28,r1,0
++	lli	r29,r1,8
++	lli	r30,r1,16
++	lli	r31,r1,24
++	addik	r1,r1,32
++	rtsd	r15,8
++	nop
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	lwi	r28,r1,0
+@@ -95,7 +119,7 @@ $LaRETURN_HERE:
+ 	lwi	r30,r1,8
+ 	lwi	r31,r1,12
+ 	rtsd	r15,8
+-	addik	r1,r1,16
++#endif
+         .end __modsi3
+ 	.size	__modsi3, . - __modsi3
+ 
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index cb3b6b8321f..2044399db4a 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -41,6 +41,9 @@
+ 	.globl	__mulsi3
+ 	.ent	__mulsi3
+ 	.type	__mulsi3,@function
++#ifdef __arch64__
++        .align 3
++#endif
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index ee2bdd0950d..d2332bcfe62 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -41,6 +41,16 @@
+ 	.globl	__udivsi3
+ 	.ent	__udivsi3
+ 	.type	__udivsi3,@function
++#ifdef __arch64__
++        .align 3
++__udivsi3:
++	.frame	r1,0,r15	
++
++	ADDLIK   r1,r1,-24
++    	SLI     r29,r1,0
++	SLI     r30,r1,8
++	SLI     r31,r1,16
++#else
+ __udivsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -48,7 +58,7 @@ __udivsi3:
+     	SWI     r29,r1,0
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+-
++#endif
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
+ 	ADDIK   r30,r0,0                    # Clear mod
+@@ -98,6 +108,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++        # Restore values of CSRs and that of r3 and the divisor and the dividend
++	LLI     r29,r1,0
++	LLI     r30,r1,8
++	LLI     r31,r1,16
++	ADDIK   r1,r1,24
++	RTSD    r15,8
++	NOP
++#else
+ $LaRETURN_HERE:
+         # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	LWI     r29,r1,0
+@@ -105,5 +126,6 @@ $LaRETURN_HERE:
+ 	LWI     r31,r1,8
+ 	RTSD    r15,8
+ 	ADDIK   r1,r1,12
++#endif
+         .end __udivsi3
+ 	.size	__udivsi3, . - __udivsi3
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 12c082f6417..30bd8c20b58 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -41,6 +41,16 @@
+ 	.globl	__umodsi3
+ 	.ent	__umodsi3
+ 	.type	__umodsi3,@function
++#ifdef __arch64__
++        .align 3
++__umodsi3:
++	.frame	r1,0,r15	
++
++	addik	r1,r1,-24
++	swi	r29,r1,0
++	swi	r30,r1,8
++	swi	r31,r1,16
++#else
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+@@ -48,7 +58,7 @@ __umodsi3:
+ 	swi	r29,r1,0
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+-
++#endif
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
+ 	ADDIK 	r3,r0,0                  # Clear div
+@@ -101,6 +111,17 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
++
++#ifdef __arch64__
++$LaRETURN_HERE:
++# Restore values of CSRs and that of r3 and the divisor and the dividend
++	lli 	r29,r1,0
++	lli 	r30,r1,8
++	lli 	r31,r1,16
++	addlik 	r1,r1,24
++	rtsd 	r15,8
++	nop
++#else
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+ 	lwi 	r29,r1,0
+@@ -108,5 +129,6 @@ $LaRETURN_HERE:
+ 	lwi 	r31,r1,8
+ 	rtsd 	r15,8
+ 	addik 	r1,r1,12
++#endif
+ .end __umodsi3
+ 	.size	__umodsi3, . - __umodsi3
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch
deleted file mode 100644
index 464b5a6d5d..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch
+++ /dev/null
@@ -1,73 +0,0 @@
-From cfc6628cdf81a7ab268d2699c9bbc465865681c5 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 11 Sep 2018 13:43:48 +0530
-Subject: [PATCH 38/58] [Patch, Microblaze] : Support of multilibs with m64 ...
-
----
- gcc/config/microblaze/microblaze-c.c  |  1 +
- gcc/config/microblaze/t-microblaze    | 15 ++++++---------
- libgcc/config/microblaze/t-microblaze | 11 +++--------
- 3 files changed, 10 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze-c.c b/gcc/config/microblaze/microblaze-c.c
-index dbcd21fc6ee..db543edcbe5 100644
---- a/gcc/config/microblaze/microblaze-c.c
-+++ b/gcc/config/microblaze/microblaze-c.c
-@@ -102,6 +102,7 @@ microblaze_cpp_define (cpp_reader *pfile)
-     }
-   if (TARGET_MB_64)
-     {
-+      builtin_define ("__microblaze64");
-       builtin_define ("__arch64__");
-       builtin_define ("__microblaze64__");
-       builtin_define ("__MICROBLAZE64__");
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 9fc80b142ce..35ab9654052 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,12 +1,9 @@
--MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high mlittle-endian m64
--MULTILIB_DIRNAMES = bs m mh le m64
--MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/mlittle-endian/m64
--MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high/m64 mxl-multiply-high
--MULTILIB_EXCEPTIONS += mxl-multiply-high/mlittle-endian
--MULTILIB_EXCEPTIONS += mxl-multiply-high/m64
--MULTILIB_EXCEPTIONS += *mxl-multiply-high/mlittle-endian/m64
-+MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
-+MULTILIB_DIRNAMES = m64 bs le m mh
-+MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
-diff --git a/libgcc/config/microblaze/t-microblaze b/libgcc/config/microblaze/t-microblaze
-index 35021b24b7d..8d954a49575 100644
---- a/libgcc/config/microblaze/t-microblaze
-+++ b/libgcc/config/microblaze/t-microblaze
-@@ -1,16 +1,11 @@
--LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3 \
--			_divdi3 _moddi3 _muldi3 _udivdi3 _umoddi3 
-+LIB2FUNCS_EXCLUDE += _divsi3 _modsi3 _mulsi3 _udivsi3 _umodsi3
- 
- LIB2ADD += \
-         $(srcdir)/config/microblaze/divsi3.S \
--        $(srcdir)/config/microblaze/divdi3.S \
-         $(srcdir)/config/microblaze/modsi3.S \
--        $(srcdir)/config/microblaze/moddi3.S \
-+        $(srcdir)/config/microblaze/muldi3_hard.S \
-         $(srcdir)/config/microblaze/mulsi3.S \
--        $(srcdir)/config/microblaze/muldi3.S \
-         $(srcdir)/config/microblaze/stack_overflow_exit.S \
-         $(srcdir)/config/microblaze/udivsi3.S \
--        $(srcdir)/config/microblaze/udivdi3.S \
-         $(srcdir)/config/microblaze/umodsi3.S \
--        $(srcdir)/config/microblaze/umoddi3.S \
--        $(srcdir)/config/microblaze/divsi3_table.c \
-+        $(srcdir)/config/microblaze/divsi3_table.c
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch
deleted file mode 100644
index c9d4b8c710..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-Fix-various-issues.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 0405777c25bb8110ebfd8ea69c7df062a4c03d6b Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 11 Sep 2018 14:58:00 +0530
-Subject: [PATCH 39/58] Fix various issues
-
-Fixed issues like:
-1 Interrupt alignment issue
-2 Sign extension issue
----
- gcc/config/microblaze/microblaze.c  | 16 ++++++++++------
- gcc/config/microblaze/microblaze.md |  2 +-
- 2 files changed, 11 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index cba5d86225c..b94902b8fbb 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2307,9 +2307,14 @@ compute_frame_size (HOST_WIDE_INT size)
- 
-   total_size += gp_reg_size;
- 
--  /* Add 4 bytes for MSR.  */
-+  /* Add 4/8 bytes for MSR.  */
-   if (microblaze_is_interrupt_variant ())
--    total_size += 4;
-+    {
-+      if (TARGET_MB_64)
-+        total_size += 8;
-+      else
-+        total_size += 4;
-+    }
- 
-   /* No space to be allocated for link register in leaf functions with no other
-      stack requirements.  */
-@@ -2594,7 +2599,6 @@ print_operand (FILE * file, rtx op, int letter)
-   else if (letter == 'h' || letter == 'j')
-     {
-       long val[2];
--      int val1[2];
-       long l[2];
-       if (code == CONST_DOUBLE)
- 	{
-@@ -2609,10 +2613,10 @@ print_operand (FILE * file, rtx op, int letter)
- 	}
-       else if (code == CONST_INT || code == CONST)// || code == SYMBOL_REF ||code == LABEL_REF)
-         {
--	  val1[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
--	  val1[1] = INTVAL (op) & 0x00000000ffffffffLL;
-+	  val[0] = (INTVAL (op) & 0xffffffff00000000LL) >> 32;
-+	  val[1] = INTVAL (op) & 0x00000000ffffffffLL;
-         }
--      fprintf (file, "0x%8.8lx", (letter == 'h') ? val1[0] : val1[1]);
-+      fprintf (file, "0x%8.8lx", (letter == 'h') ? val[0] : val[1]);
-     }
-   else if (code == CONST_DOUBLE)
-     {
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 1a8853056d7..7cc26e7d786 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1096,7 +1096,7 @@
-       case 1:
-       case 2:
-         {
--          output_asm_insn ("ll%i1\t%0,%1", operands);
-+          output_asm_insn ("lw%i1\t%0,%1", operands);
-           return "sextl32\t%0,%0";
-         }
-     } 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
new file mode 100644
index 0000000000..8f46859ac3
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch
@@ -0,0 +1,25 @@
+From e51fb2d87f412d1f7045050c5c2df664766de706 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 15 Oct 2018 12:00:10 +0530
+Subject: [PATCH 39/54] extending the Dwarf support to 64bit Microblaze
+
+---
+ gcc/config/microblaze/microblaze.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 60c552958b8..747adcc7a70 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
+ /* Use DWARF 2 debugging information by default.  */
+ #define DWARF2_DEBUGGING_INFO 1
+ #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+-#define DWARF2_ADDR_SIZE 4
++#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
+ 
+ /* Target machine storage layout */
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch
deleted file mode 100644
index d5fbf703ec..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-Fixed-below-issues.patch
+++ /dev/null
@@ -1,304 +0,0 @@
-From c4d60b379c8d0a5621a0dc2a3a12fb40fe45e83e Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 26 Nov 2019 17:26:15 +0530
-Subject: [PATCH 40/58] Fixed below issues:
-
-- Floating point print issues in 64bit mode
-- Dejagnu Jump related issues
-- Added dbl instruction
----
- gcc/config/microblaze/microblaze.c  | 12 +++-
- gcc/config/microblaze/microblaze.h  |  7 +++
- gcc/config/microblaze/microblaze.md | 86 ++++++++++++++++++++++++-----
- libgcc/config/microblaze/crti.S     | 24 +++++++-
- libgcc/config/microblaze/crtn.S     | 13 +++++
- 5 files changed, 125 insertions(+), 17 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index b94902b8fbb..12b1da852dd 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -2603,7 +2603,12 @@ print_operand (FILE * file, rtx op, int letter)
-       if (code == CONST_DOUBLE)
- 	{
- 	  if (GET_MODE (op) == DFmode)
--	    REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+            {
-+  	      if (TARGET_MB_64)
-+	        REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+	      else
-+	        REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), val);
-+	    }
- 	  else
- 	    {
-               REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
-@@ -4006,7 +4011,10 @@ microblaze_expand_divide (rtx operands[])
-                             gen_rtx_PLUS (QImode, regt1, div_table_rtx));
- 
-   insn = emit_insn (gen_zero_extendqisi2(operands[0],mem_rtx));
--  jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-+  if (TARGET_MB_64) 
-+    jump = emit_jump_insn_after (gen_jump_64 (div_end_label), insn);
-+  else 
-+    jump = emit_jump_insn_after (gen_jump (div_end_label), insn); 
-   JUMP_LABEL (jump) = div_end_label;
-   LABEL_NUSES (div_end_label) = 1; 
-   emit_barrier ();
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 1f6e2059545..a36e06316aa 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -888,10 +888,17 @@ do {									 \
- /* We do this to save a few 10s of code space that would be taken up
-    by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
-    definition in crtstuff.c.  */
-+#ifdef __arch64__
-+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
-+    asm ( SECTION_OP "\n"                               \
-+          "\tbrealid   r15, " #FUNC "\n\t nop\n"         \
-+          TEXT_SECTION_ASM_OP);
-+#else
- #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC)	\
-     asm ( SECTION_OP "\n"                               \
-           "\tbrlid   r15, " #FUNC "\n\t nop\n"         \
-           TEXT_SECTION_ASM_OP);
-+#endif
- 
- /* We need to group -lm as well, since some Newlib math functions 
-    reference __errno!  */
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 7cc26e7d786..013c77651c3 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -527,6 +527,15 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "floatdidf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (float:DF (match_operand:DI 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dbl\t%0,%1"
-+  [(set_attr "type"     "fcvt")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
- (define_insn "fix_truncsfsi2"
-   [(set (match_operand:SI 0 "register_operand" "=d")
-         (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-@@ -1300,7 +1309,7 @@
- (define_insn "movdi_long_int"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- 	(match_operand:DI 1 "general_operand"      "i"))]
--  ""
-+  "TARGET_MB_64"
-   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-   [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-@@ -1583,7 +1592,7 @@
-           return "ll%i1\t%0,%1";
-       case 3:
-       {
--	return "addlik\t%0,r0,%h1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #Xfer Lo";
-+	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-       }
-       case 5:
- 	return "sl%i0\t%1,%0";
-@@ -2373,9 +2382,9 @@ else
- 
- (define_insn "long_branch_compare"
-   [(set (pc)
--        (if_then_else (match_operator 0 "cmp_op"
--                                         [(match_operand 1 "register_operand" "d")
--                                          (match_operand 2 "register_operand" "d")
-+        (if_then_else (match_operator:DI 0 "cmp_op"
-+                                         [(match_operand:DI 1 "register_operand" "d")
-+                                          (match_operand:DI 2 "register_operand" "d")
-                                          ])
-                       (label_ref (match_operand 3))
-                       (pc)))
-@@ -2497,6 +2506,20 @@ else
- ;;----------------------------------------------------------------
- ;; Unconditional branches
- ;;----------------------------------------------------------------
-+(define_insn "jump_64"
-+  [(set (pc)
-+	(label_ref (match_operand 0 "" "")))]
-+  "TARGET_MB_64"
-+  {
-+    if (GET_CODE (operands[0]) == REG)
-+        return "brea%?\t%0";
-+    else	
-+        return "breai%?\t%l0";
-+  }
-+  [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_insn "jump"
-   [(set (pc)
- 	(label_ref (match_operand 0 "" "")))]
-@@ -2542,17 +2565,25 @@ else
-   {
-     //gcc_assert (GET_MODE (operands[0]) == Pmode);
- 
--    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL)
--      emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
--    else
--      emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+    if (!flag_pic || TARGET_PIC_DATA_TEXT_REL) {
-+        if (!TARGET_MB_64)
-+          emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
-+        else
-+          emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
-+      }
-+    else {
-+        if (!TARGET_MB_64)
-+          emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
-+        else
-+          emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
-+      }
-     DONE;
-   }
- )
- 
- (define_insn "tablejump_internal1"
-   [(set (pc)
--	(match_operand 0 "register_operand" "d"))
-+	(match_operand:SI 0 "register_operand" "d"))
-   (use (label_ref (match_operand 1 "" "")))]
-   ""
-   "bra%?\t%0 "
-@@ -2560,11 +2591,21 @@ else
-   (set_attr "mode"	"none")
-   (set_attr "length"	"4")])
- 
-+(define_insn "tablejump_internal2"
-+  [(set (pc)
-+	(match_operand:DI 0 "register_operand" "d"))
-+  (use (label_ref (match_operand 1 "" "")))]
-+  "TARGET_MB_64"
-+  "bra%?\t%0 "
-+  [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
- (define_expand "tablejump_internal3"
-   [(parallel [(set (pc)
--		   (plus (match_operand 0 "register_operand" "d")
--			    (label_ref (match_operand:SI 1 "" ""))))
--             (use (label_ref (match_dup 1)))])]
-+		   (plus:SI (match_operand:SI 0 "register_operand" "d")
-+			    (label_ref:SI (match_operand:SI 1 "" ""))))
-+             (use (label_ref:SI (match_dup 1)))])]
-   ""
-   ""
- )
-@@ -2595,6 +2636,23 @@ else
-   ""
- )
- 
-+(define_insn ""
-+ [(set (pc)
-+	(plus:DI (match_operand:DI 0 "register_operand" "d")
-+		 (label_ref:DI (match_operand 1 "" ""))))
-+  (use (label_ref:DI (match_dup 1)))]
-+ "TARGET_MB_64 && NEXT_INSN (as_a <rtx_insn *> (operands[1])) != 0
-+  && GET_CODE (PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[1])))) == ADDR_DIFF_VEC
-+  && flag_pic"
-+  {
-+    output_asm_insn ("addlk\t%0,%0,r20",operands);
-+    return "bra%?\t%0";
-+}
-+ [(set_attr "type"	"jump")
-+  (set_attr "mode"	"none")
-+  (set_attr "length"	"4")])
-+
-+
- ;;----------------------------------------------------------------
- ;; Function prologue/epilogue and stack allocation
- ;;----------------------------------------------------------------
-@@ -3101,7 +3159,7 @@ else
- ;; The insn to set GOT. The hardcoded number "8" accounts for $pc difference
- ;; between "mfs" and "addik" instructions.
- (define_insn "set_got"
--  [(set (match_operand:SI 0 "register_operand" "=r")
-+  [(set (match_operand 0 "register_operand" "=r")
-     (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))]
-   ""
-   "mfs\t%0,rpc\n\taddik\t%0,%0,_GLOBAL_OFFSET_TABLE_+8"
-diff --git a/libgcc/config/microblaze/crti.S b/libgcc/config/microblaze/crti.S
-index 005825f1ec5..b7436c7131f 100644
---- a/libgcc/config/microblaze/crti.S
-+++ b/libgcc/config/microblaze/crti.S
-@@ -33,11 +33,32 @@
-     .section .init, "ax"
-     .global __init
- 
-+#ifdef __arch64__
-     .weak _stack
--    .set  _stack, 0xffffffff
-+    .set  _stack, 0xffffffffffffffff
-     .weak _stack_end
-     .set  _stack_end, 0
- 
-+    .align 3
-+__init: 
-+    addlik  r1, r1, -32
-+    sl      r15, r0, r1
-+    addlik  r11, r0, _stack
-+    mts     rshr, r11
-+    addlik  r11, r0, _stack_end
-+    mts     rslr, r11
-+
-+    .section .fini, "ax"
-+    .global __fini
-+    .align 3
-+__fini: 
-+    addlik   r1, r1, -32
-+    sl       r15, r0, r1
-+#else
-+    .weak _stack
-+    .set  _stack, 0xffffffff
-+    .weak _stack_end
-+    .set  _stack_end, 0
-     .align 2
- __init: 
-     addik   r1, r1, -16
-@@ -53,3 +74,4 @@ __init:
- __fini: 
-     addik   r1, r1, -16
-     sw      r15, r0, r1
-+#endif
-diff --git a/libgcc/config/microblaze/crtn.S b/libgcc/config/microblaze/crtn.S
-index 5705eff9a4a..f1148ffebe4 100644
---- a/libgcc/config/microblaze/crtn.S
-+++ b/libgcc/config/microblaze/crtn.S
-@@ -29,7 +29,19 @@
- .section .note.GNU-stack,"",%progbits
- .previous
- #endif
-+#ifdef __arch64__
-+    .section .init, "ax"
-+    ll      r15, r0, r1
-+    addlik   r1, r1, 32
-+    rtsd    r15, 8
-+    nop 
- 
-+    .section .fini, "ax"
-+    ll      r15, r0, r1
-+    addlik   r1, r1, 32   
-+    rtsd    r15, 8
-+    nop 
-+#else
-     .section .init, "ax"
-     lw      r15, r0, r1
-     rtsd    r15, 8 
-@@ -39,3 +51,4 @@
-     lw      r15, r0, r1
-     rtsd    r15, 8 
-     addik   r1, r1, 16   
-+#endif
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch
new file mode 100644
index 0000000000..e7e581e3e4
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0040-fixing-the-typo-errors-in-umodsi3-file.patch
@@ -0,0 +1,29 @@
+From 61be4b342d470aeb7ad1c0cc5e90f5afdc906c00 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 16 Oct 2018 07:55:46 +0530
+Subject: [PATCH 40/54] fixing the typo errors in umodsi3 file
+
+---
+ libgcc/config/microblaze/umodsi3.S | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 30bd8c20b58..2dd72aef68e 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -47,9 +47,9 @@ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+ 	addik	r1,r1,-24
+-	swi	r29,r1,0
+-	swi	r30,r1,8
+-	swi	r31,r1,16
++	sli	r29,r1,0
++	sli	r30,r1,8
++	sli	r31,r1,16
+ #else
+ __umodsi3:
+ 	.frame	r1,0,r15	
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch
deleted file mode 100644
index 75ee48fa63..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-Fix-various.patch
+++ /dev/null
@@ -1,136 +0,0 @@
-From 90edf612331af9b7e99105112c2067a3f085daef Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 9 Oct 2018 10:07:08 +0530
-Subject: [PATCH 41/58] Fix various
-
--Added double arith instructions
--Fixed prologue stack pointer decrement issue
----
- gcc/config/microblaze/microblaze.md | 78 +++++++++++++++++++++++++----
- gcc/config/microblaze/t-microblaze  |  7 +++
- 2 files changed, 76 insertions(+), 9 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 013c77651c3..645f48f2847 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -527,6 +527,66 @@
-   (set_attr "mode"      "SF")
-   (set_attr "length"    "4")])
- 
-+(define_insn "fix_truncsfsi2"
-+  [(set (match_operand:SI 0 "register_operand" "=d")
-+        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
-+  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-+  "fint\t%0,%1"
-+  [(set_attr "type"     "fint")
-+  (set_attr "mode"      "SF")
-+  (set_attr "length"    "4")])
-+
-+
-+(define_insn "adddf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (plus:DF (match_operand:DF 1 "register_operand" "d")
-+                 (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dadd\t%0,%1,%2"
-+  [(set_attr "type"     "fadd")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "subdf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (minus:DF (match_operand:DF 1 "register_operand" "d")
-+                  (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "drsub\t%0,%2,%1"
-+  [(set_attr "type"     "frsub")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "muldf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (mult:DF (match_operand:DF 1 "register_operand" "d")
-+                 (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dmul\t%0,%1,%2"
-+  [(set_attr "type"     "fmul")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+(define_insn "divdf3"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (div:DF (match_operand:DF 1 "register_operand" "d")
-+                (match_operand:DF 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "ddiv\t%0,%2,%1"
-+  [(set_attr "type"     "fdiv")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
-+
-+(define_insn "sqrtdf2"
-+  [(set (match_operand:DF 0 "register_operand" "=d")
-+        (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dsqrt\t%0,%1"
-+  [(set_attr "type"     "fsqrt")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4")])
-+
- (define_insn "floatdidf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (float:DF (match_operand:DI 1 "register_operand" "d")))]
-@@ -536,13 +596,13 @@
-   (set_attr "mode"      "DF")
-   (set_attr "length"    "4")])
- 
--(define_insn "fix_truncsfsi2"
--  [(set (match_operand:SI 0 "register_operand" "=d")
--        (fix:SI (match_operand:SF 1 "register_operand" "d")))]
--  "TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
--  "fint\t%0,%1"
--  [(set_attr "type"     "fint")
--  (set_attr "mode"      "SF")
-+(define_insn "floatdfdi2"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (float:DI (match_operand:DF 1 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  "dlong\t%0,%1"
-+  [(set_attr "type"     "fcvt")
-+  (set_attr "mode"      "DI")
-   (set_attr "length"    "4")])
- 
- ;;----------------------------------------------------------------
-@@ -660,8 +720,8 @@
-   "TARGET_MB_64"
-   "@
-    rsubl\t%0,%2,%1
--   addik\t%0,%z1,-%2
--   addik\t%0,%z1,-%2"
-+   addlik\t%0,%z1,-%2
-+   addlik\t%0,%z1,-%2"
-   [(set_attr "type"	"arith,no_delay_arith,no_delay_arith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4,4,4")])
-diff --git a/gcc/config/microblaze/t-microblaze b/gcc/config/microblaze/t-microblaze
-index 35ab9654052..dfef45c268e 100644
---- a/gcc/config/microblaze/t-microblaze
-+++ b/gcc/config/microblaze/t-microblaze
-@@ -1,6 +1,13 @@
- MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
- MULTILIB_DIRNAMES = m64 bs le m mh
- MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
-+MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
new file mode 100644
index 0000000000..9f9afdb9ae
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0041-fixing-the-32bit-LTO-related-issue9-1014024.patch
@@ -0,0 +1,68 @@
+From b1eb7b1f6c33246ded3501364279a5f002cd8de0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Wed, 17 Oct 2018 16:56:14 +0530
+Subject: [PATCH 41/54] fixing the 32bit LTO related issue9(1014024)
+
+---
+ gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
+ 1 file changed, 14 insertions(+), 10 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index 747adcc7a70..bfa7bc9a01c 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
+ #define WORD_REGISTER_OPERATIONS 1
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+-/*
+-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
+-  if (GET_MODE_CLASS (MODE) == MODE_INT		\
+-      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
+-    (MODE) = TARGET_MB_64 ? DImode : SImode;
+-*/
++
++#ifndef __arch64__
++#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
++  if (GET_MODE_CLASS (MODE) == MODE_INT         \
++      && GET_MODE_SIZE (MODE) < 4)              \
++    (MODE) = SImode;
++#endif
++
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
+ 
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
++#ifdef __aarch64__
+ #define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (MODE,GP_RETURN)
+-								
+-/*#define LIBCALL_VALUE(MODE)						\
++#else								
++#define LIBCALL_VALUE(MODE)						\
+   gen_rtx_REG (								\
+ 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+ 	     || GET_MODE_SIZE (MODE) >= 4)				\
+ 	    ? (MODE)							\
+ 	    : SImode), GP_RETURN)
+-*/
++#endif
++
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+@@ -518,7 +522,7 @@ typedef struct microblaze_args
+ /* 4 insns + 2 words of data.  */
+ #define TRAMPOLINE_SIZE				(6 * 4)
+ 
+-#define TRAMPOLINE_ALIGNMENT			64
++#define TRAMPOLINE_ALIGNMENT		(TARGET_MB_64 ? 64 : 32)
+ 
+ #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
deleted file mode 100644
index 2e66625bb5..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From c7f6fb9d81ce322f71cbef7cc1f5cb2fb8956a27 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 12 Oct 2018 16:07:36 +0530
-Subject: [PATCH 42/58] Fixed the issue in the delay slot with swap
- instructions
-
----
- gcc/config/microblaze/microblaze.md | 6 ++++++
- 1 file changed, 6 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 645f48f2847..6a1e45a5b66 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -443,6 +443,9 @@
-         (bswap:SI (match_operand:SI 1 "register_operand" "r")))]
-   "TARGET_REORDER"
-   "swapb %0, %1"
-+  [(set_attr "type"	"no_delay_arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"4")]
- )
- 
- (define_insn "bswaphi2"
-@@ -451,6 +454,9 @@
-   "TARGET_REORDER"
-   "swapb %0, %1
-    swaph %0, %0"
-+  [(set_attr "type"	"no_delay_arith")
-+   (set_attr "mode"	"SI")
-+   (set_attr "length"	"8")]
- )
- 
- ;;----------------------------------------------------------------
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
new file mode 100644
index 0000000000..fb31d663f5
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
@@ -0,0 +1,25 @@
+From e0820fe8c8d9b7504595794fe6e65151d22e2acf Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 19 Oct 2018 14:26:25 +0530
+Subject: [PATCH 42/54] Fixed the missing stack adjustment in prologue of
+ modsi3 function
+
+---
+ libgcc/config/microblaze/modsi3.S | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 9500d64bdc0..4dbb25900d9 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -119,6 +119,7 @@ $LaRETURN_HERE:
+ 	lwi	r30,r1,8
+ 	lwi	r31,r1,12
+ 	rtsd	r15,8
++	addik	r1,r1,16
+ #endif
+         .end __modsi3
+ 	.size	__modsi3, . - __modsi3
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
deleted file mode 100644
index 3d532c6ad4..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch
+++ /dev/null
@@ -1,256 +0,0 @@
-From 16a9a232ae430e691c13157dd5988f9c5c7dfb71 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sat, 13 Oct 2018 21:12:43 +0530
-Subject: [PATCH 43/58] Fixed the load store issue with the 32bit arith
- libraries
-
----
- libgcc/config/microblaze/divsi3.S  | 25 ++++++++++++++++++++++++-
- libgcc/config/microblaze/modsi3.S  | 26 +++++++++++++++++++++++++-
- libgcc/config/microblaze/mulsi3.S  |  3 +++
- libgcc/config/microblaze/udivsi3.S | 24 +++++++++++++++++++++++-
- libgcc/config/microblaze/umodsi3.S | 24 +++++++++++++++++++++++-
- 5 files changed, 98 insertions(+), 4 deletions(-)
-
-diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index bb047094e2f..104243e35fe 100644
---- a/libgcc/config/microblaze/divsi3.S
-+++ b/libgcc/config/microblaze/divsi3.S
-@@ -41,6 +41,17 @@
- 	.globl	__divsi3
- 	.ent	__divsi3
- 	.type	__divsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__divsi3:
-+	.frame	r1,0,r15	
-+
-+	ADDIK   r1,r1,-32
-+	SLI     r28,r1,0
-+	SLI     r29,r1,8
-+	SLI     r30,r1,16
-+	SLI     r31,r1,24
-+#else
- __divsi3:
- 	.frame	r1,0,r15	
- 
-@@ -49,7 +60,7 @@ __divsi3:
- 	SWI     r29,r1,4
- 	SWI     r30,r1,8
- 	SWI     r31,r1,12
--
-+#endif
- 	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
- 	BGEID   r5,$LaR5_Pos 
-@@ -89,6 +100,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r28,r1,0
-+	LLI     r29,r1,8
-+	LLI     r30,r1,16
-+	LLI     r31,r1,24
-+	ADDLIK  r1,r1,32
-+	RTSD    r15,8
-+	NOP
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	LWI     r28,r1,0
-@@ -97,6 +119,7 @@ $LaRETURN_HERE:
- 	LWI     r31,r1,12
- 	RTSD    r15,8
- 	ADDIK   r1,r1,16
-+#endif
- .end __divsi3
- 	.size	__divsi3, . - __divsi3
- 
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 9692ff310ff..9500d64bdc0 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -41,6 +41,17 @@
- 	.globl	__modsi3
- 	.ent	__modsi3
- 	.type	__modsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__modsi3:
-+	.frame	r1,0,r15	
-+
-+	addlik	r1,r1,-32
-+	sli	r28,r1,0
-+	sli	r29,r1,8
-+	sli	r30,r1,16
-+	sli	r31,r1,24
-+#else
- __modsi3:
- 	.frame	r1,0,r15	
- 
-@@ -49,6 +60,7 @@ __modsi3:
- 	swi	r29,r1,4
- 	swi	r30,r1,8
- 	swi	r31,r1,12
-+#endif
- 
- 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
-@@ -88,6 +100,18 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or	r3,r0,r0        # set result to 0 [Both mod as well as div are 0]
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli	r28,r1,0
-+	lli	r29,r1,8
-+	lli	r30,r1,16
-+	lli	r31,r1,24
-+	addik	r1,r1,32
-+	rtsd	r15,8
-+	nop
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	lwi	r28,r1,0
-@@ -95,7 +119,7 @@ $LaRETURN_HERE:
- 	lwi	r30,r1,8
- 	lwi	r31,r1,12
- 	rtsd	r15,8
--	addik	r1,r1,16
-+#endif
-         .end __modsi3
- 	.size	__modsi3, . - __modsi3
- 
-diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index cb3b6b8321f..2044399db4a 100644
---- a/libgcc/config/microblaze/mulsi3.S
-+++ b/libgcc/config/microblaze/mulsi3.S
-@@ -41,6 +41,9 @@
- 	.globl	__mulsi3
- 	.ent	__mulsi3
- 	.type	__mulsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+#endif
- __mulsi3:
- 	.frame	r1,0,r15
- 	add	r3,r0,r0
-diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index ee2bdd0950d..d2332bcfe62 100644
---- a/libgcc/config/microblaze/udivsi3.S
-+++ b/libgcc/config/microblaze/udivsi3.S
-@@ -41,6 +41,16 @@
- 	.globl	__udivsi3
- 	.ent	__udivsi3
- 	.type	__udivsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__udivsi3:
-+	.frame	r1,0,r15	
-+
-+	ADDLIK   r1,r1,-24
-+    	SLI     r29,r1,0
-+	SLI     r30,r1,8
-+	SLI     r31,r1,16
-+#else
- __udivsi3:
- 	.frame	r1,0,r15	
- 
-@@ -48,7 +58,7 @@ __udivsi3:
-     	SWI     r29,r1,0
- 	SWI     r30,r1,4
- 	SWI     r31,r1,8
--
-+#endif
- 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
- 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
- 	ADDIK   r30,r0,0                    # Clear mod
-@@ -98,6 +108,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+        # Restore values of CSRs and that of r3 and the divisor and the dividend
-+	LLI     r29,r1,0
-+	LLI     r30,r1,8
-+	LLI     r31,r1,16
-+	ADDIK   r1,r1,24
-+	RTSD    r15,8
-+	NOP
-+#else
- $LaRETURN_HERE:
-         # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	LWI     r29,r1,0
-@@ -105,5 +126,6 @@ $LaRETURN_HERE:
- 	LWI     r31,r1,8
- 	RTSD    r15,8
- 	ADDIK   r1,r1,12
-+#endif
-         .end __udivsi3
- 	.size	__udivsi3, . - __udivsi3
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 12c082f6417..30bd8c20b58 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -41,6 +41,16 @@
- 	.globl	__umodsi3
- 	.ent	__umodsi3
- 	.type	__umodsi3,@function
-+#ifdef __arch64__
-+        .align 3
-+__umodsi3:
-+	.frame	r1,0,r15	
-+
-+	addik	r1,r1,-24
-+	swi	r29,r1,0
-+	swi	r30,r1,8
-+	swi	r31,r1,16
-+#else
- __umodsi3:
- 	.frame	r1,0,r15	
- 
-@@ -48,7 +58,7 @@ __umodsi3:
- 	swi	r29,r1,0
- 	swi	r30,r1,4
- 	swi	r31,r1,8
--
-+#endif
- 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
- 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
- 	ADDIK 	r3,r0,0                  # Clear div
-@@ -101,6 +111,17 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or 	r3,r0,r0   # set result to 0
-+
-+#ifdef __arch64__
-+$LaRETURN_HERE:
-+# Restore values of CSRs and that of r3 and the divisor and the dividend
-+	lli 	r29,r1,0
-+	lli 	r30,r1,8
-+	lli 	r31,r1,16
-+	addlik 	r1,r1,24
-+	rtsd 	r15,8
-+	nop
-+#else
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
- 	lwi 	r29,r1,0
-@@ -108,5 +129,6 @@ $LaRETURN_HERE:
- 	lwi 	r31,r1,8
- 	rtsd 	r15,8
- 	addik 	r1,r1,12
-+#endif
- .end __umodsi3
- 	.size	__umodsi3, . - __umodsi3
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
new file mode 100644
index 0000000000..ce8b13844e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
@@ -0,0 +1,29 @@
+From 1f288ec920d938accb084dc0d1d6f6115950c014 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 24 Oct 2018 18:31:04 +0530
+Subject: [PATCH 43/54] [Patch,Microblaze] : corrected SPN for dlong
+ instruction mapping.
+
+---
+ gcc/config/microblaze/microblaze.md | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index a91108cf0e5..19801f8edcc 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -602,9 +602,9 @@
+   (set_attr "mode"      "DF")
+   (set_attr "length"    "4")])
+ 
+-(define_insn "floatdfdi2"
++(define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+-        (float:DI (match_operand:DF 1 "register_operand" "d")))]
++        (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+   "TARGET_MB_64"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch
deleted file mode 100644
index d34c103d2c..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From b3766742c4e1d401d4f7cdc55a90262681689a20 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 15 Oct 2018 12:00:10 +0530
-Subject: [PATCH 44/58] extending the Dwarf support to 64bit Microblaze
-
----
- gcc/config/microblaze/microblaze.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index a36e06316aa..8504a841406 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -207,7 +207,7 @@ extern enum pipeline_type microblaze_pipe;
- /* Use DWARF 2 debugging information by default.  */
- #define DWARF2_DEBUGGING_INFO 1
- #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
--#define DWARF2_ADDR_SIZE 4
-+#define DWARF2_ADDR_SIZE (TARGET_MB_64 ? 8 : 4)
- 
- /* Target machine storage layout */
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 0000000000..fec0a2af49
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0044-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,59 @@
+From eed2bf4db9bdfc0da1c3f77ce746fb5bfa460b3c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:55:08 +0530
+Subject: [PATCH 44/54] fixing the long & long long mingw toolchain issue
+
+---
+ gcc/config/microblaze/constraints.md | 2 +-
+ gcc/config/microblaze/microblaze.md  | 8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index b8ef1650f92..89db511c453 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -55,7 +55,7 @@
+ (define_constraint "K"
+   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
++       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
+ 
+ 
+ ;; Define floating point constraints
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 19801f8edcc..8f0ae901b77 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -648,8 +648,8 @@
+   if (TARGET_MB_64) 
+    {
+      if (GET_CODE (operands[2]) == CONST_INT &&
+-       INTVAL(operands[2]) < (long)-549755813888 &&
+-	INTVAL(operands[2]) > (long)549755813887)
++       INTVAL(operands[2]) < (long long)-549755813888 &&
++	INTVAL(operands[2]) > (long long)549755813887)
+       FAIL;
+    }
+ })
+@@ -1266,7 +1266,7 @@
+ 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
+   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
+            (GET_CODE (operands[1]) == CONST_INT && 
+-                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
++                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
+   "@
+    addlk\t%0,r0,r0\t
+    addlik\t%0,r0,%1\t #N1 %X1
+@@ -1300,7 +1300,7 @@
+      case 1:
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+-	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+  	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+         else	
+ 	  return "addlik\t%0,r0,%1";
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
new file mode 100644
index 0000000000..15acc1cbb1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch
@@ -0,0 +1,47 @@
+From 682f65fa3a6b37c207b0d727dd22b6f8cc5d8d3d Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 14 Mar 2019 18:11:04 +0530
+Subject: [PATCH 45/54] Fix the MB-64 bug of handling QI objects
+
+---
+ gcc/config/microblaze/microblaze.md | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 8f0ae901b77..207d2bf1b55 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -2348,11 +2348,11 @@ else
+ 
+ (define_insn "branch_zero_64"
+   [(set (pc)
+-	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
++	(if_then_else (match_operator 0 "ordered_comparison_operator"
+   				 [(match_operand:SI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand:SI 2 "pc_or_label_operand" "")
+-                      (match_operand:SI 3 "pc_or_label_operand" "")))
++                      (match_operand 2 "pc_or_label_operand" "")
++                      (match_operand 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+@@ -2368,11 +2368,11 @@ else
+ 
+ (define_insn "long_branch_zero"
+   [(set (pc)
+-	(if_then_else (match_operator 0 "ordered_comparison_operator"
+-  				 [(match_operand 1 "register_operand" "d")
++	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
++				 [(match_operand:DI 1 "register_operand" "d")
+                                   (const_int 0)])
+-                      (match_operand 2 "pc_or_label_operand" "")
+-                      (match_operand 3 "pc_or_label_operand" "")))
++                      (match_operand:DI 2 "pc_or_label_operand" "")
++                      (match_operand:DI 3 "pc_or_label_operand" "")))
+   ]
+   "TARGET_MB_64"
+   {
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch
deleted file mode 100644
index a69c71ddc9..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0045-fixing-the-typo-errors-in-umodsi3-file.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From bdc9429b5f2300e39ecdf1db63f4d35f8e18a932 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 16 Oct 2018 07:55:46 +0530
-Subject: [PATCH 45/58] fixing the typo errors in umodsi3 file
-
----
- libgcc/config/microblaze/umodsi3.S | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 30bd8c20b58..2dd72aef68e 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -47,9 +47,9 @@ __umodsi3:
- 	.frame	r1,0,r15	
- 
- 	addik	r1,r1,-24
--	swi	r29,r1,0
--	swi	r30,r1,8
--	swi	r31,r1,16
-+	sli	r29,r1,0
-+	sli	r30,r1,8
-+	sli	r31,r1,16
- #else
- __umodsi3:
- 	.frame	r1,0,r15	
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
new file mode 100644
index 0000000000..eebf6ee72f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch
@@ -0,0 +1,87 @@
+From 444a09859149f8d21777a1c859ef2305ff86b211 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Fri, 29 Mar 2019 12:08:39 +0530
+Subject: [PATCH 46/54] [Patch,Microblaze] : We will check the possibility of
+ peephole2 optimization,if we can then we will fix the compiler issue.
+
+---
+ gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------
+ 1 file changed, 38 insertions(+), 25 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 207d2bf1b55..9b88666c0a6 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -882,31 +882,44 @@
+   (set_attr "mode"	"SI")
+   (set_attr "length"	"4")])
+ 
+-(define_peephole2
+-  [(set (match_operand:SI 0 "register_operand")
+-        (fix:SI (match_operand:SF 1 "register_operand")))
+-   (set (pc)
+-        (if_then_else (match_operator 2 "ordered_comparison_operator"
+-                       [(match_operand:SI 3 "register_operand")
+-                        (match_operand:SI 4 "arith_operand")])
+-                      (label_ref (match_operand 5))
+-                      (pc)))]
+-   "TARGET_HARD_FLOAT && !TARGET_MB_64"
+-   [(set (match_dup 1) (match_dup 3))]
+-
+-  {
+-    rtx condition;
+-    rtx cmp_op0 = operands[3];
+-    rtx cmp_op1 = operands[4];
+-    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
+-
+-    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
+-                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
+-    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
+-    emit_jump_insn (gen_condjump (condition, operands[5]));
+-  }
+-)
++;; peephole2 optimization will be done only if fint and if-then-else
++;; are dependent.added condition for the same.
++;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
++;; testcase:
++;;        volatile float vec = 1.0;
++;;        volatile int ci = 2;
++;;        register int cj = (int)(vec);
++;;//        ci=cj;
++;;//      if (ci <0) {
++;;        if (cj < 0) {
++;;                ci = 0;
++;;        }
++;; commenting for now.we will check the possibility of this optimization later
++
++;;(define_peephole2
++;;  [(set (match_operand:SI 0 "register_operand")
++;;        (fix:SI (match_operand:SF 1 "register_operand")))
++;;   (set (pc)
++;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
++;;                       [(match_operand:SI 3 "register_operand")
++;;                        (match_operand:SI 4 "arith_operand")])
++;;                      (label_ref (match_operand 5))
++;;                      (pc)))]
++;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
++;;  [(set (match_dup 1) (match_dup 3))]
++;;  {
++;;    rtx condition;
++;;    rtx cmp_op0 = operands[3];
++;;    rtx cmp_op1 = operands[4];
++;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
++;;
++;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
++;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
++;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
++;;    emit_jump_insn (gen_condjump (condition, operands[5]));
++;;  }
++;;)
+ 
+ ;;----------------------------------------------------------------
+ ;; Negation and one's complement
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch
deleted file mode 100644
index a5f7afb6fc..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0046-fixing-the-32bit-LTO-related-issue9-1014024.patch
+++ /dev/null
@@ -1,68 +0,0 @@
-From 2226c8b836bdc9d0e2a281d971288e4bcb50d503 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Wed, 17 Oct 2018 16:56:14 +0530
-Subject: [PATCH 46/58] fixing the 32bit LTO related issue9(1014024)
-
----
- gcc/config/microblaze/microblaze.h | 24 ++++++++++++++----------
- 1 file changed, 14 insertions(+), 10 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 8504a841406..0c493b6f6e4 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -265,12 +265,14 @@ extern enum pipeline_type microblaze_pipe;
- #define WORD_REGISTER_OPERATIONS 1
- 
- #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
--/*
--#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
--  if (GET_MODE_CLASS (MODE) == MODE_INT		\
--      && GET_MODE_SIZE (MODE) < (TARGET_MB_64 ? 8 : 4)) \
--    (MODE) = TARGET_MB_64 ? DImode : SImode;
--*/
-+
-+#ifndef __arch64__
-+#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
-+  if (GET_MODE_CLASS (MODE) == MODE_INT         \
-+      && GET_MODE_SIZE (MODE) < 4)              \
-+    (MODE) = SImode;
-+#endif
-+
- /* Standard register usage.  */
- 
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -469,16 +471,18 @@ extern struct microblaze_frame_info current_frame_info;
- 
- #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
- 
-+#ifdef __aarch64__
- #define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (MODE,GP_RETURN)
--								
--/*#define LIBCALL_VALUE(MODE)						\
-+#else								
-+#define LIBCALL_VALUE(MODE)						\
-   gen_rtx_REG (								\
- 	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
- 	     || GET_MODE_SIZE (MODE) >= 4)				\
- 	    ? (MODE)							\
- 	    : SImode), GP_RETURN)
--*/
-+#endif
-+
- /* 1 if N is a possible register number for a function value.
-    On the MicroBlaze, R2 R3 are the only register thus used.
-    Currently, R2 are only implemented  here (C has no complex type)  */
-@@ -518,7 +522,7 @@ typedef struct microblaze_args
- /* 4 insns + 2 words of data.  */
- #define TRAMPOLINE_SIZE				(6 * 4)
- 
--#define TRAMPOLINE_ALIGNMENT			64
-+#define TRAMPOLINE_ALIGNMENT		(TARGET_MB_64 ? 64 : 32)
- 
- #define REGNO_OK_FOR_BASE_P(regno)		microblaze_regno_ok_for_base_p ((regno), 1)
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
deleted file mode 100644
index 4229639645..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From 8ed304d49f66bc36b39dac8e804a7cdeda642739 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 19 Oct 2018 14:26:25 +0530
-Subject: [PATCH 47/58] Fixed the missing stack adjustment in prologue of
- modsi3 function
-
----
- libgcc/config/microblaze/modsi3.S | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 9500d64bdc0..4dbb25900d9 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -119,6 +119,7 @@ $LaRETURN_HERE:
- 	lwi	r30,r1,8
- 	lwi	r31,r1,12
- 	rtsd	r15,8
-+	addik	r1,r1,16
- #endif
-         .end __modsi3
- 	.size	__modsi3, . - __modsi3
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
new file mode 100644
index 0000000000..3437881237
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
@@ -0,0 +1,466 @@
+From 7cc6db7ad5bf2fac80a81711c70ac1147ab87b2c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Wed, 17 Apr 2019 12:36:16 +0530
+Subject: [PATCH 47/54] [Patch,MicroBlaze]: fixed typos in mul,div and mod
+ assembly files.
+
+---
+ libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++----
+ libgcc/config/microblaze/modsi3.S  | 40 ++++++++++++++++++---
+ libgcc/config/microblaze/mulsi3.S  | 33 ++++++++++++++++-
+ libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++---
+ libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++---
+ 5 files changed, 212 insertions(+), 20 deletions(-)
+
+diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
+index 104243e35fe..5755e29fbb6 100644
+--- a/libgcc/config/microblaze/divsi3.S
++++ b/libgcc/config/microblaze/divsi3.S
+@@ -46,7 +46,7 @@
+ __divsi3:
+ 	.frame	r1,0,r15	
+ 
+-	ADDIK   r1,r1,-32
++	ADDLIK   r1,r1,-32
+ 	SLI     r28,r1,0
+ 	SLI     r29,r1,8
+ 	SLI     r30,r1,16
+@@ -61,13 +61,23 @@ __divsi3:
+ 	SWI     r30,r1,8
+ 	SWI     r31,r1,12
+ #endif
+-	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+-	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
+-	BGEID   r5,$LaR5_Pos 
++#ifdef __arch64__
++	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++	BEAGEID   r5,$LaR5_Pos
++#else
++        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BGEID   r5,$LaR5_Pos
++#endif
+ 	XOR     r28,r5,r6               # Get the sign of the result
+ 	RSUBI   r5,r5,0                 # Make r5 positive
+ $LaR5_Pos:
+-	BGEI    r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI    r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI   r6,r6,0                 # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK   r30,r0,0                # Clear mod
+@@ -76,26 +86,51 @@ $LaR6_Pos:
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0: 
+-        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#else
++        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30             # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++#else
+ 	BEQi    r29,$LaLOOP_END
++#endif
+ 	ADD     r3,r3,r3                # Shift in the '1' into div
++#ifdef __arch64__
++        BREAI     $LaDIV2                 # Div2
++#else
+ 	BRI     $LaDIV2                 # Div2
++#endif
+ $LaLOOP_END:
++#ifdef __arch64__
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAID    $LaRETURN_HERE
++#else
+ 	BGEI    r28,$LaRETURN_HERE
+ 	BRID    $LaRETURN_HERE
++#endif
+ 	RSUBI   r3,r3,0                 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
+index 4dbb25900d9..b6129f5e822 100644
+--- a/libgcc/config/microblaze/modsi3.S
++++ b/libgcc/config/microblaze/modsi3.S
+@@ -62,40 +62,72 @@ __modsi3:
+ 	swi	r31,r1,12
+ #endif
+ 
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
++        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
++        BEAGEId   r5,$LaR5_Pos
++#else
+ 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
+ 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
+ 	BGEId	r5,$LaR5_Pos 
++#endif
+ 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
+ 	RSUBI	r5,r5,0	                # Make r5 positive
+ $LaR5_Pos:
+-	BGEI	r6,$LaR6_Pos
++#ifdef __arch64__
++	BEAGEI	r6,$LaR6_Pos
++#else
++        BGEI    r6,$LaR6_Pos
++#endif
+ 	RSUBI	r6,r6,0	    # Make r6 positive
+ $LaR6_Pos:
+ 	ADDIK	r3,r0,0      # Clear mod
+ 	ADDIK	r30,r0,0     # clear div
+-	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++#ifdef __arch64__
++	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
+ 			     # the first bit search.
++#else
++        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
++                             # the first bit search.
++#endif
+ 	ADDIK	r29,r0,32    # Initialize the loop count
+    # First part try to find the first '1' in the r5
+ $LaDIV1:
+ 	ADD	r5,r5,r5         # left shift logical r5
+-	BGEID	r5,$LaDIV1       #
++#ifdef __arch64__
++	BEAGEID	r5,$LaDIV1       #
++#else
++        BGEID   r5,$LaDIV1       #
++#endif
+ 	ADDIK	r29,r29,-1
+ $LaDIV2:
+ 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
+ 	ADDC	r3,r3,r3         # Move that bit into the Mod register
+ 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTi    r31,$LaMOD_TOO_SMALL
++#else
+ 	BLTi	r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
+ 	ADDIK	r30,r30,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK	r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30         # Shift in the '1' into div
++        BREAI     $LaDIV2          # Div2
++$LaLOOP_END:
++        BEAGEI    r28,$LaRETURN_HERE
++        BREAId    $LaRETURN_HERE
++#else
+ 	BEQi	r29,$LaLOOP_END
+ 	ADD	r30,r30,r30         # Shift in the '1' into div
+ 	BRI	$LaDIV2          # Div2
+ $LaLOOP_END:
+ 	BGEI	r28,$LaRETURN_HERE
+ 	BRId	$LaRETURN_HERE
++#endif
+ 	rsubi	r3,r3,0 # Negate the result
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+@@ -108,7 +140,7 @@ $LaRETURN_HERE:
+ 	lli	r29,r1,8
+ 	lli	r30,r1,16
+ 	lli	r31,r1,24
+-	addik	r1,r1,32
++	addlik	r1,r1,32
+ 	rtsd	r15,8
+ 	nop
+ #else
+diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
+index 2044399db4a..95709d5bb01 100644
+--- a/libgcc/config/microblaze/mulsi3.S
++++ b/libgcc/config/microblaze/mulsi3.S
+@@ -43,7 +43,37 @@
+ 	.type	__mulsi3,@function
+ #ifdef __arch64__
+         .align 3
+-#endif
++__mulsi3:
++        .frame  r1,0,r15
++        add     r3,r0,r0
++        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
++        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
++        BEAGEId   r5,$L_R5_Pos
++        XOR     r4,r5,r6                  # Get the sign of the result
++        RSUBI   r5,r5,0                   # Make r5 positive
++$L_R5_Pos:
++        BEAGEI    r6,$L_R6_Pos
++        RSUBI   r6,r6,0                   # Make r6 positive
++$L_R6_Pos:
++        breai     $L1
++$L2:
++        add     r5,r5,r5
++$L1:
++        srl     r6,r6
++        addc    r7,r0,r0
++        beaeqi    r7,$L2
++        beaneid   r6,$L2
++        add     r3,r3,r5
++        bealti    r4,$L_NegateResult
++        rtsd    r15,8
++        nop
++$L_NegateResult:
++        rtsd    r15,8
++        rsub    r3,r3,r0
++$L_Result_Is_Zero:
++        rtsd    r15,8
++        addi    r3,r0,0
++#else
+ __mulsi3:
+ 	.frame	r1,0,r15
+ 	add	r3,r0,r0
+@@ -74,5 +104,6 @@ $L_NegateResult:
+ $L_Result_Is_Zero:
+ 	rtsd	r15,8
+ 	addi	r3,r0,0
++#endif
+ 	.end __mulsi3
+ 	.size	__mulsi3, . - __mulsi3
+diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
+index d2332bcfe62..687d5588801 100644
+--- a/libgcc/config/microblaze/udivsi3.S
++++ b/libgcc/config/microblaze/udivsi3.S
+@@ -59,52 +59,96 @@ __udivsi3:
+ 	SWI     r30,r1,4
+ 	SWI     r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
++        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
++#else
+ 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
+ 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
++#endif
+ 	ADDIK   r30,r0,0                    # Clear mod
+ 	ADDIK   r29,r0,32                   # Initialize the loop count
+ 
+         # Check if r6 and r5 are equal # if yes, return 1
+ 	RSUB 	r18,r5,r6
++#ifdef __arch64__
++        BEAEQID   r18,$LaRETURN_HERE
++#else
+ 	BEQID	r18,$LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
+ 	XOR	r18,r5,r6
+-	BGEID	r18,16
++#ifdef __arch64__
++	BEAGEID	r18,16
++#else
++        BGEID   r18,16
++#endif
+ 	ADD	r3,r0,r0                    # We would anyways clear r3
++#ifdef __arch64__
++        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
++        BREAI     $LCheckr6
++        RSUB    r18,r6,r5                   # MICROBLAZEcmp
++        BEALTI    r18,$LaRETURN_HERE
++#else
+ 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
+ 	BRI	$LCheckr6
+ 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
+ 	BLTI	r18,$LaRETURN_HERE
+-
++#endif
+         # If r6 [bit 31] is set, then return result as 1
+ $LCheckr6:
+-	BGTI	r6,$LaDIV0
+-	BRID	$LaRETURN_HERE
++#ifdef __arch64__
++	BEAGTI	r6,$LaDIV0
++	BREAID	$LaRETURN_HERE
++#else
++        BGTI    r6,$LaDIV0
++        BRID    $LaRETURN_HERE
++#endif
+ 	ADDIK	r3,r0,1
+ 
+         # First part try to find the first '1' in the r5
+ $LaDIV0:
++#ifdef __arch64__
++        BEALTI    r5,$LaDIV2
++#else
+ 	BLTI    r5,$LaDIV2	
++#endif
+ $LaDIV1:
+ 	ADD     r5,r5,r5                    # left shift logical r5
++#ifdef __arch64__
++        BEAGTID   r5,$LaDIV1
++#else
+ 	BGTID   r5,$LaDIV1       
++#endif
+ 	ADDIK   r29,r29,-1
+ $LaDIV2:
+ 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
+ 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
+ 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
++#ifdef __arch64__
++        BEALTI    r31,$LaMOD_TOO_SMALL
++#else
+     	BLTI    r31,$LaMOD_TOO_SMALL
++#endif
+ 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
+ 	ADDIK   r3,r3,1
+ $LaMOD_TOO_SMALL:
+ 	ADDIK   r29,r29,-1
++#ifdef __arch64__
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r3,r3,r3 # Shift in the '1' into div
++        BREAI     $LaDIV2   # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++#else
+ 	BEQi    r29,$LaLOOP_END
+ 	ADD     r3,r3,r3 # Shift in the '1' into div
+ 	BRI     $LaDIV2   # Div2
+ $LaLOOP_END:
+ 	BRI     $LaRETURN_HERE
++#endif
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	OR      r3,r0,r0 # set result to 0
+@@ -115,7 +159,7 @@ $LaRETURN_HERE:
+ 	LLI     r29,r1,0
+ 	LLI     r30,r1,8
+ 	LLI     r31,r1,16
+-	ADDIK   r1,r1,24
++	ADDLIK   r1,r1,24
+ 	RTSD    r15,8
+ 	NOP
+ #else
+diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
+index 2dd72aef68e..59646ce437f 100644
+--- a/libgcc/config/microblaze/umodsi3.S
++++ b/libgcc/config/microblaze/umodsi3.S
+@@ -46,7 +46,7 @@
+ __umodsi3:
+ 	.frame	r1,0,r15	
+ 
+-	addik	r1,r1,-24
++	addlik	r1,r1,-24
+ 	sli	r29,r1,0
+ 	sli	r30,r1,8
+ 	sli	r31,r1,16
+@@ -59,27 +59,77 @@ __umodsi3:
+ 	swi	r30,r1,4
+ 	swi	r31,r1,8
+ #endif
++#ifdef __arch64__
++        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
++        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
++#else
+ 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
+ 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
++#endif
+ 	ADDIK 	r3,r0,0                  # Clear div
+ 	ADDIK 	r30,r0,0     	# clear mod
+ 	ADDIK 	r29,r0,32       # Initialize the loop count
+ 
+ # Check if r6 and r5 are equal # if yes, return 0
+ 	rsub 	r18,r5,r6
+-	beqi	r18,$LaRETURN_HERE
+ 
++#ifdef __arch64__
++	beaeqi    r18,$LaRETURN_HERE
++#else
++	beqi	r18,$LaRETURN_HERE
++#endif
+ # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
+ 	xor	r18,r5,r6
++#ifdef __arch64__
++        beageid   r18,16
++        addik   r3,r5,0
++        bealti    r6,$LaRETURN_HERE
++        breai     $LCheckr6
++        rsub    r18,r5,r6 # MICROBLAZEcmp
++        beagti    r18,$LaRETURN_HERE
++#else
+ 	bgeid	r18,16
+ 	addik	r3,r5,0
+ 	blti	r6,$LaRETURN_HERE
+ 	bri	$LCheckr6
+ 	rsub	r18,r5,r6 # MICROBLAZEcmp
+ 	bgti	r18,$LaRETURN_HERE
+-
++#endif
+ # If r6 [bit 31] is set, then return result as r5-r6
+ $LCheckr6:
++#ifdef __arch64__
++        beagtid   r6,$LaDIV0
++        addik   r3,r0,0
++        addik   r18,r0,0x7fffffff
++        and     r5,r5,r18
++        and     r6,r6,r18
++        breaid    $LaRETURN_HERE
++        rsub    r3,r6,r5
++# First part: try to find the first '1' in the r5
++$LaDIV0:
++        BEALTI    r5,$LaDIV2
++$LaDIV1:
++        ADD     r5,r5,r5     # left shift logical r5
++        BEAGEID   r5,$LaDIV1   #
++        ADDIK   r29,r29,-1
++$LaDIV2:
++        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
++        ADDC    r3,r3,r3     # Move that bit into the Mod register
++        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
++        BEALTi    r31,$LaMOD_TOO_SMALL
++        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
++        ADDIK   r30,r30,1
++$LaMOD_TOO_SMALL:
++        ADDIK   r29,r29,-1
++        BEAEQi    r29,$LaLOOP_END
++        ADD     r30,r30,r30 # Shift in the '1' into div
++        BREAI     $LaDIV2     # Div2
++$LaLOOP_END:
++        BREAI     $LaRETURN_HERE
++$LaDiv_By_Zero:
++$LaResult_Is_Zero:
++        or      r3,r0,r0   # set result to 0
++#else
+ 	bgtid	r6,$LaDIV0
+ 	addik	r3,r0,0
+ 	addik	r18,r0,0x7fffffff
+@@ -111,7 +161,7 @@ $LaLOOP_END:
+ $LaDiv_By_Zero:
+ $LaResult_Is_Zero:
+ 	or 	r3,r0,r0   # set result to 0
+-
++#endif
+ #ifdef __arch64__
+ $LaRETURN_HERE:
+ # Restore values of CSRs and that of r3 and the divisor and the dividend
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch
new file mode 100644
index 0000000000..94be6aff0e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Author-Nagaraju-nmekala-xilinx.com.patch
@@ -0,0 +1,479 @@
+From f6b896effc198b8d9d1e6f33889f029da5e5d96c Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 18 Apr 2019 16:00:37 +0530
+Subject: [PATCH 48/54] Author: Nagaraju <nmekala@xilinx.com> Date:   Wed Apr
+ 17 14:11:00 2019 +0530
+
+    [Patch, microblaze]: MB-64 removal of barrel-shift instructions from default
+    By default MB-64 is generatting barrel-shift instructions. It has been
+    removed from default. Barrel-shift instructions will be generated only if
+    barrel-shifter is enabled. Similarly to double instructions as well.
+
+    Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+---
+ gcc/config/microblaze/microblaze.c  |   2 +-
+ gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++--
+ 2 files changed, 252 insertions(+), 19 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index e32de46fa62..7b48c011550 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3870,7 +3870,7 @@ microblaze_expand_divide (rtx operands[])
+   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
+ 
+   if (TARGET_MB_64) {
+-      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
++      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
+       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
+     }
+   else  {
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 9b88666c0a6..60afd9be288 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -547,7 +547,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (plus:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dadd\t%0,%1,%2"
+   [(set_attr "type"     "fadd")
+   (set_attr "mode"      "DF")
+@@ -557,7 +557,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (minus:DF (match_operand:DF 1 "register_operand" "d")
+                   (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "drsub\t%0,%2,%1"
+   [(set_attr "type"     "frsub")
+   (set_attr "mode"      "DF")
+@@ -567,7 +567,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (mult:DF (match_operand:DF 1 "register_operand" "d")
+                  (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dmul\t%0,%1,%2"
+   [(set_attr "type"     "fmul")
+   (set_attr "mode"      "DF")
+@@ -577,7 +577,7 @@
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (div:DF (match_operand:DF 1 "register_operand" "d")
+                 (match_operand:DF 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "ddiv\t%0,%2,%1"
+   [(set_attr "type"     "fdiv")
+   (set_attr "mode"      "DF")
+@@ -587,7 +587,7 @@
+ (define_insn "sqrtdf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dsqrt\t%0,%1"
+   [(set_attr "type"     "fsqrt")
+   (set_attr "mode"      "DF")
+@@ -596,7 +596,7 @@
+ (define_insn "floatdidf2"
+   [(set (match_operand:DF 0 "register_operand" "=d")
+         (float:DF (match_operand:DI 1 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dbl\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DF")
+@@ -605,7 +605,7 @@
+ (define_insn "fix_truncdfdi2"
+   [(set (match_operand:DI 0 "register_operand" "=d")
+         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
+   "dlong\t%0,%1"
+   [(set_attr "type"     "fcvt")
+   (set_attr "mode"      "DI")
+@@ -1301,6 +1301,34 @@
+   (set_attr "mode"	"DI")
+   (set_attr "length"	"4")])
+ 
++(define_insn "*movdi_internal2_bshift"
++  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
++	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++        return "addlk\t%0,%1,r0";
++     case 1:
++     case 2:
++        if (GET_CODE (operands[1]) == CONST_INT &&
++	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
++	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++        else
++	  return "addlik\t%0,r0,%1";
++     case 3:
++     case 4:
++       return "ll%i1\t%0,%1";
++     case 5:
++     case 6:
++       return "sl%i0\t%z1,%0";
++     }
++   }
++  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
++  (set_attr "mode"	"DI")
++  (set_attr "length"	"4,4,12,4,8,4,8")])
++
+ (define_insn "*movdi_internal2"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
+ 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
+@@ -1314,7 +1342,15 @@
+      case 2:
+         if (GET_CODE (operands[1]) == CONST_INT && 
+ 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
+- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
++          {
++            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++            output_asm_insn ("addlik\t%0,r0,%h1", operands);
++            output_asm_insn ("addlik\t%2,r0,32", operands);
++            output_asm_insn ("addlik\t%2,%2,-1", operands);
++            output_asm_insn ("beaneid\t%2,.-8", operands);
++            output_asm_insn ("addlk\t%0,%0,%0", operands);
++            return "addlik\t%0,%0,%j1 #li => la";
++          }
+         else	
+ 	  return "addlik\t%0,r0,%1";
+      case 3:
+@@ -1389,7 +1425,7 @@
+ (define_insn "movdi_long_int"
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
+ 	(match_operand:DI 1 "general_operand"      "i"))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
+   [(set_attr "type"	"no_delay_arith")
+   (set_attr "mode"	"DI")
+@@ -1656,6 +1692,33 @@
+ ;; movdf_internal
+ ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
+ ;;
++(define_insn "*movdf_internal_64_bshift"
++  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
++        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
++  {
++    switch (which_alternative)
++    {
++      case 0:
++	return "addlk\t%0,%1,r0";
++      case 1:
++	return "addlk\t%0,r0,r0";
++      case 2:
++      case 4:
++          return "ll%i1\t%0,%1";
++      case 3:
++      {
++	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++      }
++      case 5:
++	return "sl%i0\t%1,%0";
++    }
++    gcc_unreachable ();
++  }
++  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
++  (set_attr "mode"      "DF")
++  (set_attr "length"    "4,4,4,16,4,4")])
++
+ (define_insn "*movdf_internal_64"
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
+         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
+@@ -1672,7 +1735,13 @@
+           return "ll%i1\t%0,%1";
+       case 3:
+       {
+-	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
++	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++	output_asm_insn ("addlik\t%0,r0,%h1", operands);
++	output_asm_insn ("addlik\t%2,r0,32", operands);
++	output_asm_insn ("addlik\t%2,%2,-1", operands);
++	output_asm_insn ("beaneid\t%2,.-8", operands);
++	output_asm_insn ("addlk\t%0,%0,%0", operands);
++	return "addlik\t%0,%0,%j1 #li => la";
+       }
+       case 5:
+ 	return "sl%i0\t%1,%0";
+@@ -1792,11 +1861,21 @@
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1806,7 +1885,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+   bsllli\t%0,%1,%2
+   bslll\t%0,%1,%2"
+@@ -1814,6 +1893,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+ )
++
++(define_insn "ashldi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++   (set_attr "mode"    "DI")
++   (set_attr "length"  "20")]
++)
++
++(define_insn "ashldi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "addlk\t%0,%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ ;; The following patterns apply when there is no barrel shifter present
+ 
+ (define_insn "*ashlsi3_with_mul_delay"
+@@ -1947,11 +2071,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -1961,7 +2095,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrai\t%0,%1,%2
+    bslra\t%0,%1,%2"
+@@ -1969,6 +2103,51 @@ else
+   (set_attr "mode"	"DI,DI")
+   (set_attr "length"	"4,4")]
+   )
++
++(define_insn "ashrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "arith")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "ashrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1])) 
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srla\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "DI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "ashrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2086,11 +2265,21 @@ else
+ "TARGET_MB_64"
+ {
+ ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
+-if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
++if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
+   {
+     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
+     DONE;
+   }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
++  {
++    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
++    DONE;
++  }
++else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
++  {
++    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
++    DONE;
++  }
+ else
+   FAIL;
+ }    
+@@ -2100,7 +2289,7 @@ else
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
+                    (match_operand:DI 2 "arith_operand"    "I,d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
+   "@
+    bslrli\t%0,%1,%2
+    bslrl\t%0,%1,%2"
+@@ -2109,6 +2298,50 @@ else
+   (set_attr "length"	"4,4")]
+   )
+ 
++(define_insn "lshrdi3_const"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++
++    output_asm_insn ("orli\t%3,r0,%2", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++        output_asm_insn ("addlk\t%0,%1,r0", operands);
++
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"    "DI")
++  (set_attr "length"  "20")]
++)
++
++(define_insn "lshrdi3_reg"
++  [(set (match_operand:DI 0 "register_operand" "=&d")
++       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
++                   (match_operand:DI 2 "register_operand" "d")))]
++  "TARGET_MB_64"
++  {
++    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
++    output_asm_insn ("andli\t%3,%2,31", operands);
++    if (REGNO (operands[0]) != REGNO (operands[1]))
++      output_asm_insn ("addlk\t%0,r0,%1", operands);
++    /* Exit the loop if zero shift. */
++    output_asm_insn ("beaeqid\t%3,.+24", operands);
++    /* Emit the loop.  */
++    output_asm_insn ("addlk\t%0,%0,r0", operands);
++    output_asm_insn ("addlik\t%3,%3,-1", operands);
++    output_asm_insn ("beaneid\t%3,.-8", operands);
++    return "srll\t%0,%0";
++  }
++  [(set_attr "type"    "multi")
++  (set_attr "mode"     "SI")
++  (set_attr "length"   "28")]
++)
++
+ (define_expand "lshrsi3"
+   [(set (match_operand:SI 0 "register_operand" "=&d")
+ 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
+@@ -2236,7 +2469,7 @@ else
+ 	(eq:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmpleq\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+    (set_attr "mode"	"DI")
+@@ -2248,7 +2481,7 @@ else
+ 	(ne:DI 
+ 	       (match_operand:DI 1 "register_operand" "d")
+ 	       (match_operand:DI 2 "register_operand" "d")))]
+-  "TARGET_MB_64"
++  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
+   "pcmplne\t%0,%1,%2"
+   [(set_attr "type"	"arith")
+   (set_attr "mode"	"DI")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
deleted file mode 100644
index 92fa9e5718..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From d12f2da2ae7fa7946aef94c161730c7b851c086a Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 24 Oct 2018 18:31:04 +0530
-Subject: [PATCH 48/58] [Patch,Microblaze] : corrected SPN for dlong
- instruction mapping.
-
----
- gcc/config/microblaze/microblaze.md | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6a1e45a5b66..53dbe4e4060 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -602,9 +602,9 @@
-   (set_attr "mode"      "DF")
-   (set_attr "length"    "4")])
- 
--(define_insn "floatdfdi2"
-+(define_insn "fix_truncdfdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
--        (float:DI (match_operand:DF 1 "register_operand" "d")))]
-+        (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
-   "TARGET_MB_64"
-   "dlong\t%0,%1"
-   [(set_attr "type"     "fcvt")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
new file mode 100644
index 0000000000..81ecbf8efb
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-Added-new-MB-64-single-register-arithmetic-instructi.patch
@@ -0,0 +1,107 @@
+From adb1b8d8cc2a8fb99f474d9166db9f68b8f3f8b4 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:16:53 +0530
+Subject: [PATCH 49/54] Added new MB-64 single register arithmetic instructions
+
+---
+ gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 60afd9be288..1ad139cbd44 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -654,6 +654,18 @@
+    }
+ })
+ 
++(define_insn "adddi3_int"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++  (plus:DI (match_operand:DI 1 "register_operand" "%0")
++                 (match_operand:DI 2 "immediate_operand" "I")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++  addlik\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")]
++)
++
+ (define_insn "*adddi3_long"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
+@@ -719,6 +731,18 @@
+ {
+ }")
+ 
++(define_insn "subdi316imm"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (minus:DI (match_operand:DI 1 "register_operand" "d")
++                  (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
++  "@
++   addlik\t%0,-%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
++
+ (define_insn "subsidi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
+@@ -1015,6 +1039,17 @@
+ ;; Logical
+ ;;----------------------------------------------------------------
+ 
++(define_insn "anddi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (and:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   andli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "anddi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
+ 	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
+@@ -1042,6 +1077,16 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "iordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (ior:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   orli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
+ 
+ (define_insn "iordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+@@ -1069,6 +1114,17 @@
+   (set_attr "mode"	"SI,SI,SI,SI")
+   (set_attr "length"	"4,8,8,8")])
+ 
++(define_insn "xordi3imm16"
++  [(set (match_operand:DI 0 "register_operand" "=d")
++        (xor:DI (match_operand:DI 1 "arith_operand" "%0")
++                (match_operand:DI 2 "arith_operand" "K")))]
++  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
++  "@
++   xorli\t%0,%2"
++  [(set_attr "type"     "darith")
++  (set_attr "mode"      "DI")
++  (set_attr "length"    "4")])
++
+ (define_insn "xordi3"
+   [(set (match_operand:DI 0 "register_operand" "=d,d")
+ 	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch
deleted file mode 100644
index 346157cef0..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0049-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From dfe4f5aa180a7b4c15b4b586b253541aa9d29e52 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 29 Nov 2018 17:55:08 +0530
-Subject: [PATCH 49/58] fixing the long & long long mingw toolchain issue
-
----
- gcc/config/microblaze/constraints.md | 2 +-
- gcc/config/microblaze/microblaze.md  | 8 ++++----
- 2 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index c2b0a21c53b..4a6cf419671 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -55,7 +55,7 @@
- (define_constraint "K"
-   "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-   (and (match_code "const_int")
--       (match_test "ival > (long)-549755813888 && ival < (long)549755813887")))
-+       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
- 
- ;; Define floating point constraints
- 
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 53dbe4e4060..5d277014e42 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -648,8 +648,8 @@
-   if (TARGET_MB_64) 
-    {
-      if (GET_CODE (operands[2]) == CONST_INT &&
--       INTVAL(operands[2]) < (long)-549755813888 &&
--	INTVAL(operands[2]) > (long)549755813887)
-+       INTVAL(operands[2]) < (long long)-549755813888 &&
-+	INTVAL(operands[2]) > (long long)549755813887)
-       FAIL;
-    }
- })
-@@ -1266,7 +1266,7 @@
- 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
-   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
-            (GET_CODE (operands[1]) == CONST_INT && 
--                 (INTVAL (operands[1]) <= (long)549755813887 && INTVAL (operands[1]) >= (long)-549755813888)))"  
-+                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
-   "@
-    addlk\t%0,r0,r0\t
-    addlik\t%0,r0,%1\t #N1 %X1
-@@ -1300,7 +1300,7 @@
-      case 1:
-      case 2:
-         if (GET_CODE (operands[1]) == CONST_INT && 
--	    (INTVAL (operands[1]) > (long)549755813887 || INTVAL (operands[1]) < (long)-549755813888))
-+	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-  	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-         else	
- 	  return "addlik\t%0,r0,%1";
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch
deleted file mode 100644
index 360bdb5154..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From b21e115bc1af625b2ae1acb893027af6af3c2d16 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 14 Mar 2019 18:11:04 +0530
-Subject: [PATCH 50/58] Fix the MB-64 bug of handling QI objects
-
----
- gcc/config/microblaze/microblaze.md | 14 +++++++-------
- 1 file changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 5d277014e42..a1363935c42 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -2347,11 +2347,11 @@ else
- 
- (define_insn "branch_zero_64"
-   [(set (pc)
--	(if_then_else (match_operator:SI 0 "ordered_comparison_operator"
-+	(if_then_else (match_operator 0 "ordered_comparison_operator"
-   				 [(match_operand:SI 1 "register_operand" "d")
-                                   (const_int 0)])
--                      (match_operand:SI 2 "pc_or_label_operand" "")
--                      (match_operand:SI 3 "pc_or_label_operand" "")))
-+                      (match_operand 2 "pc_or_label_operand" "")
-+                      (match_operand 3 "pc_or_label_operand" "")))
-   ]
-   "TARGET_MB_64"
-   {
-@@ -2367,11 +2367,11 @@ else
- 
- (define_insn "long_branch_zero"
-   [(set (pc)
--	(if_then_else (match_operator 0 "ordered_comparison_operator"
--  				 [(match_operand 1 "register_operand" "d")
-+	(if_then_else (match_operator:DI 0 "ordered_comparison_operator"
-+				 [(match_operand:DI 1 "register_operand" "d")
-                                   (const_int 0)])
--                      (match_operand 2 "pc_or_label_operand" "")
--                      (match_operand 3 "pc_or_label_operand" "")))
-+                      (match_operand:DI 2 "pc_or_label_operand" "")
-+                      (match_operand:DI 3 "pc_or_label_operand" "")))
-   ]
-   "TARGET_MB_64"
-   {
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
new file mode 100644
index 0000000000..d452b988e9
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
@@ -0,0 +1,44 @@
+From 797697692635d4c536181cb007b3b0d63d2431c1 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:55:22 +0530
+Subject: [PATCH 50/54] [Patch,MicroBlaze] : Added support for 64 bit Immediate
+ values.
+
+---
+ gcc/config/microblaze/constraints.md | 4 ++--
+ gcc/config/microblaze/microblaze.md  | 3 +--
+ 2 files changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
+index 89db511c453..9ad2b099310 100644
+--- a/gcc/config/microblaze/constraints.md
++++ b/gcc/config/microblaze/constraints.md
+@@ -53,9 +53,9 @@
+        (match_test "ival > 0 && ival < 0x10000")))
+ 
+ (define_constraint "K"
+-  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
++  "A constant in the range  -9223372036854775808 to 9223372036854775807 (inclusive)."
+   (and (match_code "const_int")
+-       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
++       (match_test "ival > (long long)-9223372036854775808  && ival < (long long)9223372036854775807")))
+ 
+ 
+ ;; Define floating point constraints
+diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
+index 1ad139cbd44..93de8d831fd 100644
+--- a/gcc/config/microblaze/microblaze.md
++++ b/gcc/config/microblaze/microblaze.md
+@@ -1334,8 +1334,7 @@
+   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
+ 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
+   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
+-           (GET_CODE (operands[1]) == CONST_INT && 
+-                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
++           (GET_CODE (operands[1]) == CONST_INT))"
+   "@
+    addlk\t%0,r0,r0\t
+    addlik\t%0,r0,%1\t #N1 %X1
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch
deleted file mode 100644
index 6b7bb2a10f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From ed17f79b22769e5a256e3990715e32e943bfd929 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Fri, 29 Mar 2019 12:08:39 +0530
-Subject: [PATCH 51/58] [Patch,Microblaze] : Check the possibiity of peephole2
- opt
-
-We will check the possibility of peephole2
-optimization,if we can then we will fix the compiler issue.
----
- gcc/config/microblaze/microblaze.md | 63 +++++++++++++++++------------
- 1 file changed, 38 insertions(+), 25 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index a1363935c42..626eade9468 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -882,31 +882,44 @@
-   (set_attr "mode"	"SI")
-   (set_attr "length"	"4")])
- 
--(define_peephole2
--  [(set (match_operand:SI 0 "register_operand")
--        (fix:SI (match_operand:SF 1 "register_operand")))
--   (set (pc)
--        (if_then_else (match_operator 2 "ordered_comparison_operator"
--                       [(match_operand:SI 3 "register_operand")
--                        (match_operand:SI 4 "arith_operand")])
--                      (label_ref (match_operand 5))
--                      (pc)))]
--   "TARGET_HARD_FLOAT && !TARGET_MB_64"
--   [(set (match_dup 1) (match_dup 3))]
--
--  {
--    rtx condition;
--    rtx cmp_op0 = operands[3];
--    rtx cmp_op1 = operands[4];
--    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
--
--    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
--                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
--                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
--    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
--    emit_jump_insn (gen_condjump (condition, operands[5]));
--  }
--)
-+;; peephole2 optimization will be done only if fint and if-then-else
-+;; are dependent.added condition for the same.
-+;; if they are dependent then gcc is giving "flow control insn inside a basic block" 
-+;; testcase:
-+;;        volatile float vec = 1.0;
-+;;        volatile int ci = 2;
-+;;        register int cj = (int)(vec);
-+;;//        ci=cj;
-+;;//      if (ci <0) {
-+;;        if (cj < 0) {
-+;;                ci = 0;
-+;;        }
-+;; commenting for now.we will check the possibility of this optimization later
-+
-+;;(define_peephole2
-+;;  [(set (match_operand:SI 0 "register_operand")
-+;;        (fix:SI (match_operand:SF 1 "register_operand")))
-+;;   (set (pc)
-+;;        (if_then_else (match_operator 2 "ordered_comparison_operator"
-+;;                       [(match_operand:SI 3 "register_operand")
-+;;                        (match_operand:SI 4 "arith_operand")])
-+;;                      (label_ref (match_operand 5))
-+;;                      (pc)))]
-+;;   "TARGET_HARD_FLOAT && !TARGET_MB_64 && ((REGNO (operands[0])) == (REGNO (operands[3])))"
-+;;  [(set (match_dup 1) (match_dup 3))]
-+;;  {
-+;;    rtx condition;
-+;;    rtx cmp_op0 = operands[3];
-+;;    rtx cmp_op1 = operands[4];
-+;;    rtx comp_reg =  gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM);
-+;;
-+;;    emit_insn (gen_cstoresf4 (comp_reg, operands[2],
-+;;                              gen_rtx_REG (SFmode, REGNO (cmp_op0)),
-+;;                              gen_rtx_REG (SFmode, REGNO (cmp_op1))));
-+;;    condition = gen_rtx_NE (SImode, comp_reg, const0_rtx);
-+;;    emit_jump_insn (gen_condjump (condition, operands[5]));
-+;;  }
-+;;)
- 
- ;;----------------------------------------------------------------
- ;; Negation and one's complement
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
new file mode 100644
index 0000000000..3e0c483b77
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
@@ -0,0 +1,86 @@
+From 697db2e2c2519f27011fbd1960cd8860133aaa84 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 9 Jan 2020 12:30:41 +0530
+Subject: [PATCH 51/54] [Patch, microblaze]: Fix Compiler crash with
+ -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
+ struct values in registers. Currently we are only handling SImode With this
+ patch all other modes are handled properly
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+2020-01-09 Nagaraju Mekala <nmekala@xilix.com>
+
+	* gcc/config/microblaze/microblaze.h
+	(LIBCALL_Value): Remove macro
+	(PROMOTE_MODE): Remove macro
+	* gcc/config/microblaze/microblaze.c
+	(TARGET_LIBCALL_Value): Added new macro
+	(microblaze_function_value): Updated the return Value
+---
+ gcc/config/microblaze/microblaze.c | 11 ++++++++++-
+ gcc/config/microblaze/microblaze.h | 19 -------------------
+ 2 files changed, 10 insertions(+), 20 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 7b48c011550..1bba77dab6d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -3908,7 +3908,16 @@ microblaze_function_value (const_tree valtype,
+ 			   const_tree func ATTRIBUTE_UNUSED,
+ 			   bool outgoing ATTRIBUTE_UNUSED)
+ {
+-  return LIBCALL_VALUE (TYPE_MODE (valtype));
++  return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN);
++}
++
++#undef  TARGET_LIBCALL_VALUE
++#define TARGET_LIBCALL_VALUE microblaze_libcall_value
++
++rtx
++microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
++{
++  return gen_rtx_REG (mode, GP_RETURN);
+ }
+ 
+ /* Implement TARGET_SCHED_ADJUST_COST.  */
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index bfa7bc9a01c..d467a7ee65d 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
+ 
+ #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
+ 
+-#ifndef __arch64__
+-#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
+-  if (GET_MODE_CLASS (MODE) == MODE_INT         \
+-      && GET_MODE_SIZE (MODE) < 4)              \
+-    (MODE) = SImode;
+-#endif
+-
+ /* Standard register usage.  */
+ 
+ /* On the MicroBlaze, we have 32 integer registers */
+@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info;
+ 
+ #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
+ 
+-#ifdef __aarch64__
+-#define LIBCALL_VALUE(MODE)						\
+-  gen_rtx_REG (MODE,GP_RETURN)
+-#else								
+-#define LIBCALL_VALUE(MODE)						\
+-  gen_rtx_REG (								\
+-	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
+-	     || GET_MODE_SIZE (MODE) >= 4)				\
+-	    ? (MODE)							\
+-	    : SImode), GP_RETURN)
+-#endif
+-
+ /* 1 if N is a possible register number for a function value.
+    On the MicroBlaze, R2 R3 are the only register thus used.
+    Currently, R2 are only implemented  here (C has no complex type)  */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
deleted file mode 100644
index 45505cf17a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch
+++ /dev/null
@@ -1,466 +0,0 @@
-From d845981b381b0174d97dda8a78d82cf8fcae7ca1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Wed, 17 Apr 2019 12:36:16 +0530
-Subject: [PATCH 52/58] [Patch,MicroBlaze]: fixed typos in mul,div and mod
- assembly files.
-
----
- libgcc/config/microblaze/divsi3.S  | 47 ++++++++++++++++++++----
- libgcc/config/microblaze/modsi3.S  | 40 ++++++++++++++++++---
- libgcc/config/microblaze/mulsi3.S  | 33 ++++++++++++++++-
- libgcc/config/microblaze/udivsi3.S | 54 +++++++++++++++++++++++++---
- libgcc/config/microblaze/umodsi3.S | 58 +++++++++++++++++++++++++++---
- 5 files changed, 212 insertions(+), 20 deletions(-)
-
-diff --git a/libgcc/config/microblaze/divsi3.S b/libgcc/config/microblaze/divsi3.S
-index 104243e35fe..5755e29fbb6 100644
---- a/libgcc/config/microblaze/divsi3.S
-+++ b/libgcc/config/microblaze/divsi3.S
-@@ -46,7 +46,7 @@
- __divsi3:
- 	.frame	r1,0,r15	
- 
--	ADDIK   r1,r1,-32
-+	ADDLIK   r1,r1,-32
- 	SLI     r28,r1,0
- 	SLI     r29,r1,8
- 	SLI     r30,r1,16
-@@ -61,13 +61,23 @@ __divsi3:
- 	SWI     r30,r1,8
- 	SWI     r31,r1,12
- #endif
--	BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
--	BEQI    r5,$LaResult_Is_Zero    # Result is Zero 
--	BGEID   r5,$LaR5_Pos 
-+#ifdef __arch64__
-+	BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+	BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+	BEAGEID   r5,$LaR5_Pos
-+#else
-+        BEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+        BEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+        BGEID   r5,$LaR5_Pos
-+#endif
- 	XOR     r28,r5,r6               # Get the sign of the result
- 	RSUBI   r5,r5,0                 # Make r5 positive
- $LaR5_Pos:
--	BGEI    r6,$LaR6_Pos
-+#ifdef __arch64__
-+	BEAGEI    r6,$LaR6_Pos
-+#else
-+        BGEI    r6,$LaR6_Pos
-+#endif
- 	RSUBI   r6,r6,0                 # Make r6 positive
- $LaR6_Pos:
- 	ADDIK   r30,r0,0                # Clear mod
-@@ -76,26 +86,51 @@ $LaR6_Pos:
- 
-         # First part try to find the first '1' in the r5
- $LaDIV0: 
--        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000 
-+#ifdef __arch64__
-+        BEALTI    r5,$LaDIV2              # This traps r5 == 0x80000000
-+#else
-+        BLTI    r5,$LaDIV2              # This traps r5 == 0x80000000
-+#endif
- $LaDIV1:
- 	ADD     r5,r5,r5                # left shift logical r5
-+#ifdef __arch64__
-+        BEAGTID   r5,$LaDIV1
-+#else
- 	BGTID   r5,$LaDIV1       
-+#endif
- 	ADDIK   r29,r29,-1
- $LaDIV2:
- 	ADD     r5,r5,r5                # left shift logical  r5 get the '1' into the Carry
- 	ADDC    r30,r30,r30             # Move that bit into the Mod register
- 	RSUB    r31,r6,r30              # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTI    r31,$LaMOD_TOO_SMALL
-+#else
- 	BLTI    r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR      r30,r0,r31              # Move the r31 to mod since the result was positive
- 	ADDIK   r3,r3,1
- $LaMOD_TOO_SMALL:
- 	ADDIK   r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+#else
- 	BEQi    r29,$LaLOOP_END
-+#endif
- 	ADD     r3,r3,r3                # Shift in the '1' into div
-+#ifdef __arch64__
-+        BREAI     $LaDIV2                 # Div2
-+#else
- 	BRI     $LaDIV2                 # Div2
-+#endif
- $LaLOOP_END:
-+#ifdef __arch64__
-+        BEAGEI    r28,$LaRETURN_HERE
-+        BREAID    $LaRETURN_HERE
-+#else
- 	BGEI    r28,$LaRETURN_HERE
- 	BRID    $LaRETURN_HERE
-+#endif
- 	RSUBI   r3,r3,0                 # Negate the result
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
-diff --git a/libgcc/config/microblaze/modsi3.S b/libgcc/config/microblaze/modsi3.S
-index 4dbb25900d9..b6129f5e822 100644
---- a/libgcc/config/microblaze/modsi3.S
-+++ b/libgcc/config/microblaze/modsi3.S
-@@ -62,40 +62,72 @@ __modsi3:
- 	swi	r31,r1,12
- #endif
- 
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
-+        BEAEQI    r5,$LaResult_Is_Zero    # Result is Zero
-+        BEAGEId   r5,$LaR5_Pos
-+#else
- 	BEQI	r6,$LaDiv_By_Zero       # Div_by_Zero   # Division Error
- 	BEQI	r5,$LaResult_Is_Zero    # Result is Zero 
- 	BGEId	r5,$LaR5_Pos 
-+#endif
- 	ADD	r28,r5,r0               # Get the sign of the result [ Depends only on the first arg]
- 	RSUBI	r5,r5,0	                # Make r5 positive
- $LaR5_Pos:
--	BGEI	r6,$LaR6_Pos
-+#ifdef __arch64__
-+	BEAGEI	r6,$LaR6_Pos
-+#else
-+        BGEI    r6,$LaR6_Pos
-+#endif
- 	RSUBI	r6,r6,0	    # Make r6 positive
- $LaR6_Pos:
- 	ADDIK	r3,r0,0      # Clear mod
- 	ADDIK	r30,r0,0     # clear div
--	BLTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+#ifdef __arch64__
-+	BEALTId	r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
- 			     # the first bit search.
-+#else
-+        BLTId   r5,$LaDIV2   # If r5 is still negative (0x80000000), skip
-+                             # the first bit search.
-+#endif
- 	ADDIK	r29,r0,32    # Initialize the loop count
-    # First part try to find the first '1' in the r5
- $LaDIV1:
- 	ADD	r5,r5,r5         # left shift logical r5
--	BGEID	r5,$LaDIV1       #
-+#ifdef __arch64__
-+	BEAGEID	r5,$LaDIV1       #
-+#else
-+        BGEID   r5,$LaDIV1       #
-+#endif
- 	ADDIK	r29,r29,-1
- $LaDIV2:
- 	ADD	r5,r5,r5         # left shift logical  r5 get the '1' into the Carry
- 	ADDC	r3,r3,r3         # Move that bit into the Mod register
- 	rSUB	r31,r6,r3        # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTi    r31,$LaMOD_TOO_SMALL
-+#else
- 	BLTi	r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR	r3,r0,r31       # Move the r31 to mod since the result was positive
- 	ADDIK	r30,r30,1
- $LaMOD_TOO_SMALL:
- 	ADDIK	r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r30,r30,r30         # Shift in the '1' into div
-+        BREAI     $LaDIV2          # Div2
-+$LaLOOP_END:
-+        BEAGEI    r28,$LaRETURN_HERE
-+        BREAId    $LaRETURN_HERE
-+#else
- 	BEQi	r29,$LaLOOP_END
- 	ADD	r30,r30,r30         # Shift in the '1' into div
- 	BRI	$LaDIV2          # Div2
- $LaLOOP_END:
- 	BGEI	r28,$LaRETURN_HERE
- 	BRId	$LaRETURN_HERE
-+#endif
- 	rsubi	r3,r3,0 # Negate the result
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
-@@ -108,7 +140,7 @@ $LaRETURN_HERE:
- 	lli	r29,r1,8
- 	lli	r30,r1,16
- 	lli	r31,r1,24
--	addik	r1,r1,32
-+	addlik	r1,r1,32
- 	rtsd	r15,8
- 	nop
- #else
-diff --git a/libgcc/config/microblaze/mulsi3.S b/libgcc/config/microblaze/mulsi3.S
-index 2044399db4a..95709d5bb01 100644
---- a/libgcc/config/microblaze/mulsi3.S
-+++ b/libgcc/config/microblaze/mulsi3.S
-@@ -43,7 +43,37 @@
- 	.type	__mulsi3,@function
- #ifdef __arch64__
-         .align 3
--#endif
-+__mulsi3:
-+        .frame  r1,0,r15
-+        add     r3,r0,r0
-+        BEAEQI    r5,$L_Result_Is_Zero      # Multiply by Zero
-+        BEAEQI    r6,$L_Result_Is_Zero      # Multiply by Zero
-+        BEAGEId   r5,$L_R5_Pos
-+        XOR     r4,r5,r6                  # Get the sign of the result
-+        RSUBI   r5,r5,0                   # Make r5 positive
-+$L_R5_Pos:
-+        BEAGEI    r6,$L_R6_Pos
-+        RSUBI   r6,r6,0                   # Make r6 positive
-+$L_R6_Pos:
-+        breai     $L1
-+$L2:
-+        add     r5,r5,r5
-+$L1:
-+        srl     r6,r6
-+        addc    r7,r0,r0
-+        beaeqi    r7,$L2
-+        beaneid   r6,$L2
-+        add     r3,r3,r5
-+        bealti    r4,$L_NegateResult
-+        rtsd    r15,8
-+        nop
-+$L_NegateResult:
-+        rtsd    r15,8
-+        rsub    r3,r3,r0
-+$L_Result_Is_Zero:
-+        rtsd    r15,8
-+        addi    r3,r0,0
-+#else
- __mulsi3:
- 	.frame	r1,0,r15
- 	add	r3,r0,r0
-@@ -74,5 +104,6 @@ $L_NegateResult:
- $L_Result_Is_Zero:
- 	rtsd	r15,8
- 	addi	r3,r0,0
-+#endif
- 	.end __mulsi3
- 	.size	__mulsi3, . - __mulsi3
-diff --git a/libgcc/config/microblaze/udivsi3.S b/libgcc/config/microblaze/udivsi3.S
-index d2332bcfe62..687d5588801 100644
---- a/libgcc/config/microblaze/udivsi3.S
-+++ b/libgcc/config/microblaze/udivsi3.S
-@@ -59,52 +59,96 @@ __udivsi3:
- 	SWI     r30,r1,4
- 	SWI     r31,r1,8
- #endif
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
-+        BEAEQID   r5,$LaResult_Is_Zero        # Result is Zero
-+#else
- 	BEQI    r6,$LaDiv_By_Zero           # Div_by_Zero   # Division Error
- 	BEQID   r5,$LaResult_Is_Zero        # Result is Zero 
-+#endif
- 	ADDIK   r30,r0,0                    # Clear mod
- 	ADDIK   r29,r0,32                   # Initialize the loop count
- 
-         # Check if r6 and r5 are equal # if yes, return 1
- 	RSUB 	r18,r5,r6
-+#ifdef __arch64__
-+        BEAEQID   r18,$LaRETURN_HERE
-+#else
- 	BEQID	r18,$LaRETURN_HERE
-+#endif
- 	ADDIK	r3,r0,1
- 
-         # Check if (uns)r6 is greater than (uns)r5. In that case, just return 0
- 	XOR	r18,r5,r6
--	BGEID	r18,16
-+#ifdef __arch64__
-+	BEAGEID	r18,16
-+#else
-+        BGEID   r18,16
-+#endif
- 	ADD	r3,r0,r0                    # We would anyways clear r3
-+#ifdef __arch64__
-+        BEALTI    r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
-+        BREAI     $LCheckr6
-+        RSUB    r18,r6,r5                   # MICROBLAZEcmp
-+        BEALTI    r18,$LaRETURN_HERE
-+#else
- 	BLTI	r6,$LaRETURN_HERE           # r6[bit 31 = 1] hence is greater
- 	BRI	$LCheckr6
- 	RSUB	r18,r6,r5                   # MICROBLAZEcmp
- 	BLTI	r18,$LaRETURN_HERE
--
-+#endif
-         # If r6 [bit 31] is set, then return result as 1
- $LCheckr6:
--	BGTI	r6,$LaDIV0
--	BRID	$LaRETURN_HERE
-+#ifdef __arch64__
-+	BEAGTI	r6,$LaDIV0
-+	BREAID	$LaRETURN_HERE
-+#else
-+        BGTI    r6,$LaDIV0
-+        BRID    $LaRETURN_HERE
-+#endif
- 	ADDIK	r3,r0,1
- 
-         # First part try to find the first '1' in the r5
- $LaDIV0:
-+#ifdef __arch64__
-+        BEALTI    r5,$LaDIV2
-+#else
- 	BLTI    r5,$LaDIV2	
-+#endif
- $LaDIV1:
- 	ADD     r5,r5,r5                    # left shift logical r5
-+#ifdef __arch64__
-+        BEAGTID   r5,$LaDIV1
-+#else
- 	BGTID   r5,$LaDIV1       
-+#endif
- 	ADDIK   r29,r29,-1
- $LaDIV2:
- 	ADD     r5,r5,r5                    # left shift logical  r5 get the '1' into the Carry
- 	ADDC    r30,r30,r30                 # Move that bit into the Mod register
- 	RSUB    r31,r6,r30                  # Try to subtract (r30 a r6)
-+#ifdef __arch64__
-+        BEALTI    r31,$LaMOD_TOO_SMALL
-+#else
-     	BLTI    r31,$LaMOD_TOO_SMALL
-+#endif
- 	OR      r30,r0,r31                  # Move the r31 to mod since the result was positive
- 	ADDIK   r3,r3,1
- $LaMOD_TOO_SMALL:
- 	ADDIK   r29,r29,-1
-+#ifdef __arch64__
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r3,r3,r3 # Shift in the '1' into div
-+        BREAI     $LaDIV2   # Div2
-+$LaLOOP_END:
-+        BREAI     $LaRETURN_HERE
-+#else
- 	BEQi    r29,$LaLOOP_END
- 	ADD     r3,r3,r3 # Shift in the '1' into div
- 	BRI     $LaDIV2   # Div2
- $LaLOOP_END:
- 	BRI     $LaRETURN_HERE
-+#endif
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	OR      r3,r0,r0 # set result to 0
-@@ -115,7 +159,7 @@ $LaRETURN_HERE:
- 	LLI     r29,r1,0
- 	LLI     r30,r1,8
- 	LLI     r31,r1,16
--	ADDIK   r1,r1,24
-+	ADDLIK   r1,r1,24
- 	RTSD    r15,8
- 	NOP
- #else
-diff --git a/libgcc/config/microblaze/umodsi3.S b/libgcc/config/microblaze/umodsi3.S
-index 2dd72aef68e..59646ce437f 100644
---- a/libgcc/config/microblaze/umodsi3.S
-+++ b/libgcc/config/microblaze/umodsi3.S
-@@ -46,7 +46,7 @@
- __umodsi3:
- 	.frame	r1,0,r15	
- 
--	addik	r1,r1,-24
-+	addlik	r1,r1,-24
- 	sli	r29,r1,0
- 	sli	r30,r1,8
- 	sli	r31,r1,16
-@@ -59,27 +59,77 @@ __umodsi3:
- 	swi	r30,r1,4
- 	swi	r31,r1,8
- #endif
-+#ifdef __arch64__
-+        BEAEQI    r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
-+        BEAEQId   r5,$LaResult_Is_Zero     # Result is Zero
-+#else
- 	BEQI	r6,$LaDiv_By_Zero         # Div_by_Zero   # Division Error
- 	BEQId	r5,$LaResult_Is_Zero     # Result is Zero 
-+#endif
- 	ADDIK 	r3,r0,0                  # Clear div
- 	ADDIK 	r30,r0,0     	# clear mod
- 	ADDIK 	r29,r0,32       # Initialize the loop count
- 
- # Check if r6 and r5 are equal # if yes, return 0
- 	rsub 	r18,r5,r6
--	beqi	r18,$LaRETURN_HERE
- 
-+#ifdef __arch64__
-+	beaeqi    r18,$LaRETURN_HERE
-+#else
-+	beqi	r18,$LaRETURN_HERE
-+#endif
- # Check if (uns)r6 is greater than (uns)r5. In that case, just return r5
- 	xor	r18,r5,r6
-+#ifdef __arch64__
-+        beageid   r18,16
-+        addik   r3,r5,0
-+        bealti    r6,$LaRETURN_HERE
-+        breai     $LCheckr6
-+        rsub    r18,r5,r6 # MICROBLAZEcmp
-+        beagti    r18,$LaRETURN_HERE
-+#else
- 	bgeid	r18,16
- 	addik	r3,r5,0
- 	blti	r6,$LaRETURN_HERE
- 	bri	$LCheckr6
- 	rsub	r18,r5,r6 # MICROBLAZEcmp
- 	bgti	r18,$LaRETURN_HERE
--
-+#endif
- # If r6 [bit 31] is set, then return result as r5-r6
- $LCheckr6:
-+#ifdef __arch64__
-+        beagtid   r6,$LaDIV0
-+        addik   r3,r0,0
-+        addik   r18,r0,0x7fffffff
-+        and     r5,r5,r18
-+        and     r6,r6,r18
-+        breaid    $LaRETURN_HERE
-+        rsub    r3,r6,r5
-+# First part: try to find the first '1' in the r5
-+$LaDIV0:
-+        BEALTI    r5,$LaDIV2
-+$LaDIV1:
-+        ADD     r5,r5,r5     # left shift logical r5
-+        BEAGEID   r5,$LaDIV1   #
-+        ADDIK   r29,r29,-1
-+$LaDIV2:
-+        ADD     r5,r5,r5     # left shift logical  r5 get the '1' into the Carry
-+        ADDC    r3,r3,r3     # Move that bit into the Mod register
-+        rSUB    r31,r6,r3    # Try to subtract (r3 a r6)
-+        BEALTi    r31,$LaMOD_TOO_SMALL
-+        OR      r3,r0,r31    # Move the r31 to mod since the result was positive
-+        ADDIK   r30,r30,1
-+$LaMOD_TOO_SMALL:
-+        ADDIK   r29,r29,-1
-+        BEAEQi    r29,$LaLOOP_END
-+        ADD     r30,r30,r30 # Shift in the '1' into div
-+        BREAI     $LaDIV2     # Div2
-+$LaLOOP_END:
-+        BREAI     $LaRETURN_HERE
-+$LaDiv_By_Zero:
-+$LaResult_Is_Zero:
-+        or      r3,r0,r0   # set result to 0
-+#else
- 	bgtid	r6,$LaDIV0
- 	addik	r3,r0,0
- 	addik	r18,r0,0x7fffffff
-@@ -111,7 +161,7 @@ $LaLOOP_END:
- $LaDiv_By_Zero:
- $LaResult_Is_Zero:
- 	or 	r3,r0,r0   # set result to 0
--
-+#endif
- #ifdef __arch64__
- $LaRETURN_HERE:
- # Restore values of CSRs and that of r3 and the divisor and the dividend
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
new file mode 100644
index 0000000000..91c7c026b7
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
@@ -0,0 +1,45 @@
+From d7d6835bd839150e864cbb0d9c9c7a497e93bbb8 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Wed, 8 May 2019 14:12:03 +0530
+Subject: [PATCH 52/54] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
+ disable fivopts by default
+
+Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
+
+ * gcc/common/config/microblaze/microblaze-common.c
+   (microblaze_option_optimization_table): Disable fivopts by default.
+
+Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
+
+Conflicts:
+	gcc/common/config/microblaze/microblaze-common.c
+---
+ gcc/common/config/microblaze/microblaze-common.c | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
+index 4391f939626..cf2db8afe36 100644
+--- a/gcc/common/config/microblaze/microblaze-common.c
++++ b/gcc/common/config/microblaze/microblaze-common.c
+@@ -24,7 +24,18 @@
+ #include "common/common-target.h"
+ #include "common/common-target-def.h"
+ 
++/* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
++static const struct default_options microblaze_option_optimization_table[] =
++  {
++    /* Turn off ivopts by default. It messes up cse. 
++    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
++    { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
++    { OPT_LEVELS_NONE, 0, NULL, 0 }
++  };
++
+ #undef TARGET_DEFAULT_TARGET_FLAGS
+ #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
+ 
++#undef TARGET_OPTION_OPTIMIZATION_TABLE
++#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
+ struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch
deleted file mode 100644
index 8dce847642..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch
+++ /dev/null
@@ -1,478 +0,0 @@
-From e3b95d5646d4197bff81105c12bcbc5e7dba1725 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 18 Apr 2019 16:00:37 +0530
-Subject: [PATCH 53/58] [Patch, microblaze]: MB-64 removal of barrel-shift
- instructions from default
-
-By default MB-64 is generatting barrel-shift instructions. It has been
-removed from default. Barrel-shift instructions will be generated only if
-barrel-shifter is enabled. Similarly to double instructions as well.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- gcc/config/microblaze/microblaze.c  |   2 +-
- gcc/config/microblaze/microblaze.md | 269 ++++++++++++++++++++++++++--
- 2 files changed, 252 insertions(+), 19 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 12b1da852dd..5b4c21af365 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -4000,7 +4000,7 @@ microblaze_expand_divide (rtx operands[])
-   emit_insn (gen_rtx_CLOBBER (Pmode, reg18));
- 
-   if (TARGET_MB_64) {
--      emit_insn (gen_ashldi3_long (regt1, operands[1], GEN_INT(4)));
-+      emit_insn (gen_ashldi3 (regt1, operands[1], GEN_INT(4)));
-       emit_insn (gen_adddi3 (regt1, regt1, operands[2]));
-     }
-   else  {
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 626eade9468..6cc62666269 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -547,7 +547,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (plus:DF (match_operand:DF 1 "register_operand" "d")
-                  (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dadd\t%0,%1,%2"
-   [(set_attr "type"     "fadd")
-   (set_attr "mode"      "DF")
-@@ -557,7 +557,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (minus:DF (match_operand:DF 1 "register_operand" "d")
-                   (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "drsub\t%0,%2,%1"
-   [(set_attr "type"     "frsub")
-   (set_attr "mode"      "DF")
-@@ -567,7 +567,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (mult:DF (match_operand:DF 1 "register_operand" "d")
-                  (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dmul\t%0,%1,%2"
-   [(set_attr "type"     "fmul")
-   (set_attr "mode"      "DF")
-@@ -577,7 +577,7 @@
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (div:DF (match_operand:DF 1 "register_operand" "d")
-                 (match_operand:DF 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "ddiv\t%0,%2,%1"
-   [(set_attr "type"     "fdiv")
-   (set_attr "mode"      "DF")
-@@ -587,7 +587,7 @@
- (define_insn "sqrtdf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (sqrt:DF (match_operand:DF 1 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dsqrt\t%0,%1"
-   [(set_attr "type"     "fsqrt")
-   (set_attr "mode"      "DF")
-@@ -596,7 +596,7 @@
- (define_insn "floatdidf2"
-   [(set (match_operand:DF 0 "register_operand" "=d")
-         (float:DF (match_operand:DI 1 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dbl\t%0,%1"
-   [(set_attr "type"     "fcvt")
-   (set_attr "mode"      "DF")
-@@ -605,7 +605,7 @@
- (define_insn "fix_truncdfdi2"
-   [(set (match_operand:DI 0 "register_operand" "=d")
-         (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "d"))))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_HARD_FLOAT && TARGET_FLOAT_CONVERT"
-   "dlong\t%0,%1"
-   [(set_attr "type"     "fcvt")
-   (set_attr "mode"      "DI")
-@@ -1301,6 +1301,34 @@
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"4")])
- 
-+(define_insn "*movdi_internal2_bshift"
-+  [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
-+	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+        return "addlk\t%0,%1,r0";
-+     case 1:
-+     case 2:
-+        if (GET_CODE (operands[1]) == CONST_INT &&
-+	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-+	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+        else
-+	  return "addlik\t%0,r0,%1";
-+     case 3:
-+     case 4:
-+       return "ll%i1\t%0,%1";
-+     case 5:
-+     case 6:
-+       return "sl%i0\t%z1,%0";
-+     }
-+   }
-+  [(set_attr "type"	"load,no_delay_load,no_delay_load,no_delay_load,no_delay_load,no_delay_store,no_delay_store")
-+  (set_attr "mode"	"DI")
-+  (set_attr "length"	"4,4,12,4,8,4,8")])
-+
- (define_insn "*movdi_internal2"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,   d,d,R,m")
- 	(match_operand:DI 1 "move_src_operand"         " d,I,Mnis,R,m,dJ,dJ"))]
-@@ -1314,7 +1342,15 @@
-      case 2:
-         if (GET_CODE (operands[1]) == CONST_INT && 
- 	    (INTVAL (operands[1]) > (long long)549755813887 || INTVAL (operands[1]) < (long long)-549755813888))
-- 	  return "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-+          {
-+            operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+            output_asm_insn ("addlik\t%0,r0,%h1", operands);
-+            output_asm_insn ("addlik\t%2,r0,32", operands);
-+            output_asm_insn ("addlik\t%2,%2,-1", operands);
-+            output_asm_insn ("beaneid\t%2,.-8", operands);
-+            output_asm_insn ("addlk\t%0,%0,%0", operands);
-+            return "addlik\t%0,%0,%j1 #li => la";
-+          }
-         else	
- 	  return "addlik\t%0,r0,%1";
-      case 3:
-@@ -1388,7 +1424,7 @@
- (define_insn "movdi_long_int"
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
- 	(match_operand:DI 1 "general_operand"      "i"))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "addlik\t%0,r0,%h1\n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%j1 #li => la";
-   [(set_attr "type"	"no_delay_arith")
-   (set_attr "mode"	"DI")
-@@ -1655,6 +1691,33 @@
- ;; movdf_internal
- ;; Applies to both TARGET_SOFT_FLOAT and TARGET_HARD_FLOAT
- ;;
-+(define_insn "*movdf_internal_64_bshift"
-+  [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-+        (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-+  {
-+    switch (which_alternative)
-+    {
-+      case 0:
-+	return "addlk\t%0,%1,r0";
-+      case 1:
-+	return "addlk\t%0,r0,r0";
-+      case 2:
-+      case 4:
-+          return "ll%i1\t%0,%1";
-+      case 3:
-+      {
-+	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-+      }
-+      case 5:
-+	return "sl%i0\t%1,%0";
-+    }
-+    gcc_unreachable ();
-+  }
-+  [(set_attr "type"     "no_delay_move,no_delay_move,no_delay_load,no_delay_load,no_delay_load,no_delay_store")
-+  (set_attr "mode"      "DF")
-+  (set_attr "length"    "4,4,4,16,4,4")])
-+
- (define_insn "*movdf_internal_64"
-   [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,d,d,m")
-         (match_operand:DF 1 "general_operand" "d,dG,m,F,T,d"))]
-@@ -1671,7 +1734,13 @@
-           return "ll%i1\t%0,%1";
-       case 3:
-       {
--	return "addlik\t%0,r0,%j1 \n\tbsllli\t%0,%0,32\n\taddlik\t%0,%0,%h1 #Xfer Lo";
-+	operands[2] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+	output_asm_insn ("addlik\t%0,r0,%h1", operands);
-+	output_asm_insn ("addlik\t%2,r0,32", operands);
-+	output_asm_insn ("addlik\t%2,%2,-1", operands);
-+	output_asm_insn ("beaneid\t%2,.-8", operands);
-+	output_asm_insn ("addlk\t%0,%0,%0", operands);
-+	return "addlik\t%0,%0,%j1 #li => la";
-       }
-       case 5:
- 	return "sl%i0\t%1,%0";
-@@ -1791,11 +1860,21 @@
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_ashldi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_ashldi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_ashldi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -1805,7 +1884,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(ashift:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-   bsllli\t%0,%1,%2
-   bslll\t%0,%1,%2"
-@@ -1813,6 +1892,51 @@ else
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")]
- )
-+
-+(define_insn "ashldi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "addlk\t%0,%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+   (set_attr "mode"    "DI")
-+   (set_attr "length"  "20")]
-+)
-+
-+(define_insn "ashldi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashift:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1])) 
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "addlk\t%0,%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "DI")
-+  (set_attr "length"   "28")]
-+)
-+
- ;; The following patterns apply when there is no barrel shifter present
- 
- (define_insn "*ashlsi3_with_mul_delay"
-@@ -1946,11 +2070,21 @@ else
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_ashrdi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_ashrdi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_ashrdi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -1960,7 +2094,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-    bslrai\t%0,%1,%2
-    bslra\t%0,%1,%2"
-@@ -1968,6 +2102,51 @@ else
-   (set_attr "mode"	"DI,DI")
-   (set_attr "length"	"4,4")]
-   )
-+
-+(define_insn "ashrdi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srla\t%0,%0";
-+  }
-+  [(set_attr "type"    "arith")
-+  (set_attr "mode"    "DI")
-+  (set_attr "length"  "20")]
-+)
-+
-+(define_insn "ashrdi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (ashiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1])) 
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srla\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "DI")
-+  (set_attr "length"   "28")]
-+)
-+
- (define_expand "ashrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2085,11 +2264,21 @@ else
- "TARGET_MB_64"
- {
- ;;if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
--if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65)
-+if (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && TARGET_BARREL_SHIFT)
-   {
-     emit_insn(gen_lshrdi3_long (operands[0], operands[1],operands[2]));
-     DONE;
-   }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 && CONST_INT_P (operands[2]))
-+  {
-+    emit_insn(gen_lshrdi3_const (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
-+else if(INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 65 &&  GET_CODE (operands[2]) == REG)
-+  {
-+    emit_insn(gen_lshrdi3_reg (operands[0], operands[1],operands[2]));
-+    DONE;
-+  }
- else
-   FAIL;
- }    
-@@ -2099,7 +2288,7 @@ else
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
-                    (match_operand:DI 2 "arith_operand"    "I,d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_BARREL_SHIFT"
-   "@
-    bslrli\t%0,%1,%2
-    bslrl\t%0,%1,%2"
-@@ -2108,6 +2297,50 @@ else
-   (set_attr "length"	"4,4")]
-   )
- 
-+(define_insn "lshrdi3_const"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+
-+    output_asm_insn ("orli\t%3,r0,%2", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+        output_asm_insn ("addlk\t%0,%1,r0", operands);
-+
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srll\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"    "DI")
-+  (set_attr "length"  "20")]
-+)
-+
-+(define_insn "lshrdi3_reg"
-+  [(set (match_operand:DI 0 "register_operand" "=&d")
-+       (lshiftrt:DI (match_operand:DI 1 "register_operand"  "d")
-+                   (match_operand:DI 2 "register_operand" "d")))]
-+  "TARGET_MB_64"
-+  {
-+    operands[3] = gen_rtx_REG (DImode, MB_ABI_ASM_TEMP_REGNUM);
-+    output_asm_insn ("andli\t%3,%2,31", operands);
-+    if (REGNO (operands[0]) != REGNO (operands[1]))
-+      output_asm_insn ("addlk\t%0,r0,%1", operands);
-+    /* Exit the loop if zero shift. */
-+    output_asm_insn ("beaeqid\t%3,.+24", operands);
-+    /* Emit the loop.  */
-+    output_asm_insn ("addlk\t%0,%0,r0", operands);
-+    output_asm_insn ("addlik\t%3,%3,-1", operands);
-+    output_asm_insn ("beaneid\t%3,.-8", operands);
-+    return "srll\t%0,%0";
-+  }
-+  [(set_attr "type"    "multi")
-+  (set_attr "mode"     "SI")
-+  (set_attr "length"   "28")]
-+)
-+
- (define_expand "lshrsi3"
-   [(set (match_operand:SI 0 "register_operand" "=&d")
- 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
-@@ -2235,7 +2468,7 @@ else
- 	(eq:DI 
- 	       (match_operand:DI 1 "register_operand" "d")
- 	       (match_operand:DI 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
-   "pcmpleq\t%0,%1,%2"
-   [(set_attr "type"	"arith")
-    (set_attr "mode"	"DI")
-@@ -2247,7 +2480,7 @@ else
- 	(ne:DI 
- 	       (match_operand:DI 1 "register_operand" "d")
- 	       (match_operand:DI 2 "register_operand" "d")))]
--  "TARGET_MB_64"
-+  "TARGET_MB_64 && TARGET_PATTERN_COMPARE"
-   "pcmplne\t%0,%1,%2"
-   [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
new file mode 100644
index 0000000000..377154d7f1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch
@@ -0,0 +1,198 @@
+From e146b21e18e51ab6ce77af2c39cdf3375606c1eb Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 24 Nov 2020 12:26:32 +0530
+Subject: [PATCH 53/54] [Patch, microblaze]: Reducing Stack space for arguments
+
+Currently in Microblaze target stack space for arguments in register is being
+allocated even if there are no arguments in the function.
+This patch will optimize the extra 24 bytes that are being allocated.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+              :Ajit Agarwal  <ajitkum@xilinx.com>
+---
+ gcc/config/microblaze/microblaze-protos.h |   1 +
+ gcc/config/microblaze/microblaze.c        | 132 +++++++++++++++++++++-
+ gcc/config/microblaze/microblaze.h        |   4 +-
+ 3 files changed, 134 insertions(+), 3 deletions(-)
+
+diff --git a/gcc/config/microblaze/microblaze-protos.h b/gcc/config/microblaze/microblaze-protos.h
+index 460feac4ac5..b8a3321dbdf 100644
+--- a/gcc/config/microblaze/microblaze-protos.h
++++ b/gcc/config/microblaze/microblaze-protos.h
+@@ -60,6 +60,7 @@ extern int symbol_mentioned_p (rtx);
+ extern int label_mentioned_p (rtx);
+ extern bool microblaze_cannot_force_const_mem (machine_mode, rtx);
+ extern void microblaze_eh_return (rtx op0);
++int  microblaze_reg_parm_stack_space(tree fun);
+ #endif  /* RTX_CODE */
+ 
+ /* Declare functions in microblaze-c.c.  */
+diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
+index 1bba77dab6d..dac0596bc7d 100644
+--- a/gcc/config/microblaze/microblaze.c
++++ b/gcc/config/microblaze/microblaze.c
+@@ -2080,6 +2080,136 @@ microblaze_must_save_register (int regno)
+   return 0;
+ }
+ 
++static bool
++microblaze_parm_needs_stack (cumulative_args_t args_so_far, tree type)
++{
++  int unsignedp;
++  rtx entry_parm;
++
++  /* Catch errors.  */
++  if (type == NULL || type == error_mark_node)
++    return true;
++
++  if (TREE_CODE (type) == POINTER_TYPE)
++    return true;
++
++  /* Handle types with no storage requirement.  */
++  if (TYPE_MODE (type) == VOIDmode)
++    return false;
++
++   /* Handle complex types.  */
++  if (TREE_CODE (type) == COMPLEX_TYPE)
++    return (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type))
++             || microblaze_parm_needs_stack (args_so_far, TREE_TYPE (type)));
++
++  /* Handle transparent aggregates.  */
++  if ((TREE_CODE (type) == UNION_TYPE || TREE_CODE (type) == RECORD_TYPE)
++     && TYPE_TRANSPARENT_AGGR (type))
++  type = TREE_TYPE (first_field (type));
++
++  /* See if this arg was passed by invisible reference.  */
++  function_arg_info arg (type, /*named=*/true);
++  apply_pass_by_reference_rules (get_cumulative_args (args_so_far), arg);
++
++  /* Find mode as it is passed by the ABI.  */
++  unsignedp = TYPE_UNSIGNED (type);
++  arg.mode = promote_mode (arg.type, arg.mode, &unsignedp);
++
++  /* If there is no incoming register, we need a stack.  */
++  entry_parm = microblaze_function_arg (args_so_far, arg);
++  if (entry_parm == NULL)
++    return true;
++
++  /* Likewise if we need to pass both in registers and on the stack.  */
++  if (GET_CODE (entry_parm) == PARALLEL
++     && XEXP (XVECEXP (entry_parm, 0, 0), 0) == NULL_RTX)
++   return true;
++
++  /* Also true if we're partially in registers and partially not.  */
++  if (function_arg_partial_bytes (args_so_far, arg) != 0)
++     return true;
++
++  /* Update info on where next arg arrives in registers.  */
++  microblaze_function_arg_advance (args_so_far, arg);
++  return false;
++}
++
++static bool
++microblaze_function_parms_need_stack (tree fun, bool incoming)
++{
++  tree fntype, result;
++  CUMULATIVE_ARGS args_so_far_v;
++  cumulative_args_t args_so_far;
++  int num_of_args = 0;
++
++  /* Must be a libcall, all of which only use reg parms.  */
++  if (!fun)
++    return true;
++
++  fntype = fun;
++  if (!TYPE_P (fun))
++    fntype = TREE_TYPE (fun);
++
++  /* Varargs functions need the parameter save area.  */
++  if ((!incoming && !prototype_p (fntype)) || stdarg_p (fntype))
++    return true;
++
++  INIT_CUMULATIVE_ARGS(args_so_far_v, fntype, NULL_RTX,0,0);
++  args_so_far = pack_cumulative_args (&args_so_far_v);
++
++  /* When incoming, we will have been passed the function decl.
++ *    *      It is necessary to use the decl to handle K&R style functions,
++ *       *      where TYPE_ARG_TYPES may not be available.  */
++  if (incoming)
++    {
++      gcc_assert (DECL_P (fun));
++      result = DECL_RESULT (fun);
++    }
++  else
++    result = TREE_TYPE (fntype);
++
++  if (result && aggregate_value_p (result, fntype))
++    {
++      if (!TYPE_P (result))
++        result = build_pointer_type (result);
++        microblaze_parm_needs_stack (args_so_far, result);
++    }
++
++  if (incoming)
++    {
++      tree parm;
++      for (parm = DECL_ARGUMENTS (fun);
++           parm && parm != void_list_node;
++           parm = TREE_CHAIN (parm))
++         if (microblaze_parm_needs_stack (args_so_far, TREE_TYPE (parm)))
++           return true;
++    }
++  else
++    {
++      function_args_iterator args_iter;
++      tree arg_type;
++
++      FOREACH_FUNCTION_ARGS (fntype, arg_type, args_iter)
++      {
++        num_of_args;
++        if (microblaze_parm_needs_stack (args_so_far, arg_type))
++         return true;
++      }
++    }
++
++  if (num_of_args > 3) return true;
++
++  return false;
++}
++
++int  microblaze_reg_parm_stack_space(tree fun)
++{
++  if (microblaze_function_parms_need_stack (fun,false))
++    return MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD;
++  else
++    return 0;
++}
++
+ /* Return the bytes needed to compute the frame pointer from the current
+    stack pointer.
+ 
+@@ -3470,7 +3600,7 @@ microblaze_asm_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+   emit_insn (gen_indirect_jump (temp2));
+ 
+   /* Run just enough of rest_of_compilation.  This sequence was
+-     "borrowed" from rs6000.c.  */
++     "borrowed" from microblaze.c */
+   insn = get_insns ();
+   shorten_branches (insn);
+   assemble_start_function (thunk_fndecl, fnname);
+diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
+index d467a7ee65d..be6c798c889 100644
+--- a/gcc/config/microblaze/microblaze.h
++++ b/gcc/config/microblaze/microblaze.h
+@@ -447,9 +447,9 @@ extern struct microblaze_frame_info current_frame_info;
+ #define ARG_POINTER_CFA_OFFSET(FNDECL)		0
+ #define DWARF_CIE_DATA_ALIGNMENT -1
+ 
+-#define REG_PARM_STACK_SPACE(FNDECL)  		(MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
++#define REG_PARM_STACK_SPACE(FNDECL)  		microblaze_reg_parm_stack_space(FNDECL)
+ 
+-#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)	1
++#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE)   1
+ 
+ #define STACK_BOUNDARY				(TARGET_MB_64 ? 64 : 32)
+ 
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
deleted file mode 100644
index 70e051175e..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From 6bdb6f300593c4a633a8ec485ac2744a97b51460 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Wed, 8 May 2019 14:12:03 +0530
-Subject: [PATCH 54/58] [Patch, microblaze]: Add TARGET_OPTION_OPTIMIZATION and
- disable fivopts by default
-
-Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default.
-
- * gcc/common/config/microblaze/microblaze-common.c
-   (microblaze_option_optimization_table): Disable fivopts by default.
-
-Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
----
- gcc/common/config/microblaze/microblaze-common.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/gcc/common/config/microblaze/microblaze-common.c b/gcc/common/config/microblaze/microblaze-common.c
-index 0b9d5a1b453..cf2db8afe36 100644
---- a/gcc/common/config/microblaze/microblaze-common.c
-+++ b/gcc/common/config/microblaze/microblaze-common.c
-@@ -27,13 +27,15 @@
- /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */
- static const struct default_options microblaze_option_optimization_table[] =
-   {
--    /* Turn off ivopts by default. It messes up cse. */
-+    /* Turn off ivopts by default. It messes up cse. 
-+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, */
-     { OPT_LEVELS_ALL, OPT_fivopts, NULL, 0 },
--    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
-     { OPT_LEVELS_NONE, 0, NULL, 0 }
-   };
- 
- #undef TARGET_DEFAULT_TARGET_FLAGS
- #define TARGET_DEFAULT_TARGET_FLAGS	TARGET_DEFAULT
- 
-+#undef TARGET_OPTION_OPTIMIZATION_TABLE
-+#define TARGET_OPTION_OPTIMIZATION_TABLE microblaze_option_optimization_table
- struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch
deleted file mode 100644
index 4ab3cec935..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0055-Added-new-MB-64-single-register-arithmetic-instructi.patch
+++ /dev/null
@@ -1,107 +0,0 @@
-From 3198a31122bb0436d298d29e986bb69bc3c526a9 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Fri, 23 Aug 2019 16:16:53 +0530
-Subject: [PATCH 55/58] Added new MB-64 single register arithmetic instructions
-
----
- gcc/config/microblaze/microblaze.md | 56 +++++++++++++++++++++++++++++
- 1 file changed, 56 insertions(+)
-
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 6cc62666269..696be7b300f 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -654,6 +654,18 @@
-    }
- })
- 
-+(define_insn "adddi3_int"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+  (plus:DI (match_operand:DI 1 "register_operand" "%0")
-+                 (match_operand:DI 2 "immediate_operand" "I")))]
-+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
-+  "@
-+  addlik\t%0,%2"
-+  [(set_attr "type"     "darith")
-+  (set_attr "mode"      "DI")
-+  (set_attr "length"    "4")]
-+)
-+
- (define_insn "*adddi3_long"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(plus:DI (match_operand:DI 1 "register_operand" "%d,d")
-@@ -719,6 +731,18 @@
- {
- }")
- 
-+(define_insn "subdi316imm"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (minus:DI (match_operand:DI 1 "register_operand" "d")
-+                  (match_operand:DI 2 "arith_operand" "K")))]
-+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767) && (REGNO (operands[0]) == REGNO (operands[1]))"
-+  "@
-+   addlik\t%0,-%2"
-+  [(set_attr "type"     "darith")
-+  (set_attr "mode"      "DI")
-+  (set_attr "length"    "4")])
-+
-+
- (define_insn "subsidi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- 	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
-@@ -1015,6 +1039,17 @@
- ;; Logical
- ;;----------------------------------------------------------------
- 
-+(define_insn "anddi3imm16"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (and:DI (match_operand:DI 1 "arith_operand" "%0")
-+                (match_operand:DI 2 "arith_operand" "K")))]
-+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
-+  "@
-+   andli\t%0,%2"
-+  [(set_attr "type"     "darith")
-+  (set_attr "mode"      "DI")
-+  (set_attr "length"    "4")])
-+
- (define_insn "anddi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- 	(and:DI (match_operand:DI 1 "arith_operand" "d,d,d")
-@@ -1042,6 +1077,16 @@
-   (set_attr "mode"	"SI,SI,SI,SI")
-   (set_attr "length"	"4,8,8,8")])
- 
-+(define_insn "iordi3imm16"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (ior:DI (match_operand:DI 1 "arith_operand" "%0")
-+                (match_operand:DI 2 "arith_operand" "K")))]
-+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
-+  "@
-+   orli\t%0,%2"
-+  [(set_attr "type"     "darith")
-+  (set_attr "mode"      "DI")
-+  (set_attr "length"    "4")])
- 
- (define_insn "iordi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
-@@ -1069,6 +1114,17 @@
-   (set_attr "mode"	"SI,SI,SI,SI")
-   (set_attr "length"	"4,8,8,8")])
- 
-+(define_insn "xordi3imm16"
-+  [(set (match_operand:DI 0 "register_operand" "=d")
-+        (xor:DI (match_operand:DI 1 "arith_operand" "%0")
-+                (match_operand:DI 2 "arith_operand" "K")))]
-+  "TARGET_MB_64 && ((long long)INTVAL(operands[2]) > (long long)-32768) && ((long long) INTVAL(operands[2]) < (long long)32767)"
-+  "@
-+   xorli\t%0,%2"
-+  [(set_attr "type"     "darith")
-+  (set_attr "mode"      "DI")
-+  (set_attr "length"    "4")])
-+
- (define_insn "xordi3"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
- 	(xor:DI (match_operand:DI 1 "arith_operand" "%d,d")
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
deleted file mode 100644
index afe3ae96ec..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From 1dadde6d9a49010a495529c9b5ea6c2bb75cc5f1 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 26 Aug 2019 15:55:22 +0530
-Subject: [PATCH 56/58] [Patch,MicroBlaze] : Added support for 64 bit Immediate
- values.
-
----
- gcc/config/microblaze/constraints.md | 4 ++--
- gcc/config/microblaze/microblaze.md  | 3 +--
- 2 files changed, 3 insertions(+), 4 deletions(-)
-
-diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
-index 4a6cf419671..2432b480a2c 100644
---- a/gcc/config/microblaze/constraints.md
-+++ b/gcc/config/microblaze/constraints.md
-@@ -53,9 +53,9 @@
-        (match_test "ival > 0 && ival < 0x10000")))
- 
- (define_constraint "K"
--  "A constant in the range 0xffffff8000000000L  to 0x0000007fffffffffL (inclusive)."
-+  "A constant in the range  -9223372036854775808 to 9223372036854775807 (inclusive)."
-   (and (match_code "const_int")
--       (match_test "ival > (long long)-549755813888 && ival < (long long)549755813887")))
-+       (match_test "ival > (long long)-9223372036854775808  && ival < (long long)9223372036854775807")))
- 
- ;; Define floating point constraints
- 
-diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
-index 696be7b300f..f0a9701ab18 100644
---- a/gcc/config/microblaze/microblaze.md
-+++ b/gcc/config/microblaze/microblaze.md
-@@ -1334,8 +1334,7 @@
-   [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d")
- 	(match_operand:DI 1 "immediate_operand" "J,I,Mnis"))]
-   "TARGET_MB_64 && (register_operand (operands[0], DImode) && 
--           (GET_CODE (operands[1]) == CONST_INT && 
--                 (INTVAL (operands[1]) <= (long long)549755813887 && INTVAL (operands[1]) >= (long long)-549755813888)))"  
-+           (GET_CODE (operands[1]) == CONST_INT))"
-   "@
-    addlk\t%0,r0,r0\t
-    addlik\t%0,r0,%1\t #N1 %X1
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
deleted file mode 100644
index ebd707c935..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-From ab73daf6bf1bc652e9557386cba5eb237af66350 Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Thu, 9 Jan 2020 12:30:41 +0530
-Subject: [PATCH 57/58] [Patch, microblaze]: Fix Compiler crash with
- -freg-struct-return This patch fixes a bug in MB GCC regarding the passing
- struct values in registers. Currently we are only handling SImode With this
- patch all other modes are handled properly
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-2020-01-09 Nagaraju Mekala <nmekala@xilix.com>
-
-	* gcc/config/microblaze/microblaze.h
-	(LIBCALL_Value): Remove macro
-	(PROMOTE_MODE): Remove macro
-	* gcc/config/microblaze/microblaze.c
-	(TARGET_LIBCALL_Value): Added new macro
-	(microblaze_function_value): Updated the return Value
----
- gcc/config/microblaze/microblaze.c | 11 ++++++++++-
- gcc/config/microblaze/microblaze.h | 19 -------------------
- 2 files changed, 10 insertions(+), 20 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
-index 5b4c21af365..31869982d27 100644
---- a/gcc/config/microblaze/microblaze.c
-+++ b/gcc/config/microblaze/microblaze.c
-@@ -4038,7 +4038,16 @@ microblaze_function_value (const_tree valtype,
- 			   const_tree func ATTRIBUTE_UNUSED,
- 			   bool outgoing ATTRIBUTE_UNUSED)
- {
--  return LIBCALL_VALUE (TYPE_MODE (valtype));
-+  return gen_rtx_REG (TYPE_MODE (valtype), GP_RETURN);
-+}
-+
-+#undef  TARGET_LIBCALL_VALUE
-+#define TARGET_LIBCALL_VALUE microblaze_libcall_value
-+
-+rtx
-+microblaze_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
-+{
-+  return gen_rtx_REG (mode, GP_RETURN);
- }
- 
- /* Implement TARGET_SCHED_ADJUST_COST.  */
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 0c493b6f6e4..5eb95c2600a 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -266,13 +266,6 @@ extern enum pipeline_type microblaze_pipe;
- 
- #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
- 
--#ifndef __arch64__
--#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
--  if (GET_MODE_CLASS (MODE) == MODE_INT         \
--      && GET_MODE_SIZE (MODE) < 4)              \
--    (MODE) = SImode;
--#endif
--
- /* Standard register usage.  */
- 
- /* On the MicroBlaze, we have 32 integer registers */
-@@ -471,18 +464,6 @@ extern struct microblaze_frame_info current_frame_info;
- 
- #define MAX_ARGS_IN_REGISTERS			MB_ABI_MAX_ARG_REGS
- 
--#ifdef __aarch64__
--#define LIBCALL_VALUE(MODE)						\
--  gen_rtx_REG (MODE,GP_RETURN)
--#else								
--#define LIBCALL_VALUE(MODE)						\
--  gen_rtx_REG (								\
--	   ((GET_MODE_CLASS (MODE) != MODE_INT				\
--	     || GET_MODE_SIZE (MODE) >= 4)				\
--	    ? (MODE)							\
--	    : SImode), GP_RETURN)
--#endif
--
- /* 1 if N is a possible register number for a function value.
-    On the MicroBlaze, R2 R3 are the only register thus used.
-    Currently, R2 are only implemented  here (C has no complex type)  */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch
deleted file mode 100644
index e3c4b87b51..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From dd73d8ba32c0c24f17a54538b9bb54beb5d8d4e0 Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Thu, 13 Aug 2020 16:28:57 -0500
-Subject: [PATCH 58/58] microblaze: Avoid UINTPTR_TYPE macro redefinition
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- gcc/config/microblaze/microblaze.h | 5 -----
- 1 file changed, 5 deletions(-)
-
-diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
-index 5eb95c2600a..4cb98bac849 100644
---- a/gcc/config/microblaze/microblaze.h
-+++ b/gcc/config/microblaze/microblaze.h
-@@ -246,11 +246,6 @@ extern enum pipeline_type microblaze_pipe;
- #undef PTRDIFF_TYPE
- #define PTRDIFF_TYPE (TARGET_MB_64 ? "long int" : "int")
- 
--/*#undef INTPTR_TYPE
--#define INTPTR_TYPE (TARGET_MB_64 ? "long int" : "int")*/
--#undef UINTPTR_TYPE
--#define UINTPTR_TYPE (TARGET_MB_64 ? "long unsigned int" : "unsigned int")
--
- #define DATA_ALIGNMENT(TYPE, ALIGN)					\
-   ((((ALIGN) < BITS_PER_WORD)						\
-     && (TREE_CODE (TYPE) == ARRAY_TYPE					\
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch
new file mode 100644
index 0000000000..af8ebf3be6
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-10/microblaze-mulitlib-hack.patch
@@ -0,0 +1,58 @@
+Microblaze Mulitlib hack
+
+Based on the patch:
+
+From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001
+From: Khem Raj <raj.khem@gmail.com>
+Date: Fri, 29 Mar 2013 09:10:06 +0400
+Subject: [PATCH 04/36] 64-bit multilib hack.
+
+GCC has internal multilib handling code but it assumes a very specific rigid directory
+layout. The build system implementation of multilib layout is very generic and allows
+complete customisation of the library directories.
+
+This patch is a partial solution to allow any custom directories to be passed into gcc
+and handled correctly. It forces gcc to use the base_libdir (which is the current
+directory, "."). We need to do this for each multilib that is configured as we don't
+know which compiler options may be being passed into the compiler. Since we have a compiler
+per mulitlib at this point that isn't an issue.
+
+The one problem is the target compiler is only going to work for the default multlilib at
+this point. Ideally we'd figure out which multilibs were being enabled with which paths
+and be able to patch these entries with a complete set of correct paths but this we
+don't have such code at this point. This is something the target gcc recipe should do
+and override these platform defaults in its build config.
+
+Do same for riscv64 and aarch64
+
+RP 15/8/11
+
+Upstream-Status: Inappropriate[OE-Specific]
+
+Signed-off-by: Khem Raj <raj.khem@gmail.com>
+Signed-off-by: Elvis Dowson <elvis.dowson@gmail.com>
+Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+
+Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze
+===================================================================
+--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze
++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze
+@@ -1,5 +1,6 @@
+ MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
+-MULTILIB_DIRNAMES = m64 bs le m mh
++#MULTILIB_DIRNAMES = m64 bs le m mh
++MULTILIB_DIRNAMES = . . . . .
+ MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *m64
+ MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
+Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
+===================================================================
+--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux
++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
+@@ -1,3 +1,4 @@
+ MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
+-MULTILIB_DIRNAMES = bs m mh
++#MULTILIB_DIRNAMES = bs m mh
++MULTILIB_DIRNAMES = . . .
+ MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
index 79b895fc59..f1ba2ea667 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gcc/gcc-source_10.%.bbappend
@@ -4,60 +4,56 @@ FILESEXTRAPATHS_append_microblaze := ":${THISDIR}/gcc-10"
 SRC_URI_append_microblaze = " \
     file://0001-LOCAL-Testsuite-builtins-tests-require-fpic.patch \
     file://0002-LOCAL-Quick-fail-g-.dg-opt-memcpy1.C.patch \
-    file://0003-LOCAL-Testsuite-explicitly-add-fivopts-for-tests-tha.patch \
-    file://0004-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
-    file://0005-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
-    file://0006-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
-    file://0007-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
-    file://0008-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
-    file://0009-Patch-microblaze-Fix-atomic-side-effects.patch \
-    file://0010-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
-    file://0011-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
-    file://0012-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
-    file://0013-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
-    file://0014-Patch-microblaze-Disable-fivopts-by-default.patch \
-    file://0015-Patch-microblaze-Removed-moddi3-routinue.patch \
-    file://0016-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
-    file://0017-Patch-microblaze-Add-optimized-lshrsi3.patch \
-    file://0018-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
-    file://0019-Patch-microblaze-Add-cbranchsi4_reg.patch \
-    file://0020-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
-    file://0021-Patch-OPT-Update-heuristics-for-loop-invariant-for-a.patch \
-    file://0022-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
-    file://0023-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
-    file://0024-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
-    file://0025-Patch-rtl-Optimization-Better-register-pressure-esti.patch \
-    file://0026-Patch-microblaze-Correct-the-const-high-double-immed.patch \
-    file://0027-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
-    file://0028-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
-    file://0029-Patch-microblaze-Add-new-bit-field-instructions.patch \
-    file://0030-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
-    file://0031-Fixing-the-issue-with-the-builtin_alloc.patch \
-    file://0032-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
-    file://0033-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
-    file://0034-Intial-commit-of-64-bit-Microblaze.patch \
-    file://0035-Intial-commit-for-64bit-MB-sources.patch \
-    file://0036-re-arrangement-of-the-compare-branches.patch \
-    file://0037-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
-    file://0038-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
-    file://0039-Fix-various-issues.patch \
-    file://0040-Fixed-below-issues.patch \
-    file://0041-Fix-various.patch \
-    file://0042-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
-    file://0043-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
-    file://0044-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
-    file://0045-fixing-the-typo-errors-in-umodsi3-file.patch \
-    file://0046-fixing-the-32bit-LTO-related-issue9-1014024.patch \
-    file://0047-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
-    file://0048-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
-    file://0049-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-    file://0050-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
-    file://0051-Patch-Microblaze-Check-the-possibiity-of-peephole2-o.patch \
-    file://0052-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
-    file://0053-Patch-microblaze-MB-64-removal-of-barrel-shift-instr.patch \
-    file://0054-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
-    file://0055-Added-new-MB-64-single-register-arithmetic-instructi.patch \
-    file://0056-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
-    file://0057-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
-    file://0058-microblaze-Avoid-UINTPTR_TYPE-macro-redefinition.patch \
+    file://0003-LOCAL-For-dejagnu-static-testing-on-qemu-suppress-wa.patch \
+    file://0004-Patch-testsuite-Add-MicroBlaze-to-target-supports-fo.patch \
+    file://0005-Patch-testsuite-Update-MicroBlaze-strings-test.patch \
+    file://0006-Patch-testsuite-Allow-MicroBlaze-.weakext-pattern-in.patch \
+    file://0007-Patch-testsuite-Add-MicroBlaze-to-check_profiling_av.patch \
+    file://0008-Patch-microblaze-Fix-atomic-side-effects.patch \
+    file://0009-Patch-microblaze-Fix-atomic-boolean-return-value.patch \
+    file://0010-Patch-microblaze-Fix-the-Microblaze-crash-with-msmal.patch \
+    file://0011-Patch-microblaze-Added-ashrsi3_with_size_opt.patch \
+    file://0012-Patch-microblaze-Use-bralid-for-profiler-calls.patch \
+    file://0013-Patch-microblaze-Removed-moddi3-routinue.patch \
+    file://0014-Patch-microblaze-Add-INIT_PRIORITY-support.patch \
+    file://0015-Patch-microblaze-Add-optimized-lshrsi3.patch \
+    file://0016-Patch-microblaze-Add-cbranchsi4_reg.patch \
+    file://0017-Patch-microblaze-Inline-Expansion-of-fsqrt-builtin.patch \
+    file://0018-PATCH-microblaze.md-Improve-adddi3-and-subdi3-insn-d.patch \
+    file://0019-Patch-microblaze-Update-ashlsi3-movsf-patterns.patch \
+    file://0020-Patch-microblaze-8-stage-pipeline-for-microblaze.patch \
+    file://0021-Patch-microblaze-Correct-the-const-high-double-immed.patch \
+    file://0022-Fix-microblaze-Fix-internal-compiler-error-with-msma.patch \
+    file://0023-patch-microblaze-Fix-the-calculation-of-high-word-in.patch \
+    file://0024-Patch-microblaze-Add-new-bit-field-instructions.patch \
+    file://0025-Patch-microblaze-Fix-bug-in-MB-version-calculation.patch \
+    file://0026-Fixing-the-issue-with-the-builtin_alloc.patch \
+    file://0027-Patch-Microblaze-update-in-constraints-for-bitfield-.patch \
+    file://0028-Patch-Microblaze-Removed-fsqrt-generation-for-double.patch \
+    file://0029-Patch-MicroBlaze-Intial-commit-of-64-bit-Microblaze.patch \
+    file://0030-Intial-commit-for-64bit-MB-sources.patch \
+    file://0031-re-arrangement-of-the-compare-branches.patch \
+    file://0032-Patch-Microblaze-previous-commit-broke-the-handling-.patch \
+    file://0033-Patch-Microblaze-Support-of-multilibs-with-m64.patch \
+    file://0034-Fixed-issues-like.patch \
+    file://0035-Fixed-below-issues.patch \
+    file://0036-Added-double-arith-instructions.patch \
+    file://0037-Fixed-the-issue-in-the-delay-slot-with-swap-instruct.patch \
+    file://0038-Fixed-the-load-store-issue-with-the-32bit-arith-libr.patch \
+    file://0039-extending-the-Dwarf-support-to-64bit-Microblaze.patch \
+    file://0040-fixing-the-typo-errors-in-umodsi3-file.patch \
+    file://0041-fixing-the-32bit-LTO-related-issue9-1014024.patch \
+    file://0042-Fixed-the-missing-stack-adjustment-in-prologue-of-mo.patch \
+    file://0043-Patch-Microblaze-corrected-SPN-for-dlong-instruction.patch \
+    file://0044-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+    file://0045-Fix-the-MB-64-bug-of-handling-QI-objects.patch \
+    file://0046-Patch-Microblaze-We-will-check-the-possibility-of-pe.patch \
+    file://0047-Patch-MicroBlaze-fixed-typos-in-mul-div-and-mod-asse.patch \
+    file://0048-Author-Nagaraju-nmekala-xilinx.com.patch \
+    file://0049-Added-new-MB-64-single-register-arithmetic-instructi.patch \
+    file://0050-Patch-MicroBlaze-Added-support-for-64-bit-Immediate-.patch \
+    file://0051-Patch-microblaze-Fix-Compiler-crash-with-freg-struct.patch \
+    file://0052-Patch-microblaze-Add-TARGET_OPTION_OPTIMIZATION-and-.patch \
+    file://0053-Patch-microblaze-Reducing-Stack-space-for-arguments.patch \
+    file://microblaze-mulitlib-hack.patch \
 "
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
index 906ef4dbe4..4ba5d98cfe 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb-microblaze.inc
@@ -5,35 +5,54 @@ LTTNGUST_microblaze = ""
 FILESEXTRAPATHS_append := ":${THISDIR}/gdb"
 
 SRC_URI_append_microblaze = " \
-    file://0001-sim-Allow-microblaze-architecture.patch \
-    file://0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
-    file://0004-Disable-the-warning-message-for-eh_frame_hdr.patch \
-    file://0005-Fix-relaxation-of-assembler-resolved-references.patch \
-    file://0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch \
-    file://0007-upstream-change-to-garbage-collection-sweep-causes-m.patch \
-    file://0008-Fix-bug-in-TLSTPREL-Relocation.patch \
-    file://0009-Added-Address-extension-instructions.patch \
-    file://0010-Add-new-bit-field-instructions.patch \
-    file://0011-fixing-the-imm-bug.patch \
-    file://0015-intial-commit-of-MB-64-bit.patch \
-    file://0016-MB-X-initial-commit.patch \
-    file://0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
-    file://0018-Added-relocations-for-MB-X.patch \
-    file://0019-Update-MB-x.patch \
-    file://0020-Various-fixes.patch \
-    file://0021-Adding-new-relocation-to-support-64bit-rodata.patch \
-    file://0022-fixing-the-.bss-relocation-issue.patch \
-    file://0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
-    file://0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch \
-    file://0026-fixing-the-long-long-long-mingw-toolchain-issue.patch \
-    file://0027-Added-support-to-new-arithmetic-single-register-inst.patch \
-    file://0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
-    file://0033-Fix-various-compile-warnings.patch \
-    file://0034-Add-initial-port-of-linux-gdbserver.patch \
-    file://0035-Initial-port-of-core-reading-support.patch \
-    file://0036-Fix-debug-message-when-register-is-unavailable.patch \
-    file://0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
-    file://0038-Initial-support-for-native-gdb.patch \
-    file://0039-Fixing-the-issues-related-to-GDB-7.12.patch \
-    file://0040-Patch-microblaze-Adding-64-bit-MB-support.patch \
-        "
+     file://0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch \
+     file://0003-Disable-the-warning-message-for-eh_frame_hdr.patch \
+     file://0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch \
+     file://0005-upstream-change-to-garbage-collection-sweep-causes-m.patch \
+     file://0006-Fix-bug-in-TLSTPREL-Relocation.patch \
+     file://0007-Added-Address-extension-instructions.patch \
+     file://0008-fixing-the-MAX_OPCODES-to-correct-value.patch \
+     file://0009-Add-new-bit-field-instructions.patch \
+     file://0010-fixing-the-imm-bug.patch \
+     file://0014-intial-commit-of-MB-64-bit.patch \
+     file://0015-MB-X-initial-commit.patch \
+     file://0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch \
+     file://0017-Added-relocations-for-MB-X.patch \
+     file://0018-Fixed-MB-x-relocation-issues.patch \
+     file://0019-Fixing-the-branch-related-issues.patch \
+     file://0020-Fixed-address-computation-issues-with-64bit-address.patch \
+     file://0021-Adding-new-relocation-to-support-64bit-rodata.patch \
+     file://0022-fixing-the-.bss-relocation-issue.patch \
+     file://0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch \
+     file://0025-fixing-the-long-long-long-mingw-toolchain-issue.patch \
+     file://0026-Added-support-to-new-arithmetic-single-register-inst.patch \
+     file://0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch \
+     file://0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch \
+     file://0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch \
+     file://0034-Initial-port-of-core-reading-support-Added-support-f.patch \
+     file://0035-Fix-debug-message-when-register-is-unavailable.patch \
+     file://0036-revert-master-rebase-changes-to-gdbserver.patch \
+     file://0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch \
+     file://0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch \
+     file://0039-Initial-support-for-native-gdb.patch \
+     file://0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch \
+     file://0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch \
+     file://0042-porting-GDB-for-linux.patch \
+     file://0043-Binutils-security-check-is-causing-build-error-for-w.patch \
+     file://0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch \
+     file://0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch \
+     file://0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch \
+     file://0047-bfd-elf64-microblaze.c-Fix-build-failures.patch \
+     file://0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch \
+     file://0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch \
+     file://0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch \
+     file://0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch \
+     file://0052-sim-Allow-microblaze-architecture.patch \
+     file://0053-gdb-Fix-microblaze-target-compilation.patch \
+     "
+
+#
+##     file://0048-bfd-gas-Use-standard-method-to-set-the-machine-arch.patch \
+##     file://0052-opcodes-microblaze-opc.h-Expand-the-size-to-int-to-d.patch \
+##     file://0053-opcodes-microblaze-opc.h-MIN_IMML-is-too-large.patch \
+#
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
new file mode 100644
index 0000000000..bf8757aebc
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
@@ -0,0 +1,65 @@
+From fd3110f46b2de34bddfe855aa8830c957e89d815 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 8 May 2013 11:03:36 +1000
+Subject: [PATCH 01/52] Add wdc.ext.clear and wdc.ext.flush insns
+
+Added two new instructions, wdc.ext.clear and wdc.ext.flush,
+to enable MicroBlaze to flush an external cache, which is
+used with the new coherency support for multiprocessing.
+
+Signed-off-by:nagaraju <nmekala@xilix.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ opcodes/microblaze-opc.h  | 5 ++++-
+ opcodes/microblaze-opcm.h | 4 ++--
+ 2 files changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 62ee3c9a4d..865151f95b 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -91,6 +91,7 @@
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
++#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+@@ -101,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+ 
+ struct op_code_struct
+ {
+@@ -174,7 +175,9 @@ struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 5a2d3b0c8b..42f3dd3be5 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch
deleted file mode 100644
index 6f05472060..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0001-sim-Allow-microblaze-architecture.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From d23be47051b4410e2e74c6db6bf9a1a9f7195f6d Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Thu, 6 Aug 2020 15:37:52 -0500
-Subject: [PATCH 01/40] sim: Allow microblaze* architecture
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- sim/configure     | 2 +-
- sim/configure.tgt | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/sim/configure b/sim/configure
-index 72f95cd5c7a..9e28cc78687 100755
---- a/sim/configure
-+++ b/sim/configure
-@@ -3795,7 +3795,7 @@ subdirs="$subdirs aarch64"
- 
- 
-        ;;
--   microblaze-*-*)
-+   microblaze*-*-*)
- 
-   sim_arch=microblaze
-   subdirs="$subdirs microblaze"
-diff --git a/sim/configure.tgt b/sim/configure.tgt
-index 8a8e03d96f4..f6743fe8d41 100644
---- a/sim/configure.tgt
-+++ b/sim/configure.tgt
-@@ -59,7 +59,7 @@ case "${target}" in
-    mcore-*-*)
-        SIM_ARCH(mcore)
-        ;;
--   microblaze-*-*)
-+   microblaze*-*-*)
-        SIM_ARCH(microblaze)
-        ;;
-    mips*-*-*)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
deleted file mode 100644
index 6967a3d7cd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0002-Add-wdc.ext.clear-and-wdc.ext.flush-insns.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From d7a3a238edac153f391a65ae45215a117d25bc48 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Wed, 8 May 2013 11:03:36 +1000
-Subject: [PATCH 02/40] Add wdc.ext.clear and wdc.ext.flush insns
-
-Added two new instructions, wdc.ext.clear and wdc.ext.flush,
-to enable MicroBlaze to flush an external cache, which is
-used with the new coherency support for multiprocessing.
-
-Signed-off-by:nagaraju <nmekala@xilix.com>
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- opcodes/microblaze-opc.h  | 5 ++++-
- opcodes/microblaze-opcm.h | 4 ++--
- 2 files changed, 6 insertions(+), 3 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 62ee3c9a4d1..865151f95b0 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -91,6 +91,7 @@
- #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
-+#define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
- 
- /* New Mask for msrset, msrclr insns.  */
-@@ -101,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 289
-+#define MAX_OPCODES 291
- 
- struct op_code_struct
- {
-@@ -174,7 +175,9 @@ struct op_code_struct
-   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
-   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
-   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
-+  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
-   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-+  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 5a2d3b0c8bb..42f3dd3be53 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,8 +33,8 @@ enum microblaze_instr
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
--  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
-+  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
-   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0003-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
new file mode 100644
index 0000000000..28d6057a7f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0003-Disable-the-warning-message-for-eh_frame_hdr.patch
@@ -0,0 +1,28 @@
+From 1e223d69ba8c3587c18e57e22dc3b6d2c6ce5cc9 Mon Sep 17 00:00:00 2001
+From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
+Date: Fri, 22 Jun 2012 01:20:20 +0200
+Subject: [PATCH 03/52] Disable the warning message for eh_frame_hdr
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+---
+ bfd/elf-eh-frame.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+Index: gdb-9.2/bfd/elf-eh-frame.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf-eh-frame.c
++++ gdb-9.2/bfd/elf-eh-frame.c
+@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, stru
+   goto success;
+ 
+  free_no_table:
++/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
++if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
+   _bfd_error_handler
+     /* xgettext:c-format */
+     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
+      abfd, sec);
++}
+   hdr_info->u.dwarf.table = FALSE;
+   if (sec_info)
+     free (sec_info);
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
deleted file mode 100644
index 78e10261ac..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-Disable-the-warning-message-for-eh_frame_hdr.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 2e87167d8c5d40d8dfbd8d879d78ab0bd6f3bdfd Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
-Date: Fri, 22 Jun 2012 01:20:20 +0200
-Subject: [PATCH 04/40] Disable the warning message for eh_frame_hdr
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
----
- bfd/elf-eh-frame.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/bfd/elf-eh-frame.c b/bfd/elf-eh-frame.c
-index b622ffcee2a..26b180f1490 100644
---- a/bfd/elf-eh-frame.c
-+++ b/bfd/elf-eh-frame.c
-@@ -1044,10 +1044,13 @@ _bfd_elf_parse_eh_frame (bfd *abfd, struct bfd_link_info *info,
-   goto success;
- 
-  free_no_table:
-+/* FIXME: Remove the microblaze specifics when relaxing gets fixed.  */
-+if (bfd_get_arch(abfd) != bfd_arch_microblaze) {
-   _bfd_error_handler
-     /* xgettext:c-format */
-     (_("error in %pB(%pA); no .eh_frame_hdr table will be created"),
-      abfd, sec);
-+}
-   hdr_info->u.dwarf.table = FALSE;
-   if (sec_info)
-     free (sec_info);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
new file mode 100644
index 0000000000..d5862d87b6
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0004-LOCAL-Fix-relaxation-of-assembler-resolved-reference.patch
@@ -0,0 +1,261 @@
+From e98a2f325e1a90dfd6911d124889f0760d663b5c Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 8 Nov 2016 11:54:08 +0530
+Subject: [PATCH 04/52] [LOCAL]: Fix relaxation of assembler resolved
+ references,Fixup debug_loc sections after linker relaxation Adds a new
+ reloctype R_MICROBLAZE_32_NONE, used for passing reloc info from the
+ assembler to the linker when the linker manages to fully resolve a local
+ symbol reference.
+
+This is a workaround for design flaws in the assembler to
+linker interface with regards to linker relaxation.
+
+Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+
+Conflicts:
+	bfd/elf32-microblaze.c
+	binutils/readelf.c
+	include/elf/microblaze.h
+---
+ bfd/bfd-in2.h              |   5 ++
+ bfd/elf32-microblaze.c     | 126 ++++++++++++++++++++++++++++---------
+ bfd/libbfd.h               |   1 +
+ bfd/reloc.c                |   6 ++
+ binutils/readelf.c         |   4 ++
+ gas/config/tc-microblaze.c |   4 ++
+ include/elf/microblaze.h   |   2 +
+ 7 files changed, 119 insertions(+), 29 deletions(-)
+
+Index: gdb-9.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-9.2.orig/bfd/bfd-in2.h
++++ gdb-9.2/bfd/bfd-in2.h
+@@ -5363,6 +5363,11 @@ value relative to the read-write small d
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).No relocation is 
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
+@@ -177,6 +177,20 @@ static reloc_howto_type microblaze_elf_h
+ 	  FALSE),		/* PC relative offset?  */
+ 
+    /* This reloc does nothing.	Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
+    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+ 	  3,			/* Size (0 = byte, 1 = short, 2 = long).  */
+@@ -562,7 +576,10 @@ microblaze_elf_reloc_type_lookup (bfd *
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64_NONE:
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
++     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+     case BFD_RELOC_32:
+@@ -1918,18 +1935,26 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		}
+ 	      break;
+ 	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
+ 	      {
+ 		/* This was a PC-relative instruction that was
+ 		   completely resolved.  */
+ 		int sfix, efix;
++                unsigned int val;
+ 		bfd_vma target_address;
+ 		target_address = irel->r_addend + irel->r_offset;
+ 		sfix = calc_fixup (irel->r_offset, 0, sec);
+ 		efix = calc_fixup (target_address, 0, sec);
+-		irel->r_addend -= (efix - sfix);
+-		/* Should use HOWTO.  */
+-		microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
+-						   irel->r_addend);
++
++                /* Validate the in-band val.  */
++                val = bfd_get_32 (abfd, contents + irel->r_offset);
++                if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++                }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
+ 	      }
+ 	      break;
+ 	    case R_MICROBLAZE_64_NONE:
+@@ -1973,30 +1998,73 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	  irelscanend = irelocs + o->reloc_count;
+ 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ 	    {
+-	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
+-		{
+-		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++              if (1 && ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++		      if (elf_section_data (o)->this_hdr.contents != NULL)
++		          ocontents = elf_section_data (o)->this_hdr.contents;
++		      else
++		        {
++		          /* We always cache the section contents.
++			     Perhaps, if info->keep_memory is FALSE, we
++			     should free them, if we are permitted to.  */
++
++		          if (o->rawsize == 0)
++			      o->rawsize = o->size;
++		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++		          if (ocontents == NULL)
++			      goto error_return;
++		          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++		          elf_section_data (o)->this_hdr.contents = ocontents;
++		        }
++		    }
+ 
+-		  /* Look at the reloc only if the value has been resolved.  */
+-		  if (isym->st_shndx == shndx
+-		      && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION))
+-		    {
+-		      if (ocontents == NULL)
+-			{
+-			  if (elf_section_data (o)->this_hdr.contents != NULL)
+-			    ocontents = elf_section_data (o)->this_hdr.contents;
+-			  else
+-			    {
+-			      /* We always cache the section contents.
+-				 Perhaps, if info->keep_memory is FALSE, we
+-				 should free them, if we are permitted to.  */
+-			      if (o->rawsize == 0)
+-				o->rawsize = o->size;
+-			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
+-			      if (ocontents == NULL)
+-				goto error_return;
+-			      if (!bfd_get_section_contents (abfd, o, ocontents,
+-							     (file_ptr) 0,
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++			fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++                {
++	          isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
++
++                  /* Look at the reloc only if the value has been resolved.  */
++                  if (isym->st_shndx == shndx
++                      && (ELF32_ST_TYPE (isym->st_info) == STT_SECTION))
++                    {
++                      if (ocontents == NULL)
++                        {
++                          if (elf_section_data (o)->this_hdr.contents != NULL)
++                            ocontents = elf_section_data (o)->this_hdr.contents;
++                          else
++                            {
++                              /* We always cache the section contents.
++                                 Perhaps, if info->keep_memory is FALSE, we
++                                 should free them, if we are permitted to.  */
++		              if (o->rawsize == 0)
++			        o->rawsize = o->size;
++                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                              if (ocontents == NULL)
++                                goto error_return;
++                              if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                             (file_ptr) 0,
+ 							     o->rawsize))
+ 				goto error_return;
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+@@ -2032,7 +2100,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+ 			    }
+ 			}
+-		      irelscan->r_addend -= calc_fixup (irel->r_addend
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ 							+ isym->st_value,
+ 							0,
+ 							sec);
+Index: gdb-9.2/bfd/libbfd.h
+===================================================================
+--- gdb-9.2.orig/bfd/libbfd.h
++++ gdb-9.2/bfd/libbfd.h
+@@ -2903,6 +2903,7 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+Index: gdb-9.2/bfd/reloc.c
+===================================================================
+--- gdb-9.2.orig/bfd/reloc.c
++++ gdb-9.2/bfd/reloc.c
+@@ -6807,6 +6807,12 @@ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
+ ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+Index: gdb-9.2/include/elf/microblaze.h
+===================================================================
+--- gdb-9.2.orig/include/elf/microblaze.h
++++ gdb-9.2/include/elf/microblaze.h
+@@ -61,6 +61,8 @@ START_RELOC_NUMBERS (elf_microblaze_relo
+   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
++  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++   
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch
deleted file mode 100644
index d851c589a5..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-Fix-relaxation-of-assembler-resolved-references.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 210bb23010e2c3e65f5f54c220d27da0590bab06 Mon Sep 17 00:00:00 2001
-From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
-Date: Tue, 14 Feb 2012 01:00:22 +0100
-Subject: [PATCH 05/40] Fix relaxation of assembler resolved references
-
----
- bfd/elf32-microblaze.c     | 41 ++++++++++++++++++++++++++++++++++++++
- 2 files changed, 42 insertions(+)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index c187d83ee04..dfd82438e35 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1973,6 +1973,47 @@ microblaze_elf_relax_section (bfd *abfd,
- 	  irelscanend = irelocs + o->reloc_count;
- 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- 	    {
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+                {
-+                  unsigned int val;
-+
-+                  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+
-+                  /* This was a PC-relative instruction that was completely resolved.  */
-+                  if (ocontents == NULL)
-+                    {
-+                      if (elf_section_data (o)->this_hdr.contents != NULL)
-+                          ocontents = elf_section_data (o)->this_hdr.contents;
-+                      else
-+                        {
-+                          /* We always cache the section contents.
-+                             Perhaps, if info->keep_memory is FALSE, we
-+                             should free them, if we are permitted to.  */
-+
-+                          if (o->rawsize == 0)
-+                              o->rawsize = o->size;
-+                          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+                          if (ocontents == NULL)
-+                              goto error_return;
-+                          if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                         (file_ptr) 0,
-+                                                         o->rawsize))
-+                              goto error_return;
-+                          elf_section_data (o)->this_hdr.contents = ocontents;
-+                        }
-+                    }
-+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+                  if (val != irelscan->r_addend) {
-+                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+                  }
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
-+                                                    + isym->st_value, 0, sec);
-+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                                     irelscan->r_addend);
-+              }
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
-+                  fprintf(stderr, "Unhandled NONE 64\n");
-+              }
- 	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- 		{
- 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
new file mode 100644
index 0000000000..d519530846
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0005-upstream-change-to-garbage-collection-sweep-causes-m.patch
@@ -0,0 +1,36 @@
+From c78337f4e6459e18e1d2af95d8e313b9dcb3f097 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Wed, 27 Feb 2013 13:56:11 +1000
+Subject: [PATCH 05/52] upstream change to garbage collection sweep causes mb
+ regression
+
+Upstream change for PR13177 now clears the def_regular during gc_sweep of a
+section. (All other archs in binutils/bfd/elf32-*.c received an update
+to a warning about unresolvable relocations - this warning is not present
+in binutils/bfd/elf32-microblaze.c, but this warning check would not
+prevent the error being seen)
+
+The visible issue with this change is when running a c++ application
+in Petalinux which links libstdc++.so for exception handling it segfaults
+on execution.
+
+This does not occur if static linking libstdc++.a, so its during the
+relocations for a shared lib with garbage collection this occurs
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ bfd/elflink.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+Index: gdb-9.2/bfd/elflink.c
+===================================================================
+--- gdb-9.2.orig/bfd/elflink.c
++++ gdb-9.2/bfd/elflink.c
+@@ -6274,7 +6274,6 @@ elf_gc_sweep_symbol (struct elf_link_has
+ 
+       inf = (struct elf_gc_sweep_symbol_info *) data;
+       (*inf->hide_symbol) (inf->info, h, TRUE);
+-      h->def_regular = 0;
+       h->ref_regular = 0;
+       h->ref_regular_nonweak = 0;
+     }
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fix-bug-in-TLSTPREL-Relocation.patch
new file mode 100644
index 0000000000..2843bc2d44
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-Fix-bug-in-TLSTPREL-Relocation.patch
@@ -0,0 +1,30 @@
+From 17ac5acd91e0ef6b103d18018f93fd0fc29a2048 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 15 Jun 2015 16:50:30 +0530
+Subject: [PATCH 06/52] Fix bug in TLSTPREL Relocation
+
+Fixed the problem related to the fixup/relocations TLSTPREL.
+When the fixup is applied the addend is not added at the correct offset
+of the instruction. The offset is hard coded considering its big endian
+and it fails for Little endian. This patch allows support for both
+big & little-endian compilers
+---
+ bfd/elf32-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
+@@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *ou
+ 	      relocation += addend;
+ 	      relocation -= dtprel_base(info);
+ 	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
+-			  contents + offset + 2);
++			  contents + offset + endian);
+ 	      bfd_put_16 (input_bfd, relocation & 0xffff,
+-			  contents + offset + 2 + INST_WORD_SIZE);
++			  contents + offset + endian + INST_WORD_SIZE);
+ 	      break;
+ 	    case (int) R_MICROBLAZE_TEXTREL_64:
+ 	    case (int) R_MICROBLAZE_TEXTREL_32_LO:
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
deleted file mode 100644
index eea290591f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0006-microblaze-Fixup-debug_loc-sections-after-linker-rel.patch
+++ /dev/null
@@ -1,184 +0,0 @@
-From d2aee40b9753b783853bf38d36d9b6e50d16cc20 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 6 Feb 2017 15:53:08 +0530
-Subject: [PATCH 06/40] microblaze: Fixup debug_loc sections after linker
- relaxation
-
-Adds a new reloctype R_MICROBLAZE_32_NONE, used for passing
-reloc info from the assembler to the linker when the linker
-manages to fully resolve a local symbol reference.
-
-This is a workaround for design flaws in the assembler to
-linker interface with regards to linker relaxation.
-
-Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com>
----
- bfd/bfd-in2.h              |  5 +++++
- bfd/elf32-microblaze.c     | 39 +++++++++++++++++++++++++++++++-------
- bfd/libbfd.h               |  1 +
- bfd/reloc.c                |  6 ++++++
- include/elf/microblaze.h   |  1 +
- 7 files changed, 52 insertions(+), 7 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 6f3e41da376..52c81b10b6d 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5363,6 +5363,11 @@ value relative to the read-write small data area anchor  */
- expressions of the form "Symbol Op Symbol"  */
-   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
- 
-+/* This is a 32 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imm instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_32_NONE,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index dfd82438e35..cbba704e691 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -176,6 +176,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  FALSE),		/* PC relative offset?  */
- 
-+   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
-+          0,         /* Rightshift.  */
-+          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,           /* Bitsize.  */
-+          TRUE,         /* PC_relative.  */
-+          0,           /* Bitpos.  */
-+          complain_overflow_bitfield,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_32_NONE",/* Name.  */
-+          FALSE,       /* Partial Inplace.  */
-+          0,          /* Source Mask.  */
-+          0,         /* Dest Mask.  */
-+          FALSE),       /* PC relative offset?  */
-+
-    /* This reloc does nothing.	Used for relaxation.  */
-    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -562,6 +576,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_NONE:
-       microblaze_reloc = R_MICROBLAZE_NONE;
-       break;
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-+      microblaze_reloc = R_MICROBLAZE_32_NONE;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_NONE:
-       microblaze_reloc = R_MICROBLAZE_64_NONE;
-       break;
-@@ -1918,14 +1935,22 @@ microblaze_elf_relax_section (bfd *abfd,
- 		}
- 	      break;
- 	    case R_MICROBLAZE_NONE:
-+	    case R_MICROBLAZE_32_NONE:
- 	      {
- 		/* This was a PC-relative instruction that was
- 		   completely resolved.  */
- 		int sfix, efix;
-+		unsigned int val;
- 		bfd_vma target_address;
- 		target_address = irel->r_addend + irel->r_offset;
- 		sfix = calc_fixup (irel->r_offset, 0, sec);
- 		efix = calc_fixup (target_address, 0, sec);
-+
-+		/* Validate the in-band val.  */
-+		val = bfd_get_32 (abfd, contents + irel->r_offset);
-+		if (val != irel->r_addend && ELF32_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+		       fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+		}
- 		irel->r_addend -= (efix - sfix);
- 		/* Should use HOWTO.  */
- 		microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-@@ -1973,12 +1998,16 @@ microblaze_elf_relax_section (bfd *abfd,
- 	  irelscanend = irelocs + o->reloc_count;
- 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
- 	    {
--              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_NONE)
-+              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
-                 {
-                   unsigned int val;
- 
-                   isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
- 
-+                  /* hax: We only do the following fixup for debug location lists.  */
-+                  if (strcmp(".debug_loc", o->name))
-+                    continue;
-+
-                   /* This was a PC-relative instruction that was completely resolved.  */
-                   if (ocontents == NULL)
-                     {
-@@ -2006,14 +2035,10 @@ microblaze_elf_relax_section (bfd *abfd,
-                   if (val != irelscan->r_addend) {
-                     fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-                   }
--                  irelscan->r_addend -= calc_fixup (irelscan->r_addend
--                                                    + isym->st_value, 0, sec);
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-                                                      irelscan->r_addend);
-               }
--              if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_NONE) {
--                  fprintf(stderr, "Unhandled NONE 64\n");
--              }
- 	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
- 		{
- 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-@@ -2073,7 +2098,7 @@ microblaze_elf_relax_section (bfd *abfd,
- 			      elf_section_data (o)->this_hdr.contents = ocontents;
- 			    }
- 			}
--		      irelscan->r_addend -= calc_fixup (irel->r_addend
-+                     irelscan->r_addend -= calc_fixup (irelscan->r_addend
- 							+ isym->st_value,
- 							0,
- 							sec);
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index 44cefbd66d4..a01891f3423 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2903,6 +2903,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_ROSDA",
-   "BFD_RELOC_MICROBLAZE_32_RWSDA",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-+  "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index b00b79f3190..78f13180c71 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6806,6 +6806,12 @@ ENUM
- ENUMDOC
-   This is a 32 bit reloc for the microblaze to handle
-   expressions of the form "Symbol Op Symbol"
-+ENUM
-+  BFD_RELOC_MICROBLAZE_32_NONE
-+ENUMDOC
-+  This is a 32 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imm instruction).  No relocation is
-+  done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
- ENUMDOC
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 830b5ad4461..0dba2c0f44f 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
-   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
-+  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
- 
- /* Global base address names.  */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-Added-Address-extension-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-Added-Address-extension-instructions.patch
new file mode 100644
index 0000000000..a2584ed412
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-Added-Address-extension-instructions.patch
@@ -0,0 +1,97 @@
+From 40107e7f6430aebfeba7e8f4eb6d67863520ebd4 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jan 2016 12:28:21 +0530
+Subject: [PATCH 07/52] Added Address extension instructions
+
+This patch adds the support of new instructions which are required
+for supporting Address extension feature.
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+ChangeLog:
+  2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
+
+  *microblaze-opc.h (op_code_struct): Update
+     Added new instructions
+  *microblaze-opcm.h (microblaze_instr): Update
+     Added new instructions
+---
+ opcodes/microblaze-opc.h  | 11 +++++++++++
+ opcodes/microblaze-opcm.h | 12 ++++++------
+ 2 files changed, 17 insertions(+), 6 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -178,8 +178,11 @@ struct op_code_struct
+   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ struct op_code_struct
+   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+@@ -405,6 +414,8 @@ struct op_code_struct
+   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
+   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
+   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
++  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
++  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+Index: gdb-9.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opcm.h
++++ gdb-9.2/opcodes/microblaze-opcm.h
+@@ -33,14 +33,14 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+-  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+-  shr, sw, swr, swx, lbui, lhui, lwi,
+-  sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
++  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
++  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   fint, fsqrt,
+   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
deleted file mode 100644
index 09a17eda09..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0007-upstream-change-to-garbage-collection-sweep-causes-m.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From df187bca3d19a3e5c36182929e7e14bc6a49aad5 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Wed, 27 Feb 2013 13:56:11 +1000
-Subject: [PATCH 07/40] upstream change to garbage collection sweep causes mb
- regression
-
-Upstream change for PR13177 now clears the def_regular during gc_sweep of a
-section. (All other archs in binutils/bfd/elf32-*.c received an update
-to a warning about unresolvable relocations - this warning is not present
-in binutils/bfd/elf32-microblaze.c, but this warning check would not
-prevent the error being seen)
-
-The visible issue with this change is when running a c++ application
-in Petalinux which links libstdc++.so for exception handling it segfaults
-on execution.
-
-This does not occur if static linking libstdc++.a, so its during the
-relocations for a shared lib with garbage collection this occurs
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- bfd/elflink.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/bfd/elflink.c b/bfd/elflink.c
-index 7078a2fb6f4..7926fdf63be 100644
---- a/bfd/elflink.c
-+++ b/bfd/elflink.c
-@@ -6274,7 +6274,6 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
- 
-       inf = (struct elf_gc_sweep_symbol_info *) data;
-       (*inf->hide_symbol) (inf->info, h, TRUE);
--      h->def_regular = 0;
-       h->ref_regular = 0;
-       h->ref_regular_nonweak = 0;
-     }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch
deleted file mode 100644
index c37a5aed64..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-Fix-bug-in-TLSTPREL-Relocation.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 0f1d7bd04916af6172780335dc6abc11d45564f2 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 15 Jun 2015 16:50:30 +0530
-Subject: [PATCH 08/40] Fix bug in TLSTPREL Relocation
-
-Fixed the problem related to the fixup/relocations TLSTPREL.
-When the fixup is applied the addend is not added at the correct offset
-of the instruction. The offset is hard coded considering its big endian
-and it fails for Little endian. This patch allows support for both
-big & little-endian compilers
----
- bfd/elf32-microblaze.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cbba704e691..cc4c0568c68 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1451,9 +1451,9 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 	      relocation += addend;
- 	      relocation -= dtprel_base(info);
- 	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
--			  contents + offset + 2);
-+			  contents + offset + endian);
- 	      bfd_put_16 (input_bfd, relocation & 0xffff,
--			  contents + offset + 2 + INST_WORD_SIZE);
-+			  contents + offset + endian + INST_WORD_SIZE);
- 	      break;
- 	    case (int) R_MICROBLAZE_TEXTREL_64:
- 	    case (int) R_MICROBLAZE_TEXTREL_32_LO:
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-fixing-the-MAX_OPCODES-to-correct-value.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
new file mode 100644
index 0000000000..ce2447a53e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0008-fixing-the-MAX_OPCODES-to-correct-value.patch
@@ -0,0 +1,22 @@
+From e8cd7c56c206c7a4582008d9059fe7a9ad35a44c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 28 Jan 2016 14:07:34 +0530
+Subject: [PATCH 08/52] fixing the MAX_OPCODES to correct value
+
+---
+ opcodes/microblaze-opc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -102,7 +102,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 291
++#define MAX_OPCODES 299
+ 
+ struct op_code_struct
+ {
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000000..155ef3b503
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Add-new-bit-field-instructions.patch
@@ -0,0 +1,144 @@
+From 01453aca6478379bef05095f64ed79509da3a5ca Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 18 Jul 2016 12:24:28 +0530
+Subject: [PATCH 09/52] Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged
+
+Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
+
+Conflicts:
+	opcodes/microblaze-dis.c
+---
+ gas/config/tc-microblaze.c | 71 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   | 20 +++++++++--
+ opcodes/microblaze-opc.h   | 12 ++++++-
+ opcodes/microblaze-opcm.h  |  6 +++-
+ 4 files changed, 104 insertions(+), 5 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-dis.c
++++ gdb-9.2/opcodes/microblaze-dis.c
+@@ -91,7 +91,19 @@ get_field_imm5_mbar (struct string_buf *
+ }
+ 
+ static char *
+-get_field_rfsl (struct string_buf *buf, long instr)
++get_field_imm5width (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++ else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
++static char *
++get_field_rfsl (struct string_buf *buf,long instr)
+ {
+   char *p = strbuf (buf);
+ 
+@@ -425,7 +437,11 @@ print_insn_microblaze (bfd_vma memaddr,
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
+-	  /* For tuqula instruction */
++        /* For bit field insns.  */
++	case INST_TYPE_RD_R1_IMM5_IMM5:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++	     break;
++	/* For tuqula instruction */
+ 	case INST_TYPE_RD:
+ 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
+ 	  break;
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar.  */
+ #define INST_TYPE_IMM5 20
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMM5_IMM5  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -89,7 +92,9 @@
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+ #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+@@ -102,7 +107,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 299
++#define MAX_OPCODES 301
+ 
+ struct op_code_struct
+ {
+@@ -159,6 +164,8 @@ struct op_code_struct
+   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+Index: gdb-9.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opcm.h
++++ gdb-9.2/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu,swapb,swaph,
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+-  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -129,6 +129,7 @@ enum microblaze_instr_type
+ #define RB_LOW  11 /* Low bit for RB.  */
+ #define IMM_LOW  0 /* Low bit for immediate.  */
+ #define IMM_MBAR 21 /* low bit for mbar instruction.  */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+ 
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -141,6 +142,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+ 
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch
deleted file mode 100644
index c9903a40be..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0009-Added-Address-extension-instructions.patch
+++ /dev/null
@@ -1,124 +0,0 @@
-From c0bb923f0978d5767048274cd778c8cbcef184ec Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 18 Jan 2016 12:28:21 +0530
-Subject: [PATCH 09/40] Added Address extension instructions
-
-This patch adds the support of new instructions which are required
-for supporting Address extension feature.
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
-
-ChangeLog:
-  2016-01-18 Nagaraju Mekala <nmekala@xilix.com>
-
-  *microblaze-opc.h (op_code_struct): Update
-     Added new instructions
-     Set MAX_OPCODES to matching value
-  *microblaze-opcm.h (microblaze_instr): Update
-     Added new instructions
----
- opcodes/microblaze-opc.h  | 19 +++++++++++++++----
- opcodes/microblaze-opcm.h | 12 ++++++------
- 2 files changed, 21 insertions(+), 10 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 865151f95b0..d9a84e575e8 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -102,7 +102,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 291
-+#define MAX_OPCODES 299
- 
- struct op_code_struct
- {
-@@ -178,8 +178,11 @@ struct op_code_struct
-   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
-   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
-   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
-+  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
-   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
-+  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
-   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
-+  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
-   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
-   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
-   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
-@@ -229,18 +232,24 @@ struct op_code_struct
-   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
-   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
-   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
-+  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
-   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
-   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
-+  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
-   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
-   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
-   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
-+  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
-   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
-   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
-+  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
-   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
-   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
-+  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
-   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
-   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
-   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
-+  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
-   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
-   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
-   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
-@@ -258,10 +267,10 @@ struct op_code_struct
-   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
-   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
-   {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
--  {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
-+  {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, mbi_fadd, arithmetic_inst },
-   {"frsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
--  {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
--  {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
-+  {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, mbi_fmul, arithmetic_inst },
-+  {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, mbi_fdiv, arithmetic_inst },
-   {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
-   {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
-   {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
-@@ -405,6 +414,8 @@ struct op_code_struct
-   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
-   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
-   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
-+  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
-+  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
-   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
-   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 42f3dd3be53..8be6e97a1d5 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -33,14 +33,14 @@ enum microblaze_instr
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
--  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
--  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-+  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
-+  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
-+  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
--  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
--  shr, sw, swr, swx, lbui, lhui, lwi,
--  sbi, shi, swi, msrset, msrclr, tuqula, fadd, frsub, fmul, fdiv,
-+  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
-+  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
-+  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
-   fint, fsqrt,
-   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch
deleted file mode 100644
index f94410d5bd..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-Add-new-bit-field-instructions.patch
+++ /dev/null
@@ -1,140 +0,0 @@
-From 32058fa03c18d710b3029108e967be687d00516c Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 18 Jul 2016 12:24:28 +0530
-Subject: [PATCH 10/40] Add new bit-field instructions
-
-This patches adds new bsefi and bsifi instructions.
-BSEFI- The instruction shall extract a bit field from a
-register and place it right-adjusted in the destination register.
-The other bits in the destination register shall be set to zero
-BSIFI- The instruction shall insert a right-adjusted bit field
-from a register at another position in the destination register.
-The rest of the bits in the destination register shall be unchanged
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- opcodes/microblaze-dis.c   | 17 +++++++++
- opcodes/microblaze-opc.h   | 12 ++++++-
- opcodes/microblaze-opcm.h  |  6 +++-
- 4 files changed, 103 insertions(+), 3 deletions(-)
-
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 2b3aa8e0786..356f1da22ed 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -90,6 +90,18 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
-   return p;
- }
- 
-+static char *
-+get_field_imm5width (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  if (instr & 0x00004000)
-+    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+ else
-+    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+  return p;
-+}
-+
- static char *
- get_field_rfsl (struct string_buf *buf, long instr)
- {
-@@ -426,6 +438,11 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	case INST_TYPE_NONE:
- 	  break;
- 	  /* For tuqula instruction */
-+        /* For bit field insns.  */
-+	case INST_TYPE_RD_R1_IMM5_IMM5:
-+	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
-+	  break;
-+	/* For tuqula instruction */
- 	case INST_TYPE_RD:
- 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
- 	  break;
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index d9a84e575e8..d3b234e1fcd 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -59,6 +59,9 @@
- /* For mbar.  */
- #define INST_TYPE_IMM5 20
- 
-+/* For bsefi and bsifi */
-+#define INST_TYPE_RD_R1_IMM5_IMM5  21
-+
- #define INST_TYPE_NONE 25
- 
- 
-@@ -89,7 +92,9 @@
- #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
- #define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
-+#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
-+#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
- #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
-@@ -102,7 +107,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 299
-+#define MAX_OPCODES 301
- 
- struct op_code_struct
- {
-@@ -159,6 +164,8 @@ struct op_code_struct
-   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
-   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
-   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
-+  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
-   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
-   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -438,5 +445,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5  ((int) 0x00000000)
- #define MAX_IMM5  ((int) 0x0000001f)
- 
-+#define MIN_IMM_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM_WIDTH  ((int) 0x00000020)
-+
- #endif /* MICROBLAZE_OPC */
- 
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index 8be6e97a1d5..c3b2b8f0f6e 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -29,7 +29,7 @@ enum microblaze_instr
-   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
-   mulh, mulhu, mulhsu,swapb,swaph,
-   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
--  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
-+  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
-   /* 'or/and/xor' are C++ keywords.  */
-   microblaze_or, microblaze_and, microblaze_xor,
-   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
-@@ -129,6 +129,7 @@ enum microblaze_instr_type
- #define RB_LOW  11 /* Low bit for RB.  */
- #define IMM_LOW  0 /* Low bit for immediate.  */
- #define IMM_MBAR 21 /* low bit for mbar instruction.  */
-+#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
- 
- #define RD_MASK 0x03E00000
- #define RA_MASK 0x001F0000
-@@ -141,6 +142,9 @@ enum microblaze_instr_type
- /* Imm mask for mbar.  */
- #define IMM5_MBAR_MASK 0x03E00000
- 
-+/* Imm mask for extract/insert width. */
-+#define IMM5_WIDTH_MASK 0x000007C0
-+
- /* FSL imm mask for get, put instructions.  */
- #define  RFSL_MASK 0x000000F
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-fixing-the-imm-bug.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-fixing-the-imm-bug.patch
new file mode 100644
index 0000000000..201dfeb1c3
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0010-fixing-the-imm-bug.patch
@@ -0,0 +1,24 @@
+From b2dc3bfabd4d80be7d90502e3d2dc26b508679cb Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Mon, 10 Jul 2017 16:07:28 +0530
+Subject: [PATCH 10/52] fixing the imm bug. with relax option imm -1 is also
+ getting removed this is corrected now.
+
+---
+ bfd/elf32-microblaze.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
+@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd,
+       else
+ 	symval += irel->r_addend;
+ 
+-      if ((symval & 0xffff8000) == 0
+-	  || (symval & 0xffff8000) == 0xffff8000)
++      if ((symval & 0xffff8000) == 0)
+ 	{
+ 	  /* We can delete this instruction.  */
+ 	  sec->relax[sec->relax_count].addr = irel->r_offset;
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch
deleted file mode 100644
index 3f3c81415a..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0011-fixing-the-imm-bug.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 121b64d9dafd3119925a7e95a09fa9f388e53922 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Mon, 10 Jul 2017 16:07:28 +0530
-Subject: [PATCH 11/40] fixing the imm bug.
-
-with relax option imm -1 is also getting removed this is corrected now.
----
- bfd/elf32-microblaze.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cc4c0568c68..cb7271f5017 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -1869,8 +1869,7 @@ microblaze_elf_relax_section (bfd *abfd,
-       else
- 	symval += irel->r_addend;
- 
--      if ((symval & 0xffff8000) == 0
--	  || (symval & 0xffff8000) == 0xffff8000)
-+      if ((symval & 0xffff8000) == 0)
- 	{
- 	  /* We can delete this instruction.  */
- 	  sec->relax[sec->relax_count].addr = irel->r_offset;
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0014-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0014-intial-commit-of-MB-64-bit.patch
new file mode 100644
index 0000000000..a2a80d53c5
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0014-intial-commit-of-MB-64-bit.patch
@@ -0,0 +1,4277 @@
+From b6f02b2535c4051db5fdadbf03dbb88438b5d116 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:28:28 +0530
+Subject: [PATCH 14/52] intial commit of MB 64-bit
+
+Conflicts:
+	bfd/configure
+	bfd/configure.ac
+	bfd/cpu-microblaze.c
+	ld/Makefile.am
+	ld/Makefile.in
+	opcodes/microblaze-dis.c
+---
+ bfd/Makefile.am                    |    2 +
+ bfd/Makefile.in                    |    3 +
+ bfd/config.bfd                     |    4 +
+ bfd/configure                      |    2 +
+ bfd/configure.ac                   |    2 +
+ bfd/cpu-microblaze.c               |   53 +-
+ bfd/elf64-microblaze.c             | 3610 ++++++++++++++++++++++++++++
+ bfd/targets.c                      |    6 +
+ gas/config/tc-microblaze.c         |  274 ++-
+ gas/config/tc-microblaze.h         |    4 +-
+ include/elf/common.h               |    1 +
+ ld/Makefile.am                     |    4 +
+ ld/Makefile.in                     |    6 +
+ ld/configure.tgt                   |    3 +
+ ld/emulparams/elf64microblaze.sh   |   23 +
+ ld/emulparams/elf64microblazeel.sh |   23 +
+ opcodes/microblaze-dis.c           |   35 +-
+ opcodes/microblaze-opc.h           |  162 +-
+ opcodes/microblaze-opcm.h          |   20 +-
+ 19 files changed, 4197 insertions(+), 40 deletions(-)
+ create mode 100644 bfd/elf64-microblaze.c
+ create mode 100644 ld/emulparams/elf64microblaze.sh
+ create mode 100644 ld/emulparams/elf64microblazeel.sh
+
+Index: gdb-9.2/bfd/Makefile.am
+===================================================================
+--- gdb-9.2.orig/bfd/Makefile.am
++++ gdb-9.2/bfd/Makefile.am
+@@ -568,6 +568,7 @@ BFD64_BACKENDS = \
+ 	elf64-riscv.lo \
+ 	elfxx-riscv.lo \
+ 	elf64-s390.lo \
++	elf64-microblaze.lo \
+ 	elf64-sparc.lo \
+ 	elf64-tilegx.lo \
+ 	elf64-x86-64.lo \
+@@ -602,6 +603,7 @@ BFD64_BACKENDS_CFILES = \
+ 	elf64-nfp.c \
+ 	elf64-ppc.c \
+ 	elf64-s390.c \
++	elf64-microblaze.c \
+ 	elf64-sparc.c \
+ 	elf64-tilegx.c \
+ 	elf64-x86-64.c \
+Index: gdb-9.2/bfd/Makefile.in
+===================================================================
+--- gdb-9.2.orig/bfd/Makefile.in
++++ gdb-9.2/bfd/Makefile.in
+@@ -994,6 +994,7 @@ BFD64_BACKENDS = \
+ 	elf64-riscv.lo \
+ 	elfxx-riscv.lo \
+ 	elf64-s390.lo \
++	elf64-microblaze.lo \
+ 	elf64-sparc.lo \
+ 	elf64-tilegx.lo \
+ 	elf64-x86-64.lo \
+@@ -1028,6 +1029,7 @@ BFD64_BACKENDS_CFILES = \
+ 	elf64-nfp.c \
+ 	elf64-ppc.c \
+ 	elf64-s390.c \
++	elf64-microblaze.c \
+ 	elf64-sparc.c \
+ 	elf64-tilegx.c \
+ 	elf64-x86-64.c \
+@@ -1510,6 +1512,7 @@ distclean-compile:
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ppc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-riscv.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-s390.Plo@am__quote@
++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-sparc.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-tilegx.Plo@am__quote@
+ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-x86-64.Plo@am__quote@
+Index: gdb-9.2/bfd/config.bfd
+===================================================================
+--- gdb-9.2.orig/bfd/config.bfd
++++ gdb-9.2/bfd/config.bfd
+@@ -842,11 +842,15 @@ case "${targ}" in
+   microblazeel*-*)
+     targ_defvec=microblaze_elf32_le_vec
+     targ_selvecs=microblaze_elf32_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+   microblaze*-*)
+     targ_defvec=microblaze_elf32_vec
+     targ_selvecs=microblaze_elf32_le_vec
++    targ64_selvecs=microblaze_elf64_vec
++    targ64_selvecs=microblaze_elf64_le_vec
+     ;;
+ 
+ #ifdef BFD64
+Index: gdb-9.2/bfd/configure
+===================================================================
+--- gdb-9.2.orig/bfd/configure
++++ gdb-9.2/bfd/configure
+@@ -14879,6 +14879,8 @@ do
+     s390_elf64_vec)		 tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
++    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     sh_coff_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_le_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_small_vec)		 tb="$tb coff-sh.lo $coff" ;;
+Index: gdb-9.2/bfd/configure.ac
+===================================================================
+--- gdb-9.2.orig/bfd/configure.ac
++++ gdb-9.2/bfd/configure.ac
+@@ -615,6 +615,8 @@ do
+     s390_elf64_vec)		 tb="$tb elf64-s390.lo elf64.lo $elf"; target_size=64 ;;
+     score_elf32_be_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
+     score_elf32_le_vec)		 tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64 ;;
++    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
++    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
+     sh_coff_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_le_vec)		 tb="$tb coff-sh.lo $coff" ;;
+     sh_coff_small_vec)		 tb="$tb coff-sh.lo $coff" ;;
+Index: gdb-9.2/bfd/cpu-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/cpu-microblaze.c
++++ gdb-9.2/bfd/cpu-microblaze.c
+@@ -23,7 +23,24 @@
+ #include "bfd.h"
+ #include "libbfd.h"
+ 
+-const bfd_arch_info_type bfd_microblaze_arch =
++const bfd_arch_info_type bfd_microblaze_arch[] =
++{
++#if BFD_DEFAULT_TARGET_SIZE == 64
++{
++  64,		  		/* 32 bits in a word.  */
++  64,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  FALSE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  &bfd_microblaze_arch[1]  	/* Next in list.  */
++},
+ {
+   32,				/* Bits in a word.  */
+   32,				/* Bits in an address.  */
+@@ -39,4 +56,38 @@ const bfd_arch_info_type bfd_microblaze_
+   bfd_arch_default_fill,	/* Default fill.  */
+   NULL,				/* Next in list.  */
+   0 /* Maximum offset of a reloc from the start of an insn.  */
++}
++#else
++{
++  32,		  		/* 32 bits in a word.  */
++  32,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  TRUE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  &bfd_microblaze_arch[1]   	/* Next in list.  */
++},
++{
++  64,		  		/* 32 bits in a word.  */
++  64,		  		/* 32 bits in an address.  */
++  8,		  		/* 8 bits in a byte.  */
++  bfd_arch_microblaze, 		/* Architecture.  */
++  0,		  		/* Machine number - 0 for now.  */
++  "microblaze",	  		/* Architecture name.  */
++  "MicroBlaze",	  		/* Printable name.  */
++  3,		  		/* Section align power.  */
++  FALSE,		  		/* Is this the default architecture ?  */
++  bfd_default_compatible,	/* Architecture comparison function.  */
++  bfd_default_scan,	   	/* String to architecture conversion.  */
++  bfd_arch_default_fill,	/* Default fill.  */
++  NULL,			  	/* Next in list.  */
++  0  /* Maximum offset of a reloc from the start of an insn.  */
++}
++#endif
+ };
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- /dev/null
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -0,0 +1,3610 @@
++/* Xilinx MicroBlaze-specific support for 32-bit ELF
++
++   Copyright (C) 2009-2016 Free Software Foundation, Inc.
++
++   This file is part of BFD, the Binary File Descriptor library.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program; if not, write to the
++   Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
++   Boston, MA 02110-1301, USA.  */
++
++
++int dbg1 = 0;
++
++#include "sysdep.h"
++#include "bfd.h"
++#include "bfdlink.h"
++#include "libbfd.h"
++#include "elf-bfd.h"
++#include "elf/microblaze.h"
++#include <assert.h>
++
++#define	USE_RELA	/* Only USE_REL is actually significant, but this is
++			   here are a reminder...  */
++#define INST_WORD_SIZE 4
++
++static int ro_small_data_pointer = 0;
++static int rw_small_data_pointer = 0;
++
++static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
++
++static reloc_howto_type microblaze_elf_howto_raw[] =
++{
++   /* This reloc does nothing.  */
++   HOWTO (R_MICROBLAZE_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          0,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_NONE", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
++   /* A standard 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A standard PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_PCREL",   	/* Name.  */
++          TRUE,			/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit PCREL relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_64_PCREL,/* Type.  */
++          0,			/* Rightshift.  */
++          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          64,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_64_PCREL", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* The low half of a PCREL 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_PCREL_LO,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_signed, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_32_PCREL_LO", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit relocation.  Table entry not really used.  */
++   HOWTO (R_MICROBLAZE_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* The low half of a 32 bit relocation.  */
++   HOWTO (R_MICROBLAZE_32_LO,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_signed, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_LO", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Read-only small data section relocation.  */
++   HOWTO (R_MICROBLAZE_SRO32,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_SRO32", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Read-write small data area relocation.  */
++   HOWTO (R_MICROBLAZE_SRW32,   /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_SRW32", /* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
++          0,         /* Rightshift.  */
++          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
++          32,           /* Bitsize.  */
++          TRUE,         /* PC_relative.  */
++          0,           /* Bitpos.  */
++          complain_overflow_bitfield,  /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_32_NONE",/* Name.  */
++          FALSE,       /* Partial Inplace.  */
++          0,          /* Source Mask.  */
++          0,         /* Dest Mask.  */
++          FALSE),       /* PC relative offset?  */
++
++   /* This reloc does nothing.  Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
++          0,			/* Rightshift.  */
++          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          0,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_64_NONE",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0,			/* Dest Mask.  */
++          FALSE),		/* PC relative offset?  */
++
++   /* Symbol Op Symbol relocation.  */
++   HOWTO (R_MICROBLAZE_32_SYM_OP_SYM,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          32,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_bitfield, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_32_SYM_OP_SYM",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0xffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable hierarchy.  */
++   HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type.  */
++          0,                     /* Rightshift.  */
++          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
++          0,                     /* Bitsize.  */
++          FALSE,                 /* PC_relative.  */
++          0,                     /* Bitpos.  */
++          complain_overflow_dont,/* Complain on overflow.  */
++          NULL,                  /* Special Function.  */
++          "R_MICROBLAZE_GNU_VTINHERIT", /* Name.  */
++          FALSE,                 /* Partial Inplace.  */
++          0,                     /* Source Mask.  */
++          0,                     /* Dest Mask.  */
++          FALSE),                /* PC relative offset?  */
++
++   /* GNU extension to record C++ vtable member usage.  */
++   HOWTO (R_MICROBLAZE_GNU_VTENTRY,   /* Type.  */
++          0,                     /* Rightshift.  */
++          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
++          0,                     /* Bitsize.  */
++          FALSE,                 /* PC_relative.  */
++          0,                     /* Bitpos.  */
++          complain_overflow_dont,/* Complain on overflow.  */
++          _bfd_elf_rel_vtable_reloc_fn,  /* Special Function.  */
++          "R_MICROBLAZE_GNU_VTENTRY", /* Name.  */
++          FALSE,                 /* Partial Inplace.  */
++          0,                     /* Source Mask.  */
++          0,                     /* Dest Mask.  */
++          FALSE),                /* PC relative offset?  */
++
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GOTPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit GOT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GOT_64",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A 64 bit PLT relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_PLT_64,  /* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_PLT_64",/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_REL,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_REL", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_JUMP_SLOT", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /*  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GLOB_DAT", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_GOTOFF_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* A 32 bit GOT relative relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GOTOFF_32,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GOTOFF_32", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* COPY relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_COPY,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          FALSE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_COPY", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
++   /* Marker relocs for TLS.  */
++   HOWTO (R_MICROBLAZE_TLS,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc,	/* special_function */
++	 "R_MICROBLAZE_TLS",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,			/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSGD,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSGD",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,			/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   HOWTO (R_MICROBLAZE_TLSLD,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSLD",		/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes the load module index of the load module that contains the
++      definition of its TLS sym.  */
++   HOWTO (R_MICROBLAZE_TLSDTPMOD32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPMOD32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  Used for initializing GOT */
++   HOWTO (R_MICROBLAZE_TLSDTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a dtv-relative displacement, the difference between the value
++      of sym+add and the base address of the thread-local storage block that
++      contains the definition of sym, minus 0x8000.  */
++   HOWTO (R_MICROBLAZE_TLSDTPREL64,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSDTPREL64",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSGOTTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++   /* Computes a tp-relative displacement, the difference between the value of
++      sym+add and the value of the thread pointer (r13).  */
++   HOWTO (R_MICROBLAZE_TLSTPREL32,
++	 0,			/* rightshift */
++	 2,			/* size (0 = byte, 1 = short, 2 = long) */
++	 32,			/* bitsize */
++	 FALSE,			/* pc_relative */
++	 0,			/* bitpos */
++	 complain_overflow_dont, /* complain_on_overflow */
++	 bfd_elf_generic_reloc, /* special_function */
++	 "R_MICROBLAZE_TLSTPREL32",	/* name */
++	 FALSE,			/* partial_inplace */
++	 0,			/* src_mask */
++	 0x0000ffff,		/* dst_mask */
++	 FALSE),		/* pcrel_offset */
++
++};
++
++#ifndef NUM_ELEM
++#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
++#endif
++
++/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done.  */
++
++static void
++microblaze_elf_howto_init (void)
++{
++  unsigned int i;
++
++  for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
++    {
++      unsigned int type;
++
++      type = microblaze_elf_howto_raw[i].type;
++
++      BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
++
++      microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
++    }
++}
++
++static reloc_howto_type *
++microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
++				  bfd_reloc_code_real_type code)
++{
++  enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
++
++  switch (code)
++    {
++    case BFD_RELOC_NONE:
++      microblaze_reloc = R_MICROBLAZE_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_NONE:
++      microblaze_reloc = R_MICROBLAZE_64_NONE;
++      break;
++    case BFD_RELOC_32:
++      microblaze_reloc = R_MICROBLAZE_32;
++      break;
++      /* RVA is treated the same as 32 */
++    case BFD_RELOC_RVA:
++      microblaze_reloc = R_MICROBLAZE_32;
++      break;
++    case BFD_RELOC_32_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL;
++      break;
++    case BFD_RELOC_64_PCREL:
++      microblaze_reloc = R_MICROBLAZE_64_PCREL;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
++      microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
++      break;
++    case BFD_RELOC_64:
++      microblaze_reloc = R_MICROBLAZE_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_LO:
++      microblaze_reloc = R_MICROBLAZE_32_LO;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_ROSDA:
++      microblaze_reloc = R_MICROBLAZE_SRO32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_RWSDA:
++      microblaze_reloc = R_MICROBLAZE_SRW32;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
++      microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
++      break;
++    case BFD_RELOC_VTABLE_INHERIT:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
++      break;
++    case BFD_RELOC_VTABLE_ENTRY:
++      microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTPC:
++      microblaze_reloc = R_MICROBLAZE_GOTPC_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOT:
++      microblaze_reloc = R_MICROBLAZE_GOT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_PLT:
++      microblaze_reloc = R_MICROBLAZE_PLT_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_GOTOFF:
++      microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGD:
++      microblaze_reloc = R_MICROBLAZE_TLSGD;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSLD:
++      microblaze_reloc = R_MICROBLAZE_TLSLD;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
++      break;
++    case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
++      microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
++      microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
++      break;
++    case BFD_RELOC_MICROBLAZE_COPY:
++      microblaze_reloc = R_MICROBLAZE_COPY;
++      break;
++    default:
++      return (reloc_howto_type *) NULL;
++    }
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  return microblaze_elf_howto_table [(int) microblaze_reloc];
++};
++
++static reloc_howto_type *
++microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
++				  const char *r_name)
++{
++  unsigned int i;
++
++  for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
++    if (microblaze_elf_howto_raw[i].name != NULL
++	&& strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
++      return &microblaze_elf_howto_raw[i];
++
++  return NULL;
++}
++
++/* Set the howto pointer for a RCE ELF reloc.  */
++
++static bfd_boolean
++microblaze_elf_info_to_howto (bfd * abfd,
++			      arelent * cache_ptr,
++			      Elf_Internal_Rela * dst)
++{
++  unsigned int r_type;
++
++  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
++    /* Initialize howto table if needed.  */
++    microblaze_elf_howto_init ();
++
++  r_type = ELF64_R_TYPE (dst->r_info);
++  if (r_type >= R_MICROBLAZE_max)
++    {
++      /* xgettext:c-format */
++      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
++			  abfd, r_type);
++      bfd_set_error (bfd_error_bad_value);
++      return FALSE;
++    }
++
++  cache_ptr->howto = microblaze_elf_howto_table [r_type];
++  return TRUE;
++}
++
++/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
++
++static bfd_boolean
++microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
++{
++  if (name[0] == 'L' && name[1] == '.')
++    return TRUE;
++
++  if (name[0] == '$' && name[1] == 'L')
++    return TRUE;
++
++  /* With gcc, the labels go back to starting with '.', so we accept
++     the generic ELF local label syntax as well.  */
++  return _bfd_elf_is_local_label_name (abfd, name);
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf64_mb_dyn_relocs
++{
++  struct elf64_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
++/* ELF linker hash entry.  */
++
++struct elf64_mb_link_hash_entry
++{
++  struct elf_link_hash_entry elf;
++
++  /* Track dynamic relocs copied for this symbol.  */
++  struct elf64_mb_dyn_relocs *dyn_relocs;
++
++  /* TLS Reference Types for the symbol; Updated by check_relocs */
++#define TLS_GD     1  /* GD reloc. */
++#define TLS_LD     2  /* LD reloc. */
++#define TLS_TPREL  4  /* TPREL reloc, => IE. */
++#define TLS_DTPREL 8  /* DTPREL reloc, => LD. */
++#define TLS_TLS    16 /* Any TLS reloc.  */
++  unsigned char tls_mask;
++
++};
++
++#define IS_TLS_GD(x)     (x == (TLS_TLS | TLS_GD))
++#define IS_TLS_LD(x)     (x == (TLS_TLS | TLS_LD))
++#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
++#define IS_TLS_NONE(x)   (x == 0)
++
++#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
++
++/* ELF linker hash table.  */
++
++struct elf64_mb_link_hash_table
++{
++  struct elf_link_hash_table elf;
++
++  /* Short-cuts to get to dynamic linker sections.  */
++  asection *sgot;
++  asection *sgotplt;
++  asection *srelgot;
++  asection *splt;
++  asection *srelplt;
++  asection *sdynbss;
++  asection *srelbss;
++
++  /* Small local sym to section mapping cache.  */
++  struct sym_cache sym_sec;
++
++  /* TLS Local Dynamic GOT Entry */
++  union {
++    bfd_signed_vma refcount;
++    bfd_vma offset;
++  } tlsld_got;
++};
++
++/* Nonzero if this section has TLS related relocations.  */
++#define has_tls_reloc sec_flg0
++
++/* Get the ELF linker hash table from a link_info structure.  */
++
++#define elf64_mb_hash_table(p)				\
++  (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
++  == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL)
++
++/* Create an entry in a microblaze ELF linker hash table.  */
++
++static struct bfd_hash_entry *
++link_hash_newfunc (struct bfd_hash_entry *entry,
++		   struct bfd_hash_table *table,
++		   const char *string)
++{
++  /* Allocate the structure if it has not already been allocated by a
++     subclass.  */
++  if (entry == NULL)
++    {
++      entry = bfd_hash_allocate (table,
++				 sizeof (struct elf64_mb_link_hash_entry));
++      if (entry == NULL)
++	return entry;
++    }
++
++  /* Call the allocation method of the superclass.  */
++  entry = _bfd_elf_link_hash_newfunc (entry, table, string);
++  if (entry != NULL)
++    {
++      struct elf64_mb_link_hash_entry *eh;
++
++      eh = (struct elf64_mb_link_hash_entry *) entry;
++      eh->tls_mask = 0;
++    }
++
++  return entry;
++}
++
++/* Create a mb ELF linker hash table.  */
++
++static struct bfd_link_hash_table *
++microblaze_elf_link_hash_table_create (bfd *abfd)
++{
++  struct elf64_mb_link_hash_table *ret;
++  size_t amt = sizeof (struct elf64_mb_link_hash_table);
++
++  ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
++  if (ret == NULL)
++    return NULL;
++
++  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
++				      sizeof (struct elf64_mb_link_hash_entry),
++				      MICROBLAZE_ELF_DATA))
++    {
++      free (ret);
++      return NULL;
++    }
++
++  return &ret->elf.root;
++}
++
++/* Set the values of the small data pointers.  */
++
++static void
++microblaze_elf_final_sdp (struct bfd_link_info *info)
++{
++  struct bfd_link_hash_entry *h;
++
++  h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    ro_small_data_pointer = (h->u.def.value
++                             + h->u.def.section->output_section->vma
++                             + h->u.def.section->output_offset);
++
++  h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
++  if (h != (struct bfd_link_hash_entry *) NULL
++      && h->type == bfd_link_hash_defined)
++    rw_small_data_pointer = (h->u.def.value
++                             + h->u.def.section->output_section->vma
++                             + h->u.def.section->output_offset);
++}
++
++static bfd_vma
++dtprel_base (struct bfd_link_info *info)
++{
++  /* If tls_sec is NULL, we should have signalled an error already.  */
++  if (elf_hash_table (info)->tls_sec == NULL)
++    return 0;
++  return elf_hash_table (info)->tls_sec->vma;
++}
++
++/* The size of the thread control block.  */
++#define TCB_SIZE	8
++
++/* Output a simple dynamic relocation into SRELOC.  */
++
++static void
++microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
++					  asection *sreloc,
++					  unsigned long reloc_index,
++					  unsigned long indx,
++					  int r_type,
++					  bfd_vma offset,
++					  bfd_vma addend)
++{
++
++  Elf_Internal_Rela rel;
++
++  rel.r_info = ELF64_R_INFO (indx, r_type);
++  rel.r_offset = offset;
++  rel.r_addend = addend;
++
++  bfd_elf64_swap_reloca_out (output_bfd, &rel,
++              (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
++}
++
++/* This code is taken from elf64-m32r.c
++   There is some attempt to make this function usable for many architectures,
++   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
++   if only to serve as a learning tool.
++
++   The RELOCATE_SECTION function is called by the new ELF backend linker
++   to handle the relocations for a section.
++
++   The relocs are always passed as Rela structures; if the section
++   actually uses Rel structures, the r_addend field will always be
++   zero.
++
++   This function is responsible for adjust the section contents as
++   necessary, and (if using Rela relocs and generating a
++   relocatable output file) adjusting the reloc addend as
++   necessary.
++
++   This function does not have to worry about setting the reloc
++   address or the reloc symbol index.
++
++   LOCAL_SYMS is a pointer to the swapped in local symbols.
++
++   LOCAL_SECTIONS is an array giving the section in the input file
++   corresponding to the st_shndx field of each local symbol.
++
++   The global hash table entry for the global symbols can be found
++   via elf_sym_hashes (input_bfd).
++
++   When generating relocatable output, this function must handle
++   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
++   going to be the section symbol corresponding to the output
++   section, which means that the addend must be adjusted
++   accordingly.  */
++
++static bfd_boolean
++microblaze_elf_relocate_section (bfd *output_bfd,
++			         struct bfd_link_info *info,
++			         bfd *input_bfd,
++			         asection *input_section,
++			         bfd_byte *contents,
++			         Elf_Internal_Rela *relocs,
++			         Elf_Internal_Sym *local_syms,
++			         asection **local_sections)
++{
++  struct elf64_mb_link_hash_table *htab;
++  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
++  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
++  Elf_Internal_Rela *rel, *relend;
++  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
++  /* Assume success.  */
++  bfd_boolean ret = TRUE;
++  asection *sreloc;
++  bfd_vma *local_got_offsets;
++  unsigned int tls_type;
++
++  if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
++    microblaze_elf_howto_init ();
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  local_got_offsets = elf_local_got_offsets (input_bfd);
++
++  sreloc = elf_section_data (input_section)->sreloc;
++
++  rel = relocs;
++  relend = relocs + input_section->reloc_count;
++  for (; rel < relend; rel++)
++    {
++      int r_type;
++      reloc_howto_type *howto;
++      unsigned long r_symndx;
++      bfd_vma addend = rel->r_addend;
++      bfd_vma offset = rel->r_offset;
++      struct elf_link_hash_entry *h;
++      Elf_Internal_Sym *sym;
++      asection *sec;
++      const char *sym_name;
++      bfd_reloc_status_type r = bfd_reloc_ok;
++      const char *errmsg = NULL;
++      bfd_boolean unresolved_reloc = FALSE;
++
++      h = NULL;
++      r_type = ELF64_R_TYPE (rel->r_info);
++      tls_type = 0;
++
++      if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
++	{
++	  (*_bfd_error_handler) (_("%s: unknown relocation type %d"),
++				 bfd_get_filename (input_bfd), (int) r_type);
++	  bfd_set_error (bfd_error_bad_value);
++	  ret = FALSE;
++	  continue;
++	}
++
++      howto = microblaze_elf_howto_table[r_type];
++      r_symndx = ELF64_R_SYM (rel->r_info);
++
++      if (bfd_link_relocatable (info))
++	{
++	  /* This is a relocatable link.  We don't have to change
++	     anything, unless the reloc is against a section symbol,
++	     in which case we have to adjust according to where the
++	     section symbol winds up in the output section.  */
++	  sec = NULL;
++	  if (r_symndx >= symtab_hdr->sh_info)
++	    /* External symbol.  */
++	    continue;
++
++	  /* Local symbol.  */
++	  sym = local_syms + r_symndx;
++	  sym_name = "<local symbol>";
++	  /* STT_SECTION: symbol is associated with a section.  */
++	  if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
++	    /* Symbol isn't associated with a section.  Nothing to do.  */
++	    continue;
++
++	  sec = local_sections[r_symndx];
++	  addend += sec->output_offset + sym->st_value;
++#ifndef USE_REL
++	  /* This can't be done for USE_REL because it doesn't mean anything
++	     and elf_link_input_bfd asserts this stays zero.  */
++	  /* rel->r_addend = addend; */
++#endif
++
++#ifndef USE_REL
++	  /* Addends are stored with relocs.  We're done.  */
++	  continue;
++#else /* USE_REL */
++	  /* If partial_inplace, we need to store any additional addend
++	     back in the section.  */
++	  if (!howto->partial_inplace)
++	    continue;
++	  /* ??? Here is a nice place to call a special_function like handler.  */
++	  r = _bfd_relocate_contents (howto, input_bfd, addend,
++				      contents + offset);
++#endif /* USE_REL */
++	}
++      else
++	{
++	  bfd_vma relocation;
++	  bfd_boolean resolved_to_zero;
++
++	  /* This is a final link.  */
++	  sym = NULL;
++	  sec = NULL;
++	  unresolved_reloc = FALSE;
++
++	  if (r_symndx < symtab_hdr->sh_info)
++	    {
++	      /* Local symbol.  */
++	      sym = local_syms + r_symndx;
++	      sec = local_sections[r_symndx];
++	      if (sec == 0)
++		continue;
++	      sym_name = "<local symbol>";
++	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
++	      /* r_addend may have changed if the reference section was
++		 a merge section.  */
++	      addend = rel->r_addend;
++	    }
++	  else
++	    {
++	      /* External symbol.  */
++	      bfd_boolean warned ATTRIBUTE_UNUSED;
++	      bfd_boolean ignored ATTRIBUTE_UNUSED;
++
++	      RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
++				       r_symndx, symtab_hdr, sym_hashes,
++				       h, sec, relocation,
++				       unresolved_reloc, warned, ignored);
++	      sym_name = h->root.root.string;
++	    }
++
++	  /* Sanity check the address.  */
++	  if (offset > bfd_get_section_limit (input_bfd, input_section))
++	    {
++	      r = bfd_reloc_outofrange;
++	      goto check_reloc;
++	    }
++
++	  resolved_to_zero = (h != NULL
++			      && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
++
++	  switch ((int) r_type)
++	    {
++	    case (int) R_MICROBLAZE_SRO32 :
++	      {
++		const char *name;
++
++		/* Only relocate if the symbol is defined.  */
++		if (sec)
++		  {
++		    name = bfd_section_name (sec);
++
++		    if (strcmp (name, ".sdata2") == 0
++			|| strcmp (name, ".sbss2") == 0)
++		      {
++			if (ro_small_data_pointer == 0)
++			  microblaze_elf_final_sdp (info);
++			if (ro_small_data_pointer == 0)
++			  {
++			    ret = FALSE;
++			    r = bfd_reloc_undefined;
++			    goto check_reloc;
++			  }
++
++			/* At this point `relocation' contains the object's
++			   address.  */
++			relocation -= ro_small_data_pointer;
++			/* Now it contains the offset from _SDA2_BASE_.  */
++			r = _bfd_final_link_relocate (howto, input_bfd,
++						      input_section,
++						      contents, offset,
++						      relocation, addend);
++		      }
++		    else
++		      {
++			_bfd_error_handler
++			  /* xgettext:c-format */
++			  (_("%pB: the target (%s) of an %s relocation"
++			     " is in the wrong section (%pA)"),
++			   input_bfd,
++			   sym_name,
++			   microblaze_elf_howto_table[(int) r_type]->name,
++			   sec);
++			/*bfd_set_error (bfd_error_bad_value); ??? why? */
++			ret = FALSE;
++			continue;
++		      }
++		  }
++	      }
++	      break;
++
++	    case (int) R_MICROBLAZE_SRW32 :
++	      {
++		const char *name;
++
++		/* Only relocate if the symbol is defined.  */
++		if (sec)
++		  {
++		    name = bfd_section_name (sec);
++
++		    if (strcmp (name, ".sdata") == 0
++			|| strcmp (name, ".sbss") == 0)
++		      {
++			if (rw_small_data_pointer == 0)
++			  microblaze_elf_final_sdp (info);
++			if (rw_small_data_pointer == 0)
++			  {
++			    ret = FALSE;
++			    r = bfd_reloc_undefined;
++			    goto check_reloc;
++			  }
++
++			/* At this point `relocation' contains the object's
++			   address.  */
++			relocation -= rw_small_data_pointer;
++			/* Now it contains the offset from _SDA_BASE_.  */
++			r = _bfd_final_link_relocate (howto, input_bfd,
++						      input_section,
++						      contents, offset,
++						      relocation, addend);
++		      }
++		    else
++		      {
++			_bfd_error_handler
++			  /* xgettext:c-format */
++			  (_("%pB: the target (%s) of an %s relocation"
++			     " is in the wrong section (%pA)"),
++			   input_bfd,
++			   sym_name,
++			   microblaze_elf_howto_table[(int) r_type]->name,
++			   sec);
++			/*bfd_set_error (bfd_error_bad_value); ??? why? */
++			ret = FALSE;
++			continue;
++		      }
++		  }
++	      }
++	      break;
++
++	    case (int) R_MICROBLAZE_32_SYM_OP_SYM:
++	      break; /* Do nothing.  */
++
++	    case (int) R_MICROBLAZE_GOTPC_64:
++	      relocation = htab->sgotplt->output_section->vma
++		+ htab->sgotplt->output_offset;
++	      relocation -= (input_section->output_section->vma
++			     + input_section->output_offset
++			     + offset + INST_WORD_SIZE);
++	      relocation += addend;
++	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++	                  contents + offset + endian);
++	      bfd_put_16 (input_bfd, relocation & 0xffff,
++	                  contents + offset + endian + INST_WORD_SIZE);
++	      break;
++
++	    case (int) R_MICROBLAZE_PLT_64:
++	      {
++		bfd_vma immediate;
++		if (htab->splt != NULL && h != NULL
++		    && h->plt.offset != (bfd_vma) -1)
++		  {
++		    relocation = (htab->splt->output_section->vma
++				  + htab->splt->output_offset
++				  + h->plt.offset);
++		    unresolved_reloc = FALSE;
++		    immediate = relocation - (input_section->output_section->vma
++					      + input_section->output_offset
++					      + offset + INST_WORD_SIZE);
++		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++		                contents + offset + endian);
++		    bfd_put_16 (input_bfd, immediate & 0xffff,
++		                contents + offset + endian + INST_WORD_SIZE);
++		  }
++		else
++		  {
++		    relocation -= (input_section->output_section->vma
++				   + input_section->output_offset
++				   + offset + INST_WORD_SIZE);
++		    immediate = relocation;
++		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
++		                contents + offset + endian);
++		    bfd_put_16 (input_bfd, immediate & 0xffff,
++		                contents + offset + endian + INST_WORD_SIZE);
++		  }
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_TLSGD:
++	      tls_type = (TLS_TLS | TLS_GD);
++	      goto dogot;
++	    case (int) R_MICROBLAZE_TLSLD:
++	      tls_type = (TLS_TLS | TLS_LD);
++	    dogot:
++	    case (int) R_MICROBLAZE_GOT_64:
++	      {
++		bfd_vma *offp;
++		bfd_vma off, off2;
++		unsigned long indx;
++		bfd_vma static_value;
++
++		bfd_boolean need_relocs = FALSE;
++		if (htab->sgot == NULL)
++		  abort ();
++
++		indx = 0;
++		offp = NULL;
++
++		/* 1. Identify GOT Offset;
++		   2. Compute Static Values
++		   3. Process Module Id, Process Offset
++		   4. Fixup Relocation with GOT offset value. */
++
++		/* 1. Determine GOT Offset to use : TLS_LD, global, local */
++		if (IS_TLS_LD (tls_type))
++		  offp = &htab->tlsld_got.offset;
++		else if (h != NULL)
++		  {
++		    if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1)
++			offp = &h->got.offset;
++		    else
++			abort ();
++		  }
++		else
++		  {
++		    if (local_got_offsets == NULL)
++		      abort ();
++		    offp = &local_got_offsets[r_symndx];
++		  }
++
++		if (!offp)
++		  abort ();
++
++		off = (*offp) & ~1;
++		off2 = off;
++
++		if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
++		  off2 = off + 4;
++
++		/* Symbol index to use for relocs */
++		if (h != NULL)
++		  {
++		    bfd_boolean dyn =
++			elf_hash_table (info)->dynamic_sections_created;
++
++		    if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
++							 bfd_link_pic (info),
++							 h)
++			&& (!bfd_link_pic (info)
++			    || !SYMBOL_REFERENCES_LOCAL (info, h)))
++		      indx = h->dynindx;
++		  }
++
++		/* Need to generate relocs ? */
++		if ((bfd_link_pic (info) || indx != 0)
++		    && (h == NULL
++		    || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++			&& !resolved_to_zero)
++		    || h->root.type != bfd_link_hash_undefweak))
++		  need_relocs = TRUE;
++
++		/* 2. Compute/Emit Static value of r-expression */
++		static_value = relocation + addend;
++
++		/* 3. Process module-id and offset */
++		if (! ((*offp) & 1) )
++		  {
++		    bfd_vma got_offset;
++
++		    got_offset = (htab->sgot->output_section->vma
++				  + htab->sgot->output_offset
++				  + off);
++
++		    /* Process module-id */
++		    if (IS_TLS_LD(tls_type))
++		      {
++			if (! bfd_link_pic (info))
++			  {
++			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++			  }
++			else
++			  {
++			    microblaze_elf_output_dynamic_relocation (output_bfd,
++			      htab->srelgot, htab->srelgot->reloc_count++,
++			      /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
++			      got_offset, 0);
++			  }
++		      }
++		    else if (IS_TLS_GD(tls_type))
++		      {
++		        if (! need_relocs)
++			  {
++			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
++			  }
++		        else
++			  {
++			    microblaze_elf_output_dynamic_relocation (output_bfd,
++			      htab->srelgot,
++			      htab->srelgot->reloc_count++,
++			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
++			      got_offset, indx ? 0 : static_value);
++			  }
++		      }
++
++		    /* Process Offset */
++		    if (htab->srelgot == NULL)
++		      abort ();
++
++		    got_offset = (htab->sgot->output_section->vma
++				  + htab->sgot->output_offset
++				  + off2);
++		    if (IS_TLS_LD(tls_type))
++		      {
++		        /* For LD, offset should be 0 */
++		        *offp |= 1;
++		        bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2);
++		      }
++		    else if (IS_TLS_GD(tls_type))
++		      {
++			*offp |= 1;
++			static_value -= dtprel_base(info);
++			if (need_relocs)
++			  microblaze_elf_output_dynamic_relocation
++			    (output_bfd,
++			     htab->elf.srelgot,
++			     htab->elf.srelgot->reloc_count++,
++			     /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
++			     got_offset, indx ? 0 : static_value);
++			else
++			  bfd_put_32 (output_bfd, static_value,
++				      htab->elf.sgot->contents + off2);
++		      }
++		    else
++		      {
++			bfd_put_32 (output_bfd, static_value,
++				    htab->elf.sgot->contents + off2);
++
++			/* Relocs for dyn symbols generated by
++			   finish_dynamic_symbols */
++			if (bfd_link_pic (info) && h == NULL)
++			  {
++			    *offp |= 1;
++			    microblaze_elf_output_dynamic_relocation
++			      (output_bfd,
++			       htab->elf.srelgot,
++			       htab->elf.srelgot->reloc_count++,
++			       /* symindex= */ indx, R_MICROBLAZE_REL,
++			       got_offset, static_value);
++			  }
++		      }
++		  }
++
++		/* 4. Fixup Relocation with GOT offset value
++		      Compute relative address of GOT entry for applying
++		      the current relocation */
++		relocation = htab->elf.sgot->output_section->vma
++			     + htab->elf.sgot->output_offset
++			     + off
++			     - htab->elf.sgotplt->output_section->vma
++			     - htab->elf.sgotplt->output_offset;
++
++		/* Apply Current Relocation */
++		bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++		            contents + offset + endian);
++		bfd_put_16 (input_bfd, relocation & 0xffff,
++		            contents + offset + endian + INST_WORD_SIZE);
++
++		unresolved_reloc = FALSE;
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_GOTOFF_64:
++	      {
++		bfd_vma immediate;
++		unsigned short lo, high;
++		relocation += addend;
++		relocation -= (htab->elf.sgotplt->output_section->vma
++			       + htab->elf.sgotplt->output_offset);
++		/* Write this value into correct location.  */
++		immediate = relocation;
++		lo = immediate & 0x0000ffff;
++		high = (immediate >> 16) & 0x0000ffff;
++		bfd_put_16 (input_bfd, high, contents + offset + endian);
++		bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian);
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_GOTOFF_32:
++	      {
++		relocation += addend;
++		relocation -= (htab->elf.sgotplt->output_section->vma
++			       + htab->elf.sgotplt->output_offset);
++		/* Write this value into correct location.  */
++		bfd_put_32 (input_bfd, relocation, contents + offset);
++		break;
++	      }
++
++	    case (int) R_MICROBLAZE_TLSDTPREL64:
++	      relocation += addend;
++	      relocation -= dtprel_base(info);
++	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			  contents + offset + endian);
++	      bfd_put_16 (input_bfd, relocation & 0xffff,
++			  contents + offset + endian + INST_WORD_SIZE);
++	      break;
++	    case (int) R_MICROBLAZE_64_PCREL :
++	    case (int) R_MICROBLAZE_64:
++	    case (int) R_MICROBLAZE_32:
++	      {
++		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
++		   from removed linkonce sections, or sections discarded by
++		   a linker script.  */
++		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
++		  {
++		    relocation += addend;
++		    if (r_type == R_MICROBLAZE_32)
++		      bfd_put_32 (input_bfd, relocation, contents + offset);
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_64_PCREL)
++			  relocation -= (input_section->output_section->vma
++					 + input_section->output_offset
++					 + offset + INST_WORD_SIZE);
++			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			            contents + offset + endian);
++			bfd_put_16 (input_bfd, relocation & 0xffff,
++			            contents + offset + endian + INST_WORD_SIZE);
++		      }
++		    break;
++		  }
++
++		if ((bfd_link_pic (info)
++		     && (h == NULL
++			 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++			     && !resolved_to_zero)
++			 || h->root.type != bfd_link_hash_undefweak)
++		     && (!howto->pc_relative
++			 || (h != NULL
++			     && h->dynindx != -1
++			     && (!info->symbolic
++				 || !h->def_regular))))
++		    || (!bfd_link_pic (info)
++			&& h != NULL
++			&& h->dynindx != -1
++			&& !h->non_got_ref
++			&& ((h->def_dynamic
++			     && !h->def_regular)
++			    || h->root.type == bfd_link_hash_undefweak
++			    || h->root.type == bfd_link_hash_undefined)))
++		  {
++		    Elf_Internal_Rela outrel;
++		    bfd_byte *loc;
++		    bfd_boolean skip;
++
++		    /* When generating a shared object, these relocations
++		       are copied into the output file to be resolved at run
++		       time.  */
++
++		    BFD_ASSERT (sreloc != NULL);
++
++		    skip = FALSE;
++
++		    outrel.r_offset =
++		      _bfd_elf_section_offset (output_bfd, info, input_section,
++					       rel->r_offset);
++		    if (outrel.r_offset == (bfd_vma) -1)
++		      skip = TRUE;
++		    else if (outrel.r_offset == (bfd_vma) -2)
++		      skip = TRUE;
++		    outrel.r_offset += (input_section->output_section->vma
++					+ input_section->output_offset);
++
++		    if (skip)
++		      memset (&outrel, 0, sizeof outrel);
++		    /* h->dynindx may be -1 if the symbol was marked to
++		       become local.  */
++		    else if (h != NULL
++			     && ((! info->symbolic && h->dynindx != -1)
++				 || !h->def_regular))
++		      {
++			BFD_ASSERT (h->dynindx != -1);
++			outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
++			outrel.r_addend = addend;
++		      }
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_32)
++			  {
++			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
++			    outrel.r_addend = relocation + addend;
++			  }
++			else
++			  {
++			    BFD_FAIL ();
++			    (*_bfd_error_handler)
++			      (_("%B: probably compiled without -fPIC?"),
++			       input_bfd);
++			    bfd_set_error (bfd_error_bad_value);
++			    return FALSE;
++			  }
++		      }
++
++		    loc = sreloc->contents;
++		    loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
++		    bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
++		    break;
++		  }
++		else
++		  {
++		    relocation += addend;
++		    if (r_type == R_MICROBLAZE_32)
++		      bfd_put_32 (input_bfd, relocation, contents + offset);
++		    else
++		      {
++			if (r_type == R_MICROBLAZE_64_PCREL)
++			  relocation -= (input_section->output_section->vma
++					 + input_section->output_offset
++					 + offset + INST_WORD_SIZE);
++			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			            contents + offset + endian);
++			bfd_put_16 (input_bfd, relocation & 0xffff,
++			            contents + offset + endian + INST_WORD_SIZE);
++		      }
++		    break;
++		  }
++	      }
++
++	    default :
++	      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
++					    contents, offset,
++					    relocation, addend);
++	      break;
++	    }
++	}
++
++    check_reloc:
++
++      if (r != bfd_reloc_ok)
++	{
++	  /* FIXME: This should be generic enough to go in a utility.  */
++	  const char *name;
++
++	  if (h != NULL)
++	    name = h->root.root.string;
++	  else
++	    {
++	      name = (bfd_elf_string_from_elf_section
++		      (input_bfd, symtab_hdr->sh_link, sym->st_name));
++	      if (name == NULL || *name == '\0')
++		name = bfd_section_name (sec);
++	    }
++
++	  if (errmsg != NULL)
++	    goto common_error;
++
++	  switch (r)
++	    {
++	    case bfd_reloc_overflow:
++	      (*info->callbacks->reloc_overflow)
++		(info, (h ? &h->root : NULL), name, howto->name,
++		 (bfd_vma) 0, input_bfd, input_section, offset);
++	      break;
++
++	    case bfd_reloc_undefined:
++	      (*info->callbacks->undefined_symbol)
++		(info, name, input_bfd, input_section, offset, TRUE);
++	      break;
++
++	    case bfd_reloc_outofrange:
++	      errmsg = _("internal error: out of range error");
++	      goto common_error;
++
++	    case bfd_reloc_notsupported:
++	      errmsg = _("internal error: unsupported relocation error");
++	      goto common_error;
++
++	    case bfd_reloc_dangerous:
++	      errmsg = _("internal error: dangerous error");
++	      goto common_error;
++
++	    default:
++	      errmsg = _("internal error: unknown error");
++	      /* Fall through.  */
++	    common_error:
++	      (*info->callbacks->warning) (info, errmsg, name, input_bfd,
++					   input_section, offset);
++	      break;
++	    }
++	}
++    }
++
++  return ret;
++}
++
++/* Merge backend specific data from an object file to the output
++   object file when linking.
++
++   Note: We only use this hook to catch endian mismatches.  */
++static bfd_boolean
++microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
++{
++  /* Check if we have the same endianess.  */
++  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
++    return FALSE;
++
++  return TRUE;
++}
++
++
++/* Calculate fixup value for reference.  */
++
++static int
++calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
++{
++  bfd_vma end = start + size;
++  int i, fixup = 0;
++
++  if (sec == NULL || sec->relax == NULL)
++    return 0;
++
++  /* Look for addr in relax table, total fixup value.  */
++  for (i = 0; i < sec->relax_count; i++)
++    {
++      if (end <= sec->relax[i].addr)
++        break;
++      if ((end != start) && (start > sec->relax[i].addr))
++        continue;
++      fixup += sec->relax[i].size;
++    }
++  return fixup;
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   a 32-bit instruction.  */
++static void
++microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr = bfd_get_32 (abfd, bfd_addr);
++    instr &= ~0x0000ffff;
++    instr |= (val & 0x0000ffff);
++    bfd_put_32 (abfd, instr, bfd_addr);
++}
++
++/* Read-modify-write into the bfd, an immediate value into appropriate fields of
++   two consecutive 32-bit instructions.  */
++static void
++microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
++{
++    unsigned long instr_hi;
++    unsigned long instr_lo;
++
++    instr_hi = bfd_get_32 (abfd, bfd_addr);
++    instr_hi &= ~0x0000ffff;
++    instr_hi |= ((val >> 16) & 0x0000ffff);
++    bfd_put_32 (abfd, instr_hi, bfd_addr);
++
++    instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
++    instr_lo &= ~0x0000ffff;
++    instr_lo |= (val & 0x0000ffff);
++    bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
++}
++
++static bfd_boolean
++microblaze_elf_relax_section (bfd *abfd,
++			      asection *sec,
++			      struct bfd_link_info *link_info,
++			      bfd_boolean *again)
++{
++  Elf_Internal_Shdr *symtab_hdr;
++  Elf_Internal_Rela *internal_relocs;
++  Elf_Internal_Rela *free_relocs = NULL;
++  Elf_Internal_Rela *irel, *irelend;
++  bfd_byte *contents = NULL;
++  bfd_byte *free_contents = NULL;
++  int rel_count;
++  unsigned int shndx;
++  int i, sym_index;
++  asection *o;
++  struct elf_link_hash_entry *sym_hash;
++  Elf_Internal_Sym *isymbuf, *isymend;
++  Elf_Internal_Sym *isym;
++  int symcount;
++  int offset;
++  bfd_vma src, dest;
++
++  /* We only do this once per section.  We may be able to delete some code
++     by running multiple passes, but it is not worth it.  */
++  *again = FALSE;
++
++  /* Only do this for a text section.  */
++  if (bfd_link_relocatable (link_info)
++      || (sec->flags & SEC_RELOC) == 0
++      || (sec->reloc_count == 0)
++      || (sec->flags & SEC_CODE) == 0)
++    return TRUE;
++
++  BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
++
++  /* If this is the first time we have been called for this section,
++     initialize the cooked size.  */
++  if (sec->size == 0)
++    sec->size = sec->rawsize;
++
++  /* Get symbols for this section.  */
++  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
++  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
++  symcount =  symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (isymbuf == NULL)
++    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
++ 			     	    0, NULL, NULL, NULL);
++  BFD_ASSERT (isymbuf != NULL);
++
++  internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
++  if (internal_relocs == NULL)
++    goto error_return;
++  if (! link_info->keep_memory)
++    free_relocs = internal_relocs;
++
++  sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
++						  * sizeof (struct relax_table));
++  if (sec->relax == NULL)
++    goto error_return;
++  sec->relax_count = 0;
++
++  irelend = internal_relocs + sec->reloc_count;
++  rel_count = 0;
++  for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++    {
++      bfd_vma symval;
++      if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
++	  && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ))
++	continue; /* Can't delete this reloc.  */
++
++      /* Get the section contents.  */
++      if (contents == NULL)
++	{
++	  if (elf_section_data (sec)->this_hdr.contents != NULL)
++	    contents = elf_section_data (sec)->this_hdr.contents;
++	  else
++	    {
++	      contents = (bfd_byte *) bfd_malloc (sec->size);
++	      if (contents == NULL)
++		goto error_return;
++	      free_contents = contents;
++
++	      if (!bfd_get_section_contents (abfd, sec, contents,
++					     (file_ptr) 0, sec->size))
++		goto error_return;
++              elf_section_data (sec)->this_hdr.contents = contents;
++	    }
++	}
++
++      /* Get the value of the symbol referred to by the reloc.  */
++      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++	{
++	  /* A local symbol.  */
++	  asection *sym_sec;
++
++	  isym = isymbuf + ELF64_R_SYM (irel->r_info);
++          if (isym->st_shndx == SHN_UNDEF)
++	    sym_sec = bfd_und_section_ptr;
++	  else if (isym->st_shndx == SHN_ABS)
++	    sym_sec = bfd_abs_section_ptr;
++	  else if (isym->st_shndx == SHN_COMMON)
++	    sym_sec = bfd_com_section_ptr;
++	  else
++	    sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
++
++	  symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
++	}
++      else
++	{
++	  unsigned long indx;
++	  struct elf_link_hash_entry *h;
++
++	  indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
++	  h = elf_sym_hashes (abfd)[indx];
++	  BFD_ASSERT (h != NULL);
++
++          if (h->root.type != bfd_link_hash_defined
++	      && h->root.type != bfd_link_hash_defweak)
++	    /* This appears to be a reference to an undefined
++	       symbol.  Just ignore it--it will be caught by the
++	       regular reloc processing.  */
++	    continue;
++
++	  symval = (h->root.u.def.value
++		    + h->root.u.def.section->output_section->vma
++		    + h->root.u.def.section->output_offset);
++	}
++
++      /* If this is a PC-relative reloc, subtract the instr offset from
++         the symbol value.  */
++      if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
++	{
++	  symval = symval + irel->r_addend
++	    - (irel->r_offset
++	       + sec->output_section->vma
++	       + sec->output_offset);
++        }
++      else
++	symval += irel->r_addend;
++
++      if ((symval & 0xffff8000) == 0)
++	{
++          /* We can delete this instruction.  */
++	  sec->relax[sec->relax_count].addr = irel->r_offset;
++	  sec->relax[sec->relax_count].size = INST_WORD_SIZE;
++	  sec->relax_count++;
++
++	  /* Rewrite relocation type.  */
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++	    {
++	    case R_MICROBLAZE_64_PCREL:
++	      irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_PCREL_LO);
++	      break;
++	    case R_MICROBLAZE_64:
++              irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
++                                           (int) R_MICROBLAZE_32_LO);
++	      break;
++	    default:
++	      /* Cannot happen.  */
++	      BFD_ASSERT (FALSE);
++            }
++        }
++    } /* Loop through all relocations.  */
++
++  /* Loop through the relocs again, and see if anything needs to change.  */
++  if (sec->relax_count > 0)
++    {
++      shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
++      rel_count = 0;
++      sec->relax[sec->relax_count].addr = sec->size;
++
++      for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
++        {
++	  bfd_vma nraddr;
++
++          /* Get the new reloc address.  */
++	  nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
++          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
++	    {
++	    default:
++	      break;
++	    case R_MICROBLAZE_64_PCREL:
++	      break;
++	    case R_MICROBLAZE_64:
++	    case R_MICROBLAZE_32_LO:
++	      /* If this reloc is against a symbol defined in this
++	         section, we must check the addend to see it will put the value in
++	         range to be adjusted, and hence must be changed.  */
++	      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
++	        {
++		  isym = isymbuf + ELF64_R_SYM (irel->r_info);
++		  /* Only handle relocs against .text.  */
++		  if (isym->st_shndx == shndx
++		      && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
++		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
++	        }
++	      break;
++	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
++	    case R_MICROBLAZE_64_NONE:
++	      {
++	        /* This was a PC-relative 64-bit instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++	        bfd_vma target_address;
++		target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
++		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
++		efix = calc_fixup (target_address, 0, sec);
++		irel->r_addend -= (efix - sfix);
++    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
++                                       + INST_WORD_SIZE, irel->r_addend);
++	      }
++	      break;
++	    }
++          irel->r_offset = nraddr;
++        } /* Change all relocs in this section.  */
++
++      /* Look through all other sections.  */
++      for (o = abfd->sections; o != NULL; o = o->next)
++        {
++          Elf_Internal_Rela *irelocs;
++          Elf_Internal_Rela *irelscan, *irelscanend;
++          bfd_byte *ocontents;
++
++          if (o == sec
++              || (o->flags & SEC_RELOC) == 0
++              || o->reloc_count == 0)
++            continue;
++
++          /* We always cache the relocs.  Perhaps, if info->keep_memory is
++             FALSE, we should free them, if we are permitted to.  */
++
++          irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE);
++          if (irelocs == NULL)
++            goto error_return;
++
++          ocontents = NULL;
++          irelscanend = irelocs + o->reloc_count;
++          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
++            {
++              if (1 && ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
++                {
++                  unsigned int val;
++
++                  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* hax: We only do the following fixup for debug location lists.  */
++                  if (strcmp(".debug_loc", o->name))
++                    continue;
++
++                  /* This was a PC-relative instruction that was completely resolved.  */
++                  if (ocontents == NULL)
++                    {
++		      if (elf_section_data (o)->this_hdr.contents != NULL)
++		          ocontents = elf_section_data (o)->this_hdr.contents;
++		      else
++		        {
++		          /* We always cache the section contents.
++			     Perhaps, if info->keep_memory is FALSE, we
++			     should free them, if we are permitted to.  */
++
++		          if (o->rawsize == 0)
++			      o->rawsize = o->size;
++		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++		          if (ocontents == NULL)
++			      goto error_return;
++		          if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                         (file_ptr) 0,
++                                                         o->rawsize))
++                              goto error_return;
++		          elf_section_data (o)->this_hdr.contents = ocontents;
++		        }
++		    }
++
++                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++                  if (val != irelscan->r_addend) {
++                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
++                  }
++                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                                     irelscan->r_addend);
++              }
++              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++                {
++	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++                  /* Look at the reloc only if the value has been resolved.  */
++                  if (isym->st_shndx == shndx
++                      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++                    {
++                      if (ocontents == NULL)
++                        {
++                          if (elf_section_data (o)->this_hdr.contents != NULL)
++                            ocontents = elf_section_data (o)->this_hdr.contents;
++                          else
++                            {
++                              /* We always cache the section contents.
++                                 Perhaps, if info->keep_memory is FALSE, we
++                                 should free them, if we are permitted to.  */
++		              if (o->rawsize == 0)
++			        o->rawsize = o->size;
++                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++                              if (ocontents == NULL)
++                                goto error_return;
++                              if (!bfd_get_section_contents (abfd, o, ocontents,
++                                                             (file_ptr) 0,
++							     o->rawsize))
++                                goto error_return;
++                              elf_section_data (o)->this_hdr.contents = ocontents;
++                            }
++
++                        }
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
++                    }
++		  else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
++		    {
++		      isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		      /* Look at the reloc only if the value has been resolved.  */
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++              irelscan->r_addend -= calc_fixup (irelscan->r_addend
++							+ isym->st_value,
++							0,
++							sec);
++		    }
++		}
++	      else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
++		       || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO))
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++		      bfd_vma target_address;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++
++		      unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
++		      immediate = instr & 0x0000ffff;
++		      target_address = immediate;
++		      offset = calc_fixup (target_address, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
++                                             irelscan->r_addend);
++		    }
++		}
++
++	      if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64)
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++          immediate = (instr_hi & 0x0000ffff) << 16;
++          immediate |= (instr_lo & 0x0000ffff);
++		      offset = calc_fixup (irelscan->r_addend, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++		    }
++		}
++	      else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
++		{
++		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
++
++		  /* Look at the reloc only if the value has been resolved.  */
++		  if (isym->st_shndx == shndx
++		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
++		    {
++		      bfd_vma immediate;
++		      bfd_vma target_address;
++
++		      if (ocontents == NULL)
++			{
++			  if (elf_section_data (o)->this_hdr.contents != NULL)
++			    ocontents = elf_section_data (o)->this_hdr.contents;
++			  else
++			    {
++			      /* We always cache the section contents.
++				 Perhaps, if info->keep_memory is FALSE, we
++				 should free them, if we are permitted to.  */
++			      if (o->rawsize == 0)
++				o->rawsize = o->size;
++			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
++			      if (ocontents == NULL)
++				goto error_return;
++			      if (!bfd_get_section_contents (abfd, o, ocontents,
++							     (file_ptr) 0,
++							     o->rawsize))
++				goto error_return;
++			      elf_section_data (o)->this_hdr.contents = ocontents;
++			    }
++			}
++          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset);
++          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
++                                                + irelscan->r_offset
++                                                + INST_WORD_SIZE);
++          immediate = (instr_hi & 0x0000ffff) << 16;
++          immediate |= (instr_lo & 0x0000ffff);
++		      target_address = immediate;
++		      offset = calc_fixup (target_address, 0, sec);
++		      immediate -= offset;
++		      irelscan->r_addend -= offset;
++          microblaze_bfd_write_imm_value_64 (abfd, ocontents
++                                             + irelscan->r_offset, immediate);
++		    }
++		}
++            }
++        }
++
++      /* Adjust the local symbols defined in this section.  */
++      isymend = isymbuf + symtab_hdr->sh_info;
++      for (isym = isymbuf; isym < isymend; isym++)
++        {
++          if (isym->st_shndx == shndx)
++            {
++              isym->st_value -= calc_fixup (isym->st_value, 0, sec);
++              if (isym->st_size)
++                isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
++            }
++        }
++
++      /* Now adjust the global symbols defined in this section.  */
++      isym = isymbuf + symtab_hdr->sh_info;
++      symcount =  (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
++      for (sym_index = 0; sym_index < symcount; sym_index++)
++        {
++          sym_hash = elf_sym_hashes (abfd)[sym_index];
++          if ((sym_hash->root.type == bfd_link_hash_defined
++                  || sym_hash->root.type == bfd_link_hash_defweak)
++              && sym_hash->root.u.def.section == sec)
++            {
++              sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
++                                                        0, sec);
++              if (sym_hash->size)
++                sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
++                                              sym_hash->size, sec);
++            }
++        }
++
++      /* Physically move the code and change the cooked size.  */
++      dest = sec->relax[0].addr;
++      for (i = 0; i < sec->relax_count; i++)
++        {
++          int len;
++          src = sec->relax[i].addr + sec->relax[i].size;
++          len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size;
++
++          memmove (contents + dest, contents + src, len);
++          sec->size -= sec->relax[i].size;
++          dest += len;
++        }
++
++      elf_section_data (sec)->relocs = internal_relocs;
++      free_relocs = NULL;
++
++      elf_section_data (sec)->this_hdr.contents = contents;
++      free_contents = NULL;
++
++      symtab_hdr->contents = (bfd_byte *) isymbuf;
++    }
++
++  if (free_relocs != NULL)
++    {
++      free (free_relocs);
++      free_relocs = NULL;
++    }
++
++  if (free_contents != NULL)
++    {
++      if (!link_info->keep_memory)
++	free (free_contents);
++      else
++	/* Cache the section contents for elf_link_input_bfd.  */
++	elf_section_data (sec)->this_hdr.contents = contents;
++      free_contents = NULL;
++    }
++
++  if (sec->relax_count == 0)
++    {
++      *again = FALSE;
++      free (sec->relax);
++      sec->relax = NULL;
++    }
++  else
++    *again = TRUE;
++  return TRUE;
++
++ error_return:
++  if (free_relocs != NULL)
++    free (free_relocs);
++  if (free_contents != NULL)
++    free (free_contents);
++  if (sec->relax != NULL)
++    {
++      free (sec->relax);
++      sec->relax = NULL;
++      sec->relax_count = 0;
++    }
++  return FALSE;
++}
++
++/* Return the section that should be marked against GC for a given
++   relocation.  */
++
++static asection *
++microblaze_elf_gc_mark_hook (asection *sec,
++			     struct bfd_link_info * info,
++     			     Elf_Internal_Rela * rel,
++     			     struct elf_link_hash_entry * h,
++     			     Elf_Internal_Sym * sym)
++{
++  if (h != NULL)
++    switch (ELF64_R_TYPE (rel->r_info))
++      {
++      case R_MICROBLAZE_GNU_VTINHERIT:
++      case R_MICROBLAZE_GNU_VTENTRY:
++	return NULL;
++      }
++
++  return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
++}
++
++/* Update the got entry reference counts for the section being removed.  */
++
++static bfd_boolean
++microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
++     			      struct bfd_link_info * info ATTRIBUTE_UNUSED,
++     			      asection * sec ATTRIBUTE_UNUSED,
++     			      const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
++{
++  return TRUE;
++}
++
++/* PIC support.  */
++
++#define PLT_ENTRY_SIZE 16
++
++#define PLT_ENTRY_WORD_0  0xb0000000          /* "imm 0".  */
++#define PLT_ENTRY_WORD_1  0xe9940000          /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT.  */
++#define PLT_ENTRY_WORD_1_NOPIC  0xe9800000    /* "lwi r12,r0,0" - non-PIC object.  */
++#define PLT_ENTRY_WORD_2  0x98186000          /* "brad r12".  */
++#define PLT_ENTRY_WORD_3  0x80000000          /* "nop".  */
++
++/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
++   shortcuts to them in our hash table.  */
++
++static bfd_boolean
++create_got_section (bfd *dynobj, struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++
++  if (! _bfd_elf_create_got_section (dynobj, info))
++    return FALSE;
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  htab->sgot = bfd_get_linker_section (dynobj, ".got");
++  htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt");
++  if (!htab->sgot || !htab->sgotplt)
++    return FALSE;
++
++  if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL)
++    htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got");
++  if (htab->srelgot == NULL
++      || ! bfd_set_section_flags (htab->srelgot, SEC_ALLOC
++                                  | SEC_LOAD
++                                  | SEC_HAS_CONTENTS
++                                  | SEC_IN_MEMORY
++                                  | SEC_LINKER_CREATED
++                                  | SEC_READONLY)
++      || ! bfd_set_section_alignment (htab->srelgot, 2))
++    return FALSE;
++  return TRUE;
++}
++
++static bfd_boolean
++update_local_sym_info (bfd *abfd,
++		       Elf_Internal_Shdr *symtab_hdr,
++		       unsigned long r_symndx,
++		       unsigned int tls_type)
++{
++  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
++  unsigned char *local_got_tls_masks;
++
++  if (local_got_refcounts == NULL)
++    {
++      bfd_size_type size = symtab_hdr->sh_info;
++
++      size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
++      local_got_refcounts = bfd_zalloc (abfd, size);
++      if (local_got_refcounts == NULL)
++        return FALSE;
++      elf_local_got_refcounts (abfd) = local_got_refcounts;
++    }
++
++  local_got_tls_masks =
++         (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
++  local_got_tls_masks[r_symndx] |= tls_type;
++  local_got_refcounts[r_symndx] += 1;
++
++  return TRUE;
++}
++/* Look through the relocs for a section during the first phase.  */
++
++static bfd_boolean
++microblaze_elf_check_relocs (bfd * abfd,
++			     struct bfd_link_info * info,
++     			     asection * sec,
++			     const Elf_Internal_Rela * relocs)
++{
++  Elf_Internal_Shdr *           symtab_hdr;
++  struct elf_link_hash_entry ** sym_hashes;
++  struct elf_link_hash_entry ** sym_hashes_end;
++  const Elf_Internal_Rela *     rel;
++  const Elf_Internal_Rela *     rel_end;
++  struct elf64_mb_link_hash_table *htab;
++  asection *sreloc = NULL;
++
++  if (bfd_link_relocatable (info))
++    return TRUE;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
++  sym_hashes = elf_sym_hashes (abfd);
++  sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
++  if (!elf_bad_symtab (abfd))
++    sym_hashes_end -= symtab_hdr->sh_info;
++
++  rel_end = relocs + sec->reloc_count;
++
++  for (rel = relocs; rel < rel_end; rel++)
++    {
++      unsigned int r_type;
++      struct elf_link_hash_entry * h;
++      unsigned long r_symndx;
++      unsigned char tls_type = 0;
++
++      r_symndx = ELF64_R_SYM (rel->r_info);
++      r_type = ELF64_R_TYPE (rel->r_info);
++
++      if (r_symndx < symtab_hdr->sh_info)
++        h = NULL;
++      else
++	{
++	  h = sym_hashes [r_symndx - symtab_hdr->sh_info];
++	  while (h->root.type == bfd_link_hash_indirect
++		 || h->root.type == bfd_link_hash_warning)
++	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
++	}
++
++      switch (r_type)
++        {
++	  /* This relocation describes the C++ object vtable hierarchy.
++	     Reconstruct it for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTINHERIT:
++          if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
++            return FALSE;
++          break;
++
++	  /* This relocation describes which C++ vtable entries are actually
++	     used.  Record for later use during GC.  */
++        case R_MICROBLAZE_GNU_VTENTRY:
++          if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
++            return FALSE;
++          break;
++
++	  /* This relocation requires .plt entry.  */
++        case R_MICROBLAZE_PLT_64:
++          if (h != NULL)
++	    {
++	      h->needs_plt = 1;
++	      h->plt.refcount += 1;
++	    }
++          break;
++
++	  /* This relocation requires .got entry.  */
++        case R_MICROBLAZE_TLSGD:
++          tls_type |= (TLS_TLS | TLS_GD);
++          goto dogottls;
++        case R_MICROBLAZE_TLSLD:
++          tls_type |= (TLS_TLS | TLS_LD);
++        dogottls:
++          sec->has_tls_reloc = 1;
++        case R_MICROBLAZE_GOT_64:
++          if (htab->sgot == NULL)
++            {
++              if (htab->elf.dynobj == NULL)
++                htab->elf.dynobj = abfd;
++              if (!create_got_section (htab->elf.dynobj, info))
++                return FALSE;
++            }
++          if (h != NULL)
++	    {
++	      h->got.refcount += 1;
++	      elf64_mb_hash_entry (h)->tls_mask |= tls_type;
++	    }
++          else
++	    {
++	      if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
++		return FALSE;
++	    }
++          break;
++
++        case R_MICROBLAZE_64:
++        case R_MICROBLAZE_64_PCREL:
++        case R_MICROBLAZE_32:
++          {
++            if (h != NULL && !bfd_link_pic (info))
++	      {
++		/* we may need a copy reloc.  */
++		h->non_got_ref = 1;
++
++		/* we may also need a .plt entry.  */
++		h->plt.refcount += 1;
++		if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
++		  h->pointer_equality_needed = 1;
++	      }
++
++
++	    /* If we are creating a shared library, and this is a reloc
++	       against a global symbol, or a non PC relative reloc
++	       against a local symbol, then we need to copy the reloc
++	       into the shared library.  However, if we are linking with
++	       -Bsymbolic, we do not need to copy a reloc against a
++	       global symbol which is defined in an object we are
++	       including in the link (i.e., DEF_REGULAR is set).  At
++	       this point we have not seen all the input files, so it is
++	       possible that DEF_REGULAR is not set now but will be set
++	       later (it is never cleared).  In case of a weak definition,
++	       DEF_REGULAR may be cleared later by a strong definition in
++	       a shared library.  We account for that possibility below by
++	       storing information in the relocs_copied field of the hash
++	       table entry.  A similar situation occurs when creating
++	       shared libraries and symbol visibility changes render the
++	       symbol local.
++
++	       If on the other hand, we are creating an executable, we
++	       may need to keep relocations for symbols satisfied by a
++	       dynamic library if we manage to avoid copy relocs for the
++	       symbol.  */
++
++            if ((bfd_link_pic (info)
++                 && (sec->flags & SEC_ALLOC) != 0
++                 && (r_type != R_MICROBLAZE_64_PCREL
++                     || (h != NULL
++			 && (! info->symbolic
++			     || h->root.type == bfd_link_hash_defweak
++			     || !h->def_regular))))
++                || (!bfd_link_pic (info)
++                    && (sec->flags & SEC_ALLOC) != 0
++                    && h != NULL
++                    && (h->root.type == bfd_link_hash_defweak
++                        || !h->def_regular)))
++              {
++                struct elf64_mb_dyn_relocs *p;
++                struct elf64_mb_dyn_relocs **head;
++
++                /* When creating a shared object, we must copy these
++                   relocs into the output file.  We create a reloc
++                   section in dynobj and make room for the reloc.  */
++
++		if (sreloc == NULL)
++		  {
++		    bfd *dynobj;
++
++		    if (htab->elf.dynobj == NULL)
++		      htab->elf.dynobj = abfd;
++		    dynobj = htab->elf.dynobj;
++
++		    sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
++								  2, abfd, 1);
++		    if (sreloc == NULL)
++		      return FALSE;
++		  }
++
++		/* If this is a global symbol, we count the number of
++		   relocations we need for this symbol.  */
++		if (h != NULL)
++		  head = &h->dyn_relocs;
++		else
++		  {
++		    /* Track dynamic relocs needed for local syms too.
++		       We really need local syms available to do this
++		       easily.  Oh well.  */
++
++		    asection *s;
++		    Elf_Internal_Sym *isym;
++		    void *vpp;
++
++		    isym = bfd_sym_from_r_symndx (&htab->sym_sec,
++						  abfd, r_symndx);
++		    if (isym == NULL)
++		      return FALSE;
++
++		    s = bfd_section_from_elf_index (abfd, isym->st_shndx);
++		    if (s == NULL)
++		      return FALSE;
++
++		    vpp = &elf_section_data (s)->local_dynrel;
++		    head = (struct elf64_mb_dyn_relocs **) vpp;
++		  }
++
++		p = *head;
++		if (p == NULL || p->sec != sec)
++		  {
++		    size_t amt = sizeof *p;
++		    p = ((struct elf64_mb_dyn_relocs *)
++			 bfd_alloc (htab->elf.dynobj, amt));
++		    if (p == NULL)
++		      return FALSE;
++		    p->next = *head;
++		    *head = p;
++		    p->sec = sec;
++		    p->count = 0;
++		    p->pc_count = 0;
++		  }
++
++		p->count += 1;
++		if (r_type == R_MICROBLAZE_64_PCREL)
++		  p->pc_count += 1;
++	      }
++          }
++          break;
++        }
++    }
++
++  return TRUE;
++}
++
++static bfd_boolean
++microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (!htab->sgot && !create_got_section (dynobj, info))
++    return FALSE;
++
++  if (!_bfd_elf_create_dynamic_sections (dynobj, info))
++    return FALSE;
++
++  htab->splt = bfd_get_linker_section (dynobj, ".plt");
++  htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
++  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
++  if (!bfd_link_pic (info))
++    htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
++
++  if (!htab->splt || !htab->srelplt || !htab->sdynbss
++      || (!bfd_link_pic (info) && !htab->srelbss))
++    abort ();
++
++  return TRUE;
++}
++
++/* Copy the extra info we tack onto an elf_link_hash_entry.  */
++
++static void
++microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
++				     struct elf_link_hash_entry *dir,
++				     struct elf_link_hash_entry *ind)
++{
++  struct elf64_mb_link_hash_entry *edir, *eind;
++
++  edir = (struct elf64_mb_link_hash_entry *) dir;
++  eind = (struct elf64_mb_link_hash_entry *) ind;
++
++  if (eind->dyn_relocs != NULL)
++    {
++      if (edir->dyn_relocs != NULL)
++	{
++	  struct elf64_mb_dyn_relocs **pp;
++	  struct elf64_mb_dyn_relocs *p;
++
++	  if (ind->root.type == bfd_link_hash_indirect)
++	    abort ();
++
++	  /* Add reloc counts against the weak sym to the strong sym
++	     list.  Merge any entries against the same section.  */
++	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
++	    {
++	      struct elf64_mb_dyn_relocs *q;
++
++	      for (q = edir->dyn_relocs; q != NULL; q = q->next)
++		if (q->sec == p->sec)
++		  {
++		    q->pc_count += p->pc_count;
++		    q->count += p->count;
++		    *pp = p->next;
++		    break;
++		  }
++	      if (q == NULL)
++		pp = &p->next;
++	    }
++	  *pp = edir->dyn_relocs;
++	}
++
++      edir->dyn_relocs = eind->dyn_relocs;
++      eind->dyn_relocs = NULL;
++    }
++
++  edir->tls_mask |= eind->tls_mask;
++
++  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
++}
++
++static bfd_boolean
++microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
++				      struct elf_link_hash_entry *h)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry * eh;
++  struct elf64_mb_dyn_relocs *p;
++  asection *sdynbss;
++  asection *s, *srel;
++  unsigned int power_of_two;
++  bfd *dynobj;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  /* If this is a function, put it in the procedure linkage table.  We
++     will fill in the contents of the procedure linkage table later,
++     when we know the address of the .got section.  */
++  if (h->type == STT_FUNC
++      || h->needs_plt)
++    {
++      if (h->plt.refcount <= 0
++	  || SYMBOL_CALLS_LOCAL (info, h)
++	  || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
++	      && h->root.type == bfd_link_hash_undefweak))
++	{
++	  /* This case can occur if we saw a PLT reloc in an input
++	     file, but the symbol was never referred to by a dynamic
++	     object, or if all references were garbage collected.  In
++	     such a case, we don't actually need to build a procedure
++	     linkage table, and we can just do a PC32 reloc instead.  */
++	  h->plt.offset = (bfd_vma) -1;
++	  h->needs_plt = 0;
++	}
++
++      return TRUE;
++    }
++  else
++    /* It's possible that we incorrectly decided a .plt reloc was
++       needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
++       check_relocs.  We can't decide accurately between function and
++       non-function syms in check-relocs;  Objects loaded later in
++       the link may change h->type.  So fix it now.  */
++    h->plt.offset = (bfd_vma) -1;
++
++  /* If this is a weak symbol, and there is a real definition, the
++     processor independent code will have arranged for us to see the
++     real definition first, and we can just use the same value.  */
++  if (h->is_weakalias)
++    {
++      struct elf_link_hash_entry *def = weakdef (h);
++      BFD_ASSERT (def->root.type == bfd_link_hash_defined);
++      h->root.u.def.section = def->root.u.def.section;
++      h->root.u.def.value = def->root.u.def.value;
++      return TRUE;
++    }
++
++  /* This is a reference to a symbol defined by a dynamic object which
++     is not a function.  */
++
++  /* If we are creating a shared library, we must presume that the
++     only references to the symbol are via the global offset table.
++     For such cases we need not do anything here; the relocations will
++     be handled correctly by relocate_section.  */
++  if (bfd_link_pic (info))
++    return TRUE;
++
++  /* If there are no references to this symbol that do not use the
++     GOT, we don't need to generate a copy reloc.  */
++  if (!h->non_got_ref)
++    return TRUE;
++
++  /* If -z nocopyreloc was given, we won't generate them either.  */
++  if (info->nocopyreloc)
++    {
++      h->non_got_ref = 0;
++      return TRUE;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  for (p = eh->dyn_relocs; p != NULL; p = p->next)
++    {
++      s = p->sec->output_section;
++      if (s != NULL && (s->flags & SEC_READONLY) != 0)
++	break;
++    }
++
++  /* If we didn't find any dynamic relocs in read-only sections, then
++     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
++  if (!_bfd_elf_readonly_dynrelocs (h))
++    {
++      h->non_got_ref = 0;
++      return TRUE;
++    }
++
++  /* We must allocate the symbol in our .dynbss section, which will
++     become part of the .bss section of the executable.  There will be
++     an entry for this symbol in the .dynsym section.  The dynamic
++     object will contain position independent code, so all references
++     from the dynamic object to this symbol will go through the global
++     offset table.  The dynamic linker will use the .dynsym entry to
++     determine the address it must put in the global offset table, so
++     both the dynamic object and the regular object will refer to the
++     same memory location for the variable.  */
++
++  /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
++     to copy the initial value out of the dynamic object and into the
++     runtime process image.  */
++  if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
++    {
++      s = htab->elf.sdynrelro;
++      srel = htab->elf.sreldynrelro;
++    }
++  else
++    {
++      s = htab->elf.sdynbss;
++      srel = htab->elf.srelbss;
++    }
++  if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
++    {
++      srel->size += sizeof (Elf64_External_Rela);
++      h->needs_copy = 1;
++    }
++
++  /* We need to figure out the alignment required for this symbol.  I
++     have no idea how ELF linkers handle this.  */
++  power_of_two = bfd_log2 (h->size);
++  if (power_of_two > 3)
++    power_of_two = 3;
++
++  /* Apply the required alignment.  */
++  s->size = BFD_ALIGN (s->size, (bfd_size_type) (1 << power_of_two));
++  if (power_of_two > s->alignment_power)
++    {
++      if (!bfd_set_section_alignment (s, power_of_two))
++	return FALSE;
++    }
++
++  /* Define the symbol as being at this point in the section.  */
++  h->root.u.def.section = s;
++  h->root.u.def.value = s->size;
++
++  /* Increment the section size to make room for the symbol.  */
++  s->size += h->size;
++  return TRUE;
++}
++
++/* Allocate space in .plt, .got and associated reloc sections for
++   dynamic relocs.  */
++
++static bfd_boolean
++allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
++{
++  struct bfd_link_info *info;
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh;
++  struct elf64_mb_dyn_relocs *p;
++
++  if (h->root.type == bfd_link_hash_indirect)
++    return TRUE;
++
++  info = (struct bfd_link_info *) dat;
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (htab->elf.dynamic_sections_created
++      && h->plt.refcount > 0)
++    {
++      /* Make sure this symbol is output as a dynamic symbol.
++	 Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return FALSE;
++        }
++
++      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
++        {
++          asection *s = htab->splt;
++
++          /* The first entry in .plt is reserved.  */
++          if (s->size == 0)
++            s->size = PLT_ENTRY_SIZE;
++
++          h->plt.offset = s->size;
++
++          /* If this symbol is not defined in a regular file, and we are
++             not generating a shared library, then set the symbol to this
++             location in the .plt.  This is required to make function
++             pointers compare as equal between the normal executable and
++             the shared library.  */
++          if (! bfd_link_pic (info)
++              && !h->def_regular)
++            {
++              h->root.u.def.section = s;
++              h->root.u.def.value = h->plt.offset;
++            }
++
++          /* Make room for this entry.  */
++          s->size += PLT_ENTRY_SIZE;
++
++	  /* We also need to make an entry in the .got.plt section, which
++	     will be placed in the .got section by the linker script.  */
++	  htab->elf.sgotplt->size += 4;
++
++	  /* We also need to make an entry in the .rel.plt section.  */
++	  htab->elf.srelplt->size += sizeof (Elf32_External_Rela);
++	}
++      else
++        {
++          h->plt.offset = (bfd_vma) -1;
++          h->needs_plt = 0;
++        }
++    }
++  else
++    {
++      h->plt.offset = (bfd_vma) -1;
++      h->needs_plt = 0;
++    }
++
++  eh = (struct elf64_mb_link_hash_entry *) h;
++  if (h->got.refcount > 0)
++    {
++      unsigned int need;
++      asection *s;
++
++      /* Make sure this symbol is output as a dynamic symbol.
++         Undefined weak syms won't yet be marked as dynamic.  */
++      if (h->dynindx == -1
++          && !h->forced_local)
++        {
++          if (! bfd_elf_link_record_dynamic_symbol (info, h))
++            return FALSE;
++        }
++
++      need = 0;
++      if ((eh->tls_mask & TLS_TLS) != 0)
++        {
++          /* Handle TLS Symbol */
++          if ((eh->tls_mask & TLS_LD) != 0)
++            {
++              if (!eh->elf.def_dynamic)
++                /* We'll just use htab->tlsld_got.offset.  This should
++                   always be the case.  It's a little odd if we have
++                   a local dynamic reloc against a non-local symbol.  */
++                htab->tlsld_got.refcount += 1;
++              else
++                need += 8;
++            }
++          if ((eh->tls_mask & TLS_GD) != 0)
++            need += 8;
++        }
++      else
++        {
++          /* Regular (non-TLS) symbol */
++          need += 4;
++        }
++      if (need == 0)
++        {
++          h->got.offset = (bfd_vma) -1;
++        }
++      else
++	{
++	  s = htab->elf.sgot;
++	  h->got.offset = s->size;
++	  s->size += need;
++	  htab->elf.srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
++	}
++    }
++  else
++    h->got.offset = (bfd_vma) -1;
++
++  if (h->dyn_relocs == NULL)
++    return TRUE;
++
++  /* In the shared -Bsymbolic case, discard space allocated for
++     dynamic pc-relative relocs against symbols which turn out to be
++     defined in regular objects.  For the normal shared case, discard
++     space for pc-relative relocs that have become local due to symbol
++     visibility changes.  */
++
++  if (bfd_link_pic (info))
++    {
++      if (h->def_regular
++	  && (h->forced_local
++	      || info->symbolic))
++	{
++	  struct elf64_mb_dyn_relocs **pp;
++
++	  for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
++	    {
++	      p->count -= p->pc_count;
++	      p->pc_count = 0;
++	      if (p->count == 0)
++		*pp = p->next;
++	      else
++		pp = &p->next;
++	    }
++	}
++      else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
++	h->dyn_relocs = NULL;
++    }
++  else
++    {
++      /* For the non-shared case, discard space for relocs against
++	 symbols which turn out to need copy relocs or are not
++	 dynamic.  */
++
++      if (!h->non_got_ref
++	  && ((h->def_dynamic
++	       && !h->def_regular)
++	      || (htab->elf.dynamic_sections_created
++		  && (h->root.type == bfd_link_hash_undefweak
++		      || h->root.type == bfd_link_hash_undefined))))
++	{
++	  /* Make sure this symbol is output as a dynamic symbol.
++	     Undefined weak syms won't yet be marked as dynamic.  */
++	  if (h->dynindx == -1
++	      && !h->forced_local)
++	    {
++	      if (! bfd_elf_link_record_dynamic_symbol (info, h))
++		return FALSE;
++	    }
++
++	  /* If that succeeded, we know we'll be keeping all the
++	     relocs.  */
++	  if (h->dynindx != -1)
++	    goto keep;
++	}
++
++      h->dyn_relocs = NULL;
++
++    keep: ;
++    }
++
++  /* Finally, allocate space.  */
++  for (p = h->dyn_relocs; p != NULL; p = p->next)
++    {
++      asection *sreloc = elf_section_data (p->sec)->sreloc;
++      sreloc->size += p->count * sizeof (Elf64_External_Rela);
++    }
++
++  return TRUE;
++}
++
++/* Set the sizes of the dynamic sections.  */
++
++static bfd_boolean
++microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
++				      struct bfd_link_info *info)
++{
++  struct elf64_mb_link_hash_table *htab;
++  bfd *dynobj;
++  asection *s;
++  bfd *ibfd;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  dynobj = htab->elf.dynobj;
++  BFD_ASSERT (dynobj != NULL);
++
++  /* Set up .got offsets for local syms, and space for local dynamic
++     relocs.  */
++  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
++    {
++      bfd_signed_vma *local_got;
++      bfd_signed_vma *end_local_got;
++      bfd_size_type locsymcount;
++      Elf_Internal_Shdr *symtab_hdr;
++      unsigned char *lgot_masks;
++      asection *srel;
++
++      if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
++        continue;
++
++      for (s = ibfd->sections; s != NULL; s = s->next)
++	{
++	  struct elf64_mb_dyn_relocs *p;
++
++	  for (p = ((struct elf64_mb_dyn_relocs *)
++		    elf_section_data (s)->local_dynrel);
++	       p != NULL;
++	       p = p->next)
++	    {
++	      if (!bfd_is_abs_section (p->sec)
++		  && bfd_is_abs_section (p->sec->output_section))
++		{
++		  /* Input section has been discarded, either because
++		     it is a copy of a linkonce section or due to
++		     linker script /DISCARD/, so we'll be discarding
++		     the relocs too.  */
++		}
++	      else if (p->count != 0)
++		{
++		  srel = elf_section_data (p->sec)->sreloc;
++		  srel->size += p->count * sizeof (Elf64_External_Rela);
++		  if ((p->sec->output_section->flags & SEC_READONLY) != 0)
++		    info->flags |= DF_TEXTREL;
++		}
++	    }
++	}
++
++      local_got = elf_local_got_refcounts (ibfd);
++      if (!local_got)
++        continue;
++
++      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
++      locsymcount = symtab_hdr->sh_info;
++      end_local_got = local_got + locsymcount;
++      lgot_masks = (unsigned char *) end_local_got;
++      s = htab->elf.sgot;
++      srel = htab->elf.srelgot;
++
++      for (; local_got < end_local_got; ++local_got, ++lgot_masks)
++	{
++	  if (*local_got > 0)
++	    {
++	      unsigned int need = 0;
++	      if ((*lgot_masks & TLS_TLS) != 0)
++		{
++		  if ((*lgot_masks & TLS_GD) != 0)
++		    need += 8;
++		  if ((*lgot_masks & TLS_LD) != 0)
++		    htab->tlsld_got.refcount += 1;
++		}
++	      else
++		need += 4;
++
++	      if (need == 0)
++		{
++		  *local_got = (bfd_vma) -1;
++		}
++	      else
++		{
++		  *local_got = s->size;
++		  s->size += need;
++		  if (bfd_link_pic (info))
++		    srel->size += need * (sizeof (Elf64_External_Rela) / 4);
++		}
++            }
++          else
++            *local_got = (bfd_vma) -1;
++        }
++    }
++
++  /* Allocate global sym .plt and .got entries, and space for global
++     sym dynamic relocs.  */
++  elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
++
++  if (htab->tlsld_got.refcount > 0)
++    {
++      htab->tlsld_got.offset = htab->elf.sgot->size;
++      htab->elf.sgot->size += 8;
++      if (bfd_link_pic (info))
++	htab->elf.srelgot->size += sizeof (Elf64_External_Rela);
++    }
++  else
++    htab->tlsld_got.offset = (bfd_vma) -1;
++
++  if (elf_hash_table (info)->dynamic_sections_created)
++    {
++      /* Make space for the trailing nop in .plt.  */
++      if (htab->elf.splt->size > 0)
++	htab->elf.splt->size += 4;
++    }
++
++  /* The check_relocs and adjust_dynamic_symbol entry points have
++     determined the sizes of the various dynamic sections.  Allocate
++     memory for them.  */
++  for (s = dynobj->sections; s != NULL; s = s->next)
++    {
++      const char *name;
++      bfd_boolean strip = FALSE;
++
++      if ((s->flags & SEC_LINKER_CREATED) == 0)
++        continue;
++
++      /* It's OK to base decisions on the section name, because none
++	 of the dynobj section names depend upon the input files.  */
++      name = bfd_section_name (s);
++
++      if (strncmp (name, ".rela", 5) == 0)
++	{
++	  if (s->size == 0)
++	    {
++	      /* If we don't need this section, strip it from the
++		 output file.  This is to handle .rela.bss and
++		 .rela.plt.  We must create it in
++		 create_dynamic_sections, because it must be created
++		 before the linker maps input sections to output
++		 sections.  The linker does that before
++		 adjust_dynamic_symbol is called, and it is that
++		 function which decides whether anything needs to go
++		 into these sections.  */
++	      strip = TRUE;
++	    }
++	  else
++	    {
++	      /* We use the reloc_count field as a counter if we need
++		 to copy relocs into the output file.  */
++	      s->reloc_count = 0;
++	    }
++	}
++      else if (s != htab->elf.splt
++	       && s != htab->elf.sgot
++	       && s != htab->elf.sgotplt
++	       && s != htab->elf.sdynbss
++	       && s != htab->elf.sdynrelro)
++	{
++	  /* It's not one of our sections, so don't allocate space.  */
++	  continue;
++	}
++
++      if (strip)
++        {
++          s->flags |= SEC_EXCLUDE;
++          continue;
++        }
++
++      /* Allocate memory for the section contents.  */
++      /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
++         Unused entries should be reclaimed before the section's contents
++         are written out, but at the moment this does not happen.  Thus in
++         order to prevent writing out garbage, we initialise the section's
++         contents to zero.  */
++      s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
++      if (s->contents == NULL && s->size != 0)
++        return FALSE;
++    }
++
++  if (elf_hash_table (info)->dynamic_sections_created)
++    {
++      /* Add some entries to the .dynamic section.  We fill in the
++	 values later, in microblaze_elf_finish_dynamic_sections, but we
++	 must add the entries now so that we get the correct size for
++	 the .dynamic section.  The DT_DEBUG entry is filled in by the
++	 dynamic linker and used by the debugger.  */
++#define add_dynamic_entry(TAG, VAL)			\
++      _bfd_elf_add_dynamic_entry (info, TAG, VAL)
++
++      if (bfd_link_executable (info))
++        {
++          if (!add_dynamic_entry (DT_DEBUG, 0))
++            return FALSE;
++        }
++
++      if (!add_dynamic_entry (DT_RELA, 0)
++          || !add_dynamic_entry (DT_RELASZ, 0)
++          || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela)))
++	return FALSE;
++
++      if (htab->splt->size != 0)
++        {
++          if (!add_dynamic_entry (DT_PLTGOT, 0)
++              || !add_dynamic_entry (DT_PLTRELSZ, 0)
++              || !add_dynamic_entry (DT_PLTREL, DT_RELA)
++              || !add_dynamic_entry (DT_JMPREL, 0)
++              || !add_dynamic_entry (DT_BIND_NOW, 1))
++            return FALSE;
++        }
++
++      if (info->flags & DF_TEXTREL)
++        {
++          if (!add_dynamic_entry (DT_TEXTREL, 0))
++            return FALSE;
++        }
++    }
++#undef add_dynamic_entry
++  return TRUE;
++}
++
++/* Finish up dynamic symbol handling.  We set the contents of various
++   dynamic sections here.  */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
++				      struct bfd_link_info *info,
++				      struct elf_link_hash_entry *h,
++				      Elf_Internal_Sym *sym)
++{
++  struct elf64_mb_link_hash_table *htab;
++  struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  if (h->plt.offset != (bfd_vma) -1)
++    {
++      asection *splt;
++      asection *srela;
++      asection *sgotplt;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++      bfd_vma plt_index;
++      bfd_vma got_offset;
++      bfd_vma got_addr;
++
++      /* This symbol has an entry in the procedure linkage table.  Set
++         it up.  */
++      BFD_ASSERT (h->dynindx != -1);
++
++      splt = htab->splt;
++      srela = htab->srelplt;
++      sgotplt = htab->sgotplt;
++      BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
++
++      plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved.  */
++      got_offset = (plt_index + 3) * 4; /* 3 reserved ???  */
++      got_addr = got_offset;
++
++      /* For non-PIC objects we need absolute address of the GOT entry.  */
++      if (!bfd_link_pic (info))
++	got_addr += sgotplt->output_section->vma + sgotplt->output_offset;
++
++      /* Fill in the entry in the procedure linkage table.  */
++      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
++                  splt->contents + h->plt.offset);
++      if (bfd_link_pic (info))
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      else
++        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
++                    splt->contents + h->plt.offset + 4);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
++                  splt->contents + h->plt.offset + 8);
++      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
++                  splt->contents + h->plt.offset + 12);
++
++      /* Any additions to the .got section??? */
++      /*      bfd_put_32 (output_bfd,
++	      splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
++	      sgotplt->contents + got_offset); */
++
++      /* Fill in the entry in the .rela.plt section.  */
++      rela.r_offset = (sgotplt->output_section->vma
++                       + sgotplt->output_offset
++                       + got_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
++      rela.r_addend = 0;
++      loc = srela->contents;
++      loc += plt_index * sizeof (Elf64_External_Rela);
++      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++
++      if (!h->def_regular)
++        {
++          /* Mark the symbol as undefined, rather than as defined in
++             the .plt section.  Zero the value.  */
++          sym->st_shndx = SHN_UNDEF;
++          sym->st_value = 0;
++        }
++    }
++
++  /* h->got.refcount to be checked ? */
++  if (h->got.offset != (bfd_vma) -1 &&
++      ! ((h->got.offset & 1) ||
++          IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
++    {
++      asection *sgot;
++      asection *srela;
++      bfd_vma offset;
++
++      /* This symbol has an entry in the global offset table.  Set it
++         up.  */
++
++      sgot = htab->elf.sgot;
++      srela = htab->elf.srelgot;
++      BFD_ASSERT (sgot != NULL && srela != NULL);
++
++      offset = (sgot->output_section->vma + sgot->output_offset
++		+ (h->got.offset &~ (bfd_vma) 1));
++
++      /* If this is a -Bsymbolic link, and the symbol is defined
++         locally, we just want to emit a RELATIVE reloc.  Likewise if
++         the symbol was forced to be local because of a version file.
++         The entry in the global offset table will already have been
++         initialized in the relocate_section function.  */
++      if (bfd_link_pic (info)
++          && ((info->symbolic && h->def_regular)
++	      || h->dynindx == -1))
++        {
++          asection *sec = h->root.u.def.section;
++          microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                    srela, srela->reloc_count++,
++                                                    /* symindex= */ 0,
++                                                    R_MICROBLAZE_REL, offset,
++                                                    h->root.u.def.value
++                                                    + sec->output_section->vma
++                                                    + sec->output_offset);
++        }
++      else
++        {
++          microblaze_elf_output_dynamic_relocation (output_bfd,
++                                                    srela, srela->reloc_count++,
++                                                    h->dynindx,
++                                                    R_MICROBLAZE_GLOB_DAT,
++                                                    offset, 0);
++        }
++
++      bfd_put_32 (output_bfd, (bfd_vma) 0,
++                  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
++    }
++
++  if (h->needs_copy)
++    {
++      asection *s;
++      Elf_Internal_Rela rela;
++      bfd_byte *loc;
++
++      /* This symbols needs a copy reloc.  Set it up.  */
++
++      BFD_ASSERT (h->dynindx != -1);
++
++      s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss");
++      BFD_ASSERT (s != NULL);
++
++      rela.r_offset = (h->root.u.def.value
++                       + h->root.u.def.section->output_section->vma
++                       + h->root.u.def.section->output_offset);
++      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
++      rela.r_addend = 0;
++      loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
++      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
++    }
++
++  /* Mark some specially defined symbols as absolute.  */
++  if (h == htab->elf.hdynamic
++      || h == htab->elf.hgot
++      || h == htab->elf.hplt)
++    sym->st_shndx = SHN_ABS;
++
++  return TRUE;
++}
++
++
++/* Finish up the dynamic sections.  */
++
++static bfd_boolean
++microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
++					struct bfd_link_info *info)
++{
++  bfd *dynobj;
++  asection *sdyn, *sgot;
++  struct elf64_mb_link_hash_table *htab;
++
++  htab = elf64_mb_hash_table (info);
++  if (htab == NULL)
++    return FALSE;
++
++  dynobj = htab->elf.dynobj;
++
++  sdyn = bfd_get_linker_section (dynobj, ".dynamic");
++
++  if (htab->elf.dynamic_sections_created)
++    {
++      asection *splt;
++      Elf64_External_Dyn *dyncon, *dynconend;
++
++      splt = bfd_get_linker_section (dynobj, ".plt");
++      BFD_ASSERT (splt != NULL && sdyn != NULL);
++
++      dyncon = (Elf64_External_Dyn *) sdyn->contents;
++      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
++      for (; dyncon < dynconend; dyncon++)
++        {
++          Elf_Internal_Dyn dyn;
++          const char *name;
++          bfd_boolean size;
++
++          bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
++
++          switch (dyn.d_tag)
++            {
++            case DT_PLTGOT:   name = ".got.plt"; size = FALSE; break;
++            case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break;
++            case DT_JMPREL:   name = ".rela.plt"; size = FALSE; break;
++            case DT_RELA:     name = ".rela.dyn"; size = FALSE; break;
++            case DT_RELASZ:   name = ".rela.dyn"; size = TRUE; break;
++            default:	  name = NULL; size = FALSE; break;
++            }
++
++          if (name != NULL)
++            {
++              asection *s;
++
++              s = bfd_get_section_by_name (output_bfd, name);
++              if (s == NULL)
++                dyn.d_un.d_val = 0;
++              else
++                {
++                  if (! size)
++                    dyn.d_un.d_ptr = s->vma;
++                  else
++                    dyn.d_un.d_val = s->size;
++                }
++              bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
++            }
++        }
++
++      /* Clear the first entry in the procedure linkage table,
++	 and put a nop in the last four bytes.  */
++      if (splt->size > 0)
++        {
++          memset (splt->contents, 0, PLT_ENTRY_SIZE);
++          bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
++                      splt->contents + splt->size - 4);
++        }
++
++      elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
++    }
++
++  /* Set the first entry in the global offset table to the address of
++     the dynamic section.  */
++  sgot = htab->elf.sgotplt;
++  if (sgot && sgot->size > 0)
++    {
++      if (sdyn == NULL)
++        bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
++      else
++        bfd_put_32 (output_bfd,
++                    sdyn->output_section->vma + sdyn->output_offset,
++                    sgot->contents);
++      elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
++    }
++
++  if (htab->elf.sgot && htab->elf.sgot->size > 0)
++    elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize = 4;
++
++  return TRUE;
++}
++
++/* Hook called by the linker routine which adds symbols from an object
++   file.  We use it to put .comm items in .sbss, and not .bss.  */
++
++static bfd_boolean
++microblaze_elf_add_symbol_hook (bfd *abfd,
++			        struct bfd_link_info *info,
++			        Elf_Internal_Sym *sym,
++			        const char **namep ATTRIBUTE_UNUSED,
++			        flagword *flagsp ATTRIBUTE_UNUSED,
++			        asection **secp,
++			        bfd_vma *valp)
++{
++  if (sym->st_shndx == SHN_COMMON
++      && !bfd_link_relocatable (info)
++      && sym->st_size <= elf_gp_size (abfd))
++    {
++      /* Common symbols less than or equal to -G nn bytes are automatically
++	 put into .sbss.  */
++      *secp = bfd_make_section_old_way (abfd, ".sbss");
++      if (*secp == NULL
++	  || !bfd_set_section_flags (*secp, SEC_IS_COMMON))
++	return FALSE;
++
++      *valp = sym->st_size;
++    }
++
++  return TRUE;
++}
++
++#define TARGET_LITTLE_SYM      microblaze_elf64_le_vec
++#define TARGET_LITTLE_NAME     "elf64-microblazeel"
++
++#define TARGET_BIG_SYM          microblaze_elf64_vec
++#define TARGET_BIG_NAME		"elf64-microblaze"
++
++#define ELF_ARCH		bfd_arch_microblaze
++#define ELF_TARGET_ID		MICROBLAZE_ELF_DATA
++#define ELF_MACHINE_CODE	EM_MICROBLAZE
++#define ELF_MACHINE_ALT1	EM_MICROBLAZE_OLD
++#define ELF_MAXPAGESIZE		0x1000
++#define elf_info_to_howto	microblaze_elf_info_to_howto
++#define elf_info_to_howto_rel	NULL
++
++#define bfd_elf64_bfd_reloc_type_lookup		microblaze_elf_reloc_type_lookup
++#define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
++#define elf_backend_relocate_section		microblaze_elf_relocate_section
++#define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
++#define bfd_elf64_bfd_merge_private_bfd_data    microblaze_elf_merge_private_bfd_data
++#define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
++
++#define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
++#define elf_backend_gc_sweep_hook		microblaze_elf_gc_sweep_hook
++#define elf_backend_check_relocs                microblaze_elf_check_relocs
++#define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
++#define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
++#define elf_backend_can_gc_sections		1
++#define elf_backend_can_refcount    		1
++#define elf_backend_want_got_plt    		1
++#define elf_backend_plt_readonly    		1
++#define elf_backend_got_header_size 		12
++#define elf_backend_rela_normal     		1
++
++#define elf_backend_adjust_dynamic_symbol       microblaze_elf_adjust_dynamic_symbol
++#define elf_backend_create_dynamic_sections     microblaze_elf_create_dynamic_sections
++#define elf_backend_finish_dynamic_sections     microblaze_elf_finish_dynamic_sections
++#define elf_backend_finish_dynamic_symbol       microblaze_elf_finish_dynamic_symbol
++#define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
++#define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
++
++#include "elf64-target.h"
+Index: gdb-9.2/bfd/targets.c
+===================================================================
+--- gdb-9.2.orig/bfd/targets.c
++++ gdb-9.2/bfd/targets.c
+@@ -779,6 +779,8 @@ extern const bfd_target mep_elf32_le_vec
+ extern const bfd_target metag_elf32_vec;
+ extern const bfd_target microblaze_elf32_vec;
+ extern const bfd_target microblaze_elf32_le_vec;
++extern const bfd_target microblaze_elf64_vec;
++extern const bfd_target microblaze_elf64_le_vec;
+ extern const bfd_target mips_ecoff_be_vec;
+ extern const bfd_target mips_ecoff_le_vec;
+ extern const bfd_target mips_ecoff_bele_vec;
+@@ -1150,6 +1152,10 @@ static const bfd_target * const _bfd_tar
+ 
+ 	&metag_elf32_vec,
+ 
++#ifdef BFD64
++	&microblaze_elf64_vec,
++	&microblaze_elf64_le_vec,
++#endif
+ 	&microblaze_elf32_vec,
+ 
+ 	&mips_ecoff_be_vec,
+Index: gdb-9.2/include/elf/common.h
+===================================================================
+--- gdb-9.2.orig/include/elf/common.h
++++ gdb-9.2/include/elf/common.h
+@@ -339,6 +339,7 @@
+ #define EM_RISCV 	243 	/* RISC-V */
+ #define EM_LANAI	244	/* Lanai 32-bit processor.  */
+ #define EM_BPF		247	/* Linux BPF – in-kernel virtual machine.  */
++#define EM_MB_64	248	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
+ #define EM_NFP		250	/* Netronome Flow Processor.  */
+ #define EM_CSKY		252	/* C-SKY processor family.  */
+ 
+Index: gdb-9.2/ld/emulparams/elf64microblaze.sh
+===================================================================
+--- /dev/null
++++ gdb-9.2/ld/emulparams/elf64microblaze.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+Index: gdb-9.2/ld/emulparams/elf64microblazeel.sh
+===================================================================
+--- /dev/null
++++ gdb-9.2/ld/emulparams/elf64microblazeel.sh
+@@ -0,0 +1,23 @@
++SCRIPT_NAME=elfmicroblaze
++OUTPUT_FORMAT="elf64-microblazeel"
++#BIG_OUTPUT_FORMAT="elf64-microblaze"
++LITTLE_OUTPUT_FORMAT="elf64-microblazeel"
++#TEXT_START_ADDR=0
++NONPAGED_TEXT_START_ADDR=0x28
++ALIGNMENT=4
++MAXPAGESIZE=4
++ARCH=microblaze
++EMBEDDED=yes
++
++NOP=0x80000000
++
++# Hmmm, there's got to be a better way.  This sets the stack to the
++# top of the simulator memory (2^19 bytes).
++#PAGE_SIZE=0x1000
++#DATA_ADDR=0x10000
++#OTHER_RELOCATING_SECTIONS='.stack 0x7000 : { _stack = .; *(.stack) }'
++#$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
++#OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
++
++TEMPLATE_NAME=elf32
++#GENERATE_SHLIB_SCRIPT=yes
+Index: gdb-9.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-dis.c
++++ gdb-9.2/opcodes/microblaze-dis.c
+@@ -33,6 +33,7 @@
+ #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
+ #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
+ #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
++#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
+ 
+ #define NUM_STRBUFS 3
+@@ -73,11 +74,19 @@ get_field_imm (struct string_buf *buf, l
+ }
+ 
+ static char *
+-get_field_imm5 (struct string_buf *buf, long instr)
++get_field_imml (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++  return p;
++}
++
++static char *
++get_field_imms (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+ 
+-  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
++  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
+@@ -91,14 +100,14 @@ get_field_imm5_mbar (struct string_buf *
+ }
+ 
+ static char *
+-get_field_imm5width (struct string_buf *buf, long instr)
++get_field_immw (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+ 
+   if (instr & 0x00004000)
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
+  else
+-    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
++    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
+   return p;
+ }
+ 
+@@ -306,9 +315,13 @@ print_insn_microblaze (bfd_vma memaddr,
+ 		}
+ 	    }
+ 	  break;
+-	case INST_TYPE_RD_R1_IMM5:
++	case INST_TYPE_RD_R1_IMML:
++	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
++		      get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
++          /* TODO: Also print symbol */
++	case INST_TYPE_RD_R1_IMMS:
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+-		      get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
++	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
+ 	  break;
+ 	case INST_TYPE_RD_RFSL:
+ 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+@@ -415,6 +428,10 @@ print_insn_microblaze (bfd_vma memaddr,
+ 	case INST_TYPE_RD_R2:
+ 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
+ 		      get_field_r2 (&buf, inst));
++          break;
++        case INST_TYPE_IMML:
++	  print_func (stream, "\t%s", get_field_imml (&buf, inst));
++          /* TODO: Also print symbol */
+ 	  break;
+ 	case INST_TYPE_R2:
+ 	  print_func (stream, "\t%s", get_field_r2 (&buf, inst));
+@@ -438,8 +455,8 @@ print_insn_microblaze (bfd_vma memaddr,
+ 	case INST_TYPE_NONE:
+ 	  break;
+         /* For bit field insns.  */
+-	case INST_TYPE_RD_R1_IMM5_IMM5:
+-          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
++	case INST_TYPE_RD_R1_IMMW_IMMS:
++          print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+ 	     break;
+ 	/* For tuqula instruction */
+ 	case INST_TYPE_RD:
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -40,7 +40,7 @@
+ #define INST_TYPE_RD_SPECIAL 11
+ #define INST_TYPE_R1 12
+ /* New instn type for barrel shift imms.  */
+-#define INST_TYPE_RD_R1_IMM5  13
++#define INST_TYPE_RD_R1_IMMS  13
+ #define INST_TYPE_RD_RFSL    14
+ #define INST_TYPE_R1_RFSL    15
+ 
+@@ -60,7 +60,13 @@
+ #define INST_TYPE_IMM5 20
+ 
+ /* For bsefi and bsifi */
+-#define INST_TYPE_RD_R1_IMM5_IMM5  21
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
++/* For 64-bit instructions */
++#define INST_TYPE_IMML 22
++#define INST_TYPE_RD_R1_IMML 23
++#define INST_TYPE_R1_IMML 24
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
+ 
+@@ -91,13 +97,14 @@
+ #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+-#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
++#define OPCODE_MASK_H3  0xFC000700  /* High 6 bits and bits 21, 22, 23.  */
++#define OPCODE_MASK_H3B 0xFC00E600  /* High 6 bits and bits 16, 17, 18, 21, 22.  */
+ #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
++#define OPCODE_MASK_H32B 0xFC00E000  /* High 6 bits and bit 16, 17, 18.  */
+ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -107,7 +114,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 301
++#define MAX_OPCODES 412
+ 
+ struct op_code_struct
+ {
+@@ -125,6 +132,7 @@ struct op_code_struct
+   /* More info about output format here.  */
+ } opcodes[MAX_OPCODES] =
+ {
++  /* 32-bit instructions */
+   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
+   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
+   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
+@@ -161,11 +169,11 @@ struct op_code_struct
+   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+-  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+-  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+-  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
+-  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+-  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
++  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -425,6 +433,129 @@ struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
++
++  /* 64-bit instructions */
++  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
++  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
++  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
++  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
++  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
++  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
++  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
++  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
++  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
++  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
++  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
++  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
++  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
++  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
++  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
++  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
++  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
++  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
++  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
++  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
++  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
++  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
++  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
++  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
++  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
++  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
++  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
++  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
++  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
++  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
++  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
++  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
++  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
++  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
++  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
++  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
++  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
++  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
++  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
++  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
++  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
++  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
++  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
++  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
++  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
++  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
++  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
++  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
++  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
++  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
++  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
++  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
++  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
++  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
++  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
++  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
++  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
++  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
++  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
++  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
++  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
++  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
++  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
++  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
++  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
++  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
++  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
++  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
++  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
++  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
++  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
++  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
++  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
++  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
++  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
++  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
++  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
++  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
++  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
++  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
++  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
++  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
++  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
++  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
++  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
++  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
++  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
++  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
++  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
++  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
++  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
++  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
++  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
++  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
++  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
++  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
++  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
++  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
++  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
++  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
++  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
++  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
++  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
++  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
++  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
++  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM6  ((int) 0x00000000)
++#define MAX_IMM6  ((int) 0x0000003f)
++
+ #define MIN_IMM_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM_WIDTH  ((int) 0x00000020)
+ 
++#define MIN_IMM6_WIDTH  ((int) 0x00000001)
++#define MAX_IMM6_WIDTH  ((int) 0x00000040)
++
++#define MIN_IMML  ((long) 0xffffff8000000000L)
++#define MAX_IMML  ((long) 0x0000007fffffffffL)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+Index: gdb-9.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opcm.h
++++ gdb-9.2/opcodes/microblaze-opcm.h
+@@ -25,6 +25,7 @@
+ 
+ enum microblaze_instr
+ {
++  /* 32-bit instructions */
+   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu,swapb,swaph,
+@@ -58,6 +59,18 @@ enum microblaze_instr
+   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
+   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
++
++  /* 64-bit instructions */
++  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
++  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
++  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
++  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
++  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
++  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
++  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
++  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
++  dcmp_un, dbl, dlong, dsqrt,
+   invalid_inst
+ };
+ 
+@@ -135,15 +148,18 @@ enum microblaze_instr_type
+ #define RA_MASK 0x001F0000
+ #define RB_MASK 0x0000F800
+ #define IMM_MASK 0x0000FFFF
++#define IMML_MASK 0x00FFFFFF
+ 
+-/* Imm mask for barrel shifts.  */
++/* Imm masks for barrel shifts.  */
+ #define IMM5_MASK 0x0000001F
++#define IMM6_MASK 0x0000003F
+ 
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
+-/* Imm mask for extract/insert width. */
++/* Imm masks for extract/insert width. */
+ #define IMM5_WIDTH_MASK 0x000007C0
++#define IMM6_WIDTH_MASK 0x00000FC0
+ 
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-MB-X-initial-commit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-MB-X-initial-commit.patch
new file mode 100644
index 0000000000..6f5e0b6c2b
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-MB-X-initial-commit.patch
@@ -0,0 +1,359 @@
+From 070b7b1f35dedc41b1ba9a228d701485b2239ac0 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 16:31:26 +0530
+Subject: [PATCH 15/52] MB-X initial commit code cleanup is needed.
+
+Conflicts:
+	bfd/elf32-microblaze.c
+	gas/config/tc-microblaze.c
+	opcodes/microblaze-opcm.h
+---
+ bfd/bfd-in2.h              |  10 +++
+ bfd/elf32-microblaze.c     |  59 +++++++++++++-
+ bfd/elf64-microblaze.c     |  61 ++++++++++++++-
+ bfd/libbfd.h               |   2 +
+ bfd/reloc.c                |  12 +++
+ gas/config/tc-microblaze.c | 154 ++++++++++++++++++++++++++++++-------
+ include/elf/microblaze.h   |   2 +
+ opcodes/microblaze-opc.h   |  10 +--
+ opcodes/microblaze-opcm.h  |   4 +-
+ 9 files changed, 278 insertions(+), 36 deletions(-)
+
+Index: gdb-9.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-9.2.orig/bfd/bfd-in2.h
++++ gdb-9.2/bfd/bfd-in2.h
+@@ -5374,11 +5374,21 @@ done here - only used for relaxing  */
+   BFD_RELOC_MICROBLAZE_64_NONE,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
++value in two words (with an imml instruction).  The relocation is
++PC-relative GOT offset  */
++  BFD_RELOC_MICROBLAZE_64_GPC,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOT,
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
+@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_h
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  TRUE),		/* PC relative offset?  */
+ 
++   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
++
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_h
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  TRUE),		/* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd *
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1467,7 +1502,7 @@ microblaze_elf_relocate_section (bfd *ou
+ 		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+ 		  {
+ 		    relocation += addend;
+-		    if (r_type == R_MICROBLAZE_32)
++		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+ 		      bfd_put_32 (input_bfd, relocation, contents + offset);
+ 		    else
+ 		      {
+@@ -1933,6 +1968,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ 		}
+ 	      break;
++	    case R_MICROBLAZE_IMML_64:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
+ 	    case R_MICROBLAZE_NONE:
+ 	    case R_MICROBLAZE_32_NONE:
+ 	      {
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -117,6 +117,21 @@ static reloc_howto_type microblaze_elf_h
+           TRUE), 		/* PC relative offset?  */
+ 
+    /* A 64 bit relocation.  Table entry not really used.  */
++   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
++          0,			/* Rightshift.  */
++          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          64,			/* Bitsize.  */
++          TRUE,		/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,/* Special Function.  */
++          "R_MICROBLAZE_IMML_64",   	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
++   /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
+           0,			/* Rightshift.  */
+           2,			/* Size (0 = byte, 1 = short, 2 = long).  */
+@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_h
+           0x0000ffff,		/* Dest Mask.  */
+           TRUE), 		/* PC relative offset?  */
+ 
++   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
++   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
++          0,			/* Rightshift.  */
++          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++          16,			/* Bitsize.  */
++          TRUE,			/* PC_relative.  */
++          0,			/* Bitpos.  */
++          complain_overflow_dont, /* Complain on overflow.  */
++          bfd_elf_generic_reloc,	/* Special Function.  */
++          "R_MICROBLAZE_GPC_64", 	/* Name.  */
++          FALSE,		/* Partial Inplace.  */
++          0,			/* Source Mask.  */
++          0x0000ffff,		/* Dest Mask.  */
++          TRUE), 		/* PC relative offset?  */
++
+    /* A 64 bit GOT relocation.  Table-entry not really used.  */
+    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
+           0,			/* Rightshift.  */
+@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd *
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
++    case BFD_RELOC_MICROBLAZE_64:
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
+       break;
++    case BFD_RELOC_MICROBLAZE_64_GPC:
++      microblaze_reloc = R_MICROBLAZE_GPC_64;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_GOT:
+       microblaze_reloc = R_MICROBLAZE_GOT_64;
+       break;
+@@ -1172,6 +1208,7 @@ microblaze_elf_relocate_section (bfd *ou
+ 	      break; /* Do nothing.  */
+ 
+ 	    case (int) R_MICROBLAZE_GOTPC_64:
++	    case (int) R_MICROBLAZE_GPC_64:
+ 	      relocation = htab->sgotplt->output_section->vma
+ 		+ htab->sgotplt->output_offset;
+ 	      relocation -= (input_section->output_section->vma
+@@ -1443,7 +1480,7 @@ microblaze_elf_relocate_section (bfd *ou
+ 		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
+ 		  {
+ 		    relocation += addend;
+-		    if (r_type == R_MICROBLAZE_32)
++		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
+ 		      bfd_put_32 (input_bfd, relocation, contents + offset);
+ 		    else
+ 		      {
+@@ -1889,6 +1926,28 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
+ 	        }
+ 	      break;
++	    case R_MICROBLAZE_IMML_64:
++	      {
++	        /* This was a PC-relative instruction that was
++ 		   completely resolved.  */
++	        int sfix, efix;
++            unsigned int val;
++	        bfd_vma target_address;
++	        target_address = irel->r_addend + irel->r_offset;
++	        sfix = calc_fixup (irel->r_offset, 0, sec);
++	        efix = calc_fixup (target_address, 0, sec);
++
++            /* Validate the in-band val.  */
++            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
++               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
++            }
++	        irel->r_addend -= (efix - sfix);
++	        /* Should use HOWTO.  */
++	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
++	                                           irel->r_addend);
++	      }
++	      break;
+ 	    case R_MICROBLAZE_NONE:
+ 	    case R_MICROBLAZE_32_NONE:
+ 	      {
+Index: gdb-9.2/bfd/libbfd.h
+===================================================================
+--- gdb-9.2.orig/bfd/libbfd.h
++++ gdb-9.2/bfd/libbfd.h
+@@ -2905,7 +2905,9 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
++  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
++  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+Index: gdb-9.2/bfd/reloc.c
+===================================================================
+--- gdb-9.2.orig/bfd/reloc.c
++++ gdb-9.2/bfd/reloc.c
+@@ -6815,6 +6815,12 @@ ENUMDOC
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64
++ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+@@ -6822,6 +6828,12 @@ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imml instruction).  No relocation is
++  done here - only used for relaxing
++ENUM
++  BFD_RELOC_MICROBLAZE_64_GPC
++ENUMDOC
++  This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+   PC-relative GOT offset
+ ENUM
+Index: gdb-9.2/include/elf/microblaze.h
+===================================================================
+--- gdb-9.2.orig/include/elf/microblaze.h
++++ gdb-9.2/include/elf/microblaze.h
+@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_relo
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
++  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
++  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
+    
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -282,10 +282,10 @@ struct op_code_struct
+   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+   {"msrclr",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94110000, OPCODE_MASK_H23N, msrclr, special_inst },
+-  {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, fadd, arithmetic_inst },
++  {"fadd",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000000, OPCODE_MASK_H4, mbi_fadd, arithmetic_inst },
+   {"frsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000080, OPCODE_MASK_H4, frsub, arithmetic_inst },
+-  {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, fmul, arithmetic_inst },
+-  {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, fdiv, arithmetic_inst },
++  {"fmul",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000100, OPCODE_MASK_H4, mbi_fmul, arithmetic_inst },
++  {"fdiv",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000180, OPCODE_MASK_H4, mbi_fdiv, arithmetic_inst },
+   {"fcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000210, OPCODE_MASK_H4, fcmp_lt, arithmetic_inst },
+   {"fcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000220, OPCODE_MASK_H4, fcmp_eq, arithmetic_inst },
+   {"fcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000230, OPCODE_MASK_H4, fcmp_le, arithmetic_inst },
+@@ -538,8 +538,8 @@ struct op_code_struct
+   {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
+   {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
+   {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
+-  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
+-  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
++  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
++  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
+   {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
+   {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
+   {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
+Index: gdb-9.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opcm.h
++++ gdb-9.2/opcodes/microblaze-opcm.h
+@@ -40,8 +40,8 @@ enum microblaze_instr
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
+-  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+-  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
++  sbi, shi, swi, sli, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   fint, fsqrt,
+   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch
deleted file mode 100644
index bda74adc41..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0015-intial-commit-of-MB-64-bit.patch
+++ /dev/null
@@ -1,4189 +0,0 @@
-From 48e5b2505d97ca936e9946c3945c72bdcfc1743e Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sun, 30 Sep 2018 16:28:28 +0530
-Subject: [PATCH 15/40] intial commit of MB 64-bit
-
----
- bfd/Makefile.am                    |    2 +
- bfd/Makefile.in                    |    3 +
- bfd/config.bfd                     |    4 +
- bfd/configure                      |    2 +
- bfd/configure.ac                   |    2 +
- bfd/cpu-microblaze.c               |   55 +-
- bfd/doc/Makefile.in                |    1 +
- bfd/elf64-microblaze.c             | 3560 ++++++++++++++++++++++++++++
- bfd/targets.c                      |    6 +
- include/elf/common.h               |    1 +
- ld/Makefile.am                     |    4 +
- ld/Makefile.in                     |    7 +
- ld/configure.tgt                   |    3 +
- ld/emulparams/elf64microblaze.sh   |   23 +
- ld/emulparams/elf64microblazeel.sh |   23 +
- opcodes/microblaze-dis.c           |   43 +-
- opcodes/microblaze-opc.h           |  162 +-
- opcodes/microblaze-opcm.h          |   20 +-
- 20 files changed, 4156 insertions(+), 43 deletions(-)
- create mode 100644 bfd/elf64-microblaze.c
- create mode 100644 ld/emulparams/elf64microblaze.sh
- create mode 100644 ld/emulparams/elf64microblazeel.sh
-
-diff --git a/bfd/Makefile.am b/bfd/Makefile.am
-index e5bd28f03f5..35ecb83a1a1 100644
---- a/bfd/Makefile.am
-+++ b/bfd/Makefile.am
-@@ -558,6 +558,7 @@ BFD64_BACKENDS = \
- 	elf64-ia64.lo \
- 	elf64-ia64-vms.lo \
- 	elfxx-ia64.lo \
-+	elf64-microblaze.lo \
- 	elfn32-mips.lo \
- 	elf64-mips.lo \
- 	elfxx-mips.lo \
-@@ -597,6 +598,7 @@ BFD64_BACKENDS_CFILES = \
- 	elf64-gen.c \
- 	elf64-hppa.c \
- 	elf64-ia64-vms.c \
-+	elf64-microblaze.c \
- 	elf64-mips.c \
- 	elf64-mmix.c \
- 	elf64-nfp.c \
-diff --git a/bfd/Makefile.in b/bfd/Makefile.in
-index 15334f10c55..89a2470ec8f 100644
---- a/bfd/Makefile.in
-+++ b/bfd/Makefile.in
-@@ -984,6 +984,7 @@ BFD64_BACKENDS = \
- 	elf64-ia64.lo \
- 	elf64-ia64-vms.lo \
- 	elfxx-ia64.lo \
-+	elf64-microblaze.lo \
- 	elfn32-mips.lo \
- 	elf64-mips.lo \
- 	elfxx-mips.lo \
-@@ -1023,6 +1024,7 @@ BFD64_BACKENDS_CFILES = \
- 	elf64-gen.c \
- 	elf64-hppa.c \
- 	elf64-ia64-vms.c \
-+	elf64-microblaze.c \
- 	elf64-mips.c \
- 	elf64-mmix.c \
- 	elf64-nfp.c \
-@@ -1504,6 +1506,7 @@ distclean-compile:
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-hppa.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64-vms.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-ia64.Plo@am__quote@
-+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-microblaze.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mips.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-mmix.Plo@am__quote@
- @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf64-nfp.Plo@am__quote@
-diff --git a/bfd/config.bfd b/bfd/config.bfd
-index 0a96927e0ed..1fcae568c36 100644
---- a/bfd/config.bfd
-+++ b/bfd/config.bfd
-@@ -842,11 +842,15 @@ case "${targ}" in
-   microblazeel*-*)
-     targ_defvec=microblaze_elf32_le_vec
-     targ_selvecs=microblaze_elf32_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
-   microblaze*-*)
-     targ_defvec=microblaze_elf32_vec
-     targ_selvecs=microblaze_elf32_le_vec
-+    targ64_selvecs=microblaze_elf64_vec
-+    targ64_selvecs=microblaze_elf64_le_vec
-     ;;
- 
- #ifdef BFD64
-diff --git a/bfd/configure b/bfd/configure
-index abd7b2a83e5..731c059eba0 100755
---- a/bfd/configure
-+++ b/bfd/configure
-@@ -14804,6 +14804,8 @@ do
-     metag_elf32_vec)		 tb="$tb elf32-metag.lo elf32.lo $elf" ;;
-     microblaze_elf32_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-     microblaze_elf32_le_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-+    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-     mips_ecoff_be_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_le_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_bele_vec)	 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-diff --git a/bfd/configure.ac b/bfd/configure.ac
-index 7eee83ae4d4..b87f6183b98 100644
---- a/bfd/configure.ac
-+++ b/bfd/configure.ac
-@@ -540,6 +540,8 @@ do
-     metag_elf32_vec)		 tb="$tb elf32-metag.lo elf32.lo $elf" ;;
-     microblaze_elf32_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-     microblaze_elf32_le_vec)	 tb="$tb elf32-microblaze.lo elf32.lo $elf" ;;
-+    microblaze_elf64_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-+    microblaze_elf64_le_vec)	 tb="$tb elf64-microblaze.lo elf64.lo $elf"; target_size=64 ;;
-     mips_ecoff_be_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_le_vec)		 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-     mips_ecoff_bele_vec)	 tb="$tb coff-mips.lo ecoff.lo $ecoff" ;;
-diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index 4e05d73f01b..4b48b310c6a 100644
---- a/bfd/cpu-microblaze.c
-+++ b/bfd/cpu-microblaze.c
-@@ -23,7 +23,25 @@
- #include "bfd.h"
- #include "libbfd.h"
- 
--const bfd_arch_info_type bfd_microblaze_arch =
-+const bfd_arch_info_type bfd_microblaze_arch[] =
-+{
-+#if BFD_DEFAULT_TARGET_SIZE == 64
-+{
-+  64,		  		/* 32 bits in a word.  */
-+  64,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  FALSE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  &bfd_microblaze_arch[1],  	/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+},
- {
-   32,				/* Bits in a word.  */
-   32,				/* Bits in an address.  */
-@@ -39,4 +57,39 @@ const bfd_arch_info_type bfd_microblaze_arch =
-   bfd_arch_default_fill,	/* Default fill.  */
-   NULL,				/* Next in list.  */
-   0 /* Maximum offset of a reloc from the start of an insn.  */
-+}
-+#else
-+{
-+  32,		  		/* 32 bits in a word.  */
-+  32,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  TRUE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  &bfd_microblaze_arch[1],   	/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+},
-+{
-+  64,		  		/* 32 bits in a word.  */
-+  64,		  		/* 32 bits in an address.  */
-+  8,		  		/* 8 bits in a byte.  */
-+  bfd_arch_microblaze, 		/* Architecture.  */
-+  0,		  		/* Machine number - 0 for now.  */
-+  "microblaze",	  		/* Architecture name.  */
-+  "MicroBlaze",	  		/* Printable name.  */
-+  3,		  		/* Section align power.  */
-+  FALSE,		  		/* Is this the default architecture ?  */
-+  bfd_default_compatible,	/* Architecture comparison function.  */
-+  bfd_default_scan,	   	/* String to architecture conversion.  */
-+  bfd_arch_default_fill,	/* Default fill.  */
-+  NULL,				/* Next in list.  */
-+  0 /* Maximum offset of a reloc from the start of an insn.  */
-+}
-+#endif
- };
-diff --git a/bfd/doc/Makefile.in b/bfd/doc/Makefile.in
-index 0115dfc406c..d75411d2af7 100644
---- a/bfd/doc/Makefile.in
-+++ b/bfd/doc/Makefile.in
-@@ -375,6 +375,7 @@ pdfdir = @pdfdir@
- prefix = @prefix@
- program_transform_name = @program_transform_name@
- psdir = @psdir@
-+runstatedir = @runstatedir@
- sbindir = @sbindir@
- sharedstatedir = @sharedstatedir@
- srcdir = @srcdir@
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-new file mode 100644
-index 00000000000..fa4b95e47e0
---- /dev/null
-+++ b/bfd/elf64-microblaze.c
-@@ -0,0 +1,3560 @@
-+/* Xilinx MicroBlaze-specific support for 32-bit ELF
-+
-+   Copyright (C) 2009-2016 Free Software Foundation, Inc.
-+
-+   This file is part of BFD, the Binary File Descriptor library.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program; if not, write to the
-+   Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
-+   Boston, MA 02110-1301, USA.  */
-+
-+
-+int dbg1 = 0;
-+
-+#include "sysdep.h"
-+#include "bfd.h"
-+#include "bfdlink.h"
-+#include "libbfd.h"
-+#include "elf-bfd.h"
-+#include "elf/microblaze.h"
-+#include <assert.h>
-+
-+#define	USE_RELA	/* Only USE_REL is actually significant, but this is
-+			   here are a reminder...  */
-+#define INST_WORD_SIZE 4
-+
-+static int ro_small_data_pointer = 0;
-+static int rw_small_data_pointer = 0;
-+
-+static reloc_howto_type * microblaze_elf_howto_table [(int) R_MICROBLAZE_max];
-+
-+static reloc_howto_type microblaze_elf_howto_raw[] =
-+{
-+   /* This reloc does nothing.  */
-+   HOWTO (R_MICROBLAZE_NONE,	/* Type.  */
-+          0,			/* Rightshift.  */
-+          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_NONE", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0,			/* Dest Mask.  */
-+          FALSE),		/* PC relative offset?  */
-+
-+   /* A standard 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A standard PCREL 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_PCREL,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_PCREL",   	/* Name.  */
-+          TRUE,			/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit PCREL relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_64_PCREL,/* Type.  */
-+          0,			/* Rightshift.  */
-+          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          64,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_64_PCREL", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* The low half of a PCREL 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_PCREL_LO,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_signed, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_32_PCREL_LO", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit relocation.  Table entry not really used.  */
-+   HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* The low half of a 32 bit relocation.  */
-+   HOWTO (R_MICROBLAZE_32_LO,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_signed, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_LO", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Read-only small data section relocation.  */
-+   HOWTO (R_MICROBLAZE_SRO32,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_SRO32", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Read-write small data area relocation.  */
-+   HOWTO (R_MICROBLAZE_SRW32,   /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_SRW32", /* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   HOWTO (R_MICROBLAZE_32_NONE,   /* Type.  */
-+          0,         /* Rightshift.  */
-+          2,            /* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,           /* Bitsize.  */
-+          TRUE,         /* PC_relative.  */
-+          0,           /* Bitpos.  */
-+          complain_overflow_bitfield,  /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_32_NONE",/* Name.  */
-+          FALSE,       /* Partial Inplace.  */
-+          0,          /* Source Mask.  */
-+          0,         /* Dest Mask.  */
-+          FALSE),       /* PC relative offset?  */
-+
-+   /* This reloc does nothing.  Used for relaxation.  */
-+   HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
-+          0,			/* Rightshift.  */
-+          3,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_64_NONE",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0,			/* Dest Mask.  */
-+          FALSE),		/* PC relative offset?  */
-+
-+   /* Symbol Op Symbol relocation.  */
-+   HOWTO (R_MICROBLAZE_32_SYM_OP_SYM,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          32,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_bitfield, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_32_SYM_OP_SYM",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0xffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* GNU extension to record C++ vtable hierarchy.  */
-+   HOWTO (R_MICROBLAZE_GNU_VTINHERIT, /* Type.  */
-+          0,                     /* Rightshift.  */
-+          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,                     /* Bitsize.  */
-+          FALSE,                 /* PC_relative.  */
-+          0,                     /* Bitpos.  */
-+          complain_overflow_dont,/* Complain on overflow.  */
-+          NULL,                  /* Special Function.  */
-+          "R_MICROBLAZE_GNU_VTINHERIT", /* Name.  */
-+          FALSE,                 /* Partial Inplace.  */
-+          0,                     /* Source Mask.  */
-+          0,                     /* Dest Mask.  */
-+          FALSE),                /* PC relative offset?  */
-+
-+   /* GNU extension to record C++ vtable member usage.  */
-+   HOWTO (R_MICROBLAZE_GNU_VTENTRY,   /* Type.  */
-+          0,                     /* Rightshift.  */
-+          2,                     /* Size (0 = byte, 1 = short, 2 = long).  */
-+          0,                     /* Bitsize.  */
-+          FALSE,                 /* PC_relative.  */
-+          0,                     /* Bitpos.  */
-+          complain_overflow_dont,/* Complain on overflow.  */
-+          _bfd_elf_rel_vtable_reloc_fn,  /* Special Function.  */
-+          "R_MICROBLAZE_GNU_VTENTRY", /* Name.  */
-+          FALSE,                 /* Partial Inplace.  */
-+          0,                     /* Source Mask.  */
-+          0,                     /* Dest Mask.  */
-+          FALSE),                /* PC relative offset?  */
-+
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GOTPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit GOT relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GOT_64",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit PLT relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_PLT_64,  /* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_PLT_64",/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_REL,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_REL", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_JUMP_SLOT,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_JUMP_SLOT", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /*  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GLOB_DAT,/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GLOB_DAT", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-+   /* A 64 bit GOT relative relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTOFF_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_GOTOFF_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* A 32 bit GOT relative relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GOTOFF_32,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GOTOFF_32", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* COPY relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_COPY,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          FALSE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_COPY", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-+   /* Marker relocs for TLS.  */
-+   HOWTO (R_MICROBLAZE_TLS,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc,	/* special_function */
-+	 "R_MICROBLAZE_TLS",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   HOWTO (R_MICROBLAZE_TLSGD,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSGD",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,			/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   HOWTO (R_MICROBLAZE_TLSLD,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSLD",		/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes the load module index of the load module that contains the
-+      definition of its TLS sym.  */
-+   HOWTO (R_MICROBLAZE_TLSDTPMOD32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPMOD32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a dtv-relative displacement, the difference between the value
-+      of sym+add and the base address of the thread-local storage block that
-+      contains the definition of sym, minus 0x8000.  Used for initializing GOT */
-+   HOWTO (R_MICROBLAZE_TLSDTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a dtv-relative displacement, the difference between the value
-+      of sym+add and the base address of the thread-local storage block that
-+      contains the definition of sym, minus 0x8000.  */
-+   HOWTO (R_MICROBLAZE_TLSDTPREL64,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSDTPREL64",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a tp-relative displacement, the difference between the value of
-+      sym+add and the value of the thread pointer (r13).  */
-+   HOWTO (R_MICROBLAZE_TLSGOTTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSGOTTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+   /* Computes a tp-relative displacement, the difference between the value of
-+      sym+add and the value of the thread pointer (r13).  */
-+   HOWTO (R_MICROBLAZE_TLSTPREL32,
-+	 0,			/* rightshift */
-+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
-+	 32,			/* bitsize */
-+	 FALSE,			/* pc_relative */
-+	 0,			/* bitpos */
-+	 complain_overflow_dont, /* complain_on_overflow */
-+	 bfd_elf_generic_reloc, /* special_function */
-+	 "R_MICROBLAZE_TLSTPREL32",	/* name */
-+	 FALSE,			/* partial_inplace */
-+	 0,			/* src_mask */
-+	 0x0000ffff,		/* dst_mask */
-+	 FALSE),		/* pcrel_offset */
-+
-+};
-+
-+#ifndef NUM_ELEM
-+#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
-+#endif
-+
-+/* Initialize the microblaze_elf_howto_table, so that linear accesses can be done.  */
-+
-+static void
-+microblaze_elf_howto_init (void)
-+{
-+  unsigned int i;
-+
-+  for (i = NUM_ELEM (microblaze_elf_howto_raw); i--;)
-+    {
-+      unsigned int type;
-+
-+      type = microblaze_elf_howto_raw[i].type;
-+
-+      BFD_ASSERT (type < NUM_ELEM (microblaze_elf_howto_table));
-+
-+      microblaze_elf_howto_table [type] = & microblaze_elf_howto_raw [i];
-+    }
-+}
-+
-+static reloc_howto_type *
-+microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-+				  bfd_reloc_code_real_type code)
-+{
-+  enum elf_microblaze_reloc_type microblaze_reloc = R_MICROBLAZE_NONE;
-+
-+  switch (code)
-+    {
-+    case BFD_RELOC_NONE:
-+      microblaze_reloc = R_MICROBLAZE_NONE;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_NONE:
-+      microblaze_reloc = R_MICROBLAZE_32_NONE;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_NONE:
-+      microblaze_reloc = R_MICROBLAZE_64_NONE;
-+      break;
-+    case BFD_RELOC_32:
-+      microblaze_reloc = R_MICROBLAZE_32;
-+      break;
-+      /* RVA is treated the same as 32 */
-+    case BFD_RELOC_RVA:
-+      microblaze_reloc = R_MICROBLAZE_32;
-+      break;
-+    case BFD_RELOC_32_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_32_PCREL;
-+      break;
-+    case BFD_RELOC_64_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_64_PCREL;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_LO_PCREL:
-+      microblaze_reloc = R_MICROBLAZE_32_PCREL_LO;
-+      break;
-+    case BFD_RELOC_64:
-+      microblaze_reloc = R_MICROBLAZE_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_LO:
-+      microblaze_reloc = R_MICROBLAZE_32_LO;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_ROSDA:
-+      microblaze_reloc = R_MICROBLAZE_SRO32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_RWSDA:
-+      microblaze_reloc = R_MICROBLAZE_SRW32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM:
-+      microblaze_reloc = R_MICROBLAZE_32_SYM_OP_SYM;
-+      break;
-+    case BFD_RELOC_VTABLE_INHERIT:
-+      microblaze_reloc = R_MICROBLAZE_GNU_VTINHERIT;
-+      break;
-+    case BFD_RELOC_VTABLE_ENTRY:
-+      microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOTPC:
-+      microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOT:
-+      microblaze_reloc = R_MICROBLAZE_GOT_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_PLT:
-+      microblaze_reloc = R_MICROBLAZE_PLT_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_GOTOFF:
-+      microblaze_reloc = R_MICROBLAZE_GOTOFF_64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_GOTOFF:
-+      microblaze_reloc = R_MICROBLAZE_GOTOFF_32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSGD:
-+      microblaze_reloc = R_MICROBLAZE_TLSGD;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSLD:
-+      microblaze_reloc = R_MICROBLAZE_TLSLD;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_TLSDTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSDTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPREL64;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_32_TLSDTPMOD:
-+      microblaze_reloc = R_MICROBLAZE_TLSDTPMOD32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSGOTTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_64_TLSTPREL:
-+      microblaze_reloc = R_MICROBLAZE_TLSTPREL32;
-+      break;
-+    case BFD_RELOC_MICROBLAZE_COPY:
-+      microblaze_reloc = R_MICROBLAZE_COPY;
-+      break;
-+    default:
-+      return (reloc_howto_type *) NULL;
-+    }
-+
-+  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
-+    /* Initialize howto table if needed.  */
-+    microblaze_elf_howto_init ();
-+
-+  return microblaze_elf_howto_table [(int) microblaze_reloc];
-+};
-+
-+static reloc_howto_type *
-+microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
-+				  const char *r_name)
-+{
-+  unsigned int i;
-+
-+  for (i = 0; i < NUM_ELEM (microblaze_elf_howto_raw); i++)
-+    if (microblaze_elf_howto_raw[i].name != NULL
-+	&& strcasecmp (microblaze_elf_howto_raw[i].name, r_name) == 0)
-+      return &microblaze_elf_howto_raw[i];
-+
-+  return NULL;
-+}
-+
-+/* Set the howto pointer for a RCE ELF reloc.  */
-+
-+static bfd_boolean
-+microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-+			      arelent * cache_ptr,
-+			      Elf_Internal_Rela * dst)
-+{
-+  unsigned int r_type;
-+
-+  if (!microblaze_elf_howto_table [R_MICROBLAZE_32])
-+    /* Initialize howto table if needed.  */
-+    microblaze_elf_howto_init ();
-+
-+  r_type = ELF64_R_TYPE (dst->r_info);
-+  if (r_type >= R_MICROBLAZE_max)
-+    {
-+      (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
-+			     abfd, r_type);
-+      bfd_set_error (bfd_error_bad_value);
-+      return FALSE;
-+    }
-+
-+  cache_ptr->howto = microblaze_elf_howto_table [r_type];
-+ return TRUE;
-+}
-+
-+/* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
-+
-+static bfd_boolean
-+microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
-+{
-+  if (name[0] == 'L' && name[1] == '.')
-+    return TRUE;
-+
-+  if (name[0] == '$' && name[1] == 'L')
-+    return TRUE;
-+
-+  /* With gcc, the labels go back to starting with '.', so we accept
-+     the generic ELF local label syntax as well.  */
-+  return _bfd_elf_is_local_label_name (abfd, name);
-+}
-+
-+/* The microblaze linker (like many others) needs to keep track of
-+   the number of relocs that it decides to copy as dynamic relocs in
-+   check_relocs for each symbol. This is so that it can later discard
-+   them if they are found to be unnecessary.  We store the information
-+   in a field extending the regular ELF linker hash table.  */
-+
-+struct elf64_mb_dyn_relocs
-+{
-+  struct elf64_mb_dyn_relocs *next;
-+
-+  /* The input section of the reloc.  */
-+  asection *sec;
-+
-+  /* Total number of relocs copied for the input section.  */
-+  bfd_size_type count;
-+
-+  /* Number of pc-relative relocs copied for the input section.  */
-+  bfd_size_type pc_count;
-+};
-+
-+/* ELF linker hash entry.  */
-+
-+struct elf64_mb_link_hash_entry
-+{
-+  struct elf_link_hash_entry elf;
-+
-+  /* Track dynamic relocs copied for this symbol.  */
-+  struct elf64_mb_dyn_relocs *dyn_relocs;
-+
-+  /* TLS Reference Types for the symbol; Updated by check_relocs */
-+#define TLS_GD     1  /* GD reloc. */
-+#define TLS_LD     2  /* LD reloc. */
-+#define TLS_TPREL  4  /* TPREL reloc, => IE. */
-+#define TLS_DTPREL 8  /* DTPREL reloc, => LD. */
-+#define TLS_TLS    16 /* Any TLS reloc.  */
-+  unsigned char tls_mask;
-+
-+};
-+
-+#define IS_TLS_GD(x)     (x == (TLS_TLS | TLS_GD))
-+#define IS_TLS_LD(x)     (x == (TLS_TLS | TLS_LD))
-+#define IS_TLS_DTPREL(x) (x == (TLS_TLS | TLS_DTPREL))
-+#define IS_TLS_NONE(x)   (x == 0)
-+
-+#define elf64_mb_hash_entry(ent) ((struct elf64_mb_link_hash_entry *)(ent))
-+
-+/* ELF linker hash table.  */
-+
-+struct elf64_mb_link_hash_table
-+{
-+  struct elf_link_hash_table elf;
-+
-+  /* Short-cuts to get to dynamic linker sections.  */
-+  asection *sgot;
-+  asection *sgotplt;
-+  asection *srelgot;
-+  asection *splt;
-+  asection *srelplt;
-+  asection *sdynbss;
-+  asection *srelbss;
-+
-+  /* Small local sym to section mapping cache.  */
-+  struct sym_cache sym_sec;
-+
-+  /* TLS Local Dynamic GOT Entry */
-+  union {
-+    bfd_signed_vma refcount;
-+    bfd_vma offset;
-+  } tlsld_got;
-+};
-+
-+/* Nonzero if this section has TLS related relocations.  */
-+#define has_tls_reloc sec_flg0
-+
-+/* Get the ELF linker hash table from a link_info structure.  */
-+
-+#define elf64_mb_hash_table(p)				\
-+  (elf_hash_table_id ((struct elf_link_hash_table *) ((p)->hash)) \
-+  == MICROBLAZE_ELF_DATA ? ((struct elf64_mb_link_hash_table *) ((p)->hash)) : NULL)
-+
-+/* Create an entry in a microblaze ELF linker hash table.  */
-+
-+static struct bfd_hash_entry *
-+link_hash_newfunc (struct bfd_hash_entry *entry,
-+		   struct bfd_hash_table *table,
-+		   const char *string)
-+{
-+  /* Allocate the structure if it has not already been allocated by a
-+     subclass.  */
-+  if (entry == NULL)
-+    {
-+      entry = bfd_hash_allocate (table,
-+				 sizeof (struct elf64_mb_link_hash_entry));
-+      if (entry == NULL)
-+	return entry;
-+    }
-+
-+  /* Call the allocation method of the superclass.  */
-+  entry = _bfd_elf_link_hash_newfunc (entry, table, string);
-+  if (entry != NULL)
-+    {
-+      struct elf64_mb_link_hash_entry *eh;
-+
-+      eh = (struct elf64_mb_link_hash_entry *) entry;
-+      eh->dyn_relocs = NULL;
-+      eh->tls_mask = 0;
-+    }
-+
-+  return entry;
-+}
-+
-+/* Create a mb ELF linker hash table.  */
-+
-+static struct bfd_link_hash_table *
-+microblaze_elf_link_hash_table_create (bfd *abfd)
-+{
-+  struct elf64_mb_link_hash_table *ret;
-+  bfd_size_type amt = sizeof (struct elf64_mb_link_hash_table);
-+
-+  ret = (struct elf64_mb_link_hash_table *) bfd_zmalloc (amt);
-+  if (ret == NULL)
-+    return NULL;
-+
-+  if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, link_hash_newfunc,
-+				      sizeof (struct elf64_mb_link_hash_entry),
-+				      MICROBLAZE_ELF_DATA))
-+    {
-+      free (ret);
-+      return NULL;
-+    }
-+
-+  return &ret->elf.root;
-+}
-+
-+/* Set the values of the small data pointers.  */
-+
-+static void
-+microblaze_elf_final_sdp (struct bfd_link_info *info)
-+{
-+  struct bfd_link_hash_entry *h;
-+
-+  h = bfd_link_hash_lookup (info->hash, RO_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
-+  if (h != (struct bfd_link_hash_entry *) NULL
-+      && h->type == bfd_link_hash_defined)
-+    ro_small_data_pointer = (h->u.def.value
-+                             + h->u.def.section->output_section->vma
-+                             + h->u.def.section->output_offset);
-+
-+  h = bfd_link_hash_lookup (info->hash, RW_SDA_ANCHOR_NAME, FALSE, FALSE, TRUE);
-+  if (h != (struct bfd_link_hash_entry *) NULL
-+      && h->type == bfd_link_hash_defined)
-+    rw_small_data_pointer = (h->u.def.value
-+                             + h->u.def.section->output_section->vma
-+                             + h->u.def.section->output_offset);
-+}
-+
-+static bfd_vma
-+dtprel_base (struct bfd_link_info *info)
-+{
-+  /* If tls_sec is NULL, we should have signalled an error already.  */
-+  if (elf_hash_table (info)->tls_sec == NULL)
-+    return 0;
-+  return elf_hash_table (info)->tls_sec->vma;
-+}
-+
-+/* The size of the thread control block.  */
-+#define TCB_SIZE	8
-+
-+/* Output a simple dynamic relocation into SRELOC.  */
-+
-+static void
-+microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
-+					  asection *sreloc,
-+					  unsigned long reloc_index,
-+					  unsigned long indx,
-+					  int r_type,
-+					  bfd_vma offset,
-+					  bfd_vma addend)
-+{
-+
-+  Elf_Internal_Rela rel;
-+
-+  rel.r_info = ELF64_R_INFO (indx, r_type);
-+  rel.r_offset = offset;
-+  rel.r_addend = addend;
-+
-+  bfd_elf64_swap_reloca_out (output_bfd, &rel,
-+              (sreloc->contents + reloc_index * sizeof (Elf64_External_Rela)));
-+}
-+
-+/* This code is taken from elf64-m32r.c
-+   There is some attempt to make this function usable for many architectures,
-+   both USE_REL and USE_RELA ['twould be nice if such a critter existed],
-+   if only to serve as a learning tool.
-+
-+   The RELOCATE_SECTION function is called by the new ELF backend linker
-+   to handle the relocations for a section.
-+
-+   The relocs are always passed as Rela structures; if the section
-+   actually uses Rel structures, the r_addend field will always be
-+   zero.
-+
-+   This function is responsible for adjust the section contents as
-+   necessary, and (if using Rela relocs and generating a
-+   relocatable output file) adjusting the reloc addend as
-+   necessary.
-+
-+   This function does not have to worry about setting the reloc
-+   address or the reloc symbol index.
-+
-+   LOCAL_SYMS is a pointer to the swapped in local symbols.
-+
-+   LOCAL_SECTIONS is an array giving the section in the input file
-+   corresponding to the st_shndx field of each local symbol.
-+
-+   The global hash table entry for the global symbols can be found
-+   via elf_sym_hashes (input_bfd).
-+
-+   When generating relocatable output, this function must handle
-+   STB_LOCAL/STT_SECTION symbols specially.  The output symbol is
-+   going to be the section symbol corresponding to the output
-+   section, which means that the addend must be adjusted
-+   accordingly.  */
-+
-+static bfd_boolean
-+microblaze_elf_relocate_section (bfd *output_bfd,
-+			         struct bfd_link_info *info,
-+			         bfd *input_bfd,
-+			         asection *input_section,
-+			         bfd_byte *contents,
-+			         Elf_Internal_Rela *relocs,
-+			         Elf_Internal_Sym *local_syms,
-+			         asection **local_sections)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  Elf_Internal_Shdr *symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
-+  struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
-+  Elf_Internal_Rela *rel, *relend;
-+  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
-+  /* Assume success.  */
-+  bfd_boolean ret = TRUE;
-+  asection *sreloc;
-+  bfd_vma *local_got_offsets;
-+  unsigned int tls_type;
-+
-+  if (!microblaze_elf_howto_table[R_MICROBLAZE_max-1])
-+    microblaze_elf_howto_init ();
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  local_got_offsets = elf_local_got_offsets (input_bfd);
-+
-+  sreloc = elf_section_data (input_section)->sreloc;
-+
-+  rel = relocs;
-+  relend = relocs + input_section->reloc_count;
-+  for (; rel < relend; rel++)
-+    {
-+      int r_type;
-+      reloc_howto_type *howto;
-+      unsigned long r_symndx;
-+      bfd_vma addend = rel->r_addend;
-+      bfd_vma offset = rel->r_offset;
-+      struct elf_link_hash_entry *h;
-+      Elf_Internal_Sym *sym;
-+      asection *sec;
-+      const char *sym_name;
-+      bfd_reloc_status_type r = bfd_reloc_ok;
-+      const char *errmsg = NULL;
-+      bfd_boolean unresolved_reloc = FALSE;
-+
-+      h = NULL;
-+      r_type = ELF64_R_TYPE (rel->r_info);
-+      tls_type = 0;
-+
-+      if (r_type < 0 || r_type >= (int) R_MICROBLAZE_max)
-+	{
-+	  (*_bfd_error_handler) (_("%s: unknown relocation type %d"),
-+				 bfd_get_filename (input_bfd), (int) r_type);
-+	  bfd_set_error (bfd_error_bad_value);
-+	  ret = FALSE;
-+	  continue;
-+	}
-+
-+      howto = microblaze_elf_howto_table[r_type];
-+      r_symndx = ELF64_R_SYM (rel->r_info);
-+
-+      if (bfd_link_relocatable (info))
-+	{
-+	  /* This is a relocatable link.  We don't have to change
-+	     anything, unless the reloc is against a section symbol,
-+	     in which case we have to adjust according to where the
-+	     section symbol winds up in the output section.  */
-+	  sec = NULL;
-+	  if (r_symndx >= symtab_hdr->sh_info)
-+	    /* External symbol.  */
-+	    continue;
-+
-+	  /* Local symbol.  */
-+	  sym = local_syms + r_symndx;
-+	  sym_name = "<local symbol>";
-+	  /* STT_SECTION: symbol is associated with a section.  */
-+	  if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
-+	    /* Symbol isn't associated with a section.  Nothing to do.  */
-+	    continue;
-+
-+	  sec = local_sections[r_symndx];
-+	  addend += sec->output_offset + sym->st_value;
-+#ifndef USE_REL
-+	  /* This can't be done for USE_REL because it doesn't mean anything
-+	     and elf_link_input_bfd asserts this stays zero.  */
-+	  /* rel->r_addend = addend; */
-+#endif
-+
-+#ifndef USE_REL
-+	  /* Addends are stored with relocs.  We're done.  */
-+	  continue;
-+#else /* USE_REL */
-+	  /* If partial_inplace, we need to store any additional addend
-+	     back in the section.  */
-+	  if (!howto->partial_inplace)
-+	    continue;
-+	  /* ??? Here is a nice place to call a special_function like handler.  */
-+	  r = _bfd_relocate_contents (howto, input_bfd, addend,
-+				      contents + offset);
-+#endif /* USE_REL */
-+	}
-+      else
-+	{
-+	  bfd_vma relocation;
-+
-+	  /* This is a final link.  */
-+	  sym = NULL;
-+	  sec = NULL;
-+	  unresolved_reloc = FALSE;
-+
-+	  if (r_symndx < symtab_hdr->sh_info)
-+	    {
-+	      /* Local symbol.  */
-+	      sym = local_syms + r_symndx;
-+	      sec = local_sections[r_symndx];
-+	      if (sec == 0)
-+		continue;
-+	      sym_name = "<local symbol>";
-+	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
-+	      /* r_addend may have changed if the reference section was
-+		 a merge section.  */
-+	      addend = rel->r_addend;
-+	    }
-+	  else
-+	    {
-+	      /* External symbol.  */
-+	      bfd_boolean warned ATTRIBUTE_UNUSED;
-+	      bfd_boolean ignored ATTRIBUTE_UNUSED;
-+
-+	      RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
-+				       r_symndx, symtab_hdr, sym_hashes,
-+				       h, sec, relocation,
-+				       unresolved_reloc, warned, ignored);
-+	      sym_name = h->root.root.string;
-+	    }
-+
-+	  /* Sanity check the address.  */
-+	  if (offset > bfd_get_section_limit (input_bfd, input_section))
-+	    {
-+	      r = bfd_reloc_outofrange;
-+	      goto check_reloc;
-+	    }
-+
-+	  switch ((int) r_type)
-+	    {
-+	    case (int) R_MICROBLAZE_SRO32 :
-+	      {
-+		const char *name;
-+
-+		/* Only relocate if the symbol is defined.  */
-+		if (sec)
-+		  {
-+		    name = bfd_section_name (sec);
-+
-+		    if (strcmp (name, ".sdata2") == 0
-+			|| strcmp (name, ".sbss2") == 0)
-+		      {
-+			if (ro_small_data_pointer == 0)
-+			  microblaze_elf_final_sdp (info);
-+			if (ro_small_data_pointer == 0)
-+			  {
-+			    ret = FALSE;
-+			    r = bfd_reloc_undefined;
-+			    goto check_reloc;
-+			  }
-+
-+			/* At this point `relocation' contains the object's
-+			   address.  */
-+			relocation -= ro_small_data_pointer;
-+			/* Now it contains the offset from _SDA2_BASE_.  */
-+			r = _bfd_final_link_relocate (howto, input_bfd,
-+						      input_section,
-+						      contents, offset,
-+						      relocation, addend);
-+		      }
-+		    else
-+		      {
-+			(*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
-+					       bfd_get_filename (input_bfd),
-+					       sym_name,
-+					       microblaze_elf_howto_table[(int) r_type]->name,
-+					       bfd_section_name (sec));
-+			/*bfd_set_error (bfd_error_bad_value); ??? why? */
-+			ret = FALSE;
-+			continue;
-+		      }
-+		  }
-+	      }
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_SRW32 :
-+	      {
-+		const char *name;
-+
-+		/* Only relocate if the symbol is defined.  */
-+		if (sec)
-+		  {
-+		    name = bfd_section_name (sec);
-+
-+		    if (strcmp (name, ".sdata") == 0
-+			|| strcmp (name, ".sbss") == 0)
-+		      {
-+			if (rw_small_data_pointer == 0)
-+			  microblaze_elf_final_sdp (info);
-+			if (rw_small_data_pointer == 0)
-+			  {
-+			    ret = FALSE;
-+			    r = bfd_reloc_undefined;
-+			    goto check_reloc;
-+			  }
-+
-+			/* At this point `relocation' contains the object's
-+			   address.  */
-+			relocation -= rw_small_data_pointer;
-+			/* Now it contains the offset from _SDA_BASE_.  */
-+			r = _bfd_final_link_relocate (howto, input_bfd,
-+						      input_section,
-+						      contents, offset,
-+						      relocation, addend);
-+		      }
-+		    else
-+		      {
-+			(*_bfd_error_handler) (_("%s: The target (%s) of an %s relocation is in the wrong section (%s)"),
-+					       bfd_get_filename (input_bfd),
-+					       sym_name,
-+					       microblaze_elf_howto_table[(int) r_type]->name,
-+					       bfd_section_name (sec));
-+			/*bfd_set_error (bfd_error_bad_value); ??? why? */
-+			ret = FALSE;
-+			continue;
-+		      }
-+		  }
-+	      }
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_32_SYM_OP_SYM:
-+	      break; /* Do nothing.  */
-+
-+	    case (int) R_MICROBLAZE_GOTPC_64:
-+	      relocation = htab->sgotplt->output_section->vma
-+		+ htab->sgotplt->output_offset;
-+	      relocation -= (input_section->output_section->vma
-+			     + input_section->output_offset
-+			     + offset + INST_WORD_SIZE);
-+	      relocation += addend;
-+	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+	                  contents + offset + endian);
-+	      bfd_put_16 (input_bfd, relocation & 0xffff,
-+	                  contents + offset + endian + INST_WORD_SIZE);
-+	      break;
-+
-+	    case (int) R_MICROBLAZE_PLT_64:
-+	      {
-+		bfd_vma immediate;
-+		if (htab->splt != NULL && h != NULL
-+		    && h->plt.offset != (bfd_vma) -1)
-+		  {
-+		    relocation = (htab->splt->output_section->vma
-+				  + htab->splt->output_offset
-+				  + h->plt.offset);
-+		    unresolved_reloc = FALSE;
-+		    immediate = relocation - (input_section->output_section->vma
-+					      + input_section->output_offset
-+					      + offset + INST_WORD_SIZE);
-+		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
-+		                contents + offset + endian);
-+		    bfd_put_16 (input_bfd, immediate & 0xffff,
-+		                contents + offset + endian + INST_WORD_SIZE);
-+		  }
-+		else
-+		  {
-+		    relocation -= (input_section->output_section->vma
-+				   + input_section->output_offset
-+				   + offset + INST_WORD_SIZE);
-+		    immediate = relocation;
-+		    bfd_put_16 (input_bfd, (immediate >> 16) & 0xffff,
-+		                contents + offset + endian);
-+		    bfd_put_16 (input_bfd, immediate & 0xffff,
-+		                contents + offset + endian + INST_WORD_SIZE);
-+		  }
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_TLSGD:
-+	      tls_type = (TLS_TLS | TLS_GD);
-+	      goto dogot;
-+	    case (int) R_MICROBLAZE_TLSLD:
-+	      tls_type = (TLS_TLS | TLS_LD);
-+              /* Fall through. */
-+	    dogot:
-+	    case (int) R_MICROBLAZE_GOT_64:
-+	      {
-+		bfd_vma *offp;
-+		bfd_vma off, off2;
-+		unsigned long indx;
-+		bfd_vma static_value;
-+
-+		bfd_boolean need_relocs = FALSE;
-+		if (htab->sgot == NULL)
-+		  abort ();
-+
-+		indx = 0;
-+		offp = NULL;
-+
-+		/* 1. Identify GOT Offset;
-+		   2. Compute Static Values
-+		   3. Process Module Id, Process Offset
-+		   4. Fixup Relocation with GOT offset value. */
-+
-+		/* 1. Determine GOT Offset to use : TLS_LD, global, local */
-+		if (IS_TLS_LD (tls_type))
-+		  offp = &htab->tlsld_got.offset;
-+		else if (h != NULL)
-+		  {
-+		    if (htab->sgotplt != NULL && h->got.offset != (bfd_vma) -1)
-+			offp = &h->got.offset;
-+		    else
-+			abort ();
-+		  }
-+		else
-+		  {
-+		    if (local_got_offsets == NULL)
-+		      abort ();
-+		    offp = &local_got_offsets[r_symndx];
-+		  }
-+
-+		if (!offp)
-+		  abort ();
-+
-+		off = (*offp) & ~1;
-+		off2 = off;
-+
-+		if (IS_TLS_LD(tls_type) || IS_TLS_GD(tls_type))
-+		  off2 = off + 4;
-+
-+		/* Symbol index to use for relocs */
-+		if (h != NULL)
-+		  {
-+		    bfd_boolean dyn =
-+			elf_hash_table (info)->dynamic_sections_created;
-+
-+		    if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
-+							 bfd_link_pic (info),
-+							 h)
-+			&& (!bfd_link_pic (info)
-+			    || !SYMBOL_REFERENCES_LOCAL (info, h)))
-+		      indx = h->dynindx;
-+		  }
-+
-+		/* Need to generate relocs ? */
-+		if ((bfd_link_pic (info) || indx != 0)
-+		    && (h == NULL
-+		    || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-+		    || h->root.type != bfd_link_hash_undefweak))
-+		  need_relocs = TRUE;
-+
-+		/* 2. Compute/Emit Static value of r-expression */
-+		static_value = relocation + addend;
-+
-+		/* 3. Process module-id and offset */
-+		if (! ((*offp) & 1) )
-+		  {
-+		    bfd_vma got_offset;
-+
-+		    got_offset = (htab->sgot->output_section->vma
-+				  + htab->sgot->output_offset
-+				  + off);
-+
-+		    /* Process module-id */
-+		    if (IS_TLS_LD(tls_type))
-+		      {
-+			if (! bfd_link_pic (info))
-+			  {
-+			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
-+			  }
-+			else
-+			  {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot, htab->srelgot->reloc_count++,
-+			      /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
-+			      got_offset, 0);
-+			  }
-+		      }
-+		    else if (IS_TLS_GD(tls_type))
-+		      {
-+		        if (! need_relocs)
-+			  {
-+			    bfd_put_32 (output_bfd, 1, htab->sgot->contents + off);
-+			  }
-+		        else
-+			  {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot,
-+			      htab->srelgot->reloc_count++,
-+			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
-+			      got_offset, indx ? 0 : static_value);
-+			  }
-+		      }
-+
-+		    /* Process Offset */
-+		    if (htab->srelgot == NULL)
-+		      abort ();
-+
-+		    got_offset = (htab->sgot->output_section->vma
-+				  + htab->sgot->output_offset
-+				  + off2);
-+		    if (IS_TLS_LD(tls_type))
-+		      {
-+		        /* For LD, offset should be 0 */
-+		        *offp |= 1;
-+		        bfd_put_32 (output_bfd, 0, htab->sgot->contents + off2);
-+		      }
-+		    else if (IS_TLS_GD(tls_type))
-+		      {
-+		        *offp |= 1;
-+		        static_value -= dtprel_base(info);
-+		        if (need_relocs)
-+		          {
-+			    microblaze_elf_output_dynamic_relocation (output_bfd,
-+			      htab->srelgot, htab->srelgot->reloc_count++,
-+			      /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
-+			      got_offset, indx ? 0 : static_value);
-+		          }
-+		        else
-+			  {
-+			    bfd_put_32 (output_bfd, static_value,
-+					htab->sgot->contents + off2);
-+		          }
-+		      }
-+		    else
-+		      {
-+			  bfd_put_32 (output_bfd, static_value,
-+				      htab->sgot->contents + off2);
-+
-+			  /* Relocs for dyn symbols generated by
-+			     finish_dynamic_symbols */
-+			  if (bfd_link_pic (info) && h == NULL)
-+			    {
-+			      *offp |= 1;
-+			      microblaze_elf_output_dynamic_relocation (output_bfd,
-+				htab->srelgot, htab->srelgot->reloc_count++,
-+				/* symindex= */ indx, R_MICROBLAZE_REL,
-+				got_offset, static_value);
-+			    }
-+		      }
-+		  }
-+
-+		/* 4. Fixup Relocation with GOT offset value
-+		      Compute relative address of GOT entry for applying
-+		      the current relocation */
-+		relocation = htab->sgot->output_section->vma
-+			     + htab->sgot->output_offset
-+			     + off
-+			     - htab->sgotplt->output_section->vma
-+			     - htab->sgotplt->output_offset;
-+
-+		/* Apply Current Relocation */
-+		bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+		            contents + offset + endian);
-+		bfd_put_16 (input_bfd, relocation & 0xffff,
-+		            contents + offset + endian + INST_WORD_SIZE);
-+
-+		unresolved_reloc = FALSE;
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_GOTOFF_64:
-+	      {
-+		bfd_vma immediate;
-+		unsigned short lo, high;
-+		relocation += addend;
-+		relocation -= htab->sgotplt->output_section->vma
-+		  + htab->sgotplt->output_offset;
-+		/* Write this value into correct location.  */
-+		immediate = relocation;
-+		lo = immediate & 0x0000ffff;
-+		high = (immediate >> 16) & 0x0000ffff;
-+		bfd_put_16 (input_bfd, high, contents + offset + endian);
-+		bfd_put_16 (input_bfd, lo, contents + offset + INST_WORD_SIZE + endian);
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_GOTOFF_32:
-+	      {
-+		relocation += addend;
-+		relocation -= htab->sgotplt->output_section->vma
-+		  + htab->sgotplt->output_offset;
-+		/* Write this value into correct location.  */
-+		bfd_put_32 (input_bfd, relocation, contents + offset);
-+		break;
-+	      }
-+
-+	    case (int) R_MICROBLAZE_TLSDTPREL64:
-+	      relocation += addend;
-+	      relocation -= dtprel_base(info);
-+	      bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			  contents + offset + endian);
-+	      bfd_put_16 (input_bfd, relocation & 0xffff,
-+			  contents + offset + endian + INST_WORD_SIZE);
-+	      break;
-+	    case (int) R_MICROBLAZE_64_PCREL :
-+	    case (int) R_MICROBLAZE_64:
-+	    case (int) R_MICROBLAZE_32:
-+	      {
-+		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
-+		   from removed linkonce sections, or sections discarded by
-+		   a linker script.  */
-+		if (r_symndx == STN_UNDEF || (input_section->flags & SEC_ALLOC) == 0)
-+		  {
-+		    relocation += addend;
-+		    if (r_type == R_MICROBLAZE_32)
-+		      bfd_put_32 (input_bfd, relocation, contents + offset);
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_64_PCREL)
-+			  relocation -= (input_section->output_section->vma
-+					 + input_section->output_offset
-+					 + offset + INST_WORD_SIZE);
-+			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			            contents + offset + endian);
-+			bfd_put_16 (input_bfd, relocation & 0xffff,
-+			            contents + offset + endian + INST_WORD_SIZE);
-+		      }
-+		    break;
-+		  }
-+
-+		if ((bfd_link_pic (info)
-+		     && (h == NULL
-+			 || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
-+			 || h->root.type != bfd_link_hash_undefweak)
-+		     && (!howto->pc_relative
-+			 || (h != NULL
-+			     && h->dynindx != -1
-+			     && (!info->symbolic
-+				 || !h->def_regular))))
-+		    || (!bfd_link_pic (info)
-+			&& h != NULL
-+			&& h->dynindx != -1
-+			&& !h->non_got_ref
-+			&& ((h->def_dynamic
-+			     && !h->def_regular)
-+			    || h->root.type == bfd_link_hash_undefweak
-+			    || h->root.type == bfd_link_hash_undefined)))
-+		  {
-+		    Elf_Internal_Rela outrel;
-+		    bfd_byte *loc;
-+		    bfd_boolean skip;
-+
-+		    /* When generating a shared object, these relocations
-+		       are copied into the output file to be resolved at run
-+		       time.  */
-+
-+		    BFD_ASSERT (sreloc != NULL);
-+
-+		    skip = FALSE;
-+
-+		    outrel.r_offset =
-+		      _bfd_elf_section_offset (output_bfd, info, input_section,
-+					       rel->r_offset);
-+		    if (outrel.r_offset == (bfd_vma) -1)
-+		      skip = TRUE;
-+		    else if (outrel.r_offset == (bfd_vma) -2)
-+		      skip = TRUE;
-+		    outrel.r_offset += (input_section->output_section->vma
-+					+ input_section->output_offset);
-+
-+		    if (skip)
-+		      memset (&outrel, 0, sizeof outrel);
-+		    /* h->dynindx may be -1 if the symbol was marked to
-+		       become local.  */
-+		    else if (h != NULL
-+			     && ((! info->symbolic && h->dynindx != -1)
-+				 || !h->def_regular))
-+		      {
-+			BFD_ASSERT (h->dynindx != -1);
-+			outrel.r_info = ELF64_R_INFO (h->dynindx, r_type);
-+			outrel.r_addend = addend;
-+		      }
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_32)
-+			  {
-+			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
-+			    outrel.r_addend = relocation + addend;
-+			  }
-+			else
-+			  {
-+			    BFD_FAIL ();
-+			    (*_bfd_error_handler)
-+			      (_("%pB: probably compiled without -fPIC?"),
-+			       input_bfd);
-+			    bfd_set_error (bfd_error_bad_value);
-+			    return FALSE;
-+			  }
-+		      }
-+
-+		    loc = sreloc->contents;
-+		    loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-+		    bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
-+		    break;
-+		  }
-+		else
-+		  {
-+		    relocation += addend;
-+		    if (r_type == R_MICROBLAZE_32)
-+		      bfd_put_32 (input_bfd, relocation, contents + offset);
-+		    else
-+		      {
-+			if (r_type == R_MICROBLAZE_64_PCREL)
-+			  relocation -= (input_section->output_section->vma
-+					 + input_section->output_offset
-+					 + offset + INST_WORD_SIZE);
-+			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			            contents + offset + endian);
-+			bfd_put_16 (input_bfd, relocation & 0xffff,
-+			            contents + offset + endian + INST_WORD_SIZE);
-+		      }
-+		    break;
-+		  }
-+	      }
-+
-+	    default :
-+	      r = _bfd_final_link_relocate (howto, input_bfd, input_section,
-+					    contents, offset,
-+					    relocation, addend);
-+	      break;
-+	    }
-+	}
-+
-+    check_reloc:
-+
-+      if (r != bfd_reloc_ok)
-+	{
-+	  /* FIXME: This should be generic enough to go in a utility.  */
-+	  const char *name;
-+
-+	  if (h != NULL)
-+	    name = h->root.root.string;
-+	  else
-+	    {
-+	      name = (bfd_elf_string_from_elf_section
-+		      (input_bfd, symtab_hdr->sh_link, sym->st_name));
-+	      if (name == NULL || *name == '\0')
-+		name = bfd_section_name (sec);
-+	    }
-+
-+	  if (errmsg != NULL)
-+	    goto common_error;
-+
-+	  switch (r)
-+	    {
-+	    case bfd_reloc_overflow:
-+	      (*info->callbacks->reloc_overflow)
-+		(info, (h ? &h->root : NULL), name, howto->name,
-+		 (bfd_vma) 0, input_bfd, input_section, offset);
-+	      break;
-+
-+	    case bfd_reloc_undefined:
-+	      (*info->callbacks->undefined_symbol)
-+		(info, name, input_bfd, input_section, offset, TRUE);
-+	      break;
-+
-+	    case bfd_reloc_outofrange:
-+	      errmsg = _("internal error: out of range error");
-+	      goto common_error;
-+
-+	    case bfd_reloc_notsupported:
-+	      errmsg = _("internal error: unsupported relocation error");
-+	      goto common_error;
-+
-+	    case bfd_reloc_dangerous:
-+	      errmsg = _("internal error: dangerous error");
-+	      goto common_error;
-+
-+	    default:
-+	      errmsg = _("internal error: unknown error");
-+	      /* Fall through.  */
-+	    common_error:
-+	      (*info->callbacks->warning) (info, errmsg, name, input_bfd,
-+					   input_section, offset);
-+	      break;
-+	    }
-+	}
-+    }
-+
-+  return ret;
-+}
-+
-+/* Calculate fixup value for reference.  */
-+
-+static int
-+calc_fixup (bfd_vma start, bfd_vma size, asection *sec)
-+{
-+  bfd_vma end = start + size;
-+  int i, fixup = 0;
-+
-+  if (sec == NULL || sec->relax == NULL)
-+    return 0;
-+
-+  /* Look for addr in relax table, total fixup value.  */
-+  for (i = 0; i < sec->relax_count; i++)
-+    {
-+      if (end <= sec->relax[i].addr)
-+        break;
-+      if ((end != start) && (start > sec->relax[i].addr))
-+        continue;
-+      fixup += sec->relax[i].size;
-+    }
-+  return fixup;
-+}
-+
-+/* Read-modify-write into the bfd, an immediate value into appropriate fields of
-+   a 32-bit instruction.  */
-+static void
-+microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-+{
-+    unsigned long instr = bfd_get_32 (abfd, bfd_addr);
-+    instr &= ~0x0000ffff;
-+    instr |= (val & 0x0000ffff);
-+    bfd_put_32 (abfd, instr, bfd_addr);
-+}
-+
-+/* Read-modify-write into the bfd, an immediate value into appropriate fields of
-+   two consecutive 32-bit instructions.  */
-+static void
-+microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-+{
-+    unsigned long instr_hi;
-+    unsigned long instr_lo;
-+
-+    instr_hi = bfd_get_32 (abfd, bfd_addr);
-+    instr_hi &= ~0x0000ffff;
-+    instr_hi |= ((val >> 16) & 0x0000ffff);
-+    bfd_put_32 (abfd, instr_hi, bfd_addr);
-+
-+    instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
-+    instr_lo &= ~0x0000ffff;
-+    instr_lo |= (val & 0x0000ffff);
-+    bfd_put_32 (abfd, instr_lo, bfd_addr + INST_WORD_SIZE);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_relax_section (bfd *abfd,
-+			      asection *sec,
-+			      struct bfd_link_info *link_info,
-+			      bfd_boolean *again)
-+{
-+  Elf_Internal_Shdr *symtab_hdr;
-+  Elf_Internal_Rela *internal_relocs;
-+  Elf_Internal_Rela *free_relocs = NULL;
-+  Elf_Internal_Rela *irel, *irelend;
-+  bfd_byte *contents = NULL;
-+  bfd_byte *free_contents = NULL;
-+  int rel_count;
-+  unsigned int shndx;
-+  int i, sym_index;
-+  asection *o;
-+  struct elf_link_hash_entry *sym_hash;
-+  Elf_Internal_Sym *isymbuf, *isymend;
-+  Elf_Internal_Sym *isym;
-+  int symcount;
-+  int offset;
-+  bfd_vma src, dest;
-+
-+  /* We only do this once per section.  We may be able to delete some code
-+     by running multiple passes, but it is not worth it.  */
-+  *again = FALSE;
-+
-+  /* Only do this for a text section.  */
-+  if (bfd_link_relocatable (link_info)
-+      || (sec->flags & SEC_RELOC) == 0
-+      || (sec->reloc_count == 0)
-+      || (sec->flags & SEC_CODE) == 0)
-+    return TRUE;
-+
-+  BFD_ASSERT ((sec->size > 0) || (sec->rawsize > 0));
-+
-+  /* If this is the first time we have been called for this section,
-+     initialize the cooked size.  */
-+  if (sec->size == 0)
-+    sec->size = sec->rawsize;
-+
-+  /* Get symbols for this section.  */
-+  symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
-+  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
-+  symcount =  symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
-+  if (isymbuf == NULL)
-+    isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr, symcount,
-+ 			     	    0, NULL, NULL, NULL);
-+  BFD_ASSERT (isymbuf != NULL);
-+
-+  internal_relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, link_info->keep_memory);
-+  if (internal_relocs == NULL)
-+    goto error_return;
-+  if (! link_info->keep_memory)
-+    free_relocs = internal_relocs;
-+
-+  sec->relax = (struct relax_table *) bfd_malloc ((sec->reloc_count + 1)
-+						  * sizeof (struct relax_table));
-+  if (sec->relax == NULL)
-+    goto error_return;
-+  sec->relax_count = 0;
-+
-+  irelend = internal_relocs + sec->reloc_count;
-+  rel_count = 0;
-+  for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
-+    {
-+      bfd_vma symval;
-+      if ((ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64_PCREL)
-+	  && (ELF64_R_TYPE (irel->r_info) != (int) R_MICROBLAZE_64 ))
-+	continue; /* Can't delete this reloc.  */
-+
-+      /* Get the section contents.  */
-+      if (contents == NULL)
-+	{
-+	  if (elf_section_data (sec)->this_hdr.contents != NULL)
-+	    contents = elf_section_data (sec)->this_hdr.contents;
-+	  else
-+	    {
-+	      contents = (bfd_byte *) bfd_malloc (sec->size);
-+	      if (contents == NULL)
-+		goto error_return;
-+	      free_contents = contents;
-+
-+	      if (!bfd_get_section_contents (abfd, sec, contents,
-+					     (file_ptr) 0, sec->size))
-+		goto error_return;
-+              elf_section_data (sec)->this_hdr.contents = contents;
-+	    }
-+	}
-+
-+      /* Get the value of the symbol referred to by the reloc.  */
-+      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
-+	{
-+	  /* A local symbol.  */
-+	  asection *sym_sec;
-+
-+	  isym = isymbuf + ELF64_R_SYM (irel->r_info);
-+          if (isym->st_shndx == SHN_UNDEF)
-+	    sym_sec = bfd_und_section_ptr;
-+	  else if (isym->st_shndx == SHN_ABS)
-+	    sym_sec = bfd_abs_section_ptr;
-+	  else if (isym->st_shndx == SHN_COMMON)
-+	    sym_sec = bfd_com_section_ptr;
-+	  else
-+	    sym_sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
-+
-+	  symval = _bfd_elf_rela_local_sym (abfd, isym, &sym_sec, irel);
-+	}
-+      else
-+	{
-+	  unsigned long indx;
-+	  struct elf_link_hash_entry *h;
-+
-+	  indx = ELF64_R_SYM (irel->r_info) - symtab_hdr->sh_info;
-+	  h = elf_sym_hashes (abfd)[indx];
-+	  BFD_ASSERT (h != NULL);
-+
-+          if (h->root.type != bfd_link_hash_defined
-+	      && h->root.type != bfd_link_hash_defweak)
-+	    /* This appears to be a reference to an undefined
-+	       symbol.  Just ignore it--it will be caught by the
-+	       regular reloc processing.  */
-+	    continue;
-+
-+	  symval = (h->root.u.def.value
-+		    + h->root.u.def.section->output_section->vma
-+		    + h->root.u.def.section->output_offset);
-+	}
-+
-+      /* If this is a PC-relative reloc, subtract the instr offset from
-+         the symbol value.  */
-+      if (ELF64_R_TYPE (irel->r_info) == (int) R_MICROBLAZE_64_PCREL)
-+	{
-+	  symval = symval + irel->r_addend
-+	    - (irel->r_offset
-+	       + sec->output_section->vma
-+	       + sec->output_offset);
-+        }
-+      else
-+	symval += irel->r_addend;
-+
-+      if ((symval & 0xffff8000) == 0)
-+	{
-+          /* We can delete this instruction.  */
-+	  sec->relax[sec->relax_count].addr = irel->r_offset;
-+	  sec->relax[sec->relax_count].size = INST_WORD_SIZE;
-+	  sec->relax_count++;
-+
-+	  /* Rewrite relocation type.  */
-+          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
-+	    {
-+	    case R_MICROBLAZE_64_PCREL:
-+	      irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
-+                                           (int) R_MICROBLAZE_32_PCREL_LO);
-+	      break;
-+	    case R_MICROBLAZE_64:
-+              irel->r_info = ELF64_R_INFO (ELF64_R_SYM (irel->r_info),
-+                                           (int) R_MICROBLAZE_32_LO);
-+	      break;
-+	    default:
-+	      /* Cannot happen.  */
-+	      BFD_ASSERT (FALSE);
-+            }
-+        }
-+    } /* Loop through all relocations.  */
-+
-+  /* Loop through the relocs again, and see if anything needs to change.  */
-+  if (sec->relax_count > 0)
-+    {
-+      shndx = _bfd_elf_section_from_bfd_section (abfd, sec);
-+      rel_count = 0;
-+      sec->relax[sec->relax_count].addr = sec->size;
-+
-+      for (irel = internal_relocs; irel < irelend; irel++, rel_count++)
-+        {
-+	  bfd_vma nraddr;
-+
-+          /* Get the new reloc address.  */
-+	  nraddr = irel->r_offset - calc_fixup (irel->r_offset, 0, sec);
-+          switch ((enum elf_microblaze_reloc_type) ELF64_R_TYPE (irel->r_info))
-+	    {
-+	    default:
-+	      break;
-+	    case R_MICROBLAZE_64_PCREL:
-+	      break;
-+	    case R_MICROBLAZE_64:
-+	    case R_MICROBLAZE_32_LO:
-+	      /* If this reloc is against a symbol defined in this
-+	         section, we must check the addend to see it will put the value in
-+	         range to be adjusted, and hence must be changed.  */
-+	      if (ELF64_R_SYM (irel->r_info) < symtab_hdr->sh_info)
-+	        {
-+		  isym = isymbuf + ELF64_R_SYM (irel->r_info);
-+		  /* Only handle relocs against .text.  */
-+		  if (isym->st_shndx == shndx
-+		      && ELF64_ST_TYPE (isym->st_info) == STT_SECTION)
-+		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
-+	        }
-+	      break;
-+	    case R_MICROBLAZE_NONE:
-+	    case R_MICROBLAZE_32_NONE:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+ 		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
-+	    case R_MICROBLAZE_64_NONE:
-+	      {
-+	        /* This was a PC-relative 64-bit instruction that was
-+ 		   completely resolved.  */
-+	        int sfix, efix;
-+	        bfd_vma target_address;
-+		target_address = irel->r_addend + irel->r_offset + INST_WORD_SIZE;
-+		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
-+		efix = calc_fixup (target_address, 0, sec);
-+		irel->r_addend -= (efix - sfix);
-+    microblaze_bfd_write_imm_value_32 (abfd, contents + irel->r_offset
-+                                       + INST_WORD_SIZE, irel->r_addend);
-+	      }
-+	      break;
-+	    }
-+          irel->r_offset = nraddr;
-+        } /* Change all relocs in this section.  */
-+
-+      /* Look through all other sections.  */
-+      for (o = abfd->sections; o != NULL; o = o->next)
-+        {
-+          Elf_Internal_Rela *irelocs;
-+          Elf_Internal_Rela *irelscan, *irelscanend;
-+          bfd_byte *ocontents;
-+
-+          if (o == sec
-+              || (o->flags & SEC_RELOC) == 0
-+              || o->reloc_count == 0)
-+            continue;
-+
-+          /* We always cache the relocs.  Perhaps, if info->keep_memory is
-+             FALSE, we should free them, if we are permitted to.  */
-+
-+          irelocs = _bfd_elf_link_read_relocs (abfd, o, NULL, NULL, TRUE);
-+          if (irelocs == NULL)
-+            goto error_return;
-+
-+          ocontents = NULL;
-+          irelscanend = irelocs + o->reloc_count;
-+          for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
-+            {
-+              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_NONE)
-+                {
-+                  unsigned int val;
-+
-+                  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+                  /* hax: We only do the following fixup for debug location lists.  */
-+                  if (strcmp(".debug_loc", o->name))
-+                    continue;
-+
-+                  /* This was a PC-relative instruction that was completely resolved.  */
-+                  if (ocontents == NULL)
-+                    {
-+		      if (elf_section_data (o)->this_hdr.contents != NULL)
-+		          ocontents = elf_section_data (o)->this_hdr.contents;
-+		      else
-+		        {
-+		          /* We always cache the section contents.
-+			     Perhaps, if info->keep_memory is FALSE, we
-+			     should free them, if we are permitted to.  */
-+
-+		          if (o->rawsize == 0)
-+			      o->rawsize = o->size;
-+		          ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+		          if (ocontents == NULL)
-+			      goto error_return;
-+		          if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                         (file_ptr) 0,
-+                                                         o->rawsize))
-+                              goto error_return;
-+		          elf_section_data (o)->this_hdr.contents = ocontents;
-+		        }
-+		    }
-+
-+                  val = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+                  if (val != irelscan->r_addend) {
-+                    fprintf(stderr, "%d: CORRUPT relax reloc! %x %lx\n", __LINE__, val, irelscan->r_addend);
-+                  }
-+                  irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-+                  microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                                     irelscan->r_addend);
-+              }
-+              if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
-+                {
-+	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+                  /* Look at the reloc only if the value has been resolved.  */
-+                  if (isym->st_shndx == shndx
-+                      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+                    {
-+                      if (ocontents == NULL)
-+                        {
-+                          if (elf_section_data (o)->this_hdr.contents != NULL)
-+                            ocontents = elf_section_data (o)->this_hdr.contents;
-+                          else
-+                            {
-+                              /* We always cache the section contents.
-+                                 Perhaps, if info->keep_memory is FALSE, we
-+                                 should free them, if we are permitted to.  */
-+		              if (o->rawsize == 0)
-+			        o->rawsize = o->size;
-+                              ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+                              if (ocontents == NULL)
-+                                goto error_return;
-+                              if (!bfd_get_section_contents (abfd, o, ocontents,
-+                                                             (file_ptr) 0,
-+							     o->rawsize))
-+                                goto error_return;
-+                              elf_section_data (o)->this_hdr.contents = ocontents;
-+                            }
-+
-+                        }
-+		      irelscan->r_addend -= calc_fixup (irelscan->r_addend, 0, sec);
-+                    }
-+		  else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_SYM_OP_SYM)
-+		    {
-+		      isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		      /* Look at the reloc only if the value has been resolved.  */
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+              irelscan->r_addend -= calc_fixup (irelscan->r_addend
-+							+ isym->st_value,
-+							0,
-+							sec);
-+		    }
-+		}
-+	      else if ((ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_PCREL_LO)
-+		       || (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32_LO))
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+		      bfd_vma target_address;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+
-+		      unsigned long instr = bfd_get_32 (abfd, ocontents + irelscan->r_offset);
-+		      immediate = instr & 0x0000ffff;
-+		      target_address = immediate;
-+		      offset = calc_fixup (target_address, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+          microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-+                                             irelscan->r_addend);
-+		    }
-+		}
-+
-+	      if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64)
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset);
-+          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset
-+                                                + INST_WORD_SIZE);
-+          immediate = (instr_hi & 0x0000ffff) << 16;
-+          immediate |= (instr_lo & 0x0000ffff);
-+		      offset = calc_fixup (irelscan->r_addend, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+		    }
-+		}
-+	      else if (ELF64_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_64_PCREL)
-+		{
-+		  isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
-+
-+		  /* Look at the reloc only if the value has been resolved.  */
-+		  if (isym->st_shndx == shndx
-+		      && (ELF64_ST_TYPE (isym->st_info) == STT_SECTION))
-+		    {
-+		      bfd_vma immediate;
-+		      bfd_vma target_address;
-+
-+		      if (ocontents == NULL)
-+			{
-+			  if (elf_section_data (o)->this_hdr.contents != NULL)
-+			    ocontents = elf_section_data (o)->this_hdr.contents;
-+			  else
-+			    {
-+			      /* We always cache the section contents.
-+				 Perhaps, if info->keep_memory is FALSE, we
-+				 should free them, if we are permitted to.  */
-+			      if (o->rawsize == 0)
-+				o->rawsize = o->size;
-+			      ocontents = (bfd_byte *) bfd_malloc (o->rawsize);
-+			      if (ocontents == NULL)
-+				goto error_return;
-+			      if (!bfd_get_section_contents (abfd, o, ocontents,
-+							     (file_ptr) 0,
-+							     o->rawsize))
-+				goto error_return;
-+			      elf_section_data (o)->this_hdr.contents = ocontents;
-+			    }
-+			}
-+          unsigned long instr_hi =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset);
-+          unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
-+                                                + irelscan->r_offset
-+                                                + INST_WORD_SIZE);
-+          immediate = (instr_hi & 0x0000ffff) << 16;
-+          immediate |= (instr_lo & 0x0000ffff);
-+		      target_address = immediate;
-+		      offset = calc_fixup (target_address, 0, sec);
-+		      immediate -= offset;
-+		      irelscan->r_addend -= offset;
-+          microblaze_bfd_write_imm_value_64 (abfd, ocontents
-+                                             + irelscan->r_offset, immediate);
-+		    }
-+		}
-+            }
-+        }
-+
-+      /* Adjust the local symbols defined in this section.  */
-+      isymend = isymbuf + symtab_hdr->sh_info;
-+      for (isym = isymbuf; isym < isymend; isym++)
-+        {
-+          if (isym->st_shndx == shndx)
-+            {
-+              isym->st_value -= calc_fixup (isym->st_value, 0, sec);
-+              if (isym->st_size)
-+                isym->st_size -= calc_fixup (isym->st_value, isym->st_size, sec);
-+            }
-+        }
-+
-+      /* Now adjust the global symbols defined in this section.  */
-+      isym = isymbuf + symtab_hdr->sh_info;
-+      symcount =  (symtab_hdr->sh_size / sizeof (Elf64_External_Sym)) - symtab_hdr->sh_info;
-+      for (sym_index = 0; sym_index < symcount; sym_index++)
-+        {
-+          sym_hash = elf_sym_hashes (abfd)[sym_index];
-+          if ((sym_hash->root.type == bfd_link_hash_defined
-+                  || sym_hash->root.type == bfd_link_hash_defweak)
-+              && sym_hash->root.u.def.section == sec)
-+            {
-+              sym_hash->root.u.def.value -= calc_fixup (sym_hash->root.u.def.value,
-+                                                        0, sec);
-+              if (sym_hash->size)
-+                sym_hash->size -= calc_fixup (sym_hash->root.u.def.value,
-+                                              sym_hash->size, sec);
-+            }
-+        }
-+
-+      /* Physically move the code and change the cooked size.  */
-+      dest = sec->relax[0].addr;
-+      for (i = 0; i < sec->relax_count; i++)
-+        {
-+          int len;
-+          src = sec->relax[i].addr + sec->relax[i].size;
-+          len = sec->relax[i+1].addr - sec->relax[i].addr - sec->relax[i].size;
-+
-+          memmove (contents + dest, contents + src, len);
-+          sec->size -= sec->relax[i].size;
-+          dest += len;
-+        }
-+
-+      elf_section_data (sec)->relocs = internal_relocs;
-+      free_relocs = NULL;
-+
-+      elf_section_data (sec)->this_hdr.contents = contents;
-+      free_contents = NULL;
-+
-+      symtab_hdr->contents = (bfd_byte *) isymbuf;
-+    }
-+
-+  if (free_relocs != NULL)
-+    {
-+      free (free_relocs);
-+      free_relocs = NULL;
-+    }
-+
-+  if (free_contents != NULL)
-+    {
-+      if (!link_info->keep_memory)
-+	free (free_contents);
-+      else
-+	/* Cache the section contents for elf_link_input_bfd.  */
-+	elf_section_data (sec)->this_hdr.contents = contents;
-+      free_contents = NULL;
-+    }
-+
-+  if (sec->relax_count == 0)
-+    {
-+      *again = FALSE;
-+      free (sec->relax);
-+      sec->relax = NULL;
-+    }
-+  else
-+    *again = TRUE;
-+  return TRUE;
-+
-+ error_return:
-+  if (free_relocs != NULL)
-+    free (free_relocs);
-+  if (free_contents != NULL)
-+    free (free_contents);
-+  if (sec->relax != NULL)
-+    {
-+      free (sec->relax);
-+      sec->relax = NULL;
-+      sec->relax_count = 0;
-+    }
-+  return FALSE;
-+}
-+
-+/* Return the section that should be marked against GC for a given
-+   relocation.  */
-+
-+static asection *
-+microblaze_elf_gc_mark_hook (asection *sec,
-+			     struct bfd_link_info * info,
-+     			     Elf_Internal_Rela * rel,
-+     			     struct elf_link_hash_entry * h,
-+     			     Elf_Internal_Sym * sym)
-+{
-+  if (h != NULL)
-+    switch (ELF64_R_TYPE (rel->r_info))
-+      {
-+      case R_MICROBLAZE_GNU_VTINHERIT:
-+      case R_MICROBLAZE_GNU_VTENTRY:
-+	return NULL;
-+      }
-+
-+  return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
-+}
-+
-+/* PIC support.  */
-+
-+#define PLT_ENTRY_SIZE 16
-+
-+#define PLT_ENTRY_WORD_0  0xb0000000          /* "imm 0".  */
-+#define PLT_ENTRY_WORD_1  0xe9940000          /* "lwi r12,r20,0" - relocated to lwi r12,r20,func@GOT.  */
-+#define PLT_ENTRY_WORD_1_NOPIC  0xe9800000    /* "lwi r12,r0,0" - non-PIC object.  */
-+#define PLT_ENTRY_WORD_2  0x98186000          /* "brad r12".  */
-+#define PLT_ENTRY_WORD_3  0x80000000          /* "nop".  */
-+
-+/* Create .got, .gotplt, and .rela.got sections in DYNOBJ, and set up
-+   shortcuts to them in our hash table.  */
-+
-+static bfd_boolean
-+create_got_section (bfd *dynobj, struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  if (! _bfd_elf_create_got_section (dynobj, info))
-+    return FALSE;
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  htab->sgot = bfd_get_linker_section (dynobj, ".got");
-+  htab->sgotplt = bfd_get_linker_section (dynobj, ".got.plt");
-+  if (!htab->sgot || !htab->sgotplt)
-+    return FALSE;
-+
-+  if ((htab->srelgot = bfd_get_linker_section (dynobj, ".rela.got")) == NULL)
-+    htab->srelgot = bfd_make_section_anyway (dynobj, ".rela.got");
-+  if (htab->srelgot == NULL
-+      || ! bfd_set_section_flags (htab->srelgot, SEC_ALLOC
-+                                  | SEC_LOAD
-+                                  | SEC_HAS_CONTENTS
-+                                  | SEC_IN_MEMORY
-+                                  | SEC_LINKER_CREATED
-+                                  | SEC_READONLY)
-+      || ! bfd_set_section_alignment (htab->srelgot, 2))
-+    return FALSE;
-+  return TRUE;
-+}
-+
-+static bfd_boolean
-+update_local_sym_info (bfd *abfd,
-+		       Elf_Internal_Shdr *symtab_hdr,
-+		       unsigned long r_symndx,
-+		       unsigned int tls_type)
-+{
-+  bfd_signed_vma *local_got_refcounts = elf_local_got_refcounts (abfd);
-+  unsigned char *local_got_tls_masks;
-+
-+  if (local_got_refcounts == NULL)
-+    {
-+      bfd_size_type size = symtab_hdr->sh_info;
-+
-+      size *= (sizeof (*local_got_refcounts) + sizeof (*local_got_tls_masks));
-+      local_got_refcounts = bfd_zalloc (abfd, size);
-+      if (local_got_refcounts == NULL)
-+        return FALSE;
-+      elf_local_got_refcounts (abfd) = local_got_refcounts;
-+    }
-+
-+  local_got_tls_masks =
-+         (unsigned char *) (local_got_refcounts + symtab_hdr->sh_info);
-+  local_got_tls_masks[r_symndx] |= tls_type;
-+  local_got_refcounts[r_symndx] += 1;
-+
-+  return TRUE;
-+}
-+/* Look through the relocs for a section during the first phase.  */
-+
-+static bfd_boolean
-+microblaze_elf_check_relocs (bfd * abfd,
-+			     struct bfd_link_info * info,
-+     			     asection * sec,
-+			     const Elf_Internal_Rela * relocs)
-+{
-+  Elf_Internal_Shdr *           symtab_hdr;
-+  struct elf_link_hash_entry ** sym_hashes;
-+  struct elf_link_hash_entry ** sym_hashes_end;
-+  const Elf_Internal_Rela *     rel;
-+  const Elf_Internal_Rela *     rel_end;
-+  struct elf64_mb_link_hash_table *htab;
-+  asection *sreloc = NULL;
-+
-+  if (bfd_link_relocatable (info))
-+    return TRUE;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  symtab_hdr = & elf_tdata (abfd)->symtab_hdr;
-+  sym_hashes = elf_sym_hashes (abfd);
-+  sym_hashes_end = sym_hashes + symtab_hdr->sh_size / sizeof (Elf64_External_Sym);
-+  if (!elf_bad_symtab (abfd))
-+    sym_hashes_end -= symtab_hdr->sh_info;
-+
-+  rel_end = relocs + sec->reloc_count;
-+
-+  for (rel = relocs; rel < rel_end; rel++)
-+    {
-+      unsigned int r_type;
-+      struct elf_link_hash_entry * h;
-+      unsigned long r_symndx;
-+      unsigned char tls_type = 0;
-+
-+      r_symndx = ELF64_R_SYM (rel->r_info);
-+      r_type = ELF64_R_TYPE (rel->r_info);
-+
-+      if (r_symndx < symtab_hdr->sh_info)
-+        h = NULL;
-+      else
-+	{
-+	  h = sym_hashes [r_symndx - symtab_hdr->sh_info];
-+
-+	  /* PR15323, ref flags aren't set for references in the same
-+	     object.  */
-+	  h->root.non_ir_ref_regular = 1;
-+	}
-+
-+      switch (r_type)
-+        {
-+	  /* This relocation describes the C++ object vtable hierarchy.
-+	     Reconstruct it for later use during GC.  */
-+        case R_MICROBLAZE_GNU_VTINHERIT:
-+          if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
-+            return FALSE;
-+          break;
-+
-+	  /* This relocation describes which C++ vtable entries are actually
-+	     used.  Record for later use during GC.  */
-+        case R_MICROBLAZE_GNU_VTENTRY:
-+          if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend))
-+            return FALSE;
-+          break;
-+
-+	  /* This relocation requires .plt entry.  */
-+        case R_MICROBLAZE_PLT_64:
-+          if (h != NULL)
-+	    {
-+	      h->needs_plt = 1;
-+	      h->plt.refcount += 1;
-+	    }
-+          break;
-+
-+	  /* This relocation requires .got entry.  */
-+        case R_MICROBLAZE_TLSGD:
-+          tls_type |= (TLS_TLS | TLS_GD);
-+          goto dogottls;
-+        case R_MICROBLAZE_TLSLD:
-+          tls_type |= (TLS_TLS | TLS_LD);
-+        dogottls:
-+          sec->has_tls_reloc = 1;
-+          /* Fall through. */
-+        case R_MICROBLAZE_GOT_64:
-+          if (htab->sgot == NULL)
-+            {
-+              if (htab->elf.dynobj == NULL)
-+                htab->elf.dynobj = abfd;
-+              if (!create_got_section (htab->elf.dynobj, info))
-+                return FALSE;
-+            }
-+          if (h != NULL)
-+	    {
-+	      h->got.refcount += 1;
-+	      elf64_mb_hash_entry (h)->tls_mask |= tls_type;
-+	    }
-+          else
-+	    {
-+	      if (! update_local_sym_info(abfd, symtab_hdr, r_symndx, tls_type) )
-+		return FALSE;
-+	    }
-+          break;
-+
-+        case R_MICROBLAZE_64:
-+        case R_MICROBLAZE_64_PCREL:
-+        case R_MICROBLAZE_32:
-+          {
-+            if (h != NULL && !bfd_link_pic (info))
-+	      {
-+		/* we may need a copy reloc.  */
-+		h->non_got_ref = 1;
-+
-+		/* we may also need a .plt entry.  */
-+		h->plt.refcount += 1;
-+		if (ELF64_R_TYPE (rel->r_info) != R_MICROBLAZE_64_PCREL)
-+		  h->pointer_equality_needed = 1;
-+	      }
-+
-+
-+	    /* If we are creating a shared library, and this is a reloc
-+	       against a global symbol, or a non PC relative reloc
-+	       against a local symbol, then we need to copy the reloc
-+	       into the shared library.  However, if we are linking with
-+	       -Bsymbolic, we do not need to copy a reloc against a
-+	       global symbol which is defined in an object we are
-+	       including in the link (i.e., DEF_REGULAR is set).  At
-+	       this point we have not seen all the input files, so it is
-+	       possible that DEF_REGULAR is not set now but will be set
-+	       later (it is never cleared).  In case of a weak definition,
-+	       DEF_REGULAR may be cleared later by a strong definition in
-+	       a shared library.  We account for that possibility below by
-+	       storing information in the relocs_copied field of the hash
-+	       table entry.  A similar situation occurs when creating
-+	       shared libraries and symbol visibility changes render the
-+	       symbol local.
-+
-+	       If on the other hand, we are creating an executable, we
-+	       may need to keep relocations for symbols satisfied by a
-+	       dynamic library if we manage to avoid copy relocs for the
-+	       symbol.  */
-+
-+            if ((bfd_link_pic (info)
-+                 && (sec->flags & SEC_ALLOC) != 0
-+                 && (r_type != R_MICROBLAZE_64_PCREL
-+                     || (h != NULL
-+			 && (! info->symbolic
-+			     || h->root.type == bfd_link_hash_defweak
-+			     || !h->def_regular))))
-+                || (!bfd_link_pic (info)
-+                    && (sec->flags & SEC_ALLOC) != 0
-+                    && h != NULL
-+                    && (h->root.type == bfd_link_hash_defweak
-+                        || !h->def_regular)))
-+              {
-+                struct elf64_mb_dyn_relocs *p;
-+                struct elf64_mb_dyn_relocs **head;
-+
-+                /* When creating a shared object, we must copy these
-+                   relocs into the output file.  We create a reloc
-+                   section in dynobj and make room for the reloc.  */
-+
-+		if (sreloc == NULL)
-+		  {
-+		    bfd *dynobj;
-+
-+		    if (htab->elf.dynobj == NULL)
-+		      htab->elf.dynobj = abfd;
-+		    dynobj = htab->elf.dynobj;
-+
-+		    sreloc = _bfd_elf_make_dynamic_reloc_section (sec, dynobj,
-+								  2, abfd, 1);
-+		    if (sreloc == NULL)
-+		      return FALSE;
-+		  }
-+
-+		/* If this is a global symbol, we count the number of
-+		   relocations we need for this symbol.  */
-+		if (h != NULL)
-+		  head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs;
-+		else
-+		  {
-+		    /* Track dynamic relocs needed for local syms too.
-+		       We really need local syms available to do this
-+		       easily.  Oh well.  */
-+
-+		    asection *s;
-+		    Elf_Internal_Sym *isym;
-+		    void *vpp;
-+
-+		    isym = bfd_sym_from_r_symndx (&htab->sym_sec,
-+						  abfd, r_symndx);
-+		    if (isym == NULL)
-+		      return FALSE;
-+
-+		    s = bfd_section_from_elf_index (abfd, isym->st_shndx);
-+		    if (s == NULL)
-+		      return FALSE;
-+
-+		    vpp = &elf_section_data (s)->local_dynrel;
-+		    head = (struct elf64_mb_dyn_relocs **) vpp;
-+		  }
-+
-+		p = *head;
-+		if (p == NULL || p->sec != sec)
-+		  {
-+		    bfd_size_type amt = sizeof *p;
-+		    p = ((struct elf64_mb_dyn_relocs *)
-+			 bfd_alloc (htab->elf.dynobj, amt));
-+		    if (p == NULL)
-+		      return FALSE;
-+		    p->next = *head;
-+		    *head = p;
-+		    p->sec = sec;
-+		    p->count = 0;
-+		    p->pc_count = 0;
-+		  }
-+
-+		p->count += 1;
-+		if (r_type == R_MICROBLAZE_64_PCREL)
-+		  p->pc_count += 1;
-+	      }
-+          }
-+          break;
-+        }
-+    }
-+
-+  return TRUE;
-+}
-+
-+static bfd_boolean
-+microblaze_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (!htab->sgot && !create_got_section (dynobj, info))
-+    return FALSE;
-+
-+  if (!_bfd_elf_create_dynamic_sections (dynobj, info))
-+    return FALSE;
-+
-+  htab->splt = bfd_get_linker_section (dynobj, ".plt");
-+  htab->srelplt = bfd_get_linker_section (dynobj, ".rela.plt");
-+  htab->sdynbss = bfd_get_linker_section (dynobj, ".dynbss");
-+  if (!bfd_link_pic (info))
-+    htab->srelbss = bfd_get_linker_section (dynobj, ".rela.bss");
-+
-+  if (!htab->splt || !htab->srelplt || !htab->sdynbss
-+      || (!bfd_link_pic (info) && !htab->srelbss))
-+    abort ();
-+
-+  return TRUE;
-+}
-+
-+/* Copy the extra info we tack onto an elf_link_hash_entry.  */
-+
-+static void
-+microblaze_elf_copy_indirect_symbol (struct bfd_link_info *info,
-+				     struct elf_link_hash_entry *dir,
-+				     struct elf_link_hash_entry *ind)
-+{
-+  struct elf64_mb_link_hash_entry *edir, *eind;
-+
-+  edir = (struct elf64_mb_link_hash_entry *) dir;
-+  eind = (struct elf64_mb_link_hash_entry *) ind;
-+
-+  if (eind->dyn_relocs != NULL)
-+    {
-+      if (edir->dyn_relocs != NULL)
-+	{
-+	  struct elf64_mb_dyn_relocs **pp;
-+	  struct elf64_mb_dyn_relocs *p;
-+
-+	  if (ind->root.type == bfd_link_hash_indirect)
-+	    abort ();
-+
-+	  /* Add reloc counts against the weak sym to the strong sym
-+	     list.  Merge any entries against the same section.  */
-+	  for (pp = &eind->dyn_relocs; (p = *pp) != NULL; )
-+	    {
-+	      struct elf64_mb_dyn_relocs *q;
-+
-+	      for (q = edir->dyn_relocs; q != NULL; q = q->next)
-+		if (q->sec == p->sec)
-+		  {
-+		    q->pc_count += p->pc_count;
-+		    q->count += p->count;
-+		    *pp = p->next;
-+		    break;
-+		  }
-+	      if (q == NULL)
-+		pp = &p->next;
-+	    }
-+	  *pp = edir->dyn_relocs;
-+	}
-+
-+      edir->dyn_relocs = eind->dyn_relocs;
-+      eind->dyn_relocs = NULL;
-+    }
-+
-+  edir->tls_mask |= eind->tls_mask;
-+
-+  _bfd_elf_link_hash_copy_indirect (info, dir, ind);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
-+				      struct elf_link_hash_entry *h)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry * eh;
-+  struct elf64_mb_dyn_relocs *p;
-+  asection *sdynbss, *s;
-+  unsigned int power_of_two;
-+  bfd *dynobj;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  /* If this is a function, put it in the procedure linkage table.  We
-+     will fill in the contents of the procedure linkage table later,
-+     when we know the address of the .got section.  */
-+  if (h->type == STT_FUNC
-+      || h->needs_plt)
-+    {
-+      if (h->plt.refcount <= 0
-+	  || SYMBOL_CALLS_LOCAL (info, h)
-+	  || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
-+	      && h->root.type == bfd_link_hash_undefweak))
-+	{
-+	  /* This case can occur if we saw a PLT reloc in an input
-+	     file, but the symbol was never referred to by a dynamic
-+	     object, or if all references were garbage collected.  In
-+	     such a case, we don't actually need to build a procedure
-+	     linkage table, and we can just do a PC32 reloc instead.  */
-+	  h->plt.offset = (bfd_vma) -1;
-+	  h->needs_plt = 0;
-+	}
-+
-+      return TRUE;
-+    }
-+  else
-+    /* It's possible that we incorrectly decided a .plt reloc was
-+       needed for an R_MICROBLAZE_64_PCREL reloc to a non-function sym in
-+       check_relocs.  We can't decide accurately between function and
-+       non-function syms in check-relocs;  Objects loaded later in
-+       the link may change h->type.  So fix it now.  */
-+    h->plt.offset = (bfd_vma) -1;
-+
-+  /* If this is a weak symbol, and there is a real definition, the
-+     processor independent code will have arranged for us to see the
-+     real definition first, and we can just use the same value.  */
-+  if (h->is_weakalias)
-+    {
-+      struct elf_link_hash_entry *def = weakdef (h);
-+      BFD_ASSERT (def->root.type == bfd_link_hash_defined);
-+      h->root.u.def.section = def->root.u.def.section;
-+      h->root.u.def.value = def->root.u.def.value;
-+      return TRUE;
-+    }
-+
-+  /* This is a reference to a symbol defined by a dynamic object which
-+     is not a function.  */
-+
-+  /* If we are creating a shared library, we must presume that the
-+     only references to the symbol are via the global offset table.
-+     For such cases we need not do anything here; the relocations will
-+     be handled correctly by relocate_section.  */
-+  if (bfd_link_pic (info))
-+    return TRUE;
-+
-+  /* If there are no references to this symbol that do not use the
-+     GOT, we don't need to generate a copy reloc.  */
-+  if (!h->non_got_ref)
-+    return TRUE;
-+
-+  /* If -z nocopyreloc was given, we won't generate them either.  */
-+  if (info->nocopyreloc)
-+    {
-+      h->non_got_ref = 0;
-+      return TRUE;
-+    }
-+
-+  eh = (struct elf64_mb_link_hash_entry *) h;
-+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
-+    {
-+      s = p->sec->output_section;
-+      if (s != NULL && (s->flags & SEC_READONLY) != 0)
-+	break;
-+    }
-+
-+  /* If we didn't find any dynamic relocs in read-only sections, then
-+     we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
-+  if (p == NULL)
-+    {
-+      h->non_got_ref = 0;
-+      return TRUE;
-+    }
-+
-+  /* We must allocate the symbol in our .dynbss section, which will
-+     become part of the .bss section of the executable.  There will be
-+     an entry for this symbol in the .dynsym section.  The dynamic
-+     object will contain position independent code, so all references
-+     from the dynamic object to this symbol will go through the global
-+     offset table.  The dynamic linker will use the .dynsym entry to
-+     determine the address it must put in the global offset table, so
-+     both the dynamic object and the regular object will refer to the
-+     same memory location for the variable.  */
-+
-+  /* We must generate a R_MICROBLAZE_COPY reloc to tell the dynamic linker
-+     to copy the initial value out of the dynamic object and into the
-+     runtime process image.  */
-+  dynobj = elf_hash_table (info)->dynobj;
-+  BFD_ASSERT (dynobj != NULL);
-+  if ((h->root.u.def.section->flags & SEC_ALLOC) != 0)
-+    {
-+      htab->srelbss->size += sizeof (Elf64_External_Rela);
-+      h->needs_copy = 1;
-+    }
-+
-+  /* We need to figure out the alignment required for this symbol.  I
-+     have no idea how ELF linkers handle this.  */
-+  power_of_two = bfd_log2 (h->size);
-+  if (power_of_two > 3)
-+    power_of_two = 3;
-+
-+  sdynbss = htab->sdynbss;
-+  /* Apply the required alignment.  */
-+  sdynbss->size = BFD_ALIGN (sdynbss->size, (bfd_size_type) (1 << power_of_two));
-+  if (power_of_two > bfd_section_alignment (sdynbss))
-+    {
-+      if (! bfd_set_section_alignment (sdynbss, power_of_two))
-+	return FALSE;
-+    }
-+
-+  /* Define the symbol as being at this point in the section.  */
-+  h->root.u.def.section = sdynbss;
-+  h->root.u.def.value = sdynbss->size;
-+
-+  /* Increment the section size to make room for the symbol.  */
-+  sdynbss->size += h->size;
-+  return TRUE;
-+}
-+
-+/* Allocate space in .plt, .got and associated reloc sections for
-+   dynamic relocs.  */
-+
-+static bfd_boolean
-+allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
-+{
-+  struct bfd_link_info *info;
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry *eh;
-+  struct elf64_mb_dyn_relocs *p;
-+
-+  if (h->root.type == bfd_link_hash_indirect)
-+    return TRUE;
-+
-+  info = (struct bfd_link_info *) dat;
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (htab->elf.dynamic_sections_created
-+      && h->plt.refcount > 0)
-+    {
-+      /* Make sure this symbol is output as a dynamic symbol.
-+	 Undefined weak syms won't yet be marked as dynamic.  */
-+      if (h->dynindx == -1
-+          && !h->forced_local)
-+        {
-+          if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+            return FALSE;
-+        }
-+
-+      if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, bfd_link_pic (info), h))
-+        {
-+          asection *s = htab->splt;
-+
-+          /* The first entry in .plt is reserved.  */
-+          if (s->size == 0)
-+            s->size = PLT_ENTRY_SIZE;
-+
-+          h->plt.offset = s->size;
-+
-+          /* If this symbol is not defined in a regular file, and we are
-+             not generating a shared library, then set the symbol to this
-+             location in the .plt.  This is required to make function
-+             pointers compare as equal between the normal executable and
-+             the shared library.  */
-+          if (! bfd_link_pic (info)
-+              && !h->def_regular)
-+            {
-+              h->root.u.def.section = s;
-+              h->root.u.def.value = h->plt.offset;
-+            }
-+
-+          /* Make room for this entry.  */
-+          s->size += PLT_ENTRY_SIZE;
-+
-+          /* We also need to make an entry in the .got.plt section, which
-+             will be placed in the .got section by the linker script.  */
-+	  htab->sgotplt->size += 4;
-+
-+          /* We also need to make an entry in the .rel.plt section.  */
-+          htab->srelplt->size += sizeof (Elf64_External_Rela);
-+        }
-+      else
-+        {
-+          h->plt.offset = (bfd_vma) -1;
-+          h->needs_plt = 0;
-+        }
-+    }
-+  else
-+    {
-+      h->plt.offset = (bfd_vma) -1;
-+      h->needs_plt = 0;
-+    }
-+
-+  eh = (struct elf64_mb_link_hash_entry *) h;
-+  if (h->got.refcount > 0)
-+    {
-+      unsigned int need;
-+      asection *s;
-+
-+      /* Make sure this symbol is output as a dynamic symbol.
-+         Undefined weak syms won't yet be marked as dynamic.  */
-+      if (h->dynindx == -1
-+          && !h->forced_local)
-+        {
-+          if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+            return FALSE;
-+        }
-+
-+      need = 0;
-+      if ((eh->tls_mask & TLS_TLS) != 0)
-+        {
-+          /* Handle TLS Symbol */
-+          if ((eh->tls_mask & TLS_LD) != 0)
-+            {
-+              if (!eh->elf.def_dynamic)
-+                /* We'll just use htab->tlsld_got.offset.  This should
-+                   always be the case.  It's a little odd if we have
-+                   a local dynamic reloc against a non-local symbol.  */
-+                htab->tlsld_got.refcount += 1;
-+              else
-+                need += 8;
-+            }
-+          if ((eh->tls_mask & TLS_GD) != 0)
-+            need += 8;
-+        }
-+      else
-+        {
-+          /* Regular (non-TLS) symbol */
-+          need += 4;
-+        }
-+      if (need == 0)
-+        {
-+          h->got.offset = (bfd_vma) -1;
-+        }
-+      else
-+        {
-+          s = htab->sgot;
-+          h->got.offset = s->size;
-+          s->size += need;
-+          htab->srelgot->size += need * (sizeof (Elf64_External_Rela) / 4);
-+        }
-+    }
-+  else
-+    h->got.offset = (bfd_vma) -1;
-+
-+  if (eh->dyn_relocs == NULL)
-+    return TRUE;
-+
-+  /* In the shared -Bsymbolic case, discard space allocated for
-+     dynamic pc-relative relocs against symbols which turn out to be
-+     defined in regular objects.  For the normal shared case, discard
-+     space for pc-relative relocs that have become local due to symbol
-+     visibility changes.  */
-+
-+  if (bfd_link_pic (info))
-+    {
-+      if (h->def_regular
-+	  && (h->forced_local
-+	      || info->symbolic))
-+	{
-+	  struct elf64_mb_dyn_relocs **pp;
-+
-+	  for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
-+	    {
-+	      p->count -= p->pc_count;
-+	      p->pc_count = 0;
-+	      if (p->count == 0)
-+		*pp = p->next;
-+	      else
-+		pp = &p->next;
-+	    }
-+	}
-+    }
-+  else
-+    {
-+      /* For the non-shared case, discard space for relocs against
-+	 symbols which turn out to need copy relocs or are not
-+	 dynamic.  */
-+
-+      if (!h->non_got_ref
-+	  && ((h->def_dynamic
-+	       && !h->def_regular)
-+	      || (htab->elf.dynamic_sections_created
-+		  && (h->root.type == bfd_link_hash_undefweak
-+		      || h->root.type == bfd_link_hash_undefined))))
-+	{
-+	  /* Make sure this symbol is output as a dynamic symbol.
-+	     Undefined weak syms won't yet be marked as dynamic.  */
-+	  if (h->dynindx == -1
-+	      && !h->forced_local)
-+	    {
-+	      if (! bfd_elf_link_record_dynamic_symbol (info, h))
-+		return FALSE;
-+	    }
-+
-+	  /* If that succeeded, we know we'll be keeping all the
-+	     relocs.  */
-+	  if (h->dynindx != -1)
-+	    goto keep;
-+	}
-+
-+      eh->dyn_relocs = NULL;
-+
-+    keep: ;
-+    }
-+
-+  /* Finally, allocate space.  */
-+  for (p = eh->dyn_relocs; p != NULL; p = p->next)
-+    {
-+      asection *sreloc = elf_section_data (p->sec)->sreloc;
-+      sreloc->size += p->count * sizeof (Elf64_External_Rela);
-+    }
-+
-+  return TRUE;
-+}
-+
-+/* Set the sizes of the dynamic sections.  */
-+
-+static bfd_boolean
-+microblaze_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-+				      struct bfd_link_info *info)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  bfd *dynobj;
-+  asection *s;
-+  bfd *ibfd;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  dynobj = htab->elf.dynobj;
-+  BFD_ASSERT (dynobj != NULL);
-+
-+  /* Set up .got offsets for local syms, and space for local dynamic
-+     relocs.  */
-+  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
-+    {
-+      bfd_signed_vma *local_got;
-+      bfd_signed_vma *end_local_got;
-+      bfd_size_type locsymcount;
-+      Elf_Internal_Shdr *symtab_hdr;
-+      unsigned char *lgot_masks;
-+      asection *srel;
-+
-+      if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour)
-+        continue;
-+
-+      for (s = ibfd->sections; s != NULL; s = s->next)
-+	{
-+	  struct elf64_mb_dyn_relocs *p;
-+
-+	  for (p = ((struct elf64_mb_dyn_relocs *)
-+		    elf_section_data (s)->local_dynrel);
-+	       p != NULL;
-+	       p = p->next)
-+	    {
-+	      if (!bfd_is_abs_section (p->sec)
-+		  && bfd_is_abs_section (p->sec->output_section))
-+		{
-+		  /* Input section has been discarded, either because
-+		     it is a copy of a linkonce section or due to
-+		     linker script /DISCARD/, so we'll be discarding
-+		     the relocs too.  */
-+		}
-+	      else if (p->count != 0)
-+		{
-+		  srel = elf_section_data (p->sec)->sreloc;
-+		  srel->size += p->count * sizeof (Elf64_External_Rela);
-+		  if ((p->sec->output_section->flags & SEC_READONLY) != 0)
-+		    info->flags |= DF_TEXTREL;
-+		}
-+	    }
-+	}
-+
-+      local_got = elf_local_got_refcounts (ibfd);
-+      if (!local_got)
-+        continue;
-+
-+      symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
-+      locsymcount = symtab_hdr->sh_info;
-+      end_local_got = local_got + locsymcount;
-+      lgot_masks = (unsigned char *) end_local_got;
-+      s = htab->sgot;
-+      srel = htab->srelgot;
-+
-+      for (; local_got < end_local_got; ++local_got, ++lgot_masks)
-+	{
-+	  if (*local_got > 0)
-+	    {
-+	      unsigned int need = 0;
-+	      if ((*lgot_masks & TLS_TLS) != 0)
-+		{
-+		  if ((*lgot_masks & TLS_GD) != 0)
-+		    need += 8;
-+		  if ((*lgot_masks & TLS_LD) != 0)
-+		    htab->tlsld_got.refcount += 1;
-+		}
-+	      else
-+		need += 4;
-+
-+	      if (need == 0)
-+		{
-+		  *local_got = (bfd_vma) -1;
-+		}
-+	      else
-+		{
-+		  *local_got = s->size;
-+		  s->size += need;
-+		  if (bfd_link_pic (info))
-+		    srel->size += need * (sizeof (Elf64_External_Rela) / 4);
-+		}
-+            }
-+          else
-+            *local_got = (bfd_vma) -1;
-+        }
-+    }
-+
-+  /* Allocate global sym .plt and .got entries, and space for global
-+     sym dynamic relocs.  */
-+  elf_link_hash_traverse (elf_hash_table (info), allocate_dynrelocs, info);
-+
-+  if (htab->tlsld_got.refcount > 0)
-+    {
-+      htab->tlsld_got.offset = htab->sgot->size;
-+      htab->sgot->size += 8;
-+      if (bfd_link_pic (info))
-+        htab->srelgot->size += sizeof (Elf64_External_Rela);
-+    }
-+  else
-+    htab->tlsld_got.offset = (bfd_vma) -1;
-+
-+  if (elf_hash_table (info)->dynamic_sections_created)
-+    {
-+      /* Make space for the trailing nop in .plt.  */
-+      if (htab->splt->size > 0)
-+        htab->splt->size += 4;
-+    }
-+
-+  /* The check_relocs and adjust_dynamic_symbol entry points have
-+     determined the sizes of the various dynamic sections.  Allocate
-+     memory for them.  */
-+  for (s = dynobj->sections; s != NULL; s = s->next)
-+    {
-+      const char *name;
-+      bfd_boolean strip = FALSE;
-+
-+      if ((s->flags & SEC_LINKER_CREATED) == 0)
-+        continue;
-+
-+      /* It's OK to base decisions on the section name, because none
-+         of the dynobj section names depend upon the input files.  */
-+      name = bfd_section_name (s);
-+
-+      if (strncmp (name, ".rela", 5) == 0)
-+        {
-+          if (s->size == 0)
-+            {
-+              /* If we don't need this section, strip it from the
-+        	 output file.  This is to handle .rela.bss and
-+        	 .rela.plt.  We must create it in
-+        	 create_dynamic_sections, because it must be created
-+        	 before the linker maps input sections to output
-+        	 sections.  The linker does that before
-+        	 adjust_dynamic_symbol is called, and it is that
-+        	 function which decides whether anything needs to go
-+        	 into these sections.  */
-+              strip = TRUE;
-+            }
-+          else
-+            {
-+              /* We use the reloc_count field as a counter if we need
-+        	 to copy relocs into the output file.  */
-+              s->reloc_count = 0;
-+            }
-+        }
-+      else if (s != htab->splt && s != htab->sgot && s != htab->sgotplt)
-+        {
-+          /* It's not one of our sections, so don't allocate space.  */
-+          continue;
-+        }
-+
-+      if (strip)
-+        {
-+          s->flags |= SEC_EXCLUDE;
-+          continue;
-+        }
-+
-+      /* Allocate memory for the section contents.  */
-+      /* FIXME: This should be a call to bfd_alloc not bfd_zalloc.
-+         Unused entries should be reclaimed before the section's contents
-+         are written out, but at the moment this does not happen.  Thus in
-+         order to prevent writing out garbage, we initialise the section's
-+         contents to zero.  */
-+      s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size);
-+      if (s->contents == NULL && s->size != 0)
-+        return FALSE;
-+    }
-+
-+  if (elf_hash_table (info)->dynamic_sections_created)
-+    {
-+      /* Add some entries to the .dynamic section.  We fill in the
-+	 values later, in microblaze_elf_finish_dynamic_sections, but we
-+	 must add the entries now so that we get the correct size for
-+	 the .dynamic section.  The DT_DEBUG entry is filled in by the
-+	 dynamic linker and used by the debugger.  */
-+#define add_dynamic_entry(TAG, VAL)			\
-+      _bfd_elf_add_dynamic_entry (info, TAG, VAL)
-+
-+      if (bfd_link_executable (info))
-+        {
-+          if (!add_dynamic_entry (DT_DEBUG, 0))
-+            return FALSE;
-+        }
-+
-+      if (!add_dynamic_entry (DT_RELA, 0)
-+          || !add_dynamic_entry (DT_RELASZ, 0)
-+          || !add_dynamic_entry (DT_RELAENT, sizeof (Elf64_External_Rela)))
-+	return FALSE;
-+
-+      if (htab->splt->size != 0)
-+        {
-+          if (!add_dynamic_entry (DT_PLTGOT, 0)
-+              || !add_dynamic_entry (DT_PLTRELSZ, 0)
-+              || !add_dynamic_entry (DT_PLTREL, DT_RELA)
-+              || !add_dynamic_entry (DT_JMPREL, 0)
-+              || !add_dynamic_entry (DT_BIND_NOW, 1))
-+            return FALSE;
-+        }
-+
-+      if (info->flags & DF_TEXTREL)
-+        {
-+          if (!add_dynamic_entry (DT_TEXTREL, 0))
-+            return FALSE;
-+        }
-+    }
-+#undef add_dynamic_entry
-+  return TRUE;
-+}
-+
-+/* Finish up dynamic symbol handling.  We set the contents of various
-+   dynamic sections here.  */
-+
-+static bfd_boolean
-+microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
-+				      struct bfd_link_info *info,
-+				      struct elf_link_hash_entry *h,
-+				      Elf_Internal_Sym *sym)
-+{
-+  struct elf64_mb_link_hash_table *htab;
-+  struct elf64_mb_link_hash_entry *eh = elf64_mb_hash_entry(h);
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  if (h->plt.offset != (bfd_vma) -1)
-+    {
-+      asection *splt;
-+      asection *srela;
-+      asection *sgotplt;
-+      Elf_Internal_Rela rela;
-+      bfd_byte *loc;
-+      bfd_vma plt_index;
-+      bfd_vma got_offset;
-+      bfd_vma got_addr;
-+
-+      /* This symbol has an entry in the procedure linkage table.  Set
-+         it up.  */
-+      BFD_ASSERT (h->dynindx != -1);
-+
-+      splt = htab->splt;
-+      srela = htab->srelplt;
-+      sgotplt = htab->sgotplt;
-+      BFD_ASSERT (splt != NULL && srela != NULL && sgotplt != NULL);
-+
-+      plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; /* first entry reserved.  */
-+      got_offset = (plt_index + 3) * 4; /* 3 reserved ???  */
-+      got_addr = got_offset;
-+
-+      /* For non-PIC objects we need absolute address of the GOT entry.  */
-+      if (!bfd_link_pic (info))
-+        got_addr += htab->sgotplt->output_section->vma + sgotplt->output_offset;
-+
-+      /* Fill in the entry in the procedure linkage table.  */
-+      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
-+                  splt->contents + h->plt.offset);
-+      if (bfd_link_pic (info))
-+        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
-+                    splt->contents + h->plt.offset + 4);
-+      else
-+        bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
-+                    splt->contents + h->plt.offset + 4);
-+      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
-+                  splt->contents + h->plt.offset + 8);
-+      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
-+                  splt->contents + h->plt.offset + 12);
-+
-+      /* Any additions to the .got section??? */
-+      /*      bfd_put_32 (output_bfd,
-+	      splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
-+	      sgotplt->contents + got_offset); */
-+
-+      /* Fill in the entry in the .rela.plt section.  */
-+      rela.r_offset = (sgotplt->output_section->vma
-+                       + sgotplt->output_offset
-+                       + got_offset);
-+      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_JUMP_SLOT);
-+      rela.r_addend = 0;
-+      loc = srela->contents;
-+      loc += plt_index * sizeof (Elf64_External_Rela);
-+      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
-+
-+      if (!h->def_regular)
-+        {
-+          /* Mark the symbol as undefined, rather than as defined in
-+             the .plt section.  Zero the value.  */
-+          sym->st_shndx = SHN_UNDEF;
-+          sym->st_value = 0;
-+        }
-+    }
-+
-+  /* h->got.refcount to be checked ? */
-+  if (h->got.offset != (bfd_vma) -1 &&
-+      ! ((h->got.offset & 1) ||
-+          IS_TLS_LD(eh->tls_mask) || IS_TLS_GD(eh->tls_mask)))
-+    {
-+      asection *sgot;
-+      asection *srela;
-+      bfd_vma offset;
-+
-+      /* This symbol has an entry in the global offset table.  Set it
-+         up.  */
-+
-+      sgot = htab->sgot;
-+      srela = htab->srelgot;
-+      BFD_ASSERT (sgot != NULL && srela != NULL);
-+
-+      offset = (sgot->output_section->vma + sgot->output_offset
-+		+ (h->got.offset &~ (bfd_vma) 1));
-+
-+      /* If this is a -Bsymbolic link, and the symbol is defined
-+         locally, we just want to emit a RELATIVE reloc.  Likewise if
-+         the symbol was forced to be local because of a version file.
-+         The entry in the global offset table will already have been
-+         initialized in the relocate_section function.  */
-+      if (bfd_link_pic (info)
-+          && ((info->symbolic && h->def_regular)
-+	      || h->dynindx == -1))
-+        {
-+          asection *sec = h->root.u.def.section;
-+          microblaze_elf_output_dynamic_relocation (output_bfd,
-+                                                    srela, srela->reloc_count++,
-+                                                    /* symindex= */ 0,
-+                                                    R_MICROBLAZE_REL, offset,
-+                                                    h->root.u.def.value
-+                                                    + sec->output_section->vma
-+                                                    + sec->output_offset);
-+        }
-+      else
-+        {
-+          microblaze_elf_output_dynamic_relocation (output_bfd,
-+                                                    srela, srela->reloc_count++,
-+                                                    h->dynindx,
-+                                                    R_MICROBLAZE_GLOB_DAT,
-+                                                    offset, 0);
-+        }
-+
-+      bfd_put_32 (output_bfd, (bfd_vma) 0,
-+                  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
-+    }
-+
-+  if (h->needs_copy)
-+    {
-+      asection *s;
-+      Elf_Internal_Rela rela;
-+      bfd_byte *loc;
-+
-+      /* This symbols needs a copy reloc.  Set it up.  */
-+
-+      BFD_ASSERT (h->dynindx != -1);
-+
-+      s = bfd_get_linker_section (htab->elf.dynobj, ".rela.bss");
-+      BFD_ASSERT (s != NULL);
-+
-+      rela.r_offset = (h->root.u.def.value
-+                       + h->root.u.def.section->output_section->vma
-+                       + h->root.u.def.section->output_offset);
-+      rela.r_info = ELF64_R_INFO (h->dynindx, R_MICROBLAZE_COPY);
-+      rela.r_addend = 0;
-+      loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
-+      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
-+    }
-+
-+  /* Mark some specially defined symbols as absolute.  */
-+  if (h == htab->elf.hdynamic
-+      || h == htab->elf.hgot
-+      || h == htab->elf.hplt)
-+    sym->st_shndx = SHN_ABS;
-+
-+  return TRUE;
-+}
-+
-+
-+/* Finish up the dynamic sections.  */
-+
-+static bfd_boolean
-+microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-+					struct bfd_link_info *info)
-+{
-+  bfd *dynobj;
-+  asection *sdyn, *sgot;
-+  struct elf64_mb_link_hash_table *htab;
-+
-+  htab = elf64_mb_hash_table (info);
-+  if (htab == NULL)
-+    return FALSE;
-+
-+  dynobj = htab->elf.dynobj;
-+
-+  sdyn = bfd_get_linker_section (dynobj, ".dynamic");
-+
-+  if (htab->elf.dynamic_sections_created)
-+    {
-+      asection *splt;
-+      Elf64_External_Dyn *dyncon, *dynconend;
-+
-+      splt = bfd_get_linker_section (dynobj, ".plt");
-+      BFD_ASSERT (splt != NULL && sdyn != NULL);
-+
-+      dyncon = (Elf64_External_Dyn *) sdyn->contents;
-+      dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
-+      for (; dyncon < dynconend; dyncon++)
-+        {
-+          Elf_Internal_Dyn dyn;
-+          const char *name;
-+          bfd_boolean size;
-+
-+          bfd_elf64_swap_dyn_in (dynobj, dyncon, &dyn);
-+
-+          switch (dyn.d_tag)
-+            {
-+            case DT_PLTGOT:   name = ".got.plt"; size = FALSE; break;
-+            case DT_PLTRELSZ: name = ".rela.plt"; size = TRUE; break;
-+            case DT_JMPREL:   name = ".rela.plt"; size = FALSE; break;
-+            case DT_RELA:     name = ".rela.dyn"; size = FALSE; break;
-+            case DT_RELASZ:   name = ".rela.dyn"; size = TRUE; break;
-+            default:	  name = NULL; size = FALSE; break;
-+            }
-+
-+          if (name != NULL)
-+            {
-+              asection *s;
-+
-+              s = bfd_get_section_by_name (output_bfd, name);
-+              if (s == NULL)
-+                dyn.d_un.d_val = 0;
-+              else
-+                {
-+                  if (! size)
-+                    dyn.d_un.d_ptr = s->vma;
-+                  else
-+                    dyn.d_un.d_val = s->size;
-+                }
-+              bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
-+            }
-+        }
-+
-+      /* Clear the first entry in the procedure linkage table,
-+	 and put a nop in the last four bytes.  */
-+      if (splt->size > 0)
-+        {
-+          memset (splt->contents, 0, PLT_ENTRY_SIZE);
-+          bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
-+                      splt->contents + splt->size - 4);
-+        }
-+
-+      elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
-+    }
-+
-+  /* Set the first entry in the global offset table to the address of
-+     the dynamic section.  */
-+  sgot = bfd_get_linker_section (dynobj, ".got.plt");
-+  if (sgot && sgot->size > 0)
-+    {
-+      if (sdyn == NULL)
-+        bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
-+      else
-+        bfd_put_32 (output_bfd,
-+                    sdyn->output_section->vma + sdyn->output_offset,
-+                    sgot->contents);
-+      elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
-+    }
-+
-+  if (htab->sgot && htab->sgot->size > 0)
-+    elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize = 4;
-+
-+  return TRUE;
-+}
-+
-+/* Hook called by the linker routine which adds symbols from an object
-+   file.  We use it to put .comm items in .sbss, and not .bss.  */
-+
-+static bfd_boolean
-+microblaze_elf_add_symbol_hook (bfd *abfd,
-+			        struct bfd_link_info *info,
-+			        Elf_Internal_Sym *sym,
-+			        const char **namep ATTRIBUTE_UNUSED,
-+			        flagword *flagsp ATTRIBUTE_UNUSED,
-+			        asection **secp,
-+			        bfd_vma *valp)
-+{
-+  if (sym->st_shndx == SHN_COMMON
-+      && !bfd_link_relocatable (info)
-+      && sym->st_size <= elf_gp_size (abfd))
-+    {
-+      /* Common symbols less than or equal to -G nn bytes are automatically
-+	 put into .sbss.  */
-+      *secp = bfd_make_section_old_way (abfd, ".sbss");
-+      if (*secp == NULL
-+          || ! bfd_set_section_flags (*secp, SEC_IS_COMMON))
-+        return FALSE;
-+
-+      *valp = sym->st_size;
-+    }
-+
-+  return TRUE;
-+}
-+
-+#define TARGET_LITTLE_SYM      microblaze_elf64_le_vec
-+#define TARGET_LITTLE_NAME     "elf64-microblazeel"
-+
-+#define TARGET_BIG_SYM          microblaze_elf64_vec
-+#define TARGET_BIG_NAME		"elf64-microblaze"
-+
-+#define ELF_ARCH		bfd_arch_microblaze
-+#define ELF_TARGET_ID		MICROBLAZE_ELF_DATA
-+#define ELF_MACHINE_CODE	EM_MICROBLAZE
-+#define ELF_MACHINE_ALT1	EM_MICROBLAZE_OLD
-+#define ELF_MAXPAGESIZE		0x1000
-+#define elf_info_to_howto	microblaze_elf_info_to_howto
-+#define elf_info_to_howto_rel	NULL
-+
-+#define bfd_elf64_bfd_reloc_type_lookup		microblaze_elf_reloc_type_lookup
-+#define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
-+#define elf_backend_relocate_section		microblaze_elf_relocate_section
-+#define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
-+#define bfd_elf64_bfd_merge_private_bfd_data    _bfd_generic_verify_endian_match
-+#define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
-+
-+#define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
-+#define elf_backend_check_relocs                microblaze_elf_check_relocs
-+#define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
-+#define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
-+#define elf_backend_can_gc_sections		1
-+#define elf_backend_can_refcount    		1
-+#define elf_backend_want_got_plt    		1
-+#define elf_backend_plt_readonly    		1
-+#define elf_backend_got_header_size 		12
-+#define elf_backend_rela_normal     		1
-+
-+#define elf_backend_adjust_dynamic_symbol       microblaze_elf_adjust_dynamic_symbol
-+#define elf_backend_create_dynamic_sections     microblaze_elf_create_dynamic_sections
-+#define elf_backend_finish_dynamic_sections     microblaze_elf_finish_dynamic_sections
-+#define elf_backend_finish_dynamic_symbol       microblaze_elf_finish_dynamic_symbol
-+#define elf_backend_size_dynamic_sections       microblaze_elf_size_dynamic_sections
-+#define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
-+
-+#include "elf64-target.h"
-diff --git a/bfd/targets.c b/bfd/targets.c
-index fb0c669e7f7..97b0e473e16 100644
---- a/bfd/targets.c
-+++ b/bfd/targets.c
-@@ -779,6 +779,8 @@ extern const bfd_target mep_elf32_le_vec;
- extern const bfd_target metag_elf32_vec;
- extern const bfd_target microblaze_elf32_vec;
- extern const bfd_target microblaze_elf32_le_vec;
-+extern const bfd_target microblaze_elf64_vec;
-+extern const bfd_target microblaze_elf64_le_vec;
- extern const bfd_target mips_ecoff_be_vec;
- extern const bfd_target mips_ecoff_le_vec;
- extern const bfd_target mips_ecoff_bele_vec;
-@@ -1150,6 +1152,10 @@ static const bfd_target * const _bfd_target_vector[] =
- 
- 	&metag_elf32_vec,
- 
-+#ifdef BFD64
-+	&microblaze_elf64_vec,
-+	&microblaze_elf64_le_vec,
-+#endif
- 	&microblaze_elf32_vec,
- 
- 	&mips_ecoff_be_vec,
-diff --git a/include/elf/common.h b/include/elf/common.h
-index 75c4fb7e9d7..1584e1c87d0 100644
---- a/include/elf/common.h
-+++ b/include/elf/common.h
-@@ -339,6 +339,7 @@
- #define EM_RISCV 	243 	/* RISC-V */
- #define EM_LANAI	244	/* Lanai 32-bit processor.  */
- #define EM_BPF		247	/* Linux BPF – in-kernel virtual machine.  */
-+#define EM_MB_64	248	/* Xilinx MicroBlaze 32-bit RISC soft processor core */
- #define EM_NFP		250	/* Netronome Flow Processor.  */
- #define EM_CSKY		252	/* C-SKY processor family.  */
- 
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 356f1da22ed..437f536e96a 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -33,6 +33,7 @@
- #define get_field_r1(buf, instr)   get_field (buf, instr, RA_MASK, RA_LOW)
- #define get_field_r2(buf, instr)   get_field (buf, instr, RB_MASK, RB_LOW)
- #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
-+#define get_int_field_imml(instr)  ((instr & IMML_MASK) >> IMM_LOW)
- #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
- 
- #define NUM_STRBUFS 3
-@@ -73,11 +74,20 @@ get_field_imm (struct string_buf *buf, long instr)
- }
- 
- static char *
--get_field_imm5 (struct string_buf *buf, long instr)
-+get_field_imml (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
--  sprintf (p, "%d", (short)((instr & IMM5_MASK) >> IMM_LOW));
-+  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
-+  return p;
-+}
-+
-+static char *
-+get_field_imms (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  sprintf (p, "%d", (short)((instr & IMM6_MASK) >> IMM_LOW));
-   return p;
- }
- 
-@@ -91,14 +101,14 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
- }
- 
- static char *
--get_field_imm5width (struct string_buf *buf, long instr)
-+get_field_immw (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
-   if (instr & 0x00004000)
--    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */
-  else
--    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */
-+    sprintf (p, "%d", (short)(((instr & IMM6_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM6_MASK) >> IMM_LOW) + 1)); /* bsifi */
-   return p;
- }
- 
-@@ -306,9 +316,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 		}
- 	    }
- 	  break;
--	case INST_TYPE_RD_R1_IMM5:
-+	case INST_TYPE_RD_R1_IMML:
- 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
--		      get_field_r1 (&buf, inst), get_field_imm5 (&buf, inst));
-+		   get_field_r1(&buf, inst), get_field_imm (&buf, inst));
-+          /* TODO: Also print symbol */
-+          break;
-+	case INST_TYPE_RD_R1_IMMS:
-+	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
-+	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
- 	  break;
- 	case INST_TYPE_RD_RFSL:
- 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
-@@ -412,9 +427,12 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 		}
- 	    }
- 	  break;
--	case INST_TYPE_RD_R2:
--	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
--		      get_field_r2 (&buf, inst));
-+        case INST_TYPE_IMML:
-+	  print_func (stream, "\t%s", get_field_imml (&buf, inst));
-+          /* TODO: Also print symbol */
-+	  break;
-+        case INST_TYPE_RD_R2:
-+	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_r2 (&buf, inst));
- 	  break;
- 	case INST_TYPE_R2:
- 	  print_func (stream, "\t%s", get_field_r2 (&buf, inst));
-@@ -439,8 +457,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  break;
- 	  /* For tuqula instruction */
-         /* For bit field insns.  */
--	case INST_TYPE_RD_R1_IMM5_IMM5:
--	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst), get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst));
-+	case INST_TYPE_RD_R1_IMMW_IMMS:
-+	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
-+		   get_field_immw (&buf, inst), get_field_imms (&buf, inst));
- 	  break;
- 	/* For tuqula instruction */
- 	case INST_TYPE_RD:
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index d3b234e1fcd..28dc991c430 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -40,7 +40,7 @@
- #define INST_TYPE_RD_SPECIAL 11
- #define INST_TYPE_R1 12
- /* New instn type for barrel shift imms.  */
--#define INST_TYPE_RD_R1_IMM5  13
-+#define INST_TYPE_RD_R1_IMMS  13
- #define INST_TYPE_RD_RFSL    14
- #define INST_TYPE_R1_RFSL    15
- 
-@@ -60,7 +60,13 @@
- #define INST_TYPE_IMM5 20
- 
- /* For bsefi and bsifi */
--#define INST_TYPE_RD_R1_IMM5_IMM5  21
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
-+
-+/* For 64-bit instructions */
-+#define INST_TYPE_IMML 22
-+#define INST_TYPE_RD_R1_IMML 23
-+#define INST_TYPE_R1_IMML 24
-+#define INST_TYPE_RD_R1_IMMW_IMMS  21
- 
- #define INST_TYPE_NONE 25
- 
-@@ -91,13 +97,14 @@
- #define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
- #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
- #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
--#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
--#define OPCODE_MASK_H3B 0xFC00C600  /* High 6 bits and bits 16, 17, 21, 22.  */
-+#define OPCODE_MASK_H3  0xFC000700  /* High 6 bits and bits 21, 22, 23.  */
-+#define OPCODE_MASK_H3B 0xFC00E600  /* High 6 bits and bits 16, 17, 18, 21, 22.  */
- #define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
--#define OPCODE_MASK_H32B 0xFC00C000  /* High 6 bits and bit 16, 17.  */
-+#define OPCODE_MASK_H32B 0xFC00E000  /* High 6 bits and bit 16, 17, 18.  */
- #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
- #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits.  */
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
-+#define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
- 
- /* New Mask for msrset, msrclr insns.  */
- #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
-@@ -107,7 +114,7 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 301
-+#define MAX_OPCODES 412
- 
- struct op_code_struct
- {
-@@ -125,6 +132,7 @@ struct op_code_struct
-   /* More info about output format here.  */
- } opcodes[MAX_OPCODES] =
- {
-+  /* 32-bit instructions */
-   {"add",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000000, OPCODE_MASK_H4, add, arithmetic_inst },
-   {"rsub",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H4, rsub, arithmetic_inst },
-   {"addc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000000, OPCODE_MASK_H4, addc, arithmetic_inst },
-@@ -161,11 +169,11 @@ struct op_code_struct
-   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
-   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
-   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
--  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
--  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
--  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
--  {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
--  {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-+  {"bslli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
-+  {"bsrai", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
-+  {"bsrli", INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
-+  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
-+  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
-   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
-   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
-   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
-@@ -425,6 +433,129 @@ struct op_code_struct
-   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
-   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
-   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
-+
-+  /* 64-bit instructions */
-+  {"addl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x00000100, OPCODE_MASK_H4, addl, arithmetic_inst },
-+  {"rsubl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000100, OPCODE_MASK_H4, rsubl, arithmetic_inst },
-+  {"addlc",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x08000100, OPCODE_MASK_H4, addlc, arithmetic_inst },
-+  {"rsublc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x0C000100, OPCODE_MASK_H4, rsublc, arithmetic_inst },
-+  {"addlk",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x10000100, OPCODE_MASK_H4, addlk, arithmetic_inst },
-+  {"rsublk",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000100, OPCODE_MASK_H4, rsublk, arithmetic_inst },
-+  {"addlkc",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x18000100, OPCODE_MASK_H4, addlkc, arithmetic_inst },
-+  {"rsublkc", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x1C000100, OPCODE_MASK_H4, rsublkc, arithmetic_inst },
-+  {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
-+  {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
-+  {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
-+  {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
-+  {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
-+  {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
-+  {"bslrl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000100, OPCODE_MASK_H3, bslrl, barrel_shift_inst },
-+  {"bsllli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002400, OPCODE_MASK_H3B, bsllli, barrel_shift_inst },
-+  {"bslrai",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002200, OPCODE_MASK_H3B, bslrai, barrel_shift_inst },
-+  {"bslrli",  INST_TYPE_RD_R1_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64002000, OPCODE_MASK_H3B, bslrli, barrel_shift_inst },
-+  {"bslefi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64006000, OPCODE_MASK_H32B, bslefi, barrel_shift_inst },
-+  {"bslifi",  INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6400a000, OPCODE_MASK_H32B, bslifi, barrel_shift_inst },
-+  {"orl",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000100, OPCODE_MASK_H4, orl, logical_inst },
-+  {"andl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000100, OPCODE_MASK_H4, andl, logical_inst },
-+  {"xorl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000100, OPCODE_MASK_H4, xorl, logical_inst },
-+  {"andnl",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000100, OPCODE_MASK_H4, andnl, logical_inst },
-+  {"pcmplbf", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000500, OPCODE_MASK_H4, pcmplbf, logical_inst },
-+  {"pcmpleq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000500, OPCODE_MASK_H4, pcmpleq, logical_inst },
-+  {"pcmplne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x8C000500, OPCODE_MASK_H4, pcmplne, logical_inst },
-+  {"srla",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000101, OPCODE_MASK_H34, srla, logical_inst },
-+  {"srlc",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000121, OPCODE_MASK_H34, srlc, logical_inst },
-+  {"srll",    INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000141, OPCODE_MASK_H34, srll, logical_inst },
-+  {"sextl8",  INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000160, OPCODE_MASK_H34, sextl8, logical_inst },
-+  {"sextl16", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000161, OPCODE_MASK_H34, sextl16, logical_inst },
-+  {"sextl32", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000162, OPCODE_MASK_H34, sextl32, logical_inst },
-+  {"brea",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98010000, OPCODE_MASK_H124, brea, branch_inst },
-+  {"bread",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98110000, OPCODE_MASK_H124, bread, branch_inst },
-+  {"breald",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98150000, OPCODE_MASK_H24, breald, branch_inst },
-+  {"beaeq",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000000, OPCODE_MASK_H14, beaeq, branch_inst },
-+  {"bealeq",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D000100, OPCODE_MASK_H14, bealeq, branch_inst },
-+  {"beaeqd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000000, OPCODE_MASK_H14, beaeqd, branch_inst },
-+  {"bealeqd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F000100, OPCODE_MASK_H14, bealeqd, branch_inst },
-+  {"beane",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200000, OPCODE_MASK_H14, beane, branch_inst },
-+  {"bealne",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D200100, OPCODE_MASK_H14, bealne, branch_inst },
-+  {"beaned",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200000, OPCODE_MASK_H14, beaned, branch_inst },
-+  {"bealned", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F200100, OPCODE_MASK_H14, bealned, branch_inst },
-+  {"bealt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400000, OPCODE_MASK_H14, bealt, branch_inst },
-+  {"beallt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D400100, OPCODE_MASK_H14, beallt, branch_inst },
-+  {"bealtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400000, OPCODE_MASK_H14, bealtd, branch_inst },
-+  {"bealltd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F400100, OPCODE_MASK_H14, bealltd, branch_inst },
-+  {"beale",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600000, OPCODE_MASK_H14, beale, branch_inst },
-+  {"bealle",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D600100, OPCODE_MASK_H14, bealle, branch_inst },
-+  {"bealed",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600000, OPCODE_MASK_H14, bealed, branch_inst },
-+  {"bealled", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F600100, OPCODE_MASK_H14, bealled, branch_inst },
-+  {"beagt",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800000, OPCODE_MASK_H14, beagt, branch_inst },
-+  {"bealgt",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9D800100, OPCODE_MASK_H14, bealgt, branch_inst },
-+  {"beagtd",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800000, OPCODE_MASK_H14, beagtd, branch_inst },
-+  {"bealgtd", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9F800100, OPCODE_MASK_H14, bealgtd, branch_inst },
-+  {"beage",   INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00000, OPCODE_MASK_H14, beage, branch_inst },
-+  {"bealge",  INST_TYPE_R1_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9DA00100, OPCODE_MASK_H14, bealge, branch_inst },
-+  {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
-+  {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
-+  {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
-+  {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
-+  {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
-+  {"brealid", INST_TYPE_RD_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8150000, OPCODE_MASK_H2, brealid, branch_inst },
-+  {"beaeqi",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, beaeqi, branch_inst },
-+  {"bealeqi", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD000000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beaeqi */
-+  {"beaeqid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, beaeqid, branch_inst },
-+  {"bealeqid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF000000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaeqid */
-+  {"beanei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, beanei, branch_inst },
-+  {"bealnei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD200000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beanei */
-+  {"beaneid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, beaneid, branch_inst },
-+  {"bealneid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF200000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beaneid */
-+  {"bealti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, bealti, branch_inst },
-+  {"beallti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD400000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealti */
-+  {"bealtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, bealtid, branch_inst },
-+  {"bealltid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF400000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealtid */
-+  {"bealei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, bealei, branch_inst },
-+  {"beallei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD600000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to bealei */
-+  {"bealeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, bealeid, branch_inst },
-+  {"bealleid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF600000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to bealeid */
-+  {"beagti",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, beagti, branch_inst },
-+  {"bealgti", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBD800000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagti */
-+  {"beagtid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, beagtid, branch_inst },
-+  {"bealgtid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBF800000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beagtid */
-+  {"beagei",  INST_TYPE_R1_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, beagei, branch_inst },
-+  {"bealgei", INST_TYPE_R1_IMML, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBDA00000, OPCODE_MASK_H1, invalid_inst, branch_inst }, /* Identical to beagei */
-+  {"beageid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, beageid, branch_inst },
-+  {"bealgeid",INST_TYPE_R1_IMML, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBFA00000, OPCODE_MASK_H1, invalid_inst, branch_inst },    /* Identical to beageid */
-+  {"ll",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000100, OPCODE_MASK_H4, ll, memory_load_inst },
-+  {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
-+  {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
-+  {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
-+  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
-+  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-+  {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
-+  {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
-+  {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
-+  {"dmul",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000500, OPCODE_MASK_H4, dmul, arithmetic_inst },
-+  {"ddiv",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000580, OPCODE_MASK_H4, ddiv, arithmetic_inst },
-+  {"dcmp.lt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000610, OPCODE_MASK_H4, dcmp_lt, arithmetic_inst },
-+  {"dcmp.eq", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000620, OPCODE_MASK_H4, dcmp_eq, arithmetic_inst },
-+  {"dcmp.le", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000630, OPCODE_MASK_H4, dcmp_le, arithmetic_inst },
-+  {"dcmp.gt", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000640, OPCODE_MASK_H4, dcmp_gt, arithmetic_inst },
-+  {"dcmp.ne", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000650, OPCODE_MASK_H4, dcmp_ne, arithmetic_inst },
-+  {"dcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000660, OPCODE_MASK_H4, dcmp_ge, arithmetic_inst },
-+  {"dcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000600, OPCODE_MASK_H4, dcmp_un, arithmetic_inst },
-+  {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
-+  {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
-+  {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
-+
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
- };
- 
-@@ -445,8 +576,17 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM5  ((int) 0x00000000)
- #define MAX_IMM5  ((int) 0x0000001f)
- 
-+#define MIN_IMM6  ((int) 0x00000000)
-+#define MAX_IMM6  ((int) 0x0000003f)
-+
- #define MIN_IMM_WIDTH  ((int) 0x00000001)
- #define MAX_IMM_WIDTH  ((int) 0x00000020)
- 
-+#define MIN_IMM6_WIDTH  ((int) 0x00000001)
-+#define MAX_IMM6_WIDTH  ((int) 0x00000040)
-+
-+#define MIN_IMML  ((long) 0xffffff8000000000L)
-+#define MAX_IMML  ((long) 0x0000007fffffffffL)
-+
- #endif /* MICROBLAZE_OPC */
- 
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index c3b2b8f0f6e..ad475a4af15 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -25,6 +25,7 @@
- 
- enum microblaze_instr
- {
-+  /* 32-bit instructions */
-   add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
-   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
-   mulh, mulhu, mulhsu,swapb,swaph,
-@@ -58,6 +59,18 @@ enum microblaze_instr
-   aputd, taputd, caputd, tcaputd, naputd, tnaputd, ncaputd, tncaputd,
-   eagetd, teagetd, ecagetd, tecagetd, neagetd, tneagetd, necagetd, tnecagetd,
-   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
-+
-+  /* 64-bit instructions */
-+  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
-+  andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
-+  brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
-+  bealned, bealt, beallt, bealtd, bealltd, beale, bealle, bealed, bealled, beagt,
-+  bealgt, beagtd, bealgtd, beage, bealge, beaged, bealged, breai, breaid, brealid,
-+  beaeqi, beaeqid, beanei, beaneid, bealti, bealtid, bealei, bealeid, beagti,
-+  beagtid, beagei, beageid, imml, ll, llr, sl, slr,
-+  dadd, drsub, dmul, ddiv, dcmp_lt, dcmp_eq, dcmp_le, dcmp_gt, dcmp_ne, dcmp_ge,
-+  dcmp_un, dbl, dlong, dsqrt,
-   invalid_inst
- };
- 
-@@ -135,15 +148,18 @@ enum microblaze_instr_type
- #define RA_MASK 0x001F0000
- #define RB_MASK 0x0000F800
- #define IMM_MASK 0x0000FFFF
-+#define IMML_MASK 0x00FFFFFF
- 
--/* Imm mask for barrel shifts.  */
-+/* Imm masks for barrel shifts.  */
- #define IMM5_MASK 0x0000001F
-+#define IMM6_MASK 0x0000003F
- 
- /* Imm mask for mbar.  */
- #define IMM5_MBAR_MASK 0x03E00000
- 
--/* Imm mask for extract/insert width. */
-+/* Imm masks for extract/insert width. */
- #define IMM5_WIDTH_MASK 0x000007C0
-+#define IMM6_WIDTH_MASK 0x00000FC0
- 
- /* FSL imm mask for get, put instructions.  */
- #define  RFSL_MASK 0x000000F
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch
deleted file mode 100644
index 8bf07398be..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-MB-X-initial-commit.patch
+++ /dev/null
@@ -1,337 +0,0 @@
-From f82b24b2685d0cde8f8fdd0a1dcffe7b76b2027c Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Sun, 30 Sep 2018 16:31:26 +0530
-Subject: [PATCH 16/40] MB-X initial commit code cleanup is needed.
-
----
- bfd/bfd-in2.h              |  10 +++
- bfd/elf32-microblaze.c     |  63 +++++++++++++++++-
- bfd/elf64-microblaze.c     |  59 +++++++++++++++++
- bfd/libbfd.h               |   2 +
- bfd/reloc.c                |  12 ++++
- include/elf/microblaze.h   |   2 +
- opcodes/microblaze-opc.h   |   4 +-
- opcodes/microblaze-opcm.h  |   4 +-
- 9 files changed, 243 insertions(+), 40 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 52c81b10b6d..c6738960bb2 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5373,11 +5373,21 @@ value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64_NONE,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imml instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_64,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- PC-relative GOT offset  */
-   BFD_RELOC_MICROBLAZE_64_GOTPC,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imml instruction).  The relocation is
-+PC-relative GOT offset  */
-+  BFD_RELOC_MICROBLAZE_64_GPC,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- GOT offset  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cb7271f5017..a31b407cfbf 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -116,6 +116,20 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  TRUE),		/* PC relative offset?  */
- 
-+   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_IMML_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
-+
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,	/* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -280,6 +294,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
- 	  0x0000ffff,		/* Dest Mask.  */
- 	  TRUE),		/* PC relative offset?  */
- 
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit GOT relocation.  Table-entry not really used.  */
-    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
- 	  0,			/* Rightshift.  */
-@@ -619,9 +648,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64:
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+      microblaze_reloc = R_MICROBLAZE_GPC_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-       microblaze_reloc = R_MICROBLAZE_GOT_64;
-       break;
-@@ -1933,6 +1968,28 @@ microblaze_elf_relax_section (bfd *abfd,
- 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
- 		}
- 	      break;
-+	    case R_MICROBLAZE_IMML_64:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
- 	    case R_MICROBLAZE_NONE:
- 	    case R_MICROBLAZE_32_NONE:
- 	      {
-@@ -2038,9 +2095,9 @@ microblaze_elf_relax_section (bfd *abfd,
-                   microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
-                                                      irelscan->r_addend);
-               }
--	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
--		{
--		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
-+             if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
-+               {
-+	          isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
- 
- 		  /* Look at the reloc only if the value has been resolved.  */
- 		  if (isym->st_shndx == shndx
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index fa4b95e47e0..d55700fc513 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -116,6 +116,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0x0000ffff,		/* Dest Mask.  */
-           TRUE), 		/* PC relative offset?  */
- 
-+   /* A 64 bit relocation.  Table entry not really used.  */
-+   HOWTO (R_MICROBLAZE_IMML_64,     	/* Type.  */
-+          0,			/* Rightshift.  */
-+          4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          64,			/* Bitsize.  */
-+          TRUE,		/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,/* Special Function.  */
-+          "R_MICROBLAZE_IMML_64",   	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-           0,			/* Rightshift.  */
-@@ -265,6 +280,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0x0000ffff,		/* Dest Mask.  */
-           TRUE), 		/* PC relative offset?  */
- 
-+   /* A 64 bit GOTPC relocation.  Table-entry not really used.  */
-+   HOWTO (R_MICROBLAZE_GPC_64,   	/* Type.  */
-+          0,			/* Rightshift.  */
-+          2,			/* Size (0 = byte, 1 = short, 2 = long).  */
-+          16,			/* Bitsize.  */
-+          TRUE,			/* PC_relative.  */
-+          0,			/* Bitpos.  */
-+          complain_overflow_dont, /* Complain on overflow.  */
-+          bfd_elf_generic_reloc,	/* Special Function.  */
-+          "R_MICROBLAZE_GPC_64", 	/* Name.  */
-+          FALSE,		/* Partial Inplace.  */
-+          0,			/* Source Mask.  */
-+          0x0000ffff,		/* Dest Mask.  */
-+          TRUE), 		/* PC relative offset?  */
-+
-    /* A 64 bit GOT relocation.  Table-entry not really used.  */
-    HOWTO (R_MICROBLAZE_GOT_64,  /* Type.  */
-           0,			/* Rightshift.  */
-@@ -589,9 +619,15 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64:
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-       microblaze_reloc = R_MICROBLAZE_GOTPC_64;
-       break;
-+    case BFD_RELOC_MICROBLAZE_64_GPC:
-+      microblaze_reloc = R_MICROBLAZE_GPC_64;
-+      break;
-     case BFD_RELOC_MICROBLAZE_64_GOT:
-       microblaze_reloc = R_MICROBLAZE_GOT_64;
-       break;
-@@ -1162,6 +1198,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 	      break; /* Do nothing.  */
- 
- 	    case (int) R_MICROBLAZE_GOTPC_64:
-+	    case (int) R_MICROBLAZE_GPC_64:
- 	      relocation = htab->sgotplt->output_section->vma
- 		+ htab->sgotplt->output_offset;
- 	      relocation -= (input_section->output_section->vma
-@@ -1863,6 +1900,28 @@ microblaze_elf_relax_section (bfd *abfd,
- 		    irel->r_addend -= calc_fixup (irel->r_addend, 0, sec);
- 	        }
- 	      break;
-+	    case R_MICROBLAZE_IMML_64:
-+	      {
-+	        /* This was a PC-relative instruction that was
-+		   completely resolved.  */
-+	        int sfix, efix;
-+            unsigned int val;
-+	        bfd_vma target_address;
-+	        target_address = irel->r_addend + irel->r_offset;
-+	        sfix = calc_fixup (irel->r_offset, 0, sec);
-+	        efix = calc_fixup (target_address, 0, sec);
-+
-+            /* Validate the in-band val.  */
-+            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-+               fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-+            }
-+	        irel->r_addend -= (efix - sfix);
-+	        /* Should use HOWTO.  */
-+	        microblaze_bfd_write_imm_value_64 (abfd, contents + irel->r_offset,
-+	                                           irel->r_addend);
-+	      }
-+	      break;
- 	    case R_MICROBLAZE_NONE:
- 	    case R_MICROBLAZE_32_NONE:
- 	      {
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index a01891f3423..4e71991273e 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2905,7 +2905,9 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-   "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
-+  "BFD_RELOC_MICROBLAZE_64",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
-+  "BFD_RELOC_MICROBLAZE_64_GPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-   "BFD_RELOC_MICROBLAZE_64_PLT",
-   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 78f13180c71..8b3cc604738 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6814,12 +6814,24 @@ ENUMDOC
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
-+ENUMDOC
-+  This is a 32 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imml instruction).  No relocation is
-+  done here - only used for relaxing
-+ENUM
-+  BFD_RELOC_MICROBLAZE_64
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  No relocation is
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_GOTPC
-+ENUMDOC
-+  This is a 64 bit reloc that stores the 32 bit pc relative
-+  value in two words (with an imml instruction).  No relocation is
-+  done here - only used for relaxing
-+ENUM
-+  BFD_RELOC_MICROBLAZE_64_GPC
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  The relocation is
-diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
-index 0dba2c0f44f..030eb99a1a0 100644
---- a/include/elf/microblaze.h
-+++ b/include/elf/microblaze.h
-@@ -62,6 +62,8 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
-   RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
-+  RELOC_NUMBER (R_MICROBLAZE_IMML_64, 34)
-+  RELOC_NUMBER (R_MICROBLAZE_GPC_64, 35)    /* GOT entry offset.  */
- END_RELOC_NUMBERS (R_MICROBLAZE_max)
- 
- /* Global base address names.  */
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 28dc991c430..46263bc7e16 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -538,8 +538,8 @@ struct op_code_struct
-   {"llr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000300, OPCODE_MASK_H4, llr, memory_load_inst },
-   {"sl",      INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000100, OPCODE_MASK_H4, sl, memory_store_inst },
-   {"slr",     INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000300, OPCODE_MASK_H4, slr, memory_store_inst },
--  {"lli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
--  {"sli",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-+  {"lli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xEC000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },  /* Identical to 32-bit */
-+  {"sli",     INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xFC000000, OPCODE_MASK_H, invalid_inst, memory_store_inst }, /* Identical to 32-bit */
-   {"lla",     INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* lla translates to addlik */
-   {"dadd",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000400, OPCODE_MASK_H4, dadd, arithmetic_inst },
-   {"drsub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000480, OPCODE_MASK_H4, drsub, arithmetic_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index ad475a4af15..ee01cdb7d9b 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -40,8 +40,8 @@ enum microblaze_instr
-   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
-   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
-   bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
--  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
--  sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-+  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi, lli,
-+  sbi, shi, sli, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
-   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
-   fint, fsqrt,
-   tget, tcget, tnget, tncget, tput, tcput, tnput, tncput,
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
new file mode 100644
index 0000000000..a717595b51
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0016-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
@@ -0,0 +1,33 @@
+From 8ad2e417691ac2b89ffec9db9026d53600d9a137 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 11 Sep 2018 13:48:33 +0530
+Subject: [PATCH 16/52] [Patch,Microblaze] : negl instruction is overriding
+ rsubl,fixed it by changing the instruction order...
+
+---
+ opcodes/microblaze-opc.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -275,9 +275,7 @@ struct op_code_struct
+   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
+   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
+   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
+-  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
+   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
+-  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
+   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
+   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
+@@ -555,6 +553,8 @@ struct op_code_struct
+   {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
+   {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
+   {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
++  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
++  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
+ 
+   {"", 0, 0, 0, 0, 0, 0, 0, 0},
+ };
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Added-relocations-for-MB-X.patch
new file mode 100644
index 0000000000..ac9da7a9cc
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Added-relocations-for-MB-X.patch
@@ -0,0 +1,113 @@
+From eccbce1a31ed29dc38fb9ab15b6badcf9412bdb8 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 11 Sep 2018 17:30:17 +0530
+Subject: [PATCH 17/52] Added relocations for MB-X
+
+Conflicts:
+	bfd/bfd-in2.h
+	gas/config/tc-microblaze.c
+---
+ bfd/bfd-in2.h              |  9 +++-
+ bfd/libbfd.h               |  4 +-
+ bfd/reloc.c                | 26 ++++++-----
+ gas/config/tc-microblaze.c | 90 ++++++++++++++++----------------------
+ 4 files changed, 61 insertions(+), 68 deletions(-)
+
+Index: gdb-9.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-9.2.orig/bfd/bfd-in2.h
++++ gdb-9.2/bfd/bfd-in2.h
+@@ -5371,14 +5371,19 @@ done here - only used for relaxing  */
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+-  BFD_RELOC_MICROBLAZE_64_NONE,
++  BFD_RELOC_MICROBLAZE_64_PCREL,
+ 
+-/* This is a 64 bit reloc that stores the 32 bit pc relative
++/* This is a 64 bit reloc that stores the 32 bit relative
+  *  +value in two words (with an imml instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64,
+ 
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
++ *  +value in two words (with an imm instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_64_NONE,
++
++/* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  The relocation is
+ PC-relative GOT offset  */
+   BFD_RELOC_MICROBLAZE_64_GOTPC,
+Index: gdb-9.2/bfd/libbfd.h
+===================================================================
+--- gdb-9.2.orig/bfd/libbfd.h
++++ gdb-9.2/bfd/libbfd.h
+@@ -2905,14 +2905,14 @@ static const char *const bfd_reloc_code_
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
+   "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+-  "BFD_RELOC_MICROBLAZE_64",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+-  "BFD_RELOC_MICROBLAZE_64_GPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+   "BFD_RELOC_MICROBLAZE_64_PLT",
+   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
+   "BFD_RELOC_MICROBLAZE_COPY",
++  "BFD_RELOC_MICROBLAZE_64",
++  "BFD_RELOC_MICROBLAZE_64_PCREL",
+   "BFD_RELOC_MICROBLAZE_64_TLS",
+   "BFD_RELOC_MICROBLAZE_64_TLSGD",
+   "BFD_RELOC_MICROBLAZE_64_TLSLD",
+Index: gdb-9.2/bfd/reloc.c
+===================================================================
+--- gdb-9.2.orig/bfd/reloc.c
++++ gdb-9.2/bfd/reloc.c
+@@ -6815,12 +6815,6 @@ ENUMDOC
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+-  This is a 32 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64
+-ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  No relocation is
+   done here - only used for relaxing
+@@ -6828,12 +6822,6 @@ ENUM
+   BFD_RELOC_MICROBLAZE_64_GOTPC
+ ENUMDOC
+   This is a 64 bit reloc that stores the 32 bit pc relative
+-  value in two words (with an imml instruction).  No relocation is
+-  done here - only used for relaxing
+-ENUM
+-  BFD_RELOC_MICROBLAZE_64_GPC
+-ENUMDOC
+-  This is a 64 bit reloc that stores the 32 bit pc relative
+   value in two words (with an imm instruction).  The relocation is
+   PC-relative GOT offset
+ ENUM
+@@ -6917,6 +6905,20 @@ ENUMDOC
+   value in two words (with an imm instruction).  The relocation is
+   relative offset from start of TEXT.
+ 
++  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
++  to two words (uses imml instruction).
++ENUM
++BFD_RELOC_MICROBLAZE_64,
++ENUMDOC
++ This is a 64 bit reloc that stores the 64 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
++ENUM
++BFD_RELOC_MICROBLAZE_64_PCREL,
++ENUMDOC
++ This is a 32 bit reloc that stores the 32 bit pc relative
++ value in two words (with an imml instruction).  No relocation is
++ done here - only used for relaxing
+ ENUM
+   BFD_RELOC_AARCH64_RELOC_START
+ ENUMDOC
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
deleted file mode 100644
index eaf24505af..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0017-Patch-Microblaze-negl-instruction-is-overriding-rsub.patch
+++ /dev/null
@@ -1,37 +0,0 @@
-From b6ec3e2295ba33d2c8f48500d75a147ffd84a656 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 11 Sep 2018 13:48:33 +0530
-Subject: [PATCH 17/40] [Patch,Microblaze] : negl instruction is overriding
- rsubl
-
-fixed it by changing the instruction order...
----
- opcodes/microblaze-opc.h | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index 46263bc7e16..f4ee8f43372 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -275,9 +275,7 @@ struct op_code_struct
-   {"la",    INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* la translates to addik.  */
-   {"tuqula",INST_TYPE_RD, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3000002A, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* tuqula rd translates to addik rd, r0, 42.  */
-   {"not",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA800FFFF, OPCODE_MASK_H34, invalid_inst, logical_inst }, /* not translates to xori rd,ra,-1.  */
--  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-   {"rtb",   INST_TYPE_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB6000004, OPCODE_MASK_H1, invalid_inst, return_inst }, /* rtb translates to rts rd, 4.  */
--  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
-   {"lmi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, invalid_inst, memory_load_inst },
-   {"smi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xF8000000, OPCODE_MASK_H, invalid_inst, memory_store_inst },
-   {"msrset",INST_TYPE_RD_IMM15, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x94100000, OPCODE_MASK_H23N, msrset, special_inst },
-@@ -555,6 +553,8 @@ struct op_code_struct
-   {"dbl",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000680, OPCODE_MASK_H4, dbl,   arithmetic_inst },
-   {"dlong",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000700, OPCODE_MASK_H4, dlong, arithmetic_inst },
-   {"dsqrt",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000780, OPCODE_MASK_H4, dsqrt, arithmetic_inst },
-+  {"neg",   INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* neg translates to rsub rd, ra, r0.  */
-+  {"sub",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x04000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst }, /* sub translates to rsub rd, rb, ra.  */
- 
-   {"", 0, 0, 0, 0, 0, 0, 0, 0},
- };
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch
deleted file mode 100644
index 742f9e345d..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Added-relocations-for-MB-X.patch
+++ /dev/null
@@ -1,113 +0,0 @@
-From 982f37caabea84cee52426844e73365f0cb93f3d Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 11 Sep 2018 17:30:17 +0530
-Subject: [PATCH 18/40] Added relocations for MB-X
-
----
- bfd/bfd-in2.h              | 11 +++++---
- bfd/libbfd.h               |  4 +--
- bfd/reloc.c                | 26 +++++++++---------
- 4 files changed, 63 insertions(+), 32 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index c6738960bb2..3899352b1d5 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5369,15 +5369,20 @@ done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_32_NONE,
- 
- /* This is a 64 bit reloc that stores the 32 bit pc relative
--value in two words (with an imm instruction).  No relocation is
-+value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
--  BFD_RELOC_MICROBLAZE_64_NONE,
-+  BFD_RELOC_MICROBLAZE_64_PCREL,
- 
--/* This is a 64 bit reloc that stores the 32 bit pc relative
-+/* This is a 64 bit reloc that stores the 32 bit relative
- value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64,
- 
-+/* This is a 64 bit reloc that stores the 32 bit pc relative
-+value in two words (with an imm instruction).  No relocation is
-+done here - only used for relaxing  */
-+  BFD_RELOC_MICROBLAZE_64_NONE,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  The relocation is
- PC-relative GOT offset  */
-diff --git a/bfd/libbfd.h b/bfd/libbfd.h
-index 4e71991273e..46be3891390 100644
---- a/bfd/libbfd.h
-+++ b/bfd/libbfd.h
-@@ -2905,14 +2905,14 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
-   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
-   "BFD_RELOC_MICROBLAZE_32_NONE",
-   "BFD_RELOC_MICROBLAZE_64_NONE",
--  "BFD_RELOC_MICROBLAZE_64",
-   "BFD_RELOC_MICROBLAZE_64_GOTPC",
--  "BFD_RELOC_MICROBLAZE_64_GPC",
-   "BFD_RELOC_MICROBLAZE_64_GOT",
-   "BFD_RELOC_MICROBLAZE_64_PLT",
-   "BFD_RELOC_MICROBLAZE_64_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_32_GOTOFF",
-   "BFD_RELOC_MICROBLAZE_COPY",
-+  "BFD_RELOC_MICROBLAZE_64",
-+  "BFD_RELOC_MICROBLAZE_64_PCREL",
-   "BFD_RELOC_MICROBLAZE_64_TLS",
-   "BFD_RELOC_MICROBLAZE_64_TLSGD",
-   "BFD_RELOC_MICROBLAZE_64_TLSLD",
-diff --git a/bfd/reloc.c b/bfd/reloc.c
-index 8b3cc604738..98a156f061f 100644
---- a/bfd/reloc.c
-+++ b/bfd/reloc.c
-@@ -6814,24 +6814,12 @@ ENUMDOC
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_NONE
--ENUMDOC
--  This is a 32 bit reloc that stores the 32 bit pc relative
--  value in two words (with an imml instruction).  No relocation is
--  done here - only used for relaxing
--ENUM
--  BFD_RELOC_MICROBLAZE_64
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  No relocation is
-   done here - only used for relaxing
- ENUM
-   BFD_RELOC_MICROBLAZE_64_GOTPC
--ENUMDOC
--  This is a 64 bit reloc that stores the 32 bit pc relative
--  value in two words (with an imml instruction).  No relocation is
--  done here - only used for relaxing
--ENUM
--  BFD_RELOC_MICROBLAZE_64_GPC
- ENUMDOC
-   This is a 64 bit reloc that stores the 32 bit pc relative
-   value in two words (with an imm instruction).  The relocation is
-@@ -6917,6 +6905,20 @@ ENUMDOC
-   value in two words (with an imm instruction).  The relocation is
-   relative offset from start of TEXT.
- 
-+  This is a 64 bit reloc that stores 64-bit thread pointer relative offset
-+  to two words (uses imml instruction).
-+ENUM
-+BFD_RELOC_MICROBLAZE_64,
-+ENUMDOC
-+ This is a 64 bit reloc that stores the 64 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
-+ENUM
-+BFD_RELOC_MICROBLAZE_64_PCREL,
-+ENUMDOC
-+ This is a 32 bit reloc that stores the 32 bit pc relative
-+ value in two words (with an imml instruction).  No relocation is
-+ done here - only used for relaxing
- ENUM
-   BFD_RELOC_AARCH64_RELOC_START
- ENUMDOC
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Fixed-MB-x-relocation-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Fixed-MB-x-relocation-issues.patch
new file mode 100644
index 0000000000..84a4d31605
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0018-Fixed-MB-x-relocation-issues.patch
@@ -0,0 +1,114 @@
+From 0868dedda1b7b8112870dcc69f887d32a51b94b6 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 28 Sep 2018 12:04:55 +0530
+Subject: [PATCH 18/52] -Fixed MB-x relocation issues -Added imml for required
+ MB-x instructions
+
+---
+ bfd/elf64-microblaze.c     |  68 ++++++++++++++---
+ gas/config/tc-microblaze.c | 152 +++++++++++++++++++++++++++----------
+ gas/tc.h                   |   2 +-
+ 3 files changed, 167 insertions(+), 55 deletions(-)
+
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1488,8 +1488,17 @@ microblaze_elf_relocate_section (bfd *ou
+ 			  relocation -= (input_section->output_section->vma
+ 					 + input_section->output_offset
+ 					 + offset + INST_WORD_SIZE);
+-			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
++			  {
++        		    insn &= ~0x00ffffff;
++			    insn |= (relocation >> 16) & 0xffffff;
++			    bfd_put_32 (input_bfd, insn,
+ 			            contents + offset + endian);
++			  }
++			else
++			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			              contents + offset + endian);
+ 			bfd_put_16 (input_bfd, relocation & 0xffff,
+ 			            contents + offset + endian + INST_WORD_SIZE);
+ 		      }
+@@ -1580,11 +1589,28 @@ microblaze_elf_relocate_section (bfd *ou
+ 		    else
+ 		      {
+ 			if (r_type == R_MICROBLAZE_64_PCREL)
+-			  relocation -= (input_section->output_section->vma
+-					 + input_section->output_offset
+-					 + offset + INST_WORD_SIZE);
+-			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			  {
++			    if (!input_section->output_section->vma &&
++				 !input_section->output_offset && !offset)	
++			      relocation -= (input_section->output_section->vma
++			                     + input_section->output_offset
++					     + offset);
++			    else
++			      relocation -= (input_section->output_section->vma
++			                     + input_section->output_offset
++					     + offset + INST_WORD_SIZE);
++			  }
++			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
++    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
++			  {
++        		    insn &= ~0x00ffffff;
++			    insn |= (relocation >> 16) & 0xffffff;
++			    bfd_put_32 (input_bfd, insn,
+ 			            contents + offset + endian);
++			  }
++			else
++			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
++			              contents + offset + endian);
+ 			bfd_put_16 (input_bfd, relocation & 0xffff,
+ 			            contents + offset + endian + INST_WORD_SIZE);
+ 		      }
+@@ -1703,9 +1729,19 @@ static void
+ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+ {
+     unsigned long instr = bfd_get_32 (abfd, bfd_addr);
+-    instr &= ~0x0000ffff;
+-    instr |= (val & 0x0000ffff);
+-    bfd_put_32 (abfd, instr, bfd_addr);
++
++    if (instr == 0xb2000000 || instr == 0xb2ffffff)
++      {
++        instr &= ~0x00ffffff;
++        instr |= (val & 0xffffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
++    else
++      {
++        instr &= ~0x0000ffff;
++        instr |= (val & 0x0000ffff);
++        bfd_put_32 (abfd, instr, bfd_addr);
++      }
+ }
+ 
+ /* Read-modify-write into the bfd, an immediate value into appropriate fields of
+@@ -1717,10 +1753,18 @@ microblaze_bfd_write_imm_value_64 (bfd *
+     unsigned long instr_lo;
+ 
+     instr_hi = bfd_get_32 (abfd, bfd_addr);
+-    instr_hi &= ~0x0000ffff;
+-    instr_hi |= ((val >> 16) & 0x0000ffff);
+-    bfd_put_32 (abfd, instr_hi, bfd_addr);
+-
++    if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
++      {
++        instr_hi &= ~0x00ffffff;
++        instr_hi |= (val >> 16) & 0xffffff;
++        bfd_put_32 (abfd, instr_hi,bfd_addr);
++      }
++    else
++      {
++        instr_hi &= ~0x0000ffff;
++        instr_hi |= ((val >> 16) & 0x0000ffff);
++        bfd_put_32 (abfd, instr_hi, bfd_addr);
++      }
+     instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
+     instr_lo &= ~0x0000ffff;
+     instr_lo |= (val & 0x0000ffff);
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Fixing-the-branch-related-issues.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Fixing-the-branch-related-issues.patch
new file mode 100644
index 0000000000..b3f93845ac
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Fixing-the-branch-related-issues.patch
@@ -0,0 +1,25 @@
+From 5780b5e5f9b5fe64d5172cd99399366e42c67b64 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Sun, 30 Sep 2018 17:06:58 +0530
+Subject: [PATCH 19/52] Fixing the branch related issues
+
+Conflicts:
+	bfd/elf64-microblaze.c
+---
+ bfd/elf64-microblaze.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -2545,6 +2545,9 @@ microblaze_elf_check_relocs (bfd * abfd,
+ 	  while (h->root.type == bfd_link_hash_indirect
+ 		 || h->root.type == bfd_link_hash_warning)
+ 	    h = (struct elf_link_hash_entry *) h->root.u.i.link;
++	  /* PR15323, ref flags aren't set for references in the same
++	     object.  */
++	  h->root.non_ir_ref_regular = 1;
+ 	}
+ 
+       switch (r_type)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch
deleted file mode 100644
index fc5c946436..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0019-Update-MB-x.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From 0bb779328b8564b008a6134826f043b4326f4904 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 28 Sep 2018 12:04:55 +0530
-Subject: [PATCH 19/40] Update MB-x
-
--Fixed MB-x relocation issues
--Added imml for required MB-x instructions
----
- bfd/elf64-microblaze.c     |  68 ++++++++++--
- 3 files changed, 209 insertions(+), 82 deletions(-)
-
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index d55700fc513..f8f52870639 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -1478,8 +1478,17 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 			  relocation -= (input_section->output_section->vma
- 					 + input_section->output_offset
- 					 + offset + INST_WORD_SIZE);
--			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
-+			if (insn == 0xb2000000 || insn == 0xb2ffffff)
-+			  {
-+			    insn &= ~0x00ffffff;
-+			    insn |= (relocation >> 16) & 0xffffff;
-+			    bfd_put_32 (input_bfd, insn,
- 			            contents + offset + endian);
-+			  }
-+			else
-+			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			              contents + offset + endian);
- 			bfd_put_16 (input_bfd, relocation & 0xffff,
- 			            contents + offset + endian + INST_WORD_SIZE);
- 		      }
-@@ -1569,11 +1578,28 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 		    else
- 		      {
- 			if (r_type == R_MICROBLAZE_64_PCREL)
--			  relocation -= (input_section->output_section->vma
--					 + input_section->output_offset
--					 + offset + INST_WORD_SIZE);
--			bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			  {
-+			    if (!input_section->output_section->vma &&
-+				 !input_section->output_offset && !offset)
-+			      relocation -= (input_section->output_section->vma
-+			                     + input_section->output_offset
-+					     + offset);
-+			    else
-+			      relocation -= (input_section->output_section->vma
-+			                     + input_section->output_offset
-+					     + offset + INST_WORD_SIZE);
-+			  }
-+			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
-+			if (insn == 0xb2000000 || insn == 0xb2ffffff)
-+			  {
-+			    insn &= ~0x00ffffff;
-+			    insn |= (relocation >> 16) & 0xffffff;
-+			    bfd_put_32 (input_bfd, insn,
- 			            contents + offset + endian);
-+			  }
-+			else
-+			  bfd_put_16 (input_bfd, (relocation >> 16) & 0xffff,
-+			              contents + offset + endian);
- 			bfd_put_16 (input_bfd, relocation & 0xffff,
- 			            contents + offset + endian + INST_WORD_SIZE);
- 		      }
-@@ -1677,9 +1703,19 @@ static void
- microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
- {
-     unsigned long instr = bfd_get_32 (abfd, bfd_addr);
--    instr &= ~0x0000ffff;
--    instr |= (val & 0x0000ffff);
--    bfd_put_32 (abfd, instr, bfd_addr);
-+
-+    if (instr == 0xb2000000 || instr == 0xb2ffffff)
-+      {
-+        instr &= ~0x00ffffff;
-+        instr |= (val & 0xffffff);
-+        bfd_put_32 (abfd, instr, bfd_addr);
-+      }
-+    else
-+      {
-+        instr &= ~0x0000ffff;
-+        instr |= (val & 0x0000ffff);
-+        bfd_put_32 (abfd, instr, bfd_addr);
-+      }
- }
- 
- /* Read-modify-write into the bfd, an immediate value into appropriate fields of
-@@ -1691,10 +1727,18 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
-     unsigned long instr_lo;
- 
-     instr_hi = bfd_get_32 (abfd, bfd_addr);
--    instr_hi &= ~0x0000ffff;
--    instr_hi |= ((val >> 16) & 0x0000ffff);
--    bfd_put_32 (abfd, instr_hi, bfd_addr);
--
-+    if (instr_hi == 0xb2000000 || instr_hi == 0xb2ffffff)
-+      {
-+        instr_hi &= ~0x00ffffff;
-+        instr_hi |= (val >> 16) & 0xffffff;
-+        bfd_put_32 (abfd, instr_hi,bfd_addr);
-+      }
-+    else
-+      {
-+        instr_hi &= ~0x0000ffff;
-+        instr_hi |= ((val >> 16) & 0x0000ffff);
-+        bfd_put_32 (abfd, instr_hi, bfd_addr);
-+      }
-     instr_lo = bfd_get_32 (abfd, bfd_addr + INST_WORD_SIZE);
-     instr_lo &= ~0x0000ffff;
-     instr_lo |= (val & 0x0000ffff);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Fixed-address-computation-issues-with-64bit-address.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Fixed-address-computation-issues-with-64bit-address.patch
new file mode 100644
index 0000000000..a2f34b02e1
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Fixed-address-computation-issues-with-64bit-address.patch
@@ -0,0 +1,98 @@
+From fd3df3812f8297133a598802b552252f45c80d0c Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Tue, 9 Oct 2018 10:14:22 +0530
+Subject: [PATCH 20/52] - Fixed address computation issues with 64bit address -
+ Fixed imml dissassamble issue
+
+Conflicts:
+	gas/config/tc-microblaze.c
+	opcodes/microblaze-dis.c
+---
+ bfd/bfd-in2.h              |  5 +++
+ bfd/elf64-microblaze.c     | 14 ++++----
+ gas/config/tc-microblaze.c | 74 +++++++++++++++++++++++++++++++++-----
+ opcodes/microblaze-dis.c   |  2 +-
+ 4 files changed, 79 insertions(+), 16 deletions(-)
+
+Index: gdb-9.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-9.2.orig/bfd/bfd-in2.h
++++ gdb-9.2/bfd/bfd-in2.h
+@@ -5378,6 +5378,11 @@ done here - only used for relaxing  */
+  *   +done here - only used for relaxing  */
+     BFD_RELOC_MICROBLAZE_64,
+ 
++/* This is a 64 bit reloc that stores the 32 bit relative
++ *  +value in two words (with an imml instruction).  No relocation is
++ *   +done here - only used for relaxing  */
++    BFD_RELOC_MICROBLAZE_EA64,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+  *  +value in two words (with an imm instruction).  No relocation is
+  *   +done here - only used for relaxing  */
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_h
+           0,			/* Rightshift.  */
+           4,			/* Size (0 = byte, 1 = short, 2 = long).  */
+           64,			/* Bitsize.  */
+-          TRUE,		/* PC_relative.  */
++          FALSE,		/* PC_relative.  */
+           0,			/* Bitpos.  */
+           complain_overflow_dont, /* Complain on overflow.  */
+           bfd_elf_generic_reloc,/* Special Function.  */
+           "R_MICROBLAZE_IMML_64",   	/* Name.  */
+           FALSE,		/* Partial Inplace.  */
+           0,			/* Source Mask.  */
+-          0x0000ffff,		/* Dest Mask.  */
+-          TRUE), 		/* PC relative offset?  */
++          0xffffffffffffff,		/* Dest Mask.  */
++          FALSE), 		/* PC relative offset?  */
+ 
+    /* A 64 bit relocation.  Table entry not really used.  */
+    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
+@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd *
+     case BFD_RELOC_32:
+       microblaze_reloc = R_MICROBLAZE_32;
+       break;
+-      /* RVA is treated the same as 32 */
++      /* RVA is treated the same as 64 */
+     case BFD_RELOC_RVA:
+-      microblaze_reloc = R_MICROBLAZE_32;
++      microblaze_reloc = R_MICROBLAZE_IMML_64;
+       break;
+     case BFD_RELOC_32_PCREL:
+       microblaze_reloc = R_MICROBLAZE_32_PCREL;
+@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd *
+     case BFD_RELOC_VTABLE_ENTRY:
+       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
+       break;
+-    case BFD_RELOC_MICROBLAZE_64:
++    case BFD_RELOC_MICROBLAZE_EA64:
+       microblaze_reloc = R_MICROBLAZE_IMML_64;
+       break;
+     case BFD_RELOC_MICROBLAZE_64_GOTPC:
+@@ -1982,7 +1982,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	        efix = calc_fixup (target_address, 0, sec);
+ 
+             /* Validate the in-band val.  */
+-            val = bfd_get_32 (abfd, contents + irel->r_offset);
++            val = bfd_get_64 (abfd, contents + irel->r_offset);
+             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
+                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
+             }
+Index: gdb-9.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-dis.c
++++ gdb-9.2/opcodes/microblaze-dis.c
+@@ -77,7 +77,7 @@ static char *
+ get_field_imml (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+-  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
++  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
+   return p;
+ }
+ 
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch
deleted file mode 100644
index eb0bc98287..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0020-Various-fixes.patch
+++ /dev/null
@@ -1,98 +0,0 @@
-From 188a60b441711f663f07dc3c3902c8c5d590eb6c Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Tue, 9 Oct 2018 10:14:22 +0530
-Subject: [PATCH 20/40] Various fixes
-
-- Fixed address computation issues with 64bit address
-- Fixed imml dissassamble issue
----
- bfd/bfd-in2.h              |  5 +++
- bfd/elf64-microblaze.c     | 14 ++++----
- opcodes/microblaze-dis.c   |  2 +-
- 4 files changed, 79 insertions(+), 16 deletions(-)
-
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 3899352b1d5..91761bf6964 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -5378,6 +5378,11 @@ value in two words (with an imml instruction).  No relocation is
- done here - only used for relaxing  */
-   BFD_RELOC_MICROBLAZE_64,
- 
-+/* This is a 64 bit reloc that stores the 32 bit relative
-+value in two words (with an imml instruction).  No relocation is
-+done here - only used for relaxing  */
-+    BFD_RELOC_MICROBLAZE_EA64,
-+
- /* This is a 64 bit reloc that stores the 32 bit pc relative
- value in two words (with an imm instruction).  No relocation is
- done here - only used for relaxing  */
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index f8f52870639..17e58748a0b 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -121,15 +121,15 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
-           0,			/* Rightshift.  */
-           4,			/* Size (0 = byte, 1 = short, 2 = long).  */
-           64,			/* Bitsize.  */
--          TRUE,		/* PC_relative.  */
-+          FALSE,		/* PC_relative.  */
-           0,			/* Bitpos.  */
-           complain_overflow_dont, /* Complain on overflow.  */
-           bfd_elf_generic_reloc,/* Special Function.  */
-           "R_MICROBLAZE_IMML_64",   	/* Name.  */
-           FALSE,		/* Partial Inplace.  */
-           0,			/* Source Mask.  */
--          0x0000ffff,		/* Dest Mask.  */
--          TRUE), 		/* PC relative offset?  */
-+          0xffffffffffffff,		/* Dest Mask.  */
-+          FALSE), 		/* PC relative offset?  */
- 
-    /* A 64 bit relocation.  Table entry not really used.  */
-    HOWTO (R_MICROBLAZE_64,     	/* Type.  */
-@@ -585,9 +585,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_32:
-       microblaze_reloc = R_MICROBLAZE_32;
-       break;
--      /* RVA is treated the same as 32 */
-+      /* RVA is treated the same as 64 */
-     case BFD_RELOC_RVA:
--      microblaze_reloc = R_MICROBLAZE_32;
-+      microblaze_reloc = R_MICROBLAZE_IMML_64;
-       break;
-     case BFD_RELOC_32_PCREL:
-       microblaze_reloc = R_MICROBLAZE_32_PCREL;
-@@ -619,7 +619,7 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
-     case BFD_RELOC_VTABLE_ENTRY:
-       microblaze_reloc = R_MICROBLAZE_GNU_VTENTRY;
-       break;
--    case BFD_RELOC_MICROBLAZE_64:
-+    case BFD_RELOC_MICROBLAZE_EA64:
-       microblaze_reloc = R_MICROBLAZE_IMML_64;
-       break;
-     case BFD_RELOC_MICROBLAZE_64_GOTPC:
-@@ -1956,7 +1956,7 @@ microblaze_elf_relax_section (bfd *abfd,
- 	        efix = calc_fixup (target_address, 0, sec);
- 
-             /* Validate the in-band val.  */
--            val = bfd_get_32 (abfd, contents + irel->r_offset);
-+            val = bfd_get_64 (abfd, contents + irel->r_offset);
-             if (val != irel->r_addend && ELF64_R_TYPE (irel->r_info) == R_MICROBLAZE_32_NONE) {
-                fprintf(stderr, "%d: CORRUPT relax reloc %x %lx\n", __LINE__, val, irel->r_addend);
-             }
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 437f536e96a..24ede714858 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -78,7 +78,7 @@ get_field_imml (struct string_buf *buf, long instr)
- {
-   char *p = strbuf (buf);
- 
--  sprintf (p, "%d", (short)((instr & IMML_MASK) >> IMM_LOW));
-+  sprintf (p, "%d", (int)((instr & IMML_MASK) >> IMM_LOW));
-   return p;
- }
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch
index 0d212ccc2d..abfdd8d016 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0021-Adding-new-relocation-to-support-64bit-rodata.patch
@@ -1,17 +1,18 @@
-From a485fdf959afb6cd079f482eeea9d3186e6393f8 Mon Sep 17 00:00:00 2001
+From 14a54cced8062343b83d7ff0e68f00bca562a509 Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Sat, 13 Oct 2018 21:17:01 +0530
-Subject: [PATCH 21/40] Adding new relocation to support 64bit rodata
+Subject: [PATCH 21/52] Adding new relocation to support 64bit rodata
 
 ---
  bfd/elf64-microblaze.c     | 11 +++++++--
+ gas/config/tc-microblaze.c | 49 ++++++++++++++++++++++++++++++++++----
  2 files changed, 54 insertions(+), 6 deletions(-)
 
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index 17e58748a0b..b62c47e8514 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -1463,6 +1463,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1473,6 +1473,7 @@ microblaze_elf_relocate_section (bfd *ou
  	    case (int) R_MICROBLAZE_64_PCREL :
  	    case (int) R_MICROBLAZE_64:
  	    case (int) R_MICROBLAZE_32:
@@ -19,16 +20,16 @@ index 17e58748a0b..b62c47e8514 100644
  	      {
  		/* r_symndx will be STN_UNDEF (zero) only for relocs against symbols
  		   from removed linkonce sections, or sections discarded by
-@@ -1472,6 +1473,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1482,6 +1483,8 @@ microblaze_elf_relocate_section (bfd *ou
  		    relocation += addend;
- 		    if (r_type == R_MICROBLAZE_32)
+ 		    if (r_type == R_MICROBLAZE_32)// || r_type == R_MICROBLAZE_IMML_64)
  		      bfd_put_32 (input_bfd, relocation, contents + offset);
 +		    else if (r_type == R_MICROBLAZE_IMML_64)
 +		      bfd_put_64 (input_bfd, relocation, contents + offset);
  		    else
  		      {
  			if (r_type == R_MICROBLAZE_64_PCREL)
-@@ -1549,7 +1552,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1560,7 +1563,7 @@ microblaze_elf_relocate_section (bfd *ou
  		      }
  		    else
  		      {
@@ -37,7 +38,7 @@ index 17e58748a0b..b62c47e8514 100644
  			  {
  			    outrel.r_info = ELF64_R_INFO (0, R_MICROBLAZE_REL);
  			    outrel.r_addend = relocation + addend;
-@@ -1575,6 +1578,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1586,6 +1589,8 @@ microblaze_elf_relocate_section (bfd *ou
  		    relocation += addend;
  		    if (r_type == R_MICROBLAZE_32)
  		      bfd_put_32 (input_bfd, relocation, contents + offset);
@@ -46,7 +47,7 @@ index 17e58748a0b..b62c47e8514 100644
  		    else
  		      {
  			if (r_type == R_MICROBLAZE_64_PCREL)
-@@ -2072,7 +2077,8 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2098,7 +2103,8 @@ microblaze_elf_relax_section (bfd *abfd,
                    microblaze_bfd_write_imm_value_32 (abfd, ocontents + irelscan->r_offset,
                                                       irelscan->r_addend);
                }
@@ -56,7 +57,7 @@ index 17e58748a0b..b62c47e8514 100644
                  {
  	          isym = isymbuf + ELF64_R_SYM (irelscan->r_info);
  
-@@ -2568,6 +2574,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+@@ -2606,6 +2612,7 @@ microblaze_elf_check_relocs (bfd * abfd,
          case R_MICROBLAZE_64:
          case R_MICROBLAZE_64_PCREL:
          case R_MICROBLAZE_32:
@@ -64,6 +65,3 @@ index 17e58748a0b..b62c47e8514 100644
            {
              if (h != NULL && !bfd_link_pic (info))
  	      {
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch
index aa512b87ff..3bbe2659f8 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0022-fixing-the-.bss-relocation-issue.patch
@@ -1,35 +1,35 @@
-From 24f96f4e86895b41aae21f775599a857939d002f Mon Sep 17 00:00:00 2001
+From e9e4d4837cfea27e67fa656ede535f250205eb2c Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 24 Oct 2018 12:34:37 +0530
-Subject: [PATCH 22/40] fixing the .bss relocation issue
+Subject: [PATCH 22/52] fixing the .bss relocation issue
 
 ---
  bfd/elf64-microblaze.c | 18 ++++++++++++------
  1 file changed, 12 insertions(+), 6 deletions(-)
 
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index b62c47e8514..cb3b40b574c 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -1482,7 +1482,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1492,7 +1492,7 @@ microblaze_elf_relocate_section (bfd *ou
  					 + input_section->output_offset
  					 + offset + INST_WORD_SIZE);
  			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
--			if (insn == 0xb2000000 || insn == 0xb2ffffff)
+-    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
 +			if ((insn & 0xff000000) == 0xb2000000)
  			  {
- 			    insn &= ~0x00ffffff;
+         		    insn &= ~0x00ffffff;
  			    insn |= (relocation >> 16) & 0xffffff;
-@@ -1595,7 +1595,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
+@@ -1606,7 +1606,7 @@ microblaze_elf_relocate_section (bfd *ou
  					     + offset + INST_WORD_SIZE);
  			  }
  			unsigned long insn = bfd_get_32 (input_bfd, contents + offset +endian);
--			if (insn == 0xb2000000 || insn == 0xb2ffffff)
+-    			if (insn == 0xb2000000 || insn == 0xb2ffffff)
 +			if ((insn & 0xff000000) == 0xb2000000)
  			  {
- 			    insn &= ~0x00ffffff;
+         		    insn &= ~0x00ffffff;
  			    insn |= (relocation >> 16) & 0xffffff;
-@@ -1709,7 +1709,7 @@ microblaze_bfd_write_imm_value_32 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+@@ -1735,7 +1735,7 @@ microblaze_bfd_write_imm_value_32 (bfd *
  {
      unsigned long instr = bfd_get_32 (abfd, bfd_addr);
  
@@ -38,7 +38,7 @@ index b62c47e8514..cb3b40b574c 100644
        {
          instr &= ~0x00ffffff;
          instr |= (val & 0xffffff);
-@@ -1732,7 +1732,7 @@ microblaze_bfd_write_imm_value_64 (bfd *abfd, bfd_byte *bfd_addr, bfd_vma val)
+@@ -1758,7 +1758,7 @@ microblaze_bfd_write_imm_value_64 (bfd *
      unsigned long instr_lo;
  
      instr_hi = bfd_get_32 (abfd, bfd_addr);
@@ -47,7 +47,7 @@ index b62c47e8514..cb3b40b574c 100644
        {
          instr_hi &= ~0x00ffffff;
          instr_hi |= (val >> 16) & 0xffffff;
-@@ -2225,7 +2225,10 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2251,7 +2251,10 @@ microblaze_elf_relax_section (bfd *abfd,
            unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
                                                  + irelscan->r_offset
                                                  + INST_WORD_SIZE);
@@ -59,7 +59,7 @@ index b62c47e8514..cb3b40b574c 100644
            immediate |= (instr_lo & 0x0000ffff);
  		      offset = calc_fixup (irelscan->r_addend, 0, sec);
  		      immediate -= offset;
-@@ -2269,7 +2272,10 @@ microblaze_elf_relax_section (bfd *abfd,
+@@ -2295,7 +2298,10 @@ microblaze_elf_relax_section (bfd *abfd,
            unsigned long instr_lo =  bfd_get_32 (abfd, ocontents
                                                  + irelscan->r_offset
                                                  + INST_WORD_SIZE);
@@ -71,6 +71,3 @@ index b62c47e8514..cb3b40b574c 100644
            immediate |= (instr_lo & 0x0000ffff);
  		      target_address = immediate;
  		      offset = calc_fixup (target_address, 0, sec);
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
index c645781e48..b359ce723f 100644
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0023-Fixed-the-bug-in-the-R_MICROBLAZE_64_NONE-relocation.patch
@@ -1,7 +1,7 @@
-From cd5868dca5b4a728e6418459d871f5c9ca68253e Mon Sep 17 00:00:00 2001
+From 1466dd2c74e38ae6d1dca5cf6d4cad87c94fbc8f Mon Sep 17 00:00:00 2001
 From: Nagaraju Mekala <nmekala@xilix.com>
 Date: Wed, 28 Nov 2018 14:00:29 +0530
-Subject: [PATCH 23/40] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
+Subject: [PATCH 23/52] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
  It was adjusting only lower 16bits.
 
 ---
@@ -9,10 +9,10 @@ Subject: [PATCH 23/40] Fixed the bug in the R_MICROBLAZE_64_NONE relocation.
  bfd/elf64-microblaze.c | 4 ++--
  2 files changed, 4 insertions(+), 4 deletions(-)
 
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index a31b407cfbf..04816a4a187 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
 @@ -2023,8 +2023,8 @@ microblaze_elf_relax_section (bfd *abfd,
  		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
  		efix = calc_fixup (target_address, 0, sec);
@@ -24,11 +24,11 @@ index a31b407cfbf..04816a4a187 100644
  	      }
  	      break;
  	    }
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index cb3b40b574c..b002b414d64 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -2004,8 +2004,8 @@ microblaze_elf_relax_section (bfd *abfd,
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -2030,8 +2030,8 @@ microblaze_elf_relax_section (bfd *abfd,
  		sfix = calc_fixup (irel->r_offset + INST_WORD_SIZE, 0, sec);
  		efix = calc_fixup (target_address, 0, sec);
  		irel->r_addend -= (efix - sfix);
@@ -39,6 +39,3 @@ index cb3b40b574c..b002b414d64 100644
  	      }
  	      break;
  	    }
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
deleted file mode 100644
index f5bf917a6c..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-Patch-Microblaze-Binutils-security-check-is-causing-.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 25a67af22ad040f87b3c14185c338828d4e26908 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 11 Mar 2019 14:23:58 +0530
-Subject: [PATCH 25/40] [Patch,Microblaze] : Binutils security check is causing
- build error for windows builds.commenting for now.
-
----
- bfd/elf-attrs.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/bfd/elf-attrs.c b/bfd/elf-attrs.c
-index bfe135e7fbb..abf267ad42e 100644
---- a/bfd/elf-attrs.c
-+++ b/bfd/elf-attrs.c
-@@ -440,6 +440,8 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
-   /* PR 17512: file: 2844a11d.  */
-   if (hdr->sh_size == 0)
-     return;
-+
-+  #if 0
-   if (hdr->sh_size > bfd_get_file_size (abfd))
-     {
-       /* xgettext:c-format */
-@@ -448,6 +450,7 @@ _bfd_elf_parse_attributes (bfd *abfd, Elf_Internal_Shdr * hdr)
-       bfd_set_error (bfd_error_invalid_operation);
-       return;
-     }
-+  #endif
- 
-   contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
-   if (!contents)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
new file mode 100644
index 0000000000..c2ae39e8cc
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0025-fixing-the-long-long-long-mingw-toolchain-issue.patch
@@ -0,0 +1,25 @@
+From f64c95b119637880e8898b459e7665f0d92cef20 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 29 Nov 2018 17:59:25 +0530
+Subject: [PATCH 25/52] fixing the long & long long mingw toolchain issue
+
+---
+ gas/config/tc-microblaze.c | 10 +++++-----
+ opcodes/microblaze-opc.h   |  4 ++--
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) 0xffffff8000000000L)
++#define MAX_IMML  ((long long) 0x0000007fffffffffL)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-Added-support-to-new-arithmetic-single-register-inst.patch
new file mode 100644
index 0000000000..90094aba3d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-Added-support-to-new-arithmetic-single-register-inst.patch
@@ -0,0 +1,169 @@
+From b8128385902d88414c354b772828eefe3b59fb06 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 23 Aug 2019 16:18:43 +0530
+Subject: [PATCH 26/52] Added support to new arithmetic single register
+ instructions
+
+Conflicts:
+	opcodes/microblaze-dis.c
+---
+ gas/config/tc-microblaze.c | 147 ++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   |  13 +++-
+ opcodes/microblaze-opc.h   |  43 ++++++++++-
+ opcodes/microblaze-opcm.h  |   5 +-
+ 4 files changed, 201 insertions(+), 7 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-dis.c
++++ gdb-9.2/opcodes/microblaze-dis.c
+@@ -130,9 +130,17 @@ get_field_imm15 (struct string_buf *buf,
+   return p;
+ }
+ 
++get_field_imm16 (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
++  return p;
++}
++
+ static char *
+ get_field_special (struct string_buf *buf, long instr,
+-		   struct op_code_struct *op)
++                   struct op_code_struct *op)
+ {
+   char *p = strbuf (buf);
+   char *spr;
+@@ -454,6 +462,9 @@ print_insn_microblaze (bfd_vma memaddr,
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
++	case INST_TYPE_RD_IMML:
++	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
++          break;
+         /* For bit field insns.  */
+ 	case INST_TYPE_RD_R1_IMMW_IMMS:
+           print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_immw (&buf, inst), get_field_imms (&buf, inst));
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -69,6 +69,7 @@
+ #define INST_TYPE_RD_R1_IMMW_IMMS  21
+ 
+ #define INST_TYPE_NONE 25
++#define INST_TYPE_RD_IMML 26
+ 
+ 
+ 
+@@ -84,6 +85,7 @@
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+ #define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
++#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
+ #define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
+ #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
+ #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
+@@ -106,6 +108,33 @@
+ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ #define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
+ 
++/*Defines to identify 64-bit single reg instructions */
++#define ADDLI_ONE_REG_MASK 0x68000000
++#define ADDLIC_ONE_REG_MASK 0x68020000
++#define ADDLIK_ONE_REG_MASK 0x68040000
++#define ADDLIKC_ONE_REG_MASK 0x68060000
++#define RSUBLI_ONE_REG_MASK 0x68010000
++#define RSUBLIC_ONE_REG_MASK 0x68030000
++#define RSUBLIK_ONE_REG_MASK 0x68050000
++#define RSUBLIKC_ONE_REG_MASK 0x68070000
++#define ORLI_ONE_REG_MASK 0x68100000
++#define ANDLI_ONE_REG_MASK 0x68110000
++#define XORLI_ONE_REG_MASK 0x68120000
++#define ANDLNI_ONE_REG_MASK 0x68130000
++#define ADDLI_MASK 0x20000000
++#define ADDLIC_MASK 0x28000000
++#define ADDLIK_MASK 0x30000000
++#define ADDLIKC_MASK 0x38000000
++#define RSUBLI_MASK 0x24000000
++#define RSUBLIC_MASK 0x2C000000
++#define RSUBLIK_MASK 0x34000000
++#define RSUBLIKC_MASK 0x3C000000
++#define ANDLI_MASK 0xA4000000
++#define ANDLNI_MASK 0xAC000000
++#define ORLI_MASK 0xA0000000
++#define XORLI_MASK 0xA8000000
++
++
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+ /* Mask for mbar insn.  */
+@@ -114,7 +143,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 412
++#define MAX_OPCODES 424
+ 
+ struct op_code_struct
+ {
+@@ -444,13 +473,21 @@ struct op_code_struct
+   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
+   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
+   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
+   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
+   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
+   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
+   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
+   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
+   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
++  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
+   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
++  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
+   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
+   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
+   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
+@@ -501,9 +538,13 @@ struct op_code_struct
+   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
+   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
+   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
+   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
+   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
+   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
++  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
+   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
+   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
+   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
+Index: gdb-9.2/opcodes/microblaze-opcm.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opcm.h
++++ gdb-9.2/opcodes/microblaze-opcm.h
+@@ -61,7 +61,9 @@ enum microblaze_instr
+   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
+ 
+   /* 64-bit instructions */
+-  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
++  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
++  andli, andnli, orli, xorli,
+   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
+   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
+   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
+@@ -166,5 +168,6 @@ enum microblaze_instr_type
+ 
+ /* Imm mask for msrset, msrclr instructions.  */
+ #define  IMM15_MASK 0x00007FFF
++#define IMM16_MASK 0x0000FFFF
+ 
+ #endif /* MICROBLAZE-OPCM */
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
deleted file mode 100644
index f5ddce4173..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0026-fixing-the-long-long-long-mingw-toolchain-issue.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From b9e89f0698fd0e3b0e965986681f9fd90d3dc313 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 29 Nov 2018 17:59:25 +0530
-Subject: [PATCH 26/40] fixing the long & long long mingw toolchain issue
-
----
- opcodes/microblaze-opc.h   |  4 ++--
- 2 files changed, 7 insertions(+), 7 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index f4ee8f43372..c8c2addc351 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -585,8 +585,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM6_WIDTH  ((int) 0x00000001)
- #define MAX_IMM6_WIDTH  ((int) 0x00000040)
- 
--#define MIN_IMML  ((long) 0xffffff8000000000L)
--#define MAX_IMML  ((long) 0x0000007fffffffffL)
-+#define MIN_IMML  ((long long) 0xffffff8000000000L)
-+#define MAX_IMML  ((long long) 0x0000007fffffffffL)
- 
- #endif /* MICROBLAZE_OPC */
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch
deleted file mode 100644
index bf05816db0..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Added-support-to-new-arithmetic-single-register-inst.patch
+++ /dev/null
@@ -1,181 +0,0 @@
-From efc3fd518cdb7e8bf82ac27b98b946001f83a2bf Mon Sep 17 00:00:00 2001
-From: Nagaraju <nmekala@xilinx.com>
-Date: Fri, 23 Aug 2019 16:18:43 +0530
-Subject: [PATCH 27/40] Added support to new arithmetic single register
- instructions
-
----
- opcodes/microblaze-dis.c   |  13 +++-
- opcodes/microblaze-opc.h   |  45 +++++++++++-
- opcodes/microblaze-opcm.h  |   5 +-
- 4 files changed, 201 insertions(+), 7 deletions(-)
-
-diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
-index 24ede714858..e93d9b890ba 100644
---- a/opcodes/microblaze-dis.c
-+++ b/opcodes/microblaze-dis.c
-@@ -131,6 +131,15 @@ get_field_imm15 (struct string_buf *buf, long instr)
-   return p;
- }
- 
-+static char *
-+get_field_imm16 (struct string_buf *buf, long instr)
-+{
-+  char *p = strbuf (buf);
-+
-+  sprintf (p, "%d", (short)((instr & IMM16_MASK) >> IMM_LOW));
-+  return p;
-+}
-+
- static char *
- get_field_special (struct string_buf *buf, long instr,
- 		   struct op_code_struct *op)
-@@ -448,6 +457,9 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst),
- 		      get_field_imm15 (&buf, inst));
- 	  break;
-+	case INST_TYPE_RD_IMML:
-+	  print_func (stream, "\t%s, %s", get_field_rd (&buf, inst), get_field_imm16 (&buf, inst));
-+	  break;
- 	  /* For mbar insn.  */
- 	case INST_TYPE_IMM5:
- 	  print_func (stream, "\t%s", get_field_imm5_mbar (&buf, inst));
-@@ -455,7 +467,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
- 	  /* For mbar 16 or sleep insn.  */
- 	case INST_TYPE_NONE:
- 	  break;
--	  /* For tuqula instruction */
-         /* For bit field insns.  */
- 	case INST_TYPE_RD_R1_IMMW_IMMS:
- 	  print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst), get_field_r1(&buf, inst),
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index c8c2addc351..eaf4a1bd9f9 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -69,6 +69,7 @@
- #define INST_TYPE_RD_R1_IMMW_IMMS  21
- 
- #define INST_TYPE_NONE 25
-+#define INST_TYPE_RD_IMML 26
- 
- 
- 
-@@ -84,6 +85,7 @@
- #define IMMVAL_MASK_MFS 0x0000
- 
- #define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
-+#define OPCODE_MASK_LIMM 0xFC1F0000 /* High 6 bits and 12-16 bits */
- #define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
- #define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
- #define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
-@@ -106,6 +108,33 @@
- #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
- #define OPCODE_MASK_H8  0xFF000000  /* High 8 bits only.  */
- 
-+/*Defines to identify 64-bit single reg instructions */
-+#define ADDLI_ONE_REG_MASK 0x68000000
-+#define ADDLIC_ONE_REG_MASK 0x68020000
-+#define ADDLIK_ONE_REG_MASK 0x68040000
-+#define ADDLIKC_ONE_REG_MASK 0x68060000
-+#define RSUBLI_ONE_REG_MASK 0x68010000
-+#define RSUBLIC_ONE_REG_MASK 0x68030000
-+#define RSUBLIK_ONE_REG_MASK 0x68050000
-+#define RSUBLIKC_ONE_REG_MASK 0x68070000
-+#define ORLI_ONE_REG_MASK 0x68100000
-+#define ANDLI_ONE_REG_MASK 0x68110000
-+#define XORLI_ONE_REG_MASK 0x68120000
-+#define ANDLNI_ONE_REG_MASK 0x68130000
-+#define ADDLI_MASK 0x20000000
-+#define ADDLIC_MASK 0x28000000
-+#define ADDLIK_MASK 0x30000000
-+#define ADDLIKC_MASK 0x38000000
-+#define RSUBLI_MASK 0x24000000
-+#define RSUBLIC_MASK 0x2C000000
-+#define RSUBLIK_MASK 0x34000000
-+#define RSUBLIKC_MASK 0x3C000000
-+#define ANDLI_MASK 0xA4000000
-+#define ANDLNI_MASK 0xAC000000
-+#define ORLI_MASK 0xA0000000
-+#define XORLI_MASK 0xA8000000
-+
-+
- /* New Mask for msrset, msrclr insns.  */
- #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
- /* Mask for mbar insn.  */
-@@ -114,13 +143,13 @@
- #define DELAY_SLOT 1
- #define NO_DELAY_SLOT 0
- 
--#define MAX_OPCODES 412
-+#define MAX_OPCODES 424
- 
- struct op_code_struct
- {
-   const char * name;
-   short inst_type;            /* Registers and immediate values involved.  */
--  short inst_offset_type;     /* Immediate vals offset from PC? (= 1 for branches).  */
-+  int inst_offset_type;     /* Immediate vals offset from PC? (= 1 for branches).  */
-   short delay_slots;          /* Info about delay slots needed after this instr. */
-   short immval_mask;
-   unsigned long bit_sequence; /* All the fixed bits for the op are set and
-@@ -444,13 +473,21 @@ struct op_code_struct
-   {"cmpl",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000101, OPCODE_MASK_H4, cmpl, arithmetic_inst },
-   {"cmplu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x14000103, OPCODE_MASK_H4, cmplu, arithmetic_inst },
-   {"addli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x20000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68000000, OPCODE_MASK_LIMM, addli, arithmetic_inst },
-   {"rsubli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x24000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsubli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68010000, OPCODE_MASK_LIMM, rsubli, arithmetic_inst },
-   {"addlic",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x28000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68020000, OPCODE_MASK_LIMM, addlic, arithmetic_inst },
-   {"rsublic", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x2C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+    {"rsublic", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68030000, OPCODE_MASK_LIMM, rsublic, arithmetic_inst },
-   {"addlik",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x30000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68040000, OPCODE_MASK_LIMM, addlik, arithmetic_inst },
-   {"rsublik", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x34000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"rsublik", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68050000, OPCODE_MASK_LIMM, rsublik, arithmetic_inst },
-   {"addlikc", INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x38000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },   /* Identical to 32-bit */
-+  {"addlikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68060000, OPCODE_MASK_LIMM, addlikc, arithmetic_inst },
-   {"rsublikc",INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x3C000000, OPCODE_MASK_H, invalid_inst, arithmetic_inst },  /* Identical to 32-bit */
-+  {"rsublikc", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68070000, OPCODE_MASK_LIMM, rsublikc, arithmetic_inst },
-   {"mull",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x40000100, OPCODE_MASK_H4, mull, mult_inst },
-   {"bslll",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000500, OPCODE_MASK_H3, bslll, barrel_shift_inst },
-   {"bslra",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x44000300, OPCODE_MASK_H3, bslra, barrel_shift_inst },
-@@ -501,9 +538,13 @@ struct op_code_struct
-   {"beaged",  INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00000, OPCODE_MASK_H14, beaged, branch_inst },
-   {"bealged", INST_TYPE_R1_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x9FA00100, OPCODE_MASK_H14, bealged, branch_inst },
-   {"orli",    INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA0000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"orli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68100000, OPCODE_MASK_LIMM, orli, arithmetic_inst },
-   {"andli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68110000, OPCODE_MASK_LIMM, andli, arithmetic_inst },
-   {"xorli",   INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA8000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"xorli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68120000, OPCODE_MASK_LIMM, xorli, arithmetic_inst },
-   {"andnli",  INST_TYPE_RD_R1_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xAC000000, OPCODE_MASK_H, invalid_inst, logical_inst },      /* Identical to 32-bit */
-+  {"andnli", INST_TYPE_RD_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL,0x68130000, OPCODE_MASK_LIMM, andnli, arithmetic_inst },
-   {"imml",    INST_TYPE_IMML, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB2000000, OPCODE_MASK_H8, imml, immediate_inst },
-   {"breai",   INST_TYPE_IMM, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8010000, OPCODE_MASK_H12, breai, branch_inst },
-   {"breaid",  INST_TYPE_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8110000, OPCODE_MASK_H12, breaid, branch_inst },
-diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
-index ee01cdb7d9b..31726c9b01a 100644
---- a/opcodes/microblaze-opcm.h
-+++ b/opcodes/microblaze-opcm.h
-@@ -61,7 +61,9 @@ enum microblaze_instr
-   eaputd, teaputd, ecaputd, tecaputd, neaputd, tneaputd, necaputd, tnecaputd,
- 
-   /* 64-bit instructions */
--  addl, rsubl, addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  addl, addli, addlic, addlik, addlikc, rsubl, rsubli, rsublic, rsublik, rsublikc,
-+  addlc, rsublc, addlk, rsublk, addlkc, rsublkc, cmpl, cmplu, mull,
-+  andli, andnli, orli, xorli,
-   bslll, bslra, bslrl, bsllli, bslrai, bslrli, bslefi, bslifi, orl, andl, xorl,
-   andnl, pcmplbf, pcmpleq, pcmplne, srla, srlc, srll, sextl8, sextl16, sextl32,
-   brea, bread, breald, beaeq, bealeq, beaeqd, bealeqd, beane, bealne, beaned,
-@@ -166,5 +168,6 @@ enum microblaze_instr_type
- 
- /* Imm mask for msrset, msrclr instructions.  */
- #define  IMM15_MASK 0x00007FFF
-+#define IMM16_MASK 0x0000FFFF
- 
- #endif /* MICROBLAZE-OPCM */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
new file mode 100644
index 0000000000..bbcac109cd
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0027-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
@@ -0,0 +1,26 @@
+From 41b562250cdac5fd821267c6dac68b799d80dbe3 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 26 Aug 2019 15:29:42 +0530
+Subject: [PATCH 27/52] [Patch,MicroBlaze] : double imml generation for 64 bit
+ values.
+
+---
+ gas/config/tc-microblaze.c | 322 ++++++++++++++++++++++++++++++-------
+ opcodes/microblaze-opc.h   |   4 +-
+ 2 files changed, 263 insertions(+), 63 deletions(-)
+
+Index: gdb-9.2/opcodes/microblaze-opc.h
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-opc.h
++++ gdb-9.2/opcodes/microblaze-opc.h
+@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM6_WIDTH  ((int) 0x00000001)
+ #define MAX_IMM6_WIDTH  ((int) 0x00000040)
+ 
+-#define MIN_IMML  ((long long) 0xffffff8000000000L)
+-#define MAX_IMML  ((long long) 0x0000007fffffffffL)
++#define MIN_IMML  ((long long) -9223372036854775808)
++#define MAX_IMML  ((long long) 9223372036854775807)
+ 
+ #endif /* MICROBLAZE_OPC */
+ 
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
deleted file mode 100644
index 01d615da7f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0028-Patch-MicroBlaze-double-imml-generation-for-64-bit-v.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 953a4eb8152c0aca3e36ccc22a8950c9e68965b5 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 26 Aug 2019 15:29:42 +0530
-Subject: [PATCH 28/40] [Patch,MicroBlaze] : double imml generation for 64 bit
- values.
-
----
- opcodes/microblaze-opc.h   |   4 +-
- 2 files changed, 264 insertions(+), 64 deletions(-)
-
-diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
-index eaf4a1bd9f9..79c3cf0d1a1 100644
---- a/opcodes/microblaze-opc.h
-+++ b/opcodes/microblaze-opc.h
-@@ -626,8 +626,8 @@ char pvr_register_prefix[] = "rpvr";
- #define MIN_IMM6_WIDTH  ((int) 0x00000001)
- #define MAX_IMM6_WIDTH  ((int) 0x00000040)
- 
--#define MIN_IMML  ((long long) 0xffffff8000000000L)
--#define MAX_IMML  ((long long) 0x0000007fffffffffL)
-+#define MIN_IMML  ((long long) -9223372036854775807)
-+#define MAX_IMML  ((long long) 9223372036854775807)
- 
- #endif /* MICROBLAZE_OPC */
- 
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
new file mode 100644
index 0000000000..f5280eba2a
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0032-ld-emulparams-elf64microblaze-Fix-emulation-generati.patch
@@ -0,0 +1,40 @@
+From ef6fd1a60979ca1d9fc419ec840641019bc86ac2 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Mon, 30 Nov 2020 16:17:36 -0800
+Subject: [PATCH 32/52] ld/emulparams/elf64microblaze: Fix emulation generation
+
+Compilation fails when building ld-new with:
+
+ldemul.o:(.data.rel+0x820): undefined reference to `ld_elf64microblazeel_emulation'
+ldemul.o:(.data.rel+0x828): undefined reference to `ld_elf64microblaze_emulation'
+
+The error appears to be that the elf64 files were referencing the elf32 emulation.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ ld/emulparams/elf64microblaze.sh   | 2 +-
+ ld/emulparams/elf64microblazeel.sh | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/ld/emulparams/elf64microblaze.sh
+===================================================================
+--- gdb-9.2.orig/ld/emulparams/elf64microblaze.sh
++++ gdb-9.2/ld/emulparams/elf64microblaze.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
+Index: gdb-9.2/ld/emulparams/elf64microblazeel.sh
+===================================================================
+--- gdb-9.2.orig/ld/emulparams/elf64microblazeel.sh
++++ gdb-9.2/ld/emulparams/elf64microblazeel.sh
+@@ -19,5 +19,5 @@ NOP=0x80000000
+ #$@{RELOCATING+ PROVIDE (__stack = 0x7000);@}
+ #OTHER_RELOCATING_SECTIONS='PROVIDE (_stack = _end + 0x1000);'
+ 
+-TEMPLATE_NAME=elf32
++TEMPLATE_NAME=elf
+ #GENERATE_SHLIB_SCRIPT=yes
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
new file mode 100644
index 0000000000..c82a988396
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Add-initial-port-of-linux-gdbserver-add-gdb_proc_ser.patch
@@ -0,0 +1,429 @@
+From d495e03657b25b793f7c9bdd689fdc2d1633a47b Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 23 Jan 2017 19:07:44 +0530
+Subject: [PATCH 33/52] Add initial port of linux gdbserver add
+ gdb_proc_service_h to gdbserver microblaze-linux
+
+gdbserver needs to initialise the microblaze registers
+
+other archs use this step to run a *_arch_setup() to carry out all
+architecture specific setup - may need to add in future
+
+ * add linux-ptrace.o to gdbserver configure
+ * Update breakpoint opcode
+ * fix segfault on connecting gdbserver
+ * add microblaze_linux_memory_remove_breakpoint
+ * add set_solib_svr4_fetch_link_map_offsets
+ * add set_gdbarch_fetch_tls_load_module_address
+ * Force reading of r0 as 0, prevent stores
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/configure.host                   |   3 +
+ gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++
+ gdb/microblaze-linux-tdep.c          |  29 +++-
+ gdb/microblaze-tdep.c                |  35 ++++-
+ gdb/microblaze-tdep.h                |   4 +-
+ gdb/regformats/reg-microblaze.dat    |  41 ++++++
+ 6 files changed, 298 insertions(+), 3 deletions(-)
+ create mode 100644 gdb/gdbserver/linux-microblaze-low.c
+ create mode 100644 gdb/regformats/reg-microblaze.dat
+
+Index: gdb-9.2/gdb/configure.host
+===================================================================
+--- gdb-9.2.orig/gdb/configure.host
++++ gdb-9.2/gdb/configure.host
+@@ -65,6 +65,7 @@ hppa*)			gdb_host_cpu=pa ;;
+ i[34567]86*)		gdb_host_cpu=i386 ;;
+ m68*)			gdb_host_cpu=m68k ;;
+ mips*)			gdb_host_cpu=mips ;;
++microblaze*)		gdb_host_cpu=microblaze ;;
+ powerpc* | rs6000)	gdb_host_cpu=powerpc ;;
+ sparcv9 | sparc64)	gdb_host_cpu=sparc ;;
+ s390*)			gdb_host_cpu=s390 ;;
+@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
+ mips*-*-freebsd*)	gdb_host=fbsd ;;
+ mips64*-*-openbsd*)	gdb_host=obsd64 ;;
+ 
++microblaze*-*linux*)	gdb_host=linux ;;
++
+ powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
+ 			gdb_host=aix ;;
+ powerpc*-*-freebsd*)	gdb_host=fbsd ;;
+Index: gdb-9.2/gdb/gdbserver/linux-microblaze-low.c
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/gdbserver/linux-microblaze-low.c
+@@ -0,0 +1,189 @@
++/* GNU/Linux/Microblaze specific low level interface, for the remote server for
++   GDB.
++   Copyright (C) 1995-2013 Free Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "server.h"
++#include "linux-low.h"
++
++#include <asm/ptrace.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++#include "gdb_proc_service.h"
++
++static int microblaze_regmap[] =
++ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
++  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
++  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
++  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
++  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
++  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
++  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
++  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
++  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
++  PT_FSR
++  };
++
++#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++
++/* Defined in auto-generated file microblaze-linux.c.  */
++void init_registers_microblaze (void);
++
++static int
++microblaze_cannot_store_register (int regno)
++{
++  if (microblaze_regmap[regno] == -1 || regno == 0)
++    return 1;
++
++  return 0;
++}
++
++static int
++microblaze_cannot_fetch_register (int regno)
++{
++  return 0;
++}
++
++static CORE_ADDR
++microblaze_get_pc (struct regcache *regcache)
++{
++  unsigned long pc;
++
++  collect_register_by_name (regcache, "pc", &pc);
++  return (CORE_ADDR) pc;
++}
++
++static void
++microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  unsigned long newpc = pc;
++
++  supply_register_by_name (regcache, "pc", &newpc);
++}
++
++/* dbtrap insn */
++/* brki r16, 0x18; */
++static const unsigned long microblaze_breakpoint = 0xba0c0018;
++#define microblaze_breakpoint_len 4
++
++static int
++microblaze_breakpoint_at (CORE_ADDR where)
++{
++  unsigned long insn;
++
++  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
++  if (insn == microblaze_breakpoint)
++    return 1;
++  /* If necessary, recognize more trap instructions here.  GDB only uses the
++     one.  */
++  return 0;
++}
++
++static CORE_ADDR
++microblaze_reinsert_addr (struct regcache *regcache)
++{
++  unsigned long pc;
++  collect_register_by_name (regcache, "r15", &pc);
++  return pc;
++}
++
++#ifdef HAVE_PTRACE_GETREGS
++
++static void
++microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
++{
++  int size = register_size (regno);
++
++  memset (buf, 0, sizeof (long));
++
++  if (size < sizeof (long))
++    collect_register (regcache, regno, buf + sizeof (long) - size);
++  else
++    collect_register (regcache, regno, buf);
++}
++
++static void
++microblaze_supply_ptrace_register (struct regcache *regcache,
++			    int regno, const char *buf)
++{
++  int size = register_size (regno);
++
++  if (regno == 0) {
++    unsigned long regbuf_0 = 0;
++    /* clobbering r0 so that it is always 0 as enforced by hardware */
++    supply_register (regcache, regno, (const char*)&regbuf_0);
++  } else {
++      if (size < sizeof (long))
++        supply_register (regcache, regno, buf + sizeof (long) - size);
++      else
++        supply_register (regcache, regno, buf);
++  }
++}
++
++/* Provide only a fill function for the general register set.  ps_lgetregs
++   will use this for NPTL support.  */
++
++static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++static void
++microblaze_store_gregset (struct regcache *regcache, const void *buf)
++{
++  int i;
++
++  for (i = 0; i < 32; i++)
++    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
++}
++
++#endif /* HAVE_PTRACE_GETREGS */
++
++struct regset_info target_regsets[] = {
++#ifdef HAVE_PTRACE_GETREGS
++  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
++  { 0, 0, 0, -1, -1, NULL, NULL },
++#endif /* HAVE_PTRACE_GETREGS */
++  { 0, 0, 0, -1, -1, NULL, NULL }
++};
++
++struct linux_target_ops the_low_target = {
++  init_registers_microblaze,
++  microblaze_num_regs,
++  microblaze_regmap,
++  NULL,
++  microblaze_cannot_fetch_register,
++  microblaze_cannot_store_register,
++  NULL, /* fetch_register */
++  microblaze_get_pc,
++  microblaze_set_pc,
++  (const unsigned char *) &microblaze_breakpoint,
++  microblaze_breakpoint_len,
++  microblaze_reinsert_addr,
++  0,
++  microblaze_breakpoint_at,
++  NULL,
++  NULL,
++  NULL,
++  NULL,
++  microblaze_collect_ptrace_register,
++  microblaze_supply_ptrace_register,
++};
+Index: gdb-9.2/gdb/microblaze-linux-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-linux-tdep.c
++++ gdb-9.2/gdb/microblaze-linux-tdep.c
+@@ -37,6 +37,22 @@
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
+ 
++static int microblaze_debug_flag = 0;
++
++static void
++microblaze_debug (const char *fmt, ...)
++{
++  if (microblaze_debug_flag)
++    {
++       va_list args;
++
++       va_start (args, fmt);
++       printf_unfiltered ("MICROBLAZE LINUX: ");
++       vprintf_unfiltered (fmt, args);
++       va_end (args);
++    }
++}
++
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+ 					   struct bp_target_info *bp_tgt)
+@@ -46,18 +62,25 @@ microblaze_linux_memory_remove_breakpoin
+   int val;
+   int bplen;
+   gdb_byte old_contents[BREAKPOINT_MAX];
++  struct cleanup *cleanup;
+ 
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ 
++  /* Make sure we see the memory breakpoints.  */
++  cleanup = make_show_memory_breakpoints_cleanup (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+      program modified the code on us, so it is wrong to put back the
+      old value.  */
+   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
+-    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++  {
++      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
+ 
++  do_cleanups (cleanup);
+   return val;
+ }
+ 
+@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarc
+   /* Trampolines.  */
+   tramp_frame_prepend_unwinder (gdbarch,
+ 				&microblaze_linux_sighandler_tramp_frame);
++
++  /* Enable TLS support.  */
++  set_gdbarch_fetch_tls_load_module_address (gdbarch,
++                                             svr4_fetch_objfile_link_map);
+ }
+ 
+ void
+Index: gdb-9.2/gdb/microblaze-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.c
++++ gdb-9.2/gdb/microblaze-tdep.c
+@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static int
++microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
++				    struct bp_target_info *bp_tgt)
++{
++  CORE_ADDR addr = bp_tgt->placed_address;
++  const unsigned char *bp;
++  int val;
++  int bplen;
++  gdb_byte old_contents[BREAKPOINT_MAX];
++  struct cleanup *cleanup;
++
++  /* Determine appropriate breakpoint contents and size for this address.  */
++  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
++  if (bp == NULL)
++    error (_("Software breakpoints not implemented for this target."));
++
++  /* Make sure we see the memory breakpoints.  */
++  cleanup = make_show_memory_breakpoints_cleanup (1);
++  val = target_read_memory (addr, old_contents, bplen);
++
++  /* If our breakpoint is no longer at the address, this means that the
++     program modified the code on us, so it is wrong to put back the
++     old value.  */
++  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
++  {
++    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
++    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
++  }
+ 
++  do_cleanups (cleanup);
++  return val;
++}
+ 
+ /* Allocate and initialize a frame cache.  */
+ 
+@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_
+ 				       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ 				       microblaze_breakpoint::bp_from_kind);
++  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+@@ -770,4 +802,5 @@ When non-zero, microblaze specific debug
+ 			     NULL,
+ 			     &setdebuglist, &showdebuglist);
+ 
++
+ }
+Index: gdb-9.2/gdb/microblaze-tdep.h
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.h
++++ gdb-9.2/gdb/microblaze-tdep.h
+@@ -117,6 +117,8 @@ struct microblaze_frame_cache
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+-#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
++#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
++#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
++
+ 
+ #endif /* microblaze-tdep.h */
+Index: gdb-9.2/gdb/regformats/reg-microblaze.dat
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/regformats/reg-microblaze.dat
+@@ -0,0 +1,41 @@
++name:microblaze
++expedite:r1,pc
++32:r0
++32:r1
++32:r2
++32:r3
++32:r4
++32:r5
++32:r6
++32:r7
++32:r8
++32:r9
++32:r10
++32:r11
++32:r12
++32:r13
++32:r14
++32:r15
++32:r16
++32:r17
++32:r18
++32:r19
++32:r20
++32:r21
++32:r22
++32:r23
++32:r24
++32:r25
++32:r26
++32:r27
++32:r28
++32:r29
++32:r30
++32:r31
++32:pc
++32:msr
++32:ear
++32:esr
++32:fsr
++32:slr
++32:shr
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch
deleted file mode 100644
index 4172595ba3..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0033-Fix-various-compile-warnings.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From c59684852ecd37d6f82363f2cf0e1de1f770aab7 Mon Sep 17 00:00:00 2001
-From: Mark Hatle <mark.hatle@kernel.crashing.org>
-Date: Fri, 17 Jul 2020 09:20:54 -0500
-Subject: [PATCH 33/40] Fix various compile warnings
-
-Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
----
- bfd/elf64-microblaze.c     |  9 +++++----
- 2 files changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/bfd/elf64-microblaze.c b/bfd/elf64-microblaze.c
-index b002b414d64..8308f1ebd09 100644
---- a/bfd/elf64-microblaze.c
-+++ b/bfd/elf64-microblaze.c
-@@ -692,7 +692,7 @@ microblaze_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
- /* Set the howto pointer for a RCE ELF reloc.  */
- 
- static bfd_boolean
--microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-+microblaze_elf_info_to_howto (bfd * abfd,
- 			      arelent * cache_ptr,
- 			      Elf_Internal_Rela * dst)
- {
-@@ -705,14 +705,14 @@ microblaze_elf_info_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
-   r_type = ELF64_R_TYPE (dst->r_info);
-   if (r_type >= R_MICROBLAZE_max)
-     {
--      (*_bfd_error_handler) (_("%pB: unrecognised MicroBlaze reloc number: %d"),
-+      _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
- 			     abfd, r_type);
-       bfd_set_error (bfd_error_bad_value);
-       return FALSE;
-     }
- 
-   cache_ptr->howto = microblaze_elf_howto_table [r_type];
-- return TRUE;
-+  return TRUE;
- }
- 
- /* Microblaze ELF local labels start with 'L.' or '$L', not '.L'.  */
-@@ -1560,7 +1560,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
- 			else
- 			  {
- 			    BFD_FAIL ();
--			    (*_bfd_error_handler)
-+			    _bfd_error_handler
- 			      (_("%pB: probably compiled without -fPIC?"),
- 			       input_bfd);
- 			    bfd_set_error (bfd_error_bad_value);
-@@ -2554,6 +2554,7 @@ microblaze_elf_check_relocs (bfd * abfd,
-           goto dogottls;
-         case R_MICROBLAZE_TLSLD:
-           tls_type |= (TLS_TLS | TLS_LD);
-+          /* Fall through. */
-         dogottls:
-           sec->has_tls_reloc = 1;
-           /* Fall through. */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch
deleted file mode 100644
index ff1c606c41..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Add-initial-port-of-linux-gdbserver.patch
+++ /dev/null
@@ -1,500 +0,0 @@
-From c5eee33cd39dbb9c44bdad2025a5c848139c55f2 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Mon, 23 Jan 2017 19:07:44 +0530
-Subject: [PATCH 34/40] Add initial port of linux gdbserver add
- gdb_proc_service_h to gdbserver microblaze-linux
-
-gdbserver needs to initialise the microblaze registers
-
-other archs use this step to run a *_arch_setup() to carry out all
-architecture specific setup - may need to add in future
-
- * add linux-ptrace.o to gdbserver configure
- * Update breakpoint opcode
- * fix segfault on connecting gdbserver
- * add microblaze_linux_memory_remove_breakpoint
- * add set_solib_svr4_fetch_link_map_offsets
- * add set_gdbarch_fetch_tls_load_module_address
- * Force reading of r0 as 0, prevent stores
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- gdb/configure.host                   |   3 +
- gdb/features/microblaze-linux.xml    |  12 ++
- gdb/gdbserver/Makefile.in            |   4 +
- gdb/gdbserver/configure.srv          |   8 ++
- gdb/gdbserver/linux-microblaze-low.c | 189 +++++++++++++++++++++++++++
- gdb/microblaze-linux-tdep.c          |  29 +++-
- gdb/microblaze-tdep.c                |  35 ++++-
- gdb/microblaze-tdep.h                |   4 +-
- gdb/regformats/reg-microblaze.dat    |  41 ++++++
- 9 files changed, 322 insertions(+), 3 deletions(-)
- create mode 100644 gdb/features/microblaze-linux.xml
- create mode 100644 gdb/gdbserver/linux-microblaze-low.c
- create mode 100644 gdb/regformats/reg-microblaze.dat
-
-diff --git a/gdb/configure.host b/gdb/configure.host
-index ce528237291..cf1a08e8b28 100644
---- a/gdb/configure.host
-+++ b/gdb/configure.host
-@@ -65,6 +65,7 @@ hppa*)			gdb_host_cpu=pa ;;
- i[34567]86*)		gdb_host_cpu=i386 ;;
- m68*)			gdb_host_cpu=m68k ;;
- mips*)			gdb_host_cpu=mips ;;
-+microblaze*)		gdb_host_cpu=microblaze ;;
- powerpc* | rs6000)	gdb_host_cpu=powerpc ;;
- sparcv9 | sparc64)	gdb_host_cpu=sparc ;;
- s390*)			gdb_host_cpu=s390 ;;
-@@ -133,6 +134,8 @@ mips*-*-netbsd* | mips*-*-knetbsd*-gnu)
- mips*-*-freebsd*)	gdb_host=fbsd ;;
- mips64*-*-openbsd*)	gdb_host=obsd64 ;;
- 
-+microblaze*-*linux*)	gdb_host=linux ;;
-+
- powerpc-*-aix* | rs6000-*-* | powerpc64-*-aix*)
- 			gdb_host=aix ;;
- powerpc*-*-freebsd*)	gdb_host=fbsd ;;
-diff --git a/gdb/features/microblaze-linux.xml b/gdb/features/microblaze-linux.xml
-new file mode 100644
-index 00000000000..8983e66eb3d
---- /dev/null
-+++ b/gdb/features/microblaze-linux.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <osabi>GNU/Linux</osabi>
-+  <xi:include href="microblaze-core.xml"/>
-+</target>
-diff --git a/gdb/gdbserver/Makefile.in b/gdb/gdbserver/Makefile.in
-index 16a9f2fd380..fb4762a22d5 100644
---- a/gdb/gdbserver/Makefile.in
-+++ b/gdb/gdbserver/Makefile.in
-@@ -172,6 +172,7 @@ SFILES = \
- 	$(srcdir)/linux-low.c \
- 	$(srcdir)/linux-m32r-low.c \
- 	$(srcdir)/linux-m68k-low.c \
-+	$(srcdir)/linux-microblaze-low.c \
- 	$(srcdir)/linux-mips-low.c \
- 	$(srcdir)/linux-nios2-low.c \
- 	$(srcdir)/linux-ppc-low.c \
-@@ -231,6 +232,7 @@ SFILES = \
- 	$(srcdir)/nat/linux-namespaces.c \
- 	$(srcdir)/nat/linux-osdata.c \
- 	$(srcdir)/nat/linux-personality.c \
-+	$(srcdir)/nat/microblaze-linux.c \
- 	$(srcdir)/nat/mips-linux-watch.c \
- 	$(srcdir)/nat/ppc-linux.c \
- 	$(srcdir)/nat/fork-inferior.c \
-@@ -657,6 +659,8 @@ gdbsupport/%.o: ../gdbsupport/%.c
- 
- %-generated.c: ../regformats/rs6000/%.dat | $(regdat_sh)
- 	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
-+microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
-+	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
- 
- #
- # Dependency tracking.
-diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
-index 1a4ab8e3361..e0d2b2fe04a 100644
---- a/gdb/gdbserver/configure.srv
-+++ b/gdb/gdbserver/configure.srv
-@@ -184,6 +184,14 @@ case "${target}" in
- 			srv_linux_usrregs=yes
- 			srv_linux_thread_db=yes
- 			;;
-+  microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
-+			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
-+			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
-+			srv_xmlfiles="microblaze-linux.xml"
-+			srv_linux_regsets=yes
-+			srv_linux_usrregs=yes
-+			srv_linux_thread_db=yes
-+			;;
-   powerpc*-*-linux*)	srv_regobj="powerpc-32l.o"
- 			srv_regobj="${srv_regobj} powerpc-altivec32l.o"
- 			srv_regobj="${srv_regobj} powerpc-vsx32l.o"
-diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
-new file mode 100644
-index 00000000000..cba5d6fc585
---- /dev/null
-+++ b/gdb/gdbserver/linux-microblaze-low.c
-@@ -0,0 +1,189 @@
-+/* GNU/Linux/Microblaze specific low level interface, for the remote server for
-+   GDB.
-+   Copyright (C) 1995-2013 Free Software Foundation, Inc.
-+
-+   This file is part of GDB.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
-+
-+#include "server.h"
-+#include "linux-low.h"
-+
-+#include <asm/ptrace.h>
-+#include <sys/procfs.h>
-+#include <sys/ptrace.h>
-+
-+#include "gdb_proc_service.h"
-+
-+static int microblaze_regmap[] =
-+ {PT_GPR(0),     PT_GPR(1),     PT_GPR(2),     PT_GPR(3),
-+  PT_GPR(4),     PT_GPR(5),     PT_GPR(6),     PT_GPR(7),
-+  PT_GPR(8),     PT_GPR(9),     PT_GPR(10),    PT_GPR(11),
-+  PT_GPR(12),    PT_GPR(13),    PT_GPR(14),    PT_GPR(15),
-+  PT_GPR(16),    PT_GPR(17),    PT_GPR(18),    PT_GPR(19),
-+  PT_GPR(20),    PT_GPR(21),    PT_GPR(22),    PT_GPR(23),
-+  PT_GPR(24),    PT_GPR(25),    PT_GPR(26),    PT_GPR(27),
-+  PT_GPR(28),    PT_GPR(29),    PT_GPR(30),    PT_GPR(31),
-+  PT_PC,         PT_MSR,        PT_EAR,        PT_ESR,
-+  PT_FSR
-+  };
-+
-+#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
-+
-+/* Defined in auto-generated file microblaze-linux.c.  */
-+void init_registers_microblaze (void);
-+
-+static int
-+microblaze_cannot_store_register (int regno)
-+{
-+  if (microblaze_regmap[regno] == -1 || regno == 0)
-+    return 1;
-+
-+  return 0;
-+}
-+
-+static int
-+microblaze_cannot_fetch_register (int regno)
-+{
-+  return 0;
-+}
-+
-+static CORE_ADDR
-+microblaze_get_pc (struct regcache *regcache)
-+{
-+  unsigned long pc;
-+
-+  collect_register_by_name (regcache, "pc", &pc);
-+  return (CORE_ADDR) pc;
-+}
-+
-+static void
-+microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
-+{
-+  unsigned long newpc = pc;
-+
-+  supply_register_by_name (regcache, "pc", &newpc);
-+}
-+
-+/* dbtrap insn */
-+/* brki r16, 0x18; */
-+static const unsigned long microblaze_breakpoint = 0xba0c0018;
-+#define microblaze_breakpoint_len 4
-+
-+static int
-+microblaze_breakpoint_at (CORE_ADDR where)
-+{
-+  unsigned long insn;
-+
-+  (*the_target->read_memory) (where, (unsigned char *) &insn, 4);
-+  if (insn == microblaze_breakpoint)
-+    return 1;
-+  /* If necessary, recognize more trap instructions here.  GDB only uses the
-+     one.  */
-+  return 0;
-+}
-+
-+static CORE_ADDR
-+microblaze_reinsert_addr (struct regcache *regcache)
-+{
-+  unsigned long pc;
-+  collect_register_by_name (regcache, "r15", &pc);
-+  return pc;
-+}
-+
-+#ifdef HAVE_PTRACE_GETREGS
-+
-+static void
-+microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
-+{
-+  int size = register_size (regno);
-+
-+  memset (buf, 0, sizeof (long));
-+
-+  if (size < sizeof (long))
-+    collect_register (regcache, regno, buf + sizeof (long) - size);
-+  else
-+    collect_register (regcache, regno, buf);
-+}
-+
-+static void
-+microblaze_supply_ptrace_register (struct regcache *regcache,
-+			    int regno, const char *buf)
-+{
-+  int size = register_size (regno);
-+
-+  if (regno == 0) {
-+    unsigned long regbuf_0 = 0;
-+    /* clobbering r0 so that it is always 0 as enforced by hardware */
-+    supply_register (regcache, regno, (const char*)&regbuf_0);
-+  } else {
-+      if (size < sizeof (long))
-+        supply_register (regcache, regno, buf + sizeof (long) - size);
-+      else
-+        supply_register (regcache, regno, buf);
-+  }
-+}
-+
-+/* Provide only a fill function for the general register set.  ps_lgetregs
-+   will use this for NPTL support.  */
-+
-+static void microblaze_fill_gregset (struct regcache *regcache, void *buf)
-+{
-+  int i;
-+
-+  for (i = 0; i < 32; i++)
-+    microblaze_collect_ptrace_register (regcache, i, (char *) buf + microblaze_regmap[i]);
-+}
-+
-+static void
-+microblaze_store_gregset (struct regcache *regcache, const void *buf)
-+{
-+  int i;
-+
-+  for (i = 0; i < 32; i++)
-+    supply_register (regcache, i, (char *) buf + microblaze_regmap[i]);
-+}
-+
-+#endif /* HAVE_PTRACE_GETREGS */
-+
-+struct regset_info target_regsets[] = {
-+#ifdef HAVE_PTRACE_GETREGS
-+  { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
-+  { 0, 0, 0, -1, -1, NULL, NULL },
-+#endif /* HAVE_PTRACE_GETREGS */
-+  { 0, 0, 0, -1, -1, NULL, NULL }
-+};
-+
-+struct linux_target_ops the_low_target = {
-+  init_registers_microblaze,
-+  microblaze_num_regs,
-+  microblaze_regmap,
-+  NULL,
-+  microblaze_cannot_fetch_register,
-+  microblaze_cannot_store_register,
-+  NULL, /* fetch_register */
-+  microblaze_get_pc,
-+  microblaze_set_pc,
-+  (const unsigned char *) &microblaze_breakpoint,
-+  microblaze_breakpoint_len,
-+  microblaze_reinsert_addr,
-+  0,
-+  microblaze_breakpoint_at,
-+  NULL,
-+  NULL,
-+  NULL,
-+  NULL,
-+  microblaze_collect_ptrace_register,
-+  microblaze_supply_ptrace_register,
-+};
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index 3bb9b5682ac..42c219d32f3 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -37,6 +37,22 @@
- #include "tramp-frame.h"
- #include "linux-tdep.h"
- 
-+static int microblaze_debug_flag = 0;
-+
-+static void
-+microblaze_debug (const char *fmt, ...)
-+{
-+  if (microblaze_debug_flag)
-+    {
-+       va_list args;
-+
-+       va_start (args, fmt);
-+       printf_unfiltered ("MICROBLAZE LINUX: ");
-+       vprintf_unfiltered (fmt, args);
-+       va_end (args);
-+    }
-+}
-+
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
- 					   struct bp_target_info *bp_tgt)
-@@ -50,13 +66,20 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-   /* Determine appropriate breakpoint contents and size for this address.  */
-   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
- 
-+  /* Make sure we see the memory breakpoints.  */
-+  scoped_restore restore_memory
-+    = make_scoped_restore_show_memory_breakpoints (1);
-+
-   val = target_read_memory (addr, old_contents, bplen);
- 
-   /* If our breakpoint is no longer at the address, this means that the
-      program modified the code on us, so it is wrong to put back the
-      old value.  */
-   if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
--    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+  {
-+      val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+      microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
-+  }
- 
-   return val;
- }
-@@ -129,6 +152,10 @@ microblaze_linux_init_abi (struct gdbarch_info info,
-   /* Trampolines.  */
-   tramp_frame_prepend_unwinder (gdbarch,
- 				&microblaze_linux_sighandler_tramp_frame);
-+
-+  /* Enable TLS support.  */
-+  set_gdbarch_fetch_tls_load_module_address (gdbarch,
-+                                             svr4_fetch_objfile_link_map);
- }
- 
- void
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 17871229c80..0168e4881ed 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -137,7 +137,38 @@ microblaze_fetch_instruction (CORE_ADDR pc)
- constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
- 
- typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
--
-+static int
-+microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
-+				    struct bp_target_info *bp_tgt)
-+{
-+  CORE_ADDR addr = bp_tgt->placed_address;
-+  const unsigned char *bp;
-+  int val;
-+  int bplen;
-+  gdb_byte old_contents[BREAKPOINT_MAX];
-+
-+  /* Determine appropriate breakpoint contents and size for this address.  */
-+  bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
-+  if (bp == NULL)
-+    error (_("Software breakpoints not implemented for this target."));
-+
-+  /* Make sure we see the memory breakpoints.  */
-+  scoped_restore restore_memory
-+    = make_scoped_restore_show_memory_breakpoints (1);
-+
-+  val = target_read_memory (addr, old_contents, bplen);
-+
-+  /* If our breakpoint is no longer at the address, this means that the
-+     program modified the code on us, so it is wrong to put back the
-+     old value.  */
-+  if (val == 0 && memcmp (bp, old_contents, bplen) == 0)
-+  {
-+    val = target_write_raw_memory (addr, bp_tgt->shadow_contents, bplen);
-+    microblaze_debug ("microblaze_linux_memory_remove_breakpoint writing back to memory at addr 0x%lx\n", addr);
-+  }
-+
-+  return val;
-+}
- 
- /* Allocate and initialize a frame cache.  */
- 
-@@ -731,6 +762,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- 				       microblaze_breakpoint::kind_from_pc);
-   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
- 				       microblaze_breakpoint::bp_from_kind);
-+  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
- 
-   set_gdbarch_frame_args_skip (gdbarch, 8);
- 
-@@ -770,4 +802,5 @@ When non-zero, microblaze specific debugging is enabled."),
- 			     NULL,
- 			     &setdebuglist, &showdebuglist);
- 
-+
- }
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 4fbdf9933f0..db0772643dc 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -117,6 +117,8 @@ struct microblaze_frame_cache
- 
- /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
-    Only used for native debugging.  */
--#define MICROBLAZE_BREAKPOINT {0xb9, 0xcc, 0x00, 0x60}
-+#define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
-+#define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
-+
- 
- #endif /* microblaze-tdep.h */
-diff --git a/gdb/regformats/reg-microblaze.dat b/gdb/regformats/reg-microblaze.dat
-new file mode 100644
-index 00000000000..bd8a4384424
---- /dev/null
-+++ b/gdb/regformats/reg-microblaze.dat
-@@ -0,0 +1,41 @@
-+name:microblaze
-+expedite:r1,pc
-+32:r0
-+32:r1
-+32:r2
-+32:r3
-+32:r4
-+32:r5
-+32:r6
-+32:r7
-+32:r8
-+32:r9
-+32:r10
-+32:r11
-+32:r12
-+32:r13
-+32:r14
-+32:r15
-+32:r16
-+32:r17
-+32:r18
-+32:r19
-+32:r20
-+32:r21
-+32:r22
-+32:r23
-+32:r24
-+32:r25
-+32:r26
-+32:r27
-+32:r28
-+32:r29
-+32:r30
-+32:r31
-+32:pc
-+32:msr
-+32:ear
-+32:esr
-+32:fsr
-+32:slr
-+32:shr
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Initial-port-of-core-reading-support-Added-support-f.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Initial-port-of-core-reading-support-Added-support-f.patch
new file mode 100644
index 0000000000..d32b501cc0
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0034-Initial-port-of-core-reading-support-Added-support-f.patch
@@ -0,0 +1,385 @@
+From e6929fae6b3850eb925ef147bf0d0b09ca80cdf8 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Tue, 24 Jan 2017 14:55:56 +0530
+Subject: [PATCH 34/52] Initial port of core reading support Added support for
+ reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
+ information for rebuilding ".reg" sections of core dumps at run time.
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ bfd/elf32-microblaze.c      | 84 ++++++++++++++++++++++++++++++++++
+ gdb/configure.tgt           |  2 +-
+ gdb/microblaze-linux-tdep.c | 57 +++++++++++++++++++++++
+ gdb/microblaze-tdep.c       | 90 +++++++++++++++++++++++++++++++++++++
+ gdb/microblaze-tdep.h       | 27 +++++++++++
+ 5 files changed, 259 insertions(+), 1 deletion(-)
+
+Index: gdb-9.2/bfd/elf32-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf32-microblaze.c
++++ gdb-9.2/bfd/elf32-microblaze.c
+@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd
+   return _bfd_elf_is_local_label_name (abfd, name);
+ }
+ 
++/* Support for core dump NOTE sections.  */
++static bfd_boolean
++microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
++{
++  int offset;
++  unsigned int size;
++
++  switch (note->descsz)
++    {
++      default:
++        return FALSE;
++
++      case 228:         /* Linux/MicroBlaze */
++        /* pr_cursig */
++        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
++
++        /* pr_pid */
++        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
++
++        /* pr_reg */
++        offset = 72;
++        size = 50 * 4;
++
++        break;
++    }
++
++  /* Make a ".reg/999" section.  */
++  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
++                                          size, note->descpos + offset);
++}
++
++static bfd_boolean
++microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
++{
++  switch (note->descsz)
++    {
++      default:
++        return FALSE;
++
++      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
++        elf_tdata (abfd)->core->program
++         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
++        elf_tdata (abfd)->core->command
++         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
++    }
++
++  /* Note that for some reason, a spurious space is tacked
++     onto the end of the args in some (at least one anyway)
++     implementations, so strip it off if it exists.  */
++
++  {
++    char *command = elf_tdata (abfd)->core->command;
++    int n = strlen (command);
++
++    if (0 < n && command[n - 1] == ' ')
++      command[n - 1] = '\0';
++  }
++
++  return TRUE;
++}
++
++/* The microblaze linker (like many others) needs to keep track of
++   the number of relocs that it decides to copy as dynamic relocs in
++   check_relocs for each symbol. This is so that it can later discard
++   them if they are found to be unnecessary.  We store the information
++   in a field extending the regular ELF linker hash table.  */
++
++struct elf32_mb_dyn_relocs
++{
++  struct elf32_mb_dyn_relocs *next;
++
++  /* The input section of the reloc.  */
++  asection *sec;
++
++  /* Total number of relocs copied for the input section.  */
++  bfd_size_type count;
++
++  /* Number of pc-relative relocs copied for the input section.  */
++  bfd_size_type pc_count;
++};
++
+ /* ELF linker hash entry.  */
+ 
+ struct elf32_mb_link_hash_entry
+@@ -3675,4 +3756,7 @@ microblaze_elf_add_symbol_hook (bfd *abf
+ #define elf_backend_size_dynamic_sections	microblaze_elf_size_dynamic_sections
+ #define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
+ 
++#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
++#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
++
+ #include "elf32-target.h"
+Index: gdb-9.2/gdb/configure.tgt
+===================================================================
+--- gdb-9.2.orig/gdb/configure.tgt
++++ gdb-9.2/gdb/configure.tgt
+@@ -400,7 +400,7 @@ mep-*-*)
+ 
+ microblaze*-linux-*|microblaze*-*-linux*)
+ 	# Target: Xilinx MicroBlaze running Linux
+-	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
++	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
+ 			symfile-mem.o linux-tdep.o"
+ 	gdb_sim=../sim/microblaze/libsim.a
+ 	;;
+Index: gdb-9.2/gdb/microblaze-linux-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-linux-tdep.c
++++ gdb-9.2/gdb/microblaze-linux-tdep.c
+@@ -135,11 +135,54 @@ static struct tramp_frame microblaze_lin
+   microblaze_linux_sighandler_cache_init
+ };
+ 
++const struct microblaze_gregset microblaze_linux_core_gregset;
++
++static void
++microblaze_linux_supply_core_gregset (const struct regset *regset,
++                                   struct regcache *regcache,
++                                   int regnum, const void *gregs, size_t len)
++{
++  microblaze_supply_gregset (&microblaze_linux_core_gregset, regcache,
++                             regnum, gregs);
++}
++
++static void
++microblaze_linux_collect_core_gregset (const struct regset *regset,
++                                    const struct regcache *regcache,
++                                    int regnum, void *gregs, size_t len)
++{
++  microblaze_collect_gregset (&microblaze_linux_core_gregset, regcache,
++                              regnum, gregs);
++}
++
++static void
++microblaze_linux_supply_core_fpregset (const struct regset *regset,
++                                    struct regcache *regcache,
++                                    int regnum, const void *fpregs, size_t len)
++{
++  /* FIXME.  */
++  microblaze_supply_fpregset (regcache, regnum, fpregs);
++}
++
++static void
++microblaze_linux_collect_core_fpregset (const struct regset *regset,
++                                     const struct regcache *regcache,
++                                     int regnum, void *fpregs, size_t len)
++{
++  /* FIXME.  */
++  microblaze_collect_fpregset (regcache, regnum, fpregs);
++}
+ 
+ static void
+ microblaze_linux_init_abi (struct gdbarch_info info,
+ 			   struct gdbarch *gdbarch)
+ {
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++  tdep->gregset = regset_alloc (gdbarch, microblaze_linux_supply_core_gregset,
++                                microblaze_linux_collect_core_gregset);
++  tdep->sizeof_gregset = 200;
++
+   linux_init_abi (info, gdbarch);
+ 
+   set_gdbarch_memory_remove_breakpoint (gdbarch,
+@@ -153,6 +196,20 @@ microblaze_linux_init_abi (struct gdbarc
+   tramp_frame_prepend_unwinder (gdbarch,
+ 				&microblaze_linux_sighandler_tramp_frame);
+ 
++  /* BFD target for core files.  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++  else
++    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++
++
++  /* Shared library handling.  */
++  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
++  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
++
++  set_gdbarch_regset_from_core_section (gdbarch,
++					microblaze_regset_from_core_section);
++
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+Index: gdb-9.2/gdb/microblaze-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.c
++++ gdb-9.2/gdb/microblaze-tdep.c
+@@ -137,6 +137,14 @@ microblaze_fetch_instruction (CORE_ADDR
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
++static CORE_ADDR
++microblaze_store_arguments (struct regcache *regcache, int nargs,
++			    struct value **args, CORE_ADDR sp,
++			    int struct_return, CORE_ADDR struct_addr)
++{
++  error (_("store_arguments not implemented"));
++  return sp;
++}
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ 				    struct bp_target_info *bp_tgt)
+@@ -541,6 +549,12 @@ microblaze_frame_base_address (struct fr
+   return cache->base;
+ }
+ 
++static const struct frame_unwind *
++microblaze_frame_sniffer (struct frame_info *next_frame)
++{
++  return &microblaze_frame_unwind;
++}
++
+ static const struct frame_base microblaze_frame_base =
+ {
+   &microblaze_frame_unwind,
+@@ -677,6 +691,71 @@ microblaze_register_g_packet_guesses (st
+                                   tdesc_microblaze_with_stack_protect);
+ }
+ 
++void
++microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++                        struct regcache *regcache,
++                        int regnum, const void *gregs)
++{
++  unsigned int *regs = gregs;
++  if (regnum >= 0)
++    regcache_raw_supply (regcache, regnum, regs + regnum);
++
++  if (regnum == -1) {
++    int i;
++
++    for (i = 0; i < 50; i++) {
++      regcache_raw_supply (regcache, i, regs + i);
++    }
++  }
++}
++
++
++void
++microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++                         const struct regcache *regcache,
++                         int regnum, void *gregs)
++{
++   /* FIXME.  */
++}
++
++void
++microblaze_supply_fpregset (struct regcache *regcache,
++                         int regnum, const void *fpregs)
++{
++   /* FIXME.  */
++}
++
++void
++microblaze_collect_fpregset (const struct regcache *regcache,
++                          int regnum, void *fpregs)
++{
++   /* FIXME.  */
++}
++
++
++/* Return the appropriate register set for the core section identified
++   by SECT_NAME and SECT_SIZE.  */
++
++const struct regset *
++microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++                                     const char *sect_name, size_t sect_size)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++
++  microblaze_debug ("microblaze_regset_from_core_section, sect_name = %s\n", sect_name);
++
++  if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
++    return tdep->gregset;
++
++  if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
++    return tdep->fpregset;
++
++  microblaze_debug ("microblaze_regset_from_core_section returning null :-( \n");
++  return NULL;
++}
++
++
++
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
+@@ -733,6 +812,10 @@ microblaze_gdbarch_init (struct gdbarch_
+   tdep = XCNEW (struct gdbarch_tdep);
+   gdbarch = gdbarch_alloc (&info, tdep);
+ 
++  tdep->gregset = NULL;
++  tdep->sizeof_gregset = 0;
++  tdep->fpregset = NULL;
++  tdep->sizeof_fpregset = 0;
+   set_gdbarch_long_double_bit (gdbarch, 128);
+ 
+   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
+@@ -781,6 +864,13 @@ microblaze_gdbarch_init (struct gdbarch_
+   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
+   if (tdesc_data != NULL)
+     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
++  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
++
++  /* If we have register sets, enable the generic core file support.  */
++  if (tdep->gregset) {
++      set_gdbarch_regset_from_core_section (gdbarch,
++                                          microblaze_regset_from_core_section);
++  }
+ 
+   return gdbarch;
+ }
+Index: gdb-9.2/gdb/microblaze-tdep.h
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.h
++++ gdb-9.2/gdb/microblaze-tdep.h
+@@ -22,8 +22,22 @@
+ 
+ 
+ /* Microblaze architecture-specific information.  */
++struct microblaze_gregset
++{
++   unsigned int gregs[32];
++   unsigned int fpregs[32];
++   unsigned int pregs[16];
++};
++
+ struct gdbarch_tdep
+ {
++  int dummy;		// declare something.
++
++  /* Register sets.  */
++  struct regset *gregset;
++  size_t sizeof_gregset;
++  struct regset *fpregset;
++  size_t sizeof_fpregset;
+ };
+ 
+ /* Register numbers.  */
+@@ -120,5 +134,18 @@ struct microblaze_frame_cache
+ #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
+ #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
+ 
++extern void microblaze_supply_gregset (const struct microblaze_gregset *gregset,
++                                    struct regcache *regcache,
++                                    int regnum, const void *gregs);
++extern void microblaze_collect_gregset (const struct microblaze_gregset *gregset,
++                                     const struct regcache *regcache,
++                                     int regnum, void *gregs);
++extern void microblaze_supply_fpregset (struct regcache *regcache,
++                                     int regnum, const void *fpregs);
++extern void microblaze_collect_fpregset (const struct regcache *regcache,
++                                      int regnum, void *fpregs);
++
++extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
++                                     const char *sect_name, size_t sect_size);
+ 
+ #endif /* microblaze-tdep.h */
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Fix-debug-message-when-register-is-unavailable.patch
new file mode 100644
index 0000000000..9983f17f3d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Fix-debug-message-when-register-is-unavailable.patch
@@ -0,0 +1,37 @@
+From c6da374fbce33b35b060a07ee446aaf1803b1e1d Mon Sep 17 00:00:00 2001
+From: Nathan Rossi <nathan.rossi@petalogix.com>
+Date: Tue, 8 May 2012 18:11:17 +1000
+Subject: [PATCH 35/52] Fix debug message when register is unavailable
+
+Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
+---
+ gdb/frame.c | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+Index: gdb-9.2/gdb/frame.c
+===================================================================
+--- gdb-9.2.orig/gdb/frame.c
++++ gdb-9.2/gdb/frame.c
+@@ -1255,12 +1255,19 @@ frame_unwind_register_value (frame_info
+ 	  else
+ 	    {
+ 	      int i;
+-	      const gdb_byte *buf = value_contents (value);
++	      const gdb_byte *buf = NULL;
++	      if (value_entirely_available(value)) {
++	        buf = value_contents (value);
++	      }
+ 
+ 	      fprintf_unfiltered (gdb_stdlog, " bytes=");
+ 	      fprintf_unfiltered (gdb_stdlog, "[");
+-	      for (i = 0; i < register_size (gdbarch, regnum); i++)
+-		fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++	      if (buf != NULL) {
++	        for (i = 0; i < register_size (gdbarch, regnum); i++)
++		  fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
++	      } else {
++	        fprintf_unfiltered (gdb_stdlog, "unavailable");
++	      }
+ 	      fprintf_unfiltered (gdb_stdlog, "]");
+ 	    }
+ 	}
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch
deleted file mode 100644
index 171a0bf40f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0035-Initial-port-of-core-reading-support.patch
+++ /dev/null
@@ -1,298 +0,0 @@
-From f8cbcd1ef78f6ce9ae8d3382bf2bb0d1e770d201 Mon Sep 17 00:00:00 2001
-From: Mahesh Bodapati <mbodapat@xilinx.com>
-Date: Tue, 24 Jan 2017 14:55:56 +0530
-Subject: [PATCH 35/40] Initial port of core reading support Added support for
- reading notes in linux core dumps Support for reading of PRSTATUS and PSINFO
- information for rebuilding ".reg" sections of core dumps at run time.
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- bfd/elf32-microblaze.c      | 84 +++++++++++++++++++++++++++++++++++++
- gdb/configure.tgt           |  2 +-
- gdb/microblaze-linux-tdep.c | 17 +++++++-
- gdb/microblaze-tdep.c       | 48 +++++++++++++++++++++
- gdb/microblaze-tdep.h       | 27 ++++++++++++
- 5 files changed, 176 insertions(+), 2 deletions(-)
-
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index 04816a4a187..cb7a98d307e 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -767,6 +767,87 @@ microblaze_elf_is_local_label_name (bfd *abfd, const char *name)
-   return _bfd_elf_is_local_label_name (abfd, name);
- }
- 
-+/* Support for core dump NOTE sections.  */
-+static bfd_boolean
-+microblaze_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
-+{
-+  int offset;
-+  unsigned int size;
-+
-+  switch (note->descsz)
-+    {
-+      default:
-+        return FALSE;
-+
-+      case 228:         /* Linux/MicroBlaze */
-+        /* pr_cursig */
-+        elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
-+
-+        /* pr_pid */
-+        elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
-+
-+        /* pr_reg */
-+        offset = 72;
-+        size = 50 * 4;
-+
-+        break;
-+    }
-+
-+  /* Make a ".reg/999" section.  */
-+  return _bfd_elfcore_make_pseudosection (abfd, ".reg",
-+                                          size, note->descpos + offset);
-+}
-+
-+static bfd_boolean
-+microblaze_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
-+{
-+  switch (note->descsz)
-+    {
-+      default:
-+        return FALSE;
-+
-+      case 128:         /* Linux/MicroBlaze elf_prpsinfo */
-+        elf_tdata (abfd)->core->program
-+         = _bfd_elfcore_strndup (abfd, note->descdata + 32, 16);
-+        elf_tdata (abfd)->core->command
-+         = _bfd_elfcore_strndup (abfd, note->descdata + 48, 80);
-+    }
-+
-+  /* Note that for some reason, a spurious space is tacked
-+     onto the end of the args in some (at least one anyway)
-+     implementations, so strip it off if it exists.  */
-+
-+  {
-+    char *command = elf_tdata (abfd)->core->command;
-+    int n = strlen (command);
-+
-+    if (0 < n && command[n - 1] == ' ')
-+      command[n - 1] = '\0';
-+  }
-+
-+  return TRUE;
-+}
-+
-+/* The microblaze linker (like many others) needs to keep track of
-+   the number of relocs that it decides to copy as dynamic relocs in
-+   check_relocs for each symbol. This is so that it can later discard
-+   them if they are found to be unnecessary.  We store the information
-+   in a field extending the regular ELF linker hash table.  */
-+
-+struct elf32_mb_dyn_relocs
-+{
-+  struct elf32_mb_dyn_relocs *next;
-+
-+  /* The input section of the reloc.  */
-+  asection *sec;
-+
-+  /* Total number of relocs copied for the input section.  */
-+  bfd_size_type count;
-+
-+  /* Number of pc-relative relocs copied for the input section.  */
-+  bfd_size_type pc_count;
-+};
-+
- /* ELF linker hash entry.  */
- 
- struct elf32_mb_link_hash_entry
-@@ -3673,4 +3754,7 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
- #define elf_backend_size_dynamic_sections	microblaze_elf_size_dynamic_sections
- #define elf_backend_add_symbol_hook		microblaze_elf_add_symbol_hook
- 
-+#define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
-+#define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
-+
- #include "elf32-target.h"
-diff --git a/gdb/configure.tgt b/gdb/configure.tgt
-index caa42be1c01..f0386568460 100644
---- a/gdb/configure.tgt
-+++ b/gdb/configure.tgt
-@@ -400,7 +400,7 @@ mep-*-*)
- 
- microblaze*-linux-*|microblaze*-*-linux*)
- 	# Target: Xilinx MicroBlaze running Linux
--	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o \
-+	gdb_target_obs="microblaze-tdep.o microblaze-linux-tdep.o solib-svr4.o glibc-tdep.o \
- 			symfile-mem.o linux-tdep.o"
- 	gdb_sim=../sim/microblaze/libsim.a
- 	;;
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index 42c219d32f3..0afb6efeba3 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -36,6 +36,7 @@
- #include "frame-unwind.h"
- #include "tramp-frame.h"
- #include "linux-tdep.h"
-+#include "glibc-tdep.h"
- 
- static int microblaze_debug_flag = 0;
- 
-@@ -135,11 +136,14 @@ static struct tramp_frame microblaze_linux_sighandler_tramp_frame =
-   microblaze_linux_sighandler_cache_init
- };
- 
--
- static void
- microblaze_linux_init_abi (struct gdbarch_info info,
- 			   struct gdbarch *gdbarch)
- {
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+
-+  tdep->sizeof_gregset = 200;
-+
-   linux_init_abi (info, gdbarch);
- 
-   set_gdbarch_memory_remove_breakpoint (gdbarch,
-@@ -153,6 +157,17 @@ microblaze_linux_init_abi (struct gdbarch_info info,
-   tramp_frame_prepend_unwinder (gdbarch,
- 				&microblaze_linux_sighandler_tramp_frame);
- 
-+  /* BFD target for core files.  */
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+  else
-+    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+
-+
-+  /* Shared library handling.  */
-+  set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
-+  set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
-+
-   /* Enable TLS support.  */
-   set_gdbarch_fetch_tls_load_module_address (gdbarch,
-                                              svr4_fetch_objfile_link_map);
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 0168e4881ed..98944f38d2a 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -677,6 +677,43 @@ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
-                                   tdesc_microblaze_with_stack_protect);
- }
- 
-+void
-+microblaze_supply_gregset (const struct regset *regset,
-+                        struct regcache *regcache,
-+                        int regnum, const void *gregs)
-+{
-+  const unsigned int *regs = (const unsigned int *)gregs;
-+  if (regnum >= 0)
-+    regcache->raw_supply (regnum, regs + regnum);
-+
-+  if (regnum == -1) {
-+    int i;
-+
-+    for (i = 0; i < 50; i++) {
-+      regcache->raw_supply (i, regs + i);
-+    }
-+  }
-+}
-+
-+
-+/* Return the appropriate register set for the core section identified
-+   by SECT_NAME and SECT_SIZE.  */
-+
-+static void
-+microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
-+                                     iterate_over_regset_sections_cb *cb,
-+                                     void *cb_data,
-+                                     const struct regcache *regcache)
-+{
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+
-+  cb(".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL, cb_data);
-+
-+  cb(".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data);
-+}
-+
-+
-+
- static struct gdbarch *
- microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- {
-@@ -733,6 +770,10 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   tdep = XCNEW (struct gdbarch_tdep);
-   gdbarch = gdbarch_alloc (&info, tdep);
- 
-+  tdep->gregset = NULL;
-+  tdep->sizeof_gregset = 0;
-+  tdep->fpregset = NULL;
-+  tdep->sizeof_fpregset = 0;
-   set_gdbarch_long_double_bit (gdbarch, 128);
- 
-   set_gdbarch_num_regs (gdbarch, MICROBLAZE_NUM_REGS);
-@@ -781,6 +822,13 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer);
-   if (tdesc_data != NULL)
-     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
-+  //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
-+
-+  /* If we have register sets, enable the generic core file support.  */
-+  if (tdep->gregset) {
-+    set_gdbarch_iterate_over_regset_sections (gdbarch,
-+                                          microblaze_iterate_over_regset_sections);
-+  }
- 
-   return gdbarch;
- }
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index db0772643dc..8f41ba19351 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -22,8 +22,22 @@
- 
- 
- /* Microblaze architecture-specific information.  */
-+struct microblaze_gregset
-+{
-+   unsigned int gregs[32];
-+   unsigned int fpregs[32];
-+   unsigned int pregs[16];
-+};
-+
- struct gdbarch_tdep
- {
-+  int dummy;		// declare something.
-+
-+  /* Register sets.  */
-+  struct regset *gregset;
-+  size_t sizeof_gregset;
-+  struct regset *fpregset;
-+  size_t sizeof_fpregset;
- };
- 
- /* Register numbers.  */
-@@ -120,5 +134,18 @@ struct microblaze_frame_cache
- #define MICROBLAZE_BREAKPOINT {0xba, 0x0c, 0x00, 0x18}
- #define MICROBLAZE_BREAKPOINT_LE {0x18, 0x00, 0x0c, 0xba}
- 
-+extern void microblaze_supply_gregset (const struct regset *regset,
-+                                    struct regcache *regcache,
-+                                    int regnum, const void *gregs);
-+extern void microblaze_collect_gregset (const struct regset *regset,
-+                                     const struct regcache *regcache,
-+                                     int regnum, void *gregs);
-+extern void microblaze_supply_fpregset (struct regcache *regcache,
-+                                     int regnum, const void *fpregs);
-+extern void microblaze_collect_fpregset (const struct regcache *regcache,
-+                                      int regnum, void *fpregs);
-+
-+extern const struct regset * microblaze_regset_from_core_section (struct gdbarch *gdbarch,
-+                                     const char *sect_name, size_t sect_size);
- 
- #endif /* microblaze-tdep.h */
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch
deleted file mode 100644
index f0c182d330..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-Fix-debug-message-when-register-is-unavailable.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 41fd9d3645d610ff65171e9a44427711232cb4b8 Mon Sep 17 00:00:00 2001
-From: Nathan Rossi <nathan.rossi@petalogix.com>
-Date: Tue, 8 May 2012 18:11:17 +1000
-Subject: [PATCH 36/40] Fix debug message when register is unavailable
-
-Signed-off-by: Nathan Rossi <nathan.rossi@petalogix.com>
----
- gdb/frame.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
-diff --git a/gdb/frame.c b/gdb/frame.c
-index c746a6a231e..571722c7351 100644
---- a/gdb/frame.c
-+++ b/gdb/frame.c
-@@ -1255,12 +1255,19 @@ frame_unwind_register_value (frame_info *next_frame, int regnum)
- 	  else
- 	    {
- 	      int i;
--	      const gdb_byte *buf = value_contents (value);
-+	      const gdb_byte *buf = NULL;
-+	      if (value_entirely_available(value)) {
-+	        buf = value_contents (value);
-+	      }
- 
- 	      fprintf_unfiltered (gdb_stdlog, " bytes=");
- 	      fprintf_unfiltered (gdb_stdlog, "[");
--	      for (i = 0; i < register_size (gdbarch, regnum); i++)
--		fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
-+	      if (buf != NULL) {
-+	        for (i = 0; i < register_size (gdbarch, regnum); i++)
-+		  fprintf_unfiltered (gdb_stdlog, "%02x", buf[i]);
-+	      } else {
-+	        fprintf_unfiltered (gdb_stdlog, "unavailable");
-+	      }
- 	      fprintf_unfiltered (gdb_stdlog, "]");
- 	    }
- 	}
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-revert-master-rebase-changes-to-gdbserver.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-revert-master-rebase-changes-to-gdbserver.patch
new file mode 100644
index 0000000000..cca0c7af5e
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0036-revert-master-rebase-changes-to-gdbserver.patch
@@ -0,0 +1,28 @@
+From 097961b044891887fec49824edfc15754e5faf10 Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 22 Jul 2013 11:16:05 +1000
+Subject: [PATCH 36/52] revert master-rebase changes to gdbserver
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/gdbserver/configure.srv | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+Index: gdb-9.2/gdb/gdbserver/configure.srv
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/configure.srv
++++ gdb-9.2/gdb/gdbserver/configure.srv
+@@ -184,6 +184,13 @@ case "${target}" in
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+ 			;;
++  microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
++			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
++			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++			srv_linux_regsets=yes
++			srv_linux_usrregs=yes
++			srv_linux_thread_db=yes
++			;;
+   powerpc*-*-linux*)	srv_regobj="powerpc-32l.o"
+ 			srv_regobj="${srv_regobj} powerpc-altivec32l.o"
+ 			srv_regobj="${srv_regobj} powerpc-vsx32l.o"
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
deleted file mode 100644
index 1e0bffbe27..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From 7b22823ae82445f52384e6c0bd85431294868eb7 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@xilinx.com>
-Date: Mon, 16 Dec 2013 16:37:32 +1000
-Subject: [PATCH 37/40] microblaze: Add build_gdbserver=yes to top level
- configure.tgt
-
-For Microblaze linux toolchains, set the build_gdbserver=yes
-to allow driving gdbserver configuration from the upper level
-
-This patch has been absorbed into the original patch to add
-linux gdbserver support for Microblaze.
-
-Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
----
- gdb/configure.tgt | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/gdb/configure.tgt b/gdb/configure.tgt
-index f0386568460..ae238c17cd5 100644
---- a/gdb/configure.tgt
-+++ b/gdb/configure.tgt
-@@ -408,6 +408,7 @@ microblaze*-*-*)
- 	# Target: Xilinx MicroBlaze running standalone
- 	gdb_target_obs="microblaze-tdep.o"
- 	gdb_sim=../sim/microblaze/libsim.a
-+	build_gdbserver=yes
- 	;;
- 
- mips*-*-linux*)
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
new file mode 100644
index 0000000000..f6c3a0602c
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0037-revert-master-rebase-changes-to-gdbserver-previous-c.patch
@@ -0,0 +1,30 @@
+From a8b948a7967cbea9b5b2c00ed85d2beb37db53e9 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 30 Apr 2018 17:09:55 +0530
+Subject: [PATCH 37/52] revert master-rebase changes to gdbserver , previous
+ commit typo's
+
+---
+ gdb/gdbserver/Makefile.in | 2 ++
+ 1 file changed, 2 insertions(+)
+
+Index: gdb-9.2/gdb/gdbserver/Makefile.in
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/Makefile.in
++++ gdb-9.2/gdb/gdbserver/Makefile.in
+@@ -172,6 +172,7 @@ SFILES = \
+ 	$(srcdir)/linux-low.c \
+ 	$(srcdir)/linux-m32r-low.c \
+ 	$(srcdir)/linux-m68k-low.c \
++        $(srcdir)/linux-microblaze-low.c \
+ 	$(srcdir)/linux-mips-low.c \
+ 	$(srcdir)/linux-nios2-low.c \
+ 	$(srcdir)/linux-ppc-low.c \
+@@ -232,6 +233,7 @@ SFILES = \
+ 	$(srcdir)/nat/linux-osdata.c \
+ 	$(srcdir)/nat/linux-personality.c \
+ 	$(srcdir)/nat/mips-linux-watch.c \
++        $(srcdir)/nat/microblaze-linux.c \
+ 	$(srcdir)/nat/ppc-linux.c \
+ 	$(srcdir)/nat/fork-inferior.c \
+ 	$(srcdir)/target/waitstatus.c
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch
deleted file mode 100644
index afde3ce89f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-Initial-support-for-native-gdb.patch
+++ /dev/null
@@ -1,492 +0,0 @@
-From a06b9c4860af1f8f18ccb7c0653c76c623636034 Mon Sep 17 00:00:00 2001
-From: David Holsgrove <david.holsgrove@petalogix.com>
-Date: Fri, 20 Jul 2012 15:18:35 +1000
-Subject: [PATCH 38/40] Initial support for native gdb
-
-microblaze: Follow PPC method of getting setting registers
-using PTRACE PEEK/POKE
-
-Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
----
- gdb/Makefile.in                |   2 +
- gdb/config/microblaze/linux.mh |   9 +
- gdb/microblaze-linux-nat.c     | 431 +++++++++++++++++++++++++++++++++
- 3 files changed, 442 insertions(+)
- create mode 100644 gdb/config/microblaze/linux.mh
- create mode 100644 gdb/microblaze-linux-nat.c
-
-diff --git a/gdb/Makefile.in b/gdb/Makefile.in
-index c3e074b21fe..cbcd8f43326 100644
---- a/gdb/Makefile.in
-+++ b/gdb/Makefile.in
-@@ -1337,6 +1337,7 @@ HFILES_NO_SRCDIR = \
- 	memory-map.h \
- 	memrange.h \
- 	microblaze-tdep.h \
-+	microblaze-linux-tdep.h \
- 	mips-linux-tdep.h \
- 	mips-nbsd-tdep.h \
- 	mips-tdep.h \
-@@ -2261,6 +2262,7 @@ ALLDEPFILES = \
- 	m68k-tdep.c \
- 	microblaze-linux-tdep.c \
- 	microblaze-tdep.c \
-+	microblaze-linux-nat.c \
- 	mingw-hdep.c \
- 	mips-fbsd-nat.c \
- 	mips-fbsd-tdep.c \
-diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
-new file mode 100644
-index 00000000000..a4eaf540e1d
---- /dev/null
-+++ b/gdb/config/microblaze/linux.mh
-@@ -0,0 +1,9 @@
-+# Host: Microblaze, running Linux
-+
-+NAT_FILE= config/nm-linux.h
-+NATDEPFILES= inf-ptrace.o fork-child.o \
-+	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
-+	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
-+NAT_CDEPS = $(srcdir)/proc-service.list
-+
-+LOADLIBES = -ldl $(RDYNAMIC)
-diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
-new file mode 100644
-index 00000000000..e9b8c9c5221
---- /dev/null
-+++ b/gdb/microblaze-linux-nat.c
-@@ -0,0 +1,431 @@
-+/* Microblaze GNU/Linux native support.
-+
-+   Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
-+   Software Foundation, Inc.
-+
-+   This file is part of GDB.
-+
-+   This program is free software; you can redistribute it and/or modify
-+   it under the terms of the GNU General Public License as published by
-+   the Free Software Foundation; either version 3 of the License, or
-+   (at your option) any later version.
-+
-+   This program is distributed in the hope that it will be useful,
-+   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+   GNU General Public License for more details.
-+
-+   You should have received a copy of the GNU General Public License
-+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
-+
-+#include "defs.h"
-+#include "arch-utils.h"
-+#include "dis-asm.h"
-+#include "frame.h"
-+#include "trad-frame.h"
-+#include "symtab.h"
-+#include "value.h"
-+#include "gdbcmd.h"
-+#include "breakpoint.h"
-+#include "inferior.h"
-+#include "regcache.h"
-+#include "target.h"
-+#include "frame.h"
-+#include "frame-base.h"
-+#include "frame-unwind.h"
-+#include "dwarf2-frame.h"
-+#include "osabi.h"
-+
-+#include "gdb_assert.h"
-+#include "gdb_string.h"
-+#include "target-descriptions.h"
-+#include "opcodes/microblaze-opcm.h"
-+#include "opcodes/microblaze-dis.h"
-+
-+#include "linux-nat.h"
-+#include "target-descriptions.h"
-+
-+#include <sys/user.h>
-+#include <sys/utsname.h>
-+#include <sys/procfs.h>
-+#include <sys/ptrace.h>
-+
-+/* Prototypes for supply_gregset etc. */
-+#include "gregset.h"
-+
-+#include "microblaze-tdep.h"
-+
-+#include <elf/common.h>
-+#include "auxv.h"
-+
-+/* Defines ps_err_e, struct ps_prochandle.  */
-+#include "gdb_proc_service.h"
-+
-+/* On GNU/Linux, threads are implemented as pseudo-processes, in which
-+   case we may be tracing more than one process at a time.  In that
-+   case, inferior_ptid will contain the main process ID and the
-+   individual thread (process) ID.  get_thread_id () is used to get
-+   the thread id if it's available, and the process id otherwise.  */
-+
-+int
-+get_thread_id (ptid_t ptid)
-+{
-+  int tid = TIDGET (ptid);
-+  if (0 == tid)
-+    tid = PIDGET (ptid);
-+  return tid;
-+}
-+
-+#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
-+
-+/* Non-zero if our kernel may support the PTRACE_GETREGS and
-+   PTRACE_SETREGS requests, for reading and writing the
-+   general-purpose registers.  Zero if we've tried one of
-+   them and gotten an error.  */
-+int have_ptrace_getsetregs = 1;
-+
-+static int
-+microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
-+{
-+  int u_addr = -1;
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
-+     interface, and not the wordsize of the program's ABI.  */
-+  int wordsize = sizeof (long);
-+
-+  /* General purpose registers occupy 1 slot each in the buffer.  */
-+  if (regno >= MICROBLAZE_R0_REGNUM
-+      && regno <= MICROBLAZE_FSR_REGNUM)
-+    u_addr = (regno * wordsize);
-+
-+  return u_addr;
-+}
-+
-+
-+static void
-+fetch_register (struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* This isn't really an address.  But ptrace thinks of it as one.  */
-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
-+  int bytes_transferred;
-+  unsigned int offset;         /* Offset of registers within the u area.  */
-+  char buf[MAX_REGISTER_SIZE];
-+
-+  if (regaddr == -1)
-+  {
-+    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
-+    regcache_raw_supply (regcache, regno, buf);
-+    return;
-+  }
-+
-+  /* Read the raw register using sizeof(long) sized chunks.  On a
-+     32-bit platform, 64-bit floating-point registers will require two
-+     transfers.  */
-+  for (bytes_transferred = 0;
-+       bytes_transferred < register_size (gdbarch, regno);
-+       bytes_transferred += sizeof (long))
-+  {
-+    long l;
-+
-+    errno = 0;
-+    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
-+    regaddr += sizeof (long);
-+    if (errno != 0)
-+    {
-+      char message[128];
-+      sprintf (message, "reading register %s (#%d)",
-+               gdbarch_register_name (gdbarch, regno), regno);
-+      perror_with_name (message);
-+    }
-+    memcpy (&buf[bytes_transferred], &l, sizeof (l));
-+  }
-+
-+  /* Now supply the register.  Keep in mind that the regcache's idea
-+     of the register's size may not be a multiple of sizeof
-+     (long).  */
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
-+  {
-+    /* Little-endian values are always found at the left end of the
-+       bytes transferred.  */
-+    regcache_raw_supply (regcache, regno, buf);
-+  }
-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+  {
-+    /* Big-endian values are found at the right end of the bytes
-+       transferred.  */
-+    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
-+    regcache_raw_supply (regcache, regno, buf + padding);
-+  }
-+  else
-+    internal_error (__FILE__, __LINE__,
-+                    _("fetch_register: unexpected byte order: %d"),
-+                    gdbarch_byte_order (gdbarch));
-+}
-+
-+/* This function actually issues the request to ptrace, telling
-+   it to get all general-purpose registers and put them into the
-+   specified regset.
-+
-+   If the ptrace request does not exist, this function returns 0
-+   and properly sets the have_ptrace_* flag.  If the request fails,
-+   this function calls perror_with_name.  Otherwise, if the request
-+   succeeds, then the regcache gets filled and 1 is returned.  */
-+static int
-+fetch_all_gp_regs (struct regcache *regcache, int tid)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  gdb_gregset_t gregset;
-+
-+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
-+  {
-+    if (errno == EIO)
-+    {
-+      have_ptrace_getsetregs = 0;
-+      return 0;
-+    }
-+    perror_with_name (_("Couldn't get general-purpose registers."));
-+  }
-+
-+  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
-+
-+  return 1;
-+}
-+
-+
-+/* This is a wrapper for the fetch_all_gp_regs function.  It is
-+   responsible for verifying if this target has the ptrace request
-+   that can be used to fetch all general-purpose registers at one
-+   shot.  If it doesn't, then we should fetch them using the
-+   old-fashioned way, which is to iterate over the registers and
-+   request them one by one.  */
-+static void
-+fetch_gp_regs (struct regcache *regcache, int tid)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  int i;
-+
-+  if (have_ptrace_getsetregs)
-+    if (fetch_all_gp_regs (regcache, tid))
-+      return;
-+
-+  /* If we've hit this point, it doesn't really matter which
-+     architecture we are using.  We just need to read the
-+     registers in the "old-fashioned way".  */
-+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
-+    fetch_register (regcache, tid, i);
-+}
-+
-+
-+static void
-+store_register (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  /* This isn't really an address.  But ptrace thinks of it as one.  */
-+  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
-+  int i;
-+  size_t bytes_to_transfer;
-+  char buf[MAX_REGISTER_SIZE];
-+
-+  if (regaddr == -1)
-+    return;
-+
-+  /* First collect the register.  Keep in mind that the regcache's
-+     idea of the register's size may not be a multiple of sizeof
-+     (long).  */
-+  memset (buf, 0, sizeof buf);
-+  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
-+  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
-+  {
-+    /* Little-endian values always sit at the left end of the buffer.  */
-+    regcache_raw_collect (regcache, regno, buf);
-+  }
-+  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
-+  {
-+    /* Big-endian values sit at the right end of the buffer.  */
-+    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
-+    regcache_raw_collect (regcache, regno, buf + padding);
-+  }
-+
-+  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
-+  {
-+    long l;
-+
-+    memcpy (&l, &buf[i], sizeof (l));
-+    errno = 0;
-+    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
-+    regaddr += sizeof (long);
-+
-+    if (errno != 0)
-+    {
-+      char message[128];
-+      sprintf (message, "writing register %s (#%d)",
-+               gdbarch_register_name (gdbarch, regno), regno);
-+      perror_with_name (message);
-+    }
-+  }
-+}
-+
-+/* This function actually issues the request to ptrace, telling
-+   it to store all general-purpose registers present in the specified
-+   regset.
-+
-+   If the ptrace request does not exist, this function returns 0
-+   and properly sets the have_ptrace_* flag.  If the request fails,
-+   this function calls perror_with_name.  Otherwise, if the request
-+   succeeds, then the regcache is stored and 1 is returned.  */
-+static int
-+store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  gdb_gregset_t gregset;
-+
-+  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
-+    {
-+      if (errno == EIO)
-+      {
-+        have_ptrace_getsetregs = 0;
-+        return 0;
-+      }
-+      perror_with_name (_("Couldn't get general-purpose registers."));
-+    }
-+
-+  fill_gregset (regcache, &gregset, regno);
-+
-+  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
-+    {
-+      if (errno == EIO)
-+      {
-+        have_ptrace_getsetregs = 0;
-+        return 0;
-+      }
-+      perror_with_name (_("Couldn't set general-purpose registers."));
-+    }
-+
-+  return 1;
-+}
-+
-+/* This is a wrapper for the store_all_gp_regs function.  It is
-+   responsible for verifying if this target has the ptrace request
-+   that can be used to store all general-purpose registers at one
-+   shot.  If it doesn't, then we should store them using the
-+   old-fashioned way, which is to iterate over the registers and
-+   store them one by one.  */
-+static void
-+store_gp_regs (const struct regcache *regcache, int tid, int regno)
-+{
-+  struct gdbarch *gdbarch = get_regcache_arch (regcache);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
-+  int i;
-+
-+  if (have_ptrace_getsetregs)
-+    if (store_all_gp_regs (regcache, tid, regno))
-+      return;
-+
-+  /* If we hit this point, it doesn't really matter which
-+     architecture we are using.  We just need to store the
-+     registers in the "old-fashioned way".  */
-+  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
-+    store_register (regcache, tid, i);
-+}
-+
-+
-+/* Fetch registers from the child process.  Fetch all registers if
-+   regno == -1, otherwise fetch all general registers or all floating
-+   point registers depending upon the value of regno.  */
-+
-+static void
-+microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
-+				    struct regcache *regcache, int regno)
-+{
-+  /* Get the thread id for the ptrace call.  */
-+  int tid = GET_THREAD_ID (inferior_ptid);
-+
-+  if (regno == -1)
-+    fetch_gp_regs (regcache, tid);
-+  else
-+    fetch_register (regcache, tid, regno);
-+}
-+
-+/* Store registers back into the inferior.  Store all registers if
-+   regno == -1, otherwise store all general registers or all floating
-+   point registers depending upon the value of regno.  */
-+
-+static void
-+microblaze_linux_store_inferior_registers (struct target_ops *ops,
-+				    struct regcache *regcache, int regno)
-+{
-+  /* Get the thread id for the ptrace call.  */
-+  int tid = GET_THREAD_ID (inferior_ptid);
-+
-+  if (regno >= 0)
-+    store_register (regcache, tid, regno);
-+  else
-+    store_gp_regs (regcache, tid, -1);
-+}
-+
-+/* Wrapper functions for the standard regset handling, used by
-+   thread debugging.  */
-+
-+void
-+fill_gregset (const struct regcache *regcache,
-+	      gdb_gregset_t *gregsetp, int regno)
-+{
-+  microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
-+}
-+
-+void
-+supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
-+{
-+  microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
-+}
-+
-+void
-+fill_fpregset (const struct regcache *regcache,
-+	      gdb_fpregset_t *fpregsetp, int regno)
-+{
-+  /* FIXME. */
-+}
-+
-+void
-+supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
-+{
-+  /* FIXME. */
-+}
-+
-+static const struct target_desc *
-+microblaze_linux_read_description (struct target_ops *ops)
-+{
-+  CORE_ADDR microblaze_hwcap = 0;
-+
-+  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
-+    return NULL;
-+
-+  return NULL;
-+}
-+
-+
-+void _initialize_microblaze_linux_nat (void);
-+
-+void
-+_initialize_microblaze_linux_nat (void)
-+{
-+  struct target_ops *t;
-+
-+  /* Fill in the generic GNU/Linux methods.  */
-+  t = linux_target ();
-+
-+  /* Add our register access methods.  */
-+  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
-+  t->to_store_registers = microblaze_linux_store_inferior_registers;
-+
-+  t->to_read_description = microblaze_linux_read_description;
-+
-+  /* Register the target.  */
-+  linux_nat_add_target (t);
-+}
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
new file mode 100644
index 0000000000..37a9646f4d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0038-microblaze-Add-build_gdbserver-yes-to-top-level-conf.patch
@@ -0,0 +1,29 @@
+From 6474cf4147887529ccb506b80f945aa67178f5bd Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@xilinx.com>
+Date: Mon, 16 Dec 2013 16:37:32 +1000
+Subject: [PATCH 38/52] microblaze: Add build_gdbserver=yes to top level
+ configure.tgt
+
+For Microblaze linux toolchains, set the build_gdbserver=yes
+to allow driving gdbserver configuration from the upper level
+
+This patch has been absorbed into the original patch to add
+linux gdbserver support for Microblaze.
+
+Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
+---
+ gdb/configure.tgt | 1 +
+ 1 file changed, 1 insertion(+)
+
+Index: gdb-9.2/gdb/configure.tgt
+===================================================================
+--- gdb-9.2.orig/gdb/configure.tgt
++++ gdb-9.2/gdb/configure.tgt
+@@ -408,6 +408,7 @@ microblaze*-*-*)
+ 	# Target: Xilinx MicroBlaze running standalone
+ 	gdb_target_obs="microblaze-tdep.o"
+ 	gdb_sim=../sim/microblaze/libsim.a
++	build_gdbserver=yes
+ 	;;
+ 
+ mips*-*-linux*)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch
deleted file mode 100644
index fb4b35e599..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Fixing-the-issues-related-to-GDB-7.12.patch
+++ /dev/null
@@ -1,216 +0,0 @@
-From f13ffe15c10e5d4b5c87761ae9735144d4c8da17 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Fri, 17 Feb 2017 14:09:40 +0530
-Subject: [PATCH 39/40] Fixing the issues related to GDB-7.12
-
-added all the required function which are new in 7.12 and removed
-few deprecated functions from 7.6
----
- gdb/config/microblaze/linux.mh       |  4 +-
- gdb/gdbserver/configure.srv          |  3 +-
- gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++----
- gdb/microblaze-tdep.h                |  1 +
- 4 files changed, 89 insertions(+), 16 deletions(-)
-
-diff --git a/gdb/config/microblaze/linux.mh b/gdb/config/microblaze/linux.mh
-index a4eaf540e1d..74a53b854a4 100644
---- a/gdb/config/microblaze/linux.mh
-+++ b/gdb/config/microblaze/linux.mh
-@@ -1,9 +1,11 @@
- # Host: Microblaze, running Linux
- 
-+#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
- NAT_FILE= config/nm-linux.h
- NATDEPFILES= inf-ptrace.o fork-child.o \
- 	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
--	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
-+	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
-+	linux-waitpid.o linux-personality.o linux-namespaces.o
- NAT_CDEPS = $(srcdir)/proc-service.list
- 
- LOADLIBES = -ldl $(RDYNAMIC)
-diff --git a/gdb/gdbserver/configure.srv b/gdb/gdbserver/configure.srv
-index e0d2b2fe04a..26db2dd2461 100644
---- a/gdb/gdbserver/configure.srv
-+++ b/gdb/gdbserver/configure.srv
-@@ -185,8 +185,7 @@ case "${target}" in
- 			srv_linux_thread_db=yes
- 			;;
-   microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
--			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
--			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
-+			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
- 			srv_xmlfiles="microblaze-linux.xml"
- 			srv_linux_regsets=yes
- 			srv_linux_usrregs=yes
-diff --git a/gdb/gdbserver/linux-microblaze-low.c b/gdb/gdbserver/linux-microblaze-low.c
-index cba5d6fc585..a2733f3c21c 100644
---- a/gdb/gdbserver/linux-microblaze-low.c
-+++ b/gdb/gdbserver/linux-microblaze-low.c
-@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
-   PT_FSR
-   };
- 
--#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
-+#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
- 
- /* Defined in auto-generated file microblaze-linux.c.  */
- void init_registers_microblaze (void);
-+extern const struct target_desc *tdesc_microblaze;
- 
- static int
- microblaze_cannot_store_register (int regno)
-@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regcache, CORE_ADDR pc)
- static const unsigned long microblaze_breakpoint = 0xba0c0018;
- #define microblaze_breakpoint_len 4
- 
-+/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
-+
-+static const gdb_byte *
-+microblaze_sw_breakpoint_from_kind (int kind, int *size)
-+{
-+  *size = microblaze_breakpoint_len;
-+  return (const gdb_byte *) &microblaze_breakpoint;
-+}
-+
- static int
- microblaze_breakpoint_at (CORE_ADDR where)
- {
-@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcache *regcache)
- static void
- microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
- {
--  int size = register_size (regno);
-+  int size = register_size (regcache->tdesc, regno);
- 
-   memset (buf, 0, sizeof (long));
- 
-@@ -121,7 +131,7 @@ static void
- microblaze_supply_ptrace_register (struct regcache *regcache,
- 			    int regno, const char *buf)
- {
--  int size = register_size (regno);
-+  int size = register_size (regcache->tdesc, regno);
- 
-   if (regno == 0) {
-     unsigned long regbuf_0 = 0;
-@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcache *regcache, const void *buf)
- 
- #endif /* HAVE_PTRACE_GETREGS */
- 
--struct regset_info target_regsets[] = {
-+static struct regset_info microblaze_regsets[] = {
- #ifdef HAVE_PTRACE_GETREGS
-   { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
--  { 0, 0, 0, -1, -1, NULL, NULL },
-+  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
- #endif /* HAVE_PTRACE_GETREGS */
--  { 0, 0, 0, -1, -1, NULL, NULL }
-+  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
-+  NULL_REGSET
- };
- 
-+static struct usrregs_info microblaze_usrregs_info =
-+  {
-+    microblaze_num_regs,
-+    microblaze_regmap,
-+  };
-+
-+static struct regsets_info microblaze_regsets_info =
-+  {
-+    microblaze_regsets, /* regsets */
-+    0, /* num_regsets */
-+    NULL, /* disabled_regsets */
-+  };
-+
-+static struct regs_info regs_info =
-+  {
-+    NULL, /* regset_bitmap */
-+    &microblaze_usrregs_info,
-+    &microblaze_regsets_info
-+  };
-+
-+static const struct regs_info *
-+microblaze_regs_info (void)
-+{
-+  return &regs_info;
-+}
-+
-+/* Support for hardware single step.  */
-+
-+static int
-+microblaze_supports_hardware_single_step (void)
-+{
-+  return 1;
-+}
-+
-+
-+static void
-+microblaze_arch_setup (void)
-+{
-+  current_process ()->tdesc = tdesc_microblaze;
-+}
-+
- struct linux_target_ops the_low_target = {
--  init_registers_microblaze,
--  microblaze_num_regs,
--  microblaze_regmap,
--  NULL,
-+  microblaze_arch_setup,
-+  microblaze_regs_info,
-   microblaze_cannot_fetch_register,
-   microblaze_cannot_store_register,
-   NULL, /* fetch_register */
-   microblaze_get_pc,
-   microblaze_set_pc,
--  (const unsigned char *) &microblaze_breakpoint,
--  microblaze_breakpoint_len,
--  microblaze_reinsert_addr,
-+  NULL,
-+  microblaze_sw_breakpoint_from_kind,
-+  NULL,
-   0,
-   microblaze_breakpoint_at,
-   NULL,
-   NULL,
-   NULL,
-   NULL,
-+  NULL,
-   microblaze_collect_ptrace_register,
-   microblaze_supply_ptrace_register,
-+  NULL, /* siginfo_fixup */
-+  NULL, /* new_process */
-+  NULL, /* new_thread */
-+  NULL, /* new_fork */
-+  NULL, /* prepare_to_resume */
-+  NULL, /* process_qsupported */
-+  NULL, /* supports_tracepoints */
-+  NULL, /* get_thread_area */
-+  NULL, /* install_fast_tracepoint_jump_pad */
-+  NULL, /* emit_ops */
-+  NULL, /* get_min_fast_tracepoint_insn_len */
-+  NULL, /* supports_range_stepping */
-+  NULL, /* breakpoint_kind_from_current_state */
-+  microblaze_supports_hardware_single_step,
- };
-+
-+void
-+initialize_low_arch (void)
-+{
-+  init_registers_microblaze ();
-+}
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index 8f41ba19351..d2112dc07e1 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -24,6 +24,7 @@
- /* Microblaze architecture-specific information.  */
- struct microblaze_gregset
- {
-+   microblaze_gregset() {}
-    unsigned int gregs[32];
-    unsigned int fpregs[32];
-    unsigned int pregs[16];
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-support-for-native-gdb.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-support-for-native-gdb.patch
new file mode 100644
index 0000000000..669b592736
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0039-Initial-support-for-native-gdb.patch
@@ -0,0 +1,490 @@
+From db3c0a8a59b292eea6ed1f532f4097c40cafd7df Mon Sep 17 00:00:00 2001
+From: David Holsgrove <david.holsgrove@petalogix.com>
+Date: Fri, 20 Jul 2012 15:18:35 +1000
+Subject: [PATCH 39/52] Initial support for native gdb
+
+microblaze: Follow PPC method of getting setting registers
+using PTRACE PEEK/POKE
+
+Signed-off-by: David Holsgrove <david.holsgrove@petalogix.com>
+
+Conflicts:
+	gdb/Makefile.in
+---
+ gdb/Makefile.in                |   2 +
+ gdb/config/microblaze/linux.mh |   9 +
+ gdb/microblaze-linux-nat.c     | 431 +++++++++++++++++++++++++++++++++
+ 3 files changed, 442 insertions(+)
+ create mode 100644 gdb/config/microblaze/linux.mh
+ create mode 100644 gdb/microblaze-linux-nat.c
+
+Index: gdb-9.2/gdb/Makefile.in
+===================================================================
+--- gdb-9.2.orig/gdb/Makefile.in
++++ gdb-9.2/gdb/Makefile.in
+@@ -1337,6 +1337,7 @@ HFILES_NO_SRCDIR = \
+ 	memory-map.h \
+ 	memrange.h \
+ 	microblaze-tdep.h \
++	microblaze-linux-tdep.h \
+ 	mips-linux-tdep.h \
+ 	mips-nbsd-tdep.h \
+ 	mips-tdep.h \
+@@ -2261,6 +2262,7 @@ ALLDEPFILES = \
+ 	m68k-tdep.c \
+ 	microblaze-linux-tdep.c \
+ 	microblaze-tdep.c \
++	microblaze-linux-nat.c \
+ 	mingw-hdep.c \
+ 	mips-fbsd-nat.c \
+ 	mips-fbsd-tdep.c \
+Index: gdb-9.2/gdb/config/microblaze/linux.mh
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/config/microblaze/linux.mh
+@@ -0,0 +1,9 @@
++# Host: Microblaze, running Linux
++
++NAT_FILE= config/nm-linux.h
++NATDEPFILES= inf-ptrace.o fork-child.o \
++	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
++	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++NAT_CDEPS = $(srcdir)/proc-service.list
++
++LOADLIBES = -ldl $(RDYNAMIC)
+Index: gdb-9.2/gdb/microblaze-linux-nat.c
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/microblaze-linux-nat.c
+@@ -0,0 +1,431 @@
++/* Microblaze GNU/Linux native support.
++
++   Copyright (C) 1988-1989, 1991-1992, 1994, 1996, 2000-2012 Free
++   Software Foundation, Inc.
++
++   This file is part of GDB.
++
++   This program is free software; you can redistribute it and/or modify
++   it under the terms of the GNU General Public License as published by
++   the Free Software Foundation; either version 3 of the License, or
++   (at your option) any later version.
++
++   This program is distributed in the hope that it will be useful,
++   but WITHOUT ANY WARRANTY; without even the implied warranty of
++   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++   GNU General Public License for more details.
++
++   You should have received a copy of the GNU General Public License
++   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
++
++#include "defs.h"
++#include "arch-utils.h"
++#include "dis-asm.h"
++#include "frame.h"
++#include "trad-frame.h"
++#include "symtab.h"
++#include "value.h"
++#include "gdbcmd.h"
++#include "breakpoint.h"
++#include "inferior.h"
++#include "regcache.h"
++#include "target.h"
++#include "frame.h"
++#include "frame-base.h"
++#include "frame-unwind.h"
++#include "dwarf2-frame.h"
++#include "osabi.h"
++
++#include "gdb_assert.h"
++#include "gdb_string.h"
++#include "target-descriptions.h"
++#include "opcodes/microblaze-opcm.h"
++#include "opcodes/microblaze-dis.h"
++
++#include "linux-nat.h"
++#include "target-descriptions.h"
++
++#include <sys/user.h>
++#include <sys/utsname.h>
++#include <sys/procfs.h>
++#include <sys/ptrace.h>
++
++/* Prototypes for supply_gregset etc. */
++#include "gregset.h"
++
++#include "microblaze-tdep.h"
++
++#include <elf/common.h>
++#include "auxv.h"
++
++/* Defines ps_err_e, struct ps_prochandle.  */
++#include "gdb_proc_service.h"
++
++/* On GNU/Linux, threads are implemented as pseudo-processes, in which
++   case we may be tracing more than one process at a time.  In that
++   case, inferior_ptid will contain the main process ID and the
++   individual thread (process) ID.  get_thread_id () is used to get
++   the thread id if it's available, and the process id otherwise.  */
++
++int
++get_thread_id (ptid_t ptid)
++{
++  int tid = TIDGET (ptid);
++  if (0 == tid)
++    tid = PIDGET (ptid);
++  return tid;
++}
++
++#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
++
++/* Non-zero if our kernel may support the PTRACE_GETREGS and
++   PTRACE_SETREGS requests, for reading and writing the
++   general-purpose registers.  Zero if we've tried one of
++   them and gotten an error.  */
++int have_ptrace_getsetregs = 1;
++
++static int
++microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
++{
++  int u_addr = -1;
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
++     interface, and not the wordsize of the program's ABI.  */
++  int wordsize = sizeof (long);
++
++  /* General purpose registers occupy 1 slot each in the buffer.  */
++  if (regno >= MICROBLAZE_R0_REGNUM
++      && regno <= MICROBLAZE_FSR_REGNUM)
++    u_addr = (regno * wordsize);
++
++  return u_addr;
++}
++
++
++static void
++fetch_register (struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int bytes_transferred;
++  unsigned int offset;         /* Offset of registers within the u area.  */
++  char buf[MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++  {
++    memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
++    regcache_raw_supply (regcache, regno, buf);
++    return;
++  }
++
++  /* Read the raw register using sizeof(long) sized chunks.  On a
++     32-bit platform, 64-bit floating-point registers will require two
++     transfers.  */
++  for (bytes_transferred = 0;
++       bytes_transferred < register_size (gdbarch, regno);
++       bytes_transferred += sizeof (long))
++  {
++    long l;
++
++    errno = 0;
++    l = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
++    regaddr += sizeof (long);
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "reading register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++    memcpy (&buf[bytes_transferred], &l, sizeof (l));
++  }
++
++  /* Now supply the register.  Keep in mind that the regcache's idea
++     of the register's size may not be a multiple of sizeof
++     (long).  */
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values are always found at the left end of the
++       bytes transferred.  */
++    regcache_raw_supply (regcache, regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values are found at the right end of the bytes
++       transferred.  */
++    size_t padding = (bytes_transferred - register_size (gdbarch, regno));
++    regcache_raw_supply (regcache, regno, buf + padding);
++  }
++  else
++    internal_error (__FILE__, __LINE__,
++                    _("fetch_register: unexpected byte order: %d"),
++                    gdbarch_byte_order (gdbarch));
++}
++
++/* This function actually issues the request to ptrace, telling
++   it to get all general-purpose registers and put them into the
++   specified regset.
++
++   If the ptrace request does not exist, this function returns 0
++   and properly sets the have_ptrace_* flag.  If the request fails,
++   this function calls perror_with_name.  Otherwise, if the request
++   succeeds, then the regcache gets filled and 1 is returned.  */
++static int
++fetch_all_gp_regs (struct regcache *regcache, int tid)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  gdb_gregset_t gregset;
++
++  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++  {
++    if (errno == EIO)
++    {
++      have_ptrace_getsetregs = 0;
++      return 0;
++    }
++    perror_with_name (_("Couldn't get general-purpose registers."));
++  }
++
++  supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
++
++  return 1;
++}
++
++
++/* This is a wrapper for the fetch_all_gp_regs function.  It is
++   responsible for verifying if this target has the ptrace request
++   that can be used to fetch all general-purpose registers at one
++   shot.  If it doesn't, then we should fetch them using the
++   old-fashioned way, which is to iterate over the registers and
++   request them one by one.  */
++static void
++fetch_gp_regs (struct regcache *regcache, int tid)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  int i;
++
++  if (have_ptrace_getsetregs)
++    if (fetch_all_gp_regs (regcache, tid))
++      return;
++
++  /* If we've hit this point, it doesn't really matter which
++     architecture we are using.  We just need to read the
++     registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    fetch_register (regcache, tid, i);
++}
++
++
++static void
++store_register (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  /* This isn't really an address.  But ptrace thinks of it as one.  */
++  CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
++  int i;
++  size_t bytes_to_transfer;
++  char buf[MAX_REGISTER_SIZE];
++
++  if (regaddr == -1)
++    return;
++
++  /* First collect the register.  Keep in mind that the regcache's
++     idea of the register's size may not be a multiple of sizeof
++     (long).  */
++  memset (buf, 0, sizeof buf);
++  bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
++  if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
++  {
++    /* Little-endian values always sit at the left end of the buffer.  */
++    regcache_raw_collect (regcache, regno, buf);
++  }
++  else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
++  {
++    /* Big-endian values sit at the right end of the buffer.  */
++    size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
++    regcache_raw_collect (regcache, regno, buf + padding);
++  }
++
++  for (i = 0; i < bytes_to_transfer; i += sizeof (long))
++  {
++    long l;
++
++    memcpy (&l, &buf[i], sizeof (l));
++    errno = 0;
++    ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr, l);
++    regaddr += sizeof (long);
++
++    if (errno != 0)
++    {
++      char message[128];
++      sprintf (message, "writing register %s (#%d)",
++               gdbarch_register_name (gdbarch, regno), regno);
++      perror_with_name (message);
++    }
++  }
++}
++
++/* This function actually issues the request to ptrace, telling
++   it to store all general-purpose registers present in the specified
++   regset.
++
++   If the ptrace request does not exist, this function returns 0
++   and properly sets the have_ptrace_* flag.  If the request fails,
++   this function calls perror_with_name.  Otherwise, if the request
++   succeeds, then the regcache is stored and 1 is returned.  */
++static int
++store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  gdb_gregset_t gregset;
++
++  if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
++    {
++      if (errno == EIO)
++      {
++        have_ptrace_getsetregs = 0;
++        return 0;
++      }
++      perror_with_name (_("Couldn't get general-purpose registers."));
++    }
++
++  fill_gregset (regcache, &gregset, regno);
++
++  if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
++    {
++      if (errno == EIO)
++      {
++        have_ptrace_getsetregs = 0;
++        return 0;
++      }
++      perror_with_name (_("Couldn't set general-purpose registers."));
++    }
++
++  return 1;
++}
++
++/* This is a wrapper for the store_all_gp_regs function.  It is
++   responsible for verifying if this target has the ptrace request
++   that can be used to store all general-purpose registers at one
++   shot.  If it doesn't, then we should store them using the
++   old-fashioned way, which is to iterate over the registers and
++   store them one by one.  */
++static void
++store_gp_regs (const struct regcache *regcache, int tid, int regno)
++{
++  struct gdbarch *gdbarch = get_regcache_arch (regcache);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  int i;
++
++  if (have_ptrace_getsetregs)
++    if (store_all_gp_regs (regcache, tid, regno))
++      return;
++
++  /* If we hit this point, it doesn't really matter which
++     architecture we are using.  We just need to store the
++     registers in the "old-fashioned way".  */
++  for (i = MICROBLAZE_R0_REGNUM; i <= MICROBLAZE_FSR_REGNUM; i++)
++    store_register (regcache, tid, i);
++}
++
++
++/* Fetch registers from the child process.  Fetch all registers if
++   regno == -1, otherwise fetch all general registers or all floating
++   point registers depending upon the value of regno.  */
++
++static void
++microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
++				    struct regcache *regcache, int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = GET_THREAD_ID (inferior_ptid);
++
++  if (regno == -1)
++    fetch_gp_regs (regcache, tid);
++  else
++    fetch_register (regcache, tid, regno);
++}
++
++/* Store registers back into the inferior.  Store all registers if
++   regno == -1, otherwise store all general registers or all floating
++   point registers depending upon the value of regno.  */
++
++static void
++microblaze_linux_store_inferior_registers (struct target_ops *ops,
++				    struct regcache *regcache, int regno)
++{
++  /* Get the thread id for the ptrace call.  */
++  int tid = GET_THREAD_ID (inferior_ptid);
++
++  if (regno >= 0)
++    store_register (regcache, tid, regno);
++  else
++    store_gp_regs (regcache, tid, -1);
++}
++
++/* Wrapper functions for the standard regset handling, used by
++   thread debugging.  */
++
++void
++fill_gregset (const struct regcache *regcache,
++	      gdb_gregset_t *gregsetp, int regno)
++{
++  microblaze_collect_gregset (NULL, regcache, regno, gregsetp);
++}
++
++void
++supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
++{
++  microblaze_supply_gregset (NULL, regcache, -1, gregsetp);
++}
++
++void
++fill_fpregset (const struct regcache *regcache,
++	      gdb_fpregset_t *fpregsetp, int regno)
++{
++  /* FIXME. */
++}
++
++void
++supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
++{
++  /* FIXME. */
++}
++
++static const struct target_desc *
++microblaze_linux_read_description (struct target_ops *ops)
++{
++  CORE_ADDR microblaze_hwcap = 0;
++
++  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
++    return NULL;
++
++  return NULL;
++}
++
++
++void _initialize_microblaze_linux_nat (void);
++
++void
++_initialize_microblaze_linux_nat (void)
++{
++  struct target_ops *t;
++
++  /* Fill in the generic GNU/Linux methods.  */
++  t = linux_target ();
++
++  /* Add our register access methods.  */
++  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
++  t->to_store_registers = microblaze_linux_store_inferior_registers;
++
++  t->to_read_description = microblaze_linux_read_description;
++
++  /* Register the target.  */
++  linux_nat_add_target (t);
++}
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
new file mode 100644
index 0000000000..85f8174a73
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Fixing-the-issues-related-to-GDB-7.12-added-all-the-.patch
@@ -0,0 +1,306 @@
+From bf3c50c95c4dcca6c5c07a3c082bdd9d687f1496 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Fri, 17 Feb 2017 14:09:40 +0530
+Subject: [PATCH 40/52] Fixing the issues related to GDB-7.12 added all the
+ required function which are new in 7.12 and removed few deprecated functions
+ from 7.6
+
+---
+ gdb/config/microblaze/linux.mh       |  4 +-
+ gdb/gdbserver/configure.srv          |  3 +-
+ gdb/gdbserver/linux-microblaze-low.c | 97 ++++++++++++++++++++++++----
+ gdb/microblaze-linux-tdep.c          | 68 +++++++++++++++++--
+ gdb/microblaze-tdep.h                |  1 +
+ 5 files changed, 153 insertions(+), 20 deletions(-)
+
+Index: gdb-9.2/gdb/config/microblaze/linux.mh
+===================================================================
+--- gdb-9.2.orig/gdb/config/microblaze/linux.mh
++++ gdb-9.2/gdb/config/microblaze/linux.mh
+@@ -1,9 +1,11 @@
+ # Host: Microblaze, running Linux
+ 
++#linux-nat.o linux-waitpid.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
+ NAT_FILE= config/nm-linux.h
+ NATDEPFILES= inf-ptrace.o fork-child.o \
+ 	microblaze-linux-nat.o proc-service.o linux-thread-db.o \
+-	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o
++	linux-nat.o linux-osdata.o linux-fork.o linux-procfs.o linux-ptrace.o \
++	linux-waitpid.o linux-personality.o linux-namespaces.o
+ NAT_CDEPS = $(srcdir)/proc-service.list
+ 
+ LOADLIBES = -ldl $(RDYNAMIC)
+Index: gdb-9.2/gdb/gdbserver/configure.srv
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/configure.srv
++++ gdb-9.2/gdb/gdbserver/configure.srv
+@@ -185,8 +185,7 @@ case "${target}" in
+ 			srv_linux_thread_db=yes
+ 			;;
+   microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
+-			srv_tgtobj="linux-low.o linux-osdata.o linux-microblaze-low.o "
+-			srv_tgtobj="${srv_tgtobj} linux-procfs.o linux-ptrace.o"
++			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
+ 			srv_linux_regsets=yes
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+Index: gdb-9.2/gdb/gdbserver/linux-microblaze-low.c
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/linux-microblaze-low.c
++++ gdb-9.2/gdb/gdbserver/linux-microblaze-low.c
+@@ -39,10 +39,11 @@ static int microblaze_regmap[] =
+   PT_FSR
+   };
+ 
+-#define microblaze_num_regs (sizeof microblaze_regmap / sizeof microblaze_regmap[0])
++#define microblaze_num_regs (sizeof (microblaze_regmap) / sizeof (microblaze_regmap[0]))
+ 
+ /* Defined in auto-generated file microblaze-linux.c.  */
+ void init_registers_microblaze (void);
++extern const struct target_desc *tdesc_microblaze;
+ 
+ static int
+ microblaze_cannot_store_register (int regno)
+@@ -81,6 +82,15 @@ microblaze_set_pc (struct regcache *regc
+ static const unsigned long microblaze_breakpoint = 0xba0c0018;
+ #define microblaze_breakpoint_len 4
+ 
++/* Implementation of linux_target_ops method "sw_breakpoint_from_kind".  */
++
++static const gdb_byte *
++microblaze_sw_breakpoint_from_kind (int kind, int *size)
++{
++  *size = microblaze_breakpoint_len;
++  return (const gdb_byte *) &microblaze_breakpoint;
++}
++
+ static int
+ microblaze_breakpoint_at (CORE_ADDR where)
+ {
+@@ -107,7 +117,7 @@ microblaze_reinsert_addr (struct regcach
+ static void
+ microblaze_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
+ {
+-  int size = register_size (regno);
++  int size = register_size (regcache->tdesc, regno);
+ 
+   memset (buf, 0, sizeof (long));
+ 
+@@ -121,7 +131,7 @@ static void
+ microblaze_supply_ptrace_register (struct regcache *regcache,
+ 			    int regno, const char *buf)
+ {
+-  int size = register_size (regno);
++  int size = register_size (regcache->tdesc, regno);
+ 
+   if (regno == 0) {
+     unsigned long regbuf_0 = 0;
+@@ -157,33 +167,94 @@ microblaze_store_gregset (struct regcach
+ 
+ #endif /* HAVE_PTRACE_GETREGS */
+ 
+-struct regset_info target_regsets[] = {
++static struct regset_info microblaze_regsets[] = {
+ #ifdef HAVE_PTRACE_GETREGS
+   { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), GENERAL_REGS, microblaze_fill_gregset, microblaze_store_gregset },
+-  { 0, 0, 0, -1, -1, NULL, NULL },
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
+ #endif /* HAVE_PTRACE_GETREGS */
+-  { 0, 0, 0, -1, -1, NULL, NULL }
++  { 0, 0, 0, -1, GENERAL_REGS, NULL, NULL },
++  NULL_REGSET
+ };
+ 
++static struct usrregs_info microblaze_usrregs_info =
++  {
++    microblaze_num_regs,
++    microblaze_regmap,
++  };
++
++static struct regsets_info microblaze_regsets_info =
++  {
++    microblaze_regsets, /* regsets */
++    0, /* num_regsets */
++    NULL, /* disabled_regsets */
++  };
++
++static struct regs_info regs_info =
++  {
++    NULL, /* regset_bitmap */
++    &microblaze_usrregs_info,
++    &microblaze_regsets_info
++  };
++
++static const struct regs_info *
++microblaze_regs_info (void)
++{
++  return &regs_info;
++}
++
++/* Support for hardware single step.  */
++
++static int
++microblaze_supports_hardware_single_step (void)
++{
++  return 1;
++}
++
++
++static void
++microblaze_arch_setup (void)
++{
++  current_process ()->tdesc = tdesc_microblaze;
++}
++
+ struct linux_target_ops the_low_target = {
+-  init_registers_microblaze,
+-  microblaze_num_regs,
+-  microblaze_regmap,
+-  NULL,
++  microblaze_arch_setup,
++  microblaze_regs_info,
+   microblaze_cannot_fetch_register,
+   microblaze_cannot_store_register,
+   NULL, /* fetch_register */
+   microblaze_get_pc,
+   microblaze_set_pc,
+-  (const unsigned char *) &microblaze_breakpoint,
+-  microblaze_breakpoint_len,
+-  microblaze_reinsert_addr,
++  NULL,
++  microblaze_sw_breakpoint_from_kind,
++  NULL,
+   0,
+   microblaze_breakpoint_at,
+   NULL,
+   NULL,
+   NULL,
+   NULL,
++  NULL,
+   microblaze_collect_ptrace_register,
+   microblaze_supply_ptrace_register,
++  NULL, /* siginfo_fixup */
++  NULL, /* new_process */
++  NULL, /* new_thread */
++  NULL, /* new_fork */
++  NULL, /* prepare_to_resume */
++  NULL, /* process_qsupported */
++  NULL, /* supports_tracepoints */
++  NULL, /* get_thread_area */
++  NULL, /* install_fast_tracepoint_jump_pad */
++  NULL, /* emit_ops */
++  NULL, /* get_min_fast_tracepoint_insn_len */
++  NULL, /* supports_range_stepping */
++  NULL, /* breakpoint_kind_from_current_state */
++  microblaze_supports_hardware_single_step,
+ };
++
++void
++initialize_low_arch (void)
++{
++  init_registers_microblaze ();
++}
+Index: gdb-9.2/gdb/microblaze-linux-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-linux-tdep.c
++++ gdb-9.2/gdb/microblaze-linux-tdep.c
+@@ -29,13 +29,76 @@
+ #include "regcache.h"
+ #include "value.h"
+ #include "osabi.h"
+-#include "regset.h"
+ #include "solib-svr4.h"
+ #include "microblaze-tdep.h"
+ #include "trad-frame.h"
+ #include "frame-unwind.h"
+ #include "tramp-frame.h"
+ #include "linux-tdep.h"
++#include "glibc-tdep.h"
++
++#include "gdb_assert.h"
++
++#ifndef REGSET_H
++#define REGSET_H 1
++
++struct gdbarch;
++struct regcache;
++
++/* Data structure for the supported register notes in a core file.  */
++struct core_regset_section
++{
++  const char *sect_name;
++  int size;
++  const char *human_name;
++};
++
++/* Data structure describing a register set.  */
++
++typedef void (supply_regset_ftype) (const struct regset *, struct regcache *,
++                                    int, const void *, size_t);
++typedef void (collect_regset_ftype) (const struct regset *,
++                                     const struct regcache *,
++                                     int, void *, size_t);
++
++struct regset
++{
++  /* Data pointer for private use by the methods below, presumably
++     providing some sort of description of the register set.  */
++  const void *descr;
++
++  /* Function supplying values in a register set to a register cache.  */
++  supply_regset_ftype *supply_regset;
++
++  /* Function collecting values in a register set from a register cache.  */
++  collect_regset_ftype *collect_regset;
++
++  /* Architecture associated with the register set.  */
++  struct gdbarch *arch;
++};
++
++#endif
++
++/* Allocate a fresh 'struct regset' whose supply_regset function is
++   SUPPLY_REGSET, and whose collect_regset function is COLLECT_REGSET.
++   If the regset has no collect_regset function, pass NULL for
++   COLLECT_REGSET.
++
++   The object returned is allocated on ARCH's obstack.  */
++
++struct regset *
++regset_alloc (struct gdbarch *arch,
++              supply_regset_ftype *supply_regset,
++              collect_regset_ftype *collect_regset)
++{
++  struct regset *regset = GDBARCH_OBSTACK_ZALLOC (arch, struct regset);
++
++  regset->arch = arch;
++  regset->supply_regset = supply_regset;
++  regset->collect_regset = collect_regset;
++
++  return regset;
++}
+ 
+ static int microblaze_debug_flag = 0;
+ 
+@@ -207,9 +270,6 @@ microblaze_linux_init_abi (struct gdbarc
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+   set_gdbarch_skip_solib_resolver (gdbarch, glibc_skip_solib_resolver);
+ 
+-  set_gdbarch_regset_from_core_section (gdbarch,
+-					microblaze_regset_from_core_section);
+-
+   /* Enable TLS support.  */
+   set_gdbarch_fetch_tls_load_module_address (gdbarch,
+                                              svr4_fetch_objfile_link_map);
+Index: gdb-9.2/gdb/microblaze-tdep.h
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.h
++++ gdb-9.2/gdb/microblaze-tdep.h
+@@ -24,6 +24,7 @@
+ /* Microblaze architecture-specific information.  */
+ struct microblaze_gregset
+ {
++   microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+    unsigned int pregs[16];
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
deleted file mode 100644
index 7ac8f07f9f..0000000000
--- a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0040-Patch-microblaze-Adding-64-bit-MB-support.patch
+++ /dev/null
@@ -1,949 +0,0 @@
-From 4e5a4e94cb1dd61646230100f883bd27a39cd896 Mon Sep 17 00:00:00 2001
-From: Nagaraju Mekala <nmekala@xilix.com>
-Date: Thu, 31 Jan 2019 14:36:00 +0530
-Subject: [PATCH 40/40] [Patch, microblaze]: Adding 64 bit MB support
-
-Added new architecture to Microblaze 64-bit support to GDB
-
-Signed-off-by :Nagaraju Mekala <nmekala@xilix.com>
----
- bfd/archures.c                                |   2 +
- bfd/bfd-in2.h                                 |   2 +
- bfd/cpu-microblaze.c                          |  16 +-
- bfd/elf32-microblaze.c                        |   9 +
- gdb/features/Makefile                         |   3 +
- gdb/features/microblaze-core.xml              |   6 +-
- gdb/features/microblaze-with-stack-protect.c  |   4 +-
- gdb/features/microblaze.c                     |   6 +-
- gdb/features/microblaze64-core.xml            |  69 +++++++
- gdb/features/microblaze64-stack-protect.xml   |  12 ++
- .../microblaze64-with-stack-protect.c         |  79 ++++++++
- .../microblaze64-with-stack-protect.xml       |  12 ++
- gdb/features/microblaze64.c                   |  77 ++++++++
- gdb/features/microblaze64.xml                 |  11 ++
- gdb/microblaze-linux-tdep.c                   |  29 ++-
- gdb/microblaze-tdep.c                         | 176 ++++++++++++++++--
- gdb/microblaze-tdep.h                         |   9 +-
- .../microblaze-with-stack-protect.dat         |   4 +-
- 20 files changed, 504 insertions(+), 40 deletions(-)
- create mode 100644 gdb/features/microblaze64-core.xml
- create mode 100644 gdb/features/microblaze64-stack-protect.xml
- create mode 100644 gdb/features/microblaze64-with-stack-protect.c
- create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
- create mode 100644 gdb/features/microblaze64.c
- create mode 100644 gdb/features/microblaze64.xml
-
-diff --git a/bfd/archures.c b/bfd/archures.c
-index 7866c6095b5..abc1541afe6 100644
---- a/bfd/archures.c
-+++ b/bfd/archures.c
-@@ -513,6 +513,8 @@ DESCRIPTION
- .  bfd_arch_lm32,      {* Lattice Mico32.  *}
- .#define bfd_mach_lm32		1
- .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
-+.#define bfd_mach_microblaze	1
-+.#define bfd_mach_microblaze64	2
- .  bfd_arch_tilepro,   {* Tilera TILEPro.  *}
- .  bfd_arch_tilegx,    {* Tilera TILE-Gx.  *}
- .#define bfd_mach_tilepro	1
-diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
-index 91761bf6964..cc34ce0d8c3 100644
---- a/bfd/bfd-in2.h
-+++ b/bfd/bfd-in2.h
-@@ -1896,6 +1896,8 @@ enum bfd_architecture
-   bfd_arch_lm32,      /* Lattice Mico32.  */
- #define bfd_mach_lm32          1
-   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
-+#define bfd_mach_microblaze    1
-+#define bfd_mach_microblaze64  2
-   bfd_arch_tilepro,   /* Tilera TILEPro.  */
-   bfd_arch_tilegx,    /* Tilera TILE-Gx.  */
- #define bfd_mach_tilepro       1
-diff --git a/bfd/cpu-microblaze.c b/bfd/cpu-microblaze.c
-index 4b48b310c6a..a32c4a33d75 100644
---- a/bfd/cpu-microblaze.c
-+++ b/bfd/cpu-microblaze.c
-@@ -30,8 +30,8 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   64,		  		/* 32 bits in a word.  */
-   64,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
--  bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_arch_microblaze,		/* Architecture.  */
-+  bfd_mach_microblaze64,	/* 64 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-@@ -43,11 +43,11 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   0 /* Maximum offset of a reloc from the start of an insn.  */
- },
- {
--  32,				/* Bits in a word.  */
--  32,				/* Bits in an address.  */
--  8,				/* Bits in a byte.  */
-+  32,				/* 32 bits in a word.  */
-+  32,				/* 32 bits in an address.  */
-+  8,				/* 8 bits in a byte.  */
-   bfd_arch_microblaze,		/* Architecture number.  */
--  0,				/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze,		/* 32 bit Machine */
-   "microblaze",			/* Architecture name.  */
-   "MicroBlaze",			/* Printable name.  */
-   3,				/* Section align power.  */
-@@ -64,7 +64,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   32,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
-   bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze,		/* 32 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-@@ -80,7 +80,7 @@ const bfd_arch_info_type bfd_microblaze_arch[] =
-   64,		  		/* 32 bits in an address.  */
-   8,		  		/* 8 bits in a byte.  */
-   bfd_arch_microblaze, 		/* Architecture.  */
--  0,		  		/* Machine number - 0 for now.  */
-+  bfd_mach_microblaze64,	/* 64 bit Machine */
-   "microblaze",	  		/* Architecture name.  */
-   "MicroBlaze",	  		/* Printable name.  */
-   3,		  		/* Section align power.  */
-diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
-index cb7a98d307e..e4a70150190 100644
---- a/bfd/elf32-microblaze.c
-+++ b/bfd/elf32-microblaze.c
-@@ -3684,6 +3684,14 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-   return TRUE;
- }
- 
-+
-+static bfd_boolean
-+elf_microblaze_object_p (bfd *abfd)
-+{
-+  /* Set the right machine number for an s390 elf32 file.  */
-+  return bfd_default_set_arch_mach (abfd, bfd_arch_microblaze, bfd_mach_microblaze);
-+}
-+
- /* Hook called by the linker routine which adds symbols from an object
-    file.  We use it to put .comm items in .sbss, and not .bss.  */
- 
-@@ -3756,5 +3764,6 @@ microblaze_elf_add_symbol_hook (bfd *abfd,
- 
- #define elf_backend_grok_prstatus               microblaze_elf_grok_prstatus
- #define elf_backend_grok_psinfo                 microblaze_elf_grok_psinfo
-+#define elf_backend_object_p			elf_microblaze_object_p
- 
- #include "elf32-target.h"
-diff --git a/gdb/features/Makefile b/gdb/features/Makefile
-index 9a98b0542c4..438e0c5a3fe 100644
---- a/gdb/features/Makefile
-+++ b/gdb/features/Makefile
-@@ -48,6 +48,7 @@ WHICH = arm/arm-with-iwmmxt arm/arm-with-vfpv2 arm/arm-with-vfpv3 \
- 	arm/arm-with-neon \
- 	mips-linux mips-dsp-linux \
- 	microblaze-with-stack-protect \
-+	microblaze64-with-stack-protect \
- 	mips64-linux mips64-dsp-linux \
- 	nios2-linux \
- 	rs6000/powerpc-32 \
-@@ -111,7 +112,9 @@ XMLTOC = \
- 	arc-v2.xml \
- 	arc-arcompact.xml \
- 	microblaze-with-stack-protect.xml \
-+	microblaze64-with-stack-protect.xml \
- 	microblaze.xml \
-+	microblaze64.xml \
- 	mips-dsp-linux.xml \
- 	mips-linux.xml \
- 	mips64-dsp-linux.xml \
-diff --git a/gdb/features/microblaze-core.xml b/gdb/features/microblaze-core.xml
-index f272650a41b..d1f2282fd1e 100644
---- a/gdb/features/microblaze-core.xml
-+++ b/gdb/features/microblaze-core.xml
-@@ -8,7 +8,7 @@
- <!DOCTYPE feature SYSTEM "gdb-target.dtd">
- <feature name="org.gnu.gdb.microblaze.core">
-   <reg name="r0" bitsize="32" regnum="0"/>
--  <reg name="r1" bitsize="32" type="data_ptr"/>
-+  <reg name="r1" bitsize="32"/>
-   <reg name="r2" bitsize="32"/>
-   <reg name="r3" bitsize="32"/>
-   <reg name="r4" bitsize="32"/>
-@@ -39,7 +39,7 @@
-   <reg name="r29" bitsize="32"/>
-   <reg name="r30" bitsize="32"/>
-   <reg name="r31" bitsize="32"/>
--  <reg name="rpc" bitsize="32" type="code_ptr"/>
-+  <reg name="rpc" bitsize="32"/>
-   <reg name="rmsr" bitsize="32"/>
-   <reg name="rear" bitsize="32"/>
-   <reg name="resr" bitsize="32"/>
-@@ -64,4 +64,6 @@
-   <reg name="rtlbsx" bitsize="32"/>
-   <reg name="rtlblo" bitsize="32"/>
-   <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="rslr" bitsize="32"/>
-+  <reg name="rshr" bitsize="32"/>
- </feature>
-diff --git a/gdb/features/microblaze-with-stack-protect.c b/gdb/features/microblaze-with-stack-protect.c
-index b39aa198874..ab162fd2588 100644
---- a/gdb/features/microblaze-with-stack-protect.c
-+++ b/gdb/features/microblaze-with-stack-protect.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
- 
-   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_protect (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-diff --git a/gdb/features/microblaze.c b/gdb/features/microblaze.c
-index 6c86fc07700..7919ac96e62 100644
---- a/gdb/features/microblaze.c
-+++ b/gdb/features/microblaze.c
-@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
- 
-   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
-   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
-@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
--  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
-   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
- 
-   tdesc_microblaze = result;
- }
-diff --git a/gdb/features/microblaze64-core.xml b/gdb/features/microblaze64-core.xml
-new file mode 100644
-index 00000000000..b9adadfade6
---- /dev/null
-+++ b/gdb/features/microblaze64-core.xml
-@@ -0,0 +1,69 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.core">
-+  <reg name="r0" bitsize="64" regnum="0"/>
-+  <reg name="r1" bitsize="64"/>
-+  <reg name="r2" bitsize="64"/>
-+  <reg name="r3" bitsize="64"/>
-+  <reg name="r4" bitsize="64"/>
-+  <reg name="r5" bitsize="64"/>
-+  <reg name="r6" bitsize="64"/>
-+  <reg name="r7" bitsize="64"/>
-+  <reg name="r8" bitsize="64"/>
-+  <reg name="r9" bitsize="64"/>
-+  <reg name="r10" bitsize="64"/>
-+  <reg name="r11" bitsize="64"/>
-+  <reg name="r12" bitsize="64"/>
-+  <reg name="r13" bitsize="64"/>
-+  <reg name="r14" bitsize="64"/>
-+  <reg name="r15" bitsize="64"/>
-+  <reg name="r16" bitsize="64"/>
-+  <reg name="r17" bitsize="64"/>
-+  <reg name="r18" bitsize="64"/>
-+  <reg name="r19" bitsize="64"/>
-+  <reg name="r20" bitsize="64"/>
-+  <reg name="r21" bitsize="64"/>
-+  <reg name="r22" bitsize="64"/>
-+  <reg name="r23" bitsize="64"/>
-+  <reg name="r24" bitsize="64"/>
-+  <reg name="r25" bitsize="64"/>
-+  <reg name="r26" bitsize="64"/>
-+  <reg name="r27" bitsize="64"/>
-+  <reg name="r28" bitsize="64"/>
-+  <reg name="r29" bitsize="64"/>
-+  <reg name="r30" bitsize="64"/>
-+  <reg name="r31" bitsize="64"/>
-+  <reg name="rpc" bitsize="64"/>
-+  <reg name="rmsr" bitsize="32"/>
-+  <reg name="rear" bitsize="64"/>
-+  <reg name="resr" bitsize="32"/>
-+  <reg name="rfsr" bitsize="32"/>
-+  <reg name="rbtr" bitsize="64"/>
-+  <reg name="rpvr0" bitsize="32"/>
-+  <reg name="rpvr1" bitsize="32"/>
-+  <reg name="rpvr2" bitsize="32"/>
-+  <reg name="rpvr3" bitsize="32"/>
-+  <reg name="rpvr4" bitsize="32"/>
-+  <reg name="rpvr5" bitsize="32"/>
-+  <reg name="rpvr6" bitsize="32"/>
-+  <reg name="rpvr7" bitsize="32"/>
-+  <reg name="rpvr8" bitsize="64"/>
-+  <reg name="rpvr9" bitsize="64"/>
-+  <reg name="rpvr10" bitsize="32"/>
-+  <reg name="rpvr11" bitsize="32"/>
-+  <reg name="redr" bitsize="32"/>
-+  <reg name="rpid" bitsize="32"/>
-+  <reg name="rzpr" bitsize="32"/>
-+  <reg name="rtlbx" bitsize="32"/>
-+  <reg name="rtlbsx" bitsize="32"/>
-+  <reg name="rtlblo" bitsize="32"/>
-+  <reg name="rtlbhi" bitsize="32"/>
-+  <reg name="rslr" bitsize="64"/>
-+  <reg name="rshr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-stack-protect.xml b/gdb/features/microblaze64-stack-protect.xml
-new file mode 100644
-index 00000000000..9d7ea8b9fd7
---- /dev/null
-+++ b/gdb/features/microblaze64-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
-+<feature name="org.gnu.gdb.microblaze64.stack-protect">
-+  <reg name="rslr" bitsize="64"/>
-+  <reg name="rshr" bitsize="64"/>
-+</feature>
-diff --git a/gdb/features/microblaze64-with-stack-protect.c b/gdb/features/microblaze64-with-stack-protect.c
-new file mode 100644
-index 00000000000..249cb534daa
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.c
-@@ -0,0 +1,79 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze-with-stack-protect.xml */
-+
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
-+
-+struct target_desc *tdesc_microblaze64_with_stack_protect;
-+static void
-+initialize_tdesc_microblaze64_with_stack_protect (void)
-+{
-+  struct target_desc *result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64_with_stack_protect = result;
-+}
-diff --git a/gdb/features/microblaze64-with-stack-protect.xml b/gdb/features/microblaze64-with-stack-protect.xml
-new file mode 100644
-index 00000000000..0e9f01611f3
---- /dev/null
-+++ b/gdb/features/microblaze64-with-stack-protect.xml
-@@ -0,0 +1,12 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+  <xi:include href="microblaze64-stack-protect.xml"/>
-+</target>
-diff --git a/gdb/features/microblaze64.c b/gdb/features/microblaze64.c
-new file mode 100644
-index 00000000000..5d3e2c8cd91
---- /dev/null
-+++ b/gdb/features/microblaze64.c
-@@ -0,0 +1,77 @@
-+/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
-+  Original: microblaze.xml */
-+
-+#include "defs.h"
-+#include "osabi.h"
-+#include "target-descriptions.h"
-+
-+struct target_desc *tdesc_microblaze64;
-+static void
-+initialize_tdesc_microblaze64 (void)
-+{
-+  struct target_desc *result = allocate_target_description ();
-+  struct tdesc_feature *feature;
-+
-+  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
-+  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
-+  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
-+  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
-+
-+  tdesc_microblaze64 = result;
-+}
-diff --git a/gdb/features/microblaze64.xml b/gdb/features/microblaze64.xml
-new file mode 100644
-index 00000000000..515d18e65cf
---- /dev/null
-+++ b/gdb/features/microblaze64.xml
-@@ -0,0 +1,11 @@
-+<?xml version="1.0"?>
-+<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
-+
-+     Copying and distribution of this file, with or without modification,
-+     are permitted in any medium without royalty provided the copyright
-+     notice and this notice are preserved.  -->
-+
-+<!DOCTYPE target SYSTEM "gdb-target.dtd">
-+<target>
-+  <xi:include href="microblaze64-core.xml"/>
-+</target>
-diff --git a/gdb/microblaze-linux-tdep.c b/gdb/microblaze-linux-tdep.c
-index 0afb6efeba3..48459a76991 100644
---- a/gdb/microblaze-linux-tdep.c
-+++ b/gdb/microblaze-linux-tdep.c
-@@ -159,9 +159,30 @@ microblaze_linux_init_abi (struct gdbarch_info info,
- 
-   /* BFD target for core files.  */
-   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
-+          MICROBLAZE_REGISTER_SIZE=8;
-+        }
-+      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
-+    }
-   else
--    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
-+          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
-+          MICROBLAZE_REGISTER_SIZE=8;
-+        }
-+      else
-+        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
-+    }
-+
-+  switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
- 
-   /* Shared library handling.  */
-@@ -176,6 +197,8 @@ microblaze_linux_init_abi (struct gdbarch_info info,
- void
- _initialize_microblaze_linux_tdep (void)
- {
--  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
-+			  microblaze_linux_init_abi);
-+  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
- 			  microblaze_linux_init_abi);
- }
-diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
-index 98944f38d2a..5c0d6dd48ae 100644
---- a/gdb/microblaze-tdep.c
-+++ b/gdb/microblaze-tdep.c
-@@ -40,7 +40,9 @@
- #include "remote.h"
- 
- #include "features/microblaze-with-stack-protect.c"
-+#include "features/microblaze64-with-stack-protect.c"
- #include "features/microblaze.c"
-+#include "features/microblaze64.c"
- 
- /* Instruction macros used for analyzing the prologue.  */
- /* This set of instruction macros need to be changed whenever the
-@@ -79,8 +81,9 @@ static const char *microblaze_register_names[] =
- };
- 
- #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
--
-+
- static unsigned int microblaze_debug_flag = 0;
-+int MICROBLAZE_REGISTER_SIZE = 4;
- 
- static void ATTRIBUTE_PRINTF (1, 2)
- microblaze_debug (const char *fmt, ...)
-@@ -137,6 +140,7 @@ microblaze_fetch_instruction (CORE_ADDR pc)
- constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
- 
- typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
-+#if 0
- static int
- microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
- 				    struct bp_target_info *bp_tgt)
-@@ -169,6 +173,7 @@ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
- 
-   return val;
- }
-+#endif
- 
- /* Allocate and initialize a frame cache.  */
- 
-@@ -556,7 +561,6 @@ microblaze_extract_return_value (struct type *type, struct regcache *regcache,
- 				 gdb_byte *valbuf)
- {
-   gdb_byte buf[8];
--
-   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
-   switch (TYPE_LENGTH (type))
-     {
-@@ -633,7 +637,113 @@ microblaze_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
-   return (TYPE_LENGTH (type) == 16);
- }
- 
--
-+#if 0
-+static std::vector<CORE_ADDR>
-+microblaze_software_single_step (struct regcache *regcache)
-+{
-+//  struct gdbarch *arch = get_frame_arch(frame);
-+  struct gdbarch *arch = get_regcache_arch (regcache);
-+  struct address_space *aspace = get_regcache_aspace (regcache);
-+//  struct address_space *aspace = get_frame_address_space (frame);
-+  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
-+  static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
-+  static char be_breakp[] = MICROBLAZE_BREAKPOINT;
-+  enum bfd_endian byte_order = gdbarch_byte_order (arch);
-+  char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
-+  std::vector<CORE_ADDR> ret = 0;
-+
-+ /* Save the address and the values of the next_pc and the target */
-+  static struct sstep_breaks
-+  {
-+    CORE_ADDR address;
-+    bfd_boolean valid;
-+    /* Shadow contents.  */
-+    char data[INST_WORD_SIZE];
-+  } stepbreaks[2];
-+ int ii;
-+
-+  if (1)
-+    {
-+      CORE_ADDR pc;
-+      std::vector<CORE_ADDR> *next_pcs = NULL;
-+      long insn;
-+      enum microblaze_instr minstr;
-+      bfd_boolean isunsignednum;
-+      enum microblaze_instr_type insn_type;
-+      short delay_slots;
-+      int imm;
-+      bfd_boolean immfound = FALSE;
-+
-+     /* Set a breakpoint at the next instruction */
-+      /* If the current instruction is an imm, set it at the inst after */
-+      /* If the instruction has a delay slot, skip the delay slot */
-+      pc = regcache_read_pc (regcache);
-+      insn = microblaze_fetch_instruction (pc);
-+      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
-+      if (insn_type == immediate_inst)
-+	{
-+	  int rd, ra, rb;
-+	  immfound = TRUE;
-+	  minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
-+	  pc = pc + INST_WORD_SIZE;
-+	  insn = microblaze_fetch_instruction (pc);
-+	  minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
-+	}
-+      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
-+      if (insn_type != return_inst) {
-+	stepbreaks[0].valid = TRUE;
-+      } else {
-+	stepbreaks[0].valid = FALSE;
-+      }
-+
-+      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
-+      /* Now check for branch or return instructions */
-+      if (insn_type == branch_inst || insn_type == return_inst) {
-+	int limm;
-+	int lrd, lra, lrb;
-+	int ra, rb;
-+	bfd_boolean targetvalid;
-+	bfd_boolean unconditionalbranch;
-+	microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
-+	if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
-+	  ra = regcache_raw_get_unsigned(regcache, lra);
-+	else
-+	  ra = 0;
-+	if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
-+	  rb = regcache_raw_get_unsigned(regcache, lrb);
-+	else
-+	  rb = 0;
-+	stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
-+        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
-+	if (unconditionalbranch)
-+	  stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
-+	if (targetvalid && (stepbreaks[0].valid == FALSE ||
-+			    (stepbreaks[0].address != stepbreaks[1].address))
-+	                && (stepbreaks[1].address != pc)) {
-+	  stepbreaks[1].valid = TRUE;
-+	} else {
-+	  stepbreaks[1].valid = FALSE;
-+	}
-+      } else {
-+	stepbreaks[1].valid = FALSE;
-+      }
-+
-+      /* Insert the breakpoints */
-+      for (ii = 0; ii < 2; ++ii)
-+        {
-+
-+          /* ignore invalid breakpoint. */
-+          if (stepbreaks[ii].valid) {
-+            VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
-+//            insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
-+            ret = next_pcs;
-+	  }
-+	}
-+    }
-+    return ret;
-+}
-+#endif
-+
- static int dwarf2_to_reg_map[78] =
- { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
-   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
-@@ -665,24 +775,27 @@ microblaze_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg)
-   return -1;
- }
- 
-+#if 0
- static void
- microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
- {
-+
-   register_remote_g_packet_guess (gdbarch,
--                                  4 * MICROBLAZE_NUM_CORE_REGS,
--                                  tdesc_microblaze);
-+                                  4 * MICROBLAZE_NUM_REGS,
-+                                  tdesc_microblaze64);
- 
-   register_remote_g_packet_guess (gdbarch,
-                                   4 * MICROBLAZE_NUM_REGS,
--                                  tdesc_microblaze_with_stack_protect);
-+                                  tdesc_microblaze64_with_stack_protect);
- }
-+#endif
- 
- void
- microblaze_supply_gregset (const struct regset *regset,
-                         struct regcache *regcache,
-                         int regnum, const void *gregs)
- {
--  const unsigned int *regs = (const unsigned int *)gregs;
-+  const gdb_byte *regs = (const gdb_byte *) gregs;
-   if (regnum >= 0)
-     regcache->raw_supply (regnum, regs + regnum);
- 
-@@ -713,7 +826,6 @@ microblaze_iterate_over_regset_sections (struct gdbarch *gdbarch,
- }
- 
- 
--
- static struct gdbarch *
- microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- {
-@@ -727,8 +839,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   if (arches != NULL)
-     return arches->gdbarch;
-   if (tdesc == NULL)
--    tdesc = tdesc_microblaze;
--
-+    {
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
-+        {
-+    	  tdesc = tdesc_microblaze64;
-+          MICROBLAZE_REGISTER_SIZE = 8;
-+   	}
-+      else
-+    	tdesc = tdesc_microblaze;
-+    }
-   /* Check any target description for validity.  */
-   if (tdesc_has_registers (tdesc))
-     {
-@@ -736,27 +855,35 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-       int valid_p;
-       int i;
- 
--      feature = tdesc_find_feature (tdesc,
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.core");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze.core");
-       if (feature == NULL)
-         return NULL;
-       tdesc_data = tdesc_data_alloc ();
- 
-       valid_p = 1;
--      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
-+      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
-         valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
-                                             microblaze_register_names[i]);
--      feature = tdesc_find_feature (tdesc,
-+      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
-+        feature = tdesc_find_feature (tdesc,
-+                                    "org.gnu.gdb.microblaze64.stack-protect");
-+      else
-+        feature = tdesc_find_feature (tdesc,
-                                     "org.gnu.gdb.microblaze.stack-protect");
-       if (feature != NULL)
-         {
-           valid_p = 1;
-           valid_p &= tdesc_numbered_register (feature, tdesc_data,
-                                               MICROBLAZE_SLR_REGNUM,
--                                              "rslr");
-+                                              "slr");
-           valid_p &= tdesc_numbered_register (feature, tdesc_data,
-                                               MICROBLAZE_SHR_REGNUM,
--                                              "rshr");
-+                                              "shr");
-         }
- 
-       if (!valid_p)
-@@ -764,6 +891,7 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-           tdesc_data_cleanup (tdesc_data);
-           return NULL;
-         }
-+      
-     }
- 
-   /* Allocate space for the new architecture.  */
-@@ -783,7 +911,17 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
-   /* Register numbers of various important registers.  */
-   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
-   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
-+  
-+  /* Register set.  
-+  make_regs (gdbarch); */
-+  switch (info.bfd_arch_info->mach)
-+    {
-+    case bfd_mach_microblaze64:
-+      set_gdbarch_ptr_bit (gdbarch, 64);
-+    break;
-+    }
- 
-+  
-   /* Map Dwarf2 registers to GDB registers.  */
-   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
- 
-@@ -803,13 +941,15 @@ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
- 				       microblaze_breakpoint::kind_from_pc);
-   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
- 				       microblaze_breakpoint::bp_from_kind);
--  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
-+
-+//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
- 
-   set_gdbarch_frame_args_skip (gdbarch, 8);
- 
-   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
- 
--  microblaze_register_g_packet_guesses (gdbarch);
-+  //microblaze_register_g_packet_guesses (gdbarch);
- 
-   frame_base_set_default (gdbarch, &microblaze_frame_base);
- 
-@@ -840,6 +980,8 @@ _initialize_microblaze_tdep (void)
- 
-   initialize_tdesc_microblaze_with_stack_protect ();
-   initialize_tdesc_microblaze ();
-+  initialize_tdesc_microblaze64_with_stack_protect ();
-+  initialize_tdesc_microblaze64 ();
-   /* Debug this files internals.  */
-   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
- 			     &microblaze_debug_flag, _("\
-diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
-index d2112dc07e1..bd03e969b9b 100644
---- a/gdb/microblaze-tdep.h
-+++ b/gdb/microblaze-tdep.h
-@@ -27,7 +27,7 @@ struct microblaze_gregset
-    microblaze_gregset() {}
-    unsigned int gregs[32];
-    unsigned int fpregs[32];
--   unsigned int pregs[16];
-+   unsigned int pregs[18];
- };
- 
- struct gdbarch_tdep
-@@ -101,9 +101,9 @@ enum microblaze_regnum
-   MICROBLAZE_RTLBSX_REGNUM,
-   MICROBLAZE_RTLBLO_REGNUM,
-   MICROBLAZE_RTLBHI_REGNUM,
--  MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
-+  MICROBLAZE_SLR_REGNUM,
-   MICROBLAZE_SHR_REGNUM,
--  MICROBLAZE_NUM_REGS
-+  MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
- };
- 
- struct microblaze_frame_cache
-@@ -128,7 +128,8 @@ struct microblaze_frame_cache
-   struct trad_frame_saved_reg *saved_regs;
- };
- /* All registers are 32 bits.  */
--#define MICROBLAZE_REGISTER_SIZE 4
-+extern int microblaze_reg_size;
-+#define MICROBLAZE_REGISTER_SIZE microblaze_reg_size
- 
- /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
-    Only used for native debugging.  */
-diff --git a/gdb/regformats/microblaze-with-stack-protect.dat b/gdb/regformats/microblaze-with-stack-protect.dat
-index 8040a7b3fd0..450e321d49e 100644
---- a/gdb/regformats/microblaze-with-stack-protect.dat
-+++ b/gdb/regformats/microblaze-with-stack-protect.dat
-@@ -60,5 +60,5 @@ expedite:r1,rpc
- 32:rtlbsx
- 32:rtlblo
- 32:rtlbhi
--32:rslr
--32:rshr
-+32:slr
-+32:shr
--- 
-2.17.1
-
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
new file mode 100644
index 0000000000..0c72e792c5
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0041-Adding-64-bit-MB-support-Added-new-architecture-to-M.patch
@@ -0,0 +1,953 @@
+From 992c41987cb6c89bb3f9cbc0f6a2b0aa3458e4d2 Mon Sep 17 00:00:00 2001
+From: Nagaraju Mekala <nmekala@xilix.com>
+Date: Thu, 31 Jan 2019 14:36:00 +0530
+Subject: [PATCH 41/52] Adding 64 bit MB support Added new architecture to
+ Microblaze 64-bit support to GDB Signed-off-by :Nagaraju Mekala
+ <nmekala@xilix.com>
+
+Conflicts:
+	gdb/Makefile.in
+---
+ bfd/archures.c                                |   2 +
+ bfd/bfd-in2.h                                 |   2 +
+ bfd/cpu-microblaze.c                          |   8 +-
+ gas/config/tc-microblaze.c                    |  13 ++
+ gas/config/tc-microblaze.h                    |   4 +
+ gdb/features/Makefile                         |   3 +
+ gdb/features/microblaze-core.xml              |   6 +-
+ gdb/features/microblaze-stack-protect.xml     |   4 +-
+ gdb/features/microblaze-with-stack-protect.c  |   8 +-
+ gdb/features/microblaze.c                     |   6 +-
+ gdb/features/microblaze64-core.xml            |  69 ++++++
+ gdb/features/microblaze64-stack-protect.xml   |  12 +
+ .../microblaze64-with-stack-protect.c         |  79 +++++++
+ .../microblaze64-with-stack-protect.xml       |  12 +
+ gdb/features/microblaze64.c                   |  77 +++++++
+ gdb/features/microblaze64.xml                 |  11 +
+ gdb/microblaze-tdep.c                         | 207 ++++++++++++++++--
+ gdb/microblaze-tdep.h                         |   8 +-
+ .../microblaze-with-stack-protect.dat         |   4 +-
+ 19 files changed, 491 insertions(+), 44 deletions(-)
+ create mode 100644 gdb/features/microblaze64-core.xml
+ create mode 100644 gdb/features/microblaze64-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.c
+ create mode 100644 gdb/features/microblaze64-with-stack-protect.xml
+ create mode 100644 gdb/features/microblaze64.c
+ create mode 100644 gdb/features/microblaze64.xml
+
+Index: gdb-9.2/bfd/archures.c
+===================================================================
+--- gdb-9.2.orig/bfd/archures.c
++++ gdb-9.2/bfd/archures.c
+@@ -513,6 +513,8 @@ DESCRIPTION
+ .  bfd_arch_lm32,      {* Lattice Mico32.  *}
+ .#define bfd_mach_lm32		1
+ .  bfd_arch_microblaze,{* Xilinx MicroBlaze.  *}
++.#define bfd_mach_microblaze	1
++.#define bfd_mach_microblaze64	2
+ .  bfd_arch_tilepro,   {* Tilera TILEPro.  *}
+ .  bfd_arch_tilegx,    {* Tilera TILE-Gx.  *}
+ .#define bfd_mach_tilepro	1
+Index: gdb-9.2/bfd/bfd-in2.h
+===================================================================
+--- gdb-9.2.orig/bfd/bfd-in2.h
++++ gdb-9.2/bfd/bfd-in2.h
+@@ -1896,6 +1896,8 @@ enum bfd_architecture
+   bfd_arch_lm32,      /* Lattice Mico32.  */
+ #define bfd_mach_lm32          1
+   bfd_arch_microblaze,/* Xilinx MicroBlaze.  */
++#define bfd_mach_microblaze    1
++#define bfd_mach_microblaze64  2
+   bfd_arch_tilepro,   /* Tilera TILEPro.  */
+   bfd_arch_tilegx,    /* Tilera TILE-Gx.  */
+ #define bfd_mach_tilepro       1
+Index: gdb-9.2/bfd/cpu-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/cpu-microblaze.c
++++ gdb-9.2/bfd/cpu-microblaze.c
+@@ -31,7 +31,7 @@ const bfd_arch_info_type bfd_microblaze_
+   64,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze64, 	/* 64 bit Machine  */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+@@ -46,7 +46,7 @@ const bfd_arch_info_type bfd_microblaze_
+   32,				/* Bits in an address.  */
+   8,				/* Bits in a byte.  */
+   bfd_arch_microblaze,		/* Architecture number.  */
+-  0,				/* Machine number - 0 for now.  */
++  bfd_mach_microblaze,		/* 32 bit Machine  */
+   "microblaze",			/* Architecture name.  */
+   "MicroBlaze",			/* Printable name.  */
+   3,				/* Section align power.  */
+@@ -63,7 +63,7 @@ const bfd_arch_info_type bfd_microblaze_
+   32,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze,		/* 32 bit Machine */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+@@ -78,7 +78,7 @@ const bfd_arch_info_type bfd_microblaze_
+   64,		  		/* 32 bits in an address.  */
+   8,		  		/* 8 bits in a byte.  */
+   bfd_arch_microblaze, 		/* Architecture.  */
+-  0,		  		/* Machine number - 0 for now.  */
++  bfd_mach_microblaze64,	/* 64 bit Machine */
+   "microblaze",	  		/* Architecture name.  */
+   "MicroBlaze",	  		/* Printable name.  */
+   3,		  		/* Section align power.  */
+Index: gdb-9.2/gdb/features/Makefile
+===================================================================
+--- gdb-9.2.orig/gdb/features/Makefile
++++ gdb-9.2/gdb/features/Makefile
+@@ -48,6 +48,7 @@ WHICH = arm/arm-with-iwmmxt arm/arm-with
+ 	arm/arm-with-neon \
+ 	mips-linux mips-dsp-linux \
+ 	microblaze-with-stack-protect \
++	microblaze64-with-stack-protect \
+ 	mips64-linux mips64-dsp-linux \
+ 	nios2-linux \
+ 	rs6000/powerpc-32 \
+@@ -111,7 +112,9 @@ XMLTOC = \
+ 	arc-v2.xml \
+ 	arc-arcompact.xml \
+ 	microblaze-with-stack-protect.xml \
++	microblaze64-with-stack-protect.xml \
+ 	microblaze.xml \
++	microblaze64.xml \
+ 	mips-dsp-linux.xml \
+ 	mips-linux.xml \
+ 	mips64-dsp-linux.xml \
+Index: gdb-9.2/gdb/features/microblaze-core.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-core.xml
++++ gdb-9.2/gdb/features/microblaze-core.xml
+@@ -8,7 +8,7 @@
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.core">
+   <reg name="r0" bitsize="32" regnum="0"/>
+-  <reg name="r1" bitsize="32" type="data_ptr"/>
++  <reg name="r1" bitsize="32"/>
+   <reg name="r2" bitsize="32"/>
+   <reg name="r3" bitsize="32"/>
+   <reg name="r4" bitsize="32"/>
+@@ -39,7 +39,7 @@
+   <reg name="r29" bitsize="32"/>
+   <reg name="r30" bitsize="32"/>
+   <reg name="r31" bitsize="32"/>
+-  <reg name="rpc" bitsize="32" type="code_ptr"/>
++  <reg name="rpc" bitsize="32"/>
+   <reg name="rmsr" bitsize="32"/>
+   <reg name="rear" bitsize="32"/>
+   <reg name="resr" bitsize="32"/>
+@@ -64,4 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze-stack-protect.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-stack-protect.xml
++++ gdb-9.2/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="rslr" bitsize="32"/>
+-  <reg name="rshr" bitsize="32"/>
++  <reg name="slr" bitsize="32"/>
++  <reg name="shr" bitsize="32"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze-with-stack-protect.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-with-stack-protect.c
++++ gdb-9.2/gdb/features/microblaze-with-stack-protect.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze_with_stack_p
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze_with_stack_p
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_p
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result;
+ }
+Index: gdb-9.2/gdb/features/microblaze.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze.c
++++ gdb-9.2/gdb/features/microblaze.c
+@@ -14,7 +14,7 @@ initialize_tdesc_microblaze (void)
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.core");
+   tdesc_create_reg (feature, "r0", 0, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "data_ptr");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r2", 2, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r3", 3, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r4", 4, 1, NULL, 32, "int");
+@@ -45,7 +45,7 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "r29", 29, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r30", 30, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "r31", 31, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "code_ptr");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rear", 34, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
+@@ -70,6 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result;
+ }
+Index: gdb-9.2/gdb/features/microblaze64-core.xml
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64-core.xml
+@@ -0,0 +1,69 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.core">
++  <reg name="r0" bitsize="64" regnum="0"/>
++  <reg name="r1" bitsize="64"/>
++  <reg name="r2" bitsize="64"/>
++  <reg name="r3" bitsize="64"/>
++  <reg name="r4" bitsize="64"/>
++  <reg name="r5" bitsize="64"/>
++  <reg name="r6" bitsize="64"/>
++  <reg name="r7" bitsize="64"/>
++  <reg name="r8" bitsize="64"/>
++  <reg name="r9" bitsize="64"/>
++  <reg name="r10" bitsize="64"/>
++  <reg name="r11" bitsize="64"/>
++  <reg name="r12" bitsize="64"/>
++  <reg name="r13" bitsize="64"/>
++  <reg name="r14" bitsize="64"/>
++  <reg name="r15" bitsize="64"/>
++  <reg name="r16" bitsize="64"/>
++  <reg name="r17" bitsize="64"/>
++  <reg name="r18" bitsize="64"/>
++  <reg name="r19" bitsize="64"/>
++  <reg name="r20" bitsize="64"/>
++  <reg name="r21" bitsize="64"/>
++  <reg name="r22" bitsize="64"/>
++  <reg name="r23" bitsize="64"/>
++  <reg name="r24" bitsize="64"/>
++  <reg name="r25" bitsize="64"/>
++  <reg name="r26" bitsize="64"/>
++  <reg name="r27" bitsize="64"/>
++  <reg name="r28" bitsize="64"/>
++  <reg name="r29" bitsize="64"/>
++  <reg name="r30" bitsize="64"/>
++  <reg name="r31" bitsize="64"/>
++  <reg name="rpc" bitsize="64"/>
++  <reg name="rmsr" bitsize="32"/>
++  <reg name="rear" bitsize="64"/>
++  <reg name="resr" bitsize="32"/>
++  <reg name="rfsr" bitsize="32"/>
++  <reg name="rbtr" bitsize="64"/>
++  <reg name="rpvr0" bitsize="32"/>
++  <reg name="rpvr1" bitsize="32"/>
++  <reg name="rpvr2" bitsize="32"/>
++  <reg name="rpvr3" bitsize="32"/>
++  <reg name="rpvr4" bitsize="32"/>
++  <reg name="rpvr5" bitsize="32"/>
++  <reg name="rpvr6" bitsize="32"/>
++  <reg name="rpvr7" bitsize="32"/>
++  <reg name="rpvr8" bitsize="64"/>
++  <reg name="rpvr9" bitsize="64"/>
++  <reg name="rpvr10" bitsize="32"/>
++  <reg name="rpvr11" bitsize="32"/>
++  <reg name="redr" bitsize="32"/>
++  <reg name="rpid" bitsize="32"/>
++  <reg name="rzpr" bitsize="32"/>
++  <reg name="rtlbx" bitsize="32"/>
++  <reg name="rtlbsx" bitsize="32"/>
++  <reg name="rtlblo" bitsize="32"/>
++  <reg name="rtlbhi" bitsize="32"/>
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+Index: gdb-9.2/gdb/features/microblaze64-stack-protect.xml
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE feature SYSTEM "gdb-target.dtd">
++<feature name="org.gnu.gdb.microblaze64.stack-protect">
++  <reg name="slr" bitsize="64"/>
++  <reg name="shr" bitsize="64"/>
++</feature>
+Index: gdb-9.2/gdb/features/microblaze64-with-stack-protect.c
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64-with-stack-protect.c
+@@ -0,0 +1,79 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze-with-stack-protect.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64_with_stack_protect;
++static void
++initialize_tdesc_microblaze64_with_stack_protect (void)
++{
++  struct target_desc *result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "int");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64_with_stack_protect = result;
++}
+Index: gdb-9.2/gdb/features/microblaze64-with-stack-protect.xml
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64-with-stack-protect.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++  <xi:include href="microblaze64-stack-protect.xml"/>
++</target>
+Index: gdb-9.2/gdb/features/microblaze64.c
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64.c
+@@ -0,0 +1,77 @@
++/* THIS FILE IS GENERATED.  -*- buffer-read-only: t -*- vi:set ro:
++  Original: microblaze.xml */
++
++#include "defs.h"
++#include "osabi.h"
++#include "target-descriptions.h"
++
++struct target_desc *tdesc_microblaze64;
++static void
++initialize_tdesc_microblaze64 (void)
++{
++  struct target_desc *result = allocate_target_description ();
++  struct tdesc_feature *feature;
++
++  feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.core");
++  tdesc_create_reg (feature, "r0", 0, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r1", 1, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r2", 2, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r3", 3, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r4", 4, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r5", 5, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r6", 6, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r7", 7, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r8", 8, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r9", 9, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r10", 10, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r11", 11, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r12", 12, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r13", 13, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r14", 14, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r15", 15, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r16", 16, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r17", 17, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r18", 18, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r19", 19, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r20", 20, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r21", 21, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r22", 22, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r23", 23, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r24", 24, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r25", 25, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r26", 26, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r27", 27, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r28", 28, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r29", 29, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r30", 30, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "r31", 31, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpc", 32, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rmsr", 33, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rear", 34, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "resr", 35, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rfsr", 36, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rbtr", 37, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr0", 38, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr1", 39, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr2", 40, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr3", 41, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr4", 42, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr5", 43, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr6", 44, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr7", 45, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr8", 46, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr9", 47, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rpvr10", 48, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpvr11", 49, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "redr", 50, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rpid", 51, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rzpr", 52, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbx", 53, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++
++  tdesc_microblaze64 = result;
++}
+Index: gdb-9.2/gdb/features/microblaze64.xml
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze64.xml
+@@ -0,0 +1,11 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <xi:include href="microblaze64-core.xml"/>
++</target>
+Index: gdb-9.2/gdb/microblaze-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.c
++++ gdb-9.2/gdb/microblaze-tdep.c
+@@ -40,7 +40,9 @@
+ #include "remote.h"
+ 
+ #include "features/microblaze-with-stack-protect.c"
++#include "features/microblaze64-with-stack-protect.c"
+ #include "features/microblaze.c"
++#include "features/microblaze64.c"
+ 
+ /* Instruction macros used for analyzing the prologue.  */
+ /* This set of instruction macros need to be changed whenever the
+@@ -75,12 +77,13 @@ static const char *microblaze_register_n
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "rslr", "rshr"
++  "slr", "shr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
+ 
+ static unsigned int microblaze_debug_flag = 0;
++int reg_size = 4;
+ 
+ static void ATTRIBUTE_PRINTF (1, 2)
+ microblaze_debug (const char *fmt, ...)
+@@ -145,6 +148,7 @@ microblaze_store_arguments (struct regca
+   error (_("store_arguments not implemented"));
+   return sp;
+ }
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+ 				    struct bp_target_info *bp_tgt)
+@@ -154,7 +158,7 @@ microblaze_linux_memory_remove_breakpoin
+   int val;
+   int bplen;
+   gdb_byte old_contents[BREAKPOINT_MAX];
+-  struct cleanup *cleanup;
++  //struct cleanup *cleanup;
+ 
+   /* Determine appropriate breakpoint contents and size for this address.  */
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+@@ -162,7 +166,8 @@ microblaze_linux_memory_remove_breakpoin
+     error (_("Software breakpoints not implemented for this target."));
+ 
+   /* Make sure we see the memory breakpoints.  */
+-  cleanup = make_show_memory_breakpoints_cleanup (1);
++  scoped_restore 
++    cleanup = make_scoped_restore_show_memory_breakpoints (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -178,6 +183,7 @@ microblaze_linux_memory_remove_breakpoin
+   return val;
+ }
+ 
++#endif
+ /* Allocate and initialize a frame cache.  */
+ 
+ static struct microblaze_frame_cache *
+@@ -570,17 +576,16 @@ microblaze_extract_return_value (struct
+ 				 gdb_byte *valbuf)
+ {
+   gdb_byte buf[8];
+-
+   /* Copy the return value (starting) in RETVAL_REGNUM to VALBUF.  */
+   switch (TYPE_LENGTH (type))
+     {
+       case 1:	/* return last byte in the register.  */
+ 	regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-	memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 1, 1);
++	memcpy(valbuf, buf + reg_size - 1, 1);
+ 	return;
+       case 2:	/* return last 2 bytes in register.  */
+ 	regcache->cooked_read (MICROBLAZE_RETVAL_REGNUM, buf);
+-	memcpy(valbuf, buf + MICROBLAZE_REGISTER_SIZE - 2, 2);
++	memcpy(valbuf, buf + reg_size - 2, 2);
+ 	return;
+       case 4:	/* for sizes 4 or 8, copy the required length.  */
+       case 8:
+@@ -647,7 +652,119 @@ microblaze_stabs_argument_has_addr (stru
+   return (TYPE_LENGTH (type) == 16);
+ }
+ 
+-
++#if 0
++static std::vector<CORE_ADDR>
++microblaze_software_single_step (struct regcache *regcache)
++{
++//  struct gdbarch *arch = get_frame_arch(frame);
++  struct gdbarch *arch = get_regcache_arch (regcache);
++  struct address_space *aspace = get_regcache_aspace (regcache);
++//  struct address_space *aspace = get_frame_address_space (frame);
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  static char le_breakp[] = MICROBLAZE_BREAKPOINT_LE;
++  static char be_breakp[] = MICROBLAZE_BREAKPOINT;
++  enum bfd_endian byte_order = gdbarch_byte_order (arch);
++  char *breakp = byte_order == BFD_ENDIAN_BIG ? be_breakp : le_breakp;
++  std::vector<CORE_ADDR> ret = 0;
++
++ /* Save the address and the values of the next_pc and the target */
++  static struct sstep_breaks
++  {
++    CORE_ADDR address;
++    bfd_boolean valid;
++    /* Shadow contents.  */
++    char data[INST_WORD_SIZE];
++  } stepbreaks[2];
++ int ii;
++
++  if (1)
++    {
++      CORE_ADDR pc;
++      std::vector<CORE_ADDR> *next_pcs = NULL;
++      long insn;
++      enum microblaze_instr minstr;
++      bfd_boolean isunsignednum;
++      enum microblaze_instr_type insn_type;
++      short delay_slots;
++      int imm;
++      bfd_boolean immfound = FALSE;
++
++     /* Set a breakpoint at the next instruction */
++      /* If the current instruction is an imm, set it at the inst after */
++      /* If the instruction has a delay slot, skip the delay slot */
++      pc = regcache_read_pc (regcache);
++      insn = microblaze_fetch_instruction (pc);
++      minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++      if (insn_type == immediate_inst)
++	{
++	  int rd, ra, rb;
++	  immfound = TRUE;
++	  minstr = microblaze_decode_insn (insn, &rd, &ra, &rb, &imm);
++	  pc = pc + INST_WORD_SIZE;
++	  insn = microblaze_fetch_instruction (pc);
++	  minstr = get_insn_microblaze (insn, &isunsignednum, &insn_type, &delay_slots);
++	}
++      stepbreaks[0].address = pc + (delay_slots * INST_WORD_SIZE) + INST_WORD_SIZE;
++      if (insn_type != return_inst) {
++	stepbreaks[0].valid = TRUE;
++      } else {
++	stepbreaks[0].valid = FALSE;
++      }
++
++      microblaze_debug ("single-step insn_type=%x insn=%x\n", insn_type, insn);
++      /* Now check for branch or return instructions */
++      if (insn_type == branch_inst || insn_type == return_inst) {
++	int limm;
++	int lrd, lra, lrb;
++	int ra, rb;
++	bfd_boolean targetvalid;
++	bfd_boolean unconditionalbranch;
++	microblaze_decode_insn(insn, &lrd, &lra, &lrb, &limm);
++	if (lra >= 0 && lra < MICROBLAZE_NUM_REGS)
++	  ra = regcache_raw_get_unsigned(regcache, lra);
++	else
++	  ra = 0;
++	if (lrb >= 0 && lrb < MICROBLAZE_NUM_REGS)
++	  rb = regcache_raw_get_unsigned(regcache, lrb);
++	else
++	  rb = 0;
++	stepbreaks[1].address = microblaze_get_target_address (insn, immfound, imm, pc, ra, rb, &targetvalid, &unconditionalbranch);
++        microblaze_debug ("single-step uncondbr=%d targetvalid=%d target=%x\n", unconditionalbranch, targetvalid, stepbreaks[1].address);
++	if (unconditionalbranch)
++	  stepbreaks[0].valid = FALSE; /* This is a unconditional branch: will not come to the next address */
++	if (targetvalid && (stepbreaks[0].valid == FALSE ||
++			    (stepbreaks[0].address != stepbreaks[1].address))
++	                && (stepbreaks[1].address != pc)) {
++	  stepbreaks[1].valid = TRUE;
++	} else {
++	  stepbreaks[1].valid = FALSE;
++	}
++      } else {
++	stepbreaks[1].valid = FALSE;
++      }
++
++      /* Insert the breakpoints */
++      for (ii = 0; ii < 2; ++ii)
++        {
++
++          /* ignore invalid breakpoint. */
++          if (stepbreaks[ii].valid) {
++            VEC_safe_push (CORE_ADDR, next_pcs, stepbreaks[ii].address);;
++//            insert_single_step_breakpoint (arch, aspace, stepbreaks[ii].address);
++            ret = next_pcs;
++	  }
++	}
++    }
++    return ret;
++}
++#endif
++
++static void
++microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
++{
++  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
++}
++
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -682,13 +799,14 @@ microblaze_dwarf2_reg_to_regnum (struct
+ static void
+ microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+ {
++
+   register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_CORE_REGS,
+-                                  tdesc_microblaze);
++                                  4 * MICROBLAZE_NUM_REGS,
++                                  tdesc_microblaze64);
+ 
+   register_remote_g_packet_guess (gdbarch,
+                                   4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze_with_stack_protect);
++                                  tdesc_microblaze64_with_stack_protect);
+ }
+ 
+ void
+@@ -696,15 +814,15 @@ microblaze_supply_gregset (const struct
+                         struct regcache *regcache,
+                         int regnum, const void *gregs)
+ {
+-  unsigned int *regs = gregs;
++  const gdb_byte *regs = (const gdb_byte *) gregs;
+   if (regnum >= 0)
+-    regcache_raw_supply (regcache, regnum, regs + regnum);
++    regcache->raw_supply (regnum, regs + regnum);
+ 
+   if (regnum == -1) {
+     int i;
+ 
+     for (i = 0; i < 50; i++) {
+-      regcache_raw_supply (regcache, i, regs + i);
++      regcache->raw_supply (regnum, regs + i);
+     }
+   }
+ }
+@@ -755,6 +873,17 @@ microblaze_regset_from_core_section (str
+ }
+ 
+ 
++static void
++make_regs (struct gdbarch *arch)
++{
++  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
++  int mach = gdbarch_bfd_arch_info (arch)->mach;
++  
++  if (mach == bfd_mach_microblaze64)
++    {
++      set_gdbarch_ptr_bit (arch, 64);
++    }
++}
+ 
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+@@ -769,8 +898,15 @@ microblaze_gdbarch_init (struct gdbarch_
+   if (arches != NULL)
+     return arches->gdbarch;
+   if (tdesc == NULL)
+-    tdesc = tdesc_microblaze;
+-
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) 
++        {
++    	  tdesc = tdesc_microblaze64;
++          reg_size = 8;
++   	}
++      else
++    	tdesc = tdesc_microblaze;
++    }
+   /* Check any target description for validity.  */
+   if (tdesc_has_registers (tdesc))
+     {
+@@ -778,27 +914,35 @@ microblaze_gdbarch_init (struct gdbarch_
+       int valid_p;
+       int i;
+ 
+-      feature = tdesc_find_feature (tdesc,
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.core");
++      else
++        feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze.core");
+       if (feature == NULL)
+         return NULL;
+       tdesc_data = tdesc_data_alloc ();
+ 
+       valid_p = 1;
+-      for (i = 0; i < MICROBLAZE_NUM_CORE_REGS; i++)
++      for (i = 0; i < MICROBLAZE_NUM_REGS; i++)
+         valid_p &= tdesc_numbered_register (feature, tdesc_data, i,
+                                             microblaze_register_names[i]);
+-      feature = tdesc_find_feature (tdesc,
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64)
++        feature = tdesc_find_feature (tdesc,
++                                    "org.gnu.gdb.microblaze64.stack-protect");
++      else
++        feature = tdesc_find_feature (tdesc,
+                                     "org.gnu.gdb.microblaze.stack-protect");
+       if (feature != NULL)
+         {
+           valid_p = 1;
+           valid_p &= tdesc_numbered_register (feature, tdesc_data,
+                                               MICROBLAZE_SLR_REGNUM,
+-                                              "rslr");
++                                              "slr");
+           valid_p &= tdesc_numbered_register (feature, tdesc_data,
+                                               MICROBLAZE_SHR_REGNUM,
+-                                              "rshr");
++                                              "shr");
+         }
+ 
+       if (!valid_p)
+@@ -806,6 +950,7 @@ microblaze_gdbarch_init (struct gdbarch_
+           tdesc_data_cleanup (tdesc_data);
+           return NULL;
+         }
++      
+     }
+ 
+   /* Allocate space for the new architecture.  */
+@@ -825,7 +970,17 @@ microblaze_gdbarch_init (struct gdbarch_
+   /* Register numbers of various important registers.  */
+   set_gdbarch_sp_regnum (gdbarch, MICROBLAZE_SP_REGNUM); 
+   set_gdbarch_pc_regnum (gdbarch, MICROBLAZE_PC_REGNUM); 
++  
++  /* Register set.  
++  make_regs (gdbarch); */
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
++  
+   /* Map Dwarf2 registers to GDB registers.  */
+   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, microblaze_dwarf2_reg_to_regnum);
+ 
+@@ -845,13 +1000,15 @@ microblaze_gdbarch_init (struct gdbarch_
+ 				       microblaze_breakpoint::kind_from_pc);
+   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
+ 				       microblaze_breakpoint::bp_from_kind);
+-  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch, microblaze_linux_memory_remove_breakpoint);
++
++//  set_gdbarch_software_single_step (gdbarch, microblaze_software_single_step);
+ 
+   set_gdbarch_frame_args_skip (gdbarch, 8);
+ 
+   set_gdbarch_unwind_pc (gdbarch, microblaze_unwind_pc);
+ 
+-  microblaze_register_g_packet_guesses (gdbarch);
++  //microblaze_register_g_packet_guesses (gdbarch);
+ 
+   frame_base_set_default (gdbarch, &microblaze_frame_base);
+ 
+@@ -866,11 +1023,11 @@ microblaze_gdbarch_init (struct gdbarch_
+     tdesc_use_registers (gdbarch, tdesc, tdesc_data);
+   //frame_base_append_sniffer (gdbarch, microblaze_frame_sniffer);
+ 
+-  /* If we have register sets, enable the generic core file support.  */
++  /* If we have register sets, enable the generic core file support.  
+   if (tdep->gregset) {
+       set_gdbarch_regset_from_core_section (gdbarch,
+                                           microblaze_regset_from_core_section);
+-  }
++  }*/
+ 
+   return gdbarch;
+ }
+@@ -882,6 +1039,8 @@ _initialize_microblaze_tdep (void)
+ 
+   initialize_tdesc_microblaze_with_stack_protect ();
+   initialize_tdesc_microblaze ();
++  initialize_tdesc_microblaze64_with_stack_protect ();
++  initialize_tdesc_microblaze64 ();
+   /* Debug this files internals.  */
+   add_setshow_zuinteger_cmd ("microblaze", class_maintenance,
+ 			     &microblaze_debug_flag, _("\
+Index: gdb-9.2/gdb/microblaze-tdep.h
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.h
++++ gdb-9.2/gdb/microblaze-tdep.h
+@@ -27,7 +27,7 @@ struct microblaze_gregset
+    microblaze_gregset() {}
+    unsigned int gregs[32];
+    unsigned int fpregs[32];
+-   unsigned int pregs[16];
++   unsigned int pregs[18];
+ };
+ 
+ struct gdbarch_tdep
+@@ -101,9 +101,9 @@ enum microblaze_regnum
+   MICROBLAZE_RTLBSX_REGNUM,
+   MICROBLAZE_RTLBLO_REGNUM,
+   MICROBLAZE_RTLBHI_REGNUM,
+-  MICROBLAZE_SLR_REGNUM, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_SLR_REGNUM,
++  MICROBLAZE_SLR_REGNUM,
+   MICROBLAZE_SHR_REGNUM,
+-  MICROBLAZE_NUM_REGS
++  MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+ 
+ struct microblaze_frame_cache
+@@ -128,7 +128,7 @@ struct microblaze_frame_cache
+   struct trad_frame_saved_reg *saved_regs;
+ };
+ /* All registers are 32 bits.  */
+-#define MICROBLAZE_REGISTER_SIZE 4
++//#define MICROBLAZE_REGISTER_SIZE 8
+ 
+ /* MICROBLAZE_BREAKPOINT defines the breakpoint that should be used.
+    Only used for native debugging.  */
+Index: gdb-9.2/gdb/regformats/microblaze-with-stack-protect.dat
+===================================================================
+--- gdb-9.2.orig/gdb/regformats/microblaze-with-stack-protect.dat
++++ gdb-9.2/gdb/regformats/microblaze-with-stack-protect.dat
+@@ -60,5 +60,5 @@ expedite:r1,rpc
+ 32:rtlbsx
+ 32:rtlblo
+ 32:rtlbhi
+-32:rslr
+-32:rshr
++32:slr
++32:shr
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0042-porting-GDB-for-linux.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0042-porting-GDB-for-linux.patch
new file mode 100644
index 0000000000..947ac9a970
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0042-porting-GDB-for-linux.patch
@@ -0,0 +1,151 @@
+From ecccc76dd8ea2e75cc31435b5885173690b3e07a Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Thu, 12 Dec 2019 14:56:17 +0530
+Subject: [PATCH 42/52] porting GDB for linux
+
+---
+ gdb/features/microblaze-linux.xml | 12 ++++++++++
+ gdb/gdbserver/Makefile.in         |  2 ++
+ gdb/gdbserver/configure.srv       |  3 ++-
+ gdb/microblaze-linux-tdep.c       | 39 ++++++++++++++++++++++++-------
+ 4 files changed, 47 insertions(+), 9 deletions(-)
+ create mode 100644 gdb/features/microblaze-linux.xml
+
+Index: gdb-9.2/gdb/features/microblaze-linux.xml
+===================================================================
+--- /dev/null
++++ gdb-9.2/gdb/features/microblaze-linux.xml
+@@ -0,0 +1,12 @@
++<?xml version="1.0"?>
++<!-- Copyright (C) 2014-2018 Free Software Foundation, Inc.
++
++     Copying and distribution of this file, with or without modification,
++     are permitted in any medium without royalty provided the copyright
++     notice and this notice are preserved.  -->
++
++<!DOCTYPE target SYSTEM "gdb-target.dtd">
++<target>
++  <osabi>GNU/Linux</osabi>
++  <xi:include href="microblaze-core.xml"/>
++</target>
+Index: gdb-9.2/gdb/gdbserver/Makefile.in
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/Makefile.in
++++ gdb-9.2/gdb/gdbserver/Makefile.in
+@@ -659,6 +659,8 @@ gdbsupport/%.o: ../gdbsupport/%.c
+ 
+ %-generated.c: ../regformats/rs6000/%.dat | $(regdat_sh)
+ 	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $< $@
++microblaze-linux.c : $(srcdir)/../regformats/reg-microblaze.dat $(regdat_sh)
++	$(ECHO_REGDAT) $(SHELL) $(regdat_sh) $(srcdir)/../regformats/reg-microblaze.dat microblaze-linux.c
+ 
+ #
+ # Dependency tracking.
+Index: gdb-9.2/gdb/gdbserver/configure.srv
+===================================================================
+--- gdb-9.2.orig/gdb/gdbserver/configure.srv
++++ gdb-9.2/gdb/gdbserver/configure.srv
+@@ -184,8 +184,9 @@ case "${target}" in
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+ 			;;
+-  microblaze*-*-linux*)	srv_regobj=microblaze-linux.o
++  microblaze*-*-linux*)	srv_regobj="microblaze-linux.o"
+ 			srv_tgtobj="$srv_linux_obj linux-microblaze-low.o "
++			srv_xmlfiles="microblaze-linux.xml"
+ 			srv_linux_regsets=yes
+ 			srv_linux_usrregs=yes
+ 			srv_linux_thread_db=yes
+Index: gdb-9.2/gdb/microblaze-linux-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-linux-tdep.c
++++ gdb-9.2/gdb/microblaze-linux-tdep.c
+@@ -41,7 +41,7 @@
+ 
+ #ifndef REGSET_H
+ #define REGSET_H 1
+-
++int MICROBLAZE_REGISTER_SIZE=4;
+ struct gdbarch;
+ struct regcache;
+ 
+@@ -115,7 +115,7 @@ microblaze_debug (const char *fmt, ...)
+        va_end (args);
+     }
+ }
+-
++#if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch, 
+ 					   struct bp_target_info *bp_tgt)
+@@ -131,7 +131,7 @@ microblaze_linux_memory_remove_breakpoin
+   bp = gdbarch_breakpoint_from_pc (gdbarch, &addr, &bplen);
+ 
+   /* Make sure we see the memory breakpoints.  */
+-  cleanup = make_show_memory_breakpoints_cleanup (1);
++  cleanup = make_scoped_restore_show_memory_breakpoints (1);
+   val = target_read_memory (addr, old_contents, bplen);
+ 
+   /* If our breakpoint is no longer at the address, this means that the
+@@ -146,6 +146,7 @@ microblaze_linux_memory_remove_breakpoin
+   do_cleanups (cleanup);
+   return val;
+ }
++#endif
+ 
+ static void
+ microblaze_linux_sigtramp_cache (struct frame_info *next_frame,
+@@ -248,8 +249,8 @@ microblaze_linux_init_abi (struct gdbarc
+ 
+   linux_init_abi (info, gdbarch);
+ 
+-  set_gdbarch_memory_remove_breakpoint (gdbarch,
+-					microblaze_linux_memory_remove_breakpoint);
++//  set_gdbarch_memory_remove_breakpoint (gdbarch,
++//					microblaze_linux_memory_remove_breakpoint);
+ 
+   /* Shared library handling.  */
+   set_solib_svr4_fetch_link_map_offsets (gdbarch,
+@@ -261,10 +262,30 @@ microblaze_linux_init_abi (struct gdbarc
+ 
+   /* BFD target for core files.  */
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblaze");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblaze");
++    }
+   else
+-    set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    {
++      if (info.bfd_arch_info->mach == bfd_mach_microblaze64) {
++          set_gdbarch_gcore_bfd_target (gdbarch, "elf64-microblazeel");
++          MICROBLAZE_REGISTER_SIZE=8;
++        }
++      else
++        set_gdbarch_gcore_bfd_target (gdbarch, "elf32-microblazeel");
++    }
+ 
++  switch (info.bfd_arch_info->mach)
++    {
++    case bfd_mach_microblaze64:
++      set_gdbarch_ptr_bit (gdbarch, 64);
++    break;
++    }
+ 
+   /* Shared library handling.  */
+   set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target);
+@@ -278,6 +299,8 @@ microblaze_linux_init_abi (struct gdbarc
+ void
+ _initialize_microblaze_linux_tdep (void)
+ {
+-  gdbarch_register_osabi (bfd_arch_microblaze, 0, GDB_OSABI_LINUX, 
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze, GDB_OSABI_LINUX, 
++			  microblaze_linux_init_abi);
++  gdbarch_register_osabi (bfd_arch_microblaze, bfd_mach_microblaze64, GDB_OSABI_LINUX, 
+ 			  microblaze_linux_init_abi);
+ }
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0043-Binutils-security-check-is-causing-build-error-for-w.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0043-Binutils-security-check-is-causing-build-error-for-w.patch
new file mode 100644
index 0000000000..bfe57a8631
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0043-Binutils-security-check-is-causing-build-error-for-w.patch
@@ -0,0 +1,32 @@
+From 187f46b3a0d31c5b1eac0ce9ddc7c136b2d53d70 Mon Sep 17 00:00:00 2001
+From: Mahesh Bodapati <mbodapat@xilinx.com>
+Date: Mon, 11 Mar 2019 13:57:42 +0530
+Subject: [PATCH 43/52] Binutils security check is causing build error for
+ windows builds.commenting for now.
+
+---
+ bfd/elf-attrs.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+Index: gdb-9.2/bfd/elf-attrs.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf-attrs.c
++++ gdb-9.2/bfd/elf-attrs.c
+@@ -440,7 +440,8 @@ _bfd_elf_parse_attributes (bfd *abfd, El
+   /* PR 17512: file: 2844a11d.  */
+   if (hdr->sh_size == 0)
+     return;
+-  if (hdr->sh_size > bfd_get_file_size (abfd))
++#if 0
++if (hdr->sh_size > bfd_get_file_size (abfd))
+     {
+       /* xgettext:c-format */
+       _bfd_error_handler (_("%pB: error: attribute section '%pA' too big: %#llx"),
+@@ -448,6 +449,7 @@ _bfd_elf_parse_attributes (bfd *abfd, El
+       bfd_set_error (bfd_error_invalid_operation);
+       return;
+     }
++#endif
+ 
+   contents = (bfd_byte *) bfd_malloc (hdr->sh_size + 1);
+   if (!contents)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
new file mode 100644
index 0000000000..a60ed5e703
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0044-Correcting-the-register-names-from-slr-shr-to-rslr-r.patch
@@ -0,0 +1,143 @@
+From 2c3cd36f5198c5b023f3dd157ef3fa90ab5893d7 Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Thu, 19 Dec 2019 12:22:04 +0530
+Subject: [PATCH 44/52] Correcting the register names from slr & shr to rslr &
+ rshr
+
+---
+ gdb/features/microblaze-core.xml               | 4 ++--
+ gdb/features/microblaze-stack-protect.xml      | 4 ++--
+ gdb/features/microblaze-with-stack-protect.c   | 4 ++--
+ gdb/features/microblaze.c                      | 4 ++--
+ gdb/features/microblaze64-core.xml             | 4 ++--
+ gdb/features/microblaze64-stack-protect.xml    | 4 ++--
+ gdb/features/microblaze64-with-stack-protect.c | 4 ++--
+ gdb/features/microblaze64.c                    | 4 ++--
+ gdb/microblaze-tdep.c                          | 2 +-
+ 9 files changed, 17 insertions(+), 17 deletions(-)
+
+Index: gdb-9.2/gdb/features/microblaze-core.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-core.xml
++++ gdb-9.2/gdb/features/microblaze-core.xml
+@@ -64,6 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
+-  <reg name="slr" bitsize="32"/>
+-  <reg name="shr" bitsize="32"/>
++  <reg name="rslr" bitsize="32"/>
++  <reg name="rshr" bitsize="32"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze-stack-protect.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-stack-protect.xml
++++ gdb-9.2/gdb/features/microblaze-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze.stack-protect">
+-  <reg name="slr" bitsize="32"/>
+-  <reg name="shr" bitsize="32"/>
++  <reg name="rslr" bitsize="32"/>
++  <reg name="rshr" bitsize="32"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze-with-stack-protect.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze-with-stack-protect.c
++++ gdb-9.2/gdb/features/microblaze-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze_with_stack_p
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze.stack-protect");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 32, "int");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 32, "int");
+ 
+   tdesc_microblaze_with_stack_protect = result;
+ }
+Index: gdb-9.2/gdb/features/microblaze.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze.c
++++ gdb-9.2/gdb/features/microblaze.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze = result;
+ }
+Index: gdb-9.2/gdb/features/microblaze64-core.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze64-core.xml
++++ gdb-9.2/gdb/features/microblaze64-core.xml
+@@ -64,6 +64,6 @@
+   <reg name="rtlbsx" bitsize="32"/>
+   <reg name="rtlblo" bitsize="32"/>
+   <reg name="rtlbhi" bitsize="32"/>
+-  <reg name="slr" bitsize="64"/>
+-  <reg name="shr" bitsize="64"/>
++  <reg name="rslr" bitsize="64"/>
++  <reg name="rshr" bitsize="64"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze64-stack-protect.xml
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze64-stack-protect.xml
++++ gdb-9.2/gdb/features/microblaze64-stack-protect.xml
+@@ -7,6 +7,6 @@
+ 
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <feature name="org.gnu.gdb.microblaze64.stack-protect">
+-  <reg name="slr" bitsize="64"/>
+-  <reg name="shr" bitsize="64"/>
++  <reg name="rslr" bitsize="64"/>
++  <reg name="rshr" bitsize="64"/>
+ </feature>
+Index: gdb-9.2/gdb/features/microblaze64-with-stack-protect.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze64-with-stack-protect.c
++++ gdb-9.2/gdb/features/microblaze64-with-stack-protect.c
+@@ -72,8 +72,8 @@ initialize_tdesc_microblaze64_with_stack
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+ 
+   feature = tdesc_create_feature (result, "org.gnu.gdb.microblaze64.stack-protect");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze64_with_stack_protect = result;
+ }
+Index: gdb-9.2/gdb/features/microblaze64.c
+===================================================================
+--- gdb-9.2.orig/gdb/features/microblaze64.c
++++ gdb-9.2/gdb/features/microblaze64.c
+@@ -70,8 +70,8 @@ initialize_tdesc_microblaze64 (void)
+   tdesc_create_reg (feature, "rtlbsx", 54, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlblo", 55, 1, NULL, 32, "int");
+   tdesc_create_reg (feature, "rtlbhi", 56, 1, NULL, 32, "int");
+-  tdesc_create_reg (feature, "slr", 57, 1, NULL, 64, "uint64");
+-  tdesc_create_reg (feature, "shr", 58, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rslr", 57, 1, NULL, 64, "uint64");
++  tdesc_create_reg (feature, "rshr", 58, 1, NULL, 64, "uint64");
+ 
+   tdesc_microblaze64 = result;
+ }
+Index: gdb-9.2/gdb/microblaze-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.c
++++ gdb-9.2/gdb/microblaze-tdep.c
+@@ -77,7 +77,7 @@ static const char *microblaze_register_n
+   "rpvr0", "rpvr1", "rpvr2", "rpvr3", "rpvr4", "rpvr5", "rpvr6",
+   "rpvr7", "rpvr8", "rpvr9", "rpvr10", "rpvr11",
+   "redr", "rpid", "rzpr", "rtlbx", "rtlbsx", "rtlblo", "rtlbhi",
+-  "slr", "shr"
++  "rslr", "rshr"
+ };
+ 
+ #define MICROBLAZE_NUM_REGS ARRAY_SIZE (microblaze_register_names)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
new file mode 100644
index 0000000000..eac20e3d8d
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0045-Removing-the-header-gdb_assert.h-from-MB-target-file.patch
@@ -0,0 +1,21 @@
+From 38e5305c8e008ded46a9f351cd7f79c8f81df8fd Mon Sep 17 00:00:00 2001
+From: Nagaraju <nmekala@xilinx.com>
+Date: Fri, 17 Jan 2020 15:45:48 +0530
+Subject: [PATCH 45/52] Removing the header "gdb_assert.h" from MB target file
+
+---
+ gdb/microblaze-linux-tdep.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+Index: gdb-9.2/gdb/microblaze-linux-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-linux-tdep.c
++++ gdb-9.2/gdb/microblaze-linux-tdep.c
+@@ -37,7 +37,6 @@
+ #include "linux-tdep.h"
+ #include "glibc-tdep.h"
+ 
+-#include "gdb_assert.h"
+ 
+ #ifndef REGSET_H
+ #define REGSET_H 1
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
new file mode 100644
index 0000000000..de93c81e07
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0046-bfd-cpu-microblaze.c-Enhance-disassembler.patch
@@ -0,0 +1,36 @@
+From eba7561a36a20c814ca69dc42fa8b0b7f4a33510 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 10:08:53 -0800
+Subject: [PATCH 46/52] bfd/cpu-microblaze.c: Enhance disassembler
+
+See commit aebcfb76fc165795e67917cb67cf985c4dfdc577 for why this is needed.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/cpu-microblaze.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/bfd/cpu-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/cpu-microblaze.c
++++ gdb-9.2/bfd/cpu-microblaze.c
+@@ -39,7 +39,8 @@ const bfd_arch_info_type bfd_microblaze_
+   bfd_default_compatible,	/* Architecture comparison function.  */
+   bfd_default_scan,	   	/* String to architecture conversion.  */
+   bfd_arch_default_fill,	/* Default fill.  */
+-  &bfd_microblaze_arch[1]  	/* Next in list.  */
++  &bfd_microblaze_arch[1],  	/* Next in list.  */
++  0 /* Maximum offset of a reloc from the start of an insn.  */
+ },
+ {
+   32,				/* Bits in a word.  */
+@@ -71,7 +72,8 @@ const bfd_arch_info_type bfd_microblaze_
+   bfd_default_compatible,	/* Architecture comparison function.  */
+   bfd_default_scan,	   	/* String to architecture conversion.  */
+   bfd_arch_default_fill,	/* Default fill.  */
+-  &bfd_microblaze_arch[1]   	/* Next in list.  */
++  &bfd_microblaze_arch[1],   	/* Next in list.  */
++  0 /* Maximum offset of a reloc from the start of an insn.  */
+ },
+ {
+   64,		  		/* 32 bits in a word.  */
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
new file mode 100644
index 0000000000..ad63a72f07
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0047-bfd-elf64-microblaze.c-Fix-build-failures.patch
@@ -0,0 +1,84 @@
+From c848ddceb98359db1efb3ed0d1e7b5a90053dddf Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 11:02:11 -0800
+Subject: [PATCH 47/52] bfd/elf64-microblaze.c: Fix build failures
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1572,7 +1572,7 @@ microblaze_elf_relocate_section (bfd *ou
+ 			  {
+ 			    BFD_FAIL ();
+ 			    (*_bfd_error_handler)
+-			      (_("%B: probably compiled without -fPIC?"),
++			      (_("%pB: probably compiled without -fPIC?"),
+ 			       input_bfd);
+ 			    bfd_set_error (bfd_error_bad_value);
+ 			    return FALSE;
+@@ -2691,7 +2691,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+ 		/* If this is a global symbol, we count the number of
+ 		   relocations we need for this symbol.  */
+ 		if (h != NULL)
+-		  head = &h->dyn_relocs;
++		  head = &((struct elf64_mb_link_hash_entry *) h)->dyn_relocs;
+ 		else
+ 		  {
+ 		    /* Track dynamic relocs needed for local syms too.
+@@ -2911,7 +2911,7 @@ microblaze_elf_adjust_dynamic_symbol (st
+ 
+   /* If we didn't find any dynamic relocs in read-only sections, then
+      we'll be keeping the dynamic relocs and avoiding the copy reloc.  */
+-  if (!_bfd_elf_readonly_dynrelocs (h))
++  if (p == NULL)
+     {
+       h->non_got_ref = 0;
+       return TRUE;
+@@ -3096,7 +3096,7 @@ allocate_dynrelocs (struct elf_link_hash
+   else
+     h->got.offset = (bfd_vma) -1;
+ 
+-  if (h->dyn_relocs == NULL)
++  if (eh->dyn_relocs == NULL)
+     return TRUE;
+ 
+   /* In the shared -Bsymbolic case, discard space allocated for
+@@ -3113,7 +3113,7 @@ allocate_dynrelocs (struct elf_link_hash
+ 	{
+ 	  struct elf64_mb_dyn_relocs **pp;
+ 
+-	  for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
++	  for (pp = &eh->dyn_relocs; (p = *pp) != NULL; )
+ 	    {
+ 	      p->count -= p->pc_count;
+ 	      p->pc_count = 0;
+@@ -3124,7 +3124,7 @@ allocate_dynrelocs (struct elf_link_hash
+ 	    }
+ 	}
+       else if (UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
+-	h->dyn_relocs = NULL;
++	eh->dyn_relocs = NULL;
+     }
+   else
+     {
+@@ -3154,13 +3154,13 @@ allocate_dynrelocs (struct elf_link_hash
+ 	    goto keep;
+ 	}
+ 
+-      h->dyn_relocs = NULL;
++      eh->dyn_relocs = NULL;
+ 
+     keep: ;
+     }
+ 
+   /* Finally, allocate space.  */
+-  for (p = h->dyn_relocs; p != NULL; p = p->next)
++  for (p = eh->dyn_relocs; p != NULL; p = p->next)
+     {
+       asection *sreloc = elf_section_data (p->sec)->sreloc;
+       sreloc->size += p->count * sizeof (Elf64_External_Rela);
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
new file mode 100644
index 0000000000..bee50edf98
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0048-bfd-elf-microblaze.c-Remove-obsolete-entries.patch
@@ -0,0 +1,72 @@
+From 359ee1650d98372a2f2cd360a7ea9877077f6ece Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 11:23:26 -0800
+Subject: [PATCH 48/52] bfd/elf*-microblaze.c: Remove obsolete entries
+
+Replace microblaze_elf_merge_private_bfd_data with a direct call to
+_bfd_generic_verify_endian_match, this simplifies the implementation.
+
+Remove microblaze_elf_gc_sweep_hook, removed in 2017.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 29 +----------------------------
+ 1 file changed, 1 insertion(+), 28 deletions(-)
+
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1690,21 +1690,6 @@ microblaze_elf_relocate_section (bfd *ou
+   return ret;
+ }
+ 
+-/* Merge backend specific data from an object file to the output
+-   object file when linking.
+-
+-   Note: We only use this hook to catch endian mismatches.  */
+-static bfd_boolean
+-microblaze_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+-{
+-  /* Check if we have the same endianess.  */
+-  if (! _bfd_generic_verify_endian_match (ibfd, obfd))
+-    return FALSE;
+-
+-  return TRUE;
+-}
+-
+-
+ /* Calculate fixup value for reference.  */
+ 
+ static int
+@@ -2427,17 +2412,6 @@ microblaze_elf_gc_mark_hook (asection *s
+   return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
+ }
+ 
+-/* Update the got entry reference counts for the section being removed.  */
+-
+-static bfd_boolean
+-microblaze_elf_gc_sweep_hook (bfd * abfd ATTRIBUTE_UNUSED,
+-     			      struct bfd_link_info * info ATTRIBUTE_UNUSED,
+-     			      asection * sec ATTRIBUTE_UNUSED,
+-     			      const Elf_Internal_Rela * relocs ATTRIBUTE_UNUSED)
+-{
+-  return TRUE;
+-}
+-
+ /* PIC support.  */
+ 
+ #define PLT_ENTRY_SIZE 16
+@@ -3704,11 +3678,10 @@ microblaze_elf_add_symbol_hook (bfd *abf
+ #define bfd_elf64_bfd_is_local_label_name       microblaze_elf_is_local_label_name
+ #define elf_backend_relocate_section		microblaze_elf_relocate_section
+ #define bfd_elf64_bfd_relax_section             microblaze_elf_relax_section
+-#define bfd_elf64_bfd_merge_private_bfd_data    microblaze_elf_merge_private_bfd_data
++#define bfd_elf64_bfd_merge_private_bfd_data    _bfd_generic_verify_endian_match
+ #define bfd_elf64_bfd_reloc_name_lookup		microblaze_elf_reloc_name_lookup
+ 
+ #define elf_backend_gc_mark_hook		microblaze_elf_gc_mark_hook
+-#define elf_backend_gc_sweep_hook		microblaze_elf_gc_sweep_hook
+ #define elf_backend_check_relocs                microblaze_elf_check_relocs
+ #define elf_backend_copy_indirect_symbol        microblaze_elf_copy_indirect_symbol
+ #define bfd_elf64_bfd_link_hash_table_create    microblaze_elf_link_hash_table_create
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
new file mode 100644
index 0000000000..9b95e10b30
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0049-bfd-elf64-microblaze.c-Resolve-various-compiler-warn.patch
@@ -0,0 +1,42 @@
+From bee1ab76011aca029f89f98b9388aeb0390ee90f Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 12:02:25 -0800
+Subject: [PATCH 49/52] bfd/elf64-microblaze.c: Resolve various compiler
+ warnings
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ bfd/elf64-microblaze.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/bfd/elf64-microblaze.c
+===================================================================
+--- gdb-9.2.orig/bfd/elf64-microblaze.c
++++ gdb-9.2/bfd/elf64-microblaze.c
+@@ -1258,6 +1258,7 @@ microblaze_elf_relocate_section (bfd *ou
+ 	      goto dogot;
+ 	    case (int) R_MICROBLAZE_TLSLD:
+ 	      tls_type = (TLS_TLS | TLS_LD);
++              /* Fall through. */
+ 	    dogot:
+ 	    case (int) R_MICROBLAZE_GOT_64:
+ 	      {
+@@ -2569,6 +2570,7 @@ microblaze_elf_check_relocs (bfd * abfd,
+           tls_type |= (TLS_TLS | TLS_LD);
+         dogottls:
+           sec->has_tls_reloc = 1;
++          /* Fall through. */
+         case R_MICROBLAZE_GOT_64:
+           if (htab->sgot == NULL)
+             {
+@@ -2802,10 +2804,8 @@ microblaze_elf_adjust_dynamic_symbol (st
+   struct elf64_mb_link_hash_table *htab;
+   struct elf64_mb_link_hash_entry * eh;
+   struct elf64_mb_dyn_relocs *p;
+-  asection *sdynbss;
+   asection *s, *srel;
+   unsigned int power_of_two;
+-  bfd *dynobj;
+ 
+   htab = elf64_mb_hash_table (info);
+   if (htab == NULL)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
new file mode 100644
index 0000000000..ba8394ccc3
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0050-opcodes-microblaze-dis.c-Fix-compile-warnings.patch
@@ -0,0 +1,34 @@
+From a0d3bb3d528dfb75e54a0b0c6ff0d6095ba1c2c7 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 12:30:09 -0800
+Subject: [PATCH 50/52] opcodes/microblaze-dis.c: Fix compile warnings
+
+Two compiler warnings were evident, it appears both are likely real bugs.
+
+Missing type declaration for a function, and a case statement without a break.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ opcodes/microblaze-dis.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+Index: gdb-9.2/opcodes/microblaze-dis.c
+===================================================================
+--- gdb-9.2.orig/opcodes/microblaze-dis.c
++++ gdb-9.2/opcodes/microblaze-dis.c
+@@ -130,6 +130,7 @@ get_field_imm15 (struct string_buf *buf,
+   return p;
+ }
+ 
++static char *
+ get_field_imm16 (struct string_buf *buf, long instr)
+ {
+   char *p = strbuf (buf);
+@@ -327,6 +328,7 @@ print_insn_microblaze (bfd_vma memaddr,
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+ 		      get_field_r1 (&buf, inst), get_field_imm (&buf, inst));
+           /* TODO: Also print symbol */
++          break;
+ 	case INST_TYPE_RD_R1_IMMS:
+ 	  print_func (stream, "\t%s, %s, %s", get_field_rd (&buf, inst),
+ 	           get_field_r1(&buf, inst), get_field_imms (&buf, inst));
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
new file mode 100644
index 0000000000..f32901571f
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0051-gdb-microblaze-tdep.c-Remove-unused-functions.patch
@@ -0,0 +1,96 @@
+From 202c9a6e8c4e3bfe8f84d1066c8993a77e4ad4a8 Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@xilinx.com>
+Date: Thu, 3 Dec 2020 14:51:37 -0800
+Subject: [PATCH 51/52] gdb/microblaze-tdep.c: Remove unused functions
+
+Compiler warns the removed functions are not referenced anywhere.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+---
+ gdb/microblaze-tdep.c | 45 -------------------------------------------
+ 1 file changed, 45 deletions(-)
+
+Index: gdb-9.2/gdb/microblaze-tdep.c
+===================================================================
+--- gdb-9.2.orig/gdb/microblaze-tdep.c
++++ gdb-9.2/gdb/microblaze-tdep.c
+@@ -140,14 +140,6 @@ microblaze_fetch_instruction (CORE_ADDR
+ constexpr gdb_byte microblaze_break_insn[] = MICROBLAZE_BREAKPOINT;
+ 
+ typedef BP_MANIPULATION (microblaze_break_insn) microblaze_breakpoint;
+-static CORE_ADDR
+-microblaze_store_arguments (struct regcache *regcache, int nargs,
+-			    struct value **args, CORE_ADDR sp,
+-			    int struct_return, CORE_ADDR struct_addr)
+-{
+-  error (_("store_arguments not implemented"));
+-  return sp;
+-}
+ #if 0
+ static int
+ microblaze_linux_memory_remove_breakpoint (struct gdbarch *gdbarch,
+@@ -555,12 +547,6 @@ microblaze_frame_base_address (struct fr
+   return cache->base;
+ }
+ 
+-static const struct frame_unwind *
+-microblaze_frame_sniffer (struct frame_info *next_frame)
+-{
+-  return &microblaze_frame_unwind;
+-}
+-
+ static const struct frame_base microblaze_frame_base =
+ {
+   &microblaze_frame_unwind,
+@@ -759,12 +745,6 @@ microblaze_software_single_step (struct
+ }
+ #endif
+ 
+-static void
+-microblaze_write_pc (struct regcache *regcache, CORE_ADDR pc)
+-{
+-  regcache_cooked_write_unsigned (regcache, MICROBLAZE_PC_REGNUM, pc);
+-}
+-
+ static int dwarf2_to_reg_map[78] =
+ { 0  /* r0  */,   1  /* r1  */,   2  /* r2  */,   3  /* r3  */,  /*  0- 3 */
+   4  /* r4  */,   5  /* r5  */,   6  /* r6  */,   7  /* r7  */,  /*  4- 7 */
+@@ -796,19 +776,6 @@ microblaze_dwarf2_reg_to_regnum (struct
+   return -1;
+ }
+ 
+-static void
+-microblaze_register_g_packet_guesses (struct gdbarch *gdbarch)
+-{
+-
+-  register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze64);
+-
+-  register_remote_g_packet_guess (gdbarch,
+-                                  4 * MICROBLAZE_NUM_REGS,
+-                                  tdesc_microblaze64_with_stack_protect);
+-}
+-
+ void
+ microblaze_supply_gregset (const struct microblaze_gregset *gregset,
+                         struct regcache *regcache,
+@@ -873,18 +840,6 @@ microblaze_regset_from_core_section (str
+ }
+ 
+ 
+-static void
+-make_regs (struct gdbarch *arch)
+-{
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
+-  int mach = gdbarch_bfd_arch_info (arch)->mach;
+-  
+-  if (mach == bfd_mach_microblaze64)
+-    {
+-      set_gdbarch_ptr_bit (arch, 64);
+-    }
+-}
+-
+ static struct gdbarch *
+ microblaze_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
+ {
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0052-sim-Allow-microblaze-architecture.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0052-sim-Allow-microblaze-architecture.patch
new file mode 100644
index 0000000000..88095defc9
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0052-sim-Allow-microblaze-architecture.patch
@@ -0,0 +1,37 @@
+From acee53a9c9b6cbe826dacb9f02102ae4d58e36ba Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Thu, 6 Aug 2020 15:37:52 -0500
+Subject: [PATCH 52/52] sim: Allow microblaze* architecture
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ sim/configure     | 2 +-
+ sim/configure.tgt | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+Index: gdb-9.2/sim/configure
+===================================================================
+--- gdb-9.2.orig/sim/configure
++++ gdb-9.2/sim/configure
+@@ -3795,7 +3795,7 @@ subdirs="$subdirs aarch64"
+ 
+ 
+        ;;
+-   microblaze-*-*)
++   microblaze*-*-*)
+ 
+   sim_arch=microblaze
+   subdirs="$subdirs microblaze"
+Index: gdb-9.2/sim/configure.tgt
+===================================================================
+--- gdb-9.2.orig/sim/configure.tgt
++++ gdb-9.2/sim/configure.tgt
+@@ -59,7 +59,7 @@ case "${target}" in
+    mcore-*-*)
+        SIM_ARCH(mcore)
+        ;;
+-   microblaze-*-*)
++   microblaze*-*-*)
+        SIM_ARCH(microblaze)
+        ;;
+    mips*-*-*)
diff --git a/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0053-gdb-Fix-microblaze-target-compilation.patch b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0053-gdb-Fix-microblaze-target-compilation.patch
new file mode 100644
index 0000000000..01e48a02d8
--- /dev/null
+++ b/meta-xilinx/meta-microblaze/recipes-devtools/gdb/gdb/0053-gdb-Fix-microblaze-target-compilation.patch
@@ -0,0 +1,288 @@
+From e770e163e918c6065fc437687839bfbbd0137cff Mon Sep 17 00:00:00 2001
+From: Mark Hatle <mark.hatle@kernel.crashing.org>
+Date: Mon, 7 Dec 2020 12:03:25 -0600
+Subject: [PATCH] gdb: Fix microblaze target compilation
+
+Add microblaze-linux-nat.c to configure.nat
+
+Transition microblaze-linux-nat.c to use the new gdb C++ style functions.
+
+Signed-off-by: Mark Hatle <mark.hatle@kernel.crashing.org>
+---
+ gdb/configure.nat          |  5 ++
+ gdb/microblaze-linux-nat.c | 96 ++++++++++++++------------------------
+ gdb/microblaze-tdep.h      |  3 ++
+ 3 files changed, 43 insertions(+), 61 deletions(-)
+
+diff --git a/gdb/configure.nat b/gdb/configure.nat
+index fb4522f579..2b6873f9d6 100644
+--- a/gdb/configure.nat
++++ b/gdb/configure.nat
+@@ -261,6 +261,11 @@ case ${gdb_host} in
+ 		# Host: Motorola m68k running GNU/Linux.
+ 		NATDEPFILES="${NATDEPFILES} m68k-linux-nat.o"
+ 		;;
++	    microblaze)
++		# Host: Microblaze running GNU/Linux.
++		NATDEPFILES="${NATDEPFILES} microblaze-linux-nat.o"
++		NAT_CDEPS=
++		;;
+ 	    mips)
+ 		# Host: Linux/MIPS
+ 		NATDEPFILES="${NATDEPFILES} linux-nat-trad.o \
+diff --git a/gdb/microblaze-linux-nat.c b/gdb/microblaze-linux-nat.c
+index e9b8c9c522..bac4697e1e 100644
+--- a/gdb/microblaze-linux-nat.c
++++ b/gdb/microblaze-linux-nat.c
+@@ -36,13 +36,14 @@
+ #include "dwarf2-frame.h"
+ #include "osabi.h"
+ 
+-#include "gdb_assert.h"
+-#include "gdb_string.h"
++#include "gdbsupport/gdb_assert.h"
++#include <string.h>
+ #include "target-descriptions.h"
+ #include "opcodes/microblaze-opcm.h"
+ #include "opcodes/microblaze-dis.h"
+ 
+ #include "linux-nat.h"
++#include "linux-tdep.h"
+ #include "target-descriptions.h"
+ 
+ #include <sys/user.h>
+@@ -61,22 +62,17 @@
+ /* Defines ps_err_e, struct ps_prochandle.  */
+ #include "gdb_proc_service.h"
+ 
+-/* On GNU/Linux, threads are implemented as pseudo-processes, in which
+-   case we may be tracing more than one process at a time.  In that
+-   case, inferior_ptid will contain the main process ID and the
+-   individual thread (process) ID.  get_thread_id () is used to get
+-   the thread id if it's available, and the process id otherwise.  */
+-
+-int
+-get_thread_id (ptid_t ptid)
++class microblaze_linux_nat_target final : public linux_nat_target
+ {
+-  int tid = TIDGET (ptid);
+-  if (0 == tid)
+-    tid = PIDGET (ptid);
+-  return tid;
+-}
++public:
++  /* Add our register access methods.  */
++  void fetch_registers (struct regcache *, int) override;
++  void store_registers (struct regcache *, int) override;
++
++  const struct target_desc *read_description () override;
++};
+ 
+-#define GET_THREAD_ID(PTID)	get_thread_id (PTID)
++static microblaze_linux_nat_target the_microblaze_linux_nat_target;
+ 
+ /* Non-zero if our kernel may support the PTRACE_GETREGS and
+    PTRACE_SETREGS requests, for reading and writing the
+@@ -88,7 +84,6 @@ static int
+ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ {
+   int u_addr = -1;
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
+      interface, and not the wordsize of the program's ABI.  */
+   int wordsize = sizeof (long);
+@@ -105,18 +100,16 @@ microblaze_register_u_addr (struct gdbarch *gdbarch, int regno)
+ static void
+ fetch_register (struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  struct gdbarch *gdbarch = regcache->arch ();
+   /* This isn't really an address.  But ptrace thinks of it as one.  */
+   CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+   int bytes_transferred;
+-  unsigned int offset;         /* Offset of registers within the u area.  */
+-  char buf[MAX_REGISTER_SIZE];
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
+ 
+   if (regaddr == -1)
+   {
+     memset (buf, '\0', register_size (gdbarch, regno));   /* Supply zeroes */
+-    regcache_raw_supply (regcache, regno, buf);
++    regcache->raw_supply (regno, buf);
+     return;
+   }
+ 
+@@ -149,14 +142,14 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+   {
+     /* Little-endian values are always found at the left end of the
+        bytes transferred.  */
+-    regcache_raw_supply (regcache, regno, buf);
++    regcache->raw_supply (regno, buf);
+   }
+   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+   {
+     /* Big-endian values are found at the right end of the bytes
+        transferred.  */
+     size_t padding = (bytes_transferred - register_size (gdbarch, regno));
+-    regcache_raw_supply (regcache, regno, buf + padding);
++    regcache->raw_supply (regno, buf + padding);
+   }
+   else
+     internal_error (__FILE__, __LINE__,
+@@ -175,8 +168,6 @@ fetch_register (struct regcache *regcache, int tid, int regno)
+ static int
+ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   gdb_gregset_t gregset;
+ 
+   if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -204,8 +195,6 @@ fetch_all_gp_regs (struct regcache *regcache, int tid)
+ static void
+ fetch_gp_regs (struct regcache *regcache, int tid)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   int i;
+ 
+   if (have_ptrace_getsetregs)
+@@ -223,13 +212,12 @@ fetch_gp_regs (struct regcache *regcache, int tid)
+ static void
+ store_register (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
++  struct gdbarch *gdbarch = regcache->arch ();
+   /* This isn't really an address.  But ptrace thinks of it as one.  */
+   CORE_ADDR regaddr = microblaze_register_u_addr (gdbarch, regno);
+   int i;
+   size_t bytes_to_transfer;
+-  char buf[MAX_REGISTER_SIZE];
++  char buf[MICROBLAZE_MAX_REGISTER_SIZE];
+ 
+   if (regaddr == -1)
+     return;
+@@ -242,13 +230,13 @@ store_register (const struct regcache *regcache, int tid, int regno)
+   if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
+   {
+     /* Little-endian values always sit at the left end of the buffer.  */
+-    regcache_raw_collect (regcache, regno, buf);
++    regcache->raw_collect (regno, buf);
+   }
+   else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
+   {
+     /* Big-endian values sit at the right end of the buffer.  */
+     size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
+-    regcache_raw_collect (regcache, regno, buf + padding);
++    regcache->raw_collect (regno, buf + padding);
+   }
+ 
+   for (i = 0; i < bytes_to_transfer; i += sizeof (long))
+@@ -281,8 +269,6 @@ store_register (const struct regcache *regcache, int tid, int regno)
+ static int
+ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   gdb_gregset_t gregset;
+ 
+   if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
+@@ -319,8 +305,6 @@ store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
+ static void
+ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+ {
+-  struct gdbarch *gdbarch = get_regcache_arch (regcache);
+-  struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
+   int i;
+ 
+   if (have_ptrace_getsetregs)
+@@ -339,12 +323,12 @@ store_gp_regs (const struct regcache *regcache, int tid, int regno)
+    regno == -1, otherwise fetch all general registers or all floating
+    point registers depending upon the value of regno.  */
+ 
+-static void
+-microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+-				    struct regcache *regcache, int regno)
++void
++microblaze_linux_nat_target::fetch_registers (struct regcache * regcache,
++                                              int regno)
+ {
+   /* Get the thread id for the ptrace call.  */
+-  int tid = GET_THREAD_ID (inferior_ptid);
++  int tid = regcache->ptid ().lwp ();
+ 
+   if (regno == -1)
+     fetch_gp_regs (regcache, tid);
+@@ -356,12 +340,12 @@ microblaze_linux_fetch_inferior_registers (struct target_ops *ops,
+    regno == -1, otherwise store all general registers or all floating
+    point registers depending upon the value of regno.  */
+ 
+-static void
+-microblaze_linux_store_inferior_registers (struct target_ops *ops,
+-				    struct regcache *regcache, int regno)
++void
++microblaze_linux_nat_target::store_registers (struct regcache *regcache,
++                                              int regno)
+ {
+   /* Get the thread id for the ptrace call.  */
+-  int tid = GET_THREAD_ID (inferior_ptid);
++  int tid = regcache->ptid ().lwp ();
+ 
+   if (regno >= 0)
+     store_register (regcache, tid, regno);
+@@ -398,12 +382,12 @@ supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
+   /* FIXME. */
+ }
+ 
+-static const struct target_desc *
+-microblaze_linux_read_description (struct target_ops *ops)
++const struct target_desc *
++microblaze_linux_nat_target::read_description ()
+ {
+-  CORE_ADDR microblaze_hwcap = 0;
++  CORE_ADDR microblaze_hwcap = linux_get_hwcap (this);
+ 
+-  if (target_auxv_search (ops, AT_HWCAP, &microblaze_hwcap) != 1)
++  if (microblaze_hwcap != 1)
+     return NULL;
+ 
+   return NULL;
+@@ -415,17 +399,7 @@ void _initialize_microblaze_linux_nat (void);
+ void
+ _initialize_microblaze_linux_nat (void)
+ {
+-  struct target_ops *t;
+-
+-  /* Fill in the generic GNU/Linux methods.  */
+-  t = linux_target ();
+-
+-  /* Add our register access methods.  */
+-  t->to_fetch_registers = microblaze_linux_fetch_inferior_registers;
+-  t->to_store_registers = microblaze_linux_store_inferior_registers;
+-
+-  t->to_read_description = microblaze_linux_read_description;
+-
+   /* Register the target.  */
+-  linux_nat_add_target (t);
++  linux_target = &the_microblaze_linux_nat_target;
++  add_inf_child_target (&the_microblaze_linux_nat_target);
+ }
+diff --git a/gdb/microblaze-tdep.h b/gdb/microblaze-tdep.h
+index c0fc900733..c777d93a95 100644
+--- a/gdb/microblaze-tdep.h
++++ b/gdb/microblaze-tdep.h
+@@ -106,6 +106,9 @@ enum microblaze_regnum
+   MICROBLAZE_NUM_REGS, MICROBLAZE_NUM_CORE_REGS = MICROBLAZE_NUM_REGS
+ };
+ 
++/* Big enough to hold the size of the largest register in bytes.  */
++#define MICROBLAZE_MAX_REGISTER_SIZE   64
++
+ struct microblaze_frame_cache
+ {
+   /* Base address.  */
+-- 
+2.17.1
+
diff --git a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf b/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf
index e9e0412b7e..08c2d1c65a 100644
--- a/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf
+++ b/meta-xilinx/meta-xilinx-bsp/conf/machine/aarch64-tc.conf
@@ -23,7 +23,7 @@ DEFAULTTUNE = "cortexa72-cortexa53"
 DEFAULTTUNE_virtclass-multilib-libilp32 = "cortexa72-cortexa53-ilp32"
 
 AVAILTUNES += "cortexa72-cortexa53-ilp32"
-ARMPKGARCH_tune-cortexa72-cortexa53-ilp32 = "${ARMPKGARCH_tune-cortexa72-cortexa53}_ilp32"
+ARMPKGARCH_tune-cortexa72-cortexa53-ilp32 = "${ARMPKGARCH_tune-cortexa72-cortexa53}-ilp32"
 TUNE_FEATURES_tune-cortexa72-cortexa53-ilp32 = "${TUNE_FEATURES_tune-cortexa72-cortexa53} ilp32"
 PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53-ilp32 = "${PACKAGE_EXTRA_ARCHS_tune-cortexa72-cortexa53} cortexa72-cortexa53-ilp32"
 BASE_LIB_tune-cortexa72-cortexa53-ilp32 = "lib/ilp32"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb
index f3058a9ae4..314b293ab5 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-kernel/linux/linux-xlnx_2020.2.bb
@@ -3,3 +3,12 @@ SRCREV ?= "62ea514294a0c9a80455e51f1f4de36e66e8c546"
 
 include linux-xlnx.inc
 
+FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"
+SRC_URI_append = " \
+       file://perf-fix-build-with-binutils.patch \
+       file://0001-perf-bench-Share-some-global-variables-to-fix-build-.patch \
+       file://0001-perf-tests-bp_account-Make-global-variable-static.patch \
+       file://0001-perf-cs-etm-Move-definition-of-traceid_list-global-v.patch \
+       file://0001-libtraceevent-Fix-build-with-binutils-2.35.patch \
+"
+
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0065-microblaze-multilib-hack.patch b/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0065-microblaze-multilib-hack.patch
deleted file mode 100644
index af8ebf3be6..0000000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-microblaze/gcc/gcc-9/0065-microblaze-multilib-hack.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-Microblaze Mulitlib hack
-
-Based on the patch:
-
-From c2081c51db589471ea713870c72f13999abda815 Mon Sep 17 00:00:00 2001
-From: Khem Raj <raj.khem@gmail.com>
-Date: Fri, 29 Mar 2013 09:10:06 +0400
-Subject: [PATCH 04/36] 64-bit multilib hack.
-
-GCC has internal multilib handling code but it assumes a very specific rigid directory
-layout. The build system implementation of multilib layout is very generic and allows
-complete customisation of the library directories.
-
-This patch is a partial solution to allow any custom directories to be passed into gcc
-and handled correctly. It forces gcc to use the base_libdir (which is the current
-directory, "."). We need to do this for each multilib that is configured as we don't
-know which compiler options may be being passed into the compiler. Since we have a compiler
-per mulitlib at this point that isn't an issue.
-
-The one problem is the target compiler is only going to work for the default multlilib at
-this point. Ideally we'd figure out which multilibs were being enabled with which paths
-and be able to patch these entries with a complete set of correct paths but this we
-don't have such code at this point. This is something the target gcc recipe should do
-and override these platform defaults in its build config.
-
-Do same for riscv64 and aarch64
-
-RP 15/8/11
-
-Upstream-Status: Inappropriate[OE-Specific]
-
-Signed-off-by: Khem Raj <raj.khem@gmail.com>
-Signed-off-by: Elvis Dowson <elvis.dowson@gmail.com>
-Signed-off-by: Mark Hatle <mark.hatle@windriver.com>
-Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
-
-Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze
-===================================================================
---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze
-+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze
-@@ -1,5 +1,6 @@
- MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
--MULTILIB_DIRNAMES = m64 bs le m mh
-+#MULTILIB_DIRNAMES = m64 bs le m mh
-+MULTILIB_DIRNAMES = . . . . .
- MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *m64
- MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
-Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
-===================================================================
---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze-linux
-+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze-linux
-@@ -1,3 +1,4 @@
- MULTILIB_OPTIONS = mxl-barrel-shift mno-xl-soft-mul mxl-multiply-high
--MULTILIB_DIRNAMES = bs m mh
-+#MULTILIB_DIRNAMES = bs m mh
-+MULTILIB_DIRNAMES = . . .
- MULTILIB_EXCEPTIONS = *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb
deleted file mode 100644
index d14ec53e3d..0000000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/ocl-icd/ocl-icd_git.bb
+++ /dev/null
@@ -1,19 +0,0 @@
-SUMMARY = "OpenCL ICD library"
-DESCRIPTION = "Open Source alternative to vendor specific OpenCL ICD loaders."
-
-# The LICENSE is BSD 2-Clause "Simplified" License
-LICENSE = "BSD-2-Clause"
-LIC_FILES_CHKSUM = "file://COPYING;md5=232257bbf7320320725ca9529d3782ab"
-
-SRC_URI = "git://github.com/OCL-dev/ocl-icd.git;protocol=https"
-
-PV = "2.2.12+git${SRCPV}"
-SRCREV = "af79aebe4649f30dbd711c1bf6fc661eac6e5f01"
-
-S = "${WORKDIR}/git"
-
-inherit autotools
-
-DEPENDS = "ruby-native"
-
-BBCLASSEXTEND = "native"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb
deleted file mode 100644
index 9af4442da1..0000000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/opencl-clhpp/opencl-clhpp_git.bb
+++ /dev/null
@@ -1,29 +0,0 @@
-SUMMARY  = "Host API C++ bindings"
-DESCRIPTION = "OpenCL compute API headers C++ bindings from Khronos Group"
-LICENSE  = "Khronos"
-LIC_FILES_CHKSUM = "file://LICENSE.txt;md5=7e4a01f0c56b39419aa287361a82df00"
-SECTION = "base"
-
-SRC_URI = "git://github.com/KhronosGroup/OpenCL-CLHPP.git;protocol=https"
-
-PV = "2.0.10+git${SRCPV}"
-SRCREV = "acd6972bc65845aa28bd9f670dec84cbf8b760f3"
-
-S = "${WORKDIR}/git"
-
-do_configure () {
-:
-}
-
-# Only cl2.hpp is necessary.
-# Base on the repo, Directly input_cl2.hpp copied as cl2.hpp
-do_compile () {
-:
-}
-
-do_install () {
-	install -d ${D}${includedir}/CL/
-	install -m 0644 ${S}/input_cl2.hpp ${D}${includedir}/CL/cl2.hpp
-}
-
-ALLOW_EMPTY_${PN} = "1"
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt/0001-Replace-boost-detail-endian.hpp-with-boost-predef-ot.patch b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt/0001-Replace-boost-detail-endian.hpp-with-boost-predef-ot.patch
deleted file mode 100644
index 2ad7f01a21..0000000000
--- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt/0001-Replace-boost-detail-endian.hpp-with-boost-predef-ot.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From aa556b2142b8d6c62c457f82f4470430e9fe80e7 Mon Sep 17 00:00:00 2001
-From: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
-Date: Thu, 29 Oct 2020 15:28:06 -0700
-Subject: [PATCH] Replace boost/detail/endian.hpp with
- boost/predef/other/endian.h
-
-The use of BOOST_*_ENDIAN and BOOST_BYTE_ORDER is deprecated. Include
-<boost/predef/other/endian.h> and use __BYTE_ORDER and1234
-
-Signed-off-by: Sai Hari Chandana Kalluri <chandana.kalluri@xilinx.com>
----
- runtime_src/core/common/api/xrt_kernel.cpp | 8 ++++----
- runtime_src/xocl/core/kernel.cpp           | 4 ++--
- 2 files changed, 6 insertions(+), 6 deletions(-)
-
-diff --git a/runtime_src/core/common/api/xrt_kernel.cpp b/runtime_src/core/common/api/xrt_kernel.cpp
-index 1025e9d..1fb7caf 100644
---- a/runtime_src/core/common/api/xrt_kernel.cpp
-+++ b/runtime_src/core/common/api/xrt_kernel.cpp
-@@ -48,7 +48,7 @@
- #include <cstdlib>
- using namespace std::chrono_literals;
- 
--#include <boost/detail/endian.hpp>
-+#include <boost/predef/other/endian.h>
- 
- #ifdef _WIN32
- # pragma warning( disable : 4244 4267 4996)
-@@ -464,7 +464,7 @@ class argument
-     virtual std::vector<uint32_t>
-     get_value(std::va_list* args) const
-     {
--      static_assert(BOOST_BYTE_ORDER==1234,"Big endian detected");
-+      static_assert(__BYTE_ORDER==1234,"Big endian detected");
- 
-       HostType value = va_arg(*args, VaArgType);
-       return value_to_uint32_vector(value);
-@@ -485,7 +485,7 @@ class argument
-     virtual std::vector<uint32_t>
-     get_value(std::va_list* args) const
-     {
--      static_assert(BOOST_BYTE_ORDER==1234,"Big endian detected");
-+      static_assert(__BYTE_ORDER==1234,"Big endian detected");
- 
-       HostType* value = va_arg(*args, VaArgType*);
-       return value_to_uint32_vector(value, size);
-@@ -507,7 +507,7 @@ class argument
-     virtual std::vector<uint32_t>
-     get_value(std::va_list* args) const
-     {
--      static_assert(BOOST_BYTE_ORDER==1234,"Big endian detected");
-+      static_assert(__BYTE_ORDER==1234,"Big endian detected");
-       if (xrt_core::config::get_xrt_bo()) {
-         auto bo = va_arg(*args, xrtBufferHandle);
-         return value_to_uint32_vector(xrt_core::bo::address(bo));
-diff --git a/runtime_src/xocl/core/kernel.cpp b/runtime_src/xocl/core/kernel.cpp
-index f4f7edf..ec71c7e 100644
---- a/runtime_src/xocl/core/kernel.cpp
-+++ b/runtime_src/xocl/core/kernel.cpp
-@@ -21,7 +21,7 @@
- #include "compute_unit.h"
- #include "core/common/xclbin_parser.h"
- 
--#include <boost/detail/endian.hpp>
-+#include <boost/predef/other/endian.h>
- 
- #include <sstream>
- #include <iostream>
-@@ -130,7 +130,7 @@ void
- kernel::scalar_argument::
- set(size_t size, const void* cvalue)
- {
--  static_assert(BOOST_BYTE_ORDER==1234,"Big endian detected");
-+  static_assert(__BYTE_ORDER==1234,"Big endian detected");
- 
-   if (size != m_sz)
-     throw error(CL_INVALID_ARG_SIZE,"Invalid scalar argument size, expected "
--- 
-2.7.4
-
diff --git a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
index e814f11e8c..97a7a40126 100644
--- a/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
+++ b/meta-xilinx/meta-xilinx-bsp/recipes-xrt/xrt/xrt_git.bb
@@ -14,8 +14,6 @@ REPO ?= "git://github.com/Xilinx/XRT.git;protocol=https"
 BRANCHARG = "${@['nobranch=1', 'branch=${BRANCH}'][d.getVar('BRANCH', True) != '']}"
 SRC_URI = "${REPO};${BRANCHARG}"
 
-FILESEXTRAPATHS_prepend := "${THISDIR}/xrt:"
-SRC_URI_append = " file://0001-Replace-boost-detail-endian.hpp-with-boost-predef-ot.patch"
 PV = "202020.2.8.0"
 SRCREV ?= "f19a872233fbfe2eb933f25fa3d9a780ced774e5"
 
diff --git a/meta-xilinx/meta-xilinx-standalone/classes/esw.bbclass b/meta-xilinx/meta-xilinx-standalone/classes/esw.bbclass
index 565b371276..1f7e35f424 100644
--- a/meta-xilinx/meta-xilinx-standalone/classes/esw.bbclass
+++ b/meta-xilinx/meta-xilinx-standalone/classes/esw.bbclass
@@ -15,8 +15,8 @@ SRC_URI = "${REPO};branch=${BRANCH}"
 
 SRCREV_FORMAT = "src_decouple"
 
-S = "${WORKDIR}/git/"
-B = "${WORKDIR}/build/"
+S = "${WORKDIR}/git"
+B = "${WORKDIR}/build"
 OECMAKE_SOURCEPATH = "${S}/${ESW_COMPONENT_SRC}"
 
 SPECFILE_PATH_arm = "${S}/scripts/specs/arm/Xilinx.spec"
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.%.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.%.bbappend
new file mode 100644
index 0000000000..646d0e9a9f
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.%.bbappend
@@ -0,0 +1,12 @@
+COMPATIBLE_HOST = ".*-elf"
+COMPATIBLE_HOST_arm = "[^-]*-[^-]*-eabi"
+
+# When building multiple, we need to depend on the multilib newlib
+DEPENDS_append_xilinx-standalone = " ${MLPREFIX}newlib"
+
+EXTRA_OECONF_append_xilinx-standalone = " \
+	--enable-newlib-io-c99-formats \
+	--enable-newlib-io-long-long \
+	--enable-newlib-io-float \
+	--enable-newlib-io-long-double \
+"
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.1.0.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.1.0.bbappend
deleted file mode 100644
index b2245022e3..0000000000
--- a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/libgloss_3.1.0.bbappend
+++ /dev/null
@@ -1,13 +0,0 @@
-COMPATIBLE_HOST = ".*-elf"
-COMPATIBLE_HOST_arm = "[^-]*-[^-]*-eabi"
-
-# When building multiple, we need to depend on the multilib newlib
-DEPENDS_append_xilinx-standalone = " ${MLPREFIX}newlib"
-
-EXTRA_OECONF_append_xilinx-standalone = " \
-	--enable-newlib-io-c99-formats \
-	--enable-newlib-io-long-long \
-	--enable-newlib-io-float \
-	--enable-newlib-io-long-double \
-	--disable-newlib-supplied-syscalls \
-"
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.%.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.%.bbappend
new file mode 100644
index 0000000000..90522cfbc6
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.%.bbappend
@@ -0,0 +1,20 @@
+COMPATIBLE_HOST = ".*-elf"
+COMPATIBLE_HOST_arm = "[^-]*-[^-]*-eabi"
+
+EXTRA_OECONF_append_xilinx-standalone = " \
+	--enable-newlib-io-c99-formats \
+	--enable-newlib-io-long-long \
+	--enable-newlib-io-float \
+	--enable-newlib-io-long-double \
+"
+
+# Avoid trimmping CCARGS from CC by newlib configure
+do_configure_prepend_xilinx-standalone(){
+    export CC_FOR_TARGET="${CC}"
+}
+
+# Fix for multilib newlib installations
+do_install_prepend_xilinx-standalone() {
+        mkdir -p $(dirname ${D}${libdir})
+        mkdir -p $(dirname ${D}${includedir})
+}
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.1.0.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.1.0.bbappend
deleted file mode 100644
index 536a23a1a4..0000000000
--- a/meta-xilinx/meta-xilinx-standalone/recipes-core/newlib/newlib_3.1.0.bbappend
+++ /dev/null
@@ -1,21 +0,0 @@
-COMPATIBLE_HOST = ".*-elf"
-COMPATIBLE_HOST_arm = "[^-]*-[^-]*-eabi"
-
-EXTRA_OECONF_append_xilinx-standalone = " \
-	--enable-newlib-io-c99-formats \
-	--enable-newlib-io-long-long \
-	--enable-newlib-io-float \
-	--enable-newlib-io-long-double \
-	--disable-newlib-supplied-syscalls \
-"
-
-# Avoid trimmping CCARGS from CC by newlib configure
-do_configure_prepend_xilinx-standalone(){
-    export CC_FOR_TARGET="${CC}"
-}
-
-# Fix for multilib newlib installations
-do_install_prepend_xilinx-standalone() {
-        mkdir -p $(dirname ${D}${libdir})
-        mkdir -p $(dirname ${D}${includedir})
-}
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-10/additional-microblaze-multilibs.patch b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-10/additional-microblaze-multilibs.patch
new file mode 100644
index 0000000000..3d520d0f9c
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-10/additional-microblaze-multilibs.patch
@@ -0,0 +1,86 @@
+Change the multilib settings to match the expectations of Vitis and related.
+
+The multilib list is as follows:
+
+.;
+le;@mlittle-endian
+bs;@mxl-barrel-shift
+p;@mxl-pattern-compare
+m;@mno-xl-soft-mul
+fpd;@mhard-float
+m/fpd;@mno-xl-soft-mul@mhard-float
+p/m;@mxl-pattern-compare@mno-xl-soft-mul
+p/fpd;@mxl-pattern-compare@mhard-float
+p/m/fpd;@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+bs/p;@mxl-barrel-shift@mxl-pattern-compare
+bs/m;@mxl-barrel-shift@mno-xl-soft-mul
+bs/fpd;@mxl-barrel-shift@mhard-float
+bs/m/fpd;@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
+bs/p/m;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
+bs/p/fpd;@mxl-barrel-shift@mxl-pattern-compare@mhard-float
+bs/p/m/fpd;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+le/m64;@mlittle-endian@m64
+le/bs;@mlittle-endian@mxl-barrel-shift
+le/p;@mlittle-endian@mxl-pattern-compare
+le/m;@mlittle-endian@mno-xl-soft-mul
+le/fpd;@mlittle-endian@mhard-float
+le/m/fpd;@mlittle-endian@mno-xl-soft-mul@mhard-float
+le/p/m;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul
+le/p/fpd;@mlittle-endian@mxl-pattern-compare@mhard-float
+le/p/m/fpd;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+le/bs/p;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare
+le/bs/m;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul
+le/bs/fpd;@mlittle-endian@mxl-barrel-shift@mhard-float
+le/bs/m/fpd;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
+le/bs/p/m;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
+le/bs/p/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mhard-float
+le/bs/p/m/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+le/m64/bs;@mlittle-endian@m64@mxl-barrel-shift
+le/m64/p;@mlittle-endian@m64@mxl-pattern-compare
+le/m64/m;@mlittle-endian@m64@mno-xl-soft-mul
+le/m64/fpd;@mlittle-endian@m64@mhard-float
+le/m64/m/fpd;@mlittle-endian@m64@mno-xl-soft-mul@mhard-float
+le/m64/p/m;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul
+le/m64/p/fpd;@mlittle-endian@m64@mxl-pattern-compare@mhard-float
+le/m64/p/m/fpd;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+le/m64/bs/p;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare
+le/m64/bs/m;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul
+le/m64/bs/fpd;@mlittle-endian@m64@mxl-barrel-shift@mhard-float
+le/m64/bs/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
+le/m64/bs/p/m;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
+le/m64/bs/p/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mhard-float
+le/m64/bs/p/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
+
+As part of this the order of the multilibs was changes from upstream to make
+it easier to avoid big-endian m64, which is not supported by the toolchain.
+
+Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
+
+Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze
+===================================================================
+--- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze
++++ gcc-9.2.0/gcc/config/microblaze/t-microblaze
+@@ -1,17 +1,11 @@
+-MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
+-#MULTILIB_DIRNAMES = m64 bs le m mh
+-MULTILIB_DIRNAMES = . . . . .
+-MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
+-MULTILIB_EXCEPTIONS += *m64
+-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
+-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
+-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
+-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
+-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
+-MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
++MULTILIB_OPTIONS = mlittle-endian m64 mxl-barrel-shift mxl-pattern-compare mno-xl-soft-mul mhard-float
++MULTILIB_DIRNAMES = le m64 bs p m fpd
++MULTILIB_EXCEPTIONS = mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
+ MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
+-MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
++MULTILIB_EXCEPTIONS += *mxl-pattern-compare*/*mxl-multiply-high*
++# Big endian m64 is not supported
++MULTILIB_EXCEPTIONS += m64*
+ 
+ # Extra files
+ microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-9/additional-microblaze-multilibs.patch b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-9/additional-microblaze-multilibs.patch
deleted file mode 100644
index 3d520d0f9c..0000000000
--- a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-9/additional-microblaze-multilibs.patch
+++ /dev/null
@@ -1,86 +0,0 @@
-Change the multilib settings to match the expectations of Vitis and related.
-
-The multilib list is as follows:
-
-.;
-le;@mlittle-endian
-bs;@mxl-barrel-shift
-p;@mxl-pattern-compare
-m;@mno-xl-soft-mul
-fpd;@mhard-float
-m/fpd;@mno-xl-soft-mul@mhard-float
-p/m;@mxl-pattern-compare@mno-xl-soft-mul
-p/fpd;@mxl-pattern-compare@mhard-float
-p/m/fpd;@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-bs/p;@mxl-barrel-shift@mxl-pattern-compare
-bs/m;@mxl-barrel-shift@mno-xl-soft-mul
-bs/fpd;@mxl-barrel-shift@mhard-float
-bs/m/fpd;@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
-bs/p/m;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
-bs/p/fpd;@mxl-barrel-shift@mxl-pattern-compare@mhard-float
-bs/p/m/fpd;@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-le/m64;@mlittle-endian@m64
-le/bs;@mlittle-endian@mxl-barrel-shift
-le/p;@mlittle-endian@mxl-pattern-compare
-le/m;@mlittle-endian@mno-xl-soft-mul
-le/fpd;@mlittle-endian@mhard-float
-le/m/fpd;@mlittle-endian@mno-xl-soft-mul@mhard-float
-le/p/m;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul
-le/p/fpd;@mlittle-endian@mxl-pattern-compare@mhard-float
-le/p/m/fpd;@mlittle-endian@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-le/bs/p;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare
-le/bs/m;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul
-le/bs/fpd;@mlittle-endian@mxl-barrel-shift@mhard-float
-le/bs/m/fpd;@mlittle-endian@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
-le/bs/p/m;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
-le/bs/p/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mhard-float
-le/bs/p/m/fpd;@mlittle-endian@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-le/m64/bs;@mlittle-endian@m64@mxl-barrel-shift
-le/m64/p;@mlittle-endian@m64@mxl-pattern-compare
-le/m64/m;@mlittle-endian@m64@mno-xl-soft-mul
-le/m64/fpd;@mlittle-endian@m64@mhard-float
-le/m64/m/fpd;@mlittle-endian@m64@mno-xl-soft-mul@mhard-float
-le/m64/p/m;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul
-le/m64/p/fpd;@mlittle-endian@m64@mxl-pattern-compare@mhard-float
-le/m64/p/m/fpd;@mlittle-endian@m64@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-le/m64/bs/p;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare
-le/m64/bs/m;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul
-le/m64/bs/fpd;@mlittle-endian@m64@mxl-barrel-shift@mhard-float
-le/m64/bs/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mno-xl-soft-mul@mhard-float
-le/m64/bs/p/m;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul
-le/m64/bs/p/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mhard-float
-le/m64/bs/p/m/fpd;@mlittle-endian@m64@mxl-barrel-shift@mxl-pattern-compare@mno-xl-soft-mul@mhard-float
-
-As part of this the order of the multilibs was changes from upstream to make
-it easier to avoid big-endian m64, which is not supported by the toolchain.
-
-Signed-off-by: Mark Hatle <mark.hatle@xilinx.com>
-
-Index: gcc-9.2.0/gcc/config/microblaze/t-microblaze
-===================================================================
---- gcc-9.2.0.orig/gcc/config/microblaze/t-microblaze
-+++ gcc-9.2.0/gcc/config/microblaze/t-microblaze
-@@ -1,17 +1,11 @@
--MULTILIB_OPTIONS = m64 mxl-barrel-shift mlittle-endian mno-xl-soft-mul mxl-multiply-high
--#MULTILIB_DIRNAMES = m64 bs le m mh
--MULTILIB_DIRNAMES = . . . . .
--MULTILIB_EXCEPTIONS = *m64/mxl-multiply-high mxl-multiply-high
--MULTILIB_EXCEPTIONS += *m64
--MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift
--MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
--MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul
--MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul
--MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mno-xl-soft-mul/mxl-multiply-high
--MULTILIB_EXCEPTIONS += *m64/mno-xl-soft-mul/mxl-multiply-high
-+MULTILIB_OPTIONS = mlittle-endian m64 mxl-barrel-shift mxl-pattern-compare mno-xl-soft-mul mhard-float
-+MULTILIB_DIRNAMES = le m64 bs p m fpd
-+MULTILIB_EXCEPTIONS = mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mxl-barrel-shift/mxl-multiply-high mxl-multiply-high
- MULTILIB_EXCEPTIONS += *mlittle-endian/mxl-multiply-high mxl-multiply-high
--MULTILIB_EXCEPTIONS += *m64/mxl-barrel-shift/mlittle-endian/mxl-multiply-high
-+MULTILIB_EXCEPTIONS += *mxl-pattern-compare*/*mxl-multiply-high*
-+# Big endian m64 is not supported
-+MULTILIB_EXCEPTIONS += m64*
- 
- # Extra files
- microblaze-c.o: $(srcdir)/config/microblaze/microblaze-c.c \
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_10.%.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_10.%.bbappend
new file mode 100644
index 0000000000..e1876700f2
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_10.%.bbappend
@@ -0,0 +1,7 @@
+COMPATIBLE_HOST = "${HOST_SYS}"
+
+# Add MicroBlaze Patches (only when using MicroBlaze)
+FILESEXTRAPATHS_append_microblaze_xilinx-standalone := ":${THISDIR}/gcc-10"
+SRC_URI_append_microblaze_xilinx-standalone = " \
+        file://additional-microblaze-multilibs.patch \
+"
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_9.%.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_9.%.bbappend
deleted file mode 100644
index 6a4a8c5a37..0000000000
--- a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/gcc-source_9.%.bbappend
+++ /dev/null
@@ -1,7 +0,0 @@
-COMPATIBLE_HOST = "${HOST_SYS}"
-
-# Add MicroBlaze Patches (only when using MicroBlaze)
-FILESEXTRAPATHS_append_microblaze_xilinx-standalone := ":${THISDIR}/gcc-9"
-SRC_URI_append_microblaze_xilinx-standalone = " \
-        file://additional-microblaze-multilibs.patch \
-"
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/libgcc_%.bbappend b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/libgcc_%.bbappend
index e80b0b79f4..17529a0396 100644
--- a/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/libgcc_%.bbappend
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-devtools/gcc/libgcc_%.bbappend
@@ -13,6 +13,9 @@ standalone_fixup () {
 			ln -s $each $(basename $each)
 		done
 	)
+
+	# Apparently we can end up with an empty /lib occasionally
+        find ${D}/lib -type d | sort -r | xargs rmdir || :
 }
 
 FIXUP_FUNCTION = ""
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware/fix-zynqmp-assert.patch b/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware/fix-zynqmp-assert.patch
new file mode 100644
index 0000000000..87e1b111bc
--- /dev/null
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware/fix-zynqmp-assert.patch
@@ -0,0 +1,68 @@
+diff --git a/lib/sw_apps/zynqmp_pmufw/src/pm_reset.c b/lib/sw_apps/zynqmp_pmufw/src/pm_reset.c
+index 297c6c2ddc..bc295cf013 100644
+--- a/lib/sw_apps/zynqmp_pmufw/src/pm_reset.c
++++ b/lib/sw_apps/zynqmp_pmufw/src/pm_reset.c
+@@ -52,7 +52,7 @@
+  * @pulse	Function performing reset pulse operation
+  */
+ typedef struct PmResetOps {
+-	void (*const assert)(const PmReset* const rst, const u32 action);
++	void (*const resetAssert)(const PmReset* const rst, const u32 action);
+ 	u32 (*const getStatus)(const PmReset* const s);
+ 	u32 (*const pulse)(const PmReset* const rst);
+ } PmResetOps;
+@@ -415,37 +415,37 @@ static u32 PmResetPulsePl(const PmReset* const rst)
+ }
+ 
+ static const PmResetOps pmResetOpsGeneric = {
+-	.assert = PmResetAssertGen,
++	.resetAssert = PmResetAssertGen,
+ 	.getStatus = PmResetGetStatusGen,
+ 	.pulse = PmResetPulseGen,
+ };
+ 
+ static const PmResetOps pmResetOpsGpo = {
+-	.assert = PmResetAssertGpo,
++	.resetAssert = PmResetAssertGpo,
+ 	.getStatus = PmResetGetStatusGpo,
+ 	.pulse = PmResetPulseGpo,
+ };
+ 
+ static const PmResetOps pmResetOpsRom = {
+-	.assert = PmResetAssertRom,
++	.resetAssert = PmResetAssertRom,
+ 	.getStatus = PmResetGetStatusRom,
+ 	.pulse = PmResetPulseRom,
+ };
+ 
+ static const PmResetOps pmResetOpsNoAssert = {
+-	.assert = NULL,
++	.resetAssert = NULL,
+ 	.getStatus = PmResetGetStatusRom,
+ 	.pulse = PmResetPulseRom,
+ };
+ 
+ static const PmResetOps pmResetOpsPl = {
+-	.assert = PmResetAssertPl,
++	.resetAssert = PmResetAssertPl,
+ 	.getStatus = PmResetGetStatusPl,
+ 	.pulse = PmResetPulsePl,
+ };
+ 
+ static const PmResetOps pmResetOpsGpioBankIO = {
+-	.assert = NULL,
++	.resetAssert = NULL,
+ 	.getStatus = PmResetGetStatusGpioBankIOs,
+ 	.pulse = PmResetPulseGpioBankIOs,
+ };
+@@ -1901,8 +1901,8 @@ s32 PmResetDoAssert(const PmReset *reset, u32 action)
+ 	switch (action) {
+ 	case PM_RESET_ACTION_RELEASE:
+ 	case PM_RESET_ACTION_ASSERT:
+-		if (NULL != reset->ops->assert) {
+-			reset->ops->assert(reset, action);
++		if (NULL != reset->ops->resetAssert) {
++			reset->ops->resetAssert(reset, action);
+ 		} else {
+ 			status = XST_INVALID_PARAM;
+ 		}
diff --git a/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2020.2.bb b/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2020.2.bb
index 652241c0a8..330e020957 100644
--- a/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2020.2.bb
+++ b/meta-xilinx/meta-xilinx-standalone/recipes-standalone/pmu-firmware/pmu-firmware_2020.2.bb
@@ -6,7 +6,8 @@ LIC_FILES_CHKSUM = "file://../../../../license.txt;md5=39ab6ab638f4d1836ba994ec6
 SRCREV = "e8db5fb118229fdc621e0ec7848641a23bf60998"
 PV = "${XILINX_RELEASE_VERSION}+git${SRCPV}"
 
-SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1"
+SRC_URI = "git://github.com/Xilinx/embeddedsw.git;protocol=https;nobranch=1 \
+	   file://fix-zynqmp-assert.patch;pnum=5"
 
 COMPATIBLE_HOST = "microblaze.*-elf"
 COMPATIBLE_MACHINE = "microblaze-pmu"
-- 
cgit v1.2.3