From a34c030e5ec7021e7fb452410d38abfb3993ec68 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Mon, 23 Sep 2019 22:34:48 -0400 Subject: poky: subtree update:745e38ff0f..81f9e815d3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adrian Bunk (6): openssl: Upgrade 1.1.1c -> 1.1.1d glib-2.0: Upgrade 2.60.6 -> 2.60.7 lttng-modules: Upgrade 2.10.10 -> 2.10.11 lttng-ust: Upgrade 2.10.4 -> 2.10.5 squashfs-tools: Remove UPSTREAM_CHECK_COMMITS libmpc: Remove dead UPSTREAM_CHECK_URI Alexander Kanavin (2): runqemu: decouple gtk and gl options strace: add a timeout for running ptests Alistair Francis (1): gdb: Mark gdbserver as ALLOW_EMPTY for riscv32 Andre McCurdy (9): busybox: drop unused mount.busybox and umount.busybox wrappers busybox: drop inittab from SRC_URI ( now moved to busybox-inittab ) busybox-inittab: minor formatting tweaks base-files: drop legacy empty file /etc/default/usbd busybox: rcS and rcK should not be writeable by everyone ffmpeg: add PACKAGECONFIG controls for alsa and zlib (enable by default) libwebp: apply ARM specific config options to big endian ARM initscripts: enable alignment.sh init script for big endian ARM libunwind: apply configure over-ride to both big and little endian ARM Andrew F. Davis (4): libepoxy: Disable x11 when not building for x11 cogl: Set depends to the virtual needed not explicitly on Mesa gtk+3: Set depends to the virtual needed not explicitly on Mesa weston: Set depends to the virtual needed not explicitly on Mesa Armin Kuster (1): gcc: Security fix for CVE-2019-15847 Changhyeok Bae (1): iw: upgrade to 5.3 Changqing Li (2): classextend.py: don't extend file for file dependency report-error.bbclass: add local.conf/auto.conf into error report Chen Qi (1): python-numpy: fix build for libn32 Daniel Gomez (1): lttng-modules: Add missing SRCREV_FORMAT Diego Rondini (1): initramfs-framework: support PARTLABEL option Dmitry Eremin-Solenikov (7): image-uefi.conf: add config file holding configuration for UEFI images grub-bootconf: switch to image-uefi.conf grub-efi: switch to image-uefi.conf grub-efi.bbclass: switch to image-uefi.conf systemd-boot: switch to image-uefi.conf systemd-boot.bbclass: switch to image-uefi.conf live-vm-common.bbclass: provide efi population functions for live images Hector Palacios (1): udev-extraconf: skip mounting partitions already mounted by systemd Henning Schild (6): oe-git-proxy: allow setting SOCAT from outside oeqa: add case for oe-git-proxy Revert "oe-git-proxy: Avoid resolving NO_PROXY against local files" oe-git-proxy: disable shell pathname expansion for the whole script oe-git-proxy: NO_PROXY suffix matching without wildcard for match_host oe-git-proxy: fix dash "Bad substitution" Hongxu Jia (1): elfutils: 0.176 -> 0.177 Jack Mitchell (1): iptables: add systemd helper unit to load/restore rules Jaewon Lee (1): populate_sdk_ext: Introduce mechanism to keep nativesdk* sstate in esdk Jason Wessel (1): gnupg: Extend -native wrapper to fix gpgme-native's gpgconf problems Jiang Lu (2): glib-networking:enable glib-networking build as native package libsoup:enable libsoup build as native package Joshua Watt (4): sstatesig: Update server URI Remove SSTATE_HASHEQUIV_SERVER bitbake: bitbake: Rework hash equivalence classes/archiver: Fix WORKDIR for shared source Kai Kang (1): systemd: provides ${base_sbindir}/udevadm Khem Raj (10): ptrace: Drop ptrace aid for musl/ppc elfutils: Fix build on ppc/musl cogl: Do not depend PN-dev on empty PN musl: Update to latest master glibc: Move DISTRO_FEATURE specific do_install code for target recipe only populate_sdk_base.bbclass: nativesdk-glibc-locale is required on musl too nativesdk.bbclass: Clear out LIBCEXTENSION and ABIEXTENSION openssl: Enable os option for with-rand-seed as well weston-init: Add possibility to run weston as non-root user layer.conf: Remove weston-conf from SIGGEN_EXCLUDE_SAFE_RECIPE_DEPS Li Zhou (1): qemu: Security Advisory - qemu - CVE-2019-15890 Limeng (1): tune-cortexa57-cortexa53: add tunes for ARM Cortex-A53-Cortex-A57 Martin Jansa (2): perf: fix build on kernels which don't have ${S}/tools/include/linux/bits.h bitbake: Revert "bitbake: cooker: Ensure bbappends are found in stable order" Maxime Roussin-Bélanger (1): meta: add missing descriptions and homepage in bsp Mikko Rapeli (2): busybox.inc: handle empty DEBUG_PREFIX_MAP bitbake: svn fetcher: allow "svn propget svn:externals" to fail Nathan Rossi (7): resulttool: Handle multiple series containing ptestresults gcc-cross.inc: Process binaries in build dir to be relocatable oeqa/core/case.py: Add OEPTestResultTestCase for ptestresult helpers oeqa/selftest: Rework toolchain tests to use OEPTestResultTestCase glibc-testsuite: SkipRecipe if libc is not glibc cmake: 3.15.2 -> 3.15.3 meson.bbclass: Handle microblaze* mapping to cpu family Oleksandr Kravchuk (5): python3-pygobject: update to 3.34.0 font-util: update to 1.3.2 expat: update to 2.2.8 curl: update to 7.66.0 python3-dbus: update to 1.2.12 Otavio Salvador (1): mesa: Upgrade 19.1.1 -> 19.1.6 Peter Kjellerstedt (3): glibc: Make it build without ldconfig in DISTRO_FEATURES package_rpm.bbclass: Remove a misleading bb.note() tzdata: Correct the packaging of /etc/localtime and /etc/timezone Quentin Schulz (1): externalsrc: stop rebuilds of 2+ externalsrc recipes sharing the same git repo Randy MacLeod (4): valgrind: enable ~500 more ptests valgrind: make a few more ptests pass valgrind: ptest improvements to run-ptest and more valgrind: disable 256 ptests for aarch64 Richard Purdie (8): bitbake: runqueue/siggen: Optimise hash equiv queries runqemu: Mention snapshot in the help output initramfs-framework: support PARTLABEL option systemd: Handle slow to boot mips hwdb update timeouts meta-extsdk: Either an sstate task is a proper task or it isn't oeqa/concurrenttest: Use ionice to delete build directories bitbake: utils: Add ionice option to prunedir build-appliance-image: Update to master head revision Robert Yang (2): conf/multilib.conf: Add ovmf to NON_MULTILIB_RECIPES bitbake: runqueue: validate_hashes(): currentcount should be a number Ross Burton (16): libtasn1: fix build with api-documentation enabled gstreamer1.0-libav: enable gtk-doc again python3: handle STAGING_LIBDIR/INCDIR being unset mesa: no need to depend on target python3 adwaita-icon-theme: fix rare install race oeqa/selftest/wic: improve assert messages in test_fixed_size oeqa/selftest/imagefeatures: dump the JSON if it can't be parsed libical: upgrade to 3.0.6 acpica: upgrade 20190509 -> 20190816 gdk-pixbuf: upgrade 2.38.1 -> 2.38.2 piglit: upgrade to latest revision libinput: upgrade 1.14.0 -> 1.14.1 rootfs-postcommands: check /etc/gconf exists before working on it systemd-systemctl-native: don't care about line endings opkg-utils: respect SOURCE_DATE_EPOCH when building ipkgs bitbake: fetch2/git: add git-lfs toggle option Scott Murray (1): systemd: upgrade to 243 Stefan Ghinea (1): ghostscript: CVE-2019-14811, CVE-2019-14817 Tim Blechmann (1): icecc: blacklist pixman Yeoh Ee Peng (3): bitbake: bitbake-layers: show-recipes: Show recipes only bitbake: bitbake-layers: show-recipes: Select recipes from selected layer bitbake: bitbake-layers: show-recipes: Enable bare output Yi Zhao (3): screen: add /etc/screenrc as global config file nfs-utils: fix nfs mount error on 32bit nfs server grub: remove diffutils and freetype runtime dependencies Zang Ruochen (2): btrfs-tools:upgrade 5.2.1 -> 5.2.2 timezone:upgrade 2019b -> 2019c Change-Id: I1ec24480a8964e474cd99d60a0cb0975e49b46b8 Signed-off-by: Brad Bishop --- poky/meta/recipes-devtools/gcc/gcc-9.2.inc | 3 + .../gcc/gcc-9.2/CVE-2019-15847_1.patch | 521 +++++++++++++++++++++ .../gcc/gcc-9.2/CVE-2019-15847_2.patch | 77 +++ .../gcc/gcc-9.2/CVE-2019-15847_3.patch | 62 +++ poky/meta/recipes-devtools/gcc/gcc-cross.inc | 10 +- 5 files changed, 672 insertions(+), 1 deletion(-) create mode 100644 poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_1.patch create mode 100644 poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_2.patch create mode 100644 poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_3.patch (limited to 'poky/meta/recipes-devtools/gcc') diff --git a/poky/meta/recipes-devtools/gcc/gcc-9.2.inc b/poky/meta/recipes-devtools/gcc/gcc-9.2.inc index 01d3bf0f32..c6395998d5 100644 --- a/poky/meta/recipes-devtools/gcc/gcc-9.2.inc +++ b/poky/meta/recipes-devtools/gcc/gcc-9.2.inc @@ -65,6 +65,9 @@ SRC_URI = "\ file://0035-Fix-for-testsuite-failure.patch \ file://0036-Re-introduce-spe-commandline-options.patch \ file://CVE-2019-14250.patch \ + file://CVE-2019-15847_1.patch \ + file://CVE-2019-15847_2.patch \ + file://CVE-2019-15847_3.patch \ " S = "${TMPDIR}/work-shared/gcc-${PV}-${PR}/gcc-${PV}" SRC_URI[md5sum] = "3818ad8600447f05349098232c2ddc78" diff --git a/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_1.patch b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_1.patch new file mode 100644 index 0000000000..227fd47c95 --- /dev/null +++ b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_1.patch @@ -0,0 +1,521 @@ +From 8c61566116d23063ff597271884f8e00d94ab1a1 Mon Sep 17 00:00:00 2001 +From: segher +Date: Fri, 30 Aug 2019 13:48:48 +0000 +Subject: [PATCH] Backport from trunk 2019-08-22 Segher Boessenkool + + + * config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, + UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to... + * config/rs6000/rs6000.md (unspec): ... here. + * config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb, + *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, + cmpeqb, *cmpeqb_internal): Delete, move to... + * config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb, + *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, + cmpeqb, *cmpeqb_internal): ... here. + + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275170 138bc75d-0d04-0410-961f-82ee72b054a4 + +Upstream-Status: Backport +CVE: CVE-2019-15847 p1 +Affects <= 9.2.0 +Dropped Changelog changes +Signed-off-by: Armin Kuster + +--- + gcc/config/rs6000/altivec.md | 223 ---------------------------------- + gcc/config/rs6000/rs6000.md | 224 +++++++++++++++++++++++++++++++++++ + 3 files changed, 239 insertions(+), 223 deletions(-) + +Index: gcc-9.2.0/gcc/config/rs6000/altivec.md +=================================================================== +--- gcc-9.2.0.orig/gcc/config/rs6000/altivec.md ++++ gcc-9.2.0/gcc/config/rs6000/altivec.md +@@ -80,9 +80,6 @@ + UNSPEC_VUPKHPX + UNSPEC_VUPKLPX + UNSPEC_CONVERT_4F32_8I16 +- UNSPEC_DARN +- UNSPEC_DARN_32 +- UNSPEC_DARN_RAW + UNSPEC_DST + UNSPEC_DSTT + UNSPEC_DSTST +@@ -161,9 +158,6 @@ + UNSPEC_BCDADD + UNSPEC_BCDSUB + UNSPEC_BCD_OVERFLOW +- UNSPEC_CMPRB +- UNSPEC_CMPRB2 +- UNSPEC_CMPEQB + UNSPEC_VRLMI + UNSPEC_VRLNM + ]) +@@ -4101,223 +4095,6 @@ + "bcd. %0,%1,%2,%3" + [(set_attr "type" "vecsimple")]) + +-(define_insn "darn_32" +- [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] +- "TARGET_P9_MISC" +- "darn %0,0" +- [(set_attr "type" "integer")]) +- +-(define_insn "darn_raw" +- [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "darn %0,2" +- [(set_attr "type" "integer")]) +- +-(define_insn "darn" +- [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "darn %0,1" +- [(set_attr "type" "integer")]) +- +-;; Test byte within range. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as xx:xx:hi:lo. +-;; +-;; Return in target register operand 0 a value of 1 if lo <= vv and +-;; vv <= hi. Otherwise, set register operand 0 to 0. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation only operates on +-;; SI-mode operands as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmprb" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as xx:xx:hi:lo. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +-;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other +-;; 3 bits of the target CR register are all set to 0. +-(define_insn "*cmprb_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB))] +- "TARGET_P9_MISC" +- "cmprb %0,0,%1,%2" +- [(set_attr "type" "logical")]) +- +-;; Set operand 0 register to -1 if the LT bit (0x8) of condition +-;; register operand 1 is on. Otherwise, set operand 0 register to 1 +-;; if the GT bit (0x4) of condition register operand 1 is on. +-;; Otherwise, set operand 0 to 0. Note that the result stored into +-;; register operand 0 is non-zero iff either the LT or GT bits are on +-;; within condition register operand 1. +-(define_insn "setb_signed" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 1) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +- "setb %0,%1" +- [(set_attr "type" "logical")]) +- +-(define_insn "setb_unsigned" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") +- (const_int 0)) +- (const_int -1) +- (if_then_else (gtu (match_dup 1) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +- "setb %0,%1" +- [(set_attr "type" "logical")]) +- +-;; Test byte within two ranges. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +-;; +-;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and +-;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register +-;; operand 0 to 0. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation only operates on +-;; SI-mode operands as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmprb2" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB2)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the ranges specified by operand 2. +-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +-;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). +-;; Otherwise, set the GT bit to 0. The other 3 bits of the target +-;; CR register are all set to 0. +-(define_insn "*cmprb2_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB2))] +- "TARGET_P9_MISC" +- "cmprb %0,1,%1,%2" +- [(set_attr "type" "logical")]) +- +-;; Test byte membership within set of 8 bytes. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the set specified by operand 2. +-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +-;; +-;; Return in target register operand 0 a value of 1 if vv equals one +-;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set +-;; register operand 0 to 0. Note that the 8 byte values held within +-;; operand 2 need not be unique. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation requires that operands +-;; 0 and 1 have mode SI as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmpeqb" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:DI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPEQB)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC && TARGET_64BIT" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the set specified by operand 2. +-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv +-;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, +-;; set the GT bit to zero. The other 3 bits of the target CR register +-;; are all set to 0. +-(define_insn "*cmpeqb_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:DI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPEQB))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "cmpeqb %0,%1,%2" +- [(set_attr "type" "logical")]) +- + (define_expand "bcd_" + [(parallel [(set (reg:CCFP CR6_REGNO) + (compare:CCFP +Index: gcc-9.2.0/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-9.2.0.orig/gcc/config/rs6000/rs6000.md ++++ gcc-9.2.0/gcc/config/rs6000/rs6000.md +@@ -137,6 +137,12 @@ + UNSPEC_LSQ + UNSPEC_FUSION_GPR + UNSPEC_STACK_CHECK ++ UNSPEC_DARN ++ UNSPEC_DARN_32 ++ UNSPEC_DARN_RAW ++ UNSPEC_CMPRB ++ UNSPEC_CMPRB2 ++ UNSPEC_CMPEQB + UNSPEC_ADD_ROUND_TO_ODD + UNSPEC_SUB_ROUND_TO_ODD + UNSPEC_MUL_ROUND_TO_ODD +@@ -14322,7 +14328,225 @@ + "xscmpuqp %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "size" "128")]) ++ ++;; Miscellaneous ISA 3.0 (power9) instructions ++ ++(define_insn "darn_32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] ++ "TARGET_P9_MISC" ++ "darn %0,0" ++ [(set_attr "type" "integer")]) ++ ++(define_insn "darn_raw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "darn %0,2" ++ [(set_attr "type" "integer")]) ++ ++(define_insn "darn" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI [(const_int 0)] UNSPEC_DARN))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "darn %0,1" ++ [(set_attr "type" "integer")]) ++ ++;; Test byte within range. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as xx:xx:hi:lo. ++;; ++;; Return in target register operand 0 a value of 1 if lo <= vv and ++;; vv <= hi. Otherwise, set register operand 0 to 0. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation only operates on ++;; SI-mode operands as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmprb" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as xx:xx:hi:lo. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if ++;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other ++;; 3 bits of the target CR register are all set to 0. ++(define_insn "*cmprb_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB))] ++ "TARGET_P9_MISC" ++ "cmprb %0,0,%1,%2" ++ [(set_attr "type" "logical")]) ++ ++;; Set operand 0 register to -1 if the LT bit (0x8) of condition ++;; register operand 1 is on. Otherwise, set operand 0 register to 1 ++;; if the GT bit (0x4) of condition register operand 1 is on. ++;; Otherwise, set operand 0 to 0. Note that the result stored into ++;; register operand 0 is non-zero iff either the LT or GT bits are on ++;; within condition register operand 1. ++(define_insn "setb_signed" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 1) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++ "setb %0,%1" ++ [(set_attr "type" "logical")]) + ++(define_insn "setb_unsigned" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gtu (match_dup 1) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++ "setb %0,%1" ++ [(set_attr "type" "logical")]) ++ ++;; Test byte within two ranges. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. ++;; ++;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and ++;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register ++;; operand 0 to 0. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation only operates on ++;; SI-mode operands as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmprb2" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB2)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the ranges specified by operand 2. ++;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if ++;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). ++;; Otherwise, set the GT bit to 0. The other 3 bits of the target ++;; CR register are all set to 0. ++(define_insn "*cmprb2_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB2))] ++ "TARGET_P9_MISC" ++ "cmprb %0,1,%1,%2" ++ [(set_attr "type" "logical")]) ++ ++;; Test byte membership within set of 8 bytes. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the set specified by operand 2. ++;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. ++;; ++;; Return in target register operand 0 a value of 1 if vv equals one ++;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set ++;; register operand 0 to 0. Note that the 8 byte values held within ++;; operand 2 need not be unique. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation requires that operands ++;; 0 and 1 have mode SI as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmpeqb" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:DI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPEQB)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the set specified by operand 2. ++;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv ++;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, ++;; set the GT bit to zero. The other 3 bits of the target CR register ++;; are all set to 0. ++(define_insn "*cmpeqb_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:DI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPEQB))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "cmpeqb %0,%1,%2" ++ [(set_attr "type" "logical")]) + + + (include "sync.md") diff --git a/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_2.patch b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_2.patch new file mode 100644 index 0000000000..de7a83c23f --- /dev/null +++ b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_2.patch @@ -0,0 +1,77 @@ +From 87bc784a7ca3a43182f7272241597a50d7491342 Mon Sep 17 00:00:00 2001 +From: segher +Date: Fri, 30 Aug 2019 13:51:26 +0000 +Subject: [PATCH] Backport from trunk 2019-08-22 Segher Boessenkool + + + PR target/91481 + * config/rs6000/rs6000.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, + and UNSPEC_DARN_RAW. + (unspecv): New enumerator values UNSPECV_DARN, UNSPECV_DARN_32, and + UNSPECV_DARN_RAW. + (darn_32): Use an unspec_volatile, and UNSPECV_DARN_32. + (darn_raw): Use an unspec_volatile, and UNSPECV_DARN_RAW. + (darn): Use an unspec_volatile, and UNSPECV_DARN. + + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275175 138bc75d-0d04-0410-961f-82ee72b054a4 + +Upstream-Status: Backport +CVE: CVE-2019-15847 p2 +Affects <= 9.2.0 +Dropped Changelog changes +Signed-off-by: Armin Kuster + +--- + gcc/config/rs6000/rs6000.md | 12 ++++++------ + 2 files changed, 20 insertions(+), 6 deletions(-) + +Index: gcc-9.2.0/gcc/config/rs6000/rs6000.md +=================================================================== +--- gcc-9.2.0.orig/gcc/config/rs6000/rs6000.md ++++ gcc-9.2.0/gcc/config/rs6000/rs6000.md +@@ -137,9 +137,6 @@ + UNSPEC_LSQ + UNSPEC_FUSION_GPR + UNSPEC_STACK_CHECK +- UNSPEC_DARN +- UNSPEC_DARN_32 +- UNSPEC_DARN_RAW + UNSPEC_CMPRB + UNSPEC_CMPRB2 + UNSPEC_CMPEQB +@@ -170,6 +167,9 @@ + UNSPECV_EH_RR ; eh_reg_restore + UNSPECV_ISYNC ; isync instruction + UNSPECV_MFTB ; move from time base ++ UNSPECV_DARN ; darn 1 (deliver a random number) ++ UNSPECV_DARN_32 ; darn 2 ++ UNSPECV_DARN_RAW ; darn 0 + UNSPECV_NLGR ; non-local goto receiver + UNSPECV_MFFS ; Move from FPSCR + UNSPECV_MFFSL ; Move from FPSCR light instruction version +@@ -14333,21 +14333,21 @@ + + (define_insn "darn_32" + [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))] + "TARGET_P9_MISC" + "darn %0,0" + [(set_attr "type" "integer")]) + + (define_insn "darn_raw" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] ++ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,2" + [(set_attr "type" "integer")]) + + (define_insn "darn" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN))] ++ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,1" + [(set_attr "type" "integer")]) diff --git a/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_3.patch b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_3.patch new file mode 100644 index 0000000000..ba7130ca7d --- /dev/null +++ b/poky/meta/recipes-devtools/gcc/gcc-9.2/CVE-2019-15847_3.patch @@ -0,0 +1,62 @@ +From dc4c8dd9dbe70740ec7a684b0f35620249fb036a Mon Sep 17 00:00:00 2001 +From: segher +Date: Fri, 30 Aug 2019 13:53:11 +0000 +Subject: [PATCH] Backport from trunk 2019-08-23 Segher Boessenkool + + +gcc/testsuite/ + PR target/91481 + * gcc.target/powerpc/darn-3.c: New testcase. + + +git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275176 138bc75d-0d04-0410-961f-82ee72b054a4 + +Upstream-Status: Backport +CVE: CVE-2019-15847 p3 +Affects <= 9.2.0 +Dropped Changelog changes +Signed-off-by: Armin Kuster + +--- + gcc/testsuite/ChangeLog | 6 ++++++ + gcc/testsuite/gcc.target/powerpc/darn-3.c | 16 ++++++++++++++++ + 2 files changed, 22 insertions(+) + create mode 100644 gcc/testsuite/gcc.target/powerpc/darn-3.c + +Index: gcc-9.2.0/gcc/testsuite/gcc.target/powerpc/darn-3.c +=================================================================== +--- /dev/null ++++ gcc-9.2.0/gcc/testsuite/gcc.target/powerpc/darn-3.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-aix* } } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ ++ ++static int darn32(void) { return __builtin_darn_32(); } ++ ++int four(void) ++{ ++ int sum = 0; ++ int i; ++ for (i = 0; i < 4; i++) ++ sum += darn32(); ++ return sum; ++} ++ ++/* { dg-final { scan-assembler-times {(?n)\mdarn .*,0\M} 4 } } */ +Index: gcc-9.2.0/gcc/testsuite/ChangeLog +=================================================================== +--- gcc-9.2.0.orig/gcc/testsuite/ChangeLog ++++ gcc-9.2.0/gcc/testsuite/ChangeLog +@@ -1,3 +1,11 @@ ++2019-08-30 Segher Boessenkool ++ ++ Backport from trunk ++ 2019-08-23 Segher Boessenkool ++ ++ PR target/91481 ++ * gcc.target/powerpc/darn-3.c: New testcase. ++ + 2019-08-12 Release Manager + + * GCC 9.2.0 released. diff --git a/poky/meta/recipes-devtools/gcc/gcc-cross.inc b/poky/meta/recipes-devtools/gcc/gcc-cross.inc index 95af6d89a9..8855bb1f34 100644 --- a/poky/meta/recipes-devtools/gcc/gcc-cross.inc +++ b/poky/meta/recipes-devtools/gcc/gcc-cross.inc @@ -206,9 +206,17 @@ do_package_write_ipk[noexec] = "1" do_package_write_rpm[noexec] = "1" do_package_write_deb[noexec] = "1" -BUILDDIRSTASH = "${WORKDIR}/stashed-builddir" +inherit chrpath + +python gcc_stash_builddir_fixrpaths() { + # rewrite rpaths, breaking hardlinks as required + process_dir("/", d.getVar("BUILDDIRSTASH"), d, break_hardlinks = True) +} + +BUILDDIRSTASH = "${WORKDIR}/stashed-builddir/build" do_gcc_stash_builddir[dirs] = "${B}" do_gcc_stash_builddir[cleandirs] = "${BUILDDIRSTASH}" +do_gcc_stash_builddir[postfuncs] += "gcc_stash_builddir_fixrpaths" do_gcc_stash_builddir () { dest=${BUILDDIRSTASH} hardlinkdir . $dest -- cgit v1.2.3