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From 376e7cc533e27f943191d44c112e3812885b8fd1 Mon Sep 17 00:00:00 2001
From: Rui Miguel Silva <rui.silva@linaro.org>
Date: Wed, 8 Jan 2020 09:48:11 +0000
Subject: [PATCH 2/2] board: arm: add corstone500 board
Upstream-Status: Pending [Not submitted to upstream yet]
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
Add support for the Arm corstone500 platform, with a cortex-a5
chip, add the default configuration, initialization and
makefile for this system.
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
---
arch/arm/Kconfig | 10 +++
board/armltd/corstone500/Kconfig | 12 +++
board/armltd/corstone500/Makefile | 8 ++
board/armltd/corstone500/corstone500.c | 48 ++++++++++++
configs/corstone500_defconfig | 41 ++++++++++
include/configs/corstone500.h | 102 +++++++++++++++++++++++++
6 files changed, 221 insertions(+)
create mode 100644 board/armltd/corstone500/Kconfig
create mode 100644 board/armltd/corstone500/Makefile
create mode 100644 board/armltd/corstone500/corstone500.c
create mode 100644 configs/corstone500_defconfig
create mode 100644 include/configs/corstone500.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cac4fa09fd32..b875c1ef3d32 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1309,6 +1309,15 @@ config TARGET_CORSTONE1000
select PL01X_SERIAL
select DM
+config TARGET_CORSTONE500
+ bool "Support Corstone500"
+ select CPU_V7A
+ select SEMIHOSTING
+ select PL01X_SERIAL
+ help
+ This enables support for Corstone500 ARM which is a
+ Cortex-A5 system
+
config TARGET_TOTAL_COMPUTE
bool "Support Total Compute Platform"
select ARM64
@@ -2264,6 +2273,7 @@ source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig"
source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig"
+source "board/armltd/corstone500/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
diff --git a/board/armltd/corstone500/Kconfig b/board/armltd/corstone500/Kconfig
new file mode 100644
index 000000000000..8e689bd1fdc8
--- /dev/null
+++ b/board/armltd/corstone500/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CORSTONE500
+
+config SYS_BOARD
+ default "corstone500"
+
+config SYS_VENDOR
+ default "armltd"
+
+config SYS_CONFIG_NAME
+ default "corstone500"
+
+endif
diff --git a/board/armltd/corstone500/Makefile b/board/armltd/corstone500/Makefile
new file mode 100644
index 000000000000..6598fdd3ae0d
--- /dev/null
+++ b/board/armltd/corstone500/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 ARM Limited
+# (C) Copyright 2022 Linaro
+# Rui Miguel Silva <rui.silva@linaro.org>
+#
+
+obj-y := corstone500.o
diff --git a/board/armltd/corstone500/corstone500.c b/board/armltd/corstone500/corstone500.c
new file mode 100644
index 000000000000..e878f5c6a521
--- /dev/null
+++ b/board/armltd/corstone500/corstone500.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_pl01x.h>
+#include <malloc.h>
+#include <asm/global_data.h>
+
+static const struct pl01x_serial_plat serial_platdata = {
+ .base = V2M_UART0,
+ .type = TYPE_PL011,
+ .clock = CONFIG_PL011_CLOCK,
+};
+
+U_BOOT_DRVINFO(corstone500_serials) = {
+ .name = "serial_pl01x",
+ .plat = &serial_platdata,
+};
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
+
diff --git a/configs/corstone500_defconfig b/configs/corstone500_defconfig
new file mode 100644
index 000000000000..91661beb8d8d
--- /dev/null
+++ b/configs/corstone500_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_TARGET_CORSTONE500=y
+CONFIG_TEXT_BASE=0x88000000
+CONFIG_SYS_MALLOC_LEN=0x840000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x40000
+CONFIG_SYS_PROMPT="corstone500# "
+CONFIG_IDENT_STRING=" corstone500 aarch32"
+CONFIG_SYS_LOAD_ADDR=0x90000000
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xff000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x83f00000
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyAMA0 earlycon=pl011,0x1a200000 root=/dev/ram0 rw loglevel=9"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+# CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_ARMFLASH=y
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_DM=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SERIAL=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/corstone500.h b/include/configs/corstone500.h
new file mode 100644
index 000000000000..416f5fa4399d
--- /dev/null
+++ b/include/configs/corstone500.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 ARM Limited
+ * (C) Copyright 2022 Linaro
+ * Rui Miguel Silva <rui.silva@linaro.org>
+ *
+ * Configuration for Cortex-A5 Corstone500. Parts were derived from other ARM
+ * configurations.
+ */
+
+#ifndef __CORSTONE500_H
+#define __CORSTONE500_H
+
+/* Generic Timer Definitions */
+#define CONFIG_SYS_HZ_CLOCK 7500000
+#define CONFIG_SYS_HZ 1000
+#define COUNTER_FREQUENCY CONFIG_SYS_HZ_CLOCK
+
+#ifdef CONFIG_CORSTONE500_MEMORY_MAP_EXTENDED
+#define V2M_SRAM0 0x00010000
+#define V2M_SRAM1 0x02200000
+#define V2M_QSPI 0x0a800000
+#else
+#define V2M_SRAM0 0x00000000
+#define V2M_SRAM1 0x02000000
+#define V2M_QSPI 0x08000000
+#endif
+
+#define V2M_DEBUG 0x10000000
+#define V2M_BASE_PERIPH 0x1a000000
+#define V2M_A5_PERIPH 0x1c000000
+#define V2M_L2CC_PERIPH 0x1c010000
+
+#define V2M_MASTER_EXPANSION0 0x40000000
+#define V2M_MASTER_EXPANSION1 0x60000000
+
+#define V2M_BASE 0x80000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 16)
+
+#define V2M_SYSID (V2M_BASE_PERIPH)
+#define V2M_SYCTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(1))
+#define V2M_COUNTER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(2))
+#define V2M_COUNTER_READ (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(3))
+#define V2M_TIMER_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(4))
+#define V2M_TIMER0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(5))
+
+#define V2M_WATCHDOG_CTL (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(16))
+#define V2M_WATCHDOG_REFRESH (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(17))
+
+#define V2M_UART0 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(32))
+#define V2M_UART1 (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(33))
+
+#define V2M_RTC (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(34))
+#define V2M_TRNG (V2M_BASE_PERIPH + V2M_PERIPH_OFFSET(35))
+
+/* PL011 Serial Configuration */
+#define CONFIG_CONS_INDEX 0
+#define CONFIG_PL011_CLOCK 7500000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM_1 (V2M_BASE)
+
+/* Top 16MB reserved for secure world use */
+#define DRAM_SEC_SIZE 0x01000000
+#define PHYS_SDRAM_1_SIZE (0x80000000 - DRAM_SEC_SIZE)
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+#define CONFIG_SYS_MMIO_TIMER
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_name=Image\0" \
+ "kernel_addr=0x80f00000\0" \
+ "initrd_name=ramdisk.img\0" \
+ "initrd_addr=0x84000000\0" \
+ "fdt_name=devtree.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0"
+
+#define CONFIG_BOOTCOMMAND "echo copy to RAM...; " \
+ "cp.b 0x80100000 $kernel_addr 0xb00000; " \
+ "cp.b 0x80d00000 $initrd_addr 0x800000; " \
+ "bootz $kernel_addr $initrd_addr:0x800000 $fdt_addr"
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_FLASH_BASE 0x80000000
+/* Store environment at top of flash */
+#define CONFIG_ENV_ADDR 0x0a7c0000
+#define CONFIG_ENV_SECT_SIZE 0x0040000
+
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define FLASH_MAX_SECTOR_SI 0x00040000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#endif
--
2.39.1
|
