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From 235fabb2269a86e016bab2886b9129c77f0fea71 Wed Oct 11 16:18:22 2023
From: Mariam Elshakfy <mariam.elshakfy@arm.com>
Date: Wed Oct 11 16:18:22 2023 +0000
Subject: [PATCH] Platform/ARM/N1Sdp: Reserve OP-TEE Region from UEFI
To enable cache on N1SDP, OP-TEE has to be moved
to run from DDR4 memory. Since this memory is
known to application side, it must be reserved
Upstream-Status: Pending (not yet submitted to upstream)
Signed-off-by: Mariam Elshakfy <mariam.elshakfy@arm.com>
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
index 78f309c3aa..dc82d5bd87 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLib.inf
@@ -62,6 +62,9 @@
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize
+
[Guids]
gArmNeoverseN1SocPlatformInfoDescriptorGuid
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
index 8bb9407490..d8ad0f975c 100644
--- a/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
+++ b/Silicon/ARM/NeoverseN1Soc/Library/PlatformLib/PlatformLibMem.c
@@ -150,6 +150,19 @@ ArmPlatformGetVirtualMemoryMap (
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
EFI_RESOURCE_ATTRIBUTE_TESTED;
+ // Reserved OP-TEE region
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_SYSTEM_MEMORY,
+ ResourceAttributes,
+ PcdGet64 (PcdOpteeMemoryBase),
+ PcdGet64 (PcdOpteeMemorySize)
+ );
+ BuildMemoryAllocationHob (
+ PcdGet64 (PcdOpteeMemoryBase),
+ PcdGet64 (PcdOpteeMemorySize),
+ EfiReservedMemoryType
+ );
+
BuildResourceDescriptorHob (
EFI_RESOURCE_SYSTEM_MEMORY,
ResourceAttributes,
diff --git a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
index 9e257ebde0..b400b94fd5 100644
--- a/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
+++ b/Silicon/ARM/NeoverseN1Soc/NeoverseN1Soc.dec
@@ -86,5 +86,9 @@
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieMmio64Translation|0x40000000000|UINT64|0x00000050
gArmNeoverseN1SocTokenSpaceGuid.PcdRemotePcieSegmentNumber|2|UINT32|0x00000051
+ # Base Address of OP-TEE
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemoryBase|0xDE000000|UINT64|0x00000052
+ gArmNeoverseN1SocTokenSpaceGuid.PcdOpteeMemorySize|0x02000000|UINT64|0x00000053
+
[Ppis]
gNtFwConfigDtInfoPpiGuid = { 0xb50dee0e, 0x577f, 0x47fb, { 0x83, 0xd0, 0x41, 0x78, 0x61, 0x8b, 0x33, 0x8a } }
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