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authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:18 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:08:30 +0300
commit0626db663b184485fba3ba122aeb522ca994ac5a (patch)
treee75d2bcc9413019de2576f9f91429929694d5228
parent34547419ed59910beeff85120a5058ead302765e (diff)
downloadu-boot-0626db663b184485fba3ba122aeb522ca994ac5a.tar.xz
mmc: sdhci: rockchip: fix bus width setting
Rockchip sdhci controller capable of 8-bit transfer. The original can only run at 4 bit mode. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--drivers/mmc/rockchip_sdhci.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index f31d329c81..f4050b1c6f 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -47,10 +47,24 @@ static int arasan_sdhci_probe(struct udevice *dev)
host->name = dev->name;
host->ioaddr = map_sysmem(dtplat->reg[1], dtplat->reg[3]);
+ host->host_caps |= MMC_MODE_8BIT;
max_frequency = dtplat->max_frequency;
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &clk);
#else
max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
+ switch (dev_read_u32_default(dev, "bus-width", 4)) {
+ case 8:
+ host->host_caps |= MMC_MODE_8BIT;
+ break;
+ case 4:
+ host->host_caps |= MMC_MODE_4BIT;
+ break;
+ case 1:
+ break;
+ default:
+ printf("Invalid \"bus-width\" value\n");
+ return -EINVAL;
+ }
ret = clk_get_by_index(dev, 0, &clk);
#endif
if (!ret) {