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authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:09 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:05:01 +0300
commit4055b4671538482b1c23632528a7adf97b9183e5 (patch)
treea294353ae36e21b64774f17e4709e4176354889a
parent55782c4014d63062e5efd4fee93b900c020155d8 (diff)
downloadu-boot-4055b4671538482b1c23632528a7adf97b9183e5.tar.xz
rockchip: clk: rk3288: fix mmc clock setting
Mmc clock automatically divide 2 in internal. Before this: gpll = 594MHz, clock = 148.5MHz div = 594/148.5-1 = 3 output clock is 99MHz After this: gpll = 594MHz, clock = 148.5MHz div = 297+148.5-1/148.5 = 2 output clock is 148.5Mhz Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 792ee76509..a5596d7e05 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -520,7 +520,7 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
}
src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
- return DIV_TO_RATE(src_rate, div);
+ return DIV_TO_RATE(src_rate, div) / 2;
}
static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
@@ -530,10 +530,10 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
int mux;
debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
- src_clk_div = RATE_TO_DIV(gclk_rate, freq);
+ src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
if (src_clk_div > 0x3f) {
- src_clk_div = RATE_TO_DIV(OSC_HZ, freq);
+ src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
mux = EMMC_PLL_SELECT_24MHZ;
assert((int)EMMC_PLL_SELECT_24MHZ ==
(int)MMC0_PLL_SELECT_24MHZ);