summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:16 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:05:02 +0300
commit589aad3ee36a92c531798d28ecc6b4515d7e6547 (patch)
treed24fe43b997a5a5f241ca84a3091b16bdf42ee66
parent970b0da7a693b23c41c7ede063360dcd76bcd123 (diff)
downloadu-boot-589aad3ee36a92c531798d28ecc6b4515d7e6547.tar.xz
mmc: dw_mmc: rockchip: fix data crc error on ddr52 8bit mode
The clk_divider must be set to 1 on ddr52 8bit mode for rockchip platform. Otherwise we will get a data crc error during data transmission. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--drivers/mmc/dw_mmc.c2
-rw-r--r--drivers/mmc/rockchip_dw_mmc.c7
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index e862eb228e..dcd7fba086 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -344,7 +344,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
int timeout = 10000;
unsigned long sclk;
- if ((freq == host->clock) || (freq == 0))
+ if (freq == 0)
return 0;
/*
* If host->get_mmc_clk isn't defined,
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index f79e557ab1..6027642f44 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -43,6 +43,13 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
int ret;
+ /*
+ * If DDR52 8bit mode(only emmc work in 8bit mode),
+ * divider must be set 1
+ */
+ if (mmc_card_ddr52(host->mmc) && host->mmc->bus_width == 8)
+ freq *= 2;
+
ret = clk_set_rate(&priv->clk, freq);
if (ret < 0) {
debug("%s: err=%d\n", __func__, ret);