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authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:15 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:05:02 +0300
commit970b0da7a693b23c41c7ede063360dcd76bcd123 (patch)
treeb13399fc094708c850d3e22f63188360f94a615d
parent8920f389fed6e5d19867fc589c6258e29a91b28e (diff)
downloadu-boot-970b0da7a693b23c41c7ede063360dcd76bcd123.tar.xz
mmc: add DDR52 support for eMMC card
4.41+ eMMC card devices can run at 52MHz on DDR 8-bit mode, it can improve write/read performance. Host driver can set MMC_MODE_DDR_52Mhz to enable this feature. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--drivers/mmc/mmc.c26
1 files changed, 25 insertions, 1 deletions
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 2fdf220658..c5bb334725 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -795,6 +795,27 @@ static int mmc_select_hs(struct mmc *mmc)
return ret;
}
+static int mmc_select_hs_ddr(struct mmc *mmc)
+{
+ u32 ext_csd_bits;
+ int err = 0;
+
+ if (mmc->bus_width == MMC_BUS_WIDTH_1BIT)
+ return 0;
+
+ ext_csd_bits = (mmc->bus_width == MMC_BUS_WIDTH_8BIT) ?
+ EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4;
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_BUS_WIDTH, ext_csd_bits);
+ if (err)
+ return err;
+
+ mmc_set_timing(mmc, MMC_TIMING_MMC_DDR52);
+
+ return 0;
+}
+
#ifndef CONFIG_SPL_BUILD
static int mmc_select_hs200(struct mmc *mmc)
{
@@ -941,8 +962,11 @@ static int mmc_change_freq(struct mmc *mmc)
if (mmc_card_hs200(mmc))
err = mmc_hs200_tuning(mmc);
- else
+ else if (!mmc_card_hs400es(mmc)) {
err = mmc_select_bus_width(mmc) > 0 ? 0 : err;
+ if (!err && avail_type & EXT_CSD_CARD_TYPE_DDR_52)
+ err = mmc_select_hs_ddr(mmc);
+ }
return err;
}