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authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:26 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:08:31 +0300
commitcdd56a12e6e1f36b17492073746829a5875af91b (patch)
tree2eb80f9eaefaba8dd331817914da51d516092e08
parentd6c8dc9aa2caef539109d6ea4a3918269977008a (diff)
downloadu-boot-cdd56a12e6e1f36b17492073746829a5875af91b.tar.xz
dts: rk3399: change the maximum eMMC clock frequency to 150MHz
The rockchip mmc controllers don't support _the _odd__ divider, otherwise probably cause unpredictable error. The driver originally select gpll(594M) as the clock source, and we set div to 3 at 200MHz. We have to change the maximum eMMC clock frequency to 150MHz in U-Boot stage, so that the div will be 4. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--arch/arm/dts/rk3399.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 7f1fc50f38..25bd63ecfb 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -283,7 +283,7 @@
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
- max-frequency = <200000000>;
+ max-frequency = <150000000>;
clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
clock-names = "clk_xin", "clk_ahb";
clock-output-names = "emmc_cardclock";