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authorZiyuan Xu <xzy.xu@rock-chips.com>2017-05-15 09:07:11 +0300
committerKever Yang <kever.yang@rock-chips.com>2017-07-18 17:05:01 +0300
commitfa1b1f8241bd725d7ed3c3a2e4429fca6e7446d9 (patch)
tree59e448cba990c76a4695a32c2860963dfb714fb3
parentd7ba1a518bdaa96e8e81b6c2cc0b7bc35160e01a (diff)
downloadu-boot-fa1b1f8241bd725d7ed3c3a2e4429fca6e7446d9.tar.xz
rockchip: clk: rk3399: fix emmc clock setting
Before this: gpll = 594MHz, set_clock = 200MHz div = 594/200 = 2 real clock is 297MHz After this: gpll = 594MHz, clock = 148.5MHz div = 594+200-1/200 = 3 real clock is 198Mhz Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
-rw-r--r--drivers/clk/rockchip/clk_rk3399.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 53d2a3f85d..54079cd1d7 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -794,7 +794,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
break;
case SCLK_EMMC:
/* Select aclk_emmc source from GPLL */
- src_clk_div = GPLL_HZ / aclk_emmc;
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
assert(src_clk_div - 1 < 31);
rk_clrsetreg(&cru->clksel_con[21],
@@ -803,7 +803,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
(src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
/* Select clk_emmc source from GPLL too */
- src_clk_div = GPLL_HZ / set_rate;
+ src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
assert(src_clk_div - 1 < 127);
rk_clrsetreg(&cru->clksel_con[22],