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authorDongjin Kim <tobetter@gmail.com>2019-08-09 10:50:52 +0300
committerDongjin Kim <tobetter@gmail.com>2020-02-17 06:45:46 +0300
commit3b8b5cbd956b22080925dd3beaaac463452c12f1 (patch)
treed4a7dbf05bb23ea5efe8669c19735535e512dfb0
parentf16862e0c94411dbdb0fcaaa6616266da8d40f7b (diff)
downloadu-boot-3b8b5cbd956b22080925dd3beaaac463452c12f1.tar.xz
ODROID-N2: firmware: reset the DDR configurationtravis/odroidn2-75
Change-Id: Ib52f1accc13dfa0db9b02a2dfbdab5dceb404efc Signed-off-by: Dongjin Kim <tobetter@gmail.com>
-rw-r--r--board/hardkernel/odroidn2/firmware/timing.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/hardkernel/odroidn2/firmware/timing.c b/board/hardkernel/odroidn2/firmware/timing.c
index 7b65a22735..6801380ba7 100644
--- a/board/hardkernel/odroidn2/firmware/timing.c
+++ b/board/hardkernel/odroidn2/firmware/timing.c
@@ -96,7 +96,7 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0x61},
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30},
+ .phy_odt_config_rank = {0x23,0x13},
.dfi_odt_config = 0x0808,
.PllBypassEn = 0,
.ddr_rdbi_wr_enable = 0,
@@ -154,7 +154,7 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61},
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30},
+ .phy_odt_config_rank = {0x23,0x13},
.dfi_odt_config = 0x0808,
.PllBypassEn = 0,
.ddr_rdbi_wr_enable = 0,