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authorxiaobo gu <xiaobo.gu@amlogic.com>2018-12-29 15:32:36 +0300
committerDongjin Kim <tobetter@gmail.com>2020-02-17 06:45:46 +0300
commitf16862e0c94411dbdb0fcaaa6616266da8d40f7b (patch)
tree3f103f629cfc4a5e38e909b2c3f23e0af1bb2bdc
parent19bb3cc67c97946330731ba52a5b95bcbabfff10 (diff)
downloadu-boot-f16862e0c94411dbdb0fcaaa6616266da8d40f7b.tar.xz
uboot: update ddr and emmc driver. [1/3]
6a2a443 storage: mmc/nand: support support to read saved ddr parameter [1/1] cb80c6c uboot: emmc: setup emmc hs400 debug environment in uboot [1/1] 9927af4 ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3] c9dfa59 ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3] ac463ed ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3] 3fead4a dram: scramble: update scramble key config [2/2] dram: scramble: update scramble key config [2/2] PD#SWPL-3152 Problem: can not configure non-sec memory scramble key in uboot Solution: add config interface in ddr function Verity: test pass on u200/w400/x301 Change-Id: Ie987ecc336483518913dc3cb850cbe04d348720e Signed-off-by: xiaobo gu <xiaobo.gu@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> ddr: timing:G12A/G12B/TL1_update_LPDDR4_PHY_V_0_1_12_bl33 [2/3] PD#SWPL-5973 Problem: none Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_12" 20190128 1 reduice funciton ddr_init_soc_calculate_impedence_ctrl code size 2 modify ddr4 DqDqsRcvCntrl register for swith to extend vref range improve vref training 3 adjust 16bit lpddr4 dfi mode register and DMC_DRAM_DFI_CTRL register for 16bit test 4 change ddr scramble to after exter_ddrtest 5 add amlogic vref correction function 6 combine g12 rev-a and rev-b 7 repair tl1 ddr3 autosize function 8 config cfg_ddr_dqs=5 improve rank switch speed 9 change ddr4 rtt_park to 0 for ddr4 dqs level will increase vddq power 10 add fail_pass_ddr test method 11 disable asr only apd after ddrtest 12 add ddr_fast_boot function 13 add lpddr4 fast boot vt function Verify: test pass at x301 Change-Id: I19c0100cd08990854ab1f006d5e7060e7c2cc1bf Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> ddr: driver:G12A/G12B/TL1 update LPDDR4_PHY_V_0_1_13 bl33 [2/3] PD#SWPL-7341 Problem: none. Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_13" 20190417 1 add ddr_fast_boot data sha2 checksum 2 repair ddr reinit training all use for auto frequency scan 3 adjust tl1 bl2 stack link 4 reparir cs0 4GB support ,limit ddr addtest <=3928M 5 change tl1 board id to ddr id Verify: test pass at x301 and u200. Change-Id: I582fc6b67d6b565ef260b9bc4c144425ece95cc4 Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> ddr: timing:G12A/G12B/TL1/TM2 update LPDDR4_PHY_V_0_1_14 bl33 [2/3] PD#SWPL-7880 Problem: none. Solution: DDR_DRIVER_VERSION "LPDDR4_PHY_V_0_1_14" 20190426 1 add soc window vref offset function 2 add usb_download_full test function 3 repair lpddr4 CA delay offset function 4 repair suspend resume test command 5 2400 ddr4 change cl from 16 to 18. compatibility new JEDEC 6 add dfi_mrl max value limmit 7 change lpddr4 init soc vref value Verify: test pass at T309,U200,W400. Change-Id: Ie92971f4a009511b72b22eea6dba56c461438d2b Signed-off-by: zhiguang.ouyang <zhiguang.ouyang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> uboot: emmc: setup emmc hs400 debug environment in uboot [1/1] PD#SWPL-1265 Problem: HS400 enviroment is too complexity to debug Solution: setup HS400 environment in uboot Verify: verify on tl1_skt Change-Id: Iddc3ec8bdad496baf5792457d5417fe06ac3ce9b Signed-off-by: Ruixuan Li <ruixuan.li@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com> storage: mmc/nand: support support to read saved ddr parameter [1/1] PD#SWPL-5550 Problem: Implement to the function that can read ddr parameter which saved in reserved area. Solution: provide interface. Verify: tl1-x301 axg-s400 Change-Id: I68a0a83ac435ad6d4a11e01edc290aedae650941 Signed-off-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Qiang Li <qiang.li@amlogic.com> Signed-off-by: Liang Yang <liang.yang@amlogic.com> Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
-rw-r--r--arch/arm/include/asm/arch-g12a/ddr_define.h2
-rw-r--r--arch/arm/include/asm/arch-g12a/timing.h16
-rw-r--r--arch/arm/include/asm/arch-g12b/ddr_define.h2
-rw-r--r--arch/arm/include/asm/arch-g12b/timing.h18
-rw-r--r--board/amlogic/g12a_skt_v1/firmware/timing.c25
-rw-r--r--board/amlogic/g12a_u200_v1/firmware/timing.c20
-rw-r--r--board/amlogic/g12a_u211_v1/firmware/timing.c20
-rw-r--r--board/amlogic/g12a_u212_v1/firmware/timing.c20
-rw-r--r--board/amlogic/g12a_u220_v1/firmware/timing.c374
-rw-r--r--board/amlogic/g12a_u221_v1/firmware/timing.c20
-rw-r--r--board/amlogic/g12b_skt_v1/firmware/timing.c92
-rw-r--r--board/amlogic/g12b_w400_v1/firmware/timing.c18
-rw-r--r--board/amlogic/tl1_skt_v1/firmware/timing.c6
-rw-r--r--common/cmd_ddr_test.c72390
-rw-r--r--common/store_interface.c5
15 files changed, 37104 insertions, 35924 deletions
diff --git a/arch/arm/include/asm/arch-g12a/ddr_define.h b/arch/arm/include/asm/arch-g12a/ddr_define.h
index ca44a90615..f13f5e18e7 100644
--- a/arch/arm/include/asm/arch-g12a/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12a/ddr_define.h
@@ -83,6 +83,8 @@
(chl_set == CONFIG_DDR0_16BIT))
#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
/* DMC_DDR_CTRL defines */
#define DDR_DDR4_ENABLE (1<<22)
#define DDR_RANK1_ENABLE (1<<21)
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h
index de9da4950e..7170cbb210 100644
--- a/arch/arm/include/asm/arch-g12a/timing.h
+++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -73,7 +73,8 @@ typedef struct ddr_reg {
typedef struct ddr_set{
unsigned int magic;
- unsigned int rsv_int0;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -131,7 +132,9 @@ typedef struct ddr_set{
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
- unsigned char phy_odt_config_rank[4];
+ unsigned char phy_odt_config_rank[2];
+ unsigned char rever1;
+ unsigned char rever2;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -232,7 +235,7 @@ typedef struct ddr_set{
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
//system reserve,do not modify
- unsigned short dq_bdlr_org;
+ unsigned short tdqs2dq;
unsigned char dram_data_wr_odt_ohm;
unsigned char bitTimeControl_2d;
//system reserve,do not modify
@@ -251,7 +254,7 @@ typedef struct ddr_set{
//system reserve,do not modify
/* align8 */
- unsigned long rsv_long0[2];
+ //unsigned long rsv_long0[2];
/* v1 end */
//unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
//unsigned char read_dq_bit_delay[72];
@@ -262,10 +265,13 @@ typedef struct ddr_set{
unsigned short write_dqs_delay[16];
unsigned short write_dq_bit_delay[72];
unsigned short read_dqs_gate_delay[16];
- unsigned char dq_dqs_delay_flag; //read_dqs read_dq,write_dqs, write_dq
+ unsigned char soc_bit_vref[32];
+ unsigned char dram_bit_vref[32];
+ unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
unsigned char dfi_mrl;
unsigned char dfi_hwtmrl;
unsigned char ARdPtrInitVal;
+ unsigned char retraining[16];
//override read bit delay
}__attribute__ ((packed)) ddr_set_t;
diff --git a/arch/arm/include/asm/arch-g12b/ddr_define.h b/arch/arm/include/asm/arch-g12b/ddr_define.h
index 8b3578e582..3e8a6f0ef0 100644
--- a/arch/arm/include/asm/arch-g12b/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12b/ddr_define.h
@@ -83,6 +83,8 @@
(chl_set == CONFIG_DDR0_16BIT))
#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
/* DMC_DDR_CTRL defines */
#define DDR_DDR4_ENABLE (1<<22)
#define DDR_RANK1_ENABLE (1<<21)
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h
index cd1002ead9..4124457bf5 100644
--- a/arch/arm/include/asm/arch-g12b/timing.h
+++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -73,7 +73,8 @@ typedef struct ddr_reg {
typedef struct ddr_set{
unsigned int magic;
- unsigned int rsv_int0;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -131,7 +132,9 @@ typedef struct ddr_set{
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
- unsigned char phy_odt_config_rank[4];
+ unsigned char phy_odt_config_rank[2];
+ unsigned char rever1;
+ unsigned char rever2;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -232,7 +235,7 @@ typedef struct ddr_set{
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
//system reserve,do not modify
- unsigned short dq_bdlr_org;
+ unsigned short tdqs2dq;
unsigned char dram_data_wr_odt_ohm;
unsigned char bitTimeControl_2d;
//system reserve,do not modify
@@ -251,7 +254,7 @@ typedef struct ddr_set{
//system reserve,do not modify
/* align8 */
- unsigned long rsv_long0[2];
+ //unsigned long rsv_long0[2];
/* v1 end */
//unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
//unsigned char read_dq_bit_delay[72];
@@ -260,12 +263,17 @@ typedef struct ddr_set{
unsigned char read_dqs_delay[16];
unsigned char read_dq_bit_delay[72];
unsigned short write_dqs_delay[16];
+//*/
unsigned short write_dq_bit_delay[72];
unsigned short read_dqs_gate_delay[16];
- unsigned char dq_dqs_delay_flag; //read_dqs read_dq,write_dqs, write_dq
+ unsigned char soc_bit_vref[32];
+ unsigned char dram_bit_vref[32];
+// /*
+ unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
unsigned char dfi_mrl;
unsigned char dfi_hwtmrl;
unsigned char ARdPtrInitVal;
+ unsigned char retraining[16];
//override read bit delay
}__attribute__ ((packed)) ddr_set_t;
diff --git a/board/amlogic/g12a_skt_v1/firmware/timing.c b/board/amlogic/g12a_skt_v1/firmware/timing.c
index 8bb82382db..20dee869c8 100644
--- a/board/amlogic/g12a_skt_v1/firmware/timing.c
+++ b/board/amlogic/g12a_skt_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -131,7 +131,7 @@ ddr_set_t __ddr_setting[] = {
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.slt_test_function={0x0,0x0}, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
- .read_dq_bit_delay={
+/* .read_dq_bit_delay={
6 ,
4 ,
7 ,
@@ -223,6 +223,7 @@ ddr_set_t __ddr_setting[] = {
0x0 ,
0x0 ,
},//DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
+ */
// .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS,
.bitTimeControl_2d=1, //use 6 about 1s 7 about 2s 1 about 400ms
},
@@ -245,8 +246,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//4096,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -328,8 +329,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -395,6 +396,7 @@ ddr_set_t __ddr_setting[] = {
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
.bitTimeControl_2d=1,
+ /*
//.slt_test_function = { DMC_TEST_SLT_SCAN_FREQUENCY|DMC_TEST_SLT_OFFSET_DELAY , 5},
.write_dq_bit_delay={
0x8002 ,
@@ -470,6 +472,7 @@ ddr_set_t __ddr_setting[] = {
0x8002 ,
0x8002 ,
} ,
+*/
//.dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ,
//.dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
//DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
@@ -494,8 +497,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -566,8 +569,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12a_u200_v1/firmware/timing.c b/board/amlogic/g12a_u200_v1/firmware/timing.c
index 194ee7d93c..800982d6ee 100644
--- a/board/amlogic/g12a_u200_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u200_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -304,8 +304,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -375,8 +375,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12a_u211_v1/firmware/timing.c b/board/amlogic/g12a_u211_v1/firmware/timing.c
index 4d7632e79e..d91893eb10 100644
--- a/board/amlogic/g12a_u211_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u211_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -303,8 +303,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -374,8 +374,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12a_u212_v1/firmware/timing.c b/board/amlogic/g12a_u212_v1/firmware/timing.c
index 4d7632e79e..d91893eb10 100644
--- a/board/amlogic/g12a_u212_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u212_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -303,8 +303,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -374,8 +374,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12a_u220_v1/firmware/timing.c b/board/amlogic/g12a_u220_v1/firmware/timing.c
index 8e83ce6f22..1a4852640c 100644
--- a/board/amlogic/g12a_u220_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u220_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,//40,
@@ -296,8 +296,9 @@ ddr_set_t __ddr_setting[] = {
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
},
+/*
{
- /* g12a u220 lpddr4 repair mode */
+ // g12a u220 lpddr4 repair mode
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
//.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
@@ -316,15 +317,14 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,//40,
.cs_drv_ohm = 40,//40,
.ac_drv_ohm = 40,//40,
- /*
.soc_data_drv_ohm_p = 40,//30,//30,
.soc_data_drv_ohm_n = 40,//30,//30,
.soc_data_odt_ohm_p = 0,
@@ -332,8 +332,8 @@ ddr_set_t __ddr_setting[] = {
.dram_data_drv_ohm = 40,// 48, //lpddr4 sdram only240/1-6
.dram_data_odt_ohm = 120,// 48,//48,
.lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
- */
- ///*
+
+ ////
.soc_data_drv_ohm_p = 48,//30,//30,
.soc_data_drv_ohm_n = 48,//30,//30,
.soc_data_odt_ohm_p = 0,
@@ -342,7 +342,7 @@ ddr_set_t __ddr_setting[] = {
.dram_data_odt_ohm = 48,// 48,//48,
.dram_ac_odt_ohm = 120,
.lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
- //*/
+ ////
.soc_clk_slew_rate = 0x3ff,//0x253,
.soc_cs_slew_rate = 0x100,//0x253,
.soc_ac_slew_rate = 0x100,//0x253,
@@ -364,349 +364,13 @@ ddr_set_t __ddr_setting[] = {
.ddr_lpddr34_ca_remap = {00,00},
.ddr_lpddr34_dq_remap = {3,2,0,1,7,6,5,4, 14,13,12,15,8,9,11,10, 20,21,22,23,16,17,19,18, 24,25,28,26,31,30,27,29},
.dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
-/*
- .slt_test_function = { DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 7 ,
-
- .ac_trace_delay = {
- 32 ,
- 32 ,
- 30 ,
- 29 ,
- 0 ,
- 32 ,
- 32 ,
- 29 ,
- 27 ,
- 0 ,
- } ,
-
- .write_dqs_delay = {
- 144 ,
- 144 ,
- 160 ,
- 160 ,
- 160 ,
- 160 ,
- 140 ,
- 140 ,
- 142 ,
- 142 ,
- 160 ,
- 160 ,
- 160 ,
- 160 ,
- 142 ,
- 142 ,
- } ,
-
- .read_dqs_delay = {
- 11 ,
- 2 ,
- 11 ,
- 0 ,
- 13 ,
- 1 ,
- 13 ,
- 5 ,
- 13 ,
- 3 ,
- 10 ,
- 2 ,
- 11 ,
- 1 ,
- 10 ,
- 5 ,
- } ,
-
- .write_dq_bit_delay = {
- 77 ,
- 75 ,
- 80 ,
- 79 ,
- 84 ,
- 84 ,
- 84 ,
- 83 ,
- 79 ,
- 60 ,
- 62 ,
- 67 ,
- 65 ,
- 69 ,
- 69 ,
- 70 ,
- 70 ,
- 65 ,
- 60 ,
- 61 ,
- 67 ,
- 65 ,
- 69 ,
- 69 ,
- 69 ,
- 69 ,
- 65 ,
- 75 ,
- 74 ,
- 72 ,
- 79 ,
- 74 ,
- 80 ,
- 79 ,
- 79 ,
- 76 ,
- 76 ,
- 73 ,
- 79 ,
- 77 ,
- 82 ,
- 82 ,
- 82 ,
- 82 ,
- 78 ,
- 61 ,
- 63 ,
- 67 ,
- 65 ,
- 70 ,
- 70 ,
- 71 ,
- 70 ,
- 66 ,
- 61 ,
- 63 ,
- 68 ,
- 66 ,
- 71 ,
- 71 ,
- 70 ,
- 70 ,
- 66 ,
- 80 ,
- 78 ,
- 77 ,
- 82 ,
- 78 ,
- 84 ,
- 84 ,
- 84 ,
- 80 ,
- } ,
-
- .read_dq_bit_delay = {
- 4 ,
- 0 ,
- 18 ,
- 12 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 10 ,
- 8 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 4 ,
- 14 ,
- 12 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 10 ,
- 2 ,
- 0 ,
- 18 ,
- 0 ,
- 10 ,
- 10 ,
- 10 ,
- 0 ,
- 6 ,
- 0 ,
- 16 ,
- 14 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 2 ,
- 0 ,
- 10 ,
- 10 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 2 ,
- 12 ,
- 12 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 0 ,
- 10 ,
- 4 ,
- 0 ,
- 16 ,
- 0 ,
- 10 ,
- 10 ,
- 10 ,
- 0 ,
- } ,
-
- .read_dqs_gate_delay = {
- 375 ,
- 375 ,
- 367 ,
- 367 ,
- 363 ,
- 363 ,
- 371 ,
- 371 ,
- 379 ,
- 379 ,
- 371 ,
- 371 ,
- 371 ,
- 371 ,
- 381 ,
- 381 ,
- } ,
-
- .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS|DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ|
- DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS|DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ
- ,
- */
-///*
- .read_dqs_delay = {
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- 0x82 ,
- },
- .write_dq_bit_delay = {
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- 0x8002 ,
- } ,
-
- .dq_dqs_delay_flag = DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS | DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ,
- //*/
-},
+},
+*/
{
/* g12a Y2 dongle */
.board_id = CONFIG_BOARD_ID_MASK,
@@ -727,8 +391,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -798,8 +462,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12a_u221_v1/firmware/timing.c b/board/amlogic/g12a_u221_v1/firmware/timing.c
index 6642e98fce..ba1f632cbc 100644
--- a/board/amlogic/g12a_u221_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u221_v1/firmware/timing.c
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -147,8 +147,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -230,8 +230,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -303,8 +303,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -374,8 +374,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
diff --git a/board/amlogic/g12b_skt_v1/firmware/timing.c b/board/amlogic/g12b_skt_v1/firmware/timing.c
index a67f508fd9..dece6dc9b7 100644
--- a/board/amlogic/g12b_skt_v1/firmware/timing.c
+++ b/board/amlogic/g12b_skt_v1/firmware/timing.c
@@ -61,6 +61,82 @@
ddr_set_t __ddr_setting[] = {
{
/* ddr4 */
+ ///*
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1200, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .imem_load_addr = 0xFFFC0000, //sram
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 1,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 48,
+ .soc_data_drv_ohm_n = 48,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 48,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //60,
+ .dram_ac_odt_ohm = 0,
+ .dram_data_wr_odt_ohm = 120,
+ //.max_core_timmming_frequency=1400,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 820,//700,
+ .vref_dram_permil = 785,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32+10,32+0,32+15,32+5,32,32,32+25,32+20,32+10,32},
+ //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d = 1,
+},
+//*/
+{
+ /* ddr4 */
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
@@ -78,8 +154,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -148,8 +224,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -232,8 +308,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -306,8 +382,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
diff --git a/board/amlogic/g12b_w400_v1/firmware/timing.c b/board/amlogic/g12b_w400_v1/firmware/timing.c
index fae427d528..c904361cff 100644
--- a/board/amlogic/g12b_w400_v1/firmware/timing.c
+++ b/board/amlogic/g12b_w400_v1/firmware/timing.c
@@ -65,7 +65,7 @@ ddr_set_t __ddr_setting[] = {
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
.DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {1200, 0, 0, 0},
+ .DRAMFreq = {1320, 0, 0, 0},
.ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
@@ -78,8 +78,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -148,8 +148,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -232,8 +232,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -307,8 +307,8 @@ ddr_set_t __ddr_setting[] = {
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
diff --git a/board/amlogic/tl1_skt_v1/firmware/timing.c b/board/amlogic/tl1_skt_v1/firmware/timing.c
index c52e5745fb..45a1f23f08 100644
--- a/board/amlogic/tl1_skt_v1/firmware/timing.c
+++ b/board/amlogic/tl1_skt_v1/firmware/timing.c
@@ -268,9 +268,9 @@ ddr_set_t __ddr_setting[] = {
.ddr_start_offset = CFG_DDR_START_OFFSET,
.DisabledDbyte = 0xf0,
.Is2Ttiming = 1,
- .HdtCtrl = 0x5,//0xC8,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB =0,// 1024,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
.phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
.dfi_odt_config = 0x0c0c,
diff --git a/common/cmd_ddr_test.c b/common/cmd_ddr_test.c
index 1b14987d22..fb5127803f 100644
--- a/common/cmd_ddr_test.c
+++ b/common/cmd_ddr_test.c
@@ -1,21 +1,37 @@
-#include <common.h>
-//#include <asm/arch/secure_apb.h>
-
-
-//#include<stdio.h>
-
-//#include <asm/io.h>
-//#include <asm/arch/io.h>
-//#include <asm/arch/register.h>
-//#include <asm/arch-g9tv/mmc.h> //jiaxing debug
-
-//extern void aml_cache_disable(void);
-//#ifndef char* itoa(intnum,char*str,intradix)
-
+#include <common.h>
+#include <u-boot/sha256.h>
+//#include <asm/arch/secure_apb.h>
+
+//#include<stdio.h>
+
+//#include <asm/io.h>
+//#include <asm/arch/io.h>
+//#include <asm/arch/register.h>
+//#include <asm/arch-g9tv/mmc.h> //jiaxing debug
+
+//extern void aml_cache_disable(void);
+//#ifndef char* itoa(intnum,char*str,intradix)
+
+
+//#define USE_FOR_NEWMAN
+//#define USE_FOR_UBOOT_2018
+#ifdef USE_FOR_NEWMAN
+///*
+int setenv(const char *varname, const char *varvalue)
+{
+return 1;
+}
+
+char *getenv(const char *name)
+{
+ return NULL;
+}
+//*/
+#endif
#define DWC_AC_PINMUX_TOTAL 28
-#define DWC_DFI_PINMUX_TOTAL 26
-
+#define DWC_DFI_PINMUX_TOTAL 26
+
//#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
#define DDR_STICKY_MAGIC_NUMBER 0x20180000
#define DDR_CHIP_ID 0x30
@@ -26,94 +42,95 @@
#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
-#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
-#define CONFIG_DDR_TYPE_DDR3 0
-#define CONFIG_DDR_TYPE_DDR4 1
-#define CONFIG_DDR_TYPE_LPDDR4 2
-#define CONFIG_DDR_TYPE_LPDDR3 3
-#define CONFIG_DDR_TYPE_LPDDR2 4
-//#define CONFIG_DDR_TYPE_LPDDR4X 5
-#define CONFIG_DDR_TYPE_AUTO 0xf
-#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
-
-#define CONFIG_DDR0_16BIT_CH0 0x1
-#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
-#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
-#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
-#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
-#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
-#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
-#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
-
-/*
-static uint32_t ddr_rd_16bit_on_32reg(uint32_t addr)
-{
-uint32_t read_value=0;
-uint32_t addr_t=((addr>>2) << 2);
-read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
-read_value=(read_value>>((addr%4)<<3))&0xffff;
-return read_value;
-
-}
-static uint32_t ddr_wr_16bit_on_32reg(uint32_t addr,uint32_t value)
-{
-uint32_t read_value=0;
-uint32_t write_value=0;
-uint32_t addr_t=((addr>>2) << 2);
-uint32_t offset=((addr%4)<<3);
-read_value= *(volatile uint32_t *)(( unsigned long )(addr_t));
-write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
- *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
-
-return write_value;
-
-}
-*/
-static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
-{
- uint32_t read_value=0;
- uint32_t addr_t=0;
- uint32_t offset=0;
- if(size==8){
- offset=((offset_index%4)<<3);
- addr_t=(base_addr+((offset_index>>2) << 2));
- read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
- read_value=(read_value>>offset)&0xff;
-
- }
- if(size==16){
- offset=((offset_index%2)<<4);
- addr_t=(base_addr+((offset_index>>1) << 2));
- read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
- read_value=(read_value>>offset)&0xffff;
- }
- return read_value;
-
-}
-static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
-{
- uint32_t read_value=0;
- uint32_t write_value=0;
- uint32_t addr_t=0;
- uint32_t offset=0;
- if(size==8){
- offset=((offset_index%4)<<3);
- addr_t=(base_addr+((offset_index>>2) << 2));
- read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
- write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
- }
- if(size==16){
- offset=((offset_index%2)<<4);
- addr_t=(base_addr+((offset_index>>1) << 2));
- read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
- write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
- }
- *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
- return write_value;
-}
-typedef struct ddr_set{
+#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+//#define CONFIG_DDR_TYPE_LPDDR4X 5
+#define CONFIG_DDR_TYPE_AUTO 0xf
+#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
+
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+
+/*
+static uint32_t ddr_rd_16bit_on_32reg(uint32_t addr)
+{
+uint32_t read_value=0;
+uint32_t addr_t=((addr>>2) << 2);
+read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
+read_value=(read_value>>((addr%4)<<3))&0xffff;
+return read_value;
+
+}
+static uint32_t ddr_wr_16bit_on_32reg(uint32_t addr,uint32_t value)
+{
+uint32_t read_value=0;
+uint32_t write_value=0;
+uint32_t addr_t=((addr>>2) << 2);
+uint32_t offset=((addr%4)<<3);
+read_value= *(volatile uint32_t *)(( unsigned long )(addr_t));
+write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
+ *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
+
+return write_value;
+
+}
+*/
+static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
+{
+ uint32_t read_value=0;
+ uint32_t addr_t=0;
+ uint32_t offset=0;
+ if(size==8){
+ offset=((offset_index%4)<<3);
+ addr_t=(base_addr+((offset_index>>2) << 2));
+ read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
+ read_value=(read_value>>offset)&0xff;
+
+ }
+ if(size==16){
+ offset=((offset_index%2)<<4);
+ addr_t=(base_addr+((offset_index>>1) << 2));
+ read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
+ read_value=(read_value>>offset)&0xffff;
+ }
+ return read_value;
+
+}
+static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
+{
+ uint32_t read_value=0;
+ uint32_t write_value=0;
+ uint32_t addr_t=0;
+ uint32_t offset=0;
+ if(size==8){
+ offset=((offset_index%4)<<3);
+ addr_t=(base_addr+((offset_index>>2) << 2));
+ read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
+ write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
+ }
+ if(size==16){
+ offset=((offset_index%2)<<4);
+ addr_t=(base_addr+((offset_index>>1) << 2));
+ read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
+ write_value=(value<<offset)|(read_value&(~(0xffff<<offset)));
+ }
+ *(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
+ return write_value;
+}
+typedef struct ddr_set{
unsigned int magic;
- unsigned int rsv_int0;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+// unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -171,7 +188,9 @@ typedef struct ddr_set{
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
- unsigned char phy_odt_config_rank[4];
+ unsigned char phy_odt_config_rank[2];
+ unsigned char rever1;
+ unsigned char rever2;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -254,24 +273,28 @@ typedef struct ddr_set{
unsigned short soc_data_slew_rate;
//system reserve,do not modify
unsigned short vref_output_permil; //phy
- //setting same with vref_dram_permil
+ //setting same with vref_dram_permil
unsigned short vref_receiver_permil; //soc
//soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short vref_dram_permil;
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
- unsigned short vref_reverse;
- //system reserve,do not modify
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
/* align8 */
- unsigned char ac_trace_delay[12];
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ unsigned char lpddr4_x8_mode;
//system reserve,do not modify ,take care ,please follow SI
unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
//use for lpddr3 /lpddr4 ca pinmux remap
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
- unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
- //system reserve,do not modify
- unsigned short dq_bdlr_org;
- unsigned char rsv_char1[2];
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;//dq_bdlr_org;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
//system reserve,do not modify
/* align8 */
@@ -288,19553 +311,19567 @@ typedef struct ddr_set{
//system reserve,do not modify
/* align8 */
- unsigned long rsv_long0[2];
+ //unsigned long rsv_long0[2];
/* v1 end */
- unsigned char dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
- /* v2 start */
- unsigned char dq_bit_delay[72];
+// /*
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[32];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned char retraining[16];
//override read bit delay
-// unsigned short dq_bdlr_org[2];
-// unsigned char dqs_adjust_line[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-}ddr_set_t;
-
-ddr_set_t p_ddr_set_t;
-
-char* itoa_ddr_test(int num,char*str,int radix)
-{/*索引表*/
- printf("\nitoa_ddr_test 1\n");
- char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
- unsigned unum;/*中间变量*/
- char temp;
- int i=0,j,k;
- /*确定unum的值*/
- if (radix == 10 && num<0) /*十进制负数*/
- {
- unum = (unsigned)-num;
- str[i++] = '-';
- }
- else
- unum = (unsigned)num;/*其他情况*/
- /*转换*/
- printf("\nitoa_ddr_test 2\n");
- printf("\nunum=0x%08x\n",unum);
- printf("\nunum2=0x%08x\n",(unum%(unsigned)radix));
- printf("\nradix=0x%08x\n",radix);
- str[0] = index[0];
- printf("\nitoa_ddr_test 22\n");
- unum /= radix;
- printf("\nitoa_ddr_test 23\n");
- do {
- str[i++] = index[unum%(unsigned)radix];
- unum /= radix;
- }while(unum);
- printf("\nitoa_ddr_test 3\n");
- str[i] = '\0';
- /*逆序*/
- if (str[0] == '-')
- k = 1;/*十进制负数*/
- else
- k = 0;
- printf("\nitoa_ddr_test 4\n");
- for (j = k;j <= (i-1)/2;j++)
- {
- temp = str[j];
- str[j] = str[i-1+k-j];
- str[i-1+k-j] = temp;
- }
- return str;
-}
-//#endif
-
-/*
-char *strsep(char **stringp, const char *delim)
-{
- char *s;
- const char *spanp;
- int c, sc;
- char *tok;
- if ((s = *stringp)== NULL)
- return (NULL);
- for (tok = s;;) {
- c = *s++;
- spanp = delim;
- do {
- if ((sc =*spanp++) == c) {
- if (c == 0)
- s = NULL;
- else
- s[-1] = 0;
- *stringp = s;
- return (tok);
- }
- } while (sc != 0);
- }
-
-}
-*/
-int TOLOWER(int ch)
-{
-
- if ((unsigned int)(ch - 'A') < 26u )
- ch += 'a' - 'A';
-
- return ch;
-}//大写字母转换为小写字母。
-
-int isxdigit(int ch)
-{
- return (unsigned int)( ch - '0') < 10u ||
- (unsigned int)((ch | 0x20) - 'a') < 6u;
-}//判断字符c是否为十六进制数字。
-//当c为A-F,a-f或0-9之间的十六进制数字时,返回非零值,否则返回零。
-int isdigit(int ch)
-{
- return (unsigned int)(ch - '0') < 10u;
-}//判断字符c是否为数字
-unsigned int simple_guess_base(const char *cp)
-{
- if (cp[0] == '0') {
- if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
- return 16;
- else
- // return 8;
- return 10;
- } else {
- return 10;
- }
-}
-unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
-{
- unsigned int result = 0;
- //printf("test sizeof(str_buf)==%d\n",1);
- if(cp == NULL) //jiaxing add 20170616
- return 0;
- if (!base)
- base = simple_guess_base(cp);
- if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
- cp += 2;
- if (base == 10) {
- while ((*cp)== '0')
- cp++;
- }
- while (isxdigit(*cp)) {//检查当前cp是否是个十六进制数值,不是直接返回0
- unsigned int value;
- value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
- if (value >= base)
- break;
- result = result * base + value;
- cp++;
- }
- if (endp)
- *endp = (char *)cp;
- return result;
-}
-unsigned int env_to_a_num(const char *env_name)
-{
- char *str_buf = NULL;
- char buf[48];
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
- unsigned int a_num = 0;
- char *endp;
-
- printf("str==%s\n",str_buf);
-
- a_num=simple_strtoull_ddr(str_buf, &endp, 0);
- printf("%s==0x%08x\n",str_buf,a_num);
-
- return a_num;
-}
-unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num)
-{
- char *str_buf=NULL;
- char buf[1024];
- //unsigned int str_to_numarry[48];
- //str_buf = (char *)malloc(sizeof(char)*1024);
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
-
- printf("str==%s\n",str_buf);
-
- sprintf(buf, "0x%08x", *a_num);
-
- printf( "%s==0x%08x", buf,*a_num);
- setenv(env_name, buf);
-
- run_command("save",0);
- return 1;
-}
-unsigned int env_to_num(const char *env_name,unsigned int *num_arry)
-{
- char *str_buf = NULL;
- char buf[1024];
- unsigned int str_to_numarry[48];
- //str_buf = (char *)malloc(sizeof(char)*1024);
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
-
- char * str[48];
- char *endp;
- int i;
- for (i = 0; i < 48; i++)
- str_to_numarry[i] = 0;
- printf("str==%s\n",str_buf);
- for (i = 0; i < 48; i++) {
- str[i] = strsep(&str_buf, ";");
- //str[i] = strsep(&str_buf, " ");
- if(str[i] == NULL)
- break;
- str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
- //printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
- //num_arry[i]=str_to_numarry[i];
- }
- for (i = 0; i < 48; i++) {
- printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
- num_arry[i] = str_to_numarry[i];
- }
- //num_arry=(unsigned int *)(&str_to_numarry);
- return 1;
-}
-
-unsigned int num_to_env(const char *env_name,unsigned int *num_arry)
-{
- char *str_buf=NULL;
- char buf[1024];
- int i;
- //unsigned int str_to_numarry[48];
- //str_buf = (char *)malloc(sizeof(char)*1024);
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
-
- //char * str[48];
- printf("str==%s\n",str_buf);
-
-
- sprintf(buf, "0x%08x", num_arry[0]);
- for (i = 1; i < 48; i++) {
- //num_arry[i]=0;
- sprintf(buf, "%s;0x%08x", buf,num_arry[i]);
- printf("%d %d\n", i,num_arry[i]);
- }
- //sprintf(str, "%lx", value);
- printf( "%s", buf);
- setenv(env_name, buf);
-
- run_command("save",0);
- //num_arry=(unsigned int *)(&str_to_numarry);
- return 1;
-}
-
-#define TDATA32F 0xffffffff
-#define TDATA32A 0xaaaaaaaa
-#define TDATA325 0x55555555
-#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2))
-//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567
-#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
-#define DMC_STICKY_G12A_0 ((0x0000 << 2) + 0xff638800)
-#define DMC_STICKY_MAGIC_0 0x12345678
-#define DMC_STICKY_MAGIC_1 0xabcdbead
-#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
-#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
-unsigned int dmc_sticky[64];
-unsigned int sticky_reg_base_add=0;
-
-//#define DDR_TEST_ACLCDLR
-unsigned int global_boot_times= 0;
-unsigned int watchdog_time_s= 20;
-unsigned int global_ddr_clk=1;
-unsigned int bdlr_100step=0;
-unsigned int ui_1_32_100step=0;
-unsigned int error_count =0;
-unsigned int error_outof_count_flag=0;
-unsigned int copy_test_flag = 0;
-unsigned int training_pattern_flag = 0;
-unsigned int test_start_addr=0x1080000;
-
-unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
-unsigned int dq_lcd_bdl_value_bdlr0_org_a;
-unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
-unsigned int dq_lcd_bdl_value_bdlr0_min_a;
-unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
-unsigned int dq_lcd_bdl_value_bdlr0_max_a;
-unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
-unsigned int dq_lcd_bdl_value_bdlr0_status_a;
-
-unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
-unsigned int dq_lcd_bdl_value_bdlr0_org_b;
-unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
-unsigned int dq_lcd_bdl_value_bdlr0_min_b;
-unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
-unsigned int dq_lcd_bdl_value_bdlr0_max_b;
-
-unsigned int dq_lcd_bdl_value_wdq_org_a[4];
-unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
-unsigned int dq_lcd_bdl_value_wdq_min_a[4];
-unsigned int dq_lcd_bdl_value_wdq_max_a[4];
-unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
-unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
-unsigned int dq_lcd_bdl_value_wdq_status_a[4];
-unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
-
-unsigned int dq_lcd_bdl_value_wdq_org_b[4];
-unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
-unsigned int dq_lcd_bdl_value_wdq_min_b[4];
-unsigned int dq_lcd_bdl_value_wdq_max_b[4];
-unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
-unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
-unsigned int dq_lcd_bdl_value_wdq_status_b[4];
-unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
-unsigned int acbdlr0_9_reg_org[10];
-unsigned int acbdlr0_9_reg_setup_max[40];
-unsigned int acbdlr0_9_reg_hold_max[40];
-unsigned int acbdlr0_9_reg_setup_time[40];
-unsigned int acbdlr0_9_reg_hold_time[40];
-// unsigned int data_bdlr0_5_reg_org[6];
-unsigned int data_bdlr0_5_reg_org[28];//4//4lane
-unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr
-unsigned int bdlr0_9_reg_hold_max[24*4];
-unsigned int bdlr0_9_reg_setup_time[24*4];
-unsigned int bdlr0_9_reg_hold_time[24*4];
-
-#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
-#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
-
-#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
-#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
-
-//#define CONFIG_DDR_CMD_BDL_TUNE
-//#define CONFIG_CMD_DDR_TEST
-
-#ifndef CONFIG_CHIP
-//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
-#define CHIP_OLD 0
-#define CHIP_TXLX 1
-#define CHIP_A113 2
-#define CHIP_G12 3
-#define CONFIG_CHIP CHIP_G12// CHIP_OLD//
-#endif
-
-#define P_DDR_PHY_DEFAULT 0
-#define P_DDR_PHY_GX_BABY 1
-#define P_DDR_PHY_GX_TV_BABY 2
-#define P_DDR_PHY_905X 3
-
-//#define P_DDR_PHY_OLD_TAG 0
-#define P_DDR_PHY_G12 4
-
-#if (CONFIG_CHIP>=CHIP_G12)
-#define CONFIG_DDR_PHY P_DDR_PHY_G12
-#else
-//#define CONFIG_CHIP CHIP_OLD//
-//#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
-//#define CONFIG_DDR_PHY P_DDR_PHY_G12//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
-#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
-//#define CONFIG_DDR_PHY_NEW_TAG1 P_DDR_PHY_G12
-#endif
-
-#define G12_AM_DDR_PLL_CNTL0 0xff638c00
-
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
-#include <asm/arch/secure_apb.h>
-#endif
-
-#define PATTERN_USE_DDR_DES
-#define USE_64BIT_POINTER
-//#define USE_32BIT_POINTER
-#ifdef USE_64BIT_POINTER
-#define p_convter_int(a) ( unsigned int )( unsigned long )(a)
-#define int_convter_p(a) ( unsigned long )(a)
-
-#else
-#define p_convter_int(a) ( unsigned int )(a)
-#define int_convter_p(a) ( unsigned int )(a)
-#endif
-
-#ifdef PATTERN_USE_DDR_DES
-#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d])
-#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d])))
-#define des_xor_pattern(a,b) ( a^b)
-//des[temp_i]^pattern_2[temp_k][temp_i]
-#else
-#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d]
-#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d])
-#define des_xor_pattern(a,b) (a&0+b)
-#endif
-
-
-#define DDR_LCDLR_CK_USE_FAST_PATTERN
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
-#define DDR_PREFETCH_CACHE
-#endif
-#ifdef DDR_PREFETCH_CACHE
-#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
-#else
-#define ddr_pld_cache(P)
-#endif
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
-#define DDR0_PUB_REG_BASE 0xc8836000
-#define DDR1_PUB_REG_BASE 0xc8836000
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0x2000
-#define P_DDR0_CLK_CTRL 0xc8836c00
-#define P_DDR1_CLK_CTRL 0xc8836c00
-#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
-#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8836c00))
-#define CLOSE_CHANNEL_A_PHY_CLK() (writel((5), 0xc8836c00))
-#define CLOSE_CHANNEL_B_PHY_CLK() (writel((5), 0xc8836c00))
-// #define P_ISA_TIMERE 0xc1109988
-// #define get_us_time() (readl(P_ISA_TIMERE))
-#define AM_DDR_PLL_CNTL 0xc8836800
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
-
-#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
-#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
-#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
-
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
-#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
-//0x98 reserved)
-#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
-#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
-//0x9c reserved)
-#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
-#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
-#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
-#define ACBDLR_MAX 0X1F
-#define ACLCDLR_MAX 0XFF
-#define DQBDLR_MAX 0X1F
-#define DQLCDLR_MAX 0XFF
-#define DXNGTR_MAX 0X7
-#define ACBDLR_NUM 10
-#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
-
-
-#define DMC_REG_BASE 0xc8838000
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
- //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
- //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
- //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
- //bit 19:16. qos monitor channel select. select one at one time only.
- //bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
- // qos_mon_clk_timer. How long to measure the bandwidth.
-
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
- // at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
- // at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
-
-
-#elif (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY)
-#define DDR0_PUB_REG_BASE 0xc8836000
-#define DDR1_PUB_REG_BASE 0xc8837000
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0x1000
-#define P_DDR0_CLK_CTRL 0xc8836c00
-#define P_DDR1_CLK_CTRL 0xc8836c00
-#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
-#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8837c00))
-#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8836c00))
-#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8837c00))
-// #define P_ISA_TIMERE 0xc1109988
-// #define get_us_time() (readl(P_ISA_TIMERE) )
-#define AM_DDR_PLL_CNTL 0xc8836800
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
-#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
-#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
-#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
-
-#define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2))
-//0x94 reserved)
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
-#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
-//0x98 reserved)
-#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
-#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
-//0x9c reserved)
-#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
-#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
-#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
-#define ACBDLR_MAX 0X1F
-#define ACLCDLR_MAX 0XFF
-#define DQBDLR_MAX 0X1F
-#define DQLCDLR_MAX 0XFF
-#define DXNGTR_MAX 0X7
-#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
-#define DMC_REG_BASE 0xc8838000
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
- //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
- //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
- //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
- //bit 19:16. qos monitor channel select. select one at one time only.
- //bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
- // qos_mon_clk_timer. How long to measure the bandwidth.
-
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
- // at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
- // at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
- // at the test period, the granted data cycles for the selected channel and ports.
-
-#elif (CONFIG_DDR_PHY == P_DDR_PHY_905X)
-
- // #define P_ISA_TIMERE 0xc1109988
- // #define get_us_time() (readl(P_ISA_TIMERE) )
-#if CONFIG_CHIP >=CHIP_TXLX
-#define DDR0_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
-#define DDR1_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0//0x1000
-#define MMC_REG_BASE ((0x0000 << 2) + 0xff637000) // #define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xff637000) 0xc8837000
-#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
-#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
-#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
-#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-
-#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
-#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
-#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
-
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
-#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
-
-#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
-#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
-
-#define DDR0_PUB_DX0GCR0 ((0x01c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x0200 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x0240 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
-
-#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
-
-#define ACBDLR_MAX 0X3F
-#define ACLCDLR_MAX 0X1FF
-#define DQBDLR_MAX 0X3F
-#define DQLCDLR_MAX 0X1FF
-#define DXNGTR_MAX 0X1F
-
- // #define DMC_REG_BASE MMC_REG_BASE
-
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
- //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
- //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
- //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
- //bit 19:16. qos monitor channel select. select one at one time only.
- //bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
-// qos_mon_clk_timer. How long to measure the bandwidth.
-
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
- // at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
- // at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
- // at the test period, the granted data cycles for the selected channel and ports.
-
-#else
-#define DDR0_PUB_REG_BASE 0xc8836000
-#define DDR1_PUB_REG_BASE 0xc8836000
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0//0x1000
-#define MMC_REG_BASE 0xc8837000
-#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
-#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
-#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
-#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-
-#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
-#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
-#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
-
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
-#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
-
-#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
-#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
-
-#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
-
-#define ACBDLR_MAX 0X3F
-#define ACLCDLR_MAX 0X1FF
-#define DQBDLR_MAX 0X3F
-#define DQLCDLR_MAX 0X1FF
-#define DXNGTR_MAX 0X1F
-#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
-#ifndef DMC_REG_BASE
-#define DMC_REG_BASE MMC_REG_BASE
-#endif
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
-//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
-//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
-//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
-//bit 19:16. qos monitor channel select. select one at one time only.
-//bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
-// qos_mon_clk_timer. How long to measure the bandwidth.
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
-// at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
-// at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
-// at the test period, the granted data cycles for the selected channel and ports.
-#endif
-
-#elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
-
-#define DDR0_PUB_REG_BASE 0xc8001000 //0xc8836000
-#define DDR1_PUB_REG_BASE 0xc8001000 // 0xc8836000
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0x2000
-#define P_DDR0_CLK_CTRL 0xc8000800
-#define P_DDR1_CLK_CTRL 0xc8002800
-#define OPEN_CHANNEL_A_PHY_CLK() (writel((0x12b), 0xc8000800))
-#define OPEN_CHANNEL_B_PHY_CLK() (writel((0x12b), 0xc8002800))
-#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8000800))
-#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8002800))
-// #define P_ISA_TIMERE 0xc1109988
-// #define get_us_time() (readl(P_ISA_TIMERE))
-
-#define PREG_STICKY_REG0 0xc1100000+(0x207c<<2)
-#define PREG_STICKY_REG1 0xc1100000+(0x207d<<2)
-#define WATCHDOG_TC 0xc1100000+(0x2640<<2)// 0x2640
-
-#define AM_DDR_PLL_CNTL 0xc8000400
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x91<<2))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x92<<2))
-#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x91<<2))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x92<<2))
-#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
-#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
-#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
-#define ACBDLR_MAX 0X1F
-#define ACLCDLR_MAX 0XFF
-#define DQBDLR_MAX 0X1F
-#define DQLCDLR_MAX 0XFF
-#define DXNGTR_MAX 0X7
-#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
-#define DMC_REG_BASE 0xc8006000
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
-//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
-//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
-//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
-//bit 19:16. qos monitor channel select. select one at one time only.
-//bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
-// qos_mon_clk_timer. How long to measure the bandwidth.
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
-// at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
-// at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
-// at the test period, the granted data cycles for the selected channel and ports.
-
-
-
-#elif (CONFIG_DDR_PHY == P_DDR_PHY_G12)
-#define DDR0_PUB_REG_BASE 0xff636000
-#define DDR1_PUB_REG_BASE 0xff636000
-#define CHANNEL_A_REG_BASE 0
-#define CHANNEL_B_REG_BASE 0//0x1000
-#define MMC_REG_BASE 0xff637000
-#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
-#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
-#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
-#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
-
-#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
-#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
-#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
-#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
-#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
-#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
-
-#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
-#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
-#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
-
-#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
-#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
-#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
-
-#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
-#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
-
-#define ACBDLR_MAX 0X3F
-#define ACLCDLR_MAX 0X1FF
-#define DQBDLR_MAX 0X3F
-#define DQLCDLR_MAX 0X1FF
-#define DXNGTR_MAX 0X1F
-#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
-#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
-#ifndef DMC_REG_BASE
-#define DMC_REG_BASE MMC_REG_BASE
-#endif
-#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
-//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
-//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
-//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
-//bit 19:16. qos monitor channel select. select one at one time only.
-//bit 15:0. port select for the selected channel.
-#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
-// qos_mon_clk_timer. How long to measure the bandwidth.
-
-
-#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
-// at the test period, the whole MMC request time.
-#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
- // at the test period, the whole MMC granted data cycles. 64bits unit.
-#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
- // at the test period, the granted data cycles for the selected channel and ports.
-#endif
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
-#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
-#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 ))// R/W - PHY General Configuration Register 0
-#define DDR0_PUB_PGCR1 ( DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
-#define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
-#define DDR0_PUB_PGCR3 ( DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
-#define DDR0_PUB_PGCR4 ( DDR0_PUB_REG_BASE + ( 0x008 << 2 )) // R/W - PHY General Configuration Register 4
-#define DDR0_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
-#define DDR0_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
-#define DDR0_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
-#define DDR0_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 )) // R/W - PHY General Configuration Register 8
-
-#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
-#define DDR1_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 )) // R/W - PHY General Configuration Register 0
-#define DDR1_PUB_PGCR1 (DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
-#define DDR1_PUB_PGCR2 ( DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
-#define DDR1_PUB_PGCR3 (DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
-#define DDR1_PUB_PGCR4 (DDR0_PUB_REG_BASE + ( 0x008 << 2 ) )// R/W - PHY General Configuration Register 4
-#define DDR1_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
-#define DDR1_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
-#define DDR1_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
-#define DDR1_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 ) )// R/W - PHY General Configuration Register 8
-
-#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE + ( 0x1d0 << 2 ))
-#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE + ( 0x1d1 << 2 ))
-#define DDR0_PUB_DX0BDLR2 ( DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
-#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
-#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2 ))
-#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2 ))
-#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2 ))
-#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE + ( 0x1e0 << 2 ))
-#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
-#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE + ( 0x1e2 << 2 ))
-#define DDR0_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
-#define DDR0_PUB_DX0LCDLR4 (DDR0_PUB_REG_BASE + ( 0x1e4 << 2 ))
-#define DDR0_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
-#define DDR0_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
-#define DDR0_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2) )
-#define DDR0_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
-#define DDR0_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
-#define DDR0_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
-#define DDR0_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
-
-#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2) )
-#define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2) )
-#define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2) )
-#define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2) )
-#define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2) )
-#define DDR0_PUB_DX1BDLR5 ( DDR0_PUB_REG_BASE + ( 0x216 << 2) )
-#define DDR0_PUB_DX1BDLR6 ( DDR0_PUB_REG_BASE + ( 0x218 << 2) )
-#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2) )
-#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2) )
-#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE + ( 0x222 << 2) )
-#define DDR0_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2) )
-#define DDR0_PUB_DX1LCDLR4 (DDR0_PUB_REG_BASE + ( 0x224 << 2) )
-#define DDR0_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2) )
-#define DDR0_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2) )
-#define DDR0_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2) )
-#define DDR0_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
-#define DDR0_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2) )
-#define DDR0_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2) )
-#define DDR0_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2) )
-
-#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2) )
-#define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2) )
-#define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2) )
-#define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2) )
-#define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2) )
-#define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2) )
-#define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2) )
-#define DDR0_PUB_DX2LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x260 << 2) )
-#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2) )
-#define DDR0_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2) )
-#define DDR0_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2) )
-#define DDR0_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2) )
-#define DDR0_PUB_DX2LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x265 << 2) )
-#define DDR0_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2) )
-#define DDR0_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2) )
-#define DDR0_PUB_DX2GTR0 ( DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
-#define DDR0_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2) )
-#define DDR0_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2) )
-#define DDR0_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2) )
-
-#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2) )
-#define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2) )
-#define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2) )
-#define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2) )
-#define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2) )
-#define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2) )
-#define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2) )
-#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2) )
-#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2) )
-#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE + ( 0x2a2 << 2) )
-#define DDR0_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2) )
-#define DDR0_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2) )
-#define DDR0_PUB_DX3LCDLR5 (DDR0_PUB_REG_BASE + ( 0x2a5 << 2) )
-#define DDR0_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2) )
-#define DDR0_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2) )
-#define DDR0_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
-#define DDR0_PUB_DX3GTR1 ( DDR0_PUB_REG_BASE + ( 0x2b1 << 2) )
-#define DDR0_PUB_DX3GTR2 ( DDR0_PUB_REG_BASE + ( 0x2b2 << 2) )
-#define DDR0_PUB_DX3GTR3 ( DDR0_PUB_REG_BASE + ( 0x2b3 << 2) )
-
-#define DDR1_PUB_DX0BDLR0 ( DDR0_PUB_REG_BASE + ( 0x1d0 << 2) )
-#define DDR1_PUB_DX0BDLR1 ( DDR0_PUB_REG_BASE + ( 0x1d1 << 2) )
-#define DDR1_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
-#define DDR1_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
-#define DDR1_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2) )
-#define DDR1_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2) )
-#define DDR1_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2) )
-#define DDR1_PUB_DX0LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x1e0 << 2) )
-#define DDR1_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
-#define DDR1_PUB_DX0LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x1e2 << 2) )
-#define DDR1_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
-#define DDR1_PUB_DX0LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x1e4 << 2) )
-#define DDR1_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
-#define DDR1_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
-#define DDR1_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2 ))
-#define DDR1_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
-#define DDR1_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
-#define DDR1_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
-#define DDR1_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
-
-#define DDR1_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2 ))
-#define DDR1_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2 ))
-#define DDR1_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2 ))
-#define DDR1_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2 ))
-#define DDR1_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2 ))
-#define DDR1_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE + ( 0x216 << 2 ))
-#define DDR1_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE + ( 0x218 << 2 ))
-#define DDR1_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2 ))
-#define DDR1_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2 ))
-#define DDR1_PUB_DX1LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x222 << 2 ))
-#define DDR1_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2 ))
-#define DDR1_PUB_DX1LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x224 << 2 ))
-#define DDR1_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2 ))
-#define DDR1_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2 ))
-#define DDR1_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2 ))
-#define DDR1_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
-#define DDR1_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2 ))
-#define DDR1_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2 ))
-#define DDR1_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2 ))
-
-#define DDR1_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2 ))
-#define DDR1_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2 ))
-#define DDR1_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2 ))
-#define DDR1_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2 ))
-#define DDR1_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2 ))
-#define DDR1_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2 ))
-#define DDR1_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2 ))
-#define DDR1_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE + ( 0x260 << 2 ))
-#define DDR1_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2 ))
-#define DDR1_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2 ))
-#define DDR1_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2 ))
-#define DDR1_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2 ))
-#define DDR1_PUB_DX2LCDLR5 (DDR0_PUB_REG_BASE + ( 0x265 << 2 ))
-#define DDR1_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2 ))
-#define DDR1_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2 ))
-#define DDR1_PUB_DX2GTR0 (DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
-#define DDR1_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2 ))
-#define DDR1_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2 ))
-#define DDR1_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2 ))
-
-#define DDR1_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2 ))
-#define DDR1_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2 ))
-#define DDR1_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2 ))
-#define DDR1_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2 ))
-#define DDR1_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2 ))
-#define DDR1_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2 ))
-#define DDR1_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2 ))
-#define DDR1_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2 ))
-#define DDR1_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2 ))
-#define DDR1_PUB_DX3LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x2a2 << 2 ))
-#define DDR1_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2 ))
-#define DDR1_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2 ))
-#define DDR1_PUB_DX3LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x2a5 << 2 ))
-#define DDR1_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2 ))
-#define DDR1_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2 ))
-#define DDR1_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
-#define DDR1_PUB_DX3GTR1 (DDR0_PUB_REG_BASE + ( 0x2b1 << 2 ))
-#define DDR1_PUB_DX3GTR2 (DDR0_PUB_REG_BASE + ( 0x2b2 << 2 ))
-#define DDR1_PUB_DX3GTR3 (DDR0_PUB_REG_BASE + ( 0x2b3 << 2 ))
-
-
-#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 )) // R/W - LC Delay Line Present Register
-#define DDR0_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
-#define DDR0_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
-#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE + ( 0x150 << 2 )) // R/W - AC Bit Delay Line Register 0
-#define DDR0_PUB_ACBDLR3 ( DDR0_PUB_REG_BASE + ( 0x153 << 2 ) ) // R/W - AC Bit Delay Line Register 3
-
-#define DDR1_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 ) )// R/W - LC Delay Line Present Register
-#define DDR1_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
-#define DDR1_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
-#define DDR1_PUB_ACBDLR0 ( DDR0_PUB_REG_BASE + ( 0x150 << 2 ) )// R/W - AC Bit Delay Line Register 0
-
-
-#define DDR0_PUB_ACMDLR DDR0_PUB_ACMDLR0
-#define DDR1_PUB_ACMDLR DDR1_PUB_ACMDLR0
-#define DDR0_PUB_DX0GTR DDR0_PUB_DX0GTR0
-#define DDR0_PUB_DX1GTR DDR0_PUB_DX1GTR0
-#define DDR0_PUB_DX2GTR DDR0_PUB_DX2GTR0
-#define DDR0_PUB_DX3GTR DDR0_PUB_DX3GTR0
-#define DDR1_PUB_DX0GTR DDR0_PUB_DX0GTR0
-#define DDR1_PUB_DX1GTR DDR0_PUB_DX1GTR0
-#define DDR1_PUB_DX2GTR DDR0_PUB_DX2GTR0
-#define DDR1_PUB_DX3GTR DDR0_PUB_DX3GTR0
-
-
-#define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
-#define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
-#define DDR0_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 ) )// R/W - VREF Training Control Register 0
-#define DDR0_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
-#define DDR1_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
-#define DDR1_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
-#define DDR1_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 )) // R/W - VREF Training Control Register 0
-#define DDR1_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
-
-//#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
-//#define DDR1_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
-#define DDR0_PUB_DX0GCR6 ( DDR0_PUB_REG_BASE + ( 0x1c6 << 2 ) )
-#define DDR0_PUB_DX1GCR6 ( DDR0_PUB_REG_BASE + ( 0x206 << 2 ) )
-#define DDR0_PUB_DX2GCR6 ( DDR0_PUB_REG_BASE + ( 0x246 << 2 ) )
-#define DDR0_PUB_DX3GCR6 ( DDR0_PUB_REG_BASE + ( 0x286 << 2 ) )
-#define DDR0_PUB_DCR ( DDR0_PUB_REG_BASE + ( 0x040 << 2 ) ) // R/W - DRAM Configuration Register
-#define DDR0_PUB_MR0 ( DDR0_PUB_REG_BASE + ( 0x060 << 2 ) ) // R/W - Mode Register
-#define DDR0_PUB_MR1 ( DDR0_PUB_REG_BASE + ( 0x061 << 2 ) ) // R/W - Extended Mode Register
-#define DDR0_PUB_MR2 ( DDR0_PUB_REG_BASE + ( 0x062 << 2 ) ) // R/W - Extended Mode Register 2
-#define DDR0_PUB_MR3 ( DDR0_PUB_REG_BASE + ( 0x063 << 2 ) ) // R/W - Extended Mode Register 3
-#define DDR0_PUB_MR4 ( DDR0_PUB_REG_BASE + ( 0x064 << 2 ) ) // R/W - Extended Mode Register 4
-#define DDR0_PUB_MR5 ( DDR0_PUB_REG_BASE + ( 0x065 << 2 ) ) // R/W - Extended Mode Register 5
-#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
-#define DDR0_PUB_MR7 ( DDR0_PUB_REG_BASE + ( 0x067 << 2 ) ) // R/W - Extended Mode Register 7
-#define DDR0_PUB_MR11 ( DDR0_PUB_REG_BASE + ( 0x06B << 2 ) ) // R/W - Extended Mode Register 11
-#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x137 << 2 ) ) // R/W - Rank ID Register
-#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0x080 << 2 ) ) // R/W - Data Training Configuration Register
-#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x08C << 2 ) ) // R/W - Data Training Eye Data Register 0
-#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x08D << 2 ) ) // R/W - Data Training Eye Data Register 1
-#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x08E << 2 ) ) // R/W - Data Training Eye Data Register 2
-#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x08F << 2 ) ) // R/W - Vref Training Data Register
-#else
-
-#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
-#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2))
-#define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2))
-
-#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
-#define DDR1_PUB_PGCR0 (DDR1_PUB_REG_BASE+(0x02<<2))
-#define DDR1_PUB_PGCR1 (DDR1_PUB_REG_BASE+(0x03<<2))
-
-#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2))
-#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2))
-#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2))
-#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2))
-
-#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2))
-#define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2))
-#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2))
-#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2))
-#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2))
-#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2))
-
-#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2))
-#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2))
-#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2))
-#define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2))
-#define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2))
-#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2))
-#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2))
-#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2))
-#define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2))
-#define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2))
-#define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2))
-#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2))
-#define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2))
-#define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2))
-#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2))
-#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2))
-#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2))
-#define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2))
-#define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2))
-
-#define DDR1_PUB_DX0LCDLR0 (DDR1_PUB_REG_BASE+(0xAE<<2))
-#define DDR1_PUB_DX0LCDLR1 (DDR1_PUB_REG_BASE+(0xAF<<2))
-#define DDR1_PUB_DX0LCDLR2 (DDR1_PUB_REG_BASE+(0xB0<<2))
-#define DDR1_PUB_DX0MDLR (DDR1_PUB_REG_BASE+(0xB1<<2))
-#define DDR1_PUB_DX0GTR (DDR1_PUB_REG_BASE+(0xB2<<2))
-#define DDR1_PUB_DX1LCDLR0 (DDR1_PUB_REG_BASE+(0xCE<<2))
-#define DDR1_PUB_DX1LCDLR1 (DDR1_PUB_REG_BASE+(0xCF<<2))
-#define DDR1_PUB_DX1LCDLR2 (DDR1_PUB_REG_BASE+(0xD0<<2))
-#define DDR1_PUB_DX1MDLR (DDR1_PUB_REG_BASE+(0xD1<<2))
-#define DDR1_PUB_DX1GTR (DDR1_PUB_REG_BASE+(0xD2<<2))
-#define DDR1_PUB_DX2LCDLR0 (DDR1_PUB_REG_BASE+(0xEE<<2))
-#define DDR1_PUB_DX2LCDLR1 (DDR1_PUB_REG_BASE+(0xEF<<2))
-#define DDR1_PUB_DX2LCDLR2 (DDR1_PUB_REG_BASE+(0xF0<<2))
-#define DDR1_PUB_DX2MDLR (DDR1_PUB_REG_BASE+(0xF1<<2))
-#define DDR1_PUB_DX3LCDLR0 (DDR1_PUB_REG_BASE+(0x10E<<2))
-#define DDR1_PUB_DX3LCDLR1 (DDR1_PUB_REG_BASE+(0x10F<<2))
-#define DDR1_PUB_DX3LCDLR2 (DDR1_PUB_REG_BASE+(0x110<<2))
-#define DDR1_PUB_DX3MDLR (DDR1_PUB_REG_BASE+(0x111<<2))
-#define DDR1_PUB_DX3GTR (DDR1_PUB_REG_BASE+(0x112<<2))
-
-
-#define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2))
-#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2))
-#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2))
-#define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2))
-#define DDR1_PUB_ACMDLR (DDR1_PUB_REG_BASE+(0x0E<<2))
-#define DDR1_PUB_ACLCDLR (DDR1_PUB_REG_BASE+(0x0F<<2))
-#define DDR1_PUB_ACBDLR0 (DDR1_PUB_REG_BASE+(0x10<<2))
-
-#define DDR0_PUB_ACMDLR0 DDR0_PUB_ACMDLR
-#define DDR1_PUB_ACMDLR0 DDR1_PUB_ACMDLR
-#define DDR0_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
-#define DDR0_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
-#define DDR0_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
-#define DDR0_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
-#define DDR1_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
-#define DDR1_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
-#define DDR1_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
-#define DDR1_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
-#define DDR0_PUB_DCR (DDR0_PUB_REG_BASE+(0x22<<2))
-#define DDR0_PUB_MR0 (DDR0_PUB_REG_BASE+(0x27<<2))
-#define DDR0_PUB_MR1 (DDR0_PUB_REG_BASE+(0x28<<2))
-#define DDR0_PUB_MR2 (DDR0_PUB_REG_BASE+(0x29<<2))
-#define DDR0_PUB_MR3 (DDR0_PUB_REG_BASE+(0x2A<<2))
-#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Rank ID Register
-#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0<< 2 ) ) // R/W - Data Training Configuration Register
-#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 0
-#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Data Training Eye Data Register 1
-#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 2
-#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Vref Training Data Register
-
-#ifndef P_DDR0_CLK_CTRL
-#define P_DDR0_CLK_CTRL 0xc8000800
-#endif
-#ifndef P_DDR1_CLK_CTRL
-#define P_DDR1_CLK_CTRL 0xc8002800
-#endif
-
-#define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2))
-#define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2))
-#endif
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
-//unsigned int des[8];
-/*
- unsigned int pattern_1[4][8]=
- {
- 0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-0xff00ff00 ,
-
-};
-unsigned int pattern_2[4][8]={
-0x0001fe00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0002fd00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0004fb00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0008f700 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0010ef00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0020df00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0040bf00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x00807f00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-0x0000ff00 ,
-
-};
-unsigned int pattern_3[4][8]={
- 0x00010000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00020000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00040000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00080000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00100000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00200000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00400000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00800000 ,
- 0x00000000 ,
- 0x00000000 ,
- 0x00000000 ,
-};
-unsigned int pattern_4[4][8]={
- 0x51c8c049 ,
- 0x2d43592c ,
- 0x0777b50b ,
- 0x9cd2ebe5 ,
- 0xc04199d5 ,
- 0xdc968dc0 ,
- 0xb8ba8a33 ,
- 0x35e4327f ,
- 0x51c8c049 ,
- 0x2d43592c ,
- 0x0777b50b ,
- 0x9cd2ebe5 ,
- 0xc04199d5 ,
- 0xdc968dc0 ,
- 0xb8ba8a33 ,
- 0x35e4327f ,
- 0x51c8c049 ,
- 0x2d43592c ,
- 0x0777b50b ,
- 0x9cd2ebe5 ,
- 0xc04199d5 ,
- 0xdc968dc0 ,
- 0xb8ba8a33 ,
- 0x35e4327f ,
- 0x51c8c049 ,
- 0x2d43592c ,
- 0x0777b50b ,
- 0x9cd2ebe5 ,
- 0xc04199d5 ,
- 0xdc968dc0 ,
- 0xb8ba8a33 ,
- 0x35e4327f ,
-};
-unsigned int pattern_5[4][8]={
- 0xaec9c149 ,
- 0xd243592c ,
- 0xf877b50b ,
- 0x63d2ebe5 ,
- 0x3f439bd5 ,
- 0x23968dc0 ,
- 0x47ba8a33 ,
- 0xcae4327f ,
- 0xaeccc449 ,
- 0xd243592c ,
- 0xf877b50b ,
- 0x63d2ebe5 ,
- 0x3f4991d5 ,
- 0x23968dc0 ,
- 0x47ba8a33 ,
- 0xcae4327f ,
- 0xaed8d049 ,
- 0xd243592c ,
- 0xf877b50b ,
- 0x63d2ebe5 ,
- 0x3f61b9d5 ,
- 0x23968dc0 ,
- 0x47ba8a33 ,
- 0xcae4327f ,
- 0xae888049 ,
- 0xd243592c ,
- 0xf877b50b ,
- 0x63d2ebe5 ,
- 0x3fc119d5 ,
- 0x23968dc0 ,
- 0x47ba8a33 ,
- 0xcae4327f ,
-};
-unsigned int pattern_6[4][8]={
- 0xaec9c149 ,
- 0xd243a62c ,
- 0xf8774a0b ,
- 0x63d214e5 ,
- 0x3f4366d5 ,
- 0x239672c0 ,
- 0x47ba7533 ,
- 0xcae4cd7f ,
- 0xaecc3f49 ,
- 0xd243a62c ,
- 0xf8774a0b ,
- 0x63d214e5 ,
- 0x3f4966d5 ,
- 0x239672c0 ,
- 0x47ba7533 ,
- 0xcae4cd7f ,
- 0xaed83f49 ,
- 0xd243a62c ,
- 0xf8774a0b ,
- 0x63d214e5 ,
- 0x3f6166d5 ,
- 0x239672c0 ,
- 0x47ba7533 ,
- 0xcae4cd7f ,
- 0xae883f49 ,
- 0xd243a62c ,
- 0xf8774a0b ,
- 0x63d214e5 ,
- 0x3fc166d5 ,
- 0x239672c0 ,
- 0x47ba7533 ,
- 0xcae4cd7f ,
-
-};
-unsigned int des[8] ={
- 0xaec83f49,
- 0xd243a62c,
- 0xf8774a0b,
- 0x63d214e5,
- 0x3f4166d5,
- 0x239672c0,
- 0x47ba7533,
- 0xcae4cd7f,
-};
-*/
-/*
- unsigned int des[8] ;
- des[0] = 0xaec83f49;
- des[1] = 0xd243a62c;
- des[2] = 0xf8774a0b;
- des[3] = 0x63d214e5;
- des[4] = 0x3f4166d5;
- des[5] = 0x239672c0;
- des[6] = 0x47ba7533;
- des[7] = 0xcae4cd7f;
- pattern_1[0][0] = 0xff00ff00;
- pattern_1[0][1] = 0xff00ff00;
- pattern_1[0][2] = 0xff00ff00;
- pattern_1[0][3] = 0xff00ff00;
- pattern_1[0][4] = 0xff00ff00;
- pattern_1[0][5] = 0xff00ff00;
- pattern_1[0][6] = 0xff00ff00;
- pattern_1[0][7] = 0xff00ff00;
-
- pattern_1[1][0] = 0xff00ff00;
- pattern_1[1][1] = 0xff00ff00;
- pattern_1[1][2] = 0xff00ff00;
- pattern_1[1][3] = 0xff00ff00;
- pattern_1[1][4] = 0xff00ff00;
- pattern_1[1][5] = 0xff00ff00;
- pattern_1[1][6] = 0xff00ff00;
- pattern_1[1][7] = 0xff00ff00;
-
- pattern_1[2][0] = 0xff00ff00;
- pattern_1[2][1] = 0xff00ff00;
- pattern_1[2][2] = 0xff00ff00;
- pattern_1[2][3] = 0xff00ff00;
- pattern_1[2][4] = 0xff00ff00;
- pattern_1[2][5] = 0xff00ff00;
- pattern_1[2][6] = 0xff00ff00;
- pattern_1[2][7] = 0xff00ff00;
-
- pattern_1[3][0] = 0xff00ff00;
- pattern_1[3][1] = 0xff00ff00;
- pattern_1[3][2] = 0xff00ff00;
- pattern_1[3][3] = 0xff00ff00;
- pattern_1[3][4] = 0xff00ff00;
- pattern_1[3][5] = 0xff00ff00;
- pattern_1[3][6] = 0xff00ff00;
- pattern_1[3][7] = 0xff00ff00;
-
- pattern_2[0][0] = 0x0001fe00;
- pattern_2[0][1] = 0x0000ff00;
- pattern_2[0][2] = 0x0000ff00;
- pattern_2[0][3] = 0x0000ff00;
- pattern_2[0][4] = 0x0002fd00;
- pattern_2[0][5] = 0x0000ff00;
- pattern_2[0][6] = 0x0000ff00;
- pattern_2[0][7] = 0x0000ff00;
-
- pattern_2[1][0] = 0x0004fb00;
- pattern_2[1][1] = 0x0000ff00;
- pattern_2[1][2] = 0x0000ff00;
- pattern_2[1][3] = 0x0000ff00;
- pattern_2[1][4] = 0x0008f700;
- pattern_2[1][5] = 0x0000ff00;
- pattern_2[1][6] = 0x0000ff00;
- pattern_2[1][7] = 0x0000ff00;
-
- pattern_2[2][0] = 0x0010ef00;
- pattern_2[2][1] = 0x0000ff00;
- pattern_2[2][2] = 0x0000ff00;
- pattern_2[2][3] = 0x0000ff00;
- pattern_2[2][4] = 0x0020df00;
- pattern_2[2][5] = 0x0000ff00;
- pattern_2[2][6] = 0x0000ff00;
-pattern_2[2][7] = 0x0000ff00;
-
-pattern_2[3][0] = 0x0040bf00;
-pattern_2[3][1] = 0x0000ff00;
-pattern_2[3][2] = 0x0000ff00;
-pattern_2[3][3] = 0x0000ff00;
-pattern_2[3][4] = 0x00807f00;
-pattern_2[3][5] = 0x0000ff00;
-pattern_2[3][6] = 0x0000ff00;
-pattern_2[3][7] = 0x0000ff00;
-
-pattern_3[0][0] = 0x00010000;
-pattern_3[0][1] = 0x00000000;
-pattern_3[0][2] = 0x00000000;
-pattern_3[0][3] = 0x00000000;
-pattern_3[0][4] = 0x00020000;
-pattern_3[0][5] = 0x00000000;
-pattern_3[0][6] = 0x00000000;
-pattern_3[0][7] = 0x00000000;
-
-pattern_3[1][0] = 0x00040000;
-pattern_3[1][1] = 0x00000000;
-pattern_3[1][2] = 0x00000000;
-pattern_3[1][3] = 0x00000000;
-pattern_3[1][4] = 0x00080000;
- pattern_3[1][5] = 0x00000000;
- pattern_3[1][6] = 0x00000000;
- pattern_3[1][7] = 0x00000000;
-
- pattern_3[2][0] = 0x00100000;
- pattern_3[2][1] = 0x00000000;
- pattern_3[2][2] = 0x00000000;
- pattern_3[2][3] = 0x00000000;
- pattern_3[2][4] = 0x00200000;
- pattern_3[2][5] = 0x00000000;
- pattern_3[2][6] = 0x00000000;
- pattern_3[2][7] = 0x00000000;
-
- pattern_3[3][0] = 0x00400000;
- pattern_3[3][1] = 0x00000000;
- pattern_3[3][2] = 0x00000000;
- pattern_3[3][3] = 0x00000000;
- pattern_3[3][4] = 0x00800000;
- pattern_3[3][5] = 0x00000000;
- pattern_3[3][6] = 0x00000000;
- pattern_3[3][7] = 0x00000000;
-
-pattern_4[0][0] = 0x51c8c049 ;
-pattern_4[0][1] = 0x2d43592c ;
-pattern_4[0][2] = 0x0777b50b ;
-pattern_4[0][3] = 0x9cd2ebe5 ;
-pattern_4[0][4] = 0xc04199d5 ;
-pattern_4[0][5] = 0xdc968dc0 ;
-pattern_4[0][6] = 0xb8ba8a33 ;
-pattern_4[0][7] = 0x35e4327f ;
-
-pattern_4[1][0] = 0x51c8c049 ;
-pattern_4[1][1] = 0x2d43592c ;
-pattern_4[1][2] = 0x0777b50b ;
-pattern_4[1][3] = 0x9cd2ebe5 ;
-pattern_4[1][4] = 0xc04199d5 ;
-pattern_4[1][5] = 0xdc968dc0 ;
-pattern_4[1][6] = 0xb8ba8a33 ;
-pattern_4[1][7] = 0x35e4327f ;
-
-pattern_4[2][0] = 0x51c8c049 ;
-pattern_4[2][1] = 0x2d43592c ;
-pattern_4[2][2] = 0x0777b50b ;
-pattern_4[2][3] = 0x9cd2ebe5 ;
-pattern_4[2][4] = 0xc04199d5 ;
-pattern_4[2][5] = 0xdc968dc0 ;
-pattern_4[2][6] = 0xb8ba8a33 ;
-pattern_4[2][7] = 0x35e4327f ;
-
-pattern_4[3][0] = 0x51c8c049 ;
-pattern_4[3][1] = 0x2d43592c ;
-pattern_4[3][2] = 0x0777b50b ;
-pattern_4[3][3] = 0x9cd2ebe5 ;
-pattern_4[3][4] = 0xc04199d5 ;
-pattern_4[3][5] = 0xdc968dc0 ;
-pattern_4[3][6] = 0xb8ba8a33 ;
-pattern_4[3][7] = 0x35e4327f ;
-
-pattern_5[0][0] = 0xaec9c149 ;
-pattern_5[0][1] = 0xd243592c ;
-pattern_5[0][2] = 0xf877b50b ;
-pattern_5[0][3] = 0x63d2ebe5 ;
-pattern_5[0][4] = 0x3f439bd5 ;
-pattern_5[0][5] = 0x23968dc0 ;
-pattern_5[0][6] = 0x47ba8a33 ;
-pattern_5[0][7] = 0xcae4327f ;
-pattern_5[1][0] = 0xaeccc449 ;
-pattern_5[1][1] = 0xd243592c ;
-pattern_5[1][2] = 0xf877b50b ;
-pattern_5[1][3] = 0x63d2ebe5 ;
-pattern_5[1][4] = 0x3f4991d5 ;
-pattern_5[1][5] = 0x23968dc0 ;
-pattern_5[1][6] = 0x47ba8a33 ;
-pattern_5[1][7] = 0xcae4327f ;
-pattern_5[2][0] = 0xaed8d049 ;
-pattern_5[2][1] = 0xd243592c ;
-pattern_5[2][2] = 0xf877b50b ;
-pattern_5[2][3] = 0x63d2ebe5 ;
-pattern_5[2][4] = 0x3f61b9d5 ;
-pattern_5[2][5] = 0x23968dc0 ;
-pattern_5[2][6] = 0x47ba8a33 ;
-pattern_5[2][7] = 0xcae4327f ;
-pattern_5[3][0] = 0xae888049 ;
-pattern_5[3][1] = 0xd243592c ;
-pattern_5[3][2] = 0xf877b50b ;
-pattern_5[3][3] = 0x63d2ebe5 ;
-pattern_5[3][4] = 0x3fc119d5 ;
-pattern_5[3][5] = 0x23968dc0 ;
-pattern_5[3][6] = 0x47ba8a33 ;
-pattern_5[3][7] = 0xcae4327f ;
-
-pattern_6[0][1] = 0xd243a62c ;
-pattern_6[0][2] = 0xf8774a0b ;
-pattern_6[0][3] = 0x63d214e5 ;
-pattern_6[0][4] = 0x3f4366d5 ;
-pattern_6[0][5] = 0x239672c0 ;
-pattern_6[0][6] = 0x47ba7533 ;
-pattern_6[0][7] = 0xcae4cd7f ;
-pattern_6[1][0] = 0xaecc3f49 ;
-pattern_6[1][1] = 0xd243a62c ;
-pattern_6[1][2] = 0xf8774a0b ;
-pattern_6[1][3] = 0x63d214e5 ;
-pattern_6[1][4] = 0x3f4966d5 ;
-pattern_6[1][5] = 0x239672c0 ;
-pattern_6[1][6] = 0x47ba7533 ;
-pattern_6[1][7] = 0xcae4cd7f ;
-pattern_6[2][0] = 0xaed83f49 ;
-pattern_6[2][1] = 0xd243a62c ;
-pattern_6[2][2] = 0xf8774a0b ;
-pattern_6[2][3] = 0x63d214e5 ;
-pattern_6[2][4] = 0x3f6166d5 ;
-pattern_6[2][5] = 0x239672c0 ;
-pattern_6[2][6] = 0x47ba7533 ;
-pattern_6[2][7] = 0xcae4cd7f ;
-pattern_6[3][0] = 0xae883f49 ;
-pattern_6[3][1] = 0xd243a62c ;
-pattern_6[3][2] = 0xf8774a0b ;
-pattern_6[3][3] = 0x63d214e5 ;
-pattern_6[3][4] = 0x3fc166d5 ;
-pattern_6[3][5] = 0x239672c0 ;
-pattern_6[3][6] = 0x47ba7533 ;
-pattern_6[3][7] = 0xcae4cd7f ;
-*/
-#endif
-
-#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START
-#define DDR_TEST_SIZE 0x2000000
-//#define DDR_TEST_SIZE 0x2000
-
-#if (CONFIG_CHIP>=CHIP_TXLX)
-
-#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000)
-
-///*
-//#ifndef P_PIN_MUX_REG1
-// Pin Mux (9)
-// ----------------------------
-#if (CONFIG_CHIP==CHIP_TXLX)
-#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
-#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
-#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x2c << 2))
-#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
-#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
-#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x2d << 2))
-#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
-#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
-#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x2e << 2))
-#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
-#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
-#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x2f << 2))
-#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
-#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
-#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x30 << 2))
-#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
-#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
-#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x31 << 2))
-#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
-#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
-#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x32 << 2))
-#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
-#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
-#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x33 << 2))
-#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
-#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
-#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x34 << 2))
-#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
-#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
-#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x35 << 2))
-#define PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
-#define SEC_PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
-#define P_PERIPHS_PIN_MUX_10 (volatile uint32_t *)(0xff634400 + (0x36 << 2))
-#define PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
-#define SEC_PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
-#define P_PERIPHS_PIN_MUX_11 (volatile uint32_t *)(0xff634400 + (0x37 << 2))
-#define PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
-#define SEC_PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
-#define P_PERIPHS_PIN_MUX_12 (volatile uint32_t *)(0xff634400 + (0x38 << 2))
-#endif
-#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
-#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
-#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
-#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2))))
-//#endif
-
-//#ifndef P_PWM_MISC_REG_AB
-//#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
-//#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
-//#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
-//#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
-//#endif
-//*/
-//#define PWM_MISC_REG_AB (0x6c02)
-//#define P_PWM_MISC_REG_AB (volatile unsigned int *)((0x6c02 << 2) + 0xffd00000)
-//#define WATCHDOG_CNTL ((0x3c34 << 2) + 0xffd00000)
-//#define WATCHDOG_CNTL1 ((0x3c35 << 2) + 0xffd00000)
-//#define WATCHDOG_TCNT ((0x3c36 << 2) + 0xffd00000)
-//#define WATCHDOG_RESET ((0x3c37 << 2) + 0xffd00000)
-#else
-//#define ddr_udelay(a) do{}while((a<<5)--);
-#define P_EE_TIMER_E (volatile unsigned int *)(((0x2662 << 2) + 0xc1100000))
-//#define WATCHDOG_CNTL 0xc11098d0
-//#define WATCHDOG_CNTL1 0xc11098d4
-//#define WATCHDOG_TCNT 0xc11098d8
-//#define WATCHDOG_RESET 0xc11098dc
-#ifndef P_WATCHDOG_CNTL
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
-#define P_WATCHDOG_CNTL (volatile unsigned int *)0xc11098d0
-#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
-#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
-#define P_WATCHDOG_RESET (volatile unsigned int *) 0xc11098dc
-#else
-#define P_WATCHDOG_CNTL (volatile unsigned int *)(0xc1100000+(0x2640<<2))
-//#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
-//#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
-#define P_WATCHDOG_RESET (volatile unsigned int *)(0xc1100000+(0x2641<<2))
-#endif
-#endif
-
-
-#ifndef P_PIN_MUX_REG1
-#define P_PIN_MUX_REG1 (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
-#define P_PIN_MUX_REG2 (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
-#define P_PIN_MUX_REG3 (((volatile unsigned *)(0xda834400 + (0x2f << 2))))
-#define P_PIN_MUX_REG7 (((volatile unsigned *)(0xda834400 + (0x33 << 2))))
-#endif
-
-#ifndef P_PWM_MISC_REG_AB
-#define P_PWM_MISC_REG_AB (((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
-#define P_PWM_PWM_B (((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
-#define P_PWM_MISC_REG_CD (((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
-#define P_PWM_PWM_D (((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
-#endif
-
-#ifndef P_EE_TIMER_E
-#define P_EE_TIMER_E (((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
-#endif
-
-#endif
-
-#define get_us_time() (*P_EE_TIMER_E)// (readl(P_ISA_TIMERE))
-
-// #define P_ISA_TIMERE 0xc1109988
-// #define get_us_time() (readl(P_ISA_TIMERE))
-
-/*
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xff807000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)((0x6c00 << 2) + 0xffd00000)))
-
-#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
-*/
-
-#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))=((uint16_t)dat)
-#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))
-#define ACX_MAX 0x80
-
-void ddr_udelay(unsigned int us)
-{
-//#ifndef CONFIG_PXP_EMULATOR
- unsigned int t0 = (*((P_EE_TIMER_E)));
-
- while ((*((P_EE_TIMER_E))) - t0 <= us)
- ;
-//#endif
-}
-
-#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
-#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
-#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
-#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
-
-#define DDR_PARAMETER_READ 1
-#define DDR_PARAMETER_WRITE 2
-#define DDR_PARAMETER_LEFT 1
-#define DDR_PARAMETER_RIGHT 2
-
-typedef struct ddr_test_struct {
- unsigned int ddr_data_source ;
- unsigned int ddr_data_test_size ;
- unsigned int ddr_address_test_size ;
- unsigned int ddr_test_watchdog_times_s ;
- unsigned int ddr_test_lane_disable ;
-
- unsigned int ddr_test_window_flag[8] ;
- unsigned int ddr_test_window_data[100] ;
-} ddr_test_struct_t;
-ddr_test_struct_t *g_ddr_test_struct;
-
-unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
-{
-
- if(source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
- {
- sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
-
- if(read_write_flag == DDR_PARAMETER_WRITE)
- wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if(read_write_flag == DDR_PARAMETER_READ)
- parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
- }
-
- if(source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
- {
- char *pre_env_name = "ddr_test_data_num";
- char *env_name = "ddr_test_data_num_0000";
- char *str_buf = NULL;
- char *temp_s = NULL;
- char *endp = NULL;
- char buf[1024];
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
- sprintf(buf, "0x%08x", parameter_value);
-
- if(read_write_flag == DDR_PARAMETER_WRITE)
- {
- setenv(env_name, buf);
- run_command("save",0);
- }
- if(read_write_flag == DDR_PARAMETER_READ)
- {
- temp_s = getenv(env_name);
- if(temp_s)
- parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
- else
- parameter_value = 0;
- }
- }
-
- if(source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
- {
- sticky_reg_base_add=(PREG_STICKY_REG0);
-
- if(read_write_flag==DDR_PARAMETER_WRITE)
- wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if(read_write_flag==DDR_PARAMETER_READ)
- parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
- }
- return parameter_value;
-}
-
-
-unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
-{
-
- if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
- {
- sticky_reg_base_add = PREG_STICKY_REG0;
-
- if (read_write_flag == DDR_PARAMETER_WRITE)
- wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if (read_write_flag == DDR_PARAMETER_READ)
- parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
- }
-
- if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
- {
- sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
-
- if (read_write_flag == DDR_PARAMETER_WRITE)
- wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if (read_write_flag == DDR_PARAMETER_READ)
- parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
- }
-
- if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
- {
- char *pre_env_name = "ddr_test_data_num";
- char *env_name = "ddr_test_data_num_0000";
- char *str_buf = NULL;
- char *temp_s = NULL;
- char *endp = NULL;
- char buf[1024];
- str_buf = (char *)(&buf);
- memset(str_buf, 0, sizeof(buf));
- sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
- sprintf(buf, "0x%08x", parameter_value);
-
- if (read_write_flag == DDR_PARAMETER_WRITE)
- {
- setenv(env_name, buf);
- run_command("save",0);
- }
- if(read_write_flag == DDR_PARAMETER_READ)
- {
- temp_s = getenv(env_name);
- if(temp_s)
- parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
- else
- parameter_value = 0;
- }
- }
-
- return parameter_value;
-}
-
-void ddr_test_watchdog_init(uint32_t msec)
-{
-
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
- *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1);
-
- // set timeout
- //*P_WATCHDOG_TCNT = msec;
- // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
- *P_WATCHDOG_TCNT = msec;
- //writel(0,(unsigned int )P_WATCHDOG_RESET);
- *P_WATCHDOG_RESET = 0;
- //*P_WATCHDOG_RESET = 0;
-
- // enable
- *P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18);
- //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
- //*P_WATCHDOG_CNTL |= (1<<18);
-#else
- *P_WATCHDOG_CNTL = (0<<24)|(msec*8-1);
- //*P_WATCHDOG_TCNT=msec;
-#endif
-}
-
-void ddr_test_watchdog_enable(uint32_t sec)
-{
-
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
- *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
- // set timeout
- //*P_WATCHDOG_TCNT = msec;
- // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
- if(sec*100>0xffff)
- *P_WATCHDOG_TCNT=0xffff;
- else
- *P_WATCHDOG_TCNT=sec*100; //max 655s
- //writel(0,(unsigned int )P_WATCHDOG_RESET);
- *P_WATCHDOG_RESET=0;
- //*P_WATCHDOG_RESET = 0;
-
- // enable
- *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
- //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
- //*P_WATCHDOG_CNTL |= (1<<18);
-#else
- //*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1);
- *P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff);
- printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n");
-#endif
- printf("\nP_WATCHDOG_ENABLE\n");
-}
-
-void ddr_test_watchdog_disable(void )
-{
-
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
- *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
- // set timeout
- //*P_WATCHDOG_TCNT = msec;
- // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
- //*P_WATCHDOG_TCNT=sec*100;
- //writel(0,(unsigned int )P_WATCHDOG_RESET);
- *P_WATCHDOG_RESET=0;
- //*P_WATCHDOG_RESET = 0;
-
- // enable
- *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
- //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
- //*P_WATCHDOG_CNTL |= (1<<18);
-#else
- *P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1);
-#endif
- printf("\nP_WATCHDOG_DISABLE\n");
-}
-
-
-void ddr_test_watchdog_clear(void )
-{
-
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
- //*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
- // set timeout
- //*P_WATCHDOG_TCNT = msec;
- // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
- //*P_WATCHDOG_TCNT=sec*100;
- //writel(0,(unsigned int )P_WATCHDOG_RESET);
- *P_WATCHDOG_RESET=0;
- //*P_WATCHDOG_RESET = 0;
-
- // enable
- //*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
- //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
- //*P_WATCHDOG_CNTL |= (1<<18);
- //printf("\nP_WATCHDOG_CLEAR,reg=0x%8x\n",(P_WATCHDOG_RESET));
-}
-
-void ddr_test_watchdog_reset_system(void)
-{
- //#define P_WATCHDOG_CNTL 0xc11098d0
- //#define P_WATCHDOG_CNTL1 0xc11098d4
- //#define P_WATCHDOG_TCNT 0xc11098d8
- //#define P_WATCHDOG_RESET 0xc11098dc
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
- int i;
-
- while (1) {
- /*
- writel( 0x3 | (1 << 21) // sys reset en ao ee 3
- | (1 << 23) // interrupt en
- | (1 << 24) // clk en
- | (1 << 25) // clk div en
- | (1 << 26) // sys reset now ao ee 3
- , (unsigned int )P_WATCHDOG_CNTL);
- */
- *P_WATCHDOG_CNTL=
- 0x3 | (1 << 21) // sys reset en ao ee 3
- | (1 << 23) // interrupt en
- | (1 << 24) // clk en
- | (1 << 25) // clk div en
- | (1 << 26); // sys reset now ao ee 3;
- //printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL));
- //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
- //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
- printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL,
- *P_WATCHDOG_CNTL);
- //writel(0, (unsigned int )P_WATCHDOG_RESET);
- *P_WATCHDOG_RESET=0;
-
- // writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en
- //(unsigned int )P_WATCHDOG_CNTL);
- *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
- for (i=0; i<100; i++)
- *P_WATCHDOG_CNTL;
- //readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
- }
-
-#else
- //WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
- *P_WATCHDOG_CNTL=(0xf080000 | 2000);
-#endif
- while(1);
-}
-
-
-//just tune for lcdlr
-
-#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
-#else
-int do_ddr_fine_tune_lcdlr_env1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter ddr_fine_tune_lcdlr_env function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- int i = 0;
- printf("\nargc== 0x%08x\n", argc);
- for(i = 0; i<argc; i++)
- {
- printf("\nargv[%d]=%s\n",i,argv[i]);
- }
-
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
-
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
-
- char *endp;
- // unsigned int *p_start_addr;
-
-#define WR_RD_ADJ_USE_ENV 1
-#define WR_RD_ADJ_USE_UART_INPUT 2
- unsigned int wr_rd_adj_input_src=1;
- int wr_adj_per[12]={
- 100 ,
- 1000,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- };
- int rd_adj_per[12]={
- 100 ,
- 100 ,
- 80 ,
- 80 ,
- 80 ,
- 80 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- 100 ,
- };
- if(argc == 1)
- printf("\nplease read help\n");
-
- if(argc >= 2)
- {
- wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
-
- unsigned int i=0;
- if(wr_rd_adj_input_src==WR_RD_ADJ_USE_UART_INPUT)
- {
- printf("\ntune ddr lcdlr use uart input\n");
- if (argc>24+2)
- argc=24+2;
-
- for(i = 2;i<argc;i++)
- {
- if(i<(2+12))
- wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
- else
- rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
- }
- }
-
- // unsigned int = 0, max = 0xff, min = 0x00;
- if(wr_rd_adj_input_src==WR_RD_ADJ_USE_ENV)
- {
- printf("\ntune ddr lcdlr use uboot env\n");
- //char str[24];
- const char *s;
-
- // char *varname;
- int value=0;
-
- //*varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
- if (s)
- {//i=0;
- //while(s_temp)
- {
- printf("%s",s);
- //sscanf(s,"d%,",wr_adj_per);
- //sprintf(str,"d%",s);
- //getc
- }
- value = simple_strtoull_ddr(s, &endp, 16);
- printf("%d",value);
- }
- s = getenv("env_rd_lcdlr_pr");
-
- if (s)
- {//i=0;
- //while(s_temp)
- {
- printf("%s",s);
- //sscanf(s,"d%,",rd_adj_per);
-
- }
- //value = simple_strtoull_ddr(s, &endp, 16);
- }
-
- //sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
- //run_command("save",0);
-
- if (argc>24+2)
- argc=24+2;
- for(i = 2;i<argc;i++)
- {
- if(i<(2+12))
- wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
- else
- rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
- }
- }
- printf(" int wr_adj_per[12]={\n");
- for(i = 0;i<12;i++)
- printf("%04d ,\n",wr_adj_per[i]);
- printf("};\n");
- printf(" int rd_adj_per[12]={\n");
- for(i = 0;i<12;i++)
- printf("%04d ,\n",rd_adj_per[i]);
- printf("};\n");
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
- wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))|(1<<0));
- wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
- wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))|(1<<0));
-#else
- wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
- wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))|(1<<26));
- wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
- wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))|(1<<26));
-#endif
-
- int lcdlr_w=0,lcdlr_r=0;
- unsigned temp_reg=0;
- int temp_count=0;
- for( temp_count=0;temp_count<2;temp_count++)
- { temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- if(temp_count==1)
- lcdlr_w=lcdlr_w&ACBDLR_MAX;
- wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
- }
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- for( temp_count=2;temp_count<6;temp_count++)
- { temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
- lcdlr_r=lcdlr_r?lcdlr_r:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
- wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
- wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
- wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
- }
-#else
- for ( temp_count=2;temp_count<6;temp_count++) {
- temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&DQLCDLR_MAX);
- lcdlr_r=lcdlr_r?lcdlr_r:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
- wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
- }
-#endif
- for( temp_count=6;temp_count<8;temp_count++) {
- temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
-
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- if(temp_count==7)
- lcdlr_w=lcdlr_w&ACBDLR_MAX;
- wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
- }
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- for( temp_count=8;temp_count<12;temp_count++) {
- temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
- lcdlr_r=lcdlr_r?lcdlr_r:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
- wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
- wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
- wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
- }
-#else
- for( temp_count=8;temp_count<12;temp_count++) {
- temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
- lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
- lcdlr_w=lcdlr_w?lcdlr_w:1;
- lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&0xff);
- lcdlr_r=lcdlr_r?lcdlr_r:1;
- lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
- wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
- }
-#endif
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
- wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
-
- wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))&(~(1<<0)));
- wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
-#else
- wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))&(~(1<<26)));
- wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
-
- wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))&(~(1<<26)));
- wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
-#endif
- printf("\nend adjust lcdlr\n");
-
- CLOSE_CHANNEL_A_PHY_CLK();
- CLOSE_CHANNEL_B_PHY_CLK();
- }
-
- return 1;
-}
-U_BOOT_CMD(
- ddr_test_tune_dqs_env, 30, 1, do_ddr_fine_tune_lcdlr_env1,
- "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3...",
- "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
-);
-
-#endif
-//*/
-static void ddr_write(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- unsigned int i, j, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- for (j=0;j<32;j++)
- {
-
- if (m_len >= 128)
- n = 32;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- switch (i)
- {
- case 0:
- case 9:
- case 14:
- case 25:
- case 30:
- *(p+i) = TDATA32F;
- break;
- case 1:
- case 6:
- case 8:
- case 17:
- case 22:
- *(p+i) = 0;
- break;
- case 16:
- case 23:
- case 31:
- *(p+i) = TDATA32A;
- break;
- case 7:
- case 15:
- case 24:
- *(p+i) = TDATA325;
- break;
- case 2:
- case 4:
- case 10:
- case 12:
- case 19:
- case 21:
- case 27:
- case 29:
- *(p+i) = 1<<j;
- break;
- case 3:
- case 5:
- case 11:
- case 13:
- case 18:
- case 20:
- case 26:
- case 28:
- *(p+i) = ~(1<<j);
- break;
- }
- }
-
- if (m_len > 128)
- {
- m_len -= 128;
- p += 32;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_read(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- unsigned int i, j, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- for (j=0;j<32;j++)
- {
-
- if (m_len >= 128)
- n = 32;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
- switch (i)
- {
-
- case 0:
- case 9:
- case 14:
- case 25:
- case 30:
- if (*(p+i) != TDATA32F)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- case 1:
- case 6:
- case 8:
- case 17:
- case 22:
- if (*(p+i) != 0) {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
- }break;
- case 16:
- case 23:
- case 31:
- if (*(p+i) != TDATA32A) {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
- } break;
- case 7:
- case 15:
- case 24:
- if (*(p+i) != TDATA325) {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
- } break;
- case 2:
- case 4:
- case 10:
- case 12:
- case 19:
- case 21:
- case 27:
- case 29:
- if (*(p+i) != 1<<j) {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j);
- } break;
- case 3:
- case 5:
- case 11:
- case 13:
- case 18:
- case 20:
- case 26:
- case 28:
- if (*(p+i) != ~(1<<j)) {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j));
- } break;
- }
- }
-
- if (m_len > 128)
- {
- m_len -= 128;
- p += 32;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-
-static void ddr_write4(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- unsigned int i, j, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- for (j=0;j<32;j++)
- {
-
- if (m_len >= 128)
- n = 32;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
-
- *(p+i) = 0xff00ff00;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
-
- *(p+i) = ~0xff00ff00;
- break;
- case 8:
- case 9:
- case 10:
- case 11:
- *(p+i) = 0xaa55aa55;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- *(p+i) = ~0xaa55aa55;
- break;
- case 16:
- case 17:
- case 18:
- case 19:
-
- case 24:
- case 25:
- case 26:
- case 27:
-
- *(p+i) = 1<<j;
- break;
-
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- *(p+i) = ~(1<<j);
- break;
- }
- }
-
- if (m_len > 128)
- {
- m_len -= 128;
- p += 32;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_read4(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- unsigned int i, j, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- for (j=0;j<32;j++)
- {
-
- if (m_len >= 128)
- n = 32;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
- switch (i)
- {
-
- case 0:
- case 1:
- case 2:
- case 3:
-
- // *(p+i) = 0xff00ff00;
- if (*(p+i) != 0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- case 4:
- case 5:
- case 6:
- case 7:
-
- // *(p+i) = ~0xff00ff00;
- if (*(p+i) != ~0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- case 8:
- case 9:
- case 10:
- case 11:
- // *(p+i) = 0xaa55aa55;
- if (*(p+i) != 0xaa55aa55)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- // *(p+i) = ~0xaa55aa55;
- if (*(p+i) != ~0xaa55aa55)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- case 16:
- case 17:
- case 18:
- case 19:
-
- case 24:
- case 25:
- case 26:
- case 27:
-
- // *(p+i) = 1<<j;
- if (*(p+i) != (1<<j))
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
-
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- // *(p+i) = ~(1<<j);
- if (*(p+i) !=~( 1<<j))
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- }
- break;
- }
- }
-
- if (m_len > 128)
- {
- m_len -= 128;
- p += 32;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_read_full(void *buff, unsigned int m_length,unsigned int start_pattern,
- unsigned int pattern_offset)
-{
- unsigned int *p;
- unsigned int i=0;
- unsigned int m_len = m_length&0xfffffffc;
-
- p = ( unsigned int *)buff;
- //*(p)=start_pattern;
- while (m_len)
- {
- m_len=m_len-4;
-
- // *(p+i) = (*(p))+pattern_offset;
-
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p+i) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
- if ((*(p+i)) !=(start_pattern+pattern_offset*i))
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
- (start_pattern+pattern_offset*i));
- }
- break;
-
- i++;
- }
-}
-
-static void ddr_write_full(void *buff, unsigned int m_length,unsigned int start_pattern,
- unsigned int pattern_offset)
-{
- unsigned int *p;
- unsigned int i=0;
- unsigned int m_len = m_length&0xfffffffc;
-
- p = ( unsigned int *)buff;
- //*(p)=start_pattern;
- while (m_len)
- {
- m_len=m_len-4;
- *(p+i) = start_pattern+pattern_offset*i;
- i++;
- }
-}
-
-///*
-static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size)
-{
- unsigned int *p_dest;
- unsigned int *p_src;
-
- unsigned int m_len = memcpy_size;
-
- p_dest = ( unsigned int *)addr_dest;
- p_src = ( unsigned int *)addr_src;
- m_len = m_len/4; //assume it's multiple of 4
- while (m_len--) {
- ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
- *p_dest++ = *p_src++;
- *p_dest++ = *p_src++;
- *p_dest++ = *p_src++;
- *p_dest++ = *p_src++;
- }
-}
-//*/
-int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *endp;
- unsigned long loop = 1;
- unsigned int print_flag =1;
- // unsigned int start_addr = DDR_TEST_START_ADDR;
- unsigned int src_addr = DDR_TEST_START_ADDR;
- unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000;
- unsigned int test_size = DDR_TEST_SIZE;
-
-
- print_flag=1;
-
- printf("\nargc== 0x%08x\n", argc);
- int i ;
- for (i = 0;i<argc;i++)
- printf("\nargv[%d]=%s\n",i,argv[i]);
-
- // printf("\nLINE== 0x%08x\n", __LINE__);
- if (argc ==1) {
- // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- // if (*argv[2] == 0 || *endp != 0)
- src_addr = DDR_TEST_START_ADDR;
- loop = 1;
- }
- if (argc > 2) {
- // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- if (*argv[2] == 0 || *endp != 0)
- src_addr = DDR_TEST_START_ADDR;
- }
- if (argc > 3) {
- src_addr = simple_strtoull_ddr(argv[1], &endp, 16);
- dec_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- loop = 1;
- if (*argv[3] == 0 || *endp != 0)
- test_size = DDR_TEST_SIZE;
-
- }
- if (test_size<0x1000)
- test_size = DDR_TEST_SIZE;
- if (argc > 4) {
- loop = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- loop = 1;
- }
- if (argc > 5) {
- print_flag = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- print_flag = 1;
- }
- //COPY_TEST_START:
-
- ///*
- unsigned long time_start, time_end,test_loops;
- test_loops=loop;
- unsigned long size_count=0;
- size_count=loop*test_size;
- time_start = get_us_time();//us
-
- do {
- // loop = 1;
- ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size);
- //bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
- //mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
- if (print_flag)
- {
- printf("\nloop==0x%08x", ( unsigned int )loop);
- printf("\n \n");
- }
- }while(--loop);
- //*/
- time_end = get_us_time();//us
- printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start));
-
- printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
- printf("\rEnd ddr test. \n");
-
- unsigned int m_len=0,counter=0;
- unsigned int *p_dest;
- p_dest= (void *)(int_convter_p(dec_addr));
- m_len = test_size/4; //assume it's multiple of 4
- counter=(unsigned int)test_loops;
- size_count=counter*test_size;
- time_start = get_us_time();//us
- do {
- loop = 1;
- m_len = test_size/4;
- while (m_len--) {
- ddr_pld_cache(p_dest) ;
- *p_dest++ = 0x12345678;
- *p_dest++ = 0x12345678;
- *p_dest++ = 0x12345678;
- *p_dest++ = 0x12345678;
- }
- }while(--counter);
- time_end = get_us_time();//us
- printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start));
-
- printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
-
- unsigned int *p_src;
- p_src= (void *)(int_convter_p(src_addr));
- m_len = test_size/4; //assume it's multiple of 4
- unsigned int temp0=0;
- //unsigned int temp1=0;
- //unsigned int temp2=0;
- //unsigned int temp3=0;
- counter=(unsigned int)test_loops;
- size_count=counter*test_size;
-
- // #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
- //writel((1000000<<0), DMC_MON_CTRL1);
- //writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
- //writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
- time_start = get_us_time();//us
- do {
- loop = 1;
- m_len = test_size/4;
- while (m_len--) {
- // ddr_pld_cache(p_src++) ;
-#ifdef DDR_PREFETCH_CACHE
- __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src));
-#endif
- p_src++;
- temp0 =( *p_src);
- m_len--;
- m_len--;
- m_len--;
- m_len--;
- m_len--;
- m_len--;
- m_len--;
- }
- }while(--counter);
- *p_dest++ = temp0;
- *p_dest++ = *p_src;
- *p_dest++ = *p_src;
- *p_dest++ = *p_src;
- time_end = get_us_time();//us
-
- printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start));
- printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
-
- return 0;
-}
-
-U_BOOT_CMD(
- ddr_test_copy, 7, 1, do_ddr_test_copy,
- "ddr_test_copy function",
- "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n"
-);
-
-///*
-#define DDR_PATTERN_LOOP_1 32
-#define DDR_PATTERN_LOOP_2 64
-#define DDR_PATTERN_LOOP_3 96
-/*
-__asm
-{
-.Global memcpy_pld
-.type memcpy_pld ,%function
-.align 8
-memcpy_pld:
-mov x4,x0
-subs x2,x2,#8
-b.mi 2f
-1: ldr x3,[x1],#8
- subs x2,x2,#8
- str x3,[x4],#8
- prfm PLDL1KEEP,[x1,#376]
- b.pl 1b
-
-2: adds x2,x2,#4
- b.mi 3f
- ldr w3,[x1],#4
- sub x2,x2,#4
- str w3,[x4],#4
-
-3: adds x2,x2,#2
- b.mi 4f
- ldr w3,[x1],#2
- sub x2,x2,#4
- str w3,[x4],#4
-
-4: adds x2,x2,#1
- b.mi 5f
- ldr w3,[x1],#2
- sub x2,x2,#4
- str w3,[x4],#4
-
-5: ret
-}
-*/
-//static void ddr_memcpy_pld(void *addr_dest, void *addr_src, unsigned int m_length)
-//{
-/*
-asm
-{
-//.Global memcpy_pld
-.type memcpy_pld ,%function
-.align 8
-memcpy_pld:
-mov x4,x0
-subs x2,x2,#8
-b.mi 2f
-1: ldr x3,[x1],#8
- subs x2,x2,#8
- str x3,[x4],#8
- prfm PLDL1KEEP,[x1,#376]
- b.pl 1b
-
-2: adds x2,x2,#4
- b.mi 3f
- ldr w3,[x1],#4
- sub x2,x2,#4
- str w3,[x4],#4
-
-3: adds x2,x2,#2
- b.mi 4f
- ldr w3,[x1],#2
- sub x2,x2,#4
- str w3,[x4],#4
-
-4: adds x2,x2,#1
- b.mi 5f
- ldr w3,[x1],#2
- sub x2,x2,#4
- str w3,[x4],#4
-
-5: ret
-}
-memcpy_pld(addr_dest,addr_src,m_length);
-*/
-//}
-
-
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
-
-///*
-
-int ddr_test_gx_cross_talk_pattern(int ddr_test_size)
-{
- unsigned int start_addr = 0x10000000;
- error_outof_count_flag=1;
- error_count=0;
-
- unsigned int des[8] ;
- unsigned int pattern_1[4][8] ;
- unsigned int pattern_2[4][8] ;
- unsigned int pattern_3[4][8] ;
- unsigned int pattern_4[4][8] ;
- unsigned int pattern_5[4][8] ;
- unsigned int pattern_6[4][8] ;
-
- des[0] = 0xaec83f49;
- des[1] = 0xd243a62c;
- des[2] = 0xf8774a0b;
- des[3] = 0x63d214e5;
- des[4] = 0x3f4166d5;
- des[5] = 0x239672c0;
- des[6] = 0x47ba7533;
- des[7] = 0xcae4cd7f;
- pattern_1[0][0] = 0xff00ff00;
- pattern_1[0][1] = 0xff00ff00;
- pattern_1[0][2] = 0xff00ff00;
- pattern_1[0][3] = 0xff00ff00;
- pattern_1[0][4] = 0xff00ff00;
- pattern_1[0][5] = 0xff00ff00;
- pattern_1[0][6] = 0xff00ff00;
- pattern_1[0][7] = 0xff00ff00;
-
- pattern_1[1][0] = 0x00ffff00;
- pattern_1[1][1] = 0x00ffff00;
- pattern_1[1][2] = 0x00ffff00;
- pattern_1[1][3] = 0x00ffff00;
- pattern_1[1][4] = 0x00ffff00;
- pattern_1[1][5] = 0x00ffff00;
- pattern_1[1][6] = 0x00ffff00;
- pattern_1[1][7] = 0x00ffff00;
-
- pattern_1[2][0] = 0xffff0000;
- pattern_1[2][1] = 0xffff0000;
- pattern_1[2][2] = 0xffff0000;
- pattern_1[2][3] = 0xffff0000;
- pattern_1[2][4] = 0xffff0000;
- pattern_1[2][5] = 0xffff0000;
- pattern_1[2][6] = 0xffff0000;
- pattern_1[2][7] = 0xffff0000;
- pattern_1[3][0] = 0xff00ff00;
- pattern_1[3][1] = 0xff00ff00;
- pattern_1[3][2] = 0xff00ff00;
- pattern_1[3][3] = 0xff00ff00;
- pattern_1[3][4] = 0xff00ff00;
- pattern_1[3][5] = 0xff00ff00;
- pattern_1[3][6] = 0xff00ff00;
- pattern_1[3][7] = 0xff00ff00;
-
- pattern_2[0][0] = 0x0001fe00;
- pattern_2[0][1] = 0x0000ff00;
- pattern_2[0][2] = 0x0000ff00;
- pattern_2[0][3] = 0x0000ff00;
- pattern_2[0][4] = 0x0002fd00;
- pattern_2[0][5] = 0x0000ff00;
- pattern_2[0][6] = 0x0000ff00;
- pattern_2[0][7] = 0x0000ff00;
-
- pattern_2[1][0] = 0x0004fb00;
- pattern_2[1][1] = 0x0000ff00;
- pattern_2[1][2] = 0x0000ff00;
- pattern_2[1][3] = 0x0000ff00;
- pattern_2[1][4] = 0x0008f700;
- pattern_2[1][5] = 0x0000ff00;
- pattern_2[1][6] = 0x0000ff00;
- pattern_2[1][7] = 0x0000ff00;
-
- pattern_2[2][0] = 0x0010ef00;
- pattern_2[2][1] = 0x0000ff00;
- pattern_2[2][2] = 0x0000ff00;
- pattern_2[2][3] = 0x0000ff00;
- pattern_2[2][4] = 0x0020df00;
- pattern_2[2][5] = 0x0000ff00;
- pattern_2[2][6] = 0x0000ff00;
- pattern_2[2][7] = 0x0000ff00;
-
- pattern_2[3][0] = 0x0040bf00;
- pattern_2[3][1] = 0x0000ff00;
- pattern_2[3][2] = 0x0000ff00;
- pattern_2[3][3] = 0x0000ff00;
- pattern_2[3][4] = 0x00807f00;
- pattern_2[3][5] = 0x0000ff00;
- pattern_2[3][6] = 0x0000ff00;
- pattern_2[3][7] = 0x0000ff00;
-
- pattern_3[0][0] = 0x00010000;
- pattern_3[0][1] = 0x00000000;
- pattern_3[0][2] = 0x00000000;
- pattern_3[0][3] = 0x00000000;
- pattern_3[0][4] = 0x00020000;
- pattern_3[0][5] = 0x00000000;
- pattern_3[0][6] = 0x00000000;
- pattern_3[0][7] = 0x00000000;
-
- pattern_3[1][0] = 0x00040000;
- pattern_3[1][1] = 0x00000000;
- pattern_3[1][2] = 0x00000000;
- pattern_3[1][3] = 0x00000000;
- pattern_3[1][4] = 0x00080000;
- pattern_3[1][5] = 0x00000000;
- pattern_3[1][6] = 0x00000000;
- pattern_3[1][7] = 0x00000000;
-
- pattern_3[2][0] = 0x00100000;
- pattern_3[2][1] = 0x00000000;
- pattern_3[2][2] = 0x00000000;
- pattern_3[2][3] = 0x00000000;
- pattern_3[2][4] = 0x00200000;
- pattern_3[2][5] = 0x00000000;
- pattern_3[2][6] = 0x00000000;
- pattern_3[2][7] = 0x00000000;
-
- pattern_3[3][0] = 0x00400000;
- pattern_3[3][1] = 0x00000000;
- pattern_3[3][2] = 0x00000000;
- pattern_3[3][3] = 0x00000000;
- pattern_3[3][4] = 0x00800000;
- pattern_3[3][5] = 0x00000000;
- pattern_3[3][6] = 0x00000000;
- pattern_3[3][7] = 0x00000000;
-
- ///*
- pattern_4[0][0] = 0x51c8c049 ;
- pattern_4[0][1] = 0x2d43592c ;
- pattern_4[0][2] = 0x0777b50b ;
- pattern_4[0][3] = 0x9cd2ebe5 ;
- pattern_4[0][4] = 0xc04199d5 ;
- pattern_4[0][5] = 0xdc968dc0 ;
- pattern_4[0][6] = 0xb8ba8a33 ;
- pattern_4[0][7] = 0x35e4327f ;
-
- pattern_4[1][0] = 0xae37c049 ;
- pattern_4[1][1] = 0xd2bc592c ;
- pattern_4[1][2] = 0xf888b50b ;
- pattern_4[1][3] = 0x632debe5 ;
- pattern_4[1][4] = 0x3fbe99d5 ;
- pattern_4[1][5] = 0x23698dc0 ;
- pattern_4[1][6] = 0x47458a33 ;
- pattern_4[1][7] = 0xca1b327f ;
-
- pattern_4[2][0] = 0x51373f49 ;
- pattern_4[2][1] = 0x2dbca62c ;
- pattern_4[2][2] = 0x07884a0b ;
- pattern_4[2][3] = 0x9c2d14e5 ;
- pattern_4[2][4] = 0xc0be66d5 ;
- pattern_4[2][5] = 0xdc6972c0 ;
- pattern_4[2][6] = 0xb8457533 ;
- pattern_4[2][7] = 0x351bcd7f ;
-
-
- pattern_4[3][0] = 0x51c8c049 ;
- pattern_4[3][1] = 0x2d43592c ;
- pattern_4[3][2] = 0x0777b50b ;
- pattern_4[3][3] = 0x9cd2ebe5 ;
- pattern_4[3][4] = 0xc04199d5 ;
- pattern_4[3][5] = 0xdc968dc0 ;
- pattern_4[3][6] = 0xb8ba8a33 ;
- pattern_4[3][7] = 0x35e4327f ;
-
- pattern_5[0][0] = 0xaec9c149 ;
- pattern_5[0][1] = 0xd243592c ;
- pattern_5[0][2] = 0xf877b50b ;
- pattern_5[0][3] = 0x63d2ebe5 ;
- pattern_5[0][4] = 0x3f439bd5 ;
- pattern_5[0][5] = 0x23968dc0 ;
- pattern_5[0][6] = 0x47ba8a33 ;
- pattern_5[0][7] = 0xcae4327f ;
- pattern_5[1][0] = 0xaeccc449 ;
- pattern_5[1][1] = 0xd243592c ;
- pattern_5[1][2] = 0xf877b50b ;
- pattern_5[1][3] = 0x63d2ebe5 ;
- pattern_5[1][4] = 0x3f4991d5 ;
- pattern_5[1][5] = 0x23968dc0 ;
- pattern_5[1][6] = 0x47ba8a33 ;
- pattern_5[1][7] = 0xcae4327f ;
- pattern_5[2][0] = 0xaed8d049 ;
- pattern_5[2][1] = 0xd243592c ;
- pattern_5[2][2] = 0xf877b50b ;
- pattern_5[2][3] = 0x63d2ebe5 ;
- pattern_5[2][4] = 0x3f61b9d5 ;
- pattern_5[2][5] = 0x23968dc0 ;
- pattern_5[2][6] = 0x47ba8a33 ;
- pattern_5[2][7] = 0xcae4327f ;
- pattern_5[3][0] = 0xae888049 ;
- pattern_5[3][1] = 0xd243592c ;
- pattern_5[3][2] = 0xf877b50b ;
- pattern_5[3][3] = 0x63d2ebe5 ;
- pattern_5[3][4] = 0x3fc119d5 ;
- pattern_5[3][5] = 0x23968dc0 ;
- pattern_5[3][6] = 0x47ba8a33 ;
- pattern_5[3][7] = 0xcae4327f ;
-
- pattern_6[0][0] = 0xaec93f49 ;
- pattern_6[0][1] = 0xd243a62c ;
- pattern_6[0][2] = 0xf8774a0b ;
- pattern_6[0][3] = 0x63d214e5 ;
- pattern_6[0][4] = 0x3f4366d5 ;
- pattern_6[0][5] = 0x239672c0 ;
- pattern_6[0][6] = 0x47ba7533 ;
- pattern_6[0][7] = 0xcae4cd7f ;
- pattern_6[1][0] = 0xaecc3f49 ;
- pattern_6[1][1] = 0xd243a62c ;
- pattern_6[1][2] = 0xf8774a0b ;
- pattern_6[1][3] = 0x63d214e5 ;
- pattern_6[1][4] = 0x3f4966d5 ;
- pattern_6[1][5] = 0x239672c0 ;
- pattern_6[1][6] = 0x47ba7533 ;
- pattern_6[1][7] = 0xcae4cd7f ;
- pattern_6[2][0] = 0xaed83f49 ;
- pattern_6[2][1] = 0xd243a62c ;
- pattern_6[2][2] = 0xf8774a0b ;
- pattern_6[2][3] = 0x63d214e5 ;
- pattern_6[2][4] = 0x3f6166d5 ;
- pattern_6[2][5] = 0x239672c0 ;
- pattern_6[2][6] = 0x47ba7533 ;
- pattern_6[2][7] = 0xcae4cd7f ;
- pattern_6[3][0] = 0xae883f49 ;
- pattern_6[3][1] = 0xd243a62c ;
- pattern_6[3][2] = 0xf8774a0b ;
- pattern_6[3][3] = 0x63d214e5 ;
- pattern_6[3][4] = 0x3fc166d5 ;
- pattern_6[3][5] = 0x239672c0 ;
- pattern_6[3][6] = 0x47ba7533 ;
- pattern_6[3][7] = 0xcae4cd7f ;
- //*/
- //*/
- start_addr=0x10000000;
- unsigned int test_size = 0x20;
- unsigned int test_addr;
- unsigned int temp_i=0;
- unsigned int temp_k=0;
- unsigned int pattern_o[8];
- unsigned int pattern_d[8];
- {
- // if(lflag)
- // loop = 888;
-
- //if(old_pattern_flag==1)
- {
-
- printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
-
- /*
- for ((temp_k=0);(temp_k<4);(temp_k++)) {
- {
-
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
- flush_dcache_range(start_addr,start_addr + test_size);
-
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
- if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
- {error_count++;
- printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
- }
- }
- }
- }
- */
- //if(pattern_flag1==1)
- {
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
- // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
- if (pattern_o[temp_i] != pattern_4[temp_k][temp_i])
- {error_count++;
- printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
- }
-
- }
- }
- }
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
- // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
- pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
- if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
- {error_count++;
- printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]);
- }
-
- }
- }
- }
- }
- //if(pattern_flag2==1)
- {
- for ((temp_k=0);(temp_k<4);(temp_k++)) {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
- if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
- {error_count++;
- printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
- }
- }
- }
- }
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
- pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
- if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
- {error_count++;
- printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]);
- }
- }
- }
- }
-
- }
-
- // if(pattern_flag3==1)
- {
- for ((temp_k=0);(temp_k<4);(temp_k++)) {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
- if (pattern_o[temp_i] != pattern_6[temp_k][temp_i])
- {error_count++;
- printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]);
- }
- }
- }
- }
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
- pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
- if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
- {error_count++;
- printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]);
- }
- }
- }
- }
- }
-
-
-
- }
-
- printf("\Error count==0x%08x", error_count);
- printf("\n \n");
- }
-
- if (error_count)
- return 1;
- else
- return 0;
-}
-
-int ddr_test_gx_training_pattern(int ddr_test_size)
-{
- unsigned int start_addr = 0x10000000;
- error_outof_count_flag=1;
- error_count=0;
-
- unsigned int des[8] ;
- unsigned int pattern_1[4][8] ;
- // unsigned int pattern_2[4][8] ;
- // unsigned int pattern_3[4][8] ;
- // unsigned int pattern_4[4][8] ;
- // unsigned int pattern_5[4][8] ;
- //unsigned int pattern_6[4][8] ;
-
- des[0] = 0xaec83f49;
- des[1] = 0xd243a62c;
- des[2] = 0xf8774a0b;
- des[3] = 0x63d214e5;
- des[4] = 0x3f4166d5;
- des[5] = 0x239672c0;
- des[6] = 0x47ba7533;
- des[7] = 0xcae4cd7f;
- /*
- pattern_1[0][0] = 0x55005500;
- pattern_1[0][1] = 0xaa00aa00;
- pattern_1[0][2] = 0x55005500;
- pattern_1[0][3] = 0xaa00aa00;
- pattern_1[0][4] = 0x55005500;
- pattern_1[0][5] = 0xaa00aa00;
- pattern_1[0][6] = 0x55005500;
- pattern_1[0][7] = 0xaa00aa00;
-
- pattern_1[1][0] = 0x55005500;
- pattern_1[1][1] = 0xaa00aa00;
- pattern_1[1][2] = 0x55005500;
- pattern_1[1][3] = 0xaa00aa00;
- pattern_1[1][4] = 0x55005500;
- pattern_1[1][5] = 0xaa00aa00;
- pattern_1[1][6] = 0x55005500;
- pattern_1[1][7] = 0xaa00aa00;
-
- pattern_1[2][0] = 0x55005500;
- pattern_1[2][1] = 0xaa00aa00;
- pattern_1[2][2] = 0x55005500;
- pattern_1[2][3] = 0xaa00aa00;
- pattern_1[2][4] = 0x55005500;
- pattern_1[2][5] = 0xaa00aa00;
- pattern_1[2][6] = 0x55005500;
- pattern_1[2][7] = 0xaa00aa00;
-
- pattern_1[3][0] = 0x55005500;
- pattern_1[3][1] = 0xaa00aa00;
- pattern_1[3][2] = 0x55005500;
- pattern_1[3][3] = 0xaa00aa00;
- pattern_1[3][4] = 0x55005500;
- pattern_1[3][5] = 0xaa00aa00;
- pattern_1[3][6] = 0x55005500;
- pattern_1[3][7] = 0xaa00aa00;
- */
- // /*
- pattern_1[0][0] = 0x55aa5500;
- pattern_1[0][1] = 0x55aa5500;
- pattern_1[0][2] = 0x55aa5500;
- pattern_1[0][3] = 0x55aa5500;
- pattern_1[0][4] = 0xaa00ff00;
- pattern_1[0][5] = 0xaa00ff00;
- pattern_1[0][6] = 0xaa00ff00;
- pattern_1[0][7] = 0xaa00ff00;
-
- pattern_1[1][0] = 0x55005500;
- pattern_1[1][1] = 0xaa00aa00;
- pattern_1[1][2] = 0x55005500;
- pattern_1[1][3] = 0xaa00aa00;
- pattern_1[1][4] = 0x55005500;
- pattern_1[1][5] = 0xaa00aa00;
- pattern_1[1][6] = 0x55005500;
- pattern_1[1][7] = 0xaa00aa00;
-
- pattern_1[2][0] = 0x0001fe00;
- pattern_1[2][1] = 0x0000ff00;
- pattern_1[2][2] = 0x0000ff00;
- pattern_1[2][3] = 0x0000ff00;
- pattern_1[2][4] = 0x0002fd00;
- pattern_1[2][5] = 0x0000ff00;
- pattern_1[2][6] = 0x0000ff00;
- pattern_1[2][7] = 0x0000ff00;
-
- pattern_1[3][0] = 0x0004fb00;
- pattern_1[3][1] = 0x0000ff00;
- pattern_1[3][2] = 0x0000ff00;
- pattern_1[3][3] = 0x0000ff00;
- pattern_1[3][4] = 0x0008f700;
- pattern_1[3][5] = 0x0000ff00;
- pattern_1[3][6] = 0x0000ff00;
- pattern_1[3][7] = 0x0000ff00;
- //*/
- /*
- pattern_2[0][0] = 0x0001fe00;
- pattern_2[0][1] = 0x0000ff00;
- pattern_2[0][2] = 0x0000ff00;
- pattern_2[0][3] = 0x0000ff00;
- pattern_2[0][4] = 0x0002fd00;
- pattern_2[0][5] = 0x0000ff00;
- pattern_2[0][6] = 0x0000ff00;
- pattern_2[0][7] = 0x0000ff00;
-
- pattern_2[1][0] = 0x0004fb00;
- pattern_2[1][1] = 0x0000ff00;
- pattern_2[1][2] = 0x0000ff00;
- pattern_2[1][3] = 0x0000ff00;
- pattern_2[1][4] = 0x0008f700;
- pattern_2[1][5] = 0x0000ff00;
- pattern_2[1][6] = 0x0000ff00;
- pattern_2[1][7] = 0x0000ff00;
-
- pattern_2[2][0] = 0x0010ef00;
- pattern_2[2][1] = 0x0000ff00;
- pattern_2[2][2] = 0x0000ff00;
- pattern_2[2][3] = 0x0000ff00;
- pattern_2[2][4] = 0x0020df00;
- pattern_2[2][5] = 0x0000ff00;
- pattern_2[2][6] = 0x0000ff00;
- pattern_2[2][7] = 0x0000ff00;
-
- pattern_2[3][0] = 0x0040bf00;
- pattern_2[3][1] = 0x0000ff00;
- pattern_2[3][2] = 0x0000ff00;
- pattern_2[3][3] = 0x0000ff00;
- pattern_2[3][4] = 0x00807f00;
- pattern_2[3][5] = 0x0000ff00;
- pattern_2[3][6] = 0x0000ff00;
- pattern_2[3][7] = 0x0000ff00;
-
- pattern_3[0][0] = 0x00010000;
- pattern_3[0][1] = 0x00000000;
- pattern_3[0][2] = 0x00000000;
- pattern_3[0][3] = 0x00000000;
- pattern_3[0][4] = 0x00020000;
- pattern_3[0][5] = 0x00000000;
- pattern_3[0][6] = 0x00000000;
- pattern_3[0][7] = 0x00000000;
-
- pattern_3[1][0] = 0x00040000;
- pattern_3[1][1] = 0x00000000;
- pattern_3[1][2] = 0x00000000;
- pattern_3[1][3] = 0x00000000;
- pattern_3[1][4] = 0x00080000;
- pattern_3[1][5] = 0x00000000;
- pattern_3[1][6] = 0x00000000;
- pattern_3[1][7] = 0x00000000;
-
- pattern_3[2][0] = 0x00100000;
- pattern_3[2][1] = 0x00000000;
- pattern_3[2][2] = 0x00000000;
- pattern_3[2][3] = 0x00000000;
- pattern_3[2][4] = 0x00200000;
- pattern_3[2][5] = 0x00000000;
- pattern_3[2][6] = 0x00000000;
- pattern_3[2][7] = 0x00000000;
-
- pattern_3[3][0] = 0x00400000;
- pattern_3[3][1] = 0x00000000;
- pattern_3[3][2] = 0x00000000;
- pattern_3[3][3] = 0x00000000;
- pattern_3[3][4] = 0x00800000;
- pattern_3[3][5] = 0x00000000;
- pattern_3[3][6] = 0x00000000;
- pattern_3[3][7] = 0x00000000;
-
-
- pattern_4[0][0] = 0x51c8c049 ;
- pattern_4[0][1] = 0x2d43592c ;
- pattern_4[0][2] = 0x0777b50b ;
- pattern_4[0][3] = 0x9cd2ebe5 ;
- pattern_4[0][4] = 0xc04199d5 ;
- pattern_4[0][5] = 0xdc968dc0 ;
- pattern_4[0][6] = 0xb8ba8a33 ;
- pattern_4[0][7] = 0x35e4327f ;
-
- pattern_4[1][0] = 0xae37c049 ;
- pattern_4[1][1] = 0xd2bc592c ;
- pattern_4[1][2] = 0xf888b50b ;
- pattern_4[1][3] = 0x632debe5 ;
- pattern_4[1][4] = 0x3fbe99d5 ;
- pattern_4[1][5] = 0x23698dc0 ;
- pattern_4[1][6] = 0x47458a33 ;
- pattern_4[1][7] = 0xca1b327f ;
-
- pattern_4[2][0] = 0x51373f49 ;
- pattern_4[2][1] = 0x2dbca62c ;
- pattern_4[2][2] = 0x07884a0b ;
- pattern_4[2][3] = 0x9c2d14e5 ;
- pattern_4[2][4] = 0xc0be66d5 ;
- pattern_4[2][5] = 0xdc6972c0 ;
- pattern_4[2][6] = 0xb8457533 ;
- pattern_4[2][7] = 0x351bcd7f ;
-
-
- pattern_4[3][0] = 0x51c8c049 ;
- pattern_4[3][1] = 0x2d43592c ;
- pattern_4[3][2] = 0x0777b50b ;
- pattern_4[3][3] = 0x9cd2ebe5 ;
- pattern_4[3][4] = 0xc04199d5 ;
- pattern_4[3][5] = 0xdc968dc0 ;
- pattern_4[3][6] = 0xb8ba8a33 ;
- pattern_4[3][7] = 0x35e4327f ;
-
- pattern_5[0][0] = 0xaec9c149 ;
- pattern_5[0][1] = 0xd243592c ;
- pattern_5[0][2] = 0xf877b50b ;
- pattern_5[0][3] = 0x63d2ebe5 ;
- pattern_5[0][4] = 0x3f439bd5 ;
- pattern_5[0][5] = 0x23968dc0 ;
- pattern_5[0][6] = 0x47ba8a33 ;
- pattern_5[0][7] = 0xcae4327f ;
- pattern_5[1][0] = 0xaeccc449 ;
- pattern_5[1][1] = 0xd243592c ;
- pattern_5[1][2] = 0xf877b50b ;
- pattern_5[1][3] = 0x63d2ebe5 ;
- pattern_5[1][4] = 0x3f4991d5 ;
- pattern_5[1][5] = 0x23968dc0 ;
- pattern_5[1][6] = 0x47ba8a33 ;
- pattern_5[1][7] = 0xcae4327f ;
- pattern_5[2][0] = 0xaed8d049 ;
- pattern_5[2][1] = 0xd243592c ;
- pattern_5[2][2] = 0xf877b50b ;
- pattern_5[2][3] = 0x63d2ebe5 ;
- pattern_5[2][4] = 0x3f61b9d5 ;
- pattern_5[2][5] = 0x23968dc0 ;
- pattern_5[2][6] = 0x47ba8a33 ;
- pattern_5[2][7] = 0xcae4327f ;
- pattern_5[3][0] = 0xae888049 ;
- pattern_5[3][1] = 0xd243592c ;
- pattern_5[3][2] = 0xf877b50b ;
- pattern_5[3][3] = 0x63d2ebe5 ;
- pattern_5[3][4] = 0x3fc119d5 ;
- pattern_5[3][5] = 0x23968dc0 ;
- pattern_5[3][6] = 0x47ba8a33 ;
- pattern_5[3][7] = 0xcae4327f ;
-
- pattern_6[0][0] = 0xaec93f49 ;
- pattern_6[0][1] = 0xd243a62c ;
- pattern_6[0][2] = 0xf8774a0b ;
- pattern_6[0][3] = 0x63d214e5 ;
- pattern_6[0][4] = 0x3f4366d5 ;
- pattern_6[0][5] = 0x239672c0 ;
- pattern_6[0][6] = 0x47ba7533 ;
- pattern_6[0][7] = 0xcae4cd7f ;
- pattern_6[1][0] = 0xaecc3f49 ;
- pattern_6[1][1] = 0xd243a62c ;
- pattern_6[1][2] = 0xf8774a0b ;
- pattern_6[1][3] = 0x63d214e5 ;
- pattern_6[1][4] = 0x3f4966d5 ;
- pattern_6[1][5] = 0x239672c0 ;
- pattern_6[1][6] = 0x47ba7533 ;
- pattern_6[1][7] = 0xcae4cd7f ;
- pattern_6[2][0] = 0xaed83f49 ;
- pattern_6[2][1] = 0xd243a62c ;
- pattern_6[2][2] = 0xf8774a0b ;
- pattern_6[2][3] = 0x63d214e5 ;
- pattern_6[2][4] = 0x3f6166d5 ;
- pattern_6[2][5] = 0x239672c0 ;
- pattern_6[2][6] = 0x47ba7533 ;
- pattern_6[2][7] = 0xcae4cd7f ;
- pattern_6[3][0] = 0xae883f49 ;
- pattern_6[3][1] = 0xd243a62c ;
- pattern_6[3][2] = 0xf8774a0b ;
- pattern_6[3][3] = 0x63d214e5 ;
- pattern_6[3][4] = 0x3fc166d5 ;
- pattern_6[3][5] = 0x239672c0 ;
- pattern_6[3][6] = 0x47ba7533 ;
- pattern_6[3][7] = 0xcae4cd7f ;
- */
- //*/
- //*/
- start_addr=0x10000000;
- unsigned int test_size = 0x20;
- unsigned int test_addr;
- unsigned int temp_i=0;
- unsigned int temp_k=0;
- unsigned int pattern_o[8];
- unsigned int pattern_d[8];
- {
- // if(lflag)
- // loop = 888;
-
- //if(old_pattern_flag==1)
- {
-
- printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
-
- /*
- for ((temp_k=0);(temp_k<4);(temp_k++)) {
- {
-
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
- flush_dcache_range(start_addr,start_addr + test_size);
-
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
- //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
- if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
- {error_count++;
- printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
- }
- }
- }
- }
- */
- //if(pattern_flag1==1)
- {
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
- // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
- if ((pattern_o[temp_i]) != (des_pattern(temp_i,1,temp_k,temp_i)))
- {error_count++;
- // printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
- printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,1,temp_k,temp_i),pattern_1[temp_k][temp_i]);
- }
-
-
- }
- }
- }
-
- for ((temp_k=0);(temp_k<4);(temp_k++))
- {
- {
- ddr_udelay(10000);
- for ((temp_i=0);(temp_i<8);(temp_i++))
- {
- test_addr=start_addr+(temp_i<<2);
- *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
- // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
- //des[temp_i]^pattern_2[temp_k][temp_i]
- }
- // _clean_dcache_addr(0x10000000);
-#ifdef DDR_PREFETCH_CACHE
- flush_dcache_range(start_addr,start_addr + test_size);
-#endif
- for ((temp_i=0);(temp_i<8);(temp_i++)) {
- test_addr=start_addr+(temp_i<<2);
- pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
- // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
- // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
- // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
- pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
- if ((des_xor_pattern((des[temp_i]),des_inv_pattern(temp_i,1,temp_k,temp_i))) != pattern_d[temp_i])
- {error_count++;
- printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",
- pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_1[temp_k][temp_i]),pattern_d[temp_i]);
- }
-
- }
- }
- }
-
- }
- }
-
- printf("\Error count==0x%08x", error_count);
- printf("\n \n");
- }
- if (error_count)
- return 1;
- else
- return 0;
-}
-
-#endif
-
-static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
- //#define ddr_pattern_loop 32
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- case 8:
- case 9:
- case 10:
- case 11:
- case 16:
- case 17:
- case 18:
- case 19:
- case 24:
- case 25:
- case 26:
- case 27:
- // case 30:
- *(p+i) = TDATA32F;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- // case 22:
- *(p+i) = 0;
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- // case 30:
- *(p+i) = TDATA32A;
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- *(p+i) = TDATA325;
-
-
- break;
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- *(p+i) =0xfe01fe01;
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- *(p+i) =0xfd02fd02;
- break;
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- *(p+i) =0xfb04fb04;
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- *(p+i) =0xf708f708;
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- *(p+i) =0xef10ef10;
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- *(p+i) =0xdf20df20;
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- *(p+i) =0xbf40bf40;
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- *(p+i) =0x7f807f80;
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- *(p+i) =0x00000100;
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- *(p+i) =0x00000200;
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- *(p+i) =0x00000400;
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- *(p+i) =0x00000800;
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- *(p+i) =0x00001000;
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- *(p+i) =0x00002000;
- break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- *(p+i) =0x00004000;
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- *(p+i) =0x00008000;
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
- //#define ddr_pattern_loop 32
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
-
- switch (i)
- {
-
- case 0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_3+3:
- *(p+i) = 0xfe01fe01;
- break;
- case 4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_3+7:
- *(p+i) = 0xfd02fd02;
- break;
-
- case 8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_3+11:
- *(p+i) = 0xfb04fb04;
- break;
-
- case 12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_3+15:
- *(p+i) = 0xf708f708;
- break;
-
- case 16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_3+19:
- *(p+i) = 0xef10ef10;
- break;
-
- case 20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_3+23:
- *(p+i) = 0xdf20df20;
- break;
-
- case 24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_3+27:
- *(p+i) = 0xbf40bf40;
- break;
-
- case 28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_3+31:
- *(p+i) = 0x7f807f80;
- break;
-
-
- default:
-
- *(p+i) = 0xff00ff00;
- break;
-
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
-
- switch (i)
- {
-
- case 0:
- case 1:
- case 2:
- case 3:
- case 8:
- case 9:
- case 10:
- case 11:
- case 16:
- case 17:
- case 18:
- case 19:
- case 24:
- case 25:
- case 26:
- case 27:
- // case 30:
- // *(p+i) = TDATA32F;
- if (*(p+i) != TDATA32F)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
- break;
- }
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- // case 22:
- // *(p+i) = 0;
- if (*(p+i) != 0)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
- break;}
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- // case 30:
- // *(p+i) = TDATA32A;
- if (*(p+i) != TDATA32A)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- // *(p+i) = TDATA325;
- if (*(p+i) != TDATA325)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- // *(p+i) =0xfe01fe01;
- if (*(p+i) !=0xfe01fe01)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- // *(p+i) =0xfd02fd02;
- if (*(p+i) != 0xfd02fd02)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- // *(p+i) =0xfb04fb04;
- if (*(p+i) != 0xfb04fb04)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- // *(p+i) =0xf7b08f708;
- if (*(p+i) != 0xf708f708)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- // *(p+i) =0xef10ef10;
- if (*(p+i) != 0xef10ef10)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- // *(p+i) =0xdf20df20;
- if (*(p+i) != 0xdf20df20)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- // *(p+i) =0xbf40bf40;
- if (*(p+i) != 0xbf40bf40)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- // *(p+i) =0x7f807f80;
- if (*(p+i) != 0x7f807f80)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
- break;
-
- }
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- // *(p+i) =0x00000100;
- if (*(p+i) != 0x00000100)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000100);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- // *(p+i) =0x00000100;
- if (*(p+i) != 0x00000200)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000200);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- // *(p+i) =0x00000100;
- if (*(p+i) != 0x00000400)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000400);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- // *(p+i) =0x00000100;
- if (*(p+i) != 0x00000800)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000800);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != 0x00001000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00001000);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != 0x00002000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00002000);
-
- } break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != 0x00004000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00004000);
- break;
- }
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != 0x00008000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00008000);
- break;
- }
- break;
-
-
-
- }
- }
-
- if (m_len > 128*4)
- {
- m_len -= 128*4;
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-//*/
-static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
-
- switch (i)
- {
- case 0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_3+3:
- // *(p+i) = 0xfe01fe01;
- if (*(p+i) != 0xfe01fe01)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
- break;
- }
- break;
- case 4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_3+7:
- // *(p+i) = 0xfd02fd02;
- if (*(p+i) != 0xfd02fd02)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
- break;
- }
- break;
-
- case 8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_3+11:
- // *(p+i) = 0xfb04fb04;
- if (*(p+i) != 0xfb04fb04)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
- break;
- }
- break;
-
- case 12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_3+15:
- // *(p+i) = 0xf708f708;
- if (*(p+i) != 0xf708f708)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
- break;
- }
- break;
-
- case 16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_3+19:
- // *(p+i) = 0xef10ef10;
- if (*(p+i) != 0xef10ef10)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
- break;
- }
- break;
-
- case 20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_3+23:
- // *(p+i) = 0xdf20df20;
- if (*(p+i) != 0xdf20df20)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
- break;
- }
- break;
-
- case 24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_3+27:
- // *(p+i) = 0xbf40bf40;
- if (*(p+i) != 0xbf40bf40)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
- break;
- }
- break;
- case 28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_3+31:
- // *(p+i) = 0x7f807f80;
- if (*(p+i) != 0x7f807f80)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
- break;
- }
- break;
-
-
- default:
-
- // *(p+i) = 0xff00ff00;
- if (*(p+i) != 0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
- break;
- }
- break;
-
- break;
-
-
- }
- }
-
- if (m_len > 128*4)
- {
- m_len -= 128*4;
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
- //#define ddr_pattern_loop 32
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- case 8:
- case 9:
- case 10:
- case 11:
- case 16:
- case 17:
- case 18:
- case 19:
- case 24:
- case 25:
- case 26:
- case 27:
- // case 30:
- *(p+i) = ~TDATA32F;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- // case 22:
- *(p+i) = ~0;
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- // case 30:
- *(p+i) = ~TDATA32A;
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- *(p+i) =~TDATA325;
-
-
- break;
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- *(p+i) =~0xfe01fe01;
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- *(p+i) =~0xfd02fd02;
- break;
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- *(p+i) =~0xfb04fb04;
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- *(p+i) =~0xf708f708;
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- *(p+i) =~0xef10ef10;
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- *(p+i) =~0xdf20df20;
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- *(p+i) =~0xbf40bf40;
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- *(p+i) =~0x7f807f80;
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- *(p+i) =~0x00000100;
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- *(p+i) =~0x00000200;
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- *(p+i) =~0x00000400;
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- *(p+i) =~0x00000800;
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- *(p+i) =~0x00001000;
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- *(p+i) =~0x00002000;
- break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- *(p+i) =~0x00004000;
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- *(p+i) =~0x00008000;
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-
-static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
- //#define ddr_pattern_loop 32
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
-
- switch (i)
- {
- case 0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_3+3:
- *(p+i) = ~0xfe01fe01;
- break;
- case 4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_3+7:
- *(p+i) = ~0xfd02fd02;
- break;
-
- case 8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_3+11:
- *(p+i) = ~0xfb04fb04;
- break;
-
- case 12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_3+15:
- *(p+i) = ~0xf708f708;
- break;
-
- case 16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_3+19:
- *(p+i) = ~0xef10ef10;
- break;
-
- case 20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_3+23:
- *(p+i) = ~0xdf20df20;
- break;
-
- case 24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_3+27:
- *(p+i) =~0xbf40bf40;
- break;
- case 28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_3+31:
- *(p+i) = ~0x7f807f80;
- break;
-
-
- default:
-
- *(p+i) = ~0xff00ff00;
- break;
-
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- case 8:
- case 9:
- case 10:
- case 11:
- case 16:
- case 17:
- case 18:
- case 19:
- case 24:
- case 25:
- case 26:
- case 27:
- // case 30:
- // *(p+i) = TDATA32F;
- if (*(p+i) !=~TDATA32F)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA32F);
- break;
- }
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- case 12:
- case 13:
- case 14:
- case 15:
- case 20:
- case 21:
- case 22:
- case 23:
- case 28:
- case 29:
- case 30:
- case 31:
- // case 22:
- // *(p+i) = 0;
- if (*(p+i) !=~0)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0);
- }
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- // case 30:
- // *(p+i) = TDATA32A;
- if (*(p+i) != ~TDATA32A)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),~TDATA32A);
- }
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- // *(p+i) = TDATA325;
- if (*(p+i) != ~TDATA325)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA325);
- }
- break;
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- // *(p+i) =0xfe01fe01;
- if (*(p+i) !=~0xfe01fe01)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01);
- }
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- // *(p+i) =0xfd02fd02;
- if (*(p+i) != ~0xfd02fd02)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02);
- }
- break;
-
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- // *(p+i) =0xfb04fb04;
- if (*(p+i) != ~0xfb04fb04)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04);
- }
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- // *(p+i) =0xf7b08f708;
- if (*(p+i) != ~0xf708f708)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708);
- }
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- // *(p+i) =0xef10ef10;
- if (*(p+i) != ~0xef10ef10)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10);
- }
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- // *(p+i) =0xdf20df20;
- if (*(p+i) != ~0xdf20df20)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20);
- }
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- // *(p+i) =0xbf40bf40;
- if (*(p+i) != ~0xbf40bf40)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40);
- }
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- // *(p+i) =0x7f807f80;
- if (*(p+i) != ~0x7f807f80)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80);
- }
- break;
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- // *(p+i) =0x00000100;
- if (*(p+i) != ~0x00000100)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000100);
- }
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- // *(p+i) =0x00000100;
- if (*(p+i) != ~0x00000200)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000200);
- }
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- // *(p+i) =0x00000100;
- if (*(p+i) != ~0x00000400)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000400);
- }
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- // *(p+i) =0x00000100;
- if (*(p+i) != ~0x00000800)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00000800);
- }
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != ~0x00001000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00001000);
- }
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != ~0x00002000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00002000);
- }
- break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != ~0x00004000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00004000);
- }
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- // *(p+i) =0xfffffeff;
- if (*(p+i) != ~0x00008000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00008000);
- }
- break;
-
-
-
- }
- }
-
- if (m_len > 128*4)
- {
- m_len -= 128*4;
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-
-//*/
-static void ddr_read_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
-
- switch (i)
- {
- case 0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_3+3:
- // *(p+i) = 0xfe01fe01;
- if (*(p+i) != ~0xfe01fe01)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01);
- break;
- }
- break;
- case 4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_3+7:
- // *(p+i) = 0xfd02fd02;
- if (*(p+i) != ~0xfd02fd02)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfd02fd02);
- break;
- }
- break;
-
- case 8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_3+11:
- // *(p+i) = 0xfb04fb04;
- if (*(p+i) != ~0xfb04fb04)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfb04fb04);
- break;
- }
- break;
-
- case 12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_3+15:
- // *(p+i) = 0xf708f708;
- if (*(p+i) != ~0xf708f708)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xf708f708);
- break;
- }
- break;
-
- case 16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_3+19:
- // *(p+i) = 0xef10ef10;
- if (*(p+i) != ~0xef10ef10)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xef10ef10);
- break;
- }
- break;
-
- case 20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_3+23:
- // *(p+i) = 0xdf20df20;
- if (*(p+i) != ~0xdf20df20)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xdf20df20);
- break;
- }
- break;
-
- case 24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_3+27:
- // *(p+i) = 0xbf40bf40;
- if (*(p+i) != ~0xbf40bf40)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xbf40bf40);
- break;
- }
- break;
- case 28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_3+31:
- // *(p+i) = 0x7f807f80;
- if (*(p+i) != ~0x7f807f80)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x7f807f80);
- break;
- }
- break;
-
-
- default:
-
- // *(p+i) = 0xff00ff00;
- if (*(p+i) != ~0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
- break;
- }
- break;
-
- break;
-
-
- }
- }
-
- if (m_len > 128*4)
- {
- m_len -= 128*4;
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_write_pattern4_no_cross_talk(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
- //#define ddr_pattern_loop 32
- p = ( unsigned int *)buff;
-
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- *(p+i) = 0xff00ff00;
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- *(p+i) = 0xffff0000;
- break;
-
- case 8:
- case 9:
- case 10:
- case 11:
- *(p+i) = 0xff000000;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- *(p+i) = 0xff00ffff;
- break;
-
- case 16:
- case 17:
- case 18:
- case 19:
- *(p+i) = 0xff00ffff;
- break;
- case 20:
- case 21:
- case 22:
- case 23:
- *(p+i) = 0xff0000ff;
- break;
- case 24:
- case 25:
- case 26:
- case 27:
- *(p+i) = 0xffff0000;
- break;
-
- case 28:
- case 29:
- case 30:
- case 31:
- *(p+i) = 0x00ff00ff;
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- *(p+i) =~0xff00ff00;
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- *(p+i) =~0xffff0000;
- break;
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- *(p+i) =~0xff000000;
- break;
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- *(p+i) =~0xff00ffff;
- break;
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- *(p+i) =~0xff00ffff;
- break;
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- *(p+i) =~0xff00ffff;
- break;
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- *(p+i) =~0xffff0000;
- break;
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- *(p+i) =~0x00ff00ff;
- break;
-
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- *(p+i) =0x00ff0000;
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- *(p+i) =0xff000000;
- break;
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- *(p+i) =0x0000ffff;
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- *(p+i) =0x000000ff;
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- *(p+i) =0x00ff00ff;
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- *(p+i) =0xff00ff00;
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- *(p+i) =0xff00ffff;
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- *(p+i) =0xff00ff00;
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- *(p+i) =~0x00ff0000;
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- *(p+i) =~0xff000000;
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- *(p+i) =~0x0000ffff;
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- *(p+i) =~0x000000ff;
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- *(p+i) =~0x00ff00ff;
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- *(p+i) =~0xff00ff00;
- break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- *(p+i) =~0xff00ffff;
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- *(p+i) =~0xff00ff00;
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-static void ddr_read_pattern4_no_cross_talk(void *buff, unsigned int m_length)
-{
- unsigned int *p;
- // unsigned int i, j, n;
- unsigned int i, n;
- unsigned int m_len = m_length;
-
- p = ( unsigned int *)buff;
- while (m_len)
- {
- // for(j=0;j<32;j++)
- {
- if (m_len >= 128*4)
- n = 32*4;
- else
- n = m_len>>2;
-
- for (i = 0; i < n; i++)
- {
-#ifdef DDR_PREFETCH_CACHE
- ddr_pld_cache(p) ;
-#endif
- if ((error_outof_count_flag) && (error_count))
- {
- printf("Error data out of count");
- m_len=0;
- break;
- }
- switch (i)
- {
- case 0:
- case 1:
- case 2:
- case 3:
- // if(*(p+i) !=~TDATA32F)
-
- if ( *(p+i) != 0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
- }
- break;
- case 4:
- case 5:
- case 6:
- case 7:
- if ( *(p+i) != 0xffff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000);
- }
- break;
-
- case 8:
- case 9:
- case 10:
- case 11:
- // *(p+i) = 0xff000000;
- if ( *(p+i) != 0xff000000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000);
- }
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- // *(p+i) = 0xff00ffff;
- if ( *(p+i) != 0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
- }
- break;
-
- case 16:
- case 17:
- case 18:
- case 19:
- // *(p+i) = 0xff00ffff;
- if ( *(p+i) != 0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
- }
- break;
- case 20:
- case 21:
- case 22:
- case 23:
- // *(p+i) = 0xff0000ff;
- if ( *(p+i) != 0xff0000ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff0000ff);
- }
- break;
- case 24:
- case 25:
- case 26:
- case 27:
- // *(p+i) = 0xffff0000;
- if ( *(p+i) != 0xffff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xffff0000);
- }
- break;
-
- case 28:
- case 29:
- case 30:
- case 31:
- // *(p+i) = 0x00ff00ff;
- if ( *(p+i) != 0x00ff00ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff);
- }
- break;
- case DDR_PATTERN_LOOP_1+0:
- case DDR_PATTERN_LOOP_1+1:
- case DDR_PATTERN_LOOP_1+2:
- case DDR_PATTERN_LOOP_1+3:
- // *(p+i) =~0xff00ff00;
- if ( *(p+i) != ~0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
- }
- break;
- case DDR_PATTERN_LOOP_1+4:
- case DDR_PATTERN_LOOP_1+5:
- case DDR_PATTERN_LOOP_1+6:
- case DDR_PATTERN_LOOP_1+7:
- // *(p+i) =~0xffff0000;
- if ( *(p+i) != ~0xffff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000);
- }
- break;
- case DDR_PATTERN_LOOP_1+8:
- case DDR_PATTERN_LOOP_1+9:
- case DDR_PATTERN_LOOP_1+10:
- case DDR_PATTERN_LOOP_1+11:
- // *(p+i) =~0xff000000;
- if ( *(p+i) != ~0xff000000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000);
- }
- break;
- case DDR_PATTERN_LOOP_1+12:
- case DDR_PATTERN_LOOP_1+13:
- case DDR_PATTERN_LOOP_1+14:
- case DDR_PATTERN_LOOP_1+15:
- // *(p+i) =~0xff00ffff;
- if ( *(p+i) != ~0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
- }
- break;
- case DDR_PATTERN_LOOP_1+16:
- case DDR_PATTERN_LOOP_1+17:
- case DDR_PATTERN_LOOP_1+18:
- case DDR_PATTERN_LOOP_1+19:
- // *(p+i) =~0xff00ffff;
- if ( *(p+i) != ~0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
- }
- break;
- case DDR_PATTERN_LOOP_1+20:
- case DDR_PATTERN_LOOP_1+21:
- case DDR_PATTERN_LOOP_1+22:
- case DDR_PATTERN_LOOP_1+23:
- // *(p+i) =~0xff00ffff;
- if ( *(p+i) != ~0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
- }
- break;
- case DDR_PATTERN_LOOP_1+24:
- case DDR_PATTERN_LOOP_1+25:
- case DDR_PATTERN_LOOP_1+26:
- case DDR_PATTERN_LOOP_1+27:
- // *(p+i) =~0xffff0000;
- if ( *(p+i) != ~0xffff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xffff0000);
- }
- break;
- case DDR_PATTERN_LOOP_1+28:
- case DDR_PATTERN_LOOP_1+29:
- case DDR_PATTERN_LOOP_1+30:
- case DDR_PATTERN_LOOP_1+31:
- // *(p+i) =~0x00ff00ff;
- if ( *(p+i) != ~0x00ff00ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff);
- }
- break;
-
- case DDR_PATTERN_LOOP_2+0:
- case DDR_PATTERN_LOOP_2+1:
- case DDR_PATTERN_LOOP_2+2:
- case DDR_PATTERN_LOOP_2+3:
- // *(p+i) =0x00ff0000;
- if ( *(p+i) != 0x00ff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff0000);
- }
- break;
- case DDR_PATTERN_LOOP_2+4:
- case DDR_PATTERN_LOOP_2+5:
- case DDR_PATTERN_LOOP_2+6:
- case DDR_PATTERN_LOOP_2+7:
- // *(p+i) =0xff000000;
- if ( *(p+i) != 0xff000000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff000000);
- }
- break;
- case DDR_PATTERN_LOOP_2+8:
- case DDR_PATTERN_LOOP_2+9:
- case DDR_PATTERN_LOOP_2+10:
- case DDR_PATTERN_LOOP_2+11:
- // *(p+i) =0x0000ffff;
- if ( *(p+i) != 0x0000ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x0000ffff);
- }
- break;
- case DDR_PATTERN_LOOP_2+12:
- case DDR_PATTERN_LOOP_2+13:
- case DDR_PATTERN_LOOP_2+14:
- case DDR_PATTERN_LOOP_2+15:
- // *(p+i) =0x000000ff;
- if ( *(p+i) != 0x000000ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x000000ff);
- }
- break;
- case DDR_PATTERN_LOOP_2+16:
- case DDR_PATTERN_LOOP_2+17:
- case DDR_PATTERN_LOOP_2+18:
- case DDR_PATTERN_LOOP_2+19:
- // *(p+i) =0x00ff00ff;
- if ( *(p+i) != 0x00ff00ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00ff00ff);
- }
- break;
- case DDR_PATTERN_LOOP_2+20:
- case DDR_PATTERN_LOOP_2+21:
- case DDR_PATTERN_LOOP_2+22:
- case DDR_PATTERN_LOOP_2+23:
- // *(p+i) =0xff00ff00;
- if ( *(p+i) != 0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
- }
- break;
- case DDR_PATTERN_LOOP_2+24:
- case DDR_PATTERN_LOOP_2+25:
- case DDR_PATTERN_LOOP_2+26:
- case DDR_PATTERN_LOOP_2+27:
- // *(p+i) =0xff00ffff;
- if ( *(p+i) != 0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ffff);
- }
- break;
- case DDR_PATTERN_LOOP_2+28:
- case DDR_PATTERN_LOOP_2+29:
- case DDR_PATTERN_LOOP_2+30:
- case DDR_PATTERN_LOOP_2+31:
- // *(p+i) =0xff00ff00;
- if ( *(p+i) != 0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
- }
- break;
- case DDR_PATTERN_LOOP_3+0:
- case DDR_PATTERN_LOOP_3+1:
- case DDR_PATTERN_LOOP_3+2:
- case DDR_PATTERN_LOOP_3+3:
- // *(p+i) =~0x00ff0000;
- if ( *(p+i) != ~0x00ff0000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff0000);
- }
- break;
- case DDR_PATTERN_LOOP_3+4:
- case DDR_PATTERN_LOOP_3+5:
- case DDR_PATTERN_LOOP_3+6:
- case DDR_PATTERN_LOOP_3+7:
- // *(p+i) =~0xff000000;
- if ( *(p+i) != ~0xff000000)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff000000);
- }
- break;
- case DDR_PATTERN_LOOP_3+8:
- case DDR_PATTERN_LOOP_3+9:
- case DDR_PATTERN_LOOP_3+10:
- case DDR_PATTERN_LOOP_3+11:
- // *(p+i) =~0x0000ffff;
- if ( *(p+i) != ~0x0000ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x0000ffff);
- }
- break;
- case DDR_PATTERN_LOOP_3+12:
- case DDR_PATTERN_LOOP_3+13:
- case DDR_PATTERN_LOOP_3+14:
- case DDR_PATTERN_LOOP_3+15:
- // *(p+i) =~0x000000ff;
- if ( *(p+i) != ~0x000000ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x000000ff);
- }
- break;
- case DDR_PATTERN_LOOP_3+16:
- case DDR_PATTERN_LOOP_3+17:
- case DDR_PATTERN_LOOP_3+18:
- case DDR_PATTERN_LOOP_3+19:
- // *(p+i) =~0x00ff00ff;
- if ( *(p+i) != ~0x00ff00ff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0x00ff00ff);
- }
- break;
- case DDR_PATTERN_LOOP_3+20:
- case DDR_PATTERN_LOOP_3+21:
- case DDR_PATTERN_LOOP_3+22:
- case DDR_PATTERN_LOOP_3+23:
- // *(p+i) =~0xff00ff00;
- if ( *(p+i) != ~0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
- }
- break;
- case DDR_PATTERN_LOOP_3+24:
- case DDR_PATTERN_LOOP_3+25:
- case DDR_PATTERN_LOOP_3+26:
- case DDR_PATTERN_LOOP_3+27:
- // *(p+i) =~0xff00ffff;
- if ( *(p+i) != ~0xff00ffff)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ffff);
- }
- break;
- case DDR_PATTERN_LOOP_3+28:
- case DDR_PATTERN_LOOP_3+29:
- case DDR_PATTERN_LOOP_3+30:
- case DDR_PATTERN_LOOP_3+31:
- // *(p+i) =~0xff00ff00;
- if ( *(p+i) != ~0xff00ff00)
- {error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xff00ff00);
- }
- break;
-
-
- }
- }
-
- if (m_len >( 128*4))
- {
- m_len -=( 128*4);
- p += 32*4;
- }
- else
- {
- p += (m_len>>2);
- m_len = 0;
- break;
- }
- }
- }
-}
-
-
-
-int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *endp;
- unsigned int loop = 1;
- unsigned int lflag = 0;
- unsigned int start_addr = DDR_TEST_START_ADDR;
- unsigned int test_size = DDR_TEST_SIZE;
- unsigned int simple_pattern_flag = 1;
- unsigned int cross_talk_pattern_flag = 1;
- unsigned int old_pattern_flag = 1;
-
- unsigned int print_flag = 1;
- // copy_test_flag = 0;
- print_flag = 1;
- error_outof_count_flag =0;
- error_count =0;
- printf("\nargc== 0x%08x\n", argc);
- int i ;
- for (i = 0;i<argc;i++)
- {
- printf("\nargv[%d]=%s\n",i,argv[i]);
- }
- if (!argc)
- goto DDR_TEST_START;
- if (argc > 1) {
- if (strcmp(argv[1], "l") == 0) {
- lflag = 1;
- }
- else if (strcmp(argv[1], "h") == 0){
- goto usage;
- }
- else{
- loop = simple_strtoull_ddr(argv[1], &endp, 10);
- if (*argv[1] == 0 || *endp != 0)
- loop = 1;
- }
- }
- // printf("\nLINE== 0x%08x\n", __LINE__);
- if (argc ==1) {
- // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- // if (*argv[2] == 0 || *endp != 0)
- start_addr = DDR_TEST_START_ADDR;
- loop = 1;
-
- }
- if (argc > 2) {
- start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- if (*argv[2] == 0 || *endp != 0)
- start_addr = DDR_TEST_START_ADDR;
-
- }
- if (argc > 3) {
- test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- test_size = DDR_TEST_SIZE;
-
- }
- if (test_size<0x1000)
- test_size = DDR_TEST_SIZE;
-
- old_pattern_flag = 1;
- simple_pattern_flag = 1;
- cross_talk_pattern_flag = 1;
- //printf("\nLINE== 0x%08x\n", __LINE__);
- if (argc ==2) {
- if ( (strcmp(argv[1], "s") == 0))
- {
- simple_pattern_flag = 1;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 0;
- }
- else if ((strcmp(argv[1], "c") == 0))
- {
- simple_pattern_flag = 0;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 1;
- }
- else if ( (strcmp(argv[1], "e") == 0))
- {
- error_outof_count_flag=1;
- }
- }
- if (argc >2) {
- if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0))
- {
- print_flag = 0;
- }
- if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0))
- {
- copy_test_flag = 1;
- }
- if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0))
- {
- simple_pattern_flag = 1;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 0;
- }
- else if ((strcmp(argv[1], "c") == 0)||(strcmp(argv[2], "c") == 0))
- {
- simple_pattern_flag = 0;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 1;
- }
- else if ( (strcmp(argv[1], "e") == 0)||(strcmp(argv[2], "e") == 0))
- {
- error_outof_count_flag=1;
- }
- }
- //printf("\nLINE1== 0x%08x\n", __LINE__);
- if (argc > 3) {
- if ( (strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0) || (strcmp(argv[3], "p") == 0))
- {
- copy_test_flag = 1;
- }
- if ( (strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0) || (strcmp(argv[3], "n") == 0))
- {
- print_flag = 0;
- }
- if ( (strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0) || (strcmp(argv[3], "s") == 0))
- {
- simple_pattern_flag = 1;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 0;
- }
- if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0) || (strcmp(argv[3], "c") == 0))
- {
- simple_pattern_flag = 0;
- old_pattern_flag=0;
- cross_talk_pattern_flag = 1;
- }
- if ( (strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0) || (strcmp(argv[3], "e") == 0))
- {
- error_outof_count_flag=1;
- }
- }
-
- // printf("\nLINE2== 0x%08x\n", __LINE__);
- // printf("\nLINE3== 0x%08x\n", __LINE__);
- // printf("\nLINE== 0x%08x\n", __LINE__);
-
-DDR_TEST_START:
-
- ///*
- do {
- if (lflag)
- loop = 888;
-
- if (old_pattern_flag == 1)
- {
- {
- // printf("\nLINE== 0x%08x\n", __LINE__);
- //printf("\nLINE== 0x%08x\n", __LINE__);
- //printf("\nLINE== 0x%08x\n", __LINE__);
- if (print_flag)
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
- ddr_write((void *)(int_convter_p(start_addr)), test_size);
- // flush_dcache_range(start_addr,start_addr + test_size);
- if (print_flag) {
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- }
- ddr_read((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");}
- ddr_read((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\nEnd 2nd read. ");
- printf("\nStart 3rd reading... ");}
- ddr_read((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag)
- printf("\nEnd 3rd read. \n");
-
- if (copy_test_flag)
- {if(print_flag)
- printf("\n copy_test_flag = 1,start copy test. \n");
- ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
- ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- ddr_read((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- }
-
- }
- {
- // printf("\nLINE== 0x%08x\n", __LINE__);
- //printf("\nLINE== 0x%08x\n", __LINE__);
- //printf("\nLINE== 0x%08x\n", __LINE__);
- if (print_flag) {
- printf("\nStart *4 normal pattern. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
- }
- ddr_write4((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");}
- ddr_read4((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");}
- ddr_read4((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\nEnd 2nd read. ");
- printf("\nStart 3rd reading... ");}
- ddr_read4((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag)
- printf("\rEnd 3rd read. \n");
- if (copy_test_flag)
- {
-
- ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
- ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- ddr_read4((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- }
-
-
- }
- }
-
- if (simple_pattern_flag == 1)
- {
- if (print_flag) {
- printf("\nStart *4 no cross talk pattern. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
- }
- ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");}
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");}
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 2nd read. ");
- printf("\rStart 3rd reading... ");}
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag)
- printf("\rEnd 3rd read. \n");
-
- if (copy_test_flag)
- {
- ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- }
-
- }
-
- if (cross_talk_pattern_flag == 1)
- {if(print_flag){
- printf("\nStart *4 cross talk pattern p. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
- }
- ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");}
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");}
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 2nd read. ");
- printf("\rStart 3rd reading... ");}
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 3rd read. \n");
-
- printf("\nStart *4 cross talk pattern n. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
- ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");}
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");}
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 2nd read. ");
- printf("\rStart 3rd reading... ");}
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 3rd read. \n");
-
- ///*
- printf("\nStart *4 cross talk pattern p2. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
- ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");}
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");}
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 2nd read. ");
- printf("\rStart 3rd reading... ");}
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 3rd read. \n");
-
- printf("\nStart *4 cross talk pattern n2. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);}
- ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");}
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");}
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag) {
- printf("\rEnd 2nd read. ");
- printf("\rStart 3rd reading... ");}
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
- if (print_flag)
- printf("\rEnd 3rd read. \n");
-
- if (copy_test_flag)
- {
- ddr_test_copy((void *)(int_convter_p(start_addr+test_size/2)),(void *)(int_convter_p(start_addr)), test_size/2 );
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+test_size/2)), test_size/2);
- }
- // */
-
- }
-
- if (print_flag)
- printf("\nError count==0x%08x", error_count);
-
- }while(--loop);
- //*/
-
- printf("\rEnd ddr test. \n");
-
- return 0;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-}
-
-U_BOOT_CMD(
- ddrtest, 5, 1, do_ddr_test,
- "DDR test function",
- "ddrtest [LOOP] [ADDR].Default address is 0x8d000000\n"
-);
-
-int do_ddr_special_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *endp;
- unsigned int loop = 1;
- unsigned int lflag = 0;
- unsigned int start_addr = DDR_TEST_START_ADDR;
- unsigned int test_addr = DDR_TEST_START_ADDR;
- unsigned int test_size = DDR_TEST_SIZE;
- unsigned int write_times = 1;
- unsigned int read_times = 3;
- // unsigned int old_pattern_flag = 1;
-
- unsigned int print_flag = 1;
- // copy_test_flag = 0;
- print_flag = 1;
- error_outof_count_flag =0;
- error_count =0;
- printf("\nargc== 0x%08x\n", argc);
- int i ;
- for (i = 0;i<argc;i++)
- {
- printf("\nargv[%d]=%s\n",i,argv[i]);
- }
-
- if (strcmp(argv[1], "l") == 0) {
- lflag = 1;
- }
- else if (strcmp(argv[1], "h") == 0){
- goto usage;
- }
- else{
- loop = simple_strtoull_ddr(argv[1], &endp, 10);
- if (*argv[1] == 0 || *endp != 0)
- loop = 1;
- }
-
- // printf("\nLINE== 0x%08x\n", __LINE__);
- if (argc ==1) {
- // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- // if (*argv[2] == 0 || *endp != 0)
- start_addr = DDR_TEST_START_ADDR;
- loop = 1;
-
- }
- if (argc > 2) {
- start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
- if (*argv[2] == 0 || *endp != 0)
- start_addr = DDR_TEST_START_ADDR;
-
- }
- if (argc > 3) {
- test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- test_size = DDR_TEST_SIZE;
-
- }
- if (test_size<0x1000)
- test_size = DDR_TEST_SIZE;
- if (argc > 4) {
- write_times = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- write_times = 0;
-
- }
- if (argc > 5) {
- read_times = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- read_times = 0;
-
- }
- unsigned int base_pattern = 1;
- unsigned int inc_flag = 1;
- if (argc > 6) {
- base_pattern = simple_strtoull_ddr(argv[6], &endp, 16);
- if (*argv[6] == 0 || *endp != 0)
- base_pattern = 0;
-
- }
- if (argc > 7) {
- inc_flag = simple_strtoull_ddr(argv[7], &endp, 16);
- if (*argv[7] == 0 || *endp != 0)
- inc_flag = 0;
-
- }
-
-
- //printf("\nLINE== 0x%08x\n", __LINE__);
-
- //printf("\nLINE1== 0x%08x\n", __LINE__);
-
-
- // printf("\nLINE2== 0x%08x\n", __LINE__);
- // printf("\nLINE3== 0x%08x\n", __LINE__);
- // printf("\nLINE== 0x%08x\n", __LINE__);
-
-
- unsigned int count = 1;
- unsigned int test_val = 1;
-
- ///*
- do {
- if (lflag)
- loop = 888;
-
- if (1)
- {
-
- for (i=0;i<write_times;)
- {i++;
-
- printf("\nwrite_times==0x%08x \n",((unsigned int)i));
- // serial_put_hex(((unsigned long)i),32);
- // count=count_max;
- // reg=reg_base;
- // val=val_base;
- test_addr=start_addr;
- test_val=base_pattern;
- count=(test_size>>2);
- do
- {
- writel(test_val,(unsigned long)test_addr);
- test_addr=test_addr+4;
- if (inc_flag)
- test_val=test_val+1;
-
- }
- while (count--) ;
- }
-
- for (i=0;i<read_times;)
- {i++;
- printf("\nread_times==0x%08x \n",((unsigned int)i));
- //serial_puts("\nread_times= ");
- // serial_put_hex(((unsigned long)i),32);
- test_addr=start_addr;
- test_val=base_pattern;
- count=(test_size>>2);
-
- do
- {
-
- //writel(val,(unsigned long)reg);
- if (test_val != (readl((unsigned long)test_addr))) {
-
- printf("\nadd==0x%08x,pattern==0x%08x,read==0x%08x \n",((unsigned int)test_addr),((unsigned int)test_val),(readl((unsigned int)test_addr)));
- }
- test_addr=test_addr+4;
- if (inc_flag)
- test_val=test_val+1;
- }
- while (count--) ;
- }
- }
-
-
-
- if (print_flag)
- printf("\nError count==0x%08x", error_count);
-
- }while(--loop);
- //*/
-
- printf("\rEnd ddr test. \n");
-
- return 0;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-}
-U_BOOT_CMD(
- ddr_spec_test, 8, 1, do_ddr_special_test,
- "DDR test function",
- "ddrtest [LOOP] [ADDR] [size] [write_times] [read times] [pattern] [inc].ddr_spec_test 1 0x1080000 0x200000 1 3 1 1 \n"
-);
-/*
-int do_mw_mask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-char *endp;
-unsigned int reg_add=0;
-unsigned int wr_reg_value=0;
-unsigned int rd_reg_value=0;
-unsigned int wr_reg_and_mask_1=0xffffffff;
-if (argc == 1)
-{ printf("\nplease read help\n");
-printf("\nexample only change 0xc8836800 0x8c010226 0x000fffff bit20-bit31,no change pll od oc \n");
-printf("\nmwm 0xc8836800 0x8c010226 0x000fffff\n");
-}
-else{
-if (argc >= 2)
-{
-reg_add = simple_strtoull_ddr(argv[1], &endp, 10);
-}
-if (argc >= 3)
-{
-wr_reg_value = simple_strtoull_ddr(argv[2], &endp, 10);
-}
-if (argc >= 4)
-{
-wr_reg_and_mask_1 = simple_strtoull_ddr(argv[3], &endp, 10);
-
-}
-rd_reg_value= (rd_reg(reg_add));
-wr_reg(reg_add,(rd_reg_value&wr_reg_and_mask_1)|(wr_reg_value&(~wr_reg_and_mask_1)) );
-
-printf("\nmodify ok read==0x%08x\n",(rd_reg(reg_add)));
-
-}
-return 1;
-}
-U_BOOT_CMD(
- mwm, 30, 1, do_mw_mask,
- "mw mask function",
- "mw 0xc8836800 0x8c82022c 0x000fffff\n"
-);
-*/
-
-///*
-
-int ddr_test_s_cross_talk_pattern(int ddr_test_size)
-{
-#define TEST_OFFSET 0//0X40000000
- // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET;
- unsigned int start_addr=test_start_addr;
-
- error_outof_count_flag=1;
-
- error_count=0;
-
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- training_pattern_flag=0;
-#endif
- ///*
- if (training_pattern_flag)
- {
-#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
- ddr_test_gx_training_pattern(ddr_test_size);
-#endif
- if (error_count)
- return 1;
- else
- return 0;
- }
- else
- {
-#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
- ddr_test_gx_training_pattern(ddr_test_size);
-#endif
-
- }
- // */
- /*
- ddr_test_gx_cross_talk_pattern( ddr_test_size);
- if (error_count)
- return 1;
- else
- return 0;
- */
- {
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
- if (error_count)
- return error_count;
- printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
-
- if (error_count)
- return error_count;
- printf("\nStart *4 no cross talk pattern. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- }
-
- if (error_count)
- return error_count;
- //if(cross_talk_pattern_flag==1)
- {
- printf("\nStart *4 cross talk pattern p. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
-
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
-
- if (error_count)
- return error_count;
- printf("\nStart *4 cross talk pattern n. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
- }
- if (error_count)
- return error_count;
- {
- printf("\nStart *4 cross talk pattern p2. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
-
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
- if (error_count)
- return error_count;
- printf("\nStart *4 cross talk pattern n. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
- if (copy_test_flag)
- {
- if (error_count)
- return error_count;
- printf("\n start copy test ... ");
- ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 );
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
- }
- }
-
- if (error_count)
- return 1;
- else
- return 0;
- }
-
-
-
-int ddr_test_s_cross_talk_pattern_quick_retrun(int ddr_test_size)
-{
- error_outof_count_flag =1;
- #define TEST_OFFSET 0//0X40000000
- // unsigned int start_addr = DDR_TEST_START_ADDR+TEST_OFFSET;
- unsigned int start_addr=test_start_addr;
-
- error_outof_count_flag=1;
-
- error_count=0;
-
- #if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- training_pattern_flag=0;
- #endif
- ///*
- if (training_pattern_flag)
- {
- #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
- ddr_test_gx_training_pattern(ddr_test_size);
- #endif
- if (error_count)
- return 1;
- else
- return 0;
- }
- else
- {
- #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
- ddr_test_gx_training_pattern(ddr_test_size);
- #endif
- }
- // */
- /*
- ddr_test_gx_cross_talk_pattern( ddr_test_size);
- if (error_count)
- return 1;
- else
- return 0;
- */
-
- {
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
-
- printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
-
- printf("\nStart *4 no cross talk pattern. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd write. ");
- printf("\nStart 1st reading... ");
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\nEnd 1st read. ");
- printf("\nStart 2nd reading... ");
- ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
- }
- //if(cross_talk_pattern_flag==1)
- {
- printf("\nStart *4 cross talk pattern p. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
-
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
-
- printf("\nStart *4 cross talk pattern n. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
-
-
- }
-
- {
- printf("\nStart *4 cross talk pattern p2. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
-
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_p((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
-
- printf("\nStart *4 cross talk pattern n. ");
- printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
- ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd write. ");
- printf("\rStart 1st reading... ");
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 1st read. ");
- printf("\rStart 2nd reading... ");
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
- printf("\rEnd 2nd read. ");
- // printf("\rStart 3rd reading... ");
- // ddr_read_pattern4_cross_talk_n((void *)start_addr, ddr_test_size);
- // printf("\rEnd 3rd read. \n");
- if (copy_test_flag)
- {
- printf("\n start copy test ... ");
- ddr_test_copy((void *)(int_convter_p(start_addr+ddr_test_size/2)),(void *)(int_convter_p(start_addr)), ddr_test_size/2 );
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
- ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr+ddr_test_size/2)), ddr_test_size/2);
- }
-
- }
-
- if (error_count)
- return 1;
- else
- return 0;
-}
-
-#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
-int do_ddr_test_dqs_window_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter test ddr dqs window step function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- printf("\nargc== 0x%08x\n", argc);
-
- unsigned int temp_test_error= 0;
-
- char *endp;
- // unsigned int *p_start_addr;
- unsigned int test_lane_step=0;
- unsigned int testing_lane=0;
- unsigned int test_lane_step_rdqs_flag=0;
- unsigned int test_min_max_flag=0;
- unsigned int test_times=1;
- unsigned int reg_add=0;
- unsigned int reg_base_adj=0;
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
-
- unsigned int dq_lcd_bdl_reg_org=0;
- unsigned int dq_lcd_bdl_reg_left=0;
- unsigned int dq_lcd_bdl_reg_right=0;
-
- unsigned int dq_lcd_bdl_reg_left_min=0;
- unsigned int dq_lcd_bdl_reg_right_min=0;
-
- unsigned int dq_lcd_bdl_temp_reg_value=0;
-
- // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_lef;
- // unsigned int dq_lcd_bdl_temp_reg_rig;
-
- unsigned int ddr_test_size= DDR_TEST_SIZE;//DDR_CORSS_TALK_TEST_SIZE;
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
- {
- channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
- {
- channel_b_en = 1;
- }
- else
- {
- goto usage;
- }
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
- {
- channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
- {
- channel_b_en = 1;
- }
- }
- ddr_test_size = DDR_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_TEST_SIZE;
- }
- }
- if (argc >4) {
- test_lane_step = 0;
- test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- {
- test_lane_step = 0;
- }
- if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
- {
- test_lane_step = 0;
- }
- }
- if (test_lane_step >7)
- test_lane_step = 0;
- unsigned int test_loop=1;
- if (argc >5) {
- test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- {
- test_min_max_flag = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- unsigned int test_temp_value_use_sticky_register=0;
- if (argc >6) {
- test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
- if (*argv[6] == 0 || *endp != 0)
- {
- test_temp_value_use_sticky_register = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
-
- printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
- printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
- printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
- printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
- printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
- printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
-
- const char *temp_s;
- char *env_lcdlr_temp_count;
- char *buf;
- buf="";
- unsigned int lcdlr_temp_count=0;
- env_lcdlr_temp_count="lcdlr_temp_count";
-
- if(test_temp_value_use_sticky_register)
- {
- lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
- }
- else
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- else
- {
- lcdlr_temp_count=0;
- }
- }
-
- //if ( channel_a_en)
- {
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
- }
- //if ( channel_b_en)
- {
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
- }
-
-for (test_times=0;(test_times<test_loop);(test_times++))
-{
- ////tune and save training dqs value
- if (channel_a_en || channel_b_en)
- {
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
-
- {
- printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
- writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
- printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
- {
- printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
- writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
- printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
- }
- if (test_lane_step>8)
- test_lane_step=0;
- printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
-
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_lane_step>>1);
- test_lane_step_rdqs_flag=test_lane_step%2;
- testing_lane=(test_lane_step>>1);
-
- dq_lcd_bdl_temp_reg_value=readl(reg_add);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
-
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- if (test_lane_step_rdqs_flag)
- {
- dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0xff00)>>8);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
- else
- {
- dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0x00ff)>>0);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
- #endif
-
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
- {
- while (dq_lcd_bdl_temp_reg_value>0)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value--;
-
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
- }
-
- printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
- if (!test_lane_step_rdqs_flag)
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
- #else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- #endif
- }
- else
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
- #endif
- }
- printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
-
- if (temp_test_error)
- {
- //printf("\nwdqd left edge detect \n");
- dq_lcd_bdl_temp_reg_value++;
- break;
- }
- }
- printf("\n left edge detect \n");
- printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
- dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
- if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
- }
- }
- else
- {
- printf("\n left edge skip \n");
- }
-
- if (!test_lane_step_rdqs_flag)
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
- #else
- writel(dq_lcd_bdl_reg_org,reg_add);
- #endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- }
- else
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
- #else
- #endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
-
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
-
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
-
-
- if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
- {
- while (dq_lcd_bdl_temp_reg_value<DQLCDLR_MAX)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value++;
-
-
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
- if (!test_lane_step_rdqs_flag)
- {
- //writel(dq_lcd_bdl_temp_reg_value,reg_add);
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
- #else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- #endif
- }
- else
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
- #endif
- // writel(dq_lcd_bdl_temp_reg_value,reg_add);
- // writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
- printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd right edge detect \n");
- dq_lcd_bdl_temp_reg_value--;
- break;
- }
- }
- printf("\n right edge detect \n");
- printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
- dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
- if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
- }
- }
-
- if (!test_lane_step_rdqs_flag)
- {
- // writel(dq_lcd_bdl_reg_org,reg_add);
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
- #else
- writel(dq_lcd_bdl_reg_org,reg_add);
- #endif
- }
- else
- {
- #if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
- #endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
- printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
- printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- }
- }
-
-}
-
- dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
- if (!test_lane_step_rdqs_flag)
- {
- if(channel_a_en)
- {
- dq_lcd_bdl_value_wdq_org_a[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_wdq_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_wdq_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- if (channel_b_en)
- {
- dq_lcd_bdl_value_wdq_org_b[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_wdq_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_wdq_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- }
- else
- {
- if (channel_a_en) {
- dq_lcd_bdl_value_rdqs_org_a[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_rdqs_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_rdqs_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- if (channel_b_en) {
- dq_lcd_bdl_value_rdqs_org_b[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_rdqs_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_rdqs_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- }
-
- return dq_lcd_bdl_temp_reg_value;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-
-}
-U_BOOT_CMD(
- ddr_tune_dqs_step, 7, 1, do_ddr_test_dqs_window_step,
- "ddr_tune_dqs_step function",
- "ddr_tune_dqs_step a 0 0x80000 3 or ddr_tune_dqs_step b 0 0x80000 5 \n dcache off ? \n"
-);
-#else
-
-int do_ddr_test_fine_tune_dqs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter Tune ddr dqs function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- printf("\nargc== 0x%08x\n", argc);
- // unsigned int loop = 1;
- unsigned int temp_count_i = 1;
- unsigned int temp_count_j= 1;
- unsigned int temp_count_k= 1;
- unsigned int temp_test_error= 0;
-
-
- char *endp;
- // unsigned int *p_start_addr;
- unsigned int test_loop=1;
- unsigned int test_times=1;
- unsigned int reg_add=0;
- unsigned int reg_base_adj=0;
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
- unsigned int testing_channel = 0;
-
-#define DATX8_DQ_LCD_BDL_REG_WIDTH 12
-
-#define DATX8_DQ_LANE_WIDTH 4
-#define CHANNEL_CHANNEL_WIDTH 2
-
-#define CHANNEL_A 0
-#define CHANNEL_B 1
-
-
-
-#define DATX8_DQ_LANE_LANE00 0
-#define DATX8_DQ_LANE_LANE01 1
-#define DATX8_DQ_LANE_LANE02 2
-#define DATX8_DQ_LANE_LANE03 3
-
-#define DATX8_DQ_BDLR0 0
-#define DATX8_DQ_BDLR1 1
-#define DATX8_DQ_BDLR2 2
-#define DATX8_DQ_BDLR3 3
-#define DATX8_DQ_BDLR4 4
-#define DATX8_DQ_BDLR5 5
-#define DATX8_DQ_BDLR6 6
-#define DATX8_DQ_DXNLCDLR0 7
-#define DATX8_DQ_DXNLCDLR1 8
-#define DATX8_DQ_DXNLCDLR2 9
-#define DATX8_DQ_DXNMDLR 10
-#define DATX8_DQ_DXNGTR 11
-
-
-#define DDR_CORSS_TALK_TEST_SIZE 0x20000
-
-#define DQ_LCD_BDL_REG_NUM_PER_CHANNEL DATX8_DQ_LCD_BDL_REG_WIDTH*DATX8_DQ_LANE_WIDTH
-#define DQ_LCD_BDL_REG_NUM DQ_LCD_BDL_REG_NUM_PER_CHANNEL*CHANNEL_CHANNEL_WIDTH
-
- unsigned int dq_lcd_bdl_reg_org[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_left[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_right[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_index[DQ_LCD_BDL_REG_NUM];
-
- unsigned int dq_lcd_bdl_reg_left_min[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_right_min[DQ_LCD_BDL_REG_NUM];
-
- unsigned int dq_lcd_bdl_temp_reg_value;
- unsigned int dq_lcd_bdl_temp_reg_value_dqs;
- unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
- unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
- // unsigned int dq_lcd_bdl_temp_reg_value_rdqsnd;
- unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
- unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_value_dqs;
- // unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
- // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
-
- unsigned int dq_lcd_bdl_temp_reg_lef;
- unsigned int dq_lcd_bdl_temp_reg_rig;
- unsigned int dq_lcd_bdl_temp_reg_center;
- unsigned int dq_lcd_bdl_temp_reg_windows;
- unsigned int dq_lcd_bdl_temp_reg_center_min;
- unsigned int dq_lcd_bdl_temp_reg_windows_min;
-
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
-
-
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
- else
- {
- goto usage;
- }
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
-
- }
- if (argc >4) {
- test_loop = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- {
- test_loop = 1;
- }
- if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
- {
- test_loop = 100000;
- }
- }
- if (argc >5) {
- training_pattern_flag = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- {
- training_pattern_flag = 0;
- }
- else if(training_pattern_flag)
- training_pattern_flag = 1;
-
-
- }
-
-
- printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
- printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
- printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
- printf("\ntest_loop== 0x%08x\n", test_loop);
- printf("\training_pattern_flag== 0x%08x\n", training_pattern_flag);
- if ( channel_a_en)
- {
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
- }
- if ( channel_b_en)
- {
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
- }
-
-
- //save and print org training dqs value
- if (channel_a_en || channel_b_en)
- {
-
-
- //dcache_disable();
- //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
-
- {
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
-
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
-
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
-
-
-
- for ((temp_count_j=0);(temp_count_j<DATX8_DQ_LCD_BDL_REG_WIDTH);(temp_count_j++))
- {
- dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=readl(reg_add+4*temp_count_j);
- dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
- printf("\n org add 0x%08x reg== 0x%08x\n",(reg_add+4*temp_count_j), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]));
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
- =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
- =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
-
- }
- }
-
- }
-
- }
-
- }////save and print org training dqs value
-
-
- for (test_times=0;(test_times<test_loop);(test_times++))
- {
- ////tune and save training dqs value
- if (channel_a_en || channel_b_en)
-
- {
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
-
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
-
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
- { printf("\ntest lane==0x%08x\n ",temp_count_i);
-
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
- }
-
- for ((temp_count_k=0);(temp_count_k<2);(temp_count_k++))
- {
-
- if (temp_count_k == 0)
- {
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- dq_lcd_bdl_temp_reg_value_dqs=(readl(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0));
- dq_lcd_bdl_temp_reg_value_wdqd=(readl(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0))&DQLCDLR_MAX;
- dq_lcd_bdl_temp_reg_value_rdqsd=(readl(reg_add+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0BDLR0))&DQLCDLR_MAX;
- // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
-#else
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
- // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
-#endif
-
- while (dq_lcd_bdl_temp_reg_value_wdqd>0)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_wdqd--;
- printf("\nwdqd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
-#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- writel(dq_lcd_bdl_temp_reg_value_wdqd,(reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0));
-#else
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
-#endif
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd left edge detect \n");
- dq_lcd_bdl_temp_reg_value_wdqd++;
- break;
- }
- }
- printf("\nwdqd left edge detect \n");
- printf("\nwdqd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_wdqd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_wdqd>(dq_lcd_bdl_temp_reg_lef_min_value&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_lef_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
- }
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
-
- while (dq_lcd_bdl_temp_reg_value_wdqd<0xff)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_wdqd++;
- printf("\nwdqd rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd right edge detect \n");
- dq_lcd_bdl_temp_reg_value_wdqd--;
- break;
- }
- }
- printf("\nwdqd right edge detect \n");
- printf("\nwdqd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_wdqd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
-
- dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
- dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_wdqd<(dq_lcd_bdl_temp_reg_rig_min_value&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_rig_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
- }
-
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
-
- }
- else if(temp_count_k==1)
- {
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
- while (dq_lcd_bdl_temp_reg_value_rdqsd>0)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_rdqsd--;
- printf("\nrdqsd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nrdqsd left edge detect \n");
- dq_lcd_bdl_temp_reg_value_rdqsd++;
- break;
- }
- }
- printf("\nrdqsd left edge detect \n");
- printf("\nrdqsd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
-
- dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_rdqsd>((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_lef_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
- }
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
- while (dq_lcd_bdl_temp_reg_value_rdqsd<0xff)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_rdqsd++;
- printf("\nrdqsd right temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nrdqsd right edge detect \n");
- dq_lcd_bdl_temp_reg_value_rdqsd--;
- break;
- }
- }
- printf("\nrdqsd right edge detect \n");
- printf("\nrdqsd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_rdqsd<((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_rig_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
- }
-
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
-
-
-
- }
-
- }
- }
-
- }
- }
-
- ////tune and save training dqs value
-
-
-
-
- ////calculate and print dqs value
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;
-
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- // dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
-
- printf("\n org add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- printf("\n lef add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- printf("\n rig add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- printf("\n ddrtest size ==0x%08x, test times==0x%08x,test_loop==0x%08x\n",ddr_test_size,(test_times+1),test_loop);
- printf("\n add 0x00000000 reg== org lef rig center win lef_m rig_m min_c min_win \n");
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
- {
-
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
- }
-
- dq_lcd_bdl_temp_reg_lef=(dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
- dq_lcd_bdl_temp_reg_rig=(dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
-
- if (test_times == 0)
- {
- (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_lef;
- (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_rig;
-
- }
- dq_lcd_bdl_temp_reg_lef_min_value=(dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
- dq_lcd_bdl_temp_reg_rig_min_value=(dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
-
-
- //dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value&0x0000ff);
- dq_lcd_bdl_temp_reg_center=( (((dq_lcd_bdl_temp_reg_lef&0xff)+(dq_lcd_bdl_temp_reg_rig&0xff))/2)
- |(((((dq_lcd_bdl_temp_reg_lef>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<8)
- |(((((dq_lcd_bdl_temp_reg_lef>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<16) );
-
- dq_lcd_bdl_temp_reg_windows=( (((dq_lcd_bdl_temp_reg_rig&0xff)-(dq_lcd_bdl_temp_reg_lef&0xff)))
- |(((((dq_lcd_bdl_temp_reg_rig>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<8)
- |(((((dq_lcd_bdl_temp_reg_rig>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<16) );
-
-
- dq_lcd_bdl_temp_reg_center_min=( (((dq_lcd_bdl_temp_reg_lef_min_value&0xff)+(dq_lcd_bdl_temp_reg_rig_min_value&0xff))/2)
- |(((((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<8)
- |(((((dq_lcd_bdl_temp_reg_lef_min_value>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<16) );
-
- dq_lcd_bdl_temp_reg_windows_min=( (((dq_lcd_bdl_temp_reg_rig_min_value&0xff)-(dq_lcd_bdl_temp_reg_lef_min_value&0xff)))
- |(((((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<8)
- |(((((dq_lcd_bdl_temp_reg_rig_min_value>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<16) );
-
- printf("\n add 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- (dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- dq_lcd_bdl_temp_reg_center,dq_lcd_bdl_temp_reg_windows,
- (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- dq_lcd_bdl_temp_reg_center_min,dq_lcd_bdl_temp_reg_windows_min
- );
- }
-
-
- }
-
- }
-
-
-
-
- return 0;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-
-}
-
-U_BOOT_CMD(
- ddr_tune_dqs, 6, 1, do_ddr_test_fine_tune_dqs,
- "DDR tune dqs function",
- "ddr_tune_dqs a 0 0x80000 3 or ddr_tune_dqs b 0 0x80000 5 or ddr_tune_dqs a b 0x80000 l\n dcache off ? \n"
-);
-
-
-
-int do_ddr_test_dqs_window_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter test ddr dqs window step function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- printf("\nargc== 0x%08x\n", argc);
-
- unsigned int temp_test_error= 0;
-
-
- char *endp;
- // unsigned int *p_start_addr;
- unsigned int test_lane_step=0;
- unsigned int testing_lane=0;
- unsigned int test_lane_step_rdqs_flag=0;
- unsigned int test_min_max_flag=0;
- unsigned int test_times=1;
- unsigned int reg_add=0;
- unsigned int reg_base_adj=0;
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
-
-
- unsigned int dq_lcd_bdl_reg_org=0;
- unsigned int dq_lcd_bdl_reg_left=0;
- unsigned int dq_lcd_bdl_reg_right=0;
-
-
- unsigned int dq_lcd_bdl_reg_left_min=0;
- unsigned int dq_lcd_bdl_reg_right_min=0;
-
- unsigned int dq_lcd_bdl_temp_reg_value=0;
-
-
- // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
-
-
- // unsigned int dq_lcd_bdl_temp_reg_lef;
- // unsigned int dq_lcd_bdl_temp_reg_rig;
-
-
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
-
-
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
- else
- {
- goto usage;
- }
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
-
- }
- if (argc >4) {
- test_lane_step = 0;
- test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- {
- test_lane_step = 0;
- }
- if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
- {
- test_lane_step = 0;
- }
- }
- if (test_lane_step >7)
- test_lane_step = 0;
- unsigned int test_loop=1;
- if (argc >5) {
-
- test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- {
- test_min_max_flag = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- unsigned int test_temp_value_use_sticky_register=0;
- if (argc >6) {
-
- test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
- if (*argv[6] == 0 || *endp != 0)
- {
- test_temp_value_use_sticky_register = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
-
- printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
- printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
- printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
- printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
- printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
- printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
-
- const char *temp_s;
- char *env_lcdlr_temp_count;
- char *buf;
- buf="";
- unsigned int lcdlr_temp_count=0;
- env_lcdlr_temp_count="lcdlr_temp_count";
-
- if(test_temp_value_use_sticky_register)
- {lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
- }
- else
- {
-
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- else
- {lcdlr_temp_count=0;
- }
- }
-
- if ( channel_a_en)
- {
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
- }
- if ( channel_b_en)
- {
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
- }
-
-
-
- //save and print org training dqs value
- if (channel_a_en || channel_b_en)
- {
- //dcache_disable();
- //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
-
- }////save and print org training dqs value
-
-
- for (test_times=0;(test_times<test_loop);(test_times++))
- {
- ////tune and save training dqs value
- if (channel_a_en || channel_b_en)
-
- {
-
- {
-
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
-
-
-
- {
- printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
- writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
- printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
- { printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
- writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
- printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
- }
- if (test_lane_step>8)
- test_lane_step=0;
- printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
-
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+(DDR0_PUB_DX1BDLR0-DDR0_PUB_DX0BDLR0)*(test_lane_step>>1);
- test_lane_step_rdqs_flag=test_lane_step%2;
- testing_lane=(test_lane_step>>1);
- if (!test_lane_step_rdqs_flag)
- {reg_add=reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0;
- }
- else
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- reg_add=reg_add+DDR0_PUB_DX0LCDLR1-DDR0_PUB_DX0BDLR0;
-#else
- reg_add=reg_add+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0BDLR0;
-#endif
-
- }
-
- dq_lcd_bdl_temp_reg_value=readl(reg_add);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- if (test_lane_step_rdqs_flag)
- {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0xff00)>>8);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
- else
- {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&0x00ff)>>0);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
-#endif
-
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
- {
- while (dq_lcd_bdl_temp_reg_value>0)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value--;
-
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
- }
-
-
-
- printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
- if (!test_lane_step_rdqs_flag)
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
-#else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
-#endif
- }
- else
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
-#else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
-#endif
- }
- printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
-
- if (temp_test_error)
- {
- //printf("\nwdqd left edge detect \n");
- dq_lcd_bdl_temp_reg_value++;
- break;
- }
- }
- printf("\n left edge detect \n");
- printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
-
- dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
- if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
- }
- } else
- {
- printf("\n left edge skip \n");
- }
-
- if (!test_lane_step_rdqs_flag)
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
-#else
- writel(dq_lcd_bdl_reg_org,reg_add);
-#endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- }
- else
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
-#else
- writel(dq_lcd_bdl_reg_org,reg_add);
- writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
-#endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
-
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
-
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
-
-
- if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
- {
- while (dq_lcd_bdl_temp_reg_value<DQLCDLR_MAX)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value++;
-
-
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
- }
-
- printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
- if (!test_lane_step_rdqs_flag)
- {
- //writel(dq_lcd_bdl_temp_reg_value,reg_add);
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<0)|(((readl(reg_add))&0xffff00)),reg_add);
-#else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
-#endif
- }
- else
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_temp_reg_value<<8)|(dq_lcd_bdl_temp_reg_value<<16)|(((readl(reg_add))&0xff)),reg_add);
-#else
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
-#endif
- // writel(dq_lcd_bdl_temp_reg_value,reg_add);
- // writel(dq_lcd_bdl_temp_reg_value,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
- printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd right edge detect \n");
- dq_lcd_bdl_temp_reg_value--;
- break;
- }
- }
- printf("\n right edge detect \n");
- printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
- dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
- if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
- }
- }
-
- if (!test_lane_step_rdqs_flag)
- {
- // writel(dq_lcd_bdl_reg_org,reg_add);
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<0)|(((readl(reg_add))&0xffff00)),reg_add);
-#else
- writel(dq_lcd_bdl_reg_org,reg_add);
-#endif
- }
- else
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- writel((dq_lcd_bdl_reg_org<<8)|(dq_lcd_bdl_reg_org<<16)|(((readl(reg_add))&0xff)),reg_add);
-#else
- writel(dq_lcd_bdl_reg_org,reg_add);
- writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
-#endif
- // writel(dq_lcd_bdl_reg_org,reg_add);
- // writel(dq_lcd_bdl_reg_org,reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3);
- }
-
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
- printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
- printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- }
-
-
-
- }
- }
-
- }
-
- dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
- if (!test_lane_step_rdqs_flag)
- {if(channel_a_en){
- dq_lcd_bdl_value_wdq_org_a[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_wdq_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_wdq_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- if (channel_b_en)
- {
- dq_lcd_bdl_value_wdq_org_b[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_wdq_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_wdq_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- }
- else
- {
- if (channel_a_en) {
- dq_lcd_bdl_value_rdqs_org_a[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_rdqs_min_a[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_rdqs_max_a[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- if (channel_b_en) {
- dq_lcd_bdl_value_rdqs_org_b[testing_lane]=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_rdqs_min_b[testing_lane]=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_rdqs_max_b[testing_lane]=dq_lcd_bdl_reg_right_min;
- }
- }
-
- return dq_lcd_bdl_temp_reg_value;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-
-}
-
-///*
-U_BOOT_CMD(
- ddr_tune_dqs_step, 7, 1, do_ddr_test_dqs_window_step,
- "ddr_tune_dqs_step function",
- "ddr_tune_dqs_step a 0 0x80000 3 or ddr_tune_dqs_step b 0 0x80000 5 \n dcache off ? \n"
-);
-
-
-
-extern int ddr_test_s_add_cross_talk_pattern(int ddr_test_size);
-
-
-int do_ddr_test_lcdlr_clk_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter test ddr lcdlr clk step function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- printf("\nargc== 0x%08x\n", argc);
-
- unsigned int temp_test_error= 0;
-
-
- char *endp;
- // unsigned int *p_start_addr;
- unsigned int test_lane_step=0;
- // unsigned int testing_lane=0;
- // unsigned int test_lane_step_rdqs_flag=0;
- unsigned int test_min_max_flag=0;
- unsigned int test_times=1;
- unsigned int reg_add=0;
- unsigned int reg_base_adj=0;
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
-
-
- unsigned int dq_lcd_bdl_reg_org=0;
- unsigned int dq_lcd_bdl_reg_left=0;
- unsigned int dq_lcd_bdl_reg_right=0;
-
-
- unsigned int dq_lcd_bdl_reg_left_min=0;
- unsigned int dq_lcd_bdl_reg_right_min=0;
-
- unsigned int dq_lcd_bdl_temp_reg_value=0;
-
-
- // unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
-
-
- // unsigned int dq_lcd_bdl_temp_reg_lef;
- // unsigned int dq_lcd_bdl_temp_reg_rig;
-
-
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
-
-
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
- else
- {
- goto usage;
- }
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
-
- }
- if (argc >4) {
- test_lane_step = 0;
- test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- {
- test_lane_step = 0;
- }
- if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
- {
- test_lane_step = 0;
- }
- }
- if (test_lane_step >7)
- test_lane_step = 0;
- unsigned int test_loop=1;
- if (argc >5) {
-
- test_min_max_flag = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- {
- test_min_max_flag = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- unsigned int test_temp_value_use_sticky_register=0;
- if (argc >6) {
-
- test_temp_value_use_sticky_register = simple_strtoull_ddr(argv[6], &endp, 16);
- if (*argv[6] == 0 || *endp != 0)
- {
- test_temp_value_use_sticky_register = 0;
- }
- else
- {
- //test_min_max_flag =1;
- }
- }
- sticky_reg_base_add=(DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
- printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
- printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
- printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
- printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
- printf("\ntest_min_max_flag== 0x%08x\n", test_min_max_flag);
- printf("\ntest_temp_value_use_sticky_register== 0x%08x\n", test_temp_value_use_sticky_register);
- const char *temp_s;
- char *env_lcdlr_temp_count;
- char *buf;
- buf="";
- unsigned int lcdlr_temp_count=0;
- env_lcdlr_temp_count="lcdlr_temp_count_a";
- unsigned int lcdlr_max=0;
- if(test_temp_value_use_sticky_register)
- {lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
- }
- else
- {
-
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- else
- {lcdlr_temp_count=0;
- }
- }
-
- if ( channel_a_en)
- {
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
- }
- if ( channel_b_en)
- {
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
- }
-
-
-
- //save and print org training dqs value
- if (channel_a_en || channel_b_en)
- {
- //dcache_disable();
- //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
-
- }////save and print org training dqs value
-
-
- for (test_times=0;(test_times<test_loop);(test_times++))
- {
- ////tune and save training dqs value
- if (channel_a_en || channel_b_en)
-
- {
-
- {
-
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
-
-
-
- {
- printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
- writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
- printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
- { printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
- writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
- printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
- }
- if (test_lane_step>2)
- test_lane_step=0;
- printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
- if(test_lane_step==0)
- {reg_add=DDR0_PUB_ACLCDLR+reg_base_adj;
- lcdlr_max=ACLCDLR_MAX;
- }
- if(test_lane_step==1)
- {reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
- lcdlr_max=ACBDLR_MAX;
- }
-
-
- dq_lcd_bdl_temp_reg_value=readl(reg_add);
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
-
- if(test_lane_step==0)
- {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACLCDLR_MAX));
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
- if(test_lane_step==1)
- {dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACBDLR_MAX));
- dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
- }
-
-
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
- {
- while (dq_lcd_bdl_temp_reg_value>0)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value--;
-
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- }
-
-
-
- printf("\n left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
- {
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- }
-
- printf("\n rmin read reg==0x%08x\n ",(readl(reg_add)));
- //temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- //#ifdef DDR_LCDLR_CK_USE_FAST_PATTERN
- temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
- // #else
- // temp_test_error= ddr_test_s_add_cross_talk_pattern(ddr_test_size);
- // temp_test_error= temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
- // #endif
-
-
- if (temp_test_error)
- {
- //printf("\nwdqd left edge detect \n");
- dq_lcd_bdl_temp_reg_value++;
- break;
- }
- }
- printf("\n left edge detect \n");
- printf("\nleft edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
-
- dq_lcd_bdl_reg_left=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left;
- if (dq_lcd_bdl_reg_left>dq_lcd_bdl_reg_left_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
- }
- }
- else
- {
- printf("\n left edge skip \n");
- }
-
-
- {
-
- writel(dq_lcd_bdl_reg_org,reg_add);
-
- }
-
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_org;
-
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
-
-
- if ((test_min_max_flag == 0)|| (test_min_max_flag == 1))
- {
- //if(test_lane_step==0)
- while (dq_lcd_bdl_temp_reg_value<lcdlr_max)
- {
- ddr_test_watchdog_clear();
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value++;
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
- {
- writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
- }
- else
- {
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
- }
-
- printf("\n rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
- {
- writel(dq_lcd_bdl_temp_reg_value,reg_add);
- }
-
- printf("\n r max read reg==0x%08x\n ",(readl(reg_add)));
- // temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- temp_test_error=ddr_test_s_add_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd right edge detect \n");
- dq_lcd_bdl_temp_reg_value--;
- break;
- }
- }
- printf("\n right edge detect \n");
- printf("\n right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value);
-
- dq_lcd_bdl_reg_right=dq_lcd_bdl_temp_reg_value;
- if (test_times == 0)
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right;
- if (dq_lcd_bdl_reg_right<dq_lcd_bdl_reg_right_min) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min=dq_lcd_bdl_reg_right ;
- }
- }
-
- {
- writel(dq_lcd_bdl_reg_org,reg_add);
- }
-
- printf("\n read reg==0x%08x\n ",(readl(reg_add)));
- printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
- printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- }
-
-
-
- }
- }
-
- }
-
- dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
-
- {if(channel_a_en){
- if(test_lane_step==0)
- {
- dq_lcd_bdl_value_aclcdlr_org_a=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_aclcdlr_min_a=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_aclcdlr_max_a=dq_lcd_bdl_reg_right_min;
- }
- if(test_lane_step==1)
- {
- dq_lcd_bdl_value_bdlr0_org_a=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_bdlr0_min_a=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_bdlr0_max_a=dq_lcd_bdl_reg_right_min;
- }
- }
- if (channel_b_en)
- {
- if(test_lane_step==0)
- {
- dq_lcd_bdl_value_aclcdlr_org_b=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_aclcdlr_min_b=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_aclcdlr_max_b=dq_lcd_bdl_reg_right_min;
- }
- if(test_lane_step==1)
- {
- dq_lcd_bdl_value_bdlr0_org_b=dq_lcd_bdl_reg_org;
- if (test_min_max_flag != 1)
- dq_lcd_bdl_value_bdlr0_min_b=dq_lcd_bdl_reg_left_min;
- if (test_min_max_flag != 2)
- dq_lcd_bdl_value_bdlr0_max_b=dq_lcd_bdl_reg_right_min;
- }
- }
- }
-
-
-
- return dq_lcd_bdl_temp_reg_value;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-
-}
-
-U_BOOT_CMD(
- ddr_tune_aclcdlr_step, 7, 1, do_ddr_test_lcdlr_clk_step,
- "ddr_tune_aclcdlr_step function",
- "ddr_tune_aclcdlr_step a 0 0x80000 3 or ddr_tune_aclcdlr_step b 0 0x80000 5 \n dcache off ? \n"
-);
-
-int do_ddr_test_dqs_window(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnterddr_test_dqs_window function\n");
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
- // unsigned int reg_add=0;
- // unsigned int reg_base_adj=0;
-
- unsigned int lane_step= 0;
- unsigned int reg_value= 0;
- //int argc2;
- //char * argv2[30];
- char *endp;
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
-
-
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
- }
- //argc2=5;
- //for(i = 1;i<(argc);i++)
- {
- //argv2[i-1]=argv[i];
- }
-
- //argv2[0]=argv[1];
- //argv2[1]=argv[2];
- //argv2[2]=argv[3];
- //#include <stdio.h>
- // unsigned int wr_adj_per[24] ;
- if(1)
- {
- printf("\ntest use uboot env\n");
- {
- //char str[24];
- const char *s;
- unsigned int str_to_numarry[48];
- //str_buf = (char *)malloc(sizeof(char)*1024);
-
- unsigned int *num_arry;
- num_arry = (unsigned int *)(&str_to_numarry);
- int i;
- // char *varname;
- // int value=0;
-
- ///varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
- if (s)
- {//i=0;
- //while(s_temp)
- {
- env_to_num("env_wr_lcdlr_pr",num_arry);//unsigned int *num_arry
-
-
- for (i = 0; i < 48; i++) {
-
- printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
- }
- // printf("%s,lenth=%d",s,(strlen(s)));
- //sscanf(s,"d%,",wr_adj_per);
- //sprintf(str,"d%",s);
- //getc
- // if (strlen(s) > 16)
- {
- // sscanf(s, "%08x, %08x, %08x, \n",
- // &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
- }
- }
- }
- }
- }
- // unsigned int = 0, max = 0xff, min = 0x00;
- /*
- if(0)
- {
- {printf("\ntest use uboot env\n");
- {
- //char str[24];
- const char *s;
-
- // char *varname;
- int value=0;
-
- ///varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
- if (s)
- {//i=0;
- //while(s_temp)
- {
- printf("%s",s);
- //sscanf(s,"d%,",wr_adj_per);
- //sprintf(str,"d%",s);
- //getc
- if (strlen(s) > 16) {
- sscanf(s, "%08x, %08x, %08x, %08x, %08x\n",
- &wr_adj_per[i-2], &max, &min, &type_h, &type_l);
- } else {
- sscanf(buf, "%08x, %08x, %08x\n",
- &reg, &max, &min);
- }
-
- }
- value = simple_strtoull_ddr(s, &endp, 16);
- printf("%d",value);
- }
- s = getenv("env_rd_lcdlr_pr");
-
- if (s)
- {//i=0;
- //while(s_temp)
- {
- printf("%s",s);
- //sscanf(s,"d%,",rd_adj_per);
-
- }
- //value = simple_strtoull_ddr(s, &endp, 16);
- }
-
- //sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
-
-
- //run_command("save",0);
- }
-
- if (argc>24+2)
- argc=24+2;
- for(i = 2;i<argc;i++)
- {
- if(i<(2+12)){
- wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
- }
- else
- {
- rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
- }
- }
-
-
- }
- printf(" int wr_adj_per[12]={\n");
- for(i = 0;i<12;i++)
- {
- printf("%04d ,\n",wr_adj_per[i]);
-}
-printf("};\n");
-printf(" int rd_adj_per[12]={\n");
-for(i = 0;i<12;i++)
-{
- printf("%04d ,\n",rd_adj_per[i]);
-}
-printf("};\n");
-
-}
-*/
-
-char str[100];
-
-if (channel_a_en)
-{
-
- //*(char *)(argv2[0])="a";
- // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
- printf("\ntest dqs window lane a\n");
- for ((lane_step=0);(lane_step<8);(lane_step++))
- {
- //sprintf(argv2[3],"d%",( lane_step));
- //itoa_ddr_test(lane_step,(argv2[3]),10);
- //printf("\nargv2[%d]=%s\n",0,argv2[0]);
- // printf("\nargv2[%d]=%s\n",3,argv2[3]);
- // reg_value=do_ddr_test_dqs_window_step((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d",ddr_test_size,( lane_step));
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- run_command(str,0);
-
- }
-}
-
-
-if (channel_b_en)
-{//*(char *)(argv2[0])="b";
- // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
- printf("\ntest dqs window lane b\n");
- for ((lane_step=0);(lane_step<8);(lane_step++))
- {
- //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- sprintf(str,"ddr_tune_dqs_step b 0 0x%08x %d",ddr_test_size,( lane_step));
- printf("\nstr=%s\n",str);
- run_command(str,0);
-
- }
-}
-
-if (channel_a_en)
-{
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {
- printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
- lane_step,
- dq_lcd_bdl_value_wdq_org_a[lane_step],
- dq_lcd_bdl_value_wdq_min_a[lane_step],dq_lcd_bdl_value_wdq_max_a[lane_step],
- dq_lcd_bdl_value_rdqs_org_a[lane_step],
- dq_lcd_bdl_value_rdqs_min_a[lane_step],dq_lcd_bdl_value_rdqs_max_a[lane_step]);
- }}
-if (channel_b_en)
-{
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {
- printf("\n b_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
- lane_step,
- dq_lcd_bdl_value_wdq_org_b[lane_step],
- dq_lcd_bdl_value_wdq_min_b[lane_step],dq_lcd_bdl_value_wdq_max_b[lane_step],
- dq_lcd_bdl_value_rdqs_org_b[lane_step],
- dq_lcd_bdl_value_rdqs_min_b[lane_step],dq_lcd_bdl_value_rdqs_max_b[lane_step]);
- }}
-
-return reg_value;
-}
-
-/*
-U_BOOT_CMD(
- ddr_tune_dqs_step, 5, 1, do_ddr_test_fine_tune_dqs_step,
- "ddr_tune_dqs_step function",
- "ddr_tune_dqs_step a 0 0x800000 3 or ddr_tune_dqs_step b 0 0x800000 5 or ddr_tune_dqs_step a b 0x800000 l\n dcache off ? \n"
-);
-*/
-
-int do_ddr_test_fine_tune_dqs_step(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnter Tune ddr dqs step function\n");
- // if(!argc)
- // goto DDR_TUNE_DQS_START;
- printf("\nargc== 0x%08x\n", argc);
- // unsigned int loop = 1;
- unsigned int temp_count_i = 1;
- unsigned int temp_count_j= 1;
- unsigned int temp_count_k= 1;
- unsigned int temp_test_error= 0;
-
-
- char *endp;
- // unsigned int *p_start_addr;
- unsigned int test_lane_step=0;
- unsigned int test_lane_step_rdqs_flag=0;
- unsigned int test_loop=1;
- unsigned int test_times=1;
- unsigned int reg_add=0;
- unsigned int reg_base_adj=0;
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
- unsigned int testing_channel = 0;
-
-#define DATX8_DQ_LCD_BDL_REG_WIDTH 12
-
-#define DATX8_DQ_LANE_WIDTH 4
-#define CHANNEL_CHANNEL_WIDTH 2
-
-#define CHANNEL_A 0
-#define CHANNEL_B 1
-
-
-
-#define DATX8_DQ_LANE_LANE00 0
-#define DATX8_DQ_LANE_LANE01 1
-#define DATX8_DQ_LANE_LANE02 2
-#define DATX8_DQ_LANE_LANE03 3
-
-#define DATX8_DQ_BDLR0 0
-#define DATX8_DQ_BDLR1 1
-#define DATX8_DQ_BDLR2 2
-#define DATX8_DQ_BDLR3 3
-#define DATX8_DQ_BDLR4 4
-#define DATX8_DQ_BDLR5 5
-#define DATX8_DQ_BDLR6 6
-#define DATX8_DQ_DXNLCDLR0 7
-#define DATX8_DQ_DXNLCDLR1 8
-#define DATX8_DQ_DXNLCDLR2 9
-#define DATX8_DQ_DXNMDLR 10
-#define DATX8_DQ_DXNGTR 11
-
-
-#define DDR_CORSS_TALK_TEST_SIZE 0x20000
-
-#define DQ_LCD_BDL_REG_NUM_PER_CHANNEL DATX8_DQ_LCD_BDL_REG_WIDTH*DATX8_DQ_LANE_WIDTH
-#define DQ_LCD_BDL_REG_NUM DQ_LCD_BDL_REG_NUM_PER_CHANNEL*CHANNEL_CHANNEL_WIDTH
-
- unsigned int dq_lcd_bdl_reg_org[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_left[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_right[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_index[DQ_LCD_BDL_REG_NUM];
-
- unsigned int dq_lcd_bdl_reg_left_min[DQ_LCD_BDL_REG_NUM];
- unsigned int dq_lcd_bdl_reg_right_min[DQ_LCD_BDL_REG_NUM];
-
- unsigned int dq_lcd_bdl_temp_reg_value;
- unsigned int dq_lcd_bdl_temp_reg_value_dqs;
- unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
- unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
- // unsigned int dq_lcd_bdl_temp_reg_value_rdqsnd;
- unsigned int dq_lcd_bdl_temp_reg_lef_min_value;
- unsigned int dq_lcd_bdl_temp_reg_rig_min_value;
- // unsigned int dq_lcd_bdl_temp_reg_value_dqs;
- // unsigned int dq_lcd_bdl_temp_reg_value_wdqd;
- // unsigned int dq_lcd_bdl_temp_reg_value_rdqsd;
-
- unsigned int dq_lcd_bdl_temp_reg_lef;
- unsigned int dq_lcd_bdl_temp_reg_rig;
- unsigned int dq_lcd_bdl_temp_reg_center;
- unsigned int dq_lcd_bdl_temp_reg_windows;
- unsigned int dq_lcd_bdl_temp_reg_center_min;
- unsigned int dq_lcd_bdl_temp_reg_windows_min;
-
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
-
-
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
- else
- {
- goto usage;
- }
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
-
- }
- if (argc >4) {
- test_lane_step = 0;
- test_lane_step = simple_strtoull_ddr(argv[4], &endp, 16);
- if (*argv[4] == 0 || *endp != 0)
- {
- test_lane_step = 0;
- }
- if ((strcmp(argv[4], "l") == 0) || (strcmp(argv[4], "L") == 0))
- {
- test_lane_step = 0;
- }
- }
- test_loop=1;
-
- unsigned int test_min_max=0;
- if (argc >5) {
-
- test_min_max = simple_strtoull_ddr(argv[5], &endp, 16);
- if (*argv[5] == 0 || *endp != 0)
- {
- test_min_max = 0;
- }
- else
- test_min_max=1;
-
- }
-
- printf("\nchannel_a_en== 0x%08x\n", channel_a_en);
- printf("\nchannel_b_en== 0x%08x\n", channel_b_en);
- printf("\nddr_test_size== 0x%08x\n", ddr_test_size);
- printf("\ntest_lane_step== 0x%08x\n", test_lane_step);
- printf("\ntest_loop== 0x%08x\n", test_loop);
- printf("\ntest_min_max== 0x%08x\n", test_min_max);
- if ( channel_a_en)
- {
- //writel((0), 0xc8836c00);
- OPEN_CHANNEL_A_PHY_CLK();
- }
- if ( channel_b_en)
- {
- OPEN_CHANNEL_B_PHY_CLK();
- //writel((0), 0xc8836c00);
- }
-
-
-
- //save and print org training dqs value
- if (channel_a_en || channel_b_en)
- {
-
-
- //dcache_disable();
- //serial_puts("\ndebug for ddrtest ,jiaxing disable dcache");
-
- {
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
-
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
-
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
-
-
-
- for ((temp_count_j=0);(temp_count_j<DATX8_DQ_LCD_BDL_REG_WIDTH);(temp_count_j++))
- {
- dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=readl(reg_add+4*temp_count_j);
- dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
- printf("\n org add 0x%08x reg== 0x%08x\n",(reg_add+4*temp_count_j), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]));
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
- =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]
- =dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j];
-
- }
- }
-
- }
-
- }
-
- }////save and print org training dqs value
-
-
- for (test_times=0;(test_times<test_loop);(test_times++))
- {
- ////tune and save training dqs value
- if (channel_a_en || channel_b_en)
-
- {
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
-
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
-
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
- if (test_lane_step>8)
- test_lane_step=0;
- if (test_lane_step)
- {
- printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
- temp_count_i=(test_lane_step>>1);
- test_lane_step_rdqs_flag=test_lane_step-(temp_count_i<<1);
- test_lane_step=0;
- }
- {
- printf("\ntest lane==0x%08x\n ",temp_count_i);
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj;}
- }
-
- for ((temp_count_k=0);(temp_count_k<2);(temp_count_k++))
- {
- if (test_lane_step_rdqs_flag)
- {
- temp_count_k=1;
- test_lane_step_rdqs_flag=0;
- }
- if (temp_count_k == 0)
- {
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
- // dq_lcd_bdl_temp_reg_value_rdqsnd=((dq_lcd_bdl_temp_reg_value_dqs&0xff0000))>>16;
-
- while (dq_lcd_bdl_temp_reg_value_wdqd>0)
- {
- if(test_min_max)
- {break;
- }
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_wdqd--;
- printf("\nwdqd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
-
- if (temp_test_error)
- {
- //printf("\nwdqd left edge detect \n");
- dq_lcd_bdl_temp_reg_value_wdqd++;
- break;
- }
- }
- printf("\nwdqd left edge detect \n");
- printf("\nwdqd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_wdqd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_wdqd>(dq_lcd_bdl_temp_reg_lef_min_value&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_lef_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
- }
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
-
- while (dq_lcd_bdl_temp_reg_value_wdqd<0xff)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_wdqd++;
- printf("\nwdqd rig temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nwdqd right edge detect \n");
- dq_lcd_bdl_temp_reg_value_wdqd--;
- break;
- }
- }
- printf("\nwdqd right edge detect \n");
- printf("\nwdqd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_wdqd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_wdqd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x00)|dq_lcd_bdl_temp_reg_value_wdqd);
-
- dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
- dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_wdqd<(dq_lcd_bdl_temp_reg_rig_min_value&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_rig_min_value&0xffff00)|dq_lcd_bdl_temp_reg_value_wdqd) ;
- }
-
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
-
- }
- else if(temp_count_k==1)
- {
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
- while (dq_lcd_bdl_temp_reg_value_rdqsd>0)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_rdqsd--;
- printf("\nrdqsd left temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nrdqsd left edge detect \n");
- dq_lcd_bdl_temp_reg_value_rdqsd++;
- break;
- }
- }
- printf("\nrdqsd left edge detect \n");
- printf("\nrdqsd left edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
-
- dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_lef_min_value=dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_rdqsd>((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_lef_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
- }
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
- dq_lcd_bdl_temp_reg_value_dqs=readl(reg_add+4*DATX8_DQ_DXNLCDLR1);
- dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value_dqs&0xff);
- dq_lcd_bdl_temp_reg_value_rdqsd=((dq_lcd_bdl_temp_reg_value_dqs&0xff00))>>8;
-
- while (dq_lcd_bdl_temp_reg_value_rdqsd<0xff)
- {
- temp_test_error=0;
- dq_lcd_bdl_temp_reg_value_rdqsd++;
- printf("\nrdqsd right temp==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- writel(dq_lcd_bdl_temp_reg_value_dqs,(reg_add+4*DATX8_DQ_DXNLCDLR1));
- temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if (temp_test_error)
- {
- //printf("\nrdqsd right edge detect \n");
- dq_lcd_bdl_temp_reg_value_rdqsd--;
- break;
- }
- }
- printf("\nrdqsd right edge detect \n");
- printf("\nrdqsd right edge==0x%08x\n ",dq_lcd_bdl_temp_reg_value_rdqsd);
- dq_lcd_bdl_temp_reg_value_dqs=(dq_lcd_bdl_temp_reg_value_wdqd|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- //only update dq_lcd_bdl_temp_reg_value_rdqsd rdqsnd
- dq_lcd_bdl_temp_reg_value=dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- dq_lcd_bdl_temp_reg_value_dqs=((dq_lcd_bdl_temp_reg_value&0x0000ff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16));
- dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]=dq_lcd_bdl_temp_reg_value_dqs;
-
-
- dq_lcd_bdl_temp_reg_rig_min_value=dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1];
- if (dq_lcd_bdl_temp_reg_value_rdqsd<((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)) //update wdqd min value
- {
- dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]
- =((dq_lcd_bdl_temp_reg_rig_min_value&0xff)|(dq_lcd_bdl_temp_reg_value_rdqsd<<8)|(dq_lcd_bdl_temp_reg_value_rdqsd<<16)) ;
- }
-
-
-
- writel(dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1],(reg_add+4*DATX8_DQ_DXNLCDLR1));
-
-
-
-
- }
-
- }
- }
-
- }
- }
-
- ////tune and save training dqs value
-
-
-
-
- ////calculate and print dqs value
- for ((testing_channel=0);(testing_channel<(channel_a_en+channel_b_en));(testing_channel++))
- {
- if (( channel_a_en) && ( channel_b_en == 0))
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if(( channel_b_en)&&( channel_a_en==0))
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- else if ((channel_a_en+channel_b_en)==2)
- {
- if ( testing_channel == CHANNEL_A)
- {
- reg_base_adj=CHANNEL_A_REG_BASE;
- }
- else if( testing_channel==CHANNEL_B)
- {
- reg_base_adj=CHANNEL_B_REG_BASE;
- }
- }
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj;
-
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- // dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+temp_count_j]=reg_add+4*temp_count_j;
-
- printf("\n org add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- printf("\n lef add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- for ((temp_count_j=0);(temp_count_j<DQ_LCD_BDL_REG_NUM_PER_CHANNEL);(temp_count_j++))
- {
- printf("\n rig add 0x%08x reg== 0x%08x\n",(dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]), (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_j]));
- }
-
- printf("\n ddrtest size ==0x%08x, test times==0x%08x,test_loop==0x%08x\n",ddr_test_size,(test_times+1),test_loop);
- printf("\n add 0x00000000 reg== org lef rig center win lef_m rig_m min_c min_win \n");
- for ((temp_count_i=0);(temp_count_i<DATX8_DQ_LANE_WIDTH);(temp_count_i++))
- {
- {
-
- if (temp_count_i == DATX8_DQ_LANE_LANE00)
- {
- reg_add=DDR0_PUB_DX0BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE01)
- {
- reg_add=DDR0_PUB_DX1BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
-
- else if(temp_count_i==DATX8_DQ_LANE_LANE02)
- {
- reg_add=DDR0_PUB_DX2BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
- else if(temp_count_i==DATX8_DQ_LANE_LANE03)
- {
- reg_add=DDR0_PUB_DX3BDLR0+reg_base_adj+DATX8_DQ_DXNLCDLR1*4;}
- }
-
- dq_lcd_bdl_temp_reg_lef=(dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
- dq_lcd_bdl_temp_reg_rig=(dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
-
- if (test_times == 0)
- {
- (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_lef;
- (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1])=dq_lcd_bdl_temp_reg_rig;
-
- }
- dq_lcd_bdl_temp_reg_lef_min_value=(dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
- dq_lcd_bdl_temp_reg_rig_min_value=(dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]);
-
-
- //dq_lcd_bdl_temp_reg_value_wdqd=(dq_lcd_bdl_temp_reg_value&0x0000ff);
- dq_lcd_bdl_temp_reg_center=( (((dq_lcd_bdl_temp_reg_lef&0xff)+(dq_lcd_bdl_temp_reg_rig&0xff))/2)
- |(((((dq_lcd_bdl_temp_reg_lef>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<8)
- |(((((dq_lcd_bdl_temp_reg_lef>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig>>8)&0xff))/2)<<16) );
-
- dq_lcd_bdl_temp_reg_windows=( (((dq_lcd_bdl_temp_reg_rig&0xff)-(dq_lcd_bdl_temp_reg_lef&0xff)))
- |(((((dq_lcd_bdl_temp_reg_rig>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<8)
- |(((((dq_lcd_bdl_temp_reg_rig>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef>>8)&0xff)))<<16) );
-
-
- dq_lcd_bdl_temp_reg_center_min=( (((dq_lcd_bdl_temp_reg_lef_min_value&0xff)+(dq_lcd_bdl_temp_reg_rig_min_value&0xff))/2)
- |(((((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<8)
- |(((((dq_lcd_bdl_temp_reg_lef_min_value>>16)&0xff)+((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff))/2)<<16) );
-
- dq_lcd_bdl_temp_reg_windows_min=( (((dq_lcd_bdl_temp_reg_rig_min_value&0xff)-(dq_lcd_bdl_temp_reg_lef_min_value&0xff)))
- |(((((dq_lcd_bdl_temp_reg_rig_min_value>>8)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<8)
- |(((((dq_lcd_bdl_temp_reg_rig_min_value>>16)&0xff)-((dq_lcd_bdl_temp_reg_lef_min_value>>8)&0xff)))<<16) );
-
- printf("\n add 0x%08x reg== 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- (dq_lcd_bdl_reg_index[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_org[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_left[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_right[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- dq_lcd_bdl_temp_reg_center,dq_lcd_bdl_temp_reg_windows,
- (dq_lcd_bdl_reg_left_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- (dq_lcd_bdl_reg_right_min[testing_channel*DQ_LCD_BDL_REG_NUM_PER_CHANNEL+temp_count_i*DATX8_DQ_LCD_BDL_REG_WIDTH+DATX8_DQ_DXNLCDLR1]),
- dq_lcd_bdl_temp_reg_center_min,dq_lcd_bdl_temp_reg_windows_min
- );
- }
-
-
- }
-
- }
-
-
-
-
-
- return 0;
-
-usage:
- cmd_usage(cmdtp);
- return 1;
-
-}
-
-
-
-int do_ddr_test_dqs_window_env(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- printf("\nEnterddr_test_dqs_window function\n");
- printf("\nddr_test_cmd 0x22 a 0 0x80000 ns lane_disable add_test_size --- watchdog should >15s\n");
- unsigned int channel_a_en = 0;
- unsigned int channel_b_en = 0;
- // unsigned int reg_add=0;
- // unsigned int reg_base_adj=0;
-
- unsigned int lane_step= 0;
- unsigned int reg_value= 0;
- //int argc2;
- //char * argv2[30];
- char *endp;
- char *buf;
- buf="";
-
- if (argc == 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0))
-
- {channel_a_en = 1;
- }
- else if ((strcmp(argv[1], "b") == 0)||(strcmp(argv[1], "B") == 0))
-
- {channel_b_en = 1;
- }
-
-
- }
- if (argc > 2)
- {
- if ((strcmp(argv[1], "a") == 0) || (strcmp(argv[1], "A") == 0) || (strcmp(argv[2], "a") == 0) || (strcmp(argv[2], "A") == 0))
-
- {channel_a_en = 1;
- }
- if ((strcmp(argv[1], "b") == 0) || (strcmp(argv[1], "B") == 0) || (strcmp(argv[2], "b") == 0) || (strcmp(argv[2], "B") == 0))
-
- {channel_b_en = 1;
- }
- }
- unsigned int ddr_test_size= DDR_CORSS_TALK_TEST_SIZE;
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- if (argc >3) {
- ddr_test_size = simple_strtoull_ddr(argv[3], &endp, 16);
- if (*argv[3] == 0 || *endp != 0)
- {
- ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
- }
-
-
-
- if (argc >4) {
- watchdog_time_s = simple_strtoull_ddr(argv[4], &endp, 0);
- if (*argv[4] == 0 || *endp != 0)
- {
- watchdog_time_s= 20;
- }
- }
- printf("watchdog_time_s==%d\n",watchdog_time_s);
-
- unsigned int lane_disable= 0;
-
- if (argc >5) {
- lane_disable = simple_strtoull_ddr(argv[5], &endp, 0);
- if (*argv[5] == 0 || *endp != 0)
- {
- lane_disable= 0;
- }
- }
- printf("lane_disable==0x%08x\n",lane_disable);
-
- unsigned int add_test_size= DDR_CORSS_TALK_TEST_SIZE;
-
- if (argc >6) {
- add_test_size = simple_strtoull_ddr(argv[6], &endp, 0);
- if (*argv[6] == 0 || *endp != 0)
- {
- add_test_size= ddr_test_size;
- }
- }
- printf("add_test_size==0x%08x\n",add_test_size);
- //argc2=5;
- //for(i = 1;i<(argc);i++)
- {
- //argv2[i-1]=argv[i];
- }
-
- //argv2[0]=argv[1];
- //argv2[1]=argv[2];
- //argv2[2]=argv[3];
- //#include <stdio.h>
- // unsigned int wr_adj_per[24] ;
- //if(1)
-
- printf("\ntest use uboot env\n");
-
- char str[1024]="";
- char str_temp1[1024]="";
- char str_temp2[1024]="";
- const char *s;
- unsigned int str_to_numarry[48];
- //str_buf = (char *)malloc(sizeof(char)*1024);
-
- unsigned int *num_arry;
- //unsigned int *num_arry_temp;
- unsigned int *num_arry_lane0=NULL;
- unsigned int *num_arry_lane1=NULL;
- unsigned int *num_arry_lane2=NULL;
- unsigned int *num_arry_lane3=NULL;
- char *name_lane0;
- char *name_lane1;
- char *name_lane2;
- char *name_lane3;
- num_arry = (unsigned int *)(&str_to_numarry);
- int i;
- char *varname; char *env_lcdlr_temp_count;
- unsigned int lcdlr_temp_count=0;
- const char *temp_s;const char *temp_s1;
- // int value=0;
-
- varname="env_ddrtest_data_lane";
- name_lane0="ddr_test_data_lane0";
- name_lane1="ddr_test_data_lane1";
- name_lane2="ddr_test_data_lane2";
- name_lane3="ddr_test_data_lane3";
- env_lcdlr_temp_count="lcdlr_temp_count";
- s = getenv(varname);
- if (s)
- {//i=0;
- //while(s_temp)
- {
- env_to_num(varname,num_arry);//unsigned int *num_arry
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- else
- {lcdlr_temp_count=0;
- }
-
- if(0){
- env_to_num(name_lane0,num_arry_lane0);//unsigned int *num_arry
- env_to_num(name_lane1,num_arry_lane1);//unsigned int *num_arry
- env_to_num(name_lane2,num_arry_lane2);//unsigned int *num_arry
- env_to_num(name_lane3,num_arry_lane3);//unsigned int *num_arry
- }
-
- for (i = 0; i < 48; i++) {
-
- printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
- }
- //for (lane_step = 0;lane_step< 4;lane_step++)
- if(0)
- {
- for (i = 0; i < 8; i++) {
-
- printf("lane_0 str_to_numarry[%d]==%d\n",i,num_arry_lane0[i]);
- }
- for (i = 0; i < 8; i++) {
-
- printf("lane_1 str_to_numarry[%d]==%d\n",i,num_arry_lane1[i]);
- }
- for (i = 0; i < 8; i++) {
-
- printf("lane_2 str_to_numarry[%d]==%d\n",i,num_arry_lane2[i]);
- }
- for (i = 0; i < 8; i++) {
-
- printf("lane_3 str_to_numarry[%d]==%d\n",i,num_arry_lane3[i]);
- }
- }
- // printf("%s,lenth=%d",s,(strlen(s)));
- //sscanf(s,"d%,",wr_adj_per);
- //sprintf(str,"d%",s);
- //getc
- // if (strlen(s) > 16)
- {
- // sscanf(s, "%08x, %08x, %08x, \n",
- // &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
- }
- }
- }
- else
- {
- printf("no env set,exit\n");
- return 0;}
- s = getenv(varname);//for debug display env should add
-
-
- ///*
- //if(1)
-
- unsigned int test_arg_0_cmd0 =0; //master cmd
- unsigned int test_arg_1_cmd1 =0; //min cmd
- unsigned int test_arg_2_step =0; //step 0 init -1 lane0 w min -2 lane0 w max -3 lane0 r min 4 lane0 r max -----5 lane1 w min ...
- unsigned int test_arg_3_freq =0;
- unsigned int test_arg_4_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
- // unsigned int lane_step= 0;
- //char str[24];
-
-
- test_arg_0_cmd0=num_arry[0];
- test_arg_1_cmd1=num_arry[1];
- test_arg_2_step=num_arry[2];
- test_arg_3_freq=num_arry[3];
- test_arg_4_step_status=num_arry[4];
- printf("test_arg_0_cmd0==%d\n",test_arg_0_cmd0);
- printf("test_arg_0_cmd1==%d\n",test_arg_1_cmd1);
- printf("test_arg_2_step==%d\n",test_arg_2_step);
- printf("test_arg_3_freq==%d\n",test_arg_3_freq);
- printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
-
- if(test_arg_2_step)
- {
- if(test_arg_3_freq!=global_ddr_clk)
- {
- printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
- sprintf(str,"d2pll %d",test_arg_3_freq);
- printf("\nstr=%s\n",str);
- run_command(str,0);
- while(1);
- }
- }
- if(test_arg_2_step==0)
- {
- {
- test_arg_0_cmd0=0x22;
- test_arg_1_cmd1=0;
- test_arg_2_step=1;
- test_arg_3_freq=global_ddr_clk;
- test_arg_4_step_status=0;
- num_arry[0]=test_arg_0_cmd0;
- num_arry[1]=test_arg_1_cmd1;
- num_arry[2]=test_arg_2_step;
- num_arry[3]=test_arg_3_freq;
- num_arry[4]=test_arg_4_step_status;
- num_arry[5]=0;
- num_arry[6]=0;
- num_arry[7]=0;
- for (i = 8; i < 48; i++) {
- num_arry[i]=0;
- }
-
- for (lane_step = 0; lane_step < 4; lane_step++)
- {
- //if(lane_step%2)
- {
-#if ( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
- DDR0_PUB_DX0LCDLR1)
- +DDR0_PUB_DX0LCDLR1))&0xff);
- dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
- DDR0_PUB_DX0LCDLR1)
- +DDR0_PUB_DX0LCDLR1))>>8)&0xff);
-#else
- dq_lcd_bdl_value_wdq_org_a[lane_step]=((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
- DDR0_PUB_DX0LCDLR1)
- +DDR0_PUB_DX0LCDLR1))&0x1ff);
- dq_lcd_bdl_value_rdqs_org_a[lane_step]=(((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
- DDR0_PUB_DX0LCDLR3)
- +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff);
-
- printf("lcdlr1 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
- DDR0_PUB_DX0LCDLR1)
- +DDR0_PUB_DX0LCDLR1),
- ((readl((lane_step)*(DDR0_PUB_DX1LCDLR1-
- DDR0_PUB_DX0LCDLR1)
- +DDR0_PUB_DX0LCDLR1))&0x1ff),dq_lcd_bdl_value_wdq_org_a[lane_step]);
- printf("lcdlr3 %d %08x,%08x,%08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
- DDR0_PUB_DX0LCDLR3)
- +DDR0_PUB_DX0LCDLR3),
- (((readl((lane_step)*(DDR0_PUB_DX1LCDLR3-
- DDR0_PUB_DX0LCDLR3)
- +DDR0_PUB_DX0LCDLR3))>>0)&0x1ff),dq_lcd_bdl_value_rdqs_org_a[lane_step]);
-#endif
-
- //printf("lcdlr1 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR1-
- //DDR0_PUB_DX0LCDLR1)
- //+DDR0_PUB_DX0LCDLR1));
- //printf("lcdlr3 %d %08x\n", lane_step,((lane_step)*(DDR0_PUB_DX1LCDLR3-
- //DDR0_PUB_DX0LCDLR3)
- //+DDR0_PUB_DX0LCDLR3));
- //dq_lcd_bdl_value_rdqs_org_a[lane_step]=0;
- dq_lcd_bdl_value_rdqs_min_a[lane_step]=0xffff;
- dq_lcd_bdl_value_rdqs_max_a[lane_step]=0xffff;
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
- }
- //else
- {
- //dq_lcd_bdl_value_wdq_org_a[lane_step]=0;
- dq_lcd_bdl_value_wdq_min_a[lane_step]=0xffff;
- dq_lcd_bdl_value_wdq_max_a[lane_step]=0xffff;
- dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
- }
- }
-
- {
- dq_lcd_bdl_value_aclcdlr_org_a=((readl(DDR0_PUB_ACLCDLR))&ACLCDLR_MAX);
- dq_lcd_bdl_value_aclcdlr_min_a=0xffff;
- dq_lcd_bdl_value_aclcdlr_max_a=0xffff;
- dq_lcd_bdl_value_aclcdlr_status_a=0;
- dq_lcd_bdl_value_bdlr0_org_a=((readl(DDR0_PUB_ACBDLR0))&ACBDLR_MAX);
- dq_lcd_bdl_value_bdlr0_min_a=0xffff;
- dq_lcd_bdl_value_bdlr0_max_a=0xffff;
- dq_lcd_bdl_value_bdlr0_status_a=0;
- }
-
-
-
-#if 1 //( CONFIG_DDR_PHY<P_DDR_PHY_905X)
- printf("DDR0_PUB_DX0GCR0==%x\n",(readl(DDR0_PUB_DX0GCR0)));
- printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
- printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
- printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
-
-#endif
- if(lane_disable)
- {if(lane_disable&0x1){
- dq_lcd_bdl_value_wdq_status_a[0]=4;
- dq_lcd_bdl_value_rdqs_status_a[0]=4;
- }
- if(lane_disable&0x2){
- dq_lcd_bdl_value_wdq_status_a[1]=4;
- dq_lcd_bdl_value_rdqs_status_a[1]=4;
- }
- if(lane_disable&0x4){
- dq_lcd_bdl_value_wdq_status_a[2]=4;
- dq_lcd_bdl_value_rdqs_status_a[2]=4;
- }
- if(lane_disable&0x8){
- dq_lcd_bdl_value_wdq_status_a[3]=4;
- dq_lcd_bdl_value_rdqs_status_a[3]=4;
- }
- printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
- dq_lcd_bdl_value_aclcdlr_status_a=4;
- printf("dq_lcd_bdl_value_aclcdlr_status_a==%x\n",dq_lcd_bdl_value_aclcdlr_status_a);
- }
- if(lane_disable&0x20){
- dq_lcd_bdl_value_bdlr0_status_a=4;
- printf("dq_lcd_bdl_value_bdlr0_status_a==%x\n",dq_lcd_bdl_value_bdlr0_status_a);
-
- }
- }
-
- {
- for (lane_step = 0; lane_step < 4; lane_step++)
-
-
- {
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
- num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
- num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- }
-
-
-
-
- lane_step=4;
- {
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
- num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
- num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
- }
- }
-
- if(0){
- for (i = 0; i < 8; i++) {
- num_arry_lane0[i]=num_arry[8+i];
- }
- for (i = 0; i < 8; i++) {
- num_arry_lane1[i]=num_arry[8+8+i];
- }
- for (i = 0; i < 8; i++) {
- num_arry_lane2[i]=num_arry[8+8+8+i];
- }
- for (i = 0; i < 8; i++) {
- num_arry_lane3[i]=num_arry[8+8+8+8+i];
- }
- num_to_env(name_lane0,num_arry_lane0);
- num_to_env(name_lane1,num_arry_lane1);
- num_to_env(name_lane2,num_arry_lane2);
- num_to_env(name_lane3,num_arry_lane3);
- run_command("save",0);
- }
-
- }
-
-
-
-
- for (i = 0; i < 48; i++) {
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
-
-
- }
-
- test_arg_2_step++;
- num_arry[2]=test_arg_2_step;
- sprintf(str, "0x%08x", num_arry[0]);
- printf("%d %d\n", 0,num_arry[0]);
- for (i = 1; i < 48; i++) {
- //num_arry[i]=0;
- sprintf(str, "%s;0x%08x", str,num_arry[i]);
- printf("%d %d\n", i,num_arry[i]);
-
- }
- //sprintf(str, "%lx", value);
- printf("%s", str);
- setenv(varname, str);
- run_command("save",0);
-
-
- i=2;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
-
- for (i = 8; i < 48; i++) {
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- temp_s1= getenv(str_temp1);
- if(temp_s1)
- {
- num_arry[i]= simple_strtoull_ddr(temp_s1, &endp, 0);
- }
- else
- {num_arry[i]=0;
- }
- printf("ddr_test_data_num_%04d==%d\n",i,num_arry[i]);
- }
-
- ///*
- {
- for (lane_step = 0; lane_step < 4; lane_step++)
- {
- {
- dq_lcd_bdl_value_wdq_org_a[lane_step]=num_arry[8+lane_step*4*2+0];
- dq_lcd_bdl_value_wdq_min_a[lane_step]=num_arry[8+lane_step*4*2+1];
- dq_lcd_bdl_value_wdq_max_a[lane_step]=num_arry[8+lane_step*4*2+2];
- dq_lcd_bdl_value_wdq_status_a[lane_step]=num_arry[8+lane_step*4*2+3];
- }
- {
- dq_lcd_bdl_value_rdqs_org_a[lane_step]=num_arry[8+lane_step*4*2+4];
- dq_lcd_bdl_value_rdqs_min_a[lane_step]=num_arry[8+lane_step*4*2+5];
- dq_lcd_bdl_value_rdqs_max_a[lane_step]=num_arry[8+lane_step*4*2+6];
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=num_arry[8+lane_step*4*2+7];
- }
-
-
- }
- lane_step=4;
- {
- dq_lcd_bdl_value_aclcdlr_org_a=num_arry[8+lane_step*4*2+0];
- dq_lcd_bdl_value_aclcdlr_min_a=num_arry[8+lane_step*4*2+1];
- dq_lcd_bdl_value_aclcdlr_max_a=num_arry[8+lane_step*4*2+2];
- dq_lcd_bdl_value_aclcdlr_status_a=num_arry[8+lane_step*4*2+3];
- dq_lcd_bdl_value_bdlr0_org_a=num_arry[8+lane_step*4*2+4];
- dq_lcd_bdl_value_bdlr0_min_a=num_arry[8+lane_step*4*2+5];
- dq_lcd_bdl_value_bdlr0_max_a=num_arry[8+lane_step*4*2+6];
- dq_lcd_bdl_value_bdlr0_status_a=num_arry[8+lane_step*4*2+7];
- }
- }
- //*/
-
-
-
-
- if (channel_a_en)
- {
-
- //*(char *)(argv2[0])="a";
- // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
- printf("\ntest dqs window lane a\n");
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {
- ddr_test_watchdog_enable(watchdog_time_s); //s
- printf("\nenable %ds watchdog \n",watchdog_time_s);
-
- /*
- {
- lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
- */
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
- ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0)
- ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
- )
- {
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
- ||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0))
- { dq_lcd_bdl_value_wdq_status_a[lane_step]=1;
- {
- {
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+0),2);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
-
- }
- else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_wdq_min_a[lane_step]=lcdlr_temp_count;
- dq_lcd_bdl_value_wdq_status_a[lane_step]=2;
- }
-
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
- num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
- //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
-
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+1;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
-
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==2)||
- (dq_lcd_bdl_value_wdq_status_a[lane_step]==3))
- {
- // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
- // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
- // num_to_env(varname,num_arry);
- // run_command("reset",0);
- // }
-
- {
- if(dq_lcd_bdl_value_wdq_status_a[lane_step]==2)
- { dq_lcd_bdl_value_wdq_status_a[lane_step]=3;
- {
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+0),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
-
- }
- else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==3)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_wdq_max_a[lane_step]=lcdlr_temp_count;
- dq_lcd_bdl_value_wdq_status_a[lane_step]=4;
- }
-
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_wdq_org_a[lane_step];
- //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
- num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+2;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- run_command("reset",0);
- }
-
- }
-
-
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
- ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0)
- ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
- )
- {
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
- ||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
- { dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
- {
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
-
- }
- else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_rdqs_min_a[lane_step]=lcdlr_temp_count;
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
- }
-
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+5;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)||
- (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3))
- {
-
- {
- if(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)
- {
-
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
- {
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
-
- }
- else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_rdqs_max_a[lane_step]=lcdlr_temp_count;
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
- }
-
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- //ddr_udelay(1000000);
- // num_to_env(varname,num_arry);
-
- {
- i=8+lane_step*8+6;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- run_command("reset",0);
- }
-
- }
-
- /*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
- (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
- {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- num_to_env(varname,num_arry);
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
- (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
- {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- num_to_env(varname,num_arry);
- run_command("reset",0);
- }
- */
-
-
- ddr_test_watchdog_disable(); //s
- {printf("close watchdog\n");
- }
-
-
- }
-
-
-
- }
-
- if (channel_a_en)
- {
-
- //*(char *)(argv2[0])="a";
- // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
- printf("\ntest lcdlr ac bdlr window lane a...\n");
-
- {
- ddr_test_watchdog_enable(watchdog_time_s); //s
- printf("\nenable %ds watchdog \n",watchdog_time_s);
- printf("\ndq_lcd_bdl_value_aclcdlr_status_a %d \n",dq_lcd_bdl_value_aclcdlr_status_a);
- lane_step=4;
- env_lcdlr_temp_count="lcdlr_temp_count_a";
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
- ||(dq_lcd_bdl_value_aclcdlr_status_a==0)
- ||(dq_lcd_bdl_value_aclcdlr_status_a==1)
- )
- {
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
- ||(dq_lcd_bdl_value_aclcdlr_status_a==0))
- { dq_lcd_bdl_value_aclcdlr_status_a=1;
- {
- {
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
- i=8+lane_step*8+3;
- printf("aclcdlr_status_a==0x%08x\n",num_arry[i]);
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- printf("\n222test lcdlr ac bdlr window lane a...\n");
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- printf("\n333test lcdlr ac bdlr window lane a...\n");
- //ddr_tune_aclcdlr_step
- sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 0),2);
- printf("\nstr=%s\n",str);
- printf("aclcdlr_status_a1==0x%08x\n",num_arry[i]);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_aclcdlr_status_a=2;
-
- }
- else if (dq_lcd_bdl_value_aclcdlr_status_a==1)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_aclcdlr_min_a=lcdlr_temp_count;
- dq_lcd_bdl_value_aclcdlr_status_a=2;
- }
-
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
- num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_aclcdlr_min_a;
- //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_wdq_max_a[lane_step];
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
-
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+1;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
-
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_aclcdlr_status_a==2)||
- (dq_lcd_bdl_value_aclcdlr_status_a==3))
- {
- // if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
- // {dq_lcd_bdl_value_wdq_status_a[lane_step]=0;
- // num_to_env(varname,num_arry);
- // run_command("reset",0);
- // }
-
- {
- if(dq_lcd_bdl_value_aclcdlr_status_a==2)
- { dq_lcd_bdl_value_aclcdlr_status_a=3;
- {
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 0),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_aclcdlr_status_a=4;
-
- }
- else if (dq_lcd_bdl_value_aclcdlr_status_a==3)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_aclcdlr_max_a=lcdlr_temp_count;
- dq_lcd_bdl_value_aclcdlr_status_a=4;
- }
-
- num_arry[8+lane_step*4*2+0]=dq_lcd_bdl_value_aclcdlr_org_a;
- //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_wdq_min_a[lane_step];
- num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_aclcdlr_max_a;
- num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+2;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+3;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- run_command("reset",0);
- }
-
- }
-
-
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
- ||(dq_lcd_bdl_value_bdlr0_status_a==0)
- ||(dq_lcd_bdl_value_bdlr0_status_a==1)
- )
- {
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
- ||(dq_lcd_bdl_value_bdlr0_status_a==0))
- { dq_lcd_bdl_value_bdlr0_status_a=1;
- {
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 1),2);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_bdlr0_status_a=2;
-
- }
- else if (dq_lcd_bdl_value_bdlr0_status_a==1)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_bdlr0_min_a=lcdlr_temp_count;
- dq_lcd_bdl_value_bdlr0_status_a=2;
- }
-
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_bdlr0_min_a;
- //num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
- //ddr_udelay(1000000);
- //num_to_env(varname,num_arry);
- {
- i=8+lane_step*8+5;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_bdlr0_status_a==2)||
- (dq_lcd_bdl_value_bdlr0_status_a==3))
- {
-
- {
- if(dq_lcd_bdl_value_bdlr0_status_a==2)
- {
-
- dq_lcd_bdl_value_bdlr0_status_a=3;
- {
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
-
- {
- lcdlr_temp_count=0;
- sprintf(buf, "0x%08x", lcdlr_temp_count);
- printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
- run_command("save",0);
- }
-
- sprintf(str,"ddr_tune_aclcdlr_step a 0 0x%08x %d %d",add_test_size,( 1),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- ddr_udelay(2000000);
- dq_lcd_bdl_value_bdlr0_status_a=4;
-
- }
- else if (dq_lcd_bdl_value_bdlr0_status_a==3)
- {
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
- {
- lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
- }
- dq_lcd_bdl_value_bdlr0_max_a=lcdlr_temp_count;
- dq_lcd_bdl_value_bdlr0_status_a=4;
- }
-
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_bdlr0_org_a;
- //num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_bdlr0_max_a;
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_bdlr0_status_a;
- //ddr_udelay(1000000);
- // num_to_env(varname,num_arry);
-
- {
- i=8+lane_step*8+6;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- i=8+lane_step*8+7;
- sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
- run_command("save",0);
- }
- run_command("reset",0);
- }
-
- }
-
- /*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
- (dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
- {dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- num_arry[8+lane_step*4*2+5]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- //num_arry[8+lane_step*4*2+2]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- num_to_env(varname,num_arry);
- run_command("reset",0);
- }
-
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
- (dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
- {dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
- sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
- printf("\nstr=%s\n",str);
- //sprintf(str,"ddr_tune_dqs_step b 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- ddr_test_watchdog_clear();
- run_command(str,0);
- ddr_test_watchdog_clear();
- dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
- num_arry[8+lane_step*4*2+4]=dq_lcd_bdl_value_rdqs_org_a[lane_step];
- //num_arry[8+lane_step*4*2+1]=dq_lcd_bdl_value_rdqs_min_a[lane_step];
- num_arry[8+lane_step*4*2+6]=dq_lcd_bdl_value_rdqs_max_a[lane_step];
- num_arry[8+lane_step*4*2+7]=dq_lcd_bdl_value_rdqs_status_a[lane_step];
- num_to_env(varname,num_arry);
- run_command("reset",0);
- }
- */
-
-
- ddr_test_watchdog_disable(); //s
- {printf("close watchdog\n");
- }
-
-
- }
-
-
-
- }
-
- if (channel_b_en)
- {//*(char *)(argv2[0])="b";
- // run_command("ddr_test_cmd 11 a 0 0x80000 ",0);
- printf("\ntest dqs window lane b\n");
- for ((lane_step=0);(lane_step<8);(lane_step++))
- {
- //sprintf(str,"ddr_tune_dqs_step a 0 0x80000 %d",( lane_step));
- //printf("\nstr=%s\n",str);
- sprintf(str,"ddr_tune_dqs_step b 0 0x%08x %d",ddr_test_size,( lane_step));
- printf("\nstr=%s\n",str);
- run_command(str,0);
-
- }
- }
-
- unsigned int acmdlr= 0;
- unsigned int delay_step_x100= 0;
- if (channel_a_en)
- {
- acmdlr=((readl((DDR0_PUB_ACMDLR)))&ACLCDLR_MAX);
- delay_step_x100=100*1000000/(2*global_ddr_clk*acmdlr);
- printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,step=%d ps,10step=%d ps,100step=%d ps,\n",acmdlr,acmdlr,global_ddr_clk,
- delay_step_x100/100,delay_step_x100/10,delay_step_x100);
-
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {
- printf("\n a_lane_0x%08x|wdq_org 0x%08x |wdq_min 0x%08x |wdq_max 0x%08x ::|rdqs_org 0x%08x |rdqs_min 0x%08x |rdqs_max 0x%08x \n",
- lane_step,
- dq_lcd_bdl_value_wdq_org_a[lane_step],
- dq_lcd_bdl_value_wdq_min_a[lane_step],dq_lcd_bdl_value_wdq_max_a[lane_step],
- dq_lcd_bdl_value_rdqs_org_a[lane_step],
- dq_lcd_bdl_value_rdqs_min_a[lane_step],dq_lcd_bdl_value_rdqs_max_a[lane_step]);
- }
- {
- printf("\nac_lane_0x%08x|lcd_org 0x%08x |lcd_min 0x%08x |lcd_max 0x%08x ::|bdlr_org 0x%08x |bdlr_min 0x%08x |bdlr_max 0x%08x \n",
- 4,
- dq_lcd_bdl_value_aclcdlr_org_a,
- dq_lcd_bdl_value_aclcdlr_min_a,dq_lcd_bdl_value_aclcdlr_max_a,
- dq_lcd_bdl_value_bdlr0_org_a,
- dq_lcd_bdl_value_bdlr0_min_a,dq_lcd_bdl_value_bdlr0_max_a);
- }
- printf("\n\n-----------------------------------------------------------------------------\n\n");
- {
- printf("\n ac_lane_0x0000000| lcdlr_org |lcdlr_set ps|lcdlr_hold ps:|\
- clk_setup ps| clk_hold ps|adj_percent[100]\n");
-
- printf("\n ac_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
- 4,
- dq_lcd_bdl_value_aclcdlr_org_a,
- (((dq_lcd_bdl_value_aclcdlr_max_a-dq_lcd_bdl_value_aclcdlr_org_a)*delay_step_x100
- )/100),
- (((dq_lcd_bdl_value_aclcdlr_org_a-dq_lcd_bdl_value_aclcdlr_min_a)*delay_step_x100
- )/100),
-
- 0,
- 0,
- 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
- 2*dq_lcd_bdl_value_aclcdlr_org_a));
- printf("\n ck_lane0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
- 4,
- dq_lcd_bdl_value_bdlr0_org_a,
- 0,
- 0,
- (((dq_lcd_bdl_value_bdlr0_org_a-dq_lcd_bdl_value_bdlr0_min_a)*delay_step_x100
- )/100),
- (((dq_lcd_bdl_value_bdlr0_max_a-dq_lcd_bdl_value_bdlr0_org_a)*delay_step_x100
- )/100),
-
- 100*(dq_lcd_bdl_value_aclcdlr_max_a+dq_lcd_bdl_value_aclcdlr_min_a)/(
- 2*dq_lcd_bdl_value_bdlr0_org_a));
- }
- printf("\n a_lane_0x00000000| wrdq_org 0x0|w_setup x ps|w_hold x ps::|\
- rd_setup ps|rd_hold x ps|adj_percent[100]\n");
-
-
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {
- printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
- lane_step,
- dq_lcd_bdl_value_wdq_org_a[lane_step],
- (((dq_lcd_bdl_value_wdq_max_a[lane_step]-dq_lcd_bdl_value_wdq_org_a[lane_step])*delay_step_x100
- )/100),
- (((dq_lcd_bdl_value_wdq_org_a[lane_step]-dq_lcd_bdl_value_wdq_min_a[lane_step])*delay_step_x100
- )/100),
-
- 0,
- 0,
- 100*(dq_lcd_bdl_value_wdq_max_a[lane_step]+dq_lcd_bdl_value_wdq_min_a[lane_step])/(
- 2*dq_lcd_bdl_value_wdq_org_a[lane_step]));
-
- printf("\n a_lane_0x%08x| 0x%08x | %08d | %08d ::| %08d | %08d | %08d \n",
- lane_step,
- dq_lcd_bdl_value_rdqs_org_a[lane_step],
- 0,
- 0,
-
- (((dq_lcd_bdl_value_rdqs_org_a[lane_step]-dq_lcd_bdl_value_rdqs_min_a[lane_step])*delay_step_x100
- )/100),
- (((dq_lcd_bdl_value_rdqs_max_a[lane_step]-dq_lcd_bdl_value_rdqs_org_a[lane_step])*delay_step_x100
- )/100),
- 100*(dq_lcd_bdl_value_rdqs_max_a[lane_step]+dq_lcd_bdl_value_rdqs_min_a[lane_step])/(
- 2*dq_lcd_bdl_value_rdqs_org_a[lane_step]));
-
-
-
- }
- }
-
-
-
- if (channel_b_en)
- {
- for ((lane_step=0);(lane_step<4);(lane_step++))
- {;
- }
- }
-
- return reg_value;
-}
-
-
-U_BOOT_CMD(
- ddr_dqs_window_step, 6, 1, do_ddr_test_dqs_window_step,
- "DDR tune dqs function",
- "ddr_dqs_window_step a 0 0x800000 1 or ddr_dqs_window_step b 0 0x800000 5\n dcache off ? \n"
-);
-
-///*
-
-#endif
-
-int do_ddr2pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
-#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
- extern int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
- do_ddr2pll_g12_cmd(cmdtp,flag,argc, argv);
- return 1;
-#endif
-
-#define DDR_TEST_CMD_TEST_ZQ 0
-#define DDR_TEST_CMD_TEST_AC_BIT_SETUP 1
-#define DDR_TEST_CMD_TEST_AC_BIT_HOLD 2
-#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_SETUP 3
-#define DDR_TEST_CMD_TEST_DATA_WRITE_BIT_HOLD 4
-#define DDR_TEST_CMD_TEST_DATA_READ_BIT_SETUP 5
-#define DDR_TEST_CMD_TEST_DATA_READ_BIT_HOLD 6
-#define DDR_TEST_CMD_TEST_DATA_VREF 7
-#define DDR_TEST_CMD_TEST_CLK_INVETER 8
-
-#define DDR_TEST_CMD_TEST_FULLTEST 0xffffffff
- char *endp;
- unsigned int pll, zqcr;
- unsigned int zqpr_soc_dram=0;
- unsigned int ddr_test_cmd_soc_vref=0;
- unsigned int ddr_test_cmd_dram_vref=0;//0x3f;
- unsigned int ddr_test_cmd_zq_vref=0;//0x3f;
-
-
- unsigned int ddr_full_test_enable=0;
- /*
-#define DDR3_DRV_40OHM 0
-#define DDR3_DRV_34OHM 1
-#define DDR3_ODT_0OHM 0
-#define DDR3_ODT_60OHM 1
-#define DDR3_ODT_120OHM 2
-#define DDR3_ODT_40OHM 3
-#define DDR3_ODT_20OHM 4
-#define DDR3_ODT_30OHM 5
-
- // lpddr2 drv odt
-#define LPDDR2_DRV_34OHM 1
-#define LPDDR2_DRV_40OHM 2
-#define LPDDR2_DRV_48OHM 3
-#define LPDDR2_DRV_60OHM 4
-#define LPDDR2_DRV_80OHM 6
-#define LPDDR2_DRV_120OHM 7
-#define LPDDR2_ODT_0OHM 0
-
- // lpddr3 drv odt
-#define LPDDR3_DRV_34OHM 1
-#define LPDDR3_DRV_40OHM 2
-#define LPDDR3_DRV_48OHM 3
-#define LPDDR3_DRV_60OHM 4
-#define LPDDR3_DRV_80OHM 6
-#define LPDDR3_DRV_34_40OHM 9
-#define LPDDR3_DRV_40_48OHM 10
-#define LPDDR3_DRV_34_48OHM 11
-#define LPDDR3_ODT_0OHM 0
-#define LPDDR3_ODT_60OHM 1
-#define LPDDR3_ODT_12OHM 2
-#define LPDDR3_ODT_240HM 3
-
-#define DDR4_DRV_34OHM 0
-#define DDR4_DRV_48OHM 1
-#define DDR4_ODT_0OHM 0
-#define DDR4_ODT_60OHM 1
-#define DDR4_ODT_120OHM 2
-#define DDR4_ODT_40OHM 3
-#define DDR4_ODT_240OHM 4
-#define DDR4_ODT_48OHM 5
-#define DDR4_ODT_80OHM 6
-#define DDR4_ODT_34OHM 7
-*/
- printf("\nargc== 0x%08x\n", argc);
- int i ;
- for (i = 0;i<argc;i++)
- {
- printf("\nargv[%d]=%s\n",i,argv[i]);
- }
-
- unsigned int soc_data_drv_odt = 0;
- //unsigned int dram_drv = 0;
- //unsigned int dram_odt = 0;
- /* need at least two arguments */
- if (argc < 2)
- goto usage;
-
- pll = simple_strtoull_ddr(argv[1], &endp,0);
- if (*argv[1] == 0 || *endp != 0) {
- printf ("Error: Wrong format parament!\n");
- return 1;
- }
- if (argc >2)
- {
- zqcr = simple_strtoull_ddr(argv[2], &endp, 0);
- if (*argv[2] == 0 || *endp != 0) {
- zqcr = 0;
- }
- }
- else
- {
- zqcr = 0;
- }
-
- if(zqcr==0xffffffff)
- {
- ddr_full_test_enable=1;
- zqcr=0;}
-
- if (argc >3)
- {
- // soc_data_drv_odt=zqpr_soc_dram&0xfffff;
- // dram_drv=(zqpr_soc_dram>>20)&0xf;
- // dram_odt=(zqpr_soc_dram>>24)&0xf;
- //bit28 enable soc_zqpr ,bit 29 enabe dram_drv bit 30 enabel dram_odt
- zqpr_soc_dram = simple_strtoull_ddr(argv[3], &endp, 0);
- if (*argv[3] == 0 || *endp != 0) {
- zqpr_soc_dram = 0;
- }
- }
- else
- {
- zqpr_soc_dram = 0;
- }
-
- if (argc >4)
- {
- ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
- if (*argv[4] == 0 || *endp != 0) {
- ddr_test_cmd_soc_vref = 0;
- }
- }
- else
- {
- ddr_test_cmd_soc_vref = 0;
- }
- if (argc >5)
- {
- ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
- if (*argv[5] == 0 || *endp != 0) {
- ddr_test_cmd_dram_vref = 0;
- }
- }
- unsigned int soc_dram_hex_dec=0;
- if (argc >6)
- {
- soc_dram_hex_dec = simple_strtoull_ddr(argv[6], &endp, 0);
- if (*argv[6] == 0 || *endp != 0) {
- soc_dram_hex_dec = 0;
- }
- }
- if (argc >7)
- {
- ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
- if (*argv[7] == 0 || *endp != 0) {
- ddr_test_cmd_zq_vref = 0;
- }
- }
-
-
-
- unsigned int soc_dram_drv_odt_use_vlaue=0;
- unsigned int soc_ac_drv=0;
- unsigned int soc_ac_odt=0;
- unsigned int soc_data_drv=0;
- unsigned int soc_data_odt=0;
- unsigned int dram_drv=0;
- unsigned int dram_odt=0;
- unsigned int soc_data_drv_odt_adj_enable=0;
- unsigned int dram_data_drv_adj_enable=0;
- unsigned int dram_data_odt_adj_enable=0;
-
- unsigned int zq0pr_org = rd_reg(DDR0_PUB_ZQ0PR);
- unsigned int zq1pr_org = rd_reg(DDR0_PUB_ZQ1PR);
- unsigned int pub_dcr= rd_reg(DDR0_PUB_DCR);
-#define DDR_TYPE_LPDDR2 0
-#define DDR_TYPE_LPDDR3 1
-#define DDR_TYPE_DDR3 3
-#define DDR_TYPE_DDR4 4
- unsigned int ddr_type= pub_dcr&0x7; //0 -lpddr2 | 1- lpddr3 | 2- rev | 3 -ddr3 | 4- ddr4
- // unsigned int zq2pr_org = rd_reg(DDR0_PUB_ZQ2PR);
- if (argc >8)
- {
- soc_dram_drv_odt_use_vlaue = simple_strtoull_ddr(argv[8], &endp, 0);
- if (*argv[8] == 0 || *endp != 0) {
- soc_dram_drv_odt_use_vlaue = 0;
- }
- }
- if(soc_dram_drv_odt_use_vlaue)
- {if(zqcr)
- {printf("zqcr[0x%08x],\n", zqcr);
- {
- soc_ac_drv=zqcr%100;
- if(soc_ac_drv>100)
- {soc_ac_drv=0;}
- if(soc_ac_drv==0)
- {soc_ac_drv=1;}
- soc_ac_drv=(480/soc_ac_drv)-1;
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- if(soc_ac_drv>0xf)
- {soc_ac_drv=zq0pr_org&0xf;}
- }
- if(ddr_type==DDR_TYPE_DDR4)
- {
- if(soc_ac_drv>0xf)
- {soc_ac_drv=(zq0pr_org>>8)&0xf;}
- }
- }
-
-
- {
- soc_ac_odt=zqcr/100;
- if(soc_ac_odt>240)
- {soc_ac_odt=480;}
- if(soc_ac_odt==0)
- {soc_ac_odt=1;}
-
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- soc_ac_odt=(360/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
- {soc_ac_odt=(zq0pr_org>>4)&0xf;}
- }
- if(ddr_type==DDR_TYPE_DDR4)
- {
- soc_ac_odt=(480/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
- {soc_ac_odt=(zq0pr_org>>16)&0xf;}
- }
- }
-
- zqcr=(soc_ac_odt<<16)|(soc_ac_drv<<12)|(soc_ac_drv<<8)|(soc_ac_odt<<4)|(soc_ac_drv);
- printf("zqcr[0x%08x],soc_ac_odt [0x%08x],soc_ac_drv [0x%08x]\n", zqcr,soc_ac_odt,soc_ac_drv);
- }
- if(zqpr_soc_dram)
- {printf("zqpr_soc_dram[0x%08x],\n", zqpr_soc_dram);
- {
- soc_data_drv=zqpr_soc_dram%100;
- printf("soc_data_drv[%d],\n", soc_data_drv);
- if(soc_data_drv>100)
- {soc_data_drv=0;
-
- }
- if(soc_data_drv==0)
- {soc_data_drv=1;
- //soc_data_drv_odt_adj_enable=0;
- }
- else
- {//soc_data_drv_odt_adj_enable=1;
- }
- soc_data_drv=(480/soc_data_drv)-1;
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- if(soc_data_drv>0xf)
- {soc_data_drv=zq1pr_org&0xf;}
- }
- if(ddr_type==DDR_TYPE_DDR4)
- {
- if(soc_data_drv>0xf)
- {soc_data_drv=(zq1pr_org>>8)&0xf;}
- }
- }
-
-
- {
- soc_data_odt=(zqpr_soc_dram/100)%1000;
- printf("soc_data_odt[%d],\n", soc_data_odt);
- if(soc_data_odt>240)
- {soc_data_odt=360;}
- if(soc_data_odt==0)
- {soc_data_odt=1;}
-
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- soc_data_odt=(360/soc_data_odt)-1;
- if(soc_data_odt>0xf)
- {soc_data_odt=(zq1pr_org>>4)&0xf;}
- }
- if(ddr_type==DDR_TYPE_DDR4)
- {
- soc_data_odt=(480/soc_data_odt)-1;
- if(soc_data_odt>0xf)
- {soc_data_odt=(zq1pr_org>>16)&0xf;}
- }
-
- }
-
- soc_data_drv_odt_adj_enable=1;
-
- {
- dram_drv=(zqpr_soc_dram/100000)%100;
- printf("dram_drv[%d],\n", dram_drv);
-
- if(dram_drv>100)
- {dram_drv=0;}
- if(dram_drv==0)
- {
- dram_data_drv_adj_enable=0;}
- else
- {dram_data_drv_adj_enable=1;
- }
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- if(dram_drv>=40)
- {dram_drv=0;}
-
- else
- {dram_drv=1;
- }
- }
-
-
- if(ddr_type==DDR_TYPE_DDR4)
- {
- if(dram_drv<48)
- {dram_drv=0;}
-
- else
- {dram_drv=1;
- }
- }
- }
-
-
- {
- dram_odt=(zqpr_soc_dram/100000)/100;
- printf("dram_odt[%d],\n", dram_odt);
- if(dram_odt>240)
- {dram_odt=480;}
- if(dram_odt==0)
- {
- dram_data_odt_adj_enable=0;
- }
- else
- {dram_data_odt_adj_enable=1;
- }
-
-
- if(ddr_type==DDR_TYPE_DDR3)
- {
- if(dram_odt>160)
- {dram_odt=0;}
- else if (dram_odt>90)
- {dram_odt=2;}
- else if (dram_odt>50)
- {dram_odt=1;}
- else if (dram_odt>35)
- {dram_odt=3;}
- else if (dram_odt>25)
- {dram_odt=5;}
- else if (dram_odt<=25)
- {dram_odt=4;}
-
- }
- if(ddr_type==DDR_TYPE_DDR4)
- {
- if(dram_odt>280)
- {dram_odt=0;}
- else if (dram_odt>180)
- {dram_odt=4;}
- else if (dram_odt>100)
- {dram_odt=2;}
- else if (dram_odt>70)
- {dram_odt=6;}
- else if (dram_odt>54)
- {dram_odt=1;}
- else if (dram_odt>44)
- {dram_odt=5;}
- else if (dram_odt>37)
- {dram_odt=3;}
- else if (dram_odt<=34)
- {dram_odt=7;}
-
- }
-
-
-
- }
-
- zqpr_soc_dram=(dram_data_odt_adj_enable<<30)|(dram_data_drv_adj_enable<<29)|(soc_data_drv_odt_adj_enable<<28)|
- (dram_odt<<24)|(dram_drv<<20)|(soc_data_odt<<16)|(soc_data_drv<<12)|(soc_data_drv<<8)|(soc_data_odt<<4)|(soc_data_drv);
- }
- }
-
-
- if (soc_dram_hex_dec)
- {
- if (argc >4)
- {
- ddr_test_cmd_soc_vref = simple_strtoull_ddr(argv[4], &endp, 0);
- if (*argv[4] == 0 || *endp != 0) {
- ddr_test_cmd_soc_vref = 0;
- }
- }
- else
- {
- ddr_test_cmd_soc_vref = 0;
- }
- if (argc >5)
- {
- ddr_test_cmd_dram_vref = simple_strtoull_ddr(argv[5], &endp, 0);
- if (*argv[5] == 0 || *endp != 0) {
- ddr_test_cmd_dram_vref = 0;
- }
- }
- if (argc >7)
- {
- ddr_test_cmd_zq_vref = simple_strtoull_ddr(argv[7], &endp, 0);
- if (*argv[7] == 0 || *endp != 0) {
- ddr_test_cmd_zq_vref = 0;
- }
- }
- if (ddr_test_cmd_soc_vref)
- {
- if (ddr_test_cmd_soc_vref<45)
- ddr_test_cmd_soc_vref=45;
- if (ddr_test_cmd_soc_vref>88)
- ddr_test_cmd_soc_vref=88;
- ddr_test_cmd_soc_vref=(ddr_test_cmd_soc_vref*100-4407)/70;
- }
-
- if (ddr_test_cmd_dram_vref)
- {
- if (ddr_test_cmd_dram_vref<45)
- ddr_test_cmd_dram_vref=45;
- if (ddr_test_cmd_dram_vref>92)
- ddr_test_cmd_dram_vref=92;
- if (ddr_test_cmd_dram_vref>60) {
- ddr_test_cmd_dram_vref=(ddr_test_cmd_dram_vref*100-6000)/65;
- }
- else{
- ddr_test_cmd_dram_vref=((ddr_test_cmd_dram_vref*100-4500)/65)|(1<<6);
- }
- }
-
-
- printf("\nSet ddr_test_cmd_dram_vref [0x%08x]\n",ddr_test_cmd_dram_vref);
- if (ddr_test_cmd_zq_vref == 0)
- ddr_test_cmd_zq_vref=0;
- if (ddr_test_cmd_zq_vref) {
- if (ddr_test_cmd_zq_vref<45)
- ddr_test_cmd_zq_vref=45;
- if (ddr_test_cmd_zq_vref>88)
- ddr_test_cmd_zq_vref=88;
- ddr_test_cmd_zq_vref=(ddr_test_cmd_zq_vref*100-4407)/70;
- }
- }
-
- //if(ddr_test_cmd_type==DDR_TEST_CMD_TEST_AC_BIT_HOLD)
- //{if (ddr_test_cmd_clk_seed ==0)
- //ddr_test_cmd_clk_seed = 0x3f;
- //if (ddr_test_cmd_acbdl_x_seed ==0)
- //ddr_test_cmd_acbdl_x_seed = 0x3f;
- //}
-
-#if defined(CONFIG_M6TV) || defined(CONFIG_M6TVD)
- writel(zqcr | (0x3c << 24), PREG_STICKY_REG0);
-#else
- writel(zqcr | (0xf13 << 20), PREG_STICKY_REG0);
-#endif
-#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
- writel((ddr_test_cmd_zq_vref<<24)|(ddr_test_cmd_soc_vref<<8)|ddr_test_cmd_dram_vref , PREG_STICKY_REG9);
- writel((zqpr_soc_dram<<0) , PREG_STICKY_REG8);
- soc_data_drv_odt=zqpr_soc_dram&0xfffff;
- dram_drv=(zqpr_soc_dram>>20)&0xf;
- dram_odt=(zqpr_soc_dram>>24)&0xf;
- printf("setting zqpr_soc_dram [0x%08x],..bit28 enable soc_zqpr , bit 29 enabe dram_drv, bit 30 enabel dram_odt\n", zqpr_soc_dram);
- printf("soc_data_drv_odt [0x%08x],dram_drv [0x%08x],dram_odt [0x%08x]\n", soc_data_drv_odt,dram_drv,dram_odt);
- if(ddr_full_test_enable)
- {
- pll=(ddr_full_test_enable<<21)|pll;
- printf("ddr_full_test_enable %08x,set sticky reg1 bit 21 1\n", ddr_full_test_enable);
- }
-
-#endif
-
-
- writel(pll, PREG_STICKY_REG1);
-
- printf("Set pll done [0x%08x]\n", readl(PREG_STICKY_REG1));
- printf("Set STICKY_REG0 [0x%08x]\n", readl(PREG_STICKY_REG0));
-#if ( CONFIG_DDR_PHY>=P_DDR_PHY_905X)
- printf("Set STICKY_REG9 [0x%08x]\n", readl(PREG_STICKY_REG9));
- printf("Set STICKY_REG8 [0x%08x]\n", readl(PREG_STICKY_REG8));
-
-#endif
- printf("\nbegin reset 111...........\n");
- printf("\nbegin reset 2...........\n");
- printf("\nbegin reset 3...........\n");
-
-#ifdef CONFIG_M8B
- printf(" t1 \n");
- writel(0xf080000 | 2000, WATCHDOG_TC);
-#else
- printf(" t2 \n");
- // writel(WATCHDOG_TC, 0xf400000 | 2000);
- // *P_WATCHDOG_RESET = 0;
- ddr_test_watchdog_reset_system();
-#endif
- while(1);
- return 0;
-
-usage:
-
- printf(" ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n");
- printf("example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n");
- printf("or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
- printf("or ddr_test_cmd 0x17 1200 6034 0603406034 0 0 0 0 1 \n");
- printf("setting zqpr_soc_dram ,..bit28 enable soc_zqpr , bit 29 enabe dram_drv, bit 30 enabel dram_odt\n");
- printf("setting zqpr_soc_dram ,bit0-bit19 soc_data_drv_odt,bit20-bit24 dram_drv , bit24-bit28 dram_odt\n");
- printf("setting zqpr_soc_dram ,bit0-bit19 bit 0-7 use for ddr3,bit8-19 use for ddr4,odt_down_up\n");
- printf("setting zqpr_soc_dram ,soc_drv=(480/((setting)+1));ddr4---soc_odt=(480/(setting)+1));ddr3---soc_odt=(360/(setting)+1));\n");
-
- printf(" DDR3_DRV_40OHM 0\n");
- printf(" DDR3_DRV_34OHM 1\n\n");
-
- printf(" DDR3_ODT_0OHM 0\n");
- printf(" DDR3_ODT_60OHM 1\n");
- printf(" DDR3_ODT_120OHM 2\n");
- printf(" DDR3_ODT_40OHM 3\n");
- printf(" DDR3_ODT_20OHM 4\n");
- printf(" DDR3_ODT_30OHM 5\n\n\n");
-
- printf(" LPDDR2_DRV_34OHM 1\n");
- printf(" LPDDR2_DRV_40OHM 2\n");
- printf(" LPDDR2_DRV_48OHM 3\n");
- printf(" LPDDR2_DRV_60OHM 4\n");
- printf(" LPDDR2_DRV_80OHM 6\n");
- printf(" LPDDR2_DRV_120OHM 7\n\n");
-
- printf(" LPDDR2_ODT_0OHM 0\n\n\n");
-
-
- printf(" LPDDR3_DRV_34OHM 1\n");
- printf(" LPDDR3_DRV_40OHM 2\n");
- printf(" LPDDR3_DRV_48OHM 3\n");
- printf(" LPDDR3_DRV_60OHM 4\n");
- printf(" LPDDR3_DRV_80OHM 6\n");
- printf(" LPDDR3_DRV_34_40OHM 9\n");
- printf(" LPDDR3_DRV_40_48OHM 10\n");
- printf(" LPDDR3_DRV_34_48OHM 11\n\n");
-
- printf(" LPDDR3_ODT_0OHM 0\n");
- printf(" LPDDR3_ODT_60OHM 1\n");
- printf(" LPDDR3_ODT_12OHM 2\n");
- printf(" LPDDR3_ODT_240HM 3\n\n\n");
-
- printf(" DDR4_DRV_34OHM 0\n");
- printf(" DDR4_DRV_48OHM 1\n\n");
-
- printf(" DDR4_ODT_0OHM 0\n");
- printf(" DDR4_ODT_60OHM 1\n");
- printf(" DDR4_ODT_120OHM 2\n");
- printf(" DDR4_ODT_40OHM 3\n");
- printf(" DDR4_ODT_240OHM 4\n");
- printf(" DDR4_ODT_48OHM 5\n");
- printf(" DDR4_ODT_80OHM 6\n");
- printf(" DDR4_ODT_34OHM 7\n\n\n\n");
-
-
- cmd_usage(cmdtp);
- return 1;
-}
-
-int do_ddr_uboot_new_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- //ddr_test_cmd 0x36 0x20180030 0x1 cmd_offset cmd_value value_size reset_enable
-#if 1
- //#define DDR_USE_DEFINE_TEMPLATE_CONFIG 1
- //#define DDR_STICKY_MAGIC_NUMBER 0x20180000
- //#define DDR_CHIP_ID 0x30
- //#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
- //#define DDR_STICKY_SOURCE_SRAM 0x2
- //dmc sticky reg default not 0. need use common sticky reg as identity
-
-#if 0
- unsigned int ddr_pll = rd_reg(AM_DDR_PLL_CNTL0);
- extern int pll_convert_to_ddr_clk_g12a(unsigned int);
- global_ddr_clk=pll_convert_to_ddr_clk_g12a(ddr_pll);
-#endif
+ //extra
+// unsigned short dmc_test_worst_window_tx;
+// unsigned short dmc_test_worst_window_rx;
+// */
+}ddr_set_t;
+
+ddr_set_t p_ddr_set_t;
+
+char* itoa_ddr_test(int num,char*str,int radix)
+{/*索引表*/
+ printf("\nitoa_ddr_test 1\n");
+ char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+ unsigned unum;/*中间变量*/
+ char temp;
+ int i=0,j,k;
+ /*确定unum的值*/
+ if (radix == 10 && num<0) /*十进制负数*/
+ {
+ unum = (unsigned)-num;
+ str[i++] = '-';
+ }
+ else
+ unum = (unsigned)num;/*其他情况*/
+ /*转换*/
+ printf("\nitoa_ddr_test 2\n");
+ printf("\nunum=0x%08x\n",unum);
+ printf("\nunum2=0x%08x\n",(unum%(unsigned)radix));
+ printf("\nradix=0x%08x\n",radix);
+ str[0] = index[0];
+ printf("\nitoa_ddr_test 22\n");
+ unum /= radix;
+ printf("\nitoa_ddr_test 23\n");
+ do {
+ str[i++] = index[unum%(unsigned)radix];
+ unum /= radix;
+ }while(unum);
+ printf("\nitoa_ddr_test 3\n");
+ str[i] = '\0';
+ /*逆序*/
+ if (str[0] == '-')
+ k = 1;/*十进制负数*/
+ else
+ k = 0;
+ printf("\nitoa_ddr_test 4\n");
+ for (j = k;j <= (i-1)/2;j++)
+ {
+ temp = str[j];
+ str[j] = str[i-1+k-j];
+ str[i-1+k-j] = temp;
+ }
+ return str;
+}
+//#endif
+
+/*
+char *strsep(char **stringp, const char *delim)
+{
+ char *s;
+ const char *spanp;
+ int c, sc;
+ char *tok;
+ if ((s = *stringp)== NULL)
+ return (NULL);
+ for (tok = s;;) {
+ c = *s++;
+ spanp = delim;
+ do {
+ if ((sc =*spanp++) == c) {
+ if (c == 0)
+ s = NULL;
+ else
+ s[-1] = 0;
+ *stringp = s;
+ return (tok);
+ }
+ } while (sc != 0);
+ }
+
+}
+*/
+int TOLOWER(int ch)
+{
+
+ if ((unsigned int)(ch - 'A') < 26u )
+ ch += 'a' - 'A';
+
+ return ch;
+}//大写字母转换为小写字母。
+
+int isxdigit(int ch)
+{
+ return (unsigned int)( ch - '0') < 10u ||
+ (unsigned int)((ch | 0x20) - 'a') < 6u;
+}//判断字符c是否为十六进制数字。
+//当c为A-F,a-f或0-9之间的十六进制数字时,返回非零值,否则返回零。
+int isdigit(int ch)
+{
+ return (unsigned int)(ch - '0') < 10u;
+}//判断字符c是否为数字
+unsigned int simple_guess_base(const char *cp)
+{
+ if (cp[0] == '0') {
+ if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
+ return 16;
+ else
+ // return 8;
+ return 10;
+ } else {
+ return 10;
+ }
+}
+unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
+{
+ unsigned int result = 0;
+ //printf("test sizeof(str_buf)==%d\n",1);
+ if(cp == NULL) //jiaxing add 20170616
+ return 0;
+ if (!base)
+ base = simple_guess_base(cp);
+ if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
+ cp += 2;
+ if (base == 10) {
+ while ((*cp)== '0')
+ cp++;
+ }
+ while (isxdigit(*cp)) {//检查当前cp是否是个十六进制数值,不是直接返回0
+ unsigned int value;
+ value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
+ if (value >= base)
+ break;
+ result = result * base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
+}
+unsigned int env_to_a_num(const char *env_name)
+{
+ char *str_buf = NULL;
+ char buf[48];
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+ unsigned int a_num = 0;
+ char *endp;
+
+ printf("str==%s\n",str_buf);
+
+ a_num=simple_strtoull_ddr(str_buf, &endp, 0);
+ printf("%s==0x%08x\n",str_buf,a_num);
+
+ return a_num;
+}
+unsigned int a_num_to_env(const char *env_name ,unsigned int *a_num)
+{
+ char *str_buf=NULL;
+ char buf[1024];
+ //unsigned int str_to_numarry[48];
+ //str_buf = (char *)malloc(sizeof(char)*1024);
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ printf("str==%s\n",str_buf);
+
+ sprintf(buf, "0x%08x", *a_num);
+
+ printf( "%s==0x%08x", buf,*a_num);
+ setenv(env_name, buf);
+
+ run_command("save",0);
+ return 1;
+}
+unsigned int env_to_num(const char *env_name,unsigned int *num_arry)
+{
+ char *str_buf = NULL;
+ char buf[1024];
+ unsigned int str_to_numarry[48];
+ //str_buf = (char *)malloc(sizeof(char)*1024);
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ char * str[48];
+ char *endp;
+ int i;
+ for (i = 0; i < 48; i++)
+ str_to_numarry[i] = 0;
+ printf("str==%s\n",str_buf);
+ for (i = 0; i < 48; i++) {
+ str[i] = strsep(&str_buf, ";");
+ //str[i] = strsep(&str_buf, " ");
+ if(str[i] == NULL)
+ break;
+ str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
+ //printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
+ //num_arry[i]=str_to_numarry[i];
+ }
+ for (i = 0; i < 48; i++) {
+ printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
+ num_arry[i] = str_to_numarry[i];
+ }
+ //num_arry=(unsigned int *)(&str_to_numarry);
+ return 1;
+}
+
+unsigned int num_to_env(const char *env_name,unsigned int *num_arry)
+{
+ char *str_buf=NULL;
+ char buf[1024];
+ int i;
+ //unsigned int str_to_numarry[48];
+ //str_buf = (char *)malloc(sizeof(char)*1024);
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ //char * str[48];
+ printf("str==%s\n",str_buf);
+
+
+ sprintf(buf, "0x%08x", num_arry[0]);
+ for (i = 1; i < 48; i++) {
+ //num_arry[i]=0;
+ sprintf(buf, "%s;0x%08x", buf,num_arry[i]);
+ printf("%d %d\n", i,num_arry[i]);
+ }
+ //sprintf(str, "%lx", value);
+ printf( "%s", buf);
+ setenv(env_name, buf);
+
+ run_command("save",0);
+ //num_arry=(unsigned int *)(&str_to_numarry);
+ return 1;
+}
+
+#define TDATA32F 0xffffffff
+#define TDATA32A 0xaaaaaaaa
+#define TDATA325 0x55555555
+#define PREG_STICKY_G12A_REG0 (0xff634400 + (0x070 << 2))
+//#define DDR_TEST_AUTO_TEST_CMD_MAGIC 0x01234567
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xff639800)
+#define DMC_STICKY_G12A_0 ((0x0000 << 2) + 0xff638800)
+#define DMC_STICKY_MAGIC_0 0x12345678
+#define DMC_STICKY_MAGIC_1 0xabcdbead
+#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
+#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
+unsigned int dmc_sticky[64];
+unsigned int sticky_reg_base_add=0;
+
+//#define DDR_TEST_ACLCDLR
+unsigned int global_boot_times= 0;
+unsigned int watchdog_time_s= 20;
+unsigned int global_ddr_clk=1;
+unsigned int bdlr_100step=0;
+unsigned int ui_1_32_100step=0;
+unsigned int error_count =0;
+unsigned int error_outof_count_flag=0;
+unsigned int copy_test_flag = 0;
+unsigned int training_pattern_flag = 0;
+unsigned int test_start_addr=0x1080000;
+
+unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
+unsigned int dq_lcd_bdl_value_bdlr0_org_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
+unsigned int dq_lcd_bdl_value_bdlr0_min_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
+unsigned int dq_lcd_bdl_value_bdlr0_max_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
+unsigned int dq_lcd_bdl_value_bdlr0_status_a;
+
+unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
+unsigned int dq_lcd_bdl_value_bdlr0_org_b;
+unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
+unsigned int dq_lcd_bdl_value_bdlr0_min_b;
+unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
+unsigned int dq_lcd_bdl_value_bdlr0_max_b;
+
+unsigned int dq_lcd_bdl_value_wdq_org_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
+unsigned int dq_lcd_bdl_value_wdq_min_a[4];
+unsigned int dq_lcd_bdl_value_wdq_max_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
+unsigned int dq_lcd_bdl_value_wdq_status_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
+
+unsigned int dq_lcd_bdl_value_wdq_org_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
+unsigned int dq_lcd_bdl_value_wdq_min_b[4];
+unsigned int dq_lcd_bdl_value_wdq_max_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
+unsigned int dq_lcd_bdl_value_wdq_status_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
+unsigned int acbdlr0_9_reg_org[10];
+unsigned int acbdlr0_9_reg_setup_max[40];
+unsigned int acbdlr0_9_reg_hold_max[40];
+unsigned int acbdlr0_9_reg_setup_time[40];
+unsigned int acbdlr0_9_reg_hold_time[40];
+// unsigned int data_bdlr0_5_reg_org[6];
+unsigned int data_bdlr0_5_reg_org[28];//4//4lane
+unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr
+unsigned int bdlr0_9_reg_hold_max[24*4];
+unsigned int bdlr0_9_reg_setup_time[24*4];
+unsigned int bdlr0_9_reg_hold_time[24*4];
+
+#define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
+#define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
+
+#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data)
+#define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr)
+
+//#define CONFIG_DDR_CMD_BDL_TUNE
+//#define CONFIG_CMD_DDR_TEST
+
+#ifndef CONFIG_CHIP
+//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
+#define CHIP_OLD 0
+#define CHIP_TXLX 1
+#define CHIP_A113 2
+#define CHIP_G12 3
+#define CONFIG_CHIP CHIP_G12// CHIP_OLD//
+#endif
+
+#define P_DDR_PHY_DEFAULT 0
+#define P_DDR_PHY_GX_BABY 1
+#define P_DDR_PHY_GX_TV_BABY 2
+#define P_DDR_PHY_905X 3
+
+//#define P_DDR_PHY_OLD_TAG 0
+#define P_DDR_PHY_G12 4
+
+#if (CONFIG_CHIP>=CHIP_G12)
+#define CONFIG_DDR_PHY P_DDR_PHY_G12
+#else
+//#define CONFIG_CHIP CHIP_OLD//
+//#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
+//#define CONFIG_DDR_PHY P_DDR_PHY_G12//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
+#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
+//#define CONFIG_DDR_PHY_NEW_TAG1 P_DDR_PHY_G12
+#endif
+
+#define G12_AM_DDR_PLL_CNTL0 0xff638c00
+
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+#include <asm/arch/secure_apb.h>
+#endif
+
+#define PATTERN_USE_DDR_DES
+#define USE_64BIT_POINTER
+//#define USE_32BIT_POINTER
+#ifdef USE_64BIT_POINTER
+#define p_convter_int(a) ( unsigned int )( unsigned long )(a)
+#define int_convter_p(a) ( unsigned long )(a)
+
+#else
+#define p_convter_int(a) ( unsigned int )(a)
+#define int_convter_p(a) ( unsigned int )(a)
+#endif
+
+#ifdef PATTERN_USE_DDR_DES
+#define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d])
+#define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d])))
+#define des_xor_pattern(a,b) ( a^b)
+//des[temp_i]^pattern_2[temp_k][temp_i]
+#else
+#define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d]
+#define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d])
+#define des_xor_pattern(a,b) (a&0+b)
+#endif
+
+
+#define DDR_LCDLR_CK_USE_FAST_PATTERN
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+#define DDR_PREFETCH_CACHE
+#endif
+#ifdef DDR_PREFETCH_CACHE
+#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
+#else
+#define ddr_pld_cache(P)
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+#define DDR0_PUB_REG_BASE 0xc8836000
+#define DDR1_PUB_REG_BASE 0xc8836000
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0x2000
+#define P_DDR0_CLK_CTRL 0xc8836c00
+#define P_DDR1_CLK_CTRL 0xc8836c00
+#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
+#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8836c00))
+#define CLOSE_CHANNEL_A_PHY_CLK() (writel((5), 0xc8836c00))
+#define CLOSE_CHANNEL_B_PHY_CLK() (writel((5), 0xc8836c00))
+// #define P_ISA_TIMERE 0xc1109988
+// #define get_us_time() (readl(P_ISA_TIMERE))
+#define AM_DDR_PLL_CNTL 0xc8836800
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
+
+#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
+#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
+#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
+
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
+#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
+//0x98 reserved)
+#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
+#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
+//0x9c reserved)
+#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
+#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
+#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
+#define ACBDLR_MAX 0X1F
+#define ACLCDLR_MAX 0XFF
+#define DQBDLR_MAX 0X1F
+#define DQLCDLR_MAX 0XFF
+#define DXNGTR_MAX 0X7
+#define ACBDLR_NUM 10
+#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
+
+
+#define DMC_REG_BASE 0xc8838000
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+ //bit 19:16. qos monitor channel select. select one at one time only.
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+ // qos_mon_clk_timer. How long to measure the bandwidth.
+
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+
+
+#elif (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY)
+#define DDR0_PUB_REG_BASE 0xc8836000
+#define DDR1_PUB_REG_BASE 0xc8837000
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0x1000
+#define P_DDR0_CLK_CTRL 0xc8836c00
+#define P_DDR1_CLK_CTRL 0xc8836c00
+#define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
+#define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8837c00))
+#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8836c00))
+#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8837c00))
+// #define P_ISA_TIMERE 0xc1109988
+// #define get_us_time() (readl(P_ISA_TIMERE) )
+#define AM_DDR_PLL_CNTL 0xc8836800
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
+#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
+#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
+#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
+
+#define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2))
+//0x94 reserved)
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2))
+#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2))
+//0x98 reserved)
+#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2))
+#define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2))
+//0x9c reserved)
+#define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2))
+#define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2))
+#define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2))
+#define ACBDLR_MAX 0X1F
+#define ACLCDLR_MAX 0XFF
+#define DQBDLR_MAX 0X1F
+#define DQLCDLR_MAX 0XFF
+#define DXNGTR_MAX 0X7
+#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
+#define DMC_REG_BASE 0xc8838000
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+ //bit 19:16. qos monitor channel select. select one at one time only.
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+ // qos_mon_clk_timer. How long to measure the bandwidth.
+
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+ // at the test period, the granted data cycles for the selected channel and ports.
+
+#elif (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+
+ // #define P_ISA_TIMERE 0xc1109988
+ // #define get_us_time() (readl(P_ISA_TIMERE) )
+#if CONFIG_CHIP >=CHIP_TXLX
+#define DDR0_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
+#define DDR1_PUB_REG_BASE ((0x0000 << 2) + 0xff636000)//DDR0_PUB_RIDR
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0//0x1000
+#define MMC_REG_BASE ((0x0000 << 2) + 0xff637000) // #define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xff637000) 0xc8837000
+#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
+#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
+#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
+#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+
+#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
+#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
+#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
+
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
+#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
+
+#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
+#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
+
+#define DDR0_PUB_DX0GCR0 ((0x01c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x0200 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x0240 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
+
+#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
+
+#define ACBDLR_MAX 0X3F
+#define ACLCDLR_MAX 0X1FF
+#define DQBDLR_MAX 0X3F
+#define DQLCDLR_MAX 0X1FF
+#define DXNGTR_MAX 0X1F
+
+ // #define DMC_REG_BASE MMC_REG_BASE
+
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+ //bit 19:16. qos monitor channel select. select one at one time only.
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+// qos_mon_clk_timer. How long to measure the bandwidth.
+
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+ // at the test period, the granted data cycles for the selected channel and ports.
+
+#else
+#define DDR0_PUB_REG_BASE 0xc8836000
+#define DDR1_PUB_REG_BASE 0xc8836000
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0//0x1000
+#define MMC_REG_BASE 0xc8837000
+#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
+#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
+#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
+#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+
+#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
+#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
+#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
+
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
+#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
+
+#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
+#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
+
+#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
+
+#define ACBDLR_MAX 0X3F
+#define ACLCDLR_MAX 0X1FF
+#define DQBDLR_MAX 0X3F
+#define DQLCDLR_MAX 0X1FF
+#define DXNGTR_MAX 0X1F
+#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
+#ifndef DMC_REG_BASE
+#define DMC_REG_BASE MMC_REG_BASE
+#endif
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+//bit 19:16. qos monitor channel select. select one at one time only.
+//bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+// qos_mon_clk_timer. How long to measure the bandwidth.
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+// at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+// at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+// at the test period, the granted data cycles for the selected channel and ports.
+#endif
+
+#elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
+
+#define DDR0_PUB_REG_BASE 0xc8001000 //0xc8836000
+#define DDR1_PUB_REG_BASE 0xc8001000 // 0xc8836000
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0x2000
+#define P_DDR0_CLK_CTRL 0xc8000800
+#define P_DDR1_CLK_CTRL 0xc8002800
+#define OPEN_CHANNEL_A_PHY_CLK() (writel((0x12b), 0xc8000800))
+#define OPEN_CHANNEL_B_PHY_CLK() (writel((0x12b), 0xc8002800))
+#define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8000800))
+#define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8002800))
+// #define P_ISA_TIMERE 0xc1109988
+// #define get_us_time() (readl(P_ISA_TIMERE))
+
+#define PREG_STICKY_REG0 0xc1100000+(0x207c<<2)
+#define PREG_STICKY_REG1 0xc1100000+(0x207d<<2)
+#define WATCHDOG_TC 0xc1100000+(0x2640<<2)// 0x2640
+
+#define AM_DDR_PLL_CNTL 0xc8000400
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2))
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x91<<2))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x92<<2))
+#define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x91<<2))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x92<<2))
+#define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2))
+#define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2))
+#define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2))
+#define ACBDLR_MAX 0X1F
+#define ACLCDLR_MAX 0XFF
+#define DQBDLR_MAX 0X1F
+#define DQLCDLR_MAX 0XFF
+#define DXNGTR_MAX 0X7
+#define DDR0_PUB_DX0GCR0 ((0xa0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x0c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x0e0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0100 << 2) + DDR0_PUB_REG_BASE)
+#define DMC_REG_BASE 0xc8006000
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+//bit 19:16. qos monitor channel select. select one at one time only.
+//bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+// qos_mon_clk_timer. How long to measure the bandwidth.
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+// at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+// at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+// at the test period, the granted data cycles for the selected channel and ports.
+
+
+
+#elif (CONFIG_DDR_PHY == P_DDR_PHY_G12)
+#define DDR0_PUB_REG_BASE 0xff636000
+#define DDR1_PUB_REG_BASE 0xff636000
+#define CHANNEL_A_REG_BASE 0
+#define CHANNEL_B_REG_BASE 0//0x1000
+#define MMC_REG_BASE 0xff637000
+#define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 ))
+#define P_DDR0_CLK_CTRL DDR_CLK_CNTL
+#define P_DDR1_CLK_CTRL DDR_CLK_CNTL
+#define OPEN_CHANNEL_A_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define OPEN_CHANNEL_B_PHY_CLK() // (writel((0Xb000a000), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_A_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+#define CLOSE_CHANNEL_B_PHY_CLK() // (writel((0Xb000a005), DDR_CLK_CNTL))
+
+#define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 ))
+#define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0
+#define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 ))
+#define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 ))
+#define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 ))
+#define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 ))
+
+#define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 ))
+#define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 ))
+#define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 ))
+
+#define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 ))
+#define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 ))
+#define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 ))
+
+#define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR
+#define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR
+
+#define ACBDLR_MAX 0X3F
+#define ACLCDLR_MAX 0X1FF
+#define DQBDLR_MAX 0X3F
+#define DQLCDLR_MAX 0X1FF
+#define DXNGTR_MAX 0X1F
+#define DDR0_PUB_DX0GCR0 ((0x1c0 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX1GCR0 ((0x200 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX2GCR0 ((0x240 << 2) + DDR0_PUB_REG_BASE)
+#define DDR0_PUB_DX3GCR0 ((0x0280 << 2) + DDR0_PUB_REG_BASE)
+#ifndef DMC_REG_BASE
+#define DMC_REG_BASE MMC_REG_BASE
+#endif
+#define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 ))
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer.
+//bit 19:16. qos monitor channel select. select one at one time only.
+//bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 ))
+// qos_mon_clk_timer. How long to measure the bandwidth.
+
+
+#define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 ))
+// at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 ))
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
+ // at the test period, the granted data cycles for the selected channel and ports.
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
+#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 ))// R/W - PHY General Configuration Register 0
+#define DDR0_PUB_PGCR1 ( DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
+#define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
+#define DDR0_PUB_PGCR3 ( DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
+#define DDR0_PUB_PGCR4 ( DDR0_PUB_REG_BASE + ( 0x008 << 2 )) // R/W - PHY General Configuration Register 4
+#define DDR0_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
+#define DDR0_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
+#define DDR0_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
+#define DDR0_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 )) // R/W - PHY General Configuration Register 8
+
+#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
+#define DDR1_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 )) // R/W - PHY General Configuration Register 0
+#define DDR1_PUB_PGCR1 (DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1
+#define DDR1_PUB_PGCR2 ( DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2
+#define DDR1_PUB_PGCR3 (DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3
+#define DDR1_PUB_PGCR4 (DDR0_PUB_REG_BASE + ( 0x008 << 2 ) )// R/W - PHY General Configuration Register 4
+#define DDR1_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5
+#define DDR1_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6
+#define DDR1_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7
+#define DDR1_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 ) )// R/W - PHY General Configuration Register 8
+
+#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE + ( 0x1d0 << 2 ))
+#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE + ( 0x1d1 << 2 ))
+#define DDR0_PUB_DX0BDLR2 ( DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
+#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
+#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2 ))
+#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2 ))
+#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2 ))
+#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE + ( 0x1e0 << 2 ))
+#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
+#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE + ( 0x1e2 << 2 ))
+#define DDR0_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
+#define DDR0_PUB_DX0LCDLR4 (DDR0_PUB_REG_BASE + ( 0x1e4 << 2 ))
+#define DDR0_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
+#define DDR0_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
+#define DDR0_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2) )
+#define DDR0_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
+#define DDR0_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
+#define DDR0_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
+#define DDR0_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
+
+#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2) )
+#define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2) )
+#define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2) )
+#define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2) )
+#define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2) )
+#define DDR0_PUB_DX1BDLR5 ( DDR0_PUB_REG_BASE + ( 0x216 << 2) )
+#define DDR0_PUB_DX1BDLR6 ( DDR0_PUB_REG_BASE + ( 0x218 << 2) )
+#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2) )
+#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2) )
+#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE + ( 0x222 << 2) )
+#define DDR0_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2) )
+#define DDR0_PUB_DX1LCDLR4 (DDR0_PUB_REG_BASE + ( 0x224 << 2) )
+#define DDR0_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2) )
+#define DDR0_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2) )
+#define DDR0_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2) )
+#define DDR0_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
+#define DDR0_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2) )
+#define DDR0_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2) )
+#define DDR0_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2) )
+
+#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2) )
+#define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2) )
+#define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2) )
+#define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2) )
+#define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2) )
+#define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2) )
+#define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2) )
+#define DDR0_PUB_DX2LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x260 << 2) )
+#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2) )
+#define DDR0_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2) )
+#define DDR0_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2) )
+#define DDR0_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2) )
+#define DDR0_PUB_DX2LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x265 << 2) )
+#define DDR0_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2) )
+#define DDR0_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2) )
+#define DDR0_PUB_DX2GTR0 ( DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
+#define DDR0_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2) )
+#define DDR0_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2) )
+#define DDR0_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2) )
+
+#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2) )
+#define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2) )
+#define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2) )
+#define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2) )
+#define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2) )
+#define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2) )
+#define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2) )
+#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2) )
+#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2) )
+#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE + ( 0x2a2 << 2) )
+#define DDR0_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2) )
+#define DDR0_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2) )
+#define DDR0_PUB_DX3LCDLR5 (DDR0_PUB_REG_BASE + ( 0x2a5 << 2) )
+#define DDR0_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2) )
+#define DDR0_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2) )
+#define DDR0_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
+#define DDR0_PUB_DX3GTR1 ( DDR0_PUB_REG_BASE + ( 0x2b1 << 2) )
+#define DDR0_PUB_DX3GTR2 ( DDR0_PUB_REG_BASE + ( 0x2b2 << 2) )
+#define DDR0_PUB_DX3GTR3 ( DDR0_PUB_REG_BASE + ( 0x2b3 << 2) )
+
+#define DDR1_PUB_DX0BDLR0 ( DDR0_PUB_REG_BASE + ( 0x1d0 << 2) )
+#define DDR1_PUB_DX0BDLR1 ( DDR0_PUB_REG_BASE + ( 0x1d1 << 2) )
+#define DDR1_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE + ( 0x1d2 << 2 ))
+#define DDR1_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 ))
+#define DDR1_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2) )
+#define DDR1_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2) )
+#define DDR1_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2) )
+#define DDR1_PUB_DX0LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x1e0 << 2) )
+#define DDR1_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 ))
+#define DDR1_PUB_DX0LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x1e2 << 2) )
+#define DDR1_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 ))
+#define DDR1_PUB_DX0LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x1e4 << 2) )
+#define DDR1_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 ))
+#define DDR1_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 ))
+#define DDR1_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2 ))
+#define DDR1_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 ))
+#define DDR1_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) )
+#define DDR1_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) )
+#define DDR1_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2))
+
+#define DDR1_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2 ))
+#define DDR1_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2 ))
+#define DDR1_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2 ))
+#define DDR1_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2 ))
+#define DDR1_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2 ))
+#define DDR1_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE + ( 0x216 << 2 ))
+#define DDR1_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE + ( 0x218 << 2 ))
+#define DDR1_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2 ))
+#define DDR1_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2 ))
+#define DDR1_PUB_DX1LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x222 << 2 ))
+#define DDR1_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2 ))
+#define DDR1_PUB_DX1LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x224 << 2 ))
+#define DDR1_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2 ))
+#define DDR1_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2 ))
+#define DDR1_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2 ))
+#define DDR1_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 ))
+#define DDR1_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2 ))
+#define DDR1_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2 ))
+#define DDR1_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2 ))
+
+#define DDR1_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2 ))
+#define DDR1_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2 ))
+#define DDR1_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2 ))
+#define DDR1_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2 ))
+#define DDR1_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2 ))
+#define DDR1_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2 ))
+#define DDR1_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2 ))
+#define DDR1_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE + ( 0x260 << 2 ))
+#define DDR1_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2 ))
+#define DDR1_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2 ))
+#define DDR1_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2 ))
+#define DDR1_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2 ))
+#define DDR1_PUB_DX2LCDLR5 (DDR0_PUB_REG_BASE + ( 0x265 << 2 ))
+#define DDR1_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2 ))
+#define DDR1_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2 ))
+#define DDR1_PUB_DX2GTR0 (DDR0_PUB_REG_BASE + ( 0x270 << 2 ))
+#define DDR1_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2 ))
+#define DDR1_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2 ))
+#define DDR1_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2 ))
+
+#define DDR1_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2 ))
+#define DDR1_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2 ))
+#define DDR1_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2 ))
+#define DDR1_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2 ))
+#define DDR1_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2 ))
+#define DDR1_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2 ))
+#define DDR1_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2 ))
+#define DDR1_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2 ))
+#define DDR1_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2 ))
+#define DDR1_PUB_DX3LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x2a2 << 2 ))
+#define DDR1_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2 ))
+#define DDR1_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2 ))
+#define DDR1_PUB_DX3LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x2a5 << 2 ))
+#define DDR1_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2 ))
+#define DDR1_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2 ))
+#define DDR1_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 ))
+#define DDR1_PUB_DX3GTR1 (DDR0_PUB_REG_BASE + ( 0x2b1 << 2 ))
+#define DDR1_PUB_DX3GTR2 (DDR0_PUB_REG_BASE + ( 0x2b2 << 2 ))
+#define DDR1_PUB_DX3GTR3 (DDR0_PUB_REG_BASE + ( 0x2b3 << 2 ))
+
+
+#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 )) // R/W - LC Delay Line Present Register
+#define DDR0_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
+#define DDR0_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
+#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE + ( 0x150 << 2 )) // R/W - AC Bit Delay Line Register 0
+#define DDR0_PUB_ACBDLR3 ( DDR0_PUB_REG_BASE + ( 0x153 << 2 ) ) // R/W - AC Bit Delay Line Register 3
+
+#define DDR1_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 ) )// R/W - LC Delay Line Present Register
+#define DDR1_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0
+#define DDR1_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1
+#define DDR1_PUB_ACBDLR0 ( DDR0_PUB_REG_BASE + ( 0x150 << 2 ) )// R/W - AC Bit Delay Line Register 0
+
+
+#define DDR0_PUB_ACMDLR DDR0_PUB_ACMDLR0
+#define DDR1_PUB_ACMDLR DDR1_PUB_ACMDLR0
+#define DDR0_PUB_DX0GTR DDR0_PUB_DX0GTR0
+#define DDR0_PUB_DX1GTR DDR0_PUB_DX1GTR0
+#define DDR0_PUB_DX2GTR DDR0_PUB_DX2GTR0
+#define DDR0_PUB_DX3GTR DDR0_PUB_DX3GTR0
+#define DDR1_PUB_DX0GTR DDR0_PUB_DX0GTR0
+#define DDR1_PUB_DX1GTR DDR0_PUB_DX1GTR0
+#define DDR1_PUB_DX2GTR DDR0_PUB_DX2GTR0
+#define DDR1_PUB_DX3GTR DDR0_PUB_DX3GTR0
+
+
+#define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
+#define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
+#define DDR0_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 ) )// R/W - VREF Training Control Register 0
+#define DDR0_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
+#define DDR1_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0
+#define DDR1_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1
+#define DDR1_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 )) // R/W - VREF Training Control Register 0
+#define DDR1_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1
+
+//#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
+//#define DDR1_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
+#define DDR0_PUB_DX0GCR6 ( DDR0_PUB_REG_BASE + ( 0x1c6 << 2 ) )
+#define DDR0_PUB_DX1GCR6 ( DDR0_PUB_REG_BASE + ( 0x206 << 2 ) )
+#define DDR0_PUB_DX2GCR6 ( DDR0_PUB_REG_BASE + ( 0x246 << 2 ) )
+#define DDR0_PUB_DX3GCR6 ( DDR0_PUB_REG_BASE + ( 0x286 << 2 ) )
+#define DDR0_PUB_DCR ( DDR0_PUB_REG_BASE + ( 0x040 << 2 ) ) // R/W - DRAM Configuration Register
+#define DDR0_PUB_MR0 ( DDR0_PUB_REG_BASE + ( 0x060 << 2 ) ) // R/W - Mode Register
+#define DDR0_PUB_MR1 ( DDR0_PUB_REG_BASE + ( 0x061 << 2 ) ) // R/W - Extended Mode Register
+#define DDR0_PUB_MR2 ( DDR0_PUB_REG_BASE + ( 0x062 << 2 ) ) // R/W - Extended Mode Register 2
+#define DDR0_PUB_MR3 ( DDR0_PUB_REG_BASE + ( 0x063 << 2 ) ) // R/W - Extended Mode Register 3
+#define DDR0_PUB_MR4 ( DDR0_PUB_REG_BASE + ( 0x064 << 2 ) ) // R/W - Extended Mode Register 4
+#define DDR0_PUB_MR5 ( DDR0_PUB_REG_BASE + ( 0x065 << 2 ) ) // R/W - Extended Mode Register 5
+#define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6
+#define DDR0_PUB_MR7 ( DDR0_PUB_REG_BASE + ( 0x067 << 2 ) ) // R/W - Extended Mode Register 7
+#define DDR0_PUB_MR11 ( DDR0_PUB_REG_BASE + ( 0x06B << 2 ) ) // R/W - Extended Mode Register 11
+#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x137 << 2 ) ) // R/W - Rank ID Register
+#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0x080 << 2 ) ) // R/W - Data Training Configuration Register
+#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x08C << 2 ) ) // R/W - Data Training Eye Data Register 0
+#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x08D << 2 ) ) // R/W - Data Training Eye Data Register 1
+#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x08E << 2 ) ) // R/W - Data Training Eye Data Register 2
+#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x08F << 2 ) ) // R/W - Vref Training Data Register
+#else
+
+#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
+#define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2))
+#define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2))
+
+#define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2))
+#define DDR1_PUB_PGCR0 (DDR1_PUB_REG_BASE+(0x02<<2))
+#define DDR1_PUB_PGCR1 (DDR1_PUB_REG_BASE+(0x03<<2))
+
+#define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2))
+#define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2))
+#define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2))
+#define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2))
+
+#define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2))
+#define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2))
+#define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2))
+#define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2))
+#define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2))
+#define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2))
+
+#define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2))
+#define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2))
+#define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2))
+#define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2))
+#define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2))
+#define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2))
+#define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2))
+#define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2))
+#define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2))
+#define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2))
+#define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2))
+#define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2))
+#define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2))
+#define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2))
+#define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2))
+#define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2))
+#define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2))
+#define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2))
+#define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2))
+
+#define DDR1_PUB_DX0LCDLR0 (DDR1_PUB_REG_BASE+(0xAE<<2))
+#define DDR1_PUB_DX0LCDLR1 (DDR1_PUB_REG_BASE+(0xAF<<2))
+#define DDR1_PUB_DX0LCDLR2 (DDR1_PUB_REG_BASE+(0xB0<<2))
+#define DDR1_PUB_DX0MDLR (DDR1_PUB_REG_BASE+(0xB1<<2))
+#define DDR1_PUB_DX0GTR (DDR1_PUB_REG_BASE+(0xB2<<2))
+#define DDR1_PUB_DX1LCDLR0 (DDR1_PUB_REG_BASE+(0xCE<<2))
+#define DDR1_PUB_DX1LCDLR1 (DDR1_PUB_REG_BASE+(0xCF<<2))
+#define DDR1_PUB_DX1LCDLR2 (DDR1_PUB_REG_BASE+(0xD0<<2))
+#define DDR1_PUB_DX1MDLR (DDR1_PUB_REG_BASE+(0xD1<<2))
+#define DDR1_PUB_DX1GTR (DDR1_PUB_REG_BASE+(0xD2<<2))
+#define DDR1_PUB_DX2LCDLR0 (DDR1_PUB_REG_BASE+(0xEE<<2))
+#define DDR1_PUB_DX2LCDLR1 (DDR1_PUB_REG_BASE+(0xEF<<2))
+#define DDR1_PUB_DX2LCDLR2 (DDR1_PUB_REG_BASE+(0xF0<<2))
+#define DDR1_PUB_DX2MDLR (DDR1_PUB_REG_BASE+(0xF1<<2))
+#define DDR1_PUB_DX3LCDLR0 (DDR1_PUB_REG_BASE+(0x10E<<2))
+#define DDR1_PUB_DX3LCDLR1 (DDR1_PUB_REG_BASE+(0x10F<<2))
+#define DDR1_PUB_DX3LCDLR2 (DDR1_PUB_REG_BASE+(0x110<<2))
+#define DDR1_PUB_DX3MDLR (DDR1_PUB_REG_BASE+(0x111<<2))
+#define DDR1_PUB_DX3GTR (DDR1_PUB_REG_BASE+(0x112<<2))
+
+
+#define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2))
+#define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2))
+#define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2))
+#define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2))
+#define DDR1_PUB_ACMDLR (DDR1_PUB_REG_BASE+(0x0E<<2))
+#define DDR1_PUB_ACLCDLR (DDR1_PUB_REG_BASE+(0x0F<<2))
+#define DDR1_PUB_ACBDLR0 (DDR1_PUB_REG_BASE+(0x10<<2))
+
+#define DDR0_PUB_ACMDLR0 DDR0_PUB_ACMDLR
+#define DDR1_PUB_ACMDLR0 DDR1_PUB_ACMDLR
+#define DDR0_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
+#define DDR0_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
+#define DDR0_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
+#define DDR0_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
+#define DDR1_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR
+#define DDR1_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR
+#define DDR1_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR
+#define DDR1_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR
+#define DDR0_PUB_DCR (DDR0_PUB_REG_BASE+(0x22<<2))
+#define DDR0_PUB_MR0 (DDR0_PUB_REG_BASE+(0x27<<2))
+#define DDR0_PUB_MR1 (DDR0_PUB_REG_BASE+(0x28<<2))
+#define DDR0_PUB_MR2 (DDR0_PUB_REG_BASE+(0x29<<2))
+#define DDR0_PUB_MR3 (DDR0_PUB_REG_BASE+(0x2A<<2))
+#define DDR0_PUB_RANKIDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Rank ID Register
+#define DDR0_PUB_DTCR0 ( DDR0_PUB_REG_BASE + ( 0<< 2 ) ) // R/W - Data Training Configuration Register
+#define DDR0_PUB_DTEDR0 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 0
+#define DDR0_PUB_DTEDR1 ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Data Training Eye Data Register 1
+#define DDR0_PUB_DTEDR2 ( DDR0_PUB_REG_BASE + ( 0x0 << 2 ) ) // R/W - Data Training Eye Data Register 2
+#define DDR0_PUB_VTDR ( DDR0_PUB_REG_BASE + ( 0x0<< 2 ) ) // R/W - Vref Training Data Register
+
+#ifndef P_DDR0_CLK_CTRL
+#define P_DDR0_CLK_CTRL 0xc8000800
+#endif
+#ifndef P_DDR1_CLK_CTRL
+#define P_DDR1_CLK_CTRL 0xc8002800
+#endif
+
+#define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2))
+#define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2))
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+//unsigned int des[8];
+/*
+ unsigned int pattern_1[4][8]=
+ {
+ 0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+0xff00ff00 ,
+
+};
+unsigned int pattern_2[4][8]={
+0x0001fe00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0002fd00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0004fb00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0008f700 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0010ef00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0020df00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0040bf00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x00807f00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+0x0000ff00 ,
+
+};
+unsigned int pattern_3[4][8]={
+ 0x00010000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00020000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00040000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00080000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00100000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00200000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00400000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00800000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+ 0x00000000 ,
+};
+unsigned int pattern_4[4][8]={
+ 0x51c8c049 ,
+ 0x2d43592c ,
+ 0x0777b50b ,
+ 0x9cd2ebe5 ,
+ 0xc04199d5 ,
+ 0xdc968dc0 ,
+ 0xb8ba8a33 ,
+ 0x35e4327f ,
+ 0x51c8c049 ,
+ 0x2d43592c ,
+ 0x0777b50b ,
+ 0x9cd2ebe5 ,
+ 0xc04199d5 ,
+ 0xdc968dc0 ,
+ 0xb8ba8a33 ,
+ 0x35e4327f ,
+ 0x51c8c049 ,
+ 0x2d43592c ,
+ 0x0777b50b ,
+ 0x9cd2ebe5 ,
+ 0xc04199d5 ,
+ 0xdc968dc0 ,
+ 0xb8ba8a33 ,
+ 0x35e4327f ,
+ 0x51c8c049 ,
+ 0x2d43592c ,
+ 0x0777b50b ,
+ 0x9cd2ebe5 ,
+ 0xc04199d5 ,
+ 0xdc968dc0 ,
+ 0xb8ba8a33 ,
+ 0x35e4327f ,
+};
+unsigned int pattern_5[4][8]={
+ 0xaec9c149 ,
+ 0xd243592c ,
+ 0xf877b50b ,
+ 0x63d2ebe5 ,
+ 0x3f439bd5 ,
+ 0x23968dc0 ,
+ 0x47ba8a33 ,
+ 0xcae4327f ,
+ 0xaeccc449 ,
+ 0xd243592c ,
+ 0xf877b50b ,
+ 0x63d2ebe5 ,
+ 0x3f4991d5 ,
+ 0x23968dc0 ,
+ 0x47ba8a33 ,
+ 0xcae4327f ,
+ 0xaed8d049 ,
+ 0xd243592c ,
+ 0xf877b50b ,
+ 0x63d2ebe5 ,
+ 0x3f61b9d5 ,
+ 0x23968dc0 ,
+ 0x47ba8a33 ,
+ 0xcae4327f ,
+ 0xae888049 ,
+ 0xd243592c ,
+ 0xf877b50b ,
+ 0x63d2ebe5 ,
+ 0x3fc119d5 ,
+ 0x23968dc0 ,
+ 0x47ba8a33 ,
+ 0xcae4327f ,
+};
+unsigned int pattern_6[4][8]={
+ 0xaec9c149 ,
+ 0xd243a62c ,
+ 0xf8774a0b ,
+ 0x63d214e5 ,
+ 0x3f4366d5 ,
+ 0x239672c0 ,
+ 0x47ba7533 ,
+ 0xcae4cd7f ,
+ 0xaecc3f49 ,
+ 0xd243a62c ,
+ 0xf8774a0b ,
+ 0x63d214e5 ,
+ 0x3f4966d5 ,
+ 0x239672c0 ,
+ 0x47ba7533 ,
+ 0xcae4cd7f ,
+ 0xaed83f49 ,
+ 0xd243a62c ,
+ 0xf8774a0b ,
+ 0x63d214e5 ,
+ 0x3f6166d5 ,
+ 0x239672c0 ,
+ 0x47ba7533 ,
+ 0xcae4cd7f ,
+ 0xae883f49 ,
+ 0xd243a62c ,
+ 0xf8774a0b ,
+ 0x63d214e5 ,
+ 0x3fc166d5 ,
+ 0x239672c0 ,
+ 0x47ba7533 ,
+ 0xcae4cd7f ,
+
+};
+unsigned int des[8] ={
+ 0xaec83f49,
+ 0xd243a62c,
+ 0xf8774a0b,
+ 0x63d214e5,
+ 0x3f4166d5,
+ 0x239672c0,
+ 0x47ba7533,
+ 0xcae4cd7f,
+};
+*/
+/*
+ unsigned int des[8] ;
+ des[0] = 0xaec83f49;
+ des[1] = 0xd243a62c;
+ des[2] = 0xf8774a0b;
+ des[3] = 0x63d214e5;
+ des[4] = 0x3f4166d5;
+ des[5] = 0x239672c0;
+ des[6] = 0x47ba7533;
+ des[7] = 0xcae4cd7f;
+ pattern_1[0][0] = 0xff00ff00;
+ pattern_1[0][1] = 0xff00ff00;
+ pattern_1[0][2] = 0xff00ff00;
+ pattern_1[0][3] = 0xff00ff00;
+ pattern_1[0][4] = 0xff00ff00;
+ pattern_1[0][5] = 0xff00ff00;
+ pattern_1[0][6] = 0xff00ff00;
+ pattern_1[0][7] = 0xff00ff00;
+
+ pattern_1[1][0] = 0xff00ff00;
+ pattern_1[1][1] = 0xff00ff00;
+ pattern_1[1][2] = 0xff00ff00;
+ pattern_1[1][3] = 0xff00ff00;
+ pattern_1[1][4] = 0xff00ff00;
+ pattern_1[1][5] = 0xff00ff00;
+ pattern_1[1][6] = 0xff00ff00;
+ pattern_1[1][7] = 0xff00ff00;
+
+ pattern_1[2][0] = 0xff00ff00;
+ pattern_1[2][1] = 0xff00ff00;
+ pattern_1[2][2] = 0xff00ff00;
+ pattern_1[2][3] = 0xff00ff00;
+ pattern_1[2][4] = 0xff00ff00;
+ pattern_1[2][5] = 0xff00ff00;
+ pattern_1[2][6] = 0xff00ff00;
+ pattern_1[2][7] = 0xff00ff00;
+
+ pattern_1[3][0] = 0xff00ff00;
+ pattern_1[3][1] = 0xff00ff00;
+ pattern_1[3][2] = 0xff00ff00;
+ pattern_1[3][3] = 0xff00ff00;
+ pattern_1[3][4] = 0xff00ff00;
+ pattern_1[3][5] = 0xff00ff00;
+ pattern_1[3][6] = 0xff00ff00;
+ pattern_1[3][7] = 0xff00ff00;
+
+ pattern_2[0][0] = 0x0001fe00;
+ pattern_2[0][1] = 0x0000ff00;
+ pattern_2[0][2] = 0x0000ff00;
+ pattern_2[0][3] = 0x0000ff00;
+ pattern_2[0][4] = 0x0002fd00;
+ pattern_2[0][5] = 0x0000ff00;
+ pattern_2[0][6] = 0x0000ff00;
+ pattern_2[0][7] = 0x0000ff00;
+
+ pattern_2[1][0] = 0x0004fb00;
+ pattern_2[1][1] = 0x0000ff00;
+ pattern_2[1][2] = 0x0000ff00;
+ pattern_2[1][3] = 0x0000ff00;
+ pattern_2[1][4] = 0x0008f700;
+ pattern_2[1][5] = 0x0000ff00;
+ pattern_2[1][6] = 0x0000ff00;
+ pattern_2[1][7] = 0x0000ff00;
+
+ pattern_2[2][0] = 0x0010ef00;
+ pattern_2[2][1] = 0x0000ff00;
+ pattern_2[2][2] = 0x0000ff00;
+ pattern_2[2][3] = 0x0000ff00;
+ pattern_2[2][4] = 0x0020df00;
+ pattern_2[2][5] = 0x0000ff00;
+ pattern_2[2][6] = 0x0000ff00;
+pattern_2[2][7] = 0x0000ff00;
+
+pattern_2[3][0] = 0x0040bf00;
+pattern_2[3][1] = 0x0000ff00;
+pattern_2[3][2] = 0x0000ff00;
+pattern_2[3][3] = 0x0000ff00;
+pattern_2[3][4] = 0x00807f00;
+pattern_2[3][5] = 0x0000ff00;
+pattern_2[3][6] = 0x0000ff00;
+pattern_2[3][7] = 0x0000ff00;
+
+pattern_3[0][0] = 0x00010000;
+pattern_3[0][1] = 0x00000000;
+pattern_3[0][2] = 0x00000000;
+pattern_3[0][3] = 0x00000000;
+pattern_3[0][4] = 0x00020000;
+pattern_3[0][5] = 0x00000000;
+pattern_3[0][6] = 0x00000000;
+pattern_3[0][7] = 0x00000000;
+
+pattern_3[1][0] = 0x00040000;
+pattern_3[1][1] = 0x00000000;
+pattern_3[1][2] = 0x00000000;
+pattern_3[1][3] = 0x00000000;
+pattern_3[1][4] = 0x00080000;
+ pattern_3[1][5] = 0x00000000;
+ pattern_3[1][6] = 0x00000000;
+ pattern_3[1][7] = 0x00000000;
+
+ pattern_3[2][0] = 0x00100000;
+ pattern_3[2][1] = 0x00000000;
+ pattern_3[2][2] = 0x00000000;
+ pattern_3[2][3] = 0x00000000;
+ pattern_3[2][4] = 0x00200000;
+ pattern_3[2][5] = 0x00000000;
+ pattern_3[2][6] = 0x00000000;
+ pattern_3[2][7] = 0x00000000;
+
+ pattern_3[3][0] = 0x00400000;
+ pattern_3[3][1] = 0x00000000;
+ pattern_3[3][2] = 0x00000000;
+ pattern_3[3][3] = 0x00000000;
+ pattern_3[3][4] = 0x00800000;
+ pattern_3[3][5] = 0x00000000;
+ pattern_3[3][6] = 0x00000000;
+ pattern_3[3][7] = 0x00000000;
+
+pattern_4[0][0] = 0x51c8c049 ;
+pattern_4[0][1] = 0x2d43592c ;
+pattern_4[0][2] = 0x0777b50b ;
+pattern_4[0][3] = 0x9cd2ebe5 ;
+pattern_4[0][4] = 0xc04199d5 ;
+pattern_4[0][5] = 0xdc968dc0 ;
+pattern_4[0][6] = 0xb8ba8a33 ;
+pattern_4[0][7] = 0x35e4327f ;
+
+pattern_4[1][0] = 0x51c8c049 ;
+pattern_4[1][1] = 0x2d43592c ;
+pattern_4[1][2] = 0x0777b50b ;
+pattern_4[1][3] = 0x9cd2ebe5 ;
+pattern_4[1][4] = 0xc04199d5 ;
+pattern_4[1][5] = 0xdc968dc0 ;
+pattern_4[1][6] = 0xb8ba8a33 ;
+pattern_4[1][7] = 0x35e4327f ;
+
+pattern_4[2][0] = 0x51c8c049 ;
+pattern_4[2][1] = 0x2d43592c ;
+pattern_4[2][2] = 0x0777b50b ;
+pattern_4[2][3] = 0x9cd2ebe5 ;
+pattern_4[2][4] = 0xc04199d5 ;
+pattern_4[2][5] = 0xdc968dc0 ;
+pattern_4[2][6] = 0xb8ba8a33 ;
+pattern_4[2][7] = 0x35e4327f ;
+
+pattern_4[3][0] = 0x51c8c049 ;
+pattern_4[3][1] = 0x2d43592c ;
+pattern_4[3][2] = 0x0777b50b ;
+pattern_4[3][3] = 0x9cd2ebe5 ;
+pattern_4[3][4] = 0xc04199d5 ;
+pattern_4[3][5] = 0xdc968dc0 ;
+pattern_4[3][6] = 0xb8ba8a33 ;
+pattern_4[3][7] = 0x35e4327f ;
+
+pattern_5[0][0] = 0xaec9c149 ;
+pattern_5[0][1] = 0xd243592c ;
+pattern_5[0][2] = 0xf877b50b ;
+pattern_5[0][3] = 0x63d2ebe5 ;
+pattern_5[0][4] = 0x3f439bd5 ;
+pattern_5[0][5] = 0x23968dc0 ;
+pattern_5[0][6] = 0x47ba8a33 ;
+pattern_5[0][7] = 0xcae4327f ;
+pattern_5[1][0] = 0xaeccc449 ;
+pattern_5[1][1] = 0xd243592c ;
+pattern_5[1][2] = 0xf877b50b ;
+pattern_5[1][3] = 0x63d2ebe5 ;
+pattern_5[1][4] = 0x3f4991d5 ;
+pattern_5[1][5] = 0x23968dc0 ;
+pattern_5[1][6] = 0x47ba8a33 ;
+pattern_5[1][7] = 0xcae4327f ;
+pattern_5[2][0] = 0xaed8d049 ;
+pattern_5[2][1] = 0xd243592c ;
+pattern_5[2][2] = 0xf877b50b ;
+pattern_5[2][3] = 0x63d2ebe5 ;
+pattern_5[2][4] = 0x3f61b9d5 ;
+pattern_5[2][5] = 0x23968dc0 ;
+pattern_5[2][6] = 0x47ba8a33 ;
+pattern_5[2][7] = 0xcae4327f ;
+pattern_5[3][0] = 0xae888049 ;
+pattern_5[3][1] = 0xd243592c ;
+pattern_5[3][2] = 0xf877b50b ;
+pattern_5[3][3] = 0x63d2ebe5 ;
+pattern_5[3][4] = 0x3fc119d5 ;
+pattern_5[3][5] = 0x23968dc0 ;
+pattern_5[3][6] = 0x47ba8a33 ;
+pattern_5[3][7] = 0xcae4327f ;
+
+pattern_6[0][1] = 0xd243a62c ;
+pattern_6[0][2] = 0xf8774a0b ;
+pattern_6[0][3] = 0x63d214e5 ;
+pattern_6[0][4] = 0x3f4366d5 ;
+pattern_6[0][5] = 0x239672c0 ;
+pattern_6[0][6] = 0x47ba7533 ;
+pattern_6[0][7] = 0xcae4cd7f ;
+pattern_6[1][0] = 0xaecc3f49 ;
+pattern_6[1][1] = 0xd243a62c ;
+pattern_6[1][2] = 0xf8774a0b ;
+pattern_6[1][3] = 0x63d214e5 ;
+pattern_6[1][4] = 0x3f4966d5 ;
+pattern_6[1][5] = 0x239672c0 ;
+pattern_6[1][6] = 0x47ba7533 ;
+pattern_6[1][7] = 0xcae4cd7f ;
+pattern_6[2][0] = 0xaed83f49 ;
+pattern_6[2][1] = 0xd243a62c ;
+pattern_6[2][2] = 0xf8774a0b ;
+pattern_6[2][3] = 0x63d214e5 ;
+pattern_6[2][4] = 0x3f6166d5 ;
+pattern_6[2][5] = 0x239672c0 ;
+pattern_6[2][6] = 0x47ba7533 ;
+pattern_6[2][7] = 0xcae4cd7f ;
+pattern_6[3][0] = 0xae883f49 ;
+pattern_6[3][1] = 0xd243a62c ;
+pattern_6[3][2] = 0xf8774a0b ;
+pattern_6[3][3] = 0x63d214e5 ;
+pattern_6[3][4] = 0x3fc166d5 ;
+pattern_6[3][5] = 0x239672c0 ;
+pattern_6[3][6] = 0x47ba7533 ;
+pattern_6[3][7] = 0xcae4cd7f ;
+*/
+#endif
+
+#define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START
+#define DDR_TEST_SIZE 0x2000000
+//#define DDR_TEST_SIZE 0x2000
+
+#if (CONFIG_CHIP>=CHIP_TXLX)
+
+#define P_EE_TIMER_E (volatile unsigned int *)((0x3c62 << 2) + 0xffd00000)
+
+///*
+//#ifndef P_PIN_MUX_REG1
+// Pin Mux (9)
+// ----------------------------
+#if (CONFIG_CHIP==CHIP_TXLX)
+#define PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
+#define SEC_PERIPHS_PIN_MUX_0 (0xff634400 + (0x2c << 2))
+#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x2c << 2))
+#define PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
+#define SEC_PERIPHS_PIN_MUX_1 (0xff634400 + (0x2d << 2))
+#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x2d << 2))
+#define PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
+#define SEC_PERIPHS_PIN_MUX_2 (0xff634400 + (0x2e << 2))
+#define P_PERIPHS_PIN_MUX_2 (volatile uint32_t *)(0xff634400 + (0x2e << 2))
+#define PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
+#define SEC_PERIPHS_PIN_MUX_3 (0xff634400 + (0x2f << 2))
+#define P_PERIPHS_PIN_MUX_3 (volatile uint32_t *)(0xff634400 + (0x2f << 2))
+#define PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
+#define SEC_PERIPHS_PIN_MUX_4 (0xff634400 + (0x30 << 2))
+#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x30 << 2))
+#define PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
+#define SEC_PERIPHS_PIN_MUX_5 (0xff634400 + (0x31 << 2))
+#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x31 << 2))
+#define PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
+#define SEC_PERIPHS_PIN_MUX_6 (0xff634400 + (0x32 << 2))
+#define P_PERIPHS_PIN_MUX_6 (volatile uint32_t *)(0xff634400 + (0x32 << 2))
+#define PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
+#define SEC_PERIPHS_PIN_MUX_7 (0xff634400 + (0x33 << 2))
+#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x33 << 2))
+#define PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
+#define SEC_PERIPHS_PIN_MUX_8 (0xff634400 + (0x34 << 2))
+#define P_PERIPHS_PIN_MUX_8 (volatile uint32_t *)(0xff634400 + (0x34 << 2))
+#define PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
+#define SEC_PERIPHS_PIN_MUX_9 (0xff634400 + (0x35 << 2))
+#define P_PERIPHS_PIN_MUX_9 (volatile uint32_t *)(0xff634400 + (0x35 << 2))
+#define PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
+#define SEC_PERIPHS_PIN_MUX_10 (0xff634400 + (0x36 << 2))
+#define P_PERIPHS_PIN_MUX_10 (volatile uint32_t *)(0xff634400 + (0x36 << 2))
+#define PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
+#define SEC_PERIPHS_PIN_MUX_11 (0xff634400 + (0x37 << 2))
+#define P_PERIPHS_PIN_MUX_11 (volatile uint32_t *)(0xff634400 + (0x37 << 2))
+#define PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
+#define SEC_PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
+#define P_PERIPHS_PIN_MUX_12 (volatile uint32_t *)(0xff634400 + (0x38 << 2))
+#endif
+#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 P_PERIPHS_PIN_MUX_7//(((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+//#endif
+
+//#ifndef P_PWM_MISC_REG_AB
+//#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+//#define P_PWM_PWM_B (*((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+//#define P_PWM_MISC_REG_CD (*((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+//#define P_PWM_PWM_D (*((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+//#endif
+//*/
+//#define PWM_MISC_REG_AB (0x6c02)
+//#define P_PWM_MISC_REG_AB (volatile unsigned int *)((0x6c02 << 2) + 0xffd00000)
+//#define WATCHDOG_CNTL ((0x3c34 << 2) + 0xffd00000)
+//#define WATCHDOG_CNTL1 ((0x3c35 << 2) + 0xffd00000)
+//#define WATCHDOG_TCNT ((0x3c36 << 2) + 0xffd00000)
+//#define WATCHDOG_RESET ((0x3c37 << 2) + 0xffd00000)
+#else
+//#define ddr_udelay(a) do{}while((a<<5)--);
+#define P_EE_TIMER_E (volatile unsigned int *)(((0x2662 << 2) + 0xc1100000))
+//#define WATCHDOG_CNTL 0xc11098d0
+//#define WATCHDOG_CNTL1 0xc11098d4
+//#define WATCHDOG_TCNT 0xc11098d8
+//#define WATCHDOG_RESET 0xc11098dc
+#ifndef P_WATCHDOG_CNTL
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+#define P_WATCHDOG_CNTL (volatile unsigned int *)0xc11098d0
+#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
+#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
+#define P_WATCHDOG_RESET (volatile unsigned int *) 0xc11098dc
+#else
+#define P_WATCHDOG_CNTL (volatile unsigned int *)(0xc1100000+(0x2640<<2))
+//#define P_WATCHDOG_CNTL1 (volatile unsigned int *) 0xc11098d4
+//#define P_WATCHDOG_TCNT (volatile unsigned int *)0xc11098d8
+#define P_WATCHDOG_RESET (volatile unsigned int *)(0xc1100000+(0x2641<<2))
+#endif
+#endif
+
+
+#ifndef P_PIN_MUX_REG1
+#define P_PIN_MUX_REG1 (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
+#define P_PIN_MUX_REG2 (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
+#define P_PIN_MUX_REG3 (((volatile unsigned *)(0xda834400 + (0x2f << 2))))
+#define P_PIN_MUX_REG7 (((volatile unsigned *)(0xda834400 + (0x33 << 2))))
+#endif
+
+#ifndef P_PWM_MISC_REG_AB
+#define P_PWM_MISC_REG_AB (((volatile unsigned *)(0xc1100000 + (0x2156 << 2))))
+#define P_PWM_PWM_B (((volatile unsigned *)(0xc1100000 + (0x2155 << 2))))
+#define P_PWM_MISC_REG_CD (((volatile unsigned *)(0xc1100000 + (0x2192 << 2))))
+#define P_PWM_PWM_D (((volatile unsigned *)(0xc1100000 + (0x2191 << 2))))
+#endif
+
+#ifndef P_EE_TIMER_E
+#define P_EE_TIMER_E (((volatile unsigned *)(0xc1100000 + (0x2662 << 2))))
+#endif
+
+#endif
+
+#define get_us_time() (*P_EE_TIMER_E)// (readl(P_ISA_TIMERE))
+
+// #define P_ISA_TIMERE 0xc1109988
+// #define get_us_time() (readl(P_ISA_TIMERE))
+
+/*
+#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
+#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
+
+#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xff807000 + (0x02 << 2))))
+#define P_PWM_PWM_A (*((volatile unsigned *)((0x6c00 << 2) + 0xffd00000)))
+
+#define AO_PIN_MUX_REG (*((volatile unsigned *)(0xff800000 + (0x05 << 2))))
+*/
+
+#define dwc_ddrphy_apb_wr(addr, dat) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))=((uint16_t)dat)
+#define dwc_ddrphy_apb_rd(addr) *(volatile uint16_t *)(int_convter_p(((addr) << 1)+0xfe000000))
+#define ACX_MAX 0x80
+
+void ddr_udelay(unsigned int us)
+{
+//#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = (*((P_EE_TIMER_E)));
+
+ while ((*((P_EE_TIMER_E))) - t0 <= us)
+ ;
+//#endif
+}
+
+#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
+#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
+
+#define DDR_PARAMETER_READ 1
+#define DDR_PARAMETER_WRITE 2
+#define DDR_PARAMETER_LEFT 1
+#define DDR_PARAMETER_RIGHT 2
+
+typedef struct ddr_test_struct {
+ unsigned int ddr_data_source ;
+ unsigned int ddr_data_test_size ;
+ unsigned int ddr_address_test_size ;
+ unsigned int ddr_test_watchdog_times_s ;
+ unsigned int ddr_test_lane_disable ;
+
+ unsigned int ddr_test_window_flag[8] ;
+ unsigned int ddr_test_window_data[100] ;
+} ddr_test_struct_t;
+ddr_test_struct_t *g_ddr_test_struct;
+
+unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
+{
+
+ if(source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ {
+ sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
+
+ if(read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
+ if(read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
+ }
+
+ if(source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
+ {
+ char *pre_env_name = "ddr_test_data_num";
+ char *env_name = "ddr_test_data_num_0000";
+ char *str_buf = NULL;
+ char *temp_s = NULL;
+ char *endp = NULL;
+ char buf[1024];
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
+ sprintf(buf, "0x%08x", parameter_value);
+
+ if(read_write_flag == DDR_PARAMETER_WRITE)
+ {
+ setenv(env_name, buf);
+ run_command("save",0);
+ }
+ if(read_write_flag == DDR_PARAMETER_READ)
+ {
+ temp_s = getenv(env_name);
+ if(temp_s)
+ parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
+ else
+ parameter_value = 0;
+ }
+ }
+
+ if(source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
+ {
+ sticky_reg_base_add=(PREG_STICKY_REG0);
+
+ if(read_write_flag==DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
+ if(read_write_flag==DDR_PARAMETER_READ)
+ parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
+ }
+ return parameter_value;
+}
+
+
+unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
+{
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
+ {
+ sticky_reg_base_add = PREG_STICKY_REG0;
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ {
+ sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
+ {
+ char *pre_env_name = "ddr_test_data_num";
+ char *env_name = "ddr_test_data_num_0000";
+ char *str_buf = NULL;
+ char *temp_s = NULL;
+ char *endp = NULL;
+ char buf[1024];
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
+ sprintf(buf, "0x%08x", parameter_value);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ {
+ setenv(env_name, buf);
+ run_command("save",0);
+ }
+ if(read_write_flag == DDR_PARAMETER_READ)
+ {
+ temp_s = getenv(env_name);
+ if(temp_s)
+ parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
+ else
+ parameter_value = 0;
+ }
+ }
+
+ return parameter_value;
+}
+
+void ddr_test_watchdog_init(uint32_t msec)
+{
+
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+ // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+ *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1);
+
+ // set timeout
+ //*P_WATCHDOG_TCNT = msec;
+ // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
+ *P_WATCHDOG_TCNT = msec;
+ //writel(0,(unsigned int )P_WATCHDOG_RESET);
+ *P_WATCHDOG_RESET = 0;
+ //*P_WATCHDOG_RESET = 0;
+
+ // enable
+ *P_WATCHDOG_CNTL = (*P_WATCHDOG_CNTL)|(1<<18);
+ //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
+ //*P_WATCHDOG_CNTL |= (1<<18);
+#else
+ *P_WATCHDOG_CNTL = (0<<24)|(msec*8-1);
+ //*P_WATCHDOG_TCNT=msec;
+#endif
+}
+
+void ddr_test_watchdog_enable(uint32_t sec)
+{
+
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+ // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+ *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
+ // set timeout
+ //*P_WATCHDOG_TCNT = msec;
+ // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
+ if(sec*100>0xffff)
+ *P_WATCHDOG_TCNT=0xffff;
+ else
+ *P_WATCHDOG_TCNT=sec*100; //max 655s
+ //writel(0,(unsigned int )P_WATCHDOG_RESET);
+ *P_WATCHDOG_RESET=0;
+ //*P_WATCHDOG_RESET = 0;
+
+ // enable
+ *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
+ //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
+ //*P_WATCHDOG_CNTL |= (1<<18);
+#else
+ //*P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(sec*8000-1);
+ *P_WATCHDOG_CNTL=(1<<24)|(1<<19)|(0xffff);
+ printf("\nm8baby_watchdog max only 5s,please take care test size not too long for m8baby\n");
+#endif
+ printf("\nP_WATCHDOG_ENABLE\n");
+}
+
+void ddr_test_watchdog_disable(void )
+{
+
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+ // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+ *P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
+ // set timeout
+ //*P_WATCHDOG_TCNT = msec;
+ // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
+ //*P_WATCHDOG_TCNT=sec*100;
+ //writel(0,(unsigned int )P_WATCHDOG_RESET);
+ *P_WATCHDOG_RESET=0;
+ //*P_WATCHDOG_RESET = 0;
+
+ // enable
+ *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
+ //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
+ //*P_WATCHDOG_CNTL |= (1<<18);
+#else
+ *P_WATCHDOG_CNTL=(0<<24)|(0<<19)|(24000-1);
+#endif
+ printf("\nP_WATCHDOG_DISABLE\n");
+}
+
+
+void ddr_test_watchdog_clear(void )
+{
+
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+ // writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),(unsigned int )P_WATCHDOG_CNTL);
+ //*P_WATCHDOG_CNTL=(1<<24)|(1<<25)|(1<<23)|(1<<21)|(240000-1); //10ms
+ // set timeout
+ //*P_WATCHDOG_TCNT = msec;
+ // writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
+ //*P_WATCHDOG_TCNT=sec*100;
+ //writel(0,(unsigned int )P_WATCHDOG_RESET);
+ *P_WATCHDOG_RESET=0;
+ //*P_WATCHDOG_RESET = 0;
+
+ // enable
+ //*P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)&(~(1<<18));
+ //writel((readl((unsigned int )P_WATCHDOG_CNTL))|(1<<18),(unsigned int )P_WATCHDOG_CNTL);
+ //*P_WATCHDOG_CNTL |= (1<<18);
+ //printf("\nP_WATCHDOG_CLEAR,reg=0x%8x\n",(P_WATCHDOG_RESET));
+}
+
+void ddr_test_watchdog_reset_system(void)
+{
+ //#define P_WATCHDOG_CNTL 0xc11098d0
+ //#define P_WATCHDOG_CNTL1 0xc11098d4
+ //#define P_WATCHDOG_TCNT 0xc11098d8
+ //#define P_WATCHDOG_RESET 0xc11098dc
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+ int i;
+
+ while (1) {
+ /*
+ writel( 0x3 | (1 << 21) // sys reset en ao ee 3
+ | (1 << 23) // interrupt en
+ | (1 << 24) // clk en
+ | (1 << 25) // clk div en
+ | (1 << 26) // sys reset now ao ee 3
+ , (unsigned int )P_WATCHDOG_CNTL);
+ */
+ *P_WATCHDOG_CNTL=
+ 0x3 | (1 << 21) // sys reset en ao ee 3
+ | (1 << 23) // interrupt en
+ | (1 << 24) // clk en
+ | (1 << 25) // clk div en
+ | (1 << 26); // sys reset now ao ee 3;
+ //printf("\nP_WATCHDOG_CNTL reg_add_%x08==%x08",(unsigned int )P_WATCHDOG_CNTL,readl((unsigned int )P_WATCHDOG_CNTL));
+ //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
+ //printf("\nP_WATCHDOG_CNTL==%x08",readl((unsigned int )P_WATCHDOG_CNTL));
+ printf("\nP_WATCHDOG_CNTLREG_ADD %x08==%x08",(unsigned int)(unsigned long)P_WATCHDOG_CNTL,
+ *P_WATCHDOG_CNTL);
+ //writel(0, (unsigned int )P_WATCHDOG_RESET);
+ *P_WATCHDOG_RESET=0;
+
+ // writel(readl((unsigned int )P_WATCHDOG_CNTL) | (1<<18), // watchdog en
+ //(unsigned int )P_WATCHDOG_CNTL);
+ *P_WATCHDOG_CNTL=(*P_WATCHDOG_CNTL)|(1<<18);
+ for (i=0; i<100; i++)
+ *P_WATCHDOG_CNTL;
+ //readl((unsigned int )P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
+ }
+
+#else
+ //WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
+ *P_WATCHDOG_CNTL=(0xf080000 | 2000);
+#endif
+ while(1);
+}
+
+
+//just tune for lcdlr
+
+#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+#else
+int do_ddr_fine_tune_lcdlr_env1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf("\nEnter ddr_fine_tune_lcdlr_env function\n");
+ // if(!argc)
+ // goto DDR_TUNE_DQS_START;
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for(i = 0; i<argc; i++)
+ {
+ printf("\nargv[%d]=%s\n",i,argv[i]);
+ }
+
+ //writel((0), 0xc8836c00);
+ OPEN_CHANNEL_A_PHY_CLK();
+
+ OPEN_CHANNEL_B_PHY_CLK();
+ //writel((0), 0xc8836c00);
+
+ char *endp;
+ // unsigned int *p_start_addr;
+
+#define WR_RD_ADJ_USE_ENV 1
+#define WR_RD_ADJ_USE_UART_INPUT 2
+ unsigned int wr_rd_adj_input_src=1;
+ int wr_adj_per[12]={
+ 100 ,
+ 1000,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ };
+ int rd_adj_per[12]={
+ 100 ,
+ 100 ,
+ 80 ,
+ 80 ,
+ 80 ,
+ 80 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ 100 ,
+ };
+ if(argc == 1)
+ printf("\nplease read help\n");
+
+ if(argc >= 2)
+ {
+ wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
+
+ unsigned int i=0;
+ if(wr_rd_adj_input_src==WR_RD_ADJ_USE_UART_INPUT)
+ {
+ printf("\ntune ddr lcdlr use uart input\n");
+ if (argc>24+2)
+ argc=24+2;
+
+ for(i = 2;i<argc;i++)
+ {
+ if(i<(2+12))
+ wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
+ else
+ rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
+ }
+ }
+
+ // unsigned int = 0, max = 0xff, min = 0x00;
+ if(wr_rd_adj_input_src==WR_RD_ADJ_USE_ENV)
+ {
+ printf("\ntune ddr lcdlr use uboot env\n");
+ //char str[24];
+ const char *s;
+
+ // char *varname;
+ int value=0;
+
+ //*varname="env_ddrtest";
+ s = getenv("env_wr_lcdlr_pr");
+ if (s)
+ {//i=0;
+ //while(s_temp)
+ {
+ printf("%s",s);
+ //sscanf(s,"d%,",wr_adj_per);
+ //sprintf(str,"d%",s);
+ //getc
+ }
+ value = simple_strtoull_ddr(s, &endp, 16);
+ printf("%d",value);
+ }
+ s = getenv("env_rd_lcdlr_pr");
+
+ if (s)
+ {//i=0;
+ //while(s_temp)
+ {
+ printf("%s",s);
+ //sscanf(s,"d%,",rd_adj_per);
+
+ }
+ //value = simple_strtoull_ddr(s, &endp, 16);
+ }
+
+ //sprintf(str, "%lx", value);
+ // setenv("env_ddrtest", str);
+ //run_command("save",0);
+
+ if (argc>24+2)
+ argc=24+2;
+ for(i = 2;i<argc;i++)
+ {
+ if(i<(2+12))
+ wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
+ else
+ rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
+ }
+ }
+ printf(" int wr_adj_per[12]={\n");
+ for(i = 0;i<12;i++)
+ printf("%04d ,\n",wr_adj_per[i]);
+ printf("};\n");
+ printf(" int rd_adj_per[12]={\n");
+ for(i = 0;i<12;i++)
+ printf("%04d ,\n",rd_adj_per[i]);
+ printf("};\n");
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
+ wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))|(1<<0));
+ wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
+ wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))|(1<<0));
+#else
+ wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))|(1<<29));
+ wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))|(1<<26));
+ wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))|(1<<29));
+ wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))|(1<<26));
+#endif
+
+ int lcdlr_w=0,lcdlr_r=0;
+ unsigned temp_reg=0;
+ int temp_count=0;
+ for( temp_count=0;temp_count<2;temp_count++)
+ { temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ if(temp_count==1)
+ lcdlr_w=lcdlr_w&ACBDLR_MAX;
+ wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
+ }
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ for( temp_count=2;temp_count<6;temp_count++)
+ { temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
+ lcdlr_r=lcdlr_r?lcdlr_r:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
+ wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
+ wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR3-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
+ wr_reg(((uint64_t)(temp_reg+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR1)),(lcdlr_r));
+ }
+#else
+ for ( temp_count=2;temp_count<6;temp_count++) {
+ temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&DQLCDLR_MAX);
+ lcdlr_r=lcdlr_r?lcdlr_r:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
+ wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
+ }
+#endif
+ for( temp_count=6;temp_count<8;temp_count++) {
+ temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
+
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ if(temp_count==7)
+ lcdlr_w=lcdlr_w&ACBDLR_MAX;
+ wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
+ }
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ for( temp_count=8;temp_count<12;temp_count++) {
+ temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1))))&DQLCDLR_MAX);
+ lcdlr_r=lcdlr_r?lcdlr_r:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
+ wr_reg(((uint64_t)(temp_reg)),(lcdlr_w));
+ wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR3-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
+ wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
+ }
+#else
+ for( temp_count=8;temp_count<12;temp_count++) {
+ temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
+ lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
+ lcdlr_w=lcdlr_w?lcdlr_w:1;
+ lcdlr_r=(int)(((rd_reg((uint64_t)(temp_reg)))>>8)&0xff);
+ lcdlr_r=lcdlr_r?lcdlr_r:1;
+ lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
+ lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
+ wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
+ }
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
+ wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
+
+ wr_reg(DDR1_PUB_PGCR6, (rd_reg(DDR1_PUB_PGCR6))&(~(1<<0)));
+ wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
+#else
+ wr_reg(DDR0_PUB_PGCR1, (rd_reg(DDR0_PUB_PGCR1))&(~(1<<26)));
+ wr_reg(DDR0_PUB_PIR, (rd_reg(DDR0_PUB_PIR))&(~(1<<29)));
+
+ wr_reg(DDR1_PUB_PGCR1, (rd_reg(DDR1_PUB_PGCR1))&(~(1<<26)));
+ wr_reg(DDR1_PUB_PIR, (rd_reg(DDR1_PUB_PIR))&(~(1<<29)));
+#endif
+ printf("\nend adjust lcdlr\n");
+
+ CLOSE_CHANNEL_A_PHY_CLK();
+ CLOSE_CHANNEL_B_PHY_CLK();
+ }
+
+ return 1;
+}
+U_BOOT_CMD(
+ ddr_test_tune_dqs_env, 30, 1, do_ddr_fine_tune_lcdlr_env1,
+ "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3...",
+ "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
+);
+
+#endif
+//*/
+static void ddr_write(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ for (j=0;j<32;j++)
+ {
+
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ switch (i)
+ {
+ case 0:
+ case 9:
+ case 14:
+ case 25:
+ case 30:
+ *(p+i) = TDATA32F;
+ break;
+ case 1:
+ case 6:
+ case 8:
+ case 17:
+ case 22:
+ *(p+i) = 0;
+ break;
+ case 16:
+ case 23:
+ case 31:
+ *(p+i) = TDATA32A;
+ break;
+ case 7:
+ case 15:
+ case 24:
+ *(p+i) = TDATA325;
+ break;
+ case 2:
+ case 4:
+ case 10:
+ case 12:
+ case 19:
+ case 21:
+ case 27:
+ case 29:
+ *(p+i) = 1<<j;
+ break;
+ case 3:
+ case 5:
+ case 11:
+ case 13:
+ case 18:
+ case 20:
+ case 26:
+ case 28:
+ *(p+i) = ~(1<<j);
+ break;
+ }
+ }
+
+ if (m_len > 128)
+ {
+ m_len -= 128;
+ p += 32;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ for (j=0;j<32;j++)
+ {
+
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+ switch (i)
+ {
+
+ case 0:
+ case 9:
+ case 14:
+ case 25:
+ case 30:
+ if (*(p+i) != TDATA32F)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 1:
+ case 6:
+ case 8:
+ case 17:
+ case 22:
+ if (*(p+i) != 0) {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
+ }break;
+ case 16:
+ case 23:
+ case 31:
+ if (*(p+i) != TDATA32A) {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
+ } break;
+ case 7:
+ case 15:
+ case 24:
+ if (*(p+i) != TDATA325) {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
+ } break;
+ case 2:
+ case 4:
+ case 10:
+ case 12:
+ case 19:
+ case 21:
+ case 27:
+ case 29:
+ if (*(p+i) != 1<<j) {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j);
+ } break;
+ case 3:
+ case 5:
+ case 11:
+ case 13:
+ case 18:
+ case 20:
+ case 26:
+ case 28:
+ if (*(p+i) != ~(1<<j)) {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j));
+ } break;
+ }
+ }
+
+ if (m_len > 128)
+ {
+ m_len -= 128;
+ p += 32;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+
+static void ddr_write4(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ for (j=0;j<32;j++)
+ {
+
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ switch (i)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+
+ *(p+i) = 0xff00ff00;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+
+ *(p+i) = ~0xff00ff00;
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ *(p+i) = 0xaa55aa55;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ *(p+i) = ~0xaa55aa55;
+ break;
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+
+ *(p+i) = 1<<j;
+ break;
+
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ *(p+i) = ~(1<<j);
+ break;
+ }
+ }
+
+ if (m_len > 128)
+ {
+ m_len -= 128;
+ p += 32;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read4(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ for (j=0;j<32;j++)
+ {
+
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+ switch (i)
+ {
+
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+
+ // *(p+i) = 0xff00ff00;
+ if (*(p+i) != 0xff00ff00)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+
+ // *(p+i) = ~0xff00ff00;
+ if (*(p+i) != ~0xff00ff00)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ // *(p+i) = 0xaa55aa55;
+ if (*(p+i) != 0xaa55aa55)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ // *(p+i) = ~0xaa55aa55;
+ if (*(p+i) != ~0xaa55aa55)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+
+ // *(p+i) = 1<<j;
+ if (*(p+i) != (1<<j))
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ // *(p+i) = ~(1<<j);
+ if (*(p+i) !=~( 1<<j))
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ }
+ }
+
+ if (m_len > 128)
+ {
+ m_len -= 128;
+ p += 32;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_full(void *buff, unsigned int m_length,unsigned int start_pattern,
+ unsigned int pattern_offset)
+{
+ unsigned int *p;
+ unsigned int i=0;
+ unsigned int m_len = m_length&0xfffffffc;
+
+ p = ( unsigned int *)buff;
+ //*(p)=start_pattern;
+ while (m_len)
+ {
+ m_len=m_len-4;
+
+ // *(p+i) = (*(p))+pattern_offset;
+
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p+i) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+ if ((*(p+i)) !=(start_pattern+pattern_offset*i))
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
+ (start_pattern+pattern_offset*i));
+ }
+ break;
+
+ i++;
+ }
+}
+
+static void ddr_write_full(void *buff, unsigned int m_length,unsigned int start_pattern,
+ unsigned int pattern_offset)
+{
+ unsigned int *p;
+ unsigned int i=0;
+ unsigned int m_len = m_length&0xfffffffc;
+
+ p = ( unsigned int *)buff;
+ //*(p)=start_pattern;
+ while (m_len)
+ {
+ m_len=m_len-4;
+ *(p+i) = start_pattern+pattern_offset*i;
+ i++;
+ }
+}
+
+///*
+static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size)
+{
+ unsigned int *p_dest;
+ unsigned int *p_src;
+
+ unsigned int m_len = memcpy_size;
+
+ p_dest = ( unsigned int *)addr_dest;
+ p_src = ( unsigned int *)addr_src;
+ m_len = m_len/4; //assume it's multiple of 4
+ while (m_len--) {
+ ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ }
+}
+//*/
+int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *endp;
+ unsigned long loop = 1;
+ unsigned int print_flag =1;
+ // unsigned int start_addr = DDR_TEST_START_ADDR;
+ unsigned int src_addr = DDR_TEST_START_ADDR;
+ unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000;
+ unsigned int test_size = DDR_TEST_SIZE;
+
+
+ print_flag=1;
+
+ printf("\nargc== 0x%08x\n", argc);
+ int i ;
+ for (i = 0;i<argc;i++)
+ printf("\nargv[%d]=%s\n",i,argv[i]);
+
+ // printf("\nLINE== 0x%08x\n", __LINE__);
+ if (argc ==1) {
+ // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ // if (*argv[2] == 0 || *endp != 0)
+ src_addr = DDR_TEST_START_ADDR;
+ loop = 1;
+ }
+ if (argc > 2) {
+ // start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ src_addr = DDR_TEST_START_ADDR;
+ }
+ if (argc > 3) {
+ src_addr = simple_strtoull_ddr(argv[1], &endp, 16);
+ dec_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ test_size = simple_strtoull_ddr(argv[3], &endp, 16);
+ loop = 1;
+ if (*argv[3] == 0 || *endp != 0)
+ test_size = DDR_TEST_SIZE;
+
+ }
+ if (test_size<0x1000)
+ test_size = DDR_TEST_SIZE;
+ if (argc > 4) {
+ loop = simple_strtoull_ddr(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ loop = 1;
+ }
+ if (argc > 5) {
+ print_flag = simple_strtoull_ddr(argv[5], &endp, 16);
+ if (*argv[5] == 0 || *endp != 0)
+ print_flag = 1;
+ }
+ //COPY_TEST_START:
+
+ ///*
+ unsigned long time_start, time_end,test_loops;
+ test_loops=loop;
+ unsigned long size_count=0;
+ size_count=loop*test_size;
+ time_start = get_us_time();//us
+
+ do {
+ // loop = 1;
+ ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size);
+ //bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
+ //mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size);
+ if (print_flag)
+ {
+ printf("\nloop==0x%08x", ( unsigned int )loop);
+ printf("\n \n");
+ }
+ }while(--loop);
+ //*/
+ time_end = get_us_time();//us
+ printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start));
+
+ printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
+ printf("\rEnd ddr test. \n");
+
+ unsigned int m_len=0,counter=0;
+ unsigned int *p_dest;
+ p_dest= (void *)(int_convter_p(dec_addr));
+ m_len = test_size/4; //assume it's multiple of 4
+ counter=(unsigned int)test_loops;
+ size_count=counter*test_size;
+ time_start = get_us_time();//us
+ do {
+ loop = 1;
+ m_len = test_size/4;
+ while (m_len--) {
+ ddr_pld_cache(p_dest) ;
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ }
+ }while(--counter);
+ time_end = get_us_time();//us
+ printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start));
+
+ printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
+
+ unsigned int *p_src;
+ p_src= (void *)(int_convter_p(src_addr));
+ m_len = test_size/4; //assume it's multiple of 4
+ unsigned int temp0=0;
+ //unsigned int temp1=0;
+ //unsigned int temp2=0;
+ //unsigned int temp3=0;
+ counter=(unsigned int)test_loops;
+ size_count=counter*test_size;
+
+ // #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00))
+ //writel((1000000<<0), DMC_MON_CTRL1);
+ //writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
+ //writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2);
+ time_start = get_us_time();//us
+ do {
+ loop = 1;
+ m_len = test_size/4;
+ while (m_len--) {
+ // ddr_pld_cache(p_src++) ;
+#ifdef DDR_PREFETCH_CACHE
+ __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src));
+#endif
+ p_src++;
+ temp0 =( *p_src);
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ }
+ }while(--counter);
+ *p_dest++ = temp0;
+ *p_dest++ = *p_src;
+ *p_dest++ = *p_src;
+ *p_dest++ = *p_src;
+ time_end = get_us_time();//us
+
+ printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start));
+ printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start)));
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddr_test_copy, 7, 1, do_ddr_test_copy,
+ "ddr_test_copy function",
+ "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n"
+);
+
+///*
+#define DDR_PATTERN_LOOP_1 32
+#define DDR_PATTERN_LOOP_2 64
+#define DDR_PATTERN_LOOP_3 96
+/*
+__asm
+{
+.Global memcpy_pld
+.type memcpy_pld ,%function
+.align 8
+memcpy_pld:
+mov x4,x0
+subs x2,x2,#8
+b.mi 2f
+1: ldr x3,[x1],#8
+ subs x2,x2,#8
+ str x3,[x4],#8
+ prfm PLDL1KEEP,[x1,#376]
+ b.pl 1b
+
+2: adds x2,x2,#4
+ b.mi 3f
+ ldr w3,[x1],#4
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+3: adds x2,x2,#2
+ b.mi 4f
+ ldr w3,[x1],#2
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+4: adds x2,x2,#1
+ b.mi 5f
+ ldr w3,[x1],#2
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+5: ret
+}
+*/
+//static void ddr_memcpy_pld(void *addr_dest, void *addr_src, unsigned int m_length)
+//{
+/*
+asm
+{
+//.Global memcpy_pld
+.type memcpy_pld ,%function
+.align 8
+memcpy_pld:
+mov x4,x0
+subs x2,x2,#8
+b.mi 2f
+1: ldr x3,[x1],#8
+ subs x2,x2,#8
+ str x3,[x4],#8
+ prfm PLDL1KEEP,[x1,#376]
+ b.pl 1b
+
+2: adds x2,x2,#4
+ b.mi 3f
+ ldr w3,[x1],#4
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+3: adds x2,x2,#2
+ b.mi 4f
+ ldr w3,[x1],#2
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+4: adds x2,x2,#1
+ b.mi 5f
+ ldr w3,[x1],#2
+ sub x2,x2,#4
+ str w3,[x4],#4
+
+5: ret
+}
+memcpy_pld(addr_dest,addr_src,m_length);
+*/
+//}
+
+
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+
+///*
+
+int ddr_test_gx_cross_talk_pattern(int ddr_test_size)
+{
+ unsigned int start_addr = 0x10000000;
+ error_outof_count_flag=1;
+ error_count=0;
+
+ unsigned int des[8] ;
+ unsigned int pattern_1[4][8] ;
+ unsigned int pattern_2[4][8] ;
+ unsigned int pattern_3[4][8] ;
+ unsigned int pattern_4[4][8] ;
+ unsigned int pattern_5[4][8] ;
+ unsigned int pattern_6[4][8] ;
+
+ des[0] = 0xaec83f49;
+ des[1] = 0xd243a62c;
+ des[2] = 0xf8774a0b;
+ des[3] = 0x63d214e5;
+ des[4] = 0x3f4166d5;
+ des[5] = 0x239672c0;
+ des[6] = 0x47ba7533;
+ des[7] = 0xcae4cd7f;
+ pattern_1[0][0] = 0xff00ff00;
+ pattern_1[0][1] = 0xff00ff00;
+ pattern_1[0][2] = 0xff00ff00;
+ pattern_1[0][3] = 0xff00ff00;
+ pattern_1[0][4] = 0xff00ff00;
+ pattern_1[0][5] = 0xff00ff00;
+ pattern_1[0][6] = 0xff00ff00;
+ pattern_1[0][7] = 0xff00ff00;
+
+ pattern_1[1][0] = 0x00ffff00;
+ pattern_1[1][1] = 0x00ffff00;
+ pattern_1[1][2] = 0x00ffff00;
+ pattern_1[1][3] = 0x00ffff00;
+ pattern_1[1][4] = 0x00ffff00;
+ pattern_1[1][5] = 0x00ffff00;
+ pattern_1[1][6] = 0x00ffff00;
+ pattern_1[1][7] = 0x00ffff00;
+
+ pattern_1[2][0] = 0xffff0000;
+ pattern_1[2][1] = 0xffff0000;
+ pattern_1[2][2] = 0xffff0000;
+ pattern_1[2][3] = 0xffff0000;
+ pattern_1[2][4] = 0xffff0000;
+ pattern_1[2][5] = 0xffff0000;
+ pattern_1[2][6] = 0xffff0000;
+ pattern_1[2][7] = 0xffff0000;
+ pattern_1[3][0] = 0xff00ff00;
+ pattern_1[3][1] = 0xff00ff00;
+ pattern_1[3][2] = 0xff00ff00;
+ pattern_1[3][3] = 0xff00ff00;
+ pattern_1[3][4] = 0xff00ff00;
+ pattern_1[3][5] = 0xff00ff00;
+ pattern_1[3][6] = 0xff00ff00;
+ pattern_1[3][7] = 0xff00ff00;
+
+ pattern_2[0][0] = 0x0001fe00;
+ pattern_2[0][1] = 0x0000ff00;
+ pattern_2[0][2] = 0x0000ff00;
+ pattern_2[0][3] = 0x0000ff00;
+ pattern_2[0][4] = 0x0002fd00;
+ pattern_2[0][5] = 0x0000ff00;
+ pattern_2[0][6] = 0x0000ff00;
+ pattern_2[0][7] = 0x0000ff00;
+
+ pattern_2[1][0] = 0x0004fb00;
+ pattern_2[1][1] = 0x0000ff00;
+ pattern_2[1][2] = 0x0000ff00;
+ pattern_2[1][3] = 0x0000ff00;
+ pattern_2[1][4] = 0x0008f700;
+ pattern_2[1][5] = 0x0000ff00;
+ pattern_2[1][6] = 0x0000ff00;
+ pattern_2[1][7] = 0x0000ff00;
+
+ pattern_2[2][0] = 0x0010ef00;
+ pattern_2[2][1] = 0x0000ff00;
+ pattern_2[2][2] = 0x0000ff00;
+ pattern_2[2][3] = 0x0000ff00;
+ pattern_2[2][4] = 0x0020df00;
+ pattern_2[2][5] = 0x0000ff00;
+ pattern_2[2][6] = 0x0000ff00;
+ pattern_2[2][7] = 0x0000ff00;
+
+ pattern_2[3][0] = 0x0040bf00;
+ pattern_2[3][1] = 0x0000ff00;
+ pattern_2[3][2] = 0x0000ff00;
+ pattern_2[3][3] = 0x0000ff00;
+ pattern_2[3][4] = 0x00807f00;
+ pattern_2[3][5] = 0x0000ff00;
+ pattern_2[3][6] = 0x0000ff00;
+ pattern_2[3][7] = 0x0000ff00;
+
+ pattern_3[0][0] = 0x00010000;
+ pattern_3[0][1] = 0x00000000;
+ pattern_3[0][2] = 0x00000000;
+ pattern_3[0][3] = 0x00000000;
+ pattern_3[0][4] = 0x00020000;
+ pattern_3[0][5] = 0x00000000;
+ pattern_3[0][6] = 0x00000000;
+ pattern_3[0][7] = 0x00000000;
+
+ pattern_3[1][0] = 0x00040000;
+ pattern_3[1][1] = 0x00000000;
+ pattern_3[1][2] = 0x00000000;
+ pattern_3[1][3] = 0x00000000;
+ pattern_3[1][4] = 0x00080000;
+ pattern_3[1][5] = 0x00000000;
+ pattern_3[1][6] = 0x00000000;
+ pattern_3[1][7] = 0x00000000;
+
+ pattern_3[2][0] = 0x00100000;
+ pattern_3[2][1] = 0x00000000;
+ pattern_3[2][2] = 0x00000000;
+ pattern_3[2][3] = 0x00000000;
+ pattern_3[2][4] = 0x00200000;
+ pattern_3[2][5] = 0x00000000;
+ pattern_3[2][6] = 0x00000000;
+ pattern_3[2][7] = 0x00000000;
+
+ pattern_3[3][0] = 0x00400000;
+ pattern_3[3][1] = 0x00000000;
+ pattern_3[3][2] = 0x00000000;
+ pattern_3[3][3] = 0x00000000;
+ pattern_3[3][4] = 0x00800000;
+ pattern_3[3][5] = 0x00000000;
+ pattern_3[3][6] = 0x00000000;
+ pattern_3[3][7] = 0x00000000;
+
+ ///*
+ pattern_4[0][0] = 0x51c8c049 ;
+ pattern_4[0][1] = 0x2d43592c ;
+ pattern_4[0][2] = 0x0777b50b ;
+ pattern_4[0][3] = 0x9cd2ebe5 ;
+ pattern_4[0][4] = 0xc04199d5 ;
+ pattern_4[0][5] = 0xdc968dc0 ;
+ pattern_4[0][6] = 0xb8ba8a33 ;
+ pattern_4[0][7] = 0x35e4327f ;
+
+ pattern_4[1][0] = 0xae37c049 ;
+ pattern_4[1][1] = 0xd2bc592c ;
+ pattern_4[1][2] = 0xf888b50b ;
+ pattern_4[1][3] = 0x632debe5 ;
+ pattern_4[1][4] = 0x3fbe99d5 ;
+ pattern_4[1][5] = 0x23698dc0 ;
+ pattern_4[1][6] = 0x47458a33 ;
+ pattern_4[1][7] = 0xca1b327f ;
+
+ pattern_4[2][0] = 0x51373f49 ;
+ pattern_4[2][1] = 0x2dbca62c ;
+ pattern_4[2][2] = 0x07884a0b ;
+ pattern_4[2][3] = 0x9c2d14e5 ;
+ pattern_4[2][4] = 0xc0be66d5 ;
+ pattern_4[2][5] = 0xdc6972c0 ;
+ pattern_4[2][6] = 0xb8457533 ;
+ pattern_4[2][7] = 0x351bcd7f ;
+
+
+ pattern_4[3][0] = 0x51c8c049 ;
+ pattern_4[3][1] = 0x2d43592c ;
+ pattern_4[3][2] = 0x0777b50b ;
+ pattern_4[3][3] = 0x9cd2ebe5 ;
+ pattern_4[3][4] = 0xc04199d5 ;
+ pattern_4[3][5] = 0xdc968dc0 ;
+ pattern_4[3][6] = 0xb8ba8a33 ;
+ pattern_4[3][7] = 0x35e4327f ;
+
+ pattern_5[0][0] = 0xaec9c149 ;
+ pattern_5[0][1] = 0xd243592c ;
+ pattern_5[0][2] = 0xf877b50b ;
+ pattern_5[0][3] = 0x63d2ebe5 ;
+ pattern_5[0][4] = 0x3f439bd5 ;
+ pattern_5[0][5] = 0x23968dc0 ;
+ pattern_5[0][6] = 0x47ba8a33 ;
+ pattern_5[0][7] = 0xcae4327f ;
+ pattern_5[1][0] = 0xaeccc449 ;
+ pattern_5[1][1] = 0xd243592c ;
+ pattern_5[1][2] = 0xf877b50b ;
+ pattern_5[1][3] = 0x63d2ebe5 ;
+ pattern_5[1][4] = 0x3f4991d5 ;
+ pattern_5[1][5] = 0x23968dc0 ;
+ pattern_5[1][6] = 0x47ba8a33 ;
+ pattern_5[1][7] = 0xcae4327f ;
+ pattern_5[2][0] = 0xaed8d049 ;
+ pattern_5[2][1] = 0xd243592c ;
+ pattern_5[2][2] = 0xf877b50b ;
+ pattern_5[2][3] = 0x63d2ebe5 ;
+ pattern_5[2][4] = 0x3f61b9d5 ;
+ pattern_5[2][5] = 0x23968dc0 ;
+ pattern_5[2][6] = 0x47ba8a33 ;
+ pattern_5[2][7] = 0xcae4327f ;
+ pattern_5[3][0] = 0xae888049 ;
+ pattern_5[3][1] = 0xd243592c ;
+ pattern_5[3][2] = 0xf877b50b ;
+ pattern_5[3][3] = 0x63d2ebe5 ;
+ pattern_5[3][4] = 0x3fc119d5 ;
+ pattern_5[3][5] = 0x23968dc0 ;
+ pattern_5[3][6] = 0x47ba8a33 ;
+ pattern_5[3][7] = 0xcae4327f ;
+
+ pattern_6[0][0] = 0xaec93f49 ;
+ pattern_6[0][1] = 0xd243a62c ;
+ pattern_6[0][2] = 0xf8774a0b ;
+ pattern_6[0][3] = 0x63d214e5 ;
+ pattern_6[0][4] = 0x3f4366d5 ;
+ pattern_6[0][5] = 0x239672c0 ;
+ pattern_6[0][6] = 0x47ba7533 ;
+ pattern_6[0][7] = 0xcae4cd7f ;
+ pattern_6[1][0] = 0xaecc3f49 ;
+ pattern_6[1][1] = 0xd243a62c ;
+ pattern_6[1][2] = 0xf8774a0b ;
+ pattern_6[1][3] = 0x63d214e5 ;
+ pattern_6[1][4] = 0x3f4966d5 ;
+ pattern_6[1][5] = 0x239672c0 ;
+ pattern_6[1][6] = 0x47ba7533 ;
+ pattern_6[1][7] = 0xcae4cd7f ;
+ pattern_6[2][0] = 0xaed83f49 ;
+ pattern_6[2][1] = 0xd243a62c ;
+ pattern_6[2][2] = 0xf8774a0b ;
+ pattern_6[2][3] = 0x63d214e5 ;
+ pattern_6[2][4] = 0x3f6166d5 ;
+ pattern_6[2][5] = 0x239672c0 ;
+ pattern_6[2][6] = 0x47ba7533 ;
+ pattern_6[2][7] = 0xcae4cd7f ;
+ pattern_6[3][0] = 0xae883f49 ;
+ pattern_6[3][1] = 0xd243a62c ;
+ pattern_6[3][2] = 0xf8774a0b ;
+ pattern_6[3][3] = 0x63d214e5 ;
+ pattern_6[3][4] = 0x3fc166d5 ;
+ pattern_6[3][5] = 0x239672c0 ;
+ pattern_6[3][6] = 0x47ba7533 ;
+ pattern_6[3][7] = 0xcae4cd7f ;
+ //*/
+ //*/
+ start_addr=0x10000000;
+ unsigned int test_size = 0x20;
+ unsigned int test_addr;
+ unsigned int temp_i=0;
+ unsigned int temp_k=0;
+ unsigned int pattern_o[8];
+ unsigned int pattern_d[8];
+ {
+ // if(lflag)
+ // loop = 888;
+
+ //if(old_pattern_flag==1)
+ {
+
+ printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
+
+ /*
+ for ((temp_k=0);(temp_k<4);(temp_k++)) {
+ {
+
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+ flush_dcache_range(start_addr,start_addr + test_size);
+
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
+ if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
+ {error_count++;
+ printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
+ }
+ }
+ }
+ }
+ */
+ //if(pattern_flag1==1)
+ {
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
+ // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
+ if (pattern_o[temp_i] != pattern_4[temp_k][temp_i])
+ {error_count++;
+ printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
+ }
+
+ }
+ }
+ }
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
+ // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
+ pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
+ if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
+ {error_count++;
+ printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]);
+ }
+
+ }
+ }
+ }
+ }
+ //if(pattern_flag2==1)
+ {
+ for ((temp_k=0);(temp_k<4);(temp_k++)) {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
+ if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
+ {error_count++;
+ printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
+ }
+ }
+ }
+ }
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
+ pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
+ if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
+ {error_count++;
+ printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]);
+ }
+ }
+ }
+ }
+
+ }
+
+ // if(pattern_flag3==1)
+ {
+ for ((temp_k=0);(temp_k<4);(temp_k++)) {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
+ if (pattern_o[temp_i] != pattern_6[temp_k][temp_i])
+ {error_count++;
+ printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]);
+ }
+ }
+ }
+ }
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_6[temp_k][temp_i]);
+ pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
+ if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i])
+ {error_count++;
+ printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]);
+ }
+ }
+ }
+ }
+ }
+
+
+
+ }
+
+ printf("\Error count==0x%08x", error_count);
+ printf("\n \n");
+ }
+
+ if (error_count)
+ return 1;
+ else
+ return 0;
+}
+
+int ddr_test_gx_training_pattern(int ddr_test_size)
+{
+ unsigned int start_addr = 0x10000000;
+ error_outof_count_flag=1;
+ error_count=0;
+
+ unsigned int des[8] ;
+ unsigned int pattern_1[4][8] ;
+ // unsigned int pattern_2[4][8] ;
+ // unsigned int pattern_3[4][8] ;
+ // unsigned int pattern_4[4][8] ;
+ // unsigned int pattern_5[4][8] ;
+ //unsigned int pattern_6[4][8] ;
+
+ des[0] = 0xaec83f49;
+ des[1] = 0xd243a62c;
+ des[2] = 0xf8774a0b;
+ des[3] = 0x63d214e5;
+ des[4] = 0x3f4166d5;
+ des[5] = 0x239672c0;
+ des[6] = 0x47ba7533;
+ des[7] = 0xcae4cd7f;
+ /*
+ pattern_1[0][0] = 0x55005500;
+ pattern_1[0][1] = 0xaa00aa00;
+ pattern_1[0][2] = 0x55005500;
+ pattern_1[0][3] = 0xaa00aa00;
+ pattern_1[0][4] = 0x55005500;
+ pattern_1[0][5] = 0xaa00aa00;
+ pattern_1[0][6] = 0x55005500;
+ pattern_1[0][7] = 0xaa00aa00;
+
+ pattern_1[1][0] = 0x55005500;
+ pattern_1[1][1] = 0xaa00aa00;
+ pattern_1[1][2] = 0x55005500;
+ pattern_1[1][3] = 0xaa00aa00;
+ pattern_1[1][4] = 0x55005500;
+ pattern_1[1][5] = 0xaa00aa00;
+ pattern_1[1][6] = 0x55005500;
+ pattern_1[1][7] = 0xaa00aa00;
+
+ pattern_1[2][0] = 0x55005500;
+ pattern_1[2][1] = 0xaa00aa00;
+ pattern_1[2][2] = 0x55005500;
+ pattern_1[2][3] = 0xaa00aa00;
+ pattern_1[2][4] = 0x55005500;
+ pattern_1[2][5] = 0xaa00aa00;
+ pattern_1[2][6] = 0x55005500;
+ pattern_1[2][7] = 0xaa00aa00;
+
+ pattern_1[3][0] = 0x55005500;
+ pattern_1[3][1] = 0xaa00aa00;
+ pattern_1[3][2] = 0x55005500;
+ pattern_1[3][3] = 0xaa00aa00;
+ pattern_1[3][4] = 0x55005500;
+ pattern_1[3][5] = 0xaa00aa00;
+ pattern_1[3][6] = 0x55005500;
+ pattern_1[3][7] = 0xaa00aa00;
+ */
+ // /*
+ pattern_1[0][0] = 0x55aa5500;
+ pattern_1[0][1] = 0x55aa5500;
+ pattern_1[0][2] = 0x55aa5500;
+ pattern_1[0][3] = 0x55aa5500;
+ pattern_1[0][4] = 0xaa00ff00;
+ pattern_1[0][5] = 0xaa00ff00;
+ pattern_1[0][6] = 0xaa00ff00;
+ pattern_1[0][7] = 0xaa00ff00;
+
+ pattern_1[1][0] = 0x55005500;
+ pattern_1[1][1] = 0xaa00aa00;
+ pattern_1[1][2] = 0x55005500;
+ pattern_1[1][3] = 0xaa00aa00;
+ pattern_1[1][4] = 0x55005500;
+ pattern_1[1][5] = 0xaa00aa00;
+ pattern_1[1][6] = 0x55005500;
+ pattern_1[1][7] = 0xaa00aa00;
+
+ pattern_1[2][0] = 0x0001fe00;
+ pattern_1[2][1] = 0x0000ff00;
+ pattern_1[2][2] = 0x0000ff00;
+ pattern_1[2][3] = 0x0000ff00;
+ pattern_1[2][4] = 0x0002fd00;
+ pattern_1[2][5] = 0x0000ff00;
+ pattern_1[2][6] = 0x0000ff00;
+ pattern_1[2][7] = 0x0000ff00;
+
+ pattern_1[3][0] = 0x0004fb00;
+ pattern_1[3][1] = 0x0000ff00;
+ pattern_1[3][2] = 0x0000ff00;
+ pattern_1[3][3] = 0x0000ff00;
+ pattern_1[3][4] = 0x0008f700;
+ pattern_1[3][5] = 0x0000ff00;
+ pattern_1[3][6] = 0x0000ff00;
+ pattern_1[3][7] = 0x0000ff00;
+ //*/
+ /*
+ pattern_2[0][0] = 0x0001fe00;
+ pattern_2[0][1] = 0x0000ff00;
+ pattern_2[0][2] = 0x0000ff00;
+ pattern_2[0][3] = 0x0000ff00;
+ pattern_2[0][4] = 0x0002fd00;
+ pattern_2[0][5] = 0x0000ff00;
+ pattern_2[0][6] = 0x0000ff00;
+ pattern_2[0][7] = 0x0000ff00;
+
+ pattern_2[1][0] = 0x0004fb00;
+ pattern_2[1][1] = 0x0000ff00;
+ pattern_2[1][2] = 0x0000ff00;
+ pattern_2[1][3] = 0x0000ff00;
+ pattern_2[1][4] = 0x0008f700;
+ pattern_2[1][5] = 0x0000ff00;
+ pattern_2[1][6] = 0x0000ff00;
+ pattern_2[1][7] = 0x0000ff00;
+
+ pattern_2[2][0] = 0x0010ef00;
+ pattern_2[2][1] = 0x0000ff00;
+ pattern_2[2][2] = 0x0000ff00;
+ pattern_2[2][3] = 0x0000ff00;
+ pattern_2[2][4] = 0x0020df00;
+ pattern_2[2][5] = 0x0000ff00;
+ pattern_2[2][6] = 0x0000ff00;
+ pattern_2[2][7] = 0x0000ff00;
+
+ pattern_2[3][0] = 0x0040bf00;
+ pattern_2[3][1] = 0x0000ff00;
+ pattern_2[3][2] = 0x0000ff00;
+ pattern_2[3][3] = 0x0000ff00;
+ pattern_2[3][4] = 0x00807f00;
+ pattern_2[3][5] = 0x0000ff00;
+ pattern_2[3][6] = 0x0000ff00;
+ pattern_2[3][7] = 0x0000ff00;
+
+ pattern_3[0][0] = 0x00010000;
+ pattern_3[0][1] = 0x00000000;
+ pattern_3[0][2] = 0x00000000;
+ pattern_3[0][3] = 0x00000000;
+ pattern_3[0][4] = 0x00020000;
+ pattern_3[0][5] = 0x00000000;
+ pattern_3[0][6] = 0x00000000;
+ pattern_3[0][7] = 0x00000000;
+
+ pattern_3[1][0] = 0x00040000;
+ pattern_3[1][1] = 0x00000000;
+ pattern_3[1][2] = 0x00000000;
+ pattern_3[1][3] = 0x00000000;
+ pattern_3[1][4] = 0x00080000;
+ pattern_3[1][5] = 0x00000000;
+ pattern_3[1][6] = 0x00000000;
+ pattern_3[1][7] = 0x00000000;
+
+ pattern_3[2][0] = 0x00100000;
+ pattern_3[2][1] = 0x00000000;
+ pattern_3[2][2] = 0x00000000;
+ pattern_3[2][3] = 0x00000000;
+ pattern_3[2][4] = 0x00200000;
+ pattern_3[2][5] = 0x00000000;
+ pattern_3[2][6] = 0x00000000;
+ pattern_3[2][7] = 0x00000000;
+
+ pattern_3[3][0] = 0x00400000;
+ pattern_3[3][1] = 0x00000000;
+ pattern_3[3][2] = 0x00000000;
+ pattern_3[3][3] = 0x00000000;
+ pattern_3[3][4] = 0x00800000;
+ pattern_3[3][5] = 0x00000000;
+ pattern_3[3][6] = 0x00000000;
+ pattern_3[3][7] = 0x00000000;
+
+
+ pattern_4[0][0] = 0x51c8c049 ;
+ pattern_4[0][1] = 0x2d43592c ;
+ pattern_4[0][2] = 0x0777b50b ;
+ pattern_4[0][3] = 0x9cd2ebe5 ;
+ pattern_4[0][4] = 0xc04199d5 ;
+ pattern_4[0][5] = 0xdc968dc0 ;
+ pattern_4[0][6] = 0xb8ba8a33 ;
+ pattern_4[0][7] = 0x35e4327f ;
+
+ pattern_4[1][0] = 0xae37c049 ;
+ pattern_4[1][1] = 0xd2bc592c ;
+ pattern_4[1][2] = 0xf888b50b ;
+ pattern_4[1][3] = 0x632debe5 ;
+ pattern_4[1][4] = 0x3fbe99d5 ;
+ pattern_4[1][5] = 0x23698dc0 ;
+ pattern_4[1][6] = 0x47458a33 ;
+ pattern_4[1][7] = 0xca1b327f ;
+
+ pattern_4[2][0] = 0x51373f49 ;
+ pattern_4[2][1] = 0x2dbca62c ;
+ pattern_4[2][2] = 0x07884a0b ;
+ pattern_4[2][3] = 0x9c2d14e5 ;
+ pattern_4[2][4] = 0xc0be66d5 ;
+ pattern_4[2][5] = 0xdc6972c0 ;
+ pattern_4[2][6] = 0xb8457533 ;
+ pattern_4[2][7] = 0x351bcd7f ;
+
+
+ pattern_4[3][0] = 0x51c8c049 ;
+ pattern_4[3][1] = 0x2d43592c ;
+ pattern_4[3][2] = 0x0777b50b ;
+ pattern_4[3][3] = 0x9cd2ebe5 ;
+ pattern_4[3][4] = 0xc04199d5 ;
+ pattern_4[3][5] = 0xdc968dc0 ;
+ pattern_4[3][6] = 0xb8ba8a33 ;
+ pattern_4[3][7] = 0x35e4327f ;
+
+ pattern_5[0][0] = 0xaec9c149 ;
+ pattern_5[0][1] = 0xd243592c ;
+ pattern_5[0][2] = 0xf877b50b ;
+ pattern_5[0][3] = 0x63d2ebe5 ;
+ pattern_5[0][4] = 0x3f439bd5 ;
+ pattern_5[0][5] = 0x23968dc0 ;
+ pattern_5[0][6] = 0x47ba8a33 ;
+ pattern_5[0][7] = 0xcae4327f ;
+ pattern_5[1][0] = 0xaeccc449 ;
+ pattern_5[1][1] = 0xd243592c ;
+ pattern_5[1][2] = 0xf877b50b ;
+ pattern_5[1][3] = 0x63d2ebe5 ;
+ pattern_5[1][4] = 0x3f4991d5 ;
+ pattern_5[1][5] = 0x23968dc0 ;
+ pattern_5[1][6] = 0x47ba8a33 ;
+ pattern_5[1][7] = 0xcae4327f ;
+ pattern_5[2][0] = 0xaed8d049 ;
+ pattern_5[2][1] = 0xd243592c ;
+ pattern_5[2][2] = 0xf877b50b ;
+ pattern_5[2][3] = 0x63d2ebe5 ;
+ pattern_5[2][4] = 0x3f61b9d5 ;
+ pattern_5[2][5] = 0x23968dc0 ;
+ pattern_5[2][6] = 0x47ba8a33 ;
+ pattern_5[2][7] = 0xcae4327f ;
+ pattern_5[3][0] = 0xae888049 ;
+ pattern_5[3][1] = 0xd243592c ;
+ pattern_5[3][2] = 0xf877b50b ;
+ pattern_5[3][3] = 0x63d2ebe5 ;
+ pattern_5[3][4] = 0x3fc119d5 ;
+ pattern_5[3][5] = 0x23968dc0 ;
+ pattern_5[3][6] = 0x47ba8a33 ;
+ pattern_5[3][7] = 0xcae4327f ;
+
+ pattern_6[0][0] = 0xaec93f49 ;
+ pattern_6[0][1] = 0xd243a62c ;
+ pattern_6[0][2] = 0xf8774a0b ;
+ pattern_6[0][3] = 0x63d214e5 ;
+ pattern_6[0][4] = 0x3f4366d5 ;
+ pattern_6[0][5] = 0x239672c0 ;
+ pattern_6[0][6] = 0x47ba7533 ;
+ pattern_6[0][7] = 0xcae4cd7f ;
+ pattern_6[1][0] = 0xaecc3f49 ;
+ pattern_6[1][1] = 0xd243a62c ;
+ pattern_6[1][2] = 0xf8774a0b ;
+ pattern_6[1][3] = 0x63d214e5 ;
+ pattern_6[1][4] = 0x3f4966d5 ;
+ pattern_6[1][5] = 0x239672c0 ;
+ pattern_6[1][6] = 0x47ba7533 ;
+ pattern_6[1][7] = 0xcae4cd7f ;
+ pattern_6[2][0] = 0xaed83f49 ;
+ pattern_6[2][1] = 0xd243a62c ;
+ pattern_6[2][2] = 0xf8774a0b ;
+ pattern_6[2][3] = 0x63d214e5 ;
+ pattern_6[2][4] = 0x3f6166d5 ;
+ pattern_6[2][5] = 0x239672c0 ;
+ pattern_6[2][6] = 0x47ba7533 ;
+ pattern_6[2][7] = 0xcae4cd7f ;
+ pattern_6[3][0] = 0xae883f49 ;
+ pattern_6[3][1] = 0xd243a62c ;
+ pattern_6[3][2] = 0xf8774a0b ;
+ pattern_6[3][3] = 0x63d214e5 ;
+ pattern_6[3][4] = 0x3fc166d5 ;
+ pattern_6[3][5] = 0x239672c0 ;
+ pattern_6[3][6] = 0x47ba7533 ;
+ pattern_6[3][7] = 0xcae4cd7f ;
+ */
+ //*/
+ //*/
+ start_addr=0x10000000;
+ unsigned int test_size = 0x20;
+ unsigned int test_addr;
+ unsigned int temp_i=0;
+ unsigned int temp_k=0;
+ unsigned int pattern_o[8];
+ unsigned int pattern_d[8];
+ {
+ // if(lflag)
+ // loop = 888;
+
+ //if(old_pattern_flag==1)
+ {
+
+ printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size);
+
+ /*
+ for ((temp_k=0);(temp_k<4);(temp_k++)) {
+ {
+
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+ flush_dcache_range(start_addr,start_addr + test_size);
+
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]);
+ //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ //printf("\n0x%08x",pattern_5[temp_k][temp_i]);
+ if (pattern_o[temp_i] != pattern_5[temp_k][temp_i])
+ {error_count++;
+ printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]);
+ }
+ }
+ }
+ }
+ */
+ //if(pattern_flag1==1)
+ {
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
+ // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
+ if ((pattern_o[temp_i]) != (des_pattern(temp_i,1,temp_k,temp_i)))
+ {error_count++;
+ // printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]);
+ printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,1,temp_k,temp_i),pattern_1[temp_k][temp_i]);
+ }
+
+
+ }
+ }
+ }
+
+ for ((temp_k=0);(temp_k<4);(temp_k++))
+ {
+ {
+ ddr_udelay(10000);
+ for ((temp_i=0);(temp_i<8);(temp_i++))
+ {
+ test_addr=start_addr+(temp_i<<2);
+ *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i];
+ // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d]
+ //des[temp_i]^pattern_2[temp_k][temp_i]
+ }
+ // _clean_dcache_addr(0x10000000);
+#ifdef DDR_PREFETCH_CACHE
+ flush_dcache_range(start_addr,start_addr + test_size);
+#endif
+ for ((temp_i=0);(temp_i<8);(temp_i++)) {
+ test_addr=start_addr+(temp_i<<2);
+ pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr));
+ // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]);
+ // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i]));
+ // printf("\n0x%08x",pattern_4[temp_k][temp_i]);
+ pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i]));
+ if ((des_xor_pattern((des[temp_i]),des_inv_pattern(temp_i,1,temp_k,temp_i))) != pattern_d[temp_i])
+ {error_count++;
+ printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",
+ pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_1[temp_k][temp_i]),pattern_d[temp_i]);
+ }
+
+ }
+ }
+ }
+
+ }
+ }
+
+ printf("\Error count==0x%08x", error_count);
+ printf("\n \n");
+ }
+ if (error_count)
+ return 1;
+ else
+ return 0;
+}
+
+#endif
+
+static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+ //#define ddr_pattern_loop 32
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ switch (i)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ // case 30:
+ *(p+i) = TDATA32F;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ // case 22:
+ *(p+i) = 0;
+ break;
+ case DDR_PATTERN_LOOP_1+0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_1+2:
+ case DDR_PATTERN_LOOP_1+3:
+ case DDR_PATTERN_LOOP_1+8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_1+10:
+ case DDR_PATTERN_LOOP_1+11:
+ case DDR_PATTERN_LOOP_1+16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_1+18:
+ case DDR_PATTERN_LOOP_1+19:
+ case DDR_PATTERN_LOOP_1+24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_1+26:
+ case DDR_PATTERN_LOOP_1+27:
+ // case 30:
+ *(p+i) = TDATA32A;
+ break;
+ case DDR_PATTERN_LOOP_1+4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_1+6:
+ case DDR_PATTERN_LOOP_1+7:
+ case DDR_PATTERN_LOOP_1+12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_1+14:
+ case DDR_PATTERN_LOOP_1+15:
+ case DDR_PATTERN_LOOP_1+20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_1+22:
+ case DDR_PATTERN_LOOP_1+23:
+ case DDR_PATTERN_LOOP_1+28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_1+30:
+ case DDR_PATTERN_LOOP_1+31:
+ *(p+i) = TDATA325;
+
+
+ break;
+ case DDR_PATTERN_LOOP_2+0:
+ case DDR_PATTERN_LOOP_2+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_2+3:
+ *(p+i) =0xfe01fe01;
+ break;
+ case DDR_PATTERN_LOOP_2+4:
+ case DDR_PATTERN_LOOP_2+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_2+7:
+ *(p+i) =0xfd02fd02;
+ break;
+ case DDR_PATTERN_LOOP_2+8:
+ case DDR_PATTERN_LOOP_2+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_2+11:
+ *(p+i) =0xfb04fb04;
+ break;
+ case DDR_PATTERN_LOOP_2+12:
+ case DDR_PATTERN_LOOP_2+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_2+15:
+ *(p+i) =0xf708f708;
+ break;
+ case DDR_PATTERN_LOOP_2+16:
+ case DDR_PATTERN_LOOP_2+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_2+19:
+ *(p+i) =0xef10ef10;
+ break;
+ case DDR_PATTERN_LOOP_2+20:
+ case DDR_PATTERN_LOOP_2+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_2+23:
+ *(p+i) =0xdf20df20;
+ break;
+ case DDR_PATTERN_LOOP_2+24:
+ case DDR_PATTERN_LOOP_2+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_2+27:
+ *(p+i) =0xbf40bf40;
+ break;
+ case DDR_PATTERN_LOOP_2+28:
+ case DDR_PATTERN_LOOP_2+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_2+31:
+ *(p+i) =0x7f807f80;
+ break;
+ case DDR_PATTERN_LOOP_3+0:
+ case DDR_PATTERN_LOOP_3+1:
+ case DDR_PATTERN_LOOP_3+2:
+ case DDR_PATTERN_LOOP_3+3:
+ *(p+i) =0x00000100;
+ break;
+ case DDR_PATTERN_LOOP_3+4:
+ case DDR_PATTERN_LOOP_3+5:
+ case DDR_PATTERN_LOOP_3+6:
+ case DDR_PATTERN_LOOP_3+7:
+ *(p+i) =0x00000200;
+ break;
+ case DDR_PATTERN_LOOP_3+8:
+ case DDR_PATTERN_LOOP_3+9:
+ case DDR_PATTERN_LOOP_3+10:
+ case DDR_PATTERN_LOOP_3+11:
+ *(p+i) =0x00000400;
+ break;
+ case DDR_PATTERN_LOOP_3+12:
+ case DDR_PATTERN_LOOP_3+13:
+ case DDR_PATTERN_LOOP_3+14:
+ case DDR_PATTERN_LOOP_3+15:
+ *(p+i) =0x00000800;
+ break;
+ case DDR_PATTERN_LOOP_3+16:
+ case DDR_PATTERN_LOOP_3+17:
+ case DDR_PATTERN_LOOP_3+18:
+ case DDR_PATTERN_LOOP_3+19:
+ *(p+i) =0x00001000;
+ break;
+ case DDR_PATTERN_LOOP_3+20:
+ case DDR_PATTERN_LOOP_3+21:
+ case DDR_PATTERN_LOOP_3+22:
+ case DDR_PATTERN_LOOP_3+23:
+ *(p+i) =0x00002000;
+ break;
+ case DDR_PATTERN_LOOP_3+24:
+ case DDR_PATTERN_LOOP_3+25:
+ case DDR_PATTERN_LOOP_3+26:
+ case DDR_PATTERN_LOOP_3+27:
+ *(p+i) =0x00004000;
+ break;
+ case DDR_PATTERN_LOOP_3+28:
+ case DDR_PATTERN_LOOP_3+29:
+ case DDR_PATTERN_LOOP_3+30:
+ case DDR_PATTERN_LOOP_3+31:
+ *(p+i) =0x00008000;
+ break;
+
+
+ }
+ }
+
+ if (m_len >( 128*4))
+ {
+ m_len -=( 128*4);
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+ //#define ddr_pattern_loop 32
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+
+ switch (i)
+ {
+
+ case 0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_3+3:
+ *(p+i) = 0xfe01fe01;
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_3+7:
+ *(p+i) = 0xfd02fd02;
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_3+11:
+ *(p+i) = 0xfb04fb04;
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_3+15:
+ *(p+i) = 0xf708f708;
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_3+19:
+ *(p+i) = 0xef10ef10;
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_3+23:
+ *(p+i) = 0xdf20df20;
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_3+27:
+ *(p+i) = 0xbf40bf40;
+ break;
+
+ case 28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_3+31:
+ *(p+i) = 0x7f807f80;
+ break;
+
+
+ default:
+
+ *(p+i) = 0xff00ff00;
+ break;
+
+ break;
+
+
+ }
+ }
+
+ if (m_len >( 128*4))
+ {
+ m_len -=( 128*4);
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+
+ switch (i)
+ {
+
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ // case 30:
+ // *(p+i) = TDATA32F;
+ if (*(p+i) != TDATA32F)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F);
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ // case 22:
+ // *(p+i) = 0;
+ if (*(p+i) != 0)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0);
+ break;}
+ break;
+ case DDR_PATTERN_LOOP_1+0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_1+2:
+ case DDR_PATTERN_LOOP_1+3:
+ case DDR_PATTERN_LOOP_1+8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_1+10:
+ case DDR_PATTERN_LOOP_1+11:
+ case DDR_PATTERN_LOOP_1+16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_1+18:
+ case DDR_PATTERN_LOOP_1+19:
+ case DDR_PATTERN_LOOP_1+24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_1+26:
+ case DDR_PATTERN_LOOP_1+27:
+ // case 30:
+ // *(p+i) = TDATA32A;
+ if (*(p+i) != TDATA32A)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_1+4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_1+6:
+ case DDR_PATTERN_LOOP_1+7:
+ case DDR_PATTERN_LOOP_1+12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_1+14:
+ case DDR_PATTERN_LOOP_1+15:
+ case DDR_PATTERN_LOOP_1+20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_1+22:
+ case DDR_PATTERN_LOOP_1+23:
+ case DDR_PATTERN_LOOP_1+28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_1+30:
+ case DDR_PATTERN_LOOP_1+31:
+ // *(p+i) = TDATA325;
+ if (*(p+i) != TDATA325)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+0:
+ case DDR_PATTERN_LOOP_2+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_2+3:
+ // *(p+i) =0xfe01fe01;
+ if (*(p+i) !=0xfe01fe01)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+4:
+ case DDR_PATTERN_LOOP_2+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_2+7:
+ // *(p+i) =0xfd02fd02;
+ if (*(p+i) != 0xfd02fd02)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+8:
+ case DDR_PATTERN_LOOP_2+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_2+11:
+ // *(p+i) =0xfb04fb04;
+ if (*(p+i) != 0xfb04fb04)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+12:
+ case DDR_PATTERN_LOOP_2+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_2+15:
+ // *(p+i) =0xf7b08f708;
+ if (*(p+i) != 0xf708f708)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+16:
+ case DDR_PATTERN_LOOP_2+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_2+19:
+ // *(p+i) =0xef10ef10;
+ if (*(p+i) != 0xef10ef10)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+20:
+ case DDR_PATTERN_LOOP_2+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_2+23:
+ // *(p+i) =0xdf20df20;
+ if (*(p+i) != 0xdf20df20)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+24:
+ case DDR_PATTERN_LOOP_2+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_2+27:
+ // *(p+i) =0xbf40bf40;
+ if (*(p+i) != 0xbf40bf40)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+28:
+ case DDR_PATTERN_LOOP_2+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_2+31:
+ // *(p+i) =0x7f807f80;
+ if (*(p+i) != 0x7f807f80)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
+ break;
+
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+0:
+ case DDR_PATTERN_LOOP_3+1:
+ case DDR_PATTERN_LOOP_3+2:
+ case DDR_PATTERN_LOOP_3+3:
+ // *(p+i) =0x00000100;
+ if (*(p+i) != 0x00000100)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000100);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+4:
+ case DDR_PATTERN_LOOP_3+5:
+ case DDR_PATTERN_LOOP_3+6:
+ case DDR_PATTERN_LOOP_3+7:
+ // *(p+i) =0x00000100;
+ if (*(p+i) != 0x00000200)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000200);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+8:
+ case DDR_PATTERN_LOOP_3+9:
+ case DDR_PATTERN_LOOP_3+10:
+ case DDR_PATTERN_LOOP_3+11:
+ // *(p+i) =0x00000100;
+ if (*(p+i) != 0x00000400)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000400);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+12:
+ case DDR_PATTERN_LOOP_3+13:
+ case DDR_PATTERN_LOOP_3+14:
+ case DDR_PATTERN_LOOP_3+15:
+ // *(p+i) =0x00000100;
+ if (*(p+i) != 0x00000800)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00000800);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+16:
+ case DDR_PATTERN_LOOP_3+17:
+ case DDR_PATTERN_LOOP_3+18:
+ case DDR_PATTERN_LOOP_3+19:
+ // *(p+i) =0xfffffeff;
+ if (*(p+i) != 0x00001000)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00001000);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+20:
+ case DDR_PATTERN_LOOP_3+21:
+ case DDR_PATTERN_LOOP_3+22:
+ case DDR_PATTERN_LOOP_3+23:
+ // *(p+i) =0xfffffeff;
+ if (*(p+i) != 0x00002000)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00002000);
+
+ } break;
+ case DDR_PATTERN_LOOP_3+24:
+ case DDR_PATTERN_LOOP_3+25:
+ case DDR_PATTERN_LOOP_3+26:
+ case DDR_PATTERN_LOOP_3+27:
+ // *(p+i) =0xfffffeff;
+ if (*(p+i) != 0x00004000)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00004000);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3+28:
+ case DDR_PATTERN_LOOP_3+29:
+ case DDR_PATTERN_LOOP_3+30:
+ case DDR_PATTERN_LOOP_3+31:
+ // *(p+i) =0xfffffeff;
+ if (*(p+i) != 0x00008000)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x00008000);
+ break;
+ }
+ break;
+
+
+
+ }
+ }
+
+ if (m_len > 128*4)
+ {
+ m_len -= 128*4;
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+//*/
+static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+
+ switch (i)
+ {
+ case 0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_3+3:
+ // *(p+i) = 0xfe01fe01;
+ if (*(p+i) != 0xfe01fe01)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfe01fe01);
+ break;
+ }
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_3+7:
+ // *(p+i) = 0xfd02fd02;
+ if (*(p+i) != 0xfd02fd02)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfd02fd02);
+ break;
+ }
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_3+11:
+ // *(p+i) = 0xfb04fb04;
+ if (*(p+i) != 0xfb04fb04)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xfb04fb04);
+ break;
+ }
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_3+15:
+ // *(p+i) = 0xf708f708;
+ if (*(p+i) != 0xf708f708)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xf708f708);
+ break;
+ }
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_3+19:
+ // *(p+i) = 0xef10ef10;
+ if (*(p+i) != 0xef10ef10)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xef10ef10);
+ break;
+ }
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_3+23:
+ // *(p+i) = 0xdf20df20;
+ if (*(p+i) != 0xdf20df20)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xdf20df20);
+ break;
+ }
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_3+27:
+ // *(p+i) = 0xbf40bf40;
+ if (*(p+i) != 0xbf40bf40)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xbf40bf40);
+ break;
+ }
+ break;
+ case 28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_3+31:
+ // *(p+i) = 0x7f807f80;
+ if (*(p+i) != 0x7f807f80)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0x7f807f80);
+ break;
+ }
+ break;
+
+
+ default:
+
+ // *(p+i) = 0xff00ff00;
+ if (*(p+i) != 0xff00ff00)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0xff00ff00);
+ break;
+ }
+ break;
+
+ break;
+
+
+ }
+ }
+
+ if (m_len > 128*4)
+ {
+ m_len -= 128*4;
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+ //#define ddr_pattern_loop 32
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ switch (i)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ // case 30:
+ *(p+i) = ~TDATA32F;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ // case 22:
+ *(p+i) = ~0;
+ break;
+ case DDR_PATTERN_LOOP_1+0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_1+2:
+ case DDR_PATTERN_LOOP_1+3:
+ case DDR_PATTERN_LOOP_1+8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_1+10:
+ case DDR_PATTERN_LOOP_1+11:
+ case DDR_PATTERN_LOOP_1+16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_1+18:
+ case DDR_PATTERN_LOOP_1+19:
+ case DDR_PATTERN_LOOP_1+24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_1+26:
+ case DDR_PATTERN_LOOP_1+27:
+ // case 30:
+ *(p+i) = ~TDATA32A;
+ break;
+ case DDR_PATTERN_LOOP_1+4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_1+6:
+ case DDR_PATTERN_LOOP_1+7:
+ case DDR_PATTERN_LOOP_1+12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_1+14:
+ case DDR_PATTERN_LOOP_1+15:
+ case DDR_PATTERN_LOOP_1+20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_1+22:
+ case DDR_PATTERN_LOOP_1+23:
+ case DDR_PATTERN_LOOP_1+28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_1+30:
+ case DDR_PATTERN_LOOP_1+31:
+ *(p+i) =~TDATA325;
+
+
+ break;
+ case DDR_PATTERN_LOOP_2+0:
+ case DDR_PATTERN_LOOP_2+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_2+3:
+ *(p+i) =~0xfe01fe01;
+ break;
+ case DDR_PATTERN_LOOP_2+4:
+ case DDR_PATTERN_LOOP_2+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_2+7:
+ *(p+i) =~0xfd02fd02;
+ break;
+ case DDR_PATTERN_LOOP_2+8:
+ case DDR_PATTERN_LOOP_2+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_2+11:
+ *(p+i) =~0xfb04fb04;
+ break;
+ case DDR_PATTERN_LOOP_2+12:
+ case DDR_PATTERN_LOOP_2+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_2+15:
+ *(p+i) =~0xf708f708;
+ break;
+ case DDR_PATTERN_LOOP_2+16:
+ case DDR_PATTERN_LOOP_2+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_2+19:
+ *(p+i) =~0xef10ef10;
+ break;
+ case DDR_PATTERN_LOOP_2+20:
+ case DDR_PATTERN_LOOP_2+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_2+23:
+ *(p+i) =~0xdf20df20;
+ break;
+ case DDR_PATTERN_LOOP_2+24:
+ case DDR_PATTERN_LOOP_2+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_2+27:
+ *(p+i) =~0xbf40bf40;
+ break;
+ case DDR_PATTERN_LOOP_2+28:
+ case DDR_PATTERN_LOOP_2+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_2+31:
+ *(p+i) =~0x7f807f80;
+ break;
+ case DDR_PATTERN_LOOP_3+0:
+ case DDR_PATTERN_LOOP_3+1:
+ case DDR_PATTERN_LOOP_3+2:
+ case DDR_PATTERN_LOOP_3+3:
+ *(p+i) =~0x00000100;
+ break;
+ case DDR_PATTERN_LOOP_3+4:
+ case DDR_PATTERN_LOOP_3+5:
+ case DDR_PATTERN_LOOP_3+6:
+ case DDR_PATTERN_LOOP_3+7:
+ *(p+i) =~0x00000200;
+ break;
+ case DDR_PATTERN_LOOP_3+8:
+ case DDR_PATTERN_LOOP_3+9:
+ case DDR_PATTERN_LOOP_3+10:
+ case DDR_PATTERN_LOOP_3+11:
+ *(p+i) =~0x00000400;
+ break;
+ case DDR_PATTERN_LOOP_3+12:
+ case DDR_PATTERN_LOOP_3+13:
+ case DDR_PATTERN_LOOP_3+14:
+ case DDR_PATTERN_LOOP_3+15:
+ *(p+i) =~0x00000800;
+ break;
+ case DDR_PATTERN_LOOP_3+16:
+ case DDR_PATTERN_LOOP_3+17:
+ case DDR_PATTERN_LOOP_3+18:
+ case DDR_PATTERN_LOOP_3+19:
+ *(p+i) =~0x00001000;
+ break;
+ case DDR_PATTERN_LOOP_3+20:
+ case DDR_PATTERN_LOOP_3+21:
+ case DDR_PATTERN_LOOP_3+22:
+ case DDR_PATTERN_LOOP_3+23:
+ *(p+i) =~0x00002000;
+ break;
+ case DDR_PATTERN_LOOP_3+24:
+ case DDR_PATTERN_LOOP_3+25:
+ case DDR_PATTERN_LOOP_3+26:
+ case DDR_PATTERN_LOOP_3+27:
+ *(p+i) =~0x00004000;
+ break;
+ case DDR_PATTERN_LOOP_3+28:
+ case DDR_PATTERN_LOOP_3+29:
+ case DDR_PATTERN_LOOP_3+30:
+ case DDR_PATTERN_LOOP_3+31:
+ *(p+i) =~0x00008000;
+ break;
+
+
+ }
+ }
+
+ if (m_len >( 128*4))
+ {
+ m_len -=( 128*4);
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+
+static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+ //#define ddr_pattern_loop 32
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+
+ switch (i)
+ {
+ case 0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_3+3:
+ *(p+i) = ~0xfe01fe01;
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_3+7:
+ *(p+i) = ~0xfd02fd02;
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_2+10:
+ case DDR_PATTERN_LOOP_3+11:
+ *(p+i) = ~0xfb04fb04;
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_2+14:
+ case DDR_PATTERN_LOOP_3+15:
+ *(p+i) = ~0xf708f708;
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_2+18:
+ case DDR_PATTERN_LOOP_3+19:
+ *(p+i) = ~0xef10ef10;
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_2+22:
+ case DDR_PATTERN_LOOP_3+23:
+ *(p+i) = ~0xdf20df20;
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_2+26:
+ case DDR_PATTERN_LOOP_3+27:
+ *(p+i) =~0xbf40bf40;
+ break;
+ case 28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_2+30:
+ case DDR_PATTERN_LOOP_3+31:
+ *(p+i) = ~0x7f807f80;
+ break;
+
+
+ default:
+
+ *(p+i) = ~0xff00ff00;
+ break;
+
+ break;
+
+
+ }
+ }
+
+ if (m_len >( 128*4))
+ {
+ m_len -=( 128*4);
+ p += 32*4;
+ }
+ else
+ {
+ p += (m_len>>2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ // unsigned int i, j, n;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = ( unsigned int *)buff;
+
+ while (m_len)
+ {
+ // for(j=0;j<32;j++)
+ {
+ if (m_len >= 128*4)
+ n = 32*4;
+ else
+ n = m_len>>2;
+
+ for (i = 0; i < n; i++)
+ {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p) ;
+#endif
+ if ((error_outof_count_flag) && (error_count))
+ {
+ printf("Error data out of count");
+ m_len=0;
+ break;
+ }
+ switch (i)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ // case 30:
+ // *(p+i) = TDATA32F;
+ if (*(p+i) !=~TDATA32F)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA32F);
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ // case 22:
+ // *(p+i) = 0;
+ if (*(p+i) !=~0)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1+0:
+ case DDR_PATTERN_LOOP_1+1:
+ case DDR_PATTERN_LOOP_1+2:
+ case DDR_PATTERN_LOOP_1+3:
+ case DDR_PATTERN_LOOP_1+8:
+ case DDR_PATTERN_LOOP_1+9:
+ case DDR_PATTERN_LOOP_1+10:
+ case DDR_PATTERN_LOOP_1+11:
+ case DDR_PATTERN_LOOP_1+16:
+ case DDR_PATTERN_LOOP_1+17:
+ case DDR_PATTERN_LOOP_1+18:
+ case DDR_PATTERN_LOOP_1+19:
+ case DDR_PATTERN_LOOP_1+24:
+ case DDR_PATTERN_LOOP_1+25:
+ case DDR_PATTERN_LOOP_1+26:
+ case DDR_PATTERN_LOOP_1+27:
+ // case 30:
+ // *(p+i) = TDATA32A;
+ if (*(p+i) != ~TDATA32A)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),~TDATA32A);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1+4:
+ case DDR_PATTERN_LOOP_1+5:
+ case DDR_PATTERN_LOOP_1+6:
+ case DDR_PATTERN_LOOP_1+7:
+ case DDR_PATTERN_LOOP_1+12:
+ case DDR_PATTERN_LOOP_1+13:
+ case DDR_PATTERN_LOOP_1+14:
+ case DDR_PATTERN_LOOP_1+15:
+ case DDR_PATTERN_LOOP_1+20:
+ case DDR_PATTERN_LOOP_1+21:
+ case DDR_PATTERN_LOOP_1+22:
+ case DDR_PATTERN_LOOP_1+23:
+ case DDR_PATTERN_LOOP_1+28:
+ case DDR_PATTERN_LOOP_1+29:
+ case DDR_PATTERN_LOOP_1+30:
+ case DDR_PATTERN_LOOP_1+31:
+ // *(p+i) = TDATA325;
+ if (*(p+i) != ~TDATA325)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~TDATA325);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+0:
+ case DDR_PATTERN_LOOP_2+1:
+ case DDR_PATTERN_LOOP_2+2:
+ case DDR_PATTERN_LOOP_2+3:
+ // *(p+i) =0xfe01fe01;
+ if (*(p+i) !=~0xfe01fe01)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~0xfe01fe01);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2+4:
+ case DDR_PATTERN_LOOP_2+5:
+ case DDR_PATTERN_LOOP_2+6:
+ case DDR_PATTERN_LOOP_2+7:
+ // *(p+i) =0xfd02fd02;
+ if (*(p+i) != ~0xfd02fd02)
+ {error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~