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authorHakjoo Kim <ruppi.kim@hardkernel.com>2013-03-22 14:18:54 +0400
committerHakjoo Kim <ruppi.kim@hardkernel.com>2013-03-22 14:32:33 +0400
commit681af1e734c111c104d99d821a03a26e30ca6405 (patch)
tree3ec84272540b066a32c6028ec8d5354eea3adfba
parent250ef029844be2cb98635f265359396866d1749f (diff)
downloadu-boot-681af1e734c111c104d99d821a03a26e30ca6405.tar.xz
Merge modified ones by hardkernel and samsung semiconductor based on v210.12
-rwxr-xr-xCOPYING.txt349
-rwxr-xr-xMAKEALL3
-rw-r--r--Makefile28
-rw-r--r--arch/arm/config.mk3
-rw-r--r--arch/arm/cpu/arm11/Makefile50
-rw-r--r--arch/arm/cpu/arm11/cpu.c159
-rw-r--r--arch/arm/cpu/arm11/s5p6450/Makefile56
-rw-r--r--arch/arm/cpu/arm11/s5p6450/clock.c223
-rw-r--r--arch/arm/cpu/arm11/s5p6450/irom_copy.c132
-rw-r--r--arch/arm/cpu/arm11/s5p6450/movi_partition.c125
-rw-r--r--arch/arm/cpu/arm11/s5p6450/reset.c33
-rw-r--r--arch/arm/cpu/arm11/s5p6450/setup_hsmmc.c209
-rw-r--r--arch/arm/cpu/arm11/s5p6450/sys_info.c58
-rw-r--r--arch/arm/cpu/arm11/s5p6450/timer.c202
-rw-r--r--arch/arm/cpu/arm11/start.S440
-rw-r--r--arch/arm/cpu/armv7/config.mk2
-rw-r--r--arch/arm/cpu/armv7/cpu.c6
-rw-r--r--arch/arm/cpu/armv7/exynos/Makefile79
-rw-r--r--arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.c182
-rw-r--r--arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.h113
-rw-r--r--arch/arm/cpu/armv7/exynos/ace_sha1.c129
-rw-r--r--arch/arm/cpu/armv7/exynos/clock.c86
-rw-r--r--arch/arm/cpu/armv7/exynos/gpio.c5377
-rw-r--r--arch/arm/cpu/armv7/exynos/i2c.c1096
-rw-r--r--arch/arm/cpu/armv7/exynos/irom_copy.c161
-rw-r--r--arch/arm/cpu/armv7/exynos/movi_partition.c116
-rw-r--r--arch/arm/cpu/armv7/exynos/nand.c1064
-rw-r--r--arch/arm/cpu/armv7/exynos/nand_cp.c145
-rw-r--r--arch/arm/cpu/armv7/exynos/nand_write_bl.c286
-rw-r--r--arch/arm/cpu/armv7/exynos/onenand_cp.c174
-rw-r--r--arch/arm/cpu/armv7/exynos/pmic.c705
-rw-r--r--arch/arm/cpu/armv7/exynos/pmic_hkdk4212.c286
-rw-r--r--arch/arm/cpu/armv7/exynos/reset.c50
-rw-r--r--arch/arm/cpu/armv7/exynos/security_check.c55
-rw-r--r--arch/arm/cpu/armv7/exynos/setup_hsmmc.c247
-rw-r--r--arch/arm/cpu/armv7/exynos/sys_info.c75
-rw-r--r--arch/arm/cpu/armv7/exynos/uboot_sb21.h102
-rw-r--r--arch/arm/cpu/armv7/s5p-common/Makefile1
-rw-r--r--arch/arm/cpu/armv7/s5p-common/timer.c15
-rw-r--r--arch/arm/cpu/armv7/s5pv210/Makefile72
-rw-r--r--arch/arm/cpu/armv7/s5pv210/ace_sha1.c103
-rw-r--r--arch/arm/cpu/armv7/s5pv210/clock.c217
-rw-r--r--arch/arm/cpu/armv7/s5pv210/irom_copy.c219
-rw-r--r--arch/arm/cpu/armv7/s5pv210/movi_partition.c126
-rw-r--r--arch/arm/cpu/armv7/s5pv210/onenand_cp.c174
-rw-r--r--arch/arm/cpu/armv7/s5pv210/pmic.c243
-rw-r--r--arch/arm/cpu/armv7/s5pv210/reset.c34
-rw-r--r--arch/arm/cpu/armv7/s5pv210/secure.h70
-rw-r--r--arch/arm/cpu/armv7/s5pv210/secure_boot.c168
-rw-r--r--arch/arm/cpu/armv7/s5pv210/security_check.c41
-rw-r--r--arch/arm/cpu/armv7/s5pv210/setup_hsmmc.c186
-rw-r--r--arch/arm/cpu/armv7/s5pv310/Makefile69
-rw-r--r--arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.c182
-rw-r--r--arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.h113
-rw-r--r--arch/arm/cpu/armv7/s5pv310/ace_sha1.c129
-rw-r--r--arch/arm/cpu/armv7/s5pv310/clock.c72
-rw-r--r--arch/arm/cpu/armv7/s5pv310/gpio.c5377
-rw-r--r--arch/arm/cpu/armv7/s5pv310/i2c.c1096
-rw-r--r--arch/arm/cpu/armv7/s5pv310/irom_copy.c122
-rw-r--r--arch/arm/cpu/armv7/s5pv310/movi_partition.c112
-rw-r--r--arch/arm/cpu/armv7/s5pv310/nand.c1064
-rw-r--r--arch/arm/cpu/armv7/s5pv310/nand_cp.c145
-rw-r--r--arch/arm/cpu/armv7/s5pv310/nand_write_bl.c286
-rw-r--r--arch/arm/cpu/armv7/s5pv310/onenand_cp.c174
-rw-r--r--arch/arm/cpu/armv7/s5pv310/pmic.c484
-rw-r--r--arch/arm/cpu/armv7/s5pv310/reset.c34
-rw-r--r--arch/arm/cpu/armv7/s5pv310/security_check.c47
-rw-r--r--arch/arm/cpu/armv7/s5pv310/setup_hsmmc.c192
-rw-r--r--arch/arm/cpu/armv7/s5pv310/sys_info.c63
-rw-r--r--arch/arm/cpu/armv7/start.S20
-rw-r--r--arch/arm/include/asm/arch-exynos/ace_sfr.h501
-rw-r--r--arch/arm/include/asm/arch-exynos/ace_sha1.h47
-rw-r--r--arch/arm/include/asm/arch-exynos/clk.h39
-rw-r--r--arch/arm/include/asm/arch-exynos/clock.h94
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu.h859
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu_exynos5210.h715
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu_exynos5250_evt0.h753
-rw-r--r--arch/arm/include/asm/arch-exynos/cpu_exynos5250_evt1.h782
-rw-r--r--arch/arm/include/asm/arch-exynos/gpio.h496
-rw-r--r--arch/arm/include/asm/arch-exynos/i2c.h147
-rw-r--r--arch/arm/include/asm/arch-exynos/movi_partition.h100
-rw-r--r--arch/arm/include/asm/arch-exynos/pmic.h115
-rw-r--r--arch/arm/include/asm/arch-exynos/pmic_hkdk4212.h60
-rw-r--r--arch/arm/include/asm/arch-exynos/pwm.h55
-rw-r--r--arch/arm/include/asm/arch-exynos/s3c_hsmmc.h300
-rw-r--r--arch/arm/include/asm/arch-exynos/s5p_nand.h217
-rw-r--r--arch/arm/include/asm/arch-exynos/uart.h55
-rw-r--r--arch/arm/include/asm/arch-s5p6450/clk.h38
-rw-r--r--arch/arm/include/asm/arch-s5p6450/clock.h56
-rw-r--r--arch/arm/include/asm/arch-s5p6450/cpu.h1135
-rw-r--r--arch/arm/include/asm/arch-s5p6450/movi_partition.h113
-rw-r--r--arch/arm/include/asm/arch-s5p6450/pwm.h55
-rw-r--r--arch/arm/include/asm/arch-s5p6450/s3c_hsmmc.h282
-rw-r--r--arch/arm/include/asm/arch-s5p6450/uart.h55
-rw-r--r--arch/arm/include/asm/arch-s5pv210/clk.h39
-rw-r--r--arch/arm/include/asm/arch-s5pv210/cpu.h1240
-rw-r--r--arch/arm/include/asm/arch-s5pv210/gpio.h158
-rw-r--r--arch/arm/include/asm/arch-s5pv210/movi_partition.h106
-rw-r--r--arch/arm/include/asm/arch-s5pv210/pmic.h39
-rw-r--r--arch/arm/include/asm/arch-s5pv210/pwm.h55
-rw-r--r--arch/arm/include/asm/arch-s5pv210/s3c_hsmmc.h282
-rw-r--r--arch/arm/include/asm/arch-s5pv210/uart.h55
-rw-r--r--arch/arm/include/asm/arch-s5pv310/ace_sfr.h501
-rw-r--r--arch/arm/include/asm/arch-s5pv310/ace_sha1.h47
-rw-r--r--arch/arm/include/asm/arch-s5pv310/clk.h39
-rw-r--r--arch/arm/include/asm/arch-s5pv310/clock.h94
-rw-r--r--arch/arm/include/asm/arch-s5pv310/cpu.h735
-rw-r--r--arch/arm/include/asm/arch-s5pv310/gpio.h496
-rw-r--r--arch/arm/include/asm/arch-s5pv310/i2c.h147
-rw-r--r--arch/arm/include/asm/arch-s5pv310/movi_partition.h83
-rw-r--r--arch/arm/include/asm/arch-s5pv310/pmic.h63
-rw-r--r--arch/arm/include/asm/arch-s5pv310/pwm.h55
-rw-r--r--arch/arm/include/asm/arch-s5pv310/s3c_hsmmc.h282
-rw-r--r--arch/arm/include/asm/arch-s5pv310/s5p_nand.h217
-rw-r--r--arch/arm/include/asm/arch-s5pv310/uart.h55
-rw-r--r--arch/arm/include/asm/io.h2
-rw-r--r--arch/arm/lib/Makefile5
-rw-r--r--arch/arm/lib/board.c30
-rw-r--r--arch/arm/lib/bootm.c14
-rw-r--r--arch/arm/lib/eabi_compat.c2
-rw-r--r--board/samsung/smdk4212/Makefile64
-rw-r--r--board/samsung/smdk4212/clock_init_smdk4212.S327
-rw-r--r--board/samsung/smdk4212/config.mk13
-rw-r--r--board/samsung/smdk4212/lowlevel_init.S646
-rw-r--r--board/samsung/smdk4212/mem_init_smdk4212.S662
-rw-r--r--board/samsung/smdk4212/pmic.c726
-rw-r--r--board/samsung/smdk4212/smc.c191
-rw-r--r--board/samsung/smdk4212/smdk4212.c330
-rw-r--r--board/samsung/smdk4212/smdk4212_val.h250
-rw-r--r--board/samsung/smdk4212/smdk4412_val.h269
-rw-r--r--board/samsung/smdk4212/u-boot.lds85
-rw-r--r--board/samsung/smdk5210/Makefile58
-rw-r--r--board/samsung/smdk5210/clock_init_smdk5210.S380
-rw-r--r--board/samsung/smdk5210/config.mk12
-rw-r--r--board/samsung/smdk5210/lowlevel_init.S573
-rw-r--r--board/samsung/smdk5210/mem_init_smdk5210.S235
-rw-r--r--board/samsung/smdk5210/smdk5210.c197
-rw-r--r--board/samsung/smdk5210/smdk5210_val.h299
-rw-r--r--board/samsung/smdk5210/u-boot.lds85
-rw-r--r--board/samsung/smdk5250/Makefile68
-rw-r--r--board/samsung/smdk5250/clock_init_smdk5250.S388
-rw-r--r--board/samsung/smdk5250/clock_init_smdk5250_evt0.S375
-rw-r--r--board/samsung/smdk5250/config.mk12
-rw-r--r--board/samsung/smdk5250/dmc_init.c575
-rw-r--r--board/samsung/smdk5250/lowlevel_init.S696
-rw-r--r--board/samsung/smdk5250/mem_init_ddr3_evt0.S646
-rw-r--r--board/samsung/smdk5250/mem_init_lpddr2_evt0.S654
-rw-r--r--board/samsung/smdk5250/mem_init_lpddr3_evt0.S937
-rw-r--r--board/samsung/smdk5250/mem_init_smdk5250.S417
-rw-r--r--board/samsung/smdk5250/pmic.c688
-rw-r--r--board/samsung/smdk5250/smc.c187
-rw-r--r--board/samsung/smdk5250/smdk5250.c231
-rw-r--r--board/samsung/smdk5250/smdk5250_val_evt0.h380
-rw-r--r--board/samsung/smdk5250/smdk5250_val_evt1.h413
-rw-r--r--board/samsung/smdk5250/u-boot.lds85
-rw-r--r--board/samsung/smdk6450/Makefile57
-rw-r--r--board/samsung/smdk6450/config.mk13
-rw-r--r--board/samsung/smdk6450/lowlevel_init.S443
-rw-r--r--board/samsung/smdk6450/mem_setup.S83
-rw-r--r--board/samsung/smdk6450/smdk6450.c131
-rw-r--r--board/samsung/smdk6450/u-boot.lds85
-rw-r--r--board/samsung/smdkv210/Makefile58
-rw-r--r--board/samsung/smdkv210/config.mk13
-rw-r--r--board/samsung/smdkv210/lowlevel_init.S844
-rw-r--r--board/samsung/smdkv210/mem_setup.S623
-rw-r--r--board/samsung/smdkv210/smdkv210.c155
-rw-r--r--board/samsung/smdkv210/u-boot.lds85
-rw-r--r--board/samsung/smdkv310/Makefile57
-rw-r--r--board/samsung/smdkv310/config.mk13
-rw-r--r--board/samsung/smdkv310/lowlevel_init.S929
-rw-r--r--board/samsung/smdkv310/mem_setup.S726
-rw-r--r--board/samsung/smdkv310/smdkv310.c234
-rw-r--r--board/samsung/smdkv310/smdkv310_val.h312
-rw-r--r--board/samsung/smdkv310/u-boot.lds85
-rw-r--r--boards.cfg7
-rw-r--r--common/Makefile9
-rw-r--r--common/cmd_bdinfo.c3
-rw-r--r--common/cmd_bootm.c50
-rw-r--r--common/cmd_ext2.c88
-rw-r--r--common/cmd_fastboot.c2157
-rw-r--r--common/cmd_fat.c211
-rw-r--r--common/cmd_help.c10
-rw-r--r--common/cmd_mmc.c330
-rw-r--r--common/cmd_mmc_fdisk.c610
-rw-r--r--common/cmd_movi.c287
-rw-r--r--common/cmd_nand.c550
-rw-r--r--common/cmd_net.c4
-rw-r--r--common/cmd_nvedit.c2
-rw-r--r--common/cmd_onenand.c651
-rw-r--r--common/cmd_usbd.c137
-rw-r--r--common/cmd_usbd3.c110
-rw-r--r--common/command.c13
-rw-r--r--common/decompress_ext4.c137
-rw-r--r--common/env_auto.c600
-rw-r--r--common/env_common.c9
-rw-r--r--common/image.c13
-rw-r--r--common/serial.c4
-rw-r--r--disk/part_dos.c4
-rw-r--r--drivers/mmc/Makefile4
-rw-r--r--drivers/mmc/mmc.c1164
-rw-r--r--drivers/mmc/s3c_hsmmc.c459
-rw-r--r--drivers/mmc/s5p_mshc.c872
-rw-r--r--drivers/mtd/nand/nand_util.c653
-rw-r--r--drivers/mtd/onenand/Makefile4
-rw-r--r--drivers/mtd/onenand/onenand_base.c131
-rw-r--r--drivers/mtd/onenand/onenand_base_c110.c3368
-rw-r--r--drivers/mtd/onenand/onenand_bbt.c3
-rw-r--r--drivers/mtd/onenand/onenand_uboot.c71
-rw-r--r--drivers/net/dm9000x.c12
-rw-r--r--drivers/net/dm9000x.h2
-rw-r--r--drivers/net/smc911x.c18
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/serial_s5p.c8
-rw-r--r--drivers/usb/gadget/Makefile3
-rw-r--r--drivers/usb/gadget/fastboot-ss.c526
-rw-r--r--drivers/usb/gadget/fastboot.c468
-rw-r--r--drivers/usb/gadget/usbd-otg-hs.c2340
-rw-r--r--drivers/usb/gadget/usbd-otg-hs.h306
-rw-r--r--drivers/usb/gadget/usbd3-ss.c2446
-rw-r--r--drivers/usb/gadget/usbd3-ss.h1155
-rw-r--r--drivers/usb/host/Makefile1
-rw-r--r--drivers/usb/host/usb_ohci.c750
-rw-r--r--drivers/usb/host/usb_ohci.h397
-rw-r--r--fs/ext2/ext2fs.c1223
-rw-r--r--fs/fat/Makefile6
-rw-r--r--fs/fat/fat.c419
-rw-r--r--include/ace_sfr.h334
-rw-r--r--include/ace_sha1.h47
-rw-r--r--include/configs/smdk4212.h446
-rw-r--r--include/configs/smdk4412.h485
-rw-r--r--include/configs/smdk5210.h332
-rw-r--r--include/configs/smdk5250.h443
-rw-r--r--include/configs/smdk6450.h309
-rw-r--r--include/configs/smdkv210.h796
-rw-r--r--include/configs/smdkv310.h407
-rw-r--r--include/decompress_ext4.h44
-rw-r--r--include/ext2fs.h1
-rw-r--r--include/fastboot.h349
-rw-r--r--include/fat.h101
-rw-r--r--include/hardware.h42
-rw-r--r--include/linux/mtd/onenand.h50
-rw-r--r--include/linux/mtd/onenand_regs.h23
-rw-r--r--include/mmc.h108
-rw-r--r--include/nand.h3
-rw-r--r--include/s5p_mshc.h391
-rw-r--r--include/secure_boot.h74
-rw-r--r--lib/display_options.c17
-rwxr-xr-xmkbl2bin0 -> 8907 bytes
-rw-r--r--net/eth.c4
-rw-r--r--net/tftp.c11
-rw-r--r--sd_fuse/bl1.HardKernelbin0 -> 15360 bytes
-rw-r--r--sd_fuse/bl2.HardKernelbin0 -> 14592 bytes
-rwxr-xr-xsd_fuse/emmc_fastboot_fusing.sh18
-rwxr-xr-xsd_fuse/sd_fusing.sh52
-rw-r--r--sd_fuse/tzsw.HardKernelbin0 -> 159744 bytes
-rw-r--r--secure_boot/libsecureboot_u-boot_v21.txtbin0 -> 26900 bytes
256 files changed, 79676 insertions, 1083 deletions
diff --git a/COPYING.txt b/COPYING.txt
new file mode 100755
index 0000000000..91f12ec775
--- /dev/null
+++ b/COPYING.txt
@@ -0,0 +1,349 @@
+This software contains copyrighted software that is licensed under the GPL.
+You may obtain the complete Corresponding Source code from us for a period of three years after our last shipment of this product by sending email to:
+oss.request@samsung.com
+This offer is valid to anyone in receipt of this information.
+
+
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
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+
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+in new free programs; and that you know you can do these things.
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+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
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+you have. You must make sure that they, too, receive or can get the
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+ We protect your rights with two steps: (1) copyright the software, and
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+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
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+ GNU GENERAL PUBLIC LICENSE
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+
+ 0. This License applies to any program or other work which contains
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+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ <signature of Ty Coon>, 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
+
+
+
diff --git a/MAKEALL b/MAKEALL
index 42545659b8..6b002974ba 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -434,6 +434,9 @@ LIST_ARMV7=" \
omap4_sdp4430 \
s5p_goni \
smdkc100 \
+ smdkv210 \
+ smdkv310 \
+ smdk4212 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 90550280bd..07e75c4c47 100644
--- a/Makefile
+++ b/Makefile
@@ -183,6 +183,7 @@ OBJS := $(addprefix $(obj),$(OBJS))
LIBS = lib/libgeneric.o
LIBS += lib/lzma/liblzma.o
LIBS += lib/lzo/liblzo.o
+
LIBS += $(shell if [ -f board/$(VENDOR)/common/Makefile ]; then echo \
"board/$(VENDOR)/common/lib$(VENDOR).o"; fi)
LIBS += $(CPUDIR)/lib$(CPU).o
@@ -202,7 +203,9 @@ LIBS += drivers/bios_emulator/libatibiosemu.o
LIBS += drivers/block/libblock.o
LIBS += drivers/dma/libdma.o
LIBS += drivers/fpga/libfpga.o
+ifndef CONFIG_S5P6450
LIBS += drivers/gpio/libgpio.o
+endif
LIBS += drivers/hwmon/libhwmon.o
LIBS += drivers/i2c/libi2c.o
LIBS += drivers/input/libinput.o
@@ -256,10 +259,18 @@ endif
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
+ifeq ($(SOC),s5pv210)
+LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
ifeq ($(SOC),s5pc2xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
-
+ifeq ($(SOC),s5pv310)
+LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
+ifeq ($(SOC),exynos)
+LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
+endif
LIBS := $(addprefix $(obj),$(sort $(LIBS)))
.PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE)
@@ -277,6 +288,9 @@ else
PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc
endif
PLATFORM_LIBS += $(PLATFORM_LIBGCC)
+ifeq ($(CONFIG_SECURE_BOOT),y)
+PLATFORM_LIBS += -L ./secure_boot/ -lsecureboot_u-boot_v21
+endif
export PLATFORM_LIBS
# Special flags for CPP when processing the linker script.
@@ -333,6 +347,13 @@ $(obj)u-boot.srec: $(obj)u-boot
$(obj)u-boot.bin: $(obj)u-boot
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
$(BOARD_SIZE_CHECK)
+ifeq ($(CONFIG_S5PC210),y)
+ ./mkbl2 u-boot.bin bl2.bin 14336
+endif
+
+ifeq ($(CONFIG_CPU_EXYNOS5250),y)
+ ./mkbl2 u-boot.bin bl2.bin 14336
+endif
$(obj)u-boot.ldr: $(obj)u-boot
$(CREATE_LDR_ENV)
@@ -374,7 +395,11 @@ GEN_UBOOT = \
-Map u-boot.map -o u-boot
$(obj)u-boot: depend \
$(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
+ifeq ($(CONFIG_SECURE_BOOT),y)
+ cp ./secure_boot/libsecureboot_u-boot_v21.txt ./secure_boot/libsecureboot_u-boot_v21.a
+endif
$(GEN_UBOOT)
+
ifeq ($(CONFIG_KALLSYMS),y)
smap=`$(call SYSTEM_MAP,u-boot) | \
awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \
@@ -1226,6 +1251,7 @@ clean:
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
+ @rm -f bl2.bin
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 4e165bfda4..24f898242e 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -63,7 +63,8 @@ ifeq (,$(findstring arch/arm/lib/eabi_compat.o,$(PLATFORM_LIBS)))
PLATFORM_LIBS += $(OBJTREE)/arch/arm/lib/eabi_compat.o
endif
endif
-LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+#LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
+LDSCRIPT := $(TOPDIR)/board/samsung/$(BOARD)/u-boot.lds
# needed for relocation
ifndef CONFIG_NAND_SPL
diff --git a/arch/arm/cpu/arm11/Makefile b/arch/arm/cpu/arm11/Makefile
new file mode 100644
index 0000000000..38b5d0474b
--- /dev/null
+++ b/arch/arm/cpu/arm11/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(CPU).o
+
+START := start.o
+COBJS := cpu.o
+
+SRCS := $(START:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj), $(COBJS))
+START := $(addprefix $(obj),$(START))
+
+all: $(obj).depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c
new file mode 100644
index 0000000000..f86e915887
--- /dev/null
+++ b/arch/arm/cpu/arm11/cpu.c
@@ -0,0 +1,159 @@
+/*
+ * (C) Copyright 2004 Texas Insturments
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+
+#ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1 (void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1 (unsigned long value)
+{
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ :
+ : "r" (value)
+ : "memory");
+
+ read_p15_c1 ();
+}
+
+static void cp_delay (void)
+{
+ volatile int i;
+
+ /* Many OMAP regs need at least 2 nops */
+ for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_DC (1<<2) /* dcache off/on */
+#define C1_WB (1<<3) /* merging write buffer on/off */
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_BRANCH (1<<11) /* branch prediction off/on */
+#define C1_IC (1<<12) /* icache off/on */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+
+int cpu_init (void)
+{
+ /*
+ * setup up stacks if necessary
+ */
+#ifdef CONFIG_USE_IRQ
+ IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
+ FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+#endif
+ return 0;
+}
+
+int cleanup_before_linux (void)
+{
+ /*
+ * this function is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we turn off caches etc ...
+ */
+
+ unsigned long i;
+
+ disable_interrupts ();
+
+#ifdef CONFIG_LCD
+ {
+ extern void lcd_disable(void);
+ extern void lcd_panel_disable(void);
+
+ lcd_disable(); /* proper disable of lcd & panel */
+ lcd_panel_disable();
+ }
+#endif
+
+ /* turn off I/D-cache */
+ asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+ i &= ~(C1_DC | C1_IC);
+ asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+
+ /* flush I/D-cache */
+ i = 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both caches and flush btb */
+ asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync things */
+ return(0);
+}
+
+
+void branch_enable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ write_p15_c1 (reg | C1_BRANCH);
+}
+
+void branch_disable (void)
+{
+ ulong reg;
+
+ reg = read_p15_c1 ();
+ cp_delay ();
+ reg &= ~C1_BRANCH;
+ write_p15_c1 (reg);
+}
+
+int branch_status (void)
+{
+ return (read_p15_c1 () & C1_BRANCH) != 0;
+}
+
diff --git a/arch/arm/cpu/arm11/s5p6450/Makefile b/arch/arm/cpu/arm11/s5p6450/Makefile
new file mode 100644
index 0000000000..284950edb5
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/Makefile
@@ -0,0 +1,56 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2011 Samsung Electronics Co. Ltd
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += timer.o
+COBJS += clock.o
+COBJS += reset.o
+COBJS += irom_copy.o
+COBJS += movi_partition.o
+COBJS += setup_hsmmc.o
+COBJS += sys_info.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm11/s5p6450/clock.c b/arch/arm/cpu/arm11/s5p6450/clock.c
new file mode 100644
index 0000000000..037a9d2061
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/clock.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+
+unsigned long (*get_uart_clk)(int dev_index);
+unsigned long (*get_pwm_clk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+/* s5p6450: return pll clock frequency */
+static unsigned long s5p6450_get_pll_clk(int pllreg)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case DPLL:
+ r = readl(&clk->dpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [23:16]
+ * EPLL_CON: MIDV [23:16]
+ * HPLL_CON: MIDV [23:16]
+ */
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x3ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ freq = CONFIG_SYS_CLK_FREQ;
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5p6450: return ARM clock frequency */
+static unsigned long s5p6450_get_arm_clk(void)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div3);
+
+ /* APLL_RATIO: [2:0] */
+ apll_ratio = div & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll;
+
+ return armclk;
+}
+
+
+/* s5p6450: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = readl(&clk->div0);
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* s5p6450: return HCLKs frequency */
+static unsigned long get_hclk_sys_low(void)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long hclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int hclk_sys_ratio;
+
+ div = readl(&clk->div3);
+
+ offset = 8;
+
+ hclk_sys_ratio = (div >> offset) & 0xf;
+
+ hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+ return hclk;
+}
+
+/* s5p6450: return PCLKs frequency */
+static unsigned long get_pclk_sys(void)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int pclk_sys_ratio;
+
+ div = readl(&clk->div3);
+
+ offset = 12;
+
+ pclk_sys_ratio = (div >> offset) & 0xf;
+
+ pclk = get_hclk_sys_low() / (pclk_sys_ratio + 1);
+
+ return pclk;
+}
+
+/* s5p6450: return PCLKs frequency */
+static unsigned long get_pclk_pwm(void)
+{
+ struct s5p6450_clock *clk =
+ (struct s5p6450_clock *)samsung_get_base_clock();
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int pclk_div0;
+ unsigned int pclk_div1;
+
+ div = readl(&clk->div3);
+
+ pclk_div0 = ((div >> 16) & 0xf) + 1;
+
+ pclk_div1 = ((div >> 20) & 0xf) + 1;
+
+ pclk = get_pll_clk(MPLL) / (pclk_div0 * pclk_div1);
+
+ return pclk;
+}
+
+/* s5p6450: return peripheral clock frequency */
+static unsigned long s5p6450_get_pclk(void)
+{
+ return get_pclk_sys();
+}
+
+/* s5p6450: return uart clock frequency */
+static unsigned long s5p6450_get_uart_clk(int dev_index)
+{
+ return s5p6450_get_pclk();
+}
+
+/* s5p6450: return pwm clock frequency */
+static unsigned long s5p6450_get_pwm_clk(void)
+{
+ return get_pclk_pwm();
+}
+
+void s5p_clock_init(void)
+{
+ get_pll_clk = s5p6450_get_pll_clk;
+ get_arm_clk = s5p6450_get_arm_clk;
+
+ get_uart_clk = s5p6450_get_uart_clk;
+ get_pwm_clk = s5p6450_get_pwm_clk;
+}
+
+ulong get_APLL_CLK(void)
+{
+ return (s5p6450_get_pll_clk(APLL));
+}
+
+ulong get_MPLL_CLK(void)
+{
+ return (s5p6450_get_pll_clk(MPLL));
+}
diff --git a/arch/arm/cpu/arm11/s5p6450/irom_copy.c b/arch/arm/cpu/arm11/s5p6450/irom_copy.c
new file mode 100644
index 0000000000..3795573c5c
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/irom_copy.c
@@ -0,0 +1,132 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+
+extern ulong movi_read(int dev, ulong start, lbaint_t blkcnt, void *dst);
+extern ulong movi_write(int dev, ulong start, lbaint_t blkcnt, void *src);
+
+typedef u32 (*copy_sd_mmc_to_mem) \
+ (u32 start_block, u32 block_count, u32* dest_addr);
+
+typedef u32 (*copy_emmc43_to_mem) \
+ (u32 block_size, u32* dest_addr);
+
+typedef u32 (*copy_emmc44_to_mem) \
+ (u32 block_size, u32* dest_addr);
+
+typedef u32 (*emmc43_endbootop) \
+ (void);
+
+typedef u32 (*emmc44_endbootop) \
+ (void);
+
+#if defined(CONFIG_EVT0)
+#define COPY_MOVI_TO_MEM_FUNC (0x00001908)
+#define COPY_EMMC43_CH1_TO_MEM_FUNC (0x00002E64)
+#define COPY_EMMC44_CH3_TO_MEM_FUNC (0x00003FA4)
+#elif defined(CONFIG_EVT1)
+ #if defined(CONFIG_S5P6460)
+ #define COPY_MOVI_TO_MEM_FUNC (0xD0020038)
+ #else
+ #define COPY_MOVI_TO_MEM_FUNC (0x00002360)
+ #endif
+#define COPY_EMMC43_CH1_TO_MEM_FUNC (0x00003824)
+#define COPY_EMMC44_CH3_LOAD_DRAM_FUNC (0x0000653C)
+#define SDMMC_ENDBOOTOP_EMMC_FUNC (0x00001C5C)
+#define MSH_ENDBOOTOP_EMMC_FUNC (0x000040B0)
+#else
+#define COPY_MOVI_TO_MEM_FUNC (0x00001908)
+#define COPY_EMMC43_CH1_TO_MEM_FUNC (0x00002E64)
+#define COPY_EMMC44_CH3_TO_MEM_FUNC (0x00003FA4)
+#endif
+
+#define EXTERNAL_FUNC_ADDRESS (0xD0020038)
+
+#define SDMMC_ReadBlocks(uStartBlk, uNumOfBlks, uDstAddr) \
+ (((void(*)(u32, u32, u32*))(*((u32 *)EXTERNAL_FUNC_ADDRESS)))(uStartBlk, uNumOfBlks, uDstAddr))
+
+
+void movi_uboot_copy(void)
+{
+#if defined(CONFIG_S5P6460)
+ SDMMC_ReadBlocks(MOVI_UBOOT_POS, MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+#else
+ copy_sd_mmc_to_mem copy_uboot = (copy_sd_mmc_to_mem)(COPY_MOVI_TO_MEM_FUNC);
+
+ copy_uboot(MOVI_UBOOT_POS, MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+#endif
+}
+
+void emmc_uboot_copy(void)
+{
+ copy_emmc43_to_mem copy_uboot = (copy_emmc43_to_mem)(COPY_EMMC43_CH1_TO_MEM_FUNC);
+
+ copy_uboot(MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+}
+
+void emmc_4_4_uboot_copy(void)
+{
+ copy_emmc44_to_mem copy_uboot = (copy_emmc44_to_mem)(COPY_EMMC44_CH3_LOAD_DRAM_FUNC);
+
+ copy_uboot(MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+
+}
+
+void emmc_4_3_endbootOp_eMMC(void)
+{
+ emmc43_endbootop endbootop_emmc43 = (emmc43_endbootop)(SDMMC_ENDBOOTOP_EMMC_FUNC);
+ endbootop_emmc43();
+}
+
+void emmc_4_4_endbootOp_eMMC(void)
+{
+ emmc44_endbootop endbootop_emmc44 = (emmc44_endbootop)(MSH_ENDBOOTOP_EMMC_FUNC);
+ endbootop_emmc44();
+}
+
+void movi_write_env(ulong addr)
+{
+ movi_write(1, raw_area_control.image[2].start_blk,
+ raw_area_control.image[2].used_blk, addr);
+}
+
+void movi_read_env(ulong addr)
+{
+ movi_read(1, raw_area_control.image[2].start_blk,
+ raw_area_control.image[2].used_blk, addr);
+}
+
+void movi_write_bl1(ulong addr, int dev_num)
+{
+ int i;
+ ulong checksum;
+ ulong src;
+ ulong tmp;
+
+ src = addr;
+
+ for(i = 0, checksum = 0;i < (14 * 1024) - 4;i++)
+ {
+ checksum += *(u8*)addr++;
+ }
+
+ tmp = *(ulong*)addr;
+ *(ulong*)addr = checksum;
+
+ movi_write(dev_num, raw_area_control.image[1].start_blk,
+ raw_area_control.image[1].used_blk, src);
+
+ *(ulong*)addr = tmp;
+}
+
diff --git a/arch/arm/cpu/arm11/s5p6450/movi_partition.c b/arch/arm/cpu/arm11/s5p6450/movi_partition.c
new file mode 100644
index 0000000000..e026e83644
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/movi_partition.c
@@ -0,0 +1,125 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+
+#ifdef DEBUG_MOVI_PARTITION
+#define dbg(x...) printf(x)
+#else
+#define dbg(x...) do { } while (0)
+#endif
+
+raw_area_t raw_area_control;
+
+int init_raw_area_table(block_dev_desc_t * dev_desc, int location)
+{
+ int i;
+ member_t *image;
+ u32 capacity;
+
+ /* init raw_area will be 16MB */
+ raw_area_control.start_blk = 16*1024*1024/MOVI_BLKSIZE;
+ raw_area_control.next_raw_area = 0;
+ strcpy(raw_area_control.description, "initial raw table");
+
+ image = raw_area_control.image;
+
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ #if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_BL1_ONLY)
+ /* image 0 should be fwbl1 */
+ image[0].start_blk = location;
+ image[0].used_blk = MOVI_FWBL1_BLKCNT;
+ image[0].size = FWBL1_SIZE;
+ image[0].attribute = 0x0;
+ strcpy(image[0].description, "fwbl1");
+ dbg("fwbl1: %d\n", image[0].start_blk);
+ #endif
+#endif
+
+ /* image 1 should be bl2 */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ #if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_BL1_ONLY)
+ image[1].start_blk = image[0].start_blk + MOVI_FWBL1_BLKCNT;
+ #else
+ image[1].start_blk = location;
+ #endif
+#else
+ image[1].start_blk = capacity - (eFUSE_SIZE/MOVI_BLKSIZE) - MOVI_BL1_BLKCNT;
+#endif
+ image[1].used_blk = MOVI_BL1_BLKCNT;
+ image[1].size = SS_SIZE;
+ #if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_S5P6460_IP_TEST)
+ image[1].attribute = 0x3;
+ #else
+ image[1].attribute = 0x1;
+ #endif
+ strcpy(image[1].description, "u-boot parted");
+ dbg("bl1: %d\n", image[1].start_blk);
+
+ /* image 2 should be environment */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ image[2].start_blk = image[1].start_blk + MOVI_BL1_BLKCNT;
+#else
+ image[2].start_blk = image[1].start_blk - MOVI_ENV_BLKCNT;
+#endif
+ image[2].used_blk = MOVI_ENV_BLKCNT;
+ image[2].size = CONFIG_ENV_SIZE;
+ image[2].attribute = 0x10;
+ strcpy(image[2].description, "environment");
+ dbg("env: %d\n", image[2].start_blk);
+
+ /* image 3 should be u-boot */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ if(location)
+ image[3].start_blk = image[2].start_blk + MOVI_ENV_BLKCNT;
+ else
+ image[3].start_blk = image[2].start_blk;
+#else
+ image[3].start_blk = image[2].start_blk - MOVI_UBOOT_BLKCNT;
+#endif
+ image[3].used_blk = MOVI_UBOOT_BLKCNT;
+ image[3].size = PART_SIZE_BL;
+ image[3].attribute = 0x2;
+ strcpy(image[3].description, "u-boot");
+ dbg("bl2: %d\n", image[3].start_blk);
+
+ /* image 4 should be kernel */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ image[4].start_blk = image[3].start_blk + MOVI_UBOOT_BLKCNT;
+#else
+ image[4].start_blk = image[3].start_blk - MOVI_ZIMAGE_BLKCNT;
+#endif
+ image[4].used_blk = MOVI_ZIMAGE_BLKCNT;
+ image[4].size = PART_SIZE_KERNEL;
+ image[4].attribute = 0x4;
+ strcpy(image[4].description, "kernel");
+ dbg("knl: %d\n", image[4].start_blk);
+
+ /* image 5 should be RFS */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5P6450)
+ image[5].start_blk = image[4].start_blk + MOVI_ZIMAGE_BLKCNT;
+#else
+ image[5].start_blk = image[4].start_blk - MOVI_ROOTFS_BLKCNT;
+#endif
+ image[5].used_blk = MOVI_ROOTFS_BLKCNT;
+ image[5].size = PART_SIZE_ROOTFS;
+ image[5].attribute = 0x8;
+ strcpy(image[5].description, "rfs");
+ dbg("rfs: %d\n", image[5].start_blk);
+
+ for (i=6; i<15; i++) {
+ raw_area_control.image[i].start_blk = 0;
+ raw_area_control.image[i].used_blk = 0;
+ }
+}
+
diff --git a/arch/arm/cpu/arm11/s5p6450/reset.c b/arch/arm/cpu/arm11/s5p6450/reset.c
new file mode 100644
index 0000000000..7c7d65f213
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/reset.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+/* * reset the cpu by setting up the watchdog timer and let him time out */
+void reset_cpu(ulong ignored)
+{
+ printf("reset... \n\n\n");
+
+ SW_RST_REG = 0x6450;
+
+ /* loop forever and wait for reset to happen */
+ while (1)
+ {
+ if (serial_tstc())
+ {
+ serial_getc();
+ break;
+ }
+ }
+ /*NOTREACHED*/
+}
diff --git a/arch/arm/cpu/arm11/s5p6450/setup_hsmmc.c b/arch/arm/cpu/arm11/s5p6450/setup_hsmmc.c
new file mode 100644
index 0000000000..025c7c0166
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/setup_hsmmc.c
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/s3c_hsmmc.h>
+
+extern ulong get_MPLL_CLK(void);
+
+void set_hsmmc_pre_ratio (struct sdhci_host *host, uint clock)
+{
+ u32 div, clk;
+
+ clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+ /* XXX: we assume that clock is between 40MHz and 50MHz */
+ if (clock <= 400000)
+ div = 0x40;
+ else if (clock <= 20000000)
+ div = 2;
+ else if (clock <= 26000000)
+ div = 1;
+ else
+ div = 0;
+ clk = div << SDHCI_DIVIDER_SHIFT;
+
+ writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
+}
+void setup_hsmmc_clock(void)
+{
+ u32 tmp;
+ u32 clock;
+ u32 i;
+
+ /* MMC0 clock src = SCLKMPLL */
+ tmp = CLK_SRC0_REG & ~(0x3<<18);
+ CLK_SRC0_REG = tmp | (0x1<<18);
+
+ /* MMC0 clock div */
+ tmp = CLK_DIV1_REG & ~(0x0000000f);
+ clock = get_MPLL_CLK()/1000000;
+
+ for(i=0; i<0xf; i++)
+ {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV1_REG = tmp | i<<0;
+ break;
+ }
+ }
+
+#ifdef USE_MMC1
+ /* MMC1 clock src = SCLKMPLL */
+ tmp = CLK_SRC0_REG & ~(0x3<<20);
+ CLK_SRC0_REG = tmp | (0x1<<20);
+
+ /* MMC1 clock div */
+ tmp = CLK_DIV1_REG & ~(0x000000f0);
+ for(i=0; i<0xf; i++)
+ {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV1_REG = tmp | i<<4;
+ break;
+ }
+ }
+#endif
+
+#ifdef USE_MMC2
+ /* MMC2 clock src = SCLKMPLL */
+ tmp = CLK_SRC0_REG & ~(0x3<<22);
+ CLK_SRC0_REG = tmp | (0x1<<22);
+
+ /* MMC2 clock div */
+ tmp = CLK_DIV1_REG & ~(0x00000f00);
+ for(i=0; i<0xf; i++)
+ {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV1_REG = tmp | i<<8;
+ break;
+ }
+ }
+#endif
+
+#ifdef USE_MMC3
+ /* MMC2 clock src = SCLKMPLL */
+ tmp = CLK_SRC0_REG & ~(0x7<<6);
+ CLK_SRC0_REG = tmp | (0x1<<6);
+
+ /* MMC2 clock div */
+ tmp = CLK_DIV1_REG & ~(0xf<<28);
+ for(i=0; i<0xf; i++)
+ {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV1_REG = tmp | i<<28;
+ break;
+ }
+ }
+#endif
+}
+
+/*
+ * this will set the GPIO for hsmmc ch0
+ * GPG0[0:6] = CLK, CMD, CDn, DAT[0:3]
+ */
+void setup_hsmmc_cfg_gpio(void)
+{
+ ulong reg;
+
+ /* MMC channel 0 */
+ /* 7 pins will be assigned - GPG0[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPGCON0) & 0xf0000000;
+ writel(reg | 0x02222222, GPGCON0);
+ reg = readl(GPGPUD) & 0xffffc000;
+ writel(reg | 0x00002aaa, GPGPUD);
+
+#ifdef USE_MMC1
+ /* MMC channel 1 */
+ /* 7 pins will be assigned - GPG1[0:6] = CLK, CMD, CDn, DAT[0:3] */
+#ifdef CONFIG_S5P6460
+ reg = readl(GPGCON0) & 0x00ffffff;
+ writel(reg | 0x20000000, GPGCON0);
+
+ reg = readl(GPGCON1) & 0xff000000;
+ writel(reg | 0x00122222, GPGCON1);
+
+ reg = readl(GPGPUD) & 0x00002fff;
+ writel(reg | 0x0aaa8000, GPGPUD);
+#else
+ reg = readl(GPHCON0) & 0xffffffff;
+ writel(reg | 0x22222222, GPHCON0);
+
+ reg = readl(GPHCON1) & 0x000000ff;
+ writel(reg | 0x00000022, GPHCON1);
+
+ reg = readl(GPHPUD) & 0x0003ffff;
+ writel(reg | 0x00002aaa, GPHPUD);
+#endif
+
+#endif
+
+#ifdef USE_MMC2
+ /* MMC channel 2 */
+ /* 7 pins will be assigned - GPG2[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPGCON0) & 0xf0000000;
+ writel(reg | 0x30000000, GPGCON0);
+
+ reg = readl(GPGCON1) & 0x000fffff;
+ writel(reg | 0x00033333, GPGCON1);
+
+ reg = readl(GPGPUD) & 0x03ffc000;
+ writel(reg | 0x02aa8000, GPGPUD);
+#endif
+
+#ifdef USE_MMC3
+ /* MMC channel 3 */
+ /* 7 pins will be assigned - GPG0[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPGCON0) & 0xf0000000;
+ writel(reg | 0x20000000, GPGCON0);
+
+ reg = readl(GPGCON1) & 0x000fffff;
+ writel(reg | 0x00022222, GPGCON1);
+
+ reg = readl(GPGPUD) & 0x0fffc000;
+ writel(reg | 0x0aaa8000, GPGPUD);
+#endif
+}
+
+
+void setup_sdhci0_cfg_card(struct sdhci_host *host)
+{
+ u32 ctrl2;
+ u32 ctrl3 = 0;
+
+ /* don't need to alter anything acording to card-type */
+ writel(S3C_SDHCI_CONTROL4_DRIVE_9mA, host->ioaddr + S3C_SDHCI_CONTROL4);
+
+ ctrl2 = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+
+ ctrl2 |= (S3C_SDHCI_CTRL2_ENSTAASYNCCLR |
+ S3C_SDHCI_CTRL2_ENCMDCNFMSK |
+ //S3C_SDHCI_CTRL2_ENFBCLKTX |
+ S3C_SDHCI_CTRL2_ENFBCLKRX |
+ S3C_SDHCI_CTRL2_DFCNT_NONE |
+ S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+ /*
+ if(host->mmc->clock == 52*1000000)
+ ctrl3 = 0;
+ else
+ ctrl3 = S3C_SDHCI_CTRL3_FCSEL0 | S3C_SDHCI_CTRL3_FCSEL1;
+ */
+ ctrl3 = 0x7f5f3f1f;
+ //| S3C_SDHCI_CTRL3_FCSEL0
+ //| S3C_SDHCI_CTRL3_FCSEL1);
+
+ writel(ctrl2, host->ioaddr + S3C_SDHCI_CONTROL2);
+ writel(ctrl3, host->ioaddr + S3C_SDHCI_CONTROL3);
+}
+
diff --git a/arch/arm/cpu/arm11/s5p6450/sys_info.c b/arch/arm/cpu/arm11/s5p6450/sys_info.c
new file mode 100644
index 0000000000..c6efcd6ae2
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/sys_info.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+
+/* Default is s5p6450 */
+unsigned int s5p_cpu_id = 0x6450;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ s5p_clock_init();
+
+ return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+ return s5p_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ if(((PRO_ID >> 12) & 0x36450) == 0x36450){
+ printf("\nCPU: S5P6450 [Samsung SOC on ARM1176]\n");
+ }
+
+ printf("APLL = %ldMHz, MPLL = %ldMHz\n", get_APLL_CLK()/1000000, get_MPLL_CLK()/1000000);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm11/s5p6450/timer.c b/arch/arm/cpu/arm11/s5p6450/timer.c
new file mode 100644
index 0000000000..20f76a842e
--- /dev/null
+++ b/arch/arm/cpu/arm11/s5p6450/timer.c
@@ -0,0 +1,202 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/pwm.h>
+#include <div64.h>
+
+static ulong count_value;
+
+#define PRESCALER 0xf
+
+/* macro to read the 16 bit timer */
+static inline ulong read_timer(void)
+{
+ s5p6450_timer *const timers = samsung_get_base_timers();
+
+ return timers->tcnto4;
+}
+
+/* Internal tick units */
+/* Last decremneter snapshot */
+static unsigned long lastdec;
+/* Monotonic incrementing timer */
+static unsigned long long timestamp;
+
+int timer_init(void)
+{
+ unsigned int cnt=0;
+ s5p6450_timer *const timers = (s5p6450_timer *)samsung_get_base_timers();
+ u32 val;
+
+ /*
+ * @ PWM Timer 4
+ * Timer Freq(HZ) =
+ * PWM_CLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ /* set prescaler : 16 */
+ timers->tcfg0 = PRESCALER << 8;
+
+ count_value = get_pwm_clk() / (PRESCALER + 1);
+
+ /* count_value / 100 = 41700(HZ) (per 10msec)*/
+ count_value = count_value / 100;
+
+ /* load value for 10 ms timeout */
+ lastdec = count_value;
+ writel(count_value, &timers->tcntb4);
+
+ /* auto load, manual update of Timer 4 */
+ val = (readl(&timers->tcon) & ~0x00700000) | TCON_4_AUTO | TCON_4_UPDATE;
+
+ writel(val, &timers->tcon);
+
+ /* auto load, start Timer 4 */
+ writel((readl(&timers->tcon) & ~0x00700000) |TCON_4_AUTO | COUNT_4_ON,&timers->tcon);
+
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(unsigned long t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+ s5p6450_timer *const timers = (s5p6450_timer *)samsung_get_base_timers();
+ unsigned long tmo, tmp;
+
+ count_value = readl(&timers->tcntb4);
+
+ if (usec >= 1000) {
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value / 10);
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ * count_value / 10;
+ tmo /= (1000 * 1000);
+ }
+
+ /* get current timestamp */
+ tmp = get_timer(0);
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastdec value */
+ /* else, set advancing stamp wake up time */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ /* loop till event */
+ while (get_timer_masked() < tmo)
+ ; /* nop */
+}
+
+void reset_timer_masked(void)
+{
+ s5p6450_timer *const timers = (s5p6450_timer *)samsung_get_base_timers();
+ /* reset time */
+ lastdec = readl(&timers->tcnto4);
+ timestamp = 0;
+}
+
+unsigned long get_timer_masked(void)
+{
+ s5p6450_timer *const timers = (s5p6450_timer *)samsung_get_base_timers();
+ unsigned long now = readl(&timers->tcnto4);
+
+ if (lastdec >= now)
+ timestamp += lastdec - now;
+ else
+ timestamp += lastdec + count_value - now;
+
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/arm11/start.S b/arch/arm/cpu/arm11/start.S
new file mode 100644
index 0000000000..17eace0b0e
--- /dev/null
+++ b/arch/arm/cpu/arm11/start.S
@@ -0,0 +1,440 @@
+/*
+ * armboot - Startup Code for ARM1176 CPU-core
+ *
+ * Copyright (c) 2007 Samsung Electronics
+ *
+ * Copyright (C) 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
+ * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
+ * jsgood (jsgood.yang@samsung.com)
+ * Base codes by scsuh (sc.suh)
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <version.h>
+#ifdef CONFIG_ENABLE_MMU
+#include <asm/proc/domain.h>
+#endif
+
+#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
+#define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
+#endif
+
+/*
+ *************************************************************************
+ *
+ * Jump vector table as in table 3.1 in [1]
+ *
+ *************************************************************************
+ */
+
+.globl _start
+_start: b reset
+#ifndef CONFIG_NAND_SPL
+ ldr pc, _undefined_instruction
+ ldr pc, _software_interrupt
+ ldr pc, _prefetch_abort
+ ldr pc, _data_abort
+ ldr pc, _not_used
+ ldr pc, _irq
+ ldr pc, _fiq
+
+_undefined_instruction:
+ .word undefined_instruction
+_software_interrupt:
+ .word software_interrupt
+_prefetch_abort:
+ .word prefetch_abort
+_data_abort:
+ .word data_abort
+_not_used:
+ .word not_used
+_irq:
+ .word irq
+_fiq:
+ .word fiq
+_pad:
+ .word 0x12345678 /* now 16*4=64 */
+#else
+ . = _start + 64
+#endif
+
+.global _end_vect
+_end_vect:
+ .balignl 16,0xdeadbeef
+/*
+ *************************************************************************
+ *
+ * Startup Code (reset vector)
+ *
+ * do important init only if we don't start from memory!
+ * setup Memory and board specific bits prior to relocation.
+ * relocate armboot to ram
+ * setup stack
+ *
+ *************************************************************************
+ */
+
+.globl _TEXT_BASE
+_TEXT_BASE:
+ .word CONFIG_SYS_TEXT_BASE
+
+/*
+ * Below variable is very important because we use MMU in U-Boot.
+ * Without it, we cannot run code correctly before MMU is ON.
+ * by scsuh.
+ */
+_TEXT_PHY_BASE:
+ .word CONFIG_SYS_PHY_UBOOT_BASE
+
+/*
+ * These are defined in the board-specific linker script.
+ * Subtracting _start from them lets the linker put their
+ * relative position in the executable instead of leaving
+ * them null.
+ */
+
+.globl _bss_start_ofs
+_bss_start_ofs:
+ .word __bss_start - _start
+
+.globl _bss_end_ofs
+_bss_end_ofs:
+ .word _end - _start
+
+/* IRQ stack memory (calculated at run-time) + 8 bytes */
+.globl IRQ_STACK_START_IN
+IRQ_STACK_START_IN:
+ .word 0x0badc0de
+
+/*
+ * the actual reset code
+ */
+
+reset:
+ /*
+ * set the cpu to SVC32 mode
+ */
+ mrs r0, cpsr
+ bic r0, r0, #0x3f
+ orr r0, r0, #0xd3
+ msr cpsr, r0
+
+/*
+ *************************************************************************
+ *
+ * CPU_init_critical registers
+ *
+ * setup important registers
+ * setup memory timing
+ *
+ *************************************************************************
+ */
+ /*
+ * we do sys-critical inits only at reboot,
+ * not when booting from ram!
+ */
+cpu_init_crit:
+ /*
+ * When booting from NAND - it has definitely been a reset, so, no need
+ * to flush caches and disable the MMU
+ */
+#ifndef CONFIG_NAND_SPL
+ /*
+ * flush v4 I/D caches
+ */
+ mov r0, #0
+ mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+
+ /*
+ * disable MMU stuff and caches
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+
+#ifdef CONFIG_S5P6450
+ mcr p15, 0, r0, c1, c0, 0
+#else
+ /* Prepare to disable the MMU */
+ adr r2, mmu_disable_phys
+ sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
+ b mmu_disable
+
+ .align 5
+ /* Run in a single cache-line */
+mmu_disable:
+ mcr p15, 0, r0, c1, c0, 0
+ nop
+ nop
+ mov pc, r2
+mmu_disable_phys:
+#endif
+
+#ifdef CONFIG_DISABLE_TCM
+ /*
+ * Disable the TCMs
+ */
+ mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
+ cmp r0, #0
+ beq skip_tcmdisable
+ mov r1, #0
+ mov r2, #1
+ tst r0, r2
+ mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
+ tst r0, r2, LSL #16
+ mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
+skip_tcmdisable:
+#endif
+#endif
+
+#ifdef CONFIG_PERIPORT_REMAP
+ /* Peri port setup */
+ ldr r0, =CONFIG_PERIPORT_BASE
+ orr r0, r0, #CONFIG_PERIPORT_SIZE
+ mcr p15,0,r0,c15,c2,4
+#endif
+
+ /*
+ * Go setup Memory and board specific bits prior to relocation.
+ */
+ bl lowlevel_init /* go setup pll,mux,memory */
+
+ /* Set stackpointer in internal RAM to call board_init_f */
+call_board_init_f:
+ ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ ldr r0,=0x00000000
+ bl board_init_f
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ */
+ .globl relocate_code
+relocate_code:
+ mov r4, r0 /* save addr_sp */
+ mov r5, r1 /* save addr of gd */
+ mov r6, r2 /* save addr of destination */
+
+ /* Set up the stack */
+stack_setup:
+ mov sp, r4
+
+ adr r0, _start
+ cmp r0, r6
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r2, _TEXT_BASE
+ ldr r3, _bss_start_ofs
+ add r2, r0, r3 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r9-r10} /* copy from source address [r0] */
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end address [r2] */
+ blo copy_loop
+
+#ifndef CONFIG_PRELOADER
+ /*
+ * fix .rel.dyn relocations
+ */
+ ldr r0, _TEXT_BASE /* r0 <- Text base */
+ sub r9, r6, r0 /* r9 <- relocation offset */
+ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
+ add r10, r10, r0 /* r10 <- sym table in FLASH */
+ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
+ add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
+ ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
+ add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
+fixloop:
+ ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
+ add r0, r0, r9 /* r0 <- location to fix up in RAM */
+ ldr r1, [r2, #4]
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
+ beq fixrel
+ cmp r7, #2 /* absolute fixup? */
+ beq fixabs
+ /* ignore unknown type of fixup */
+ b fixnext
+fixabs:
+ /* absolute fix: set location to (offset) symbol value */
+ mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
+ add r1, r10, r1 /* r1 <- address of symbol in table */
+ ldr r1, [r1, #4] /* r1 <- symbol value */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
+ b fixnext
+fixrel:
+ /* relative fix: increase location by offset */
+ ldr r1, [r0]
+ add r1, r1, r9
+fixnext:
+ str r1, [r0]
+ add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
+ cmp r2, r3
+ blo fixloop
+#endif
+
+#ifndef CONFIG_S5P6450
+#ifdef CONFIG_ENABLE_MMU
+enable_mmu:
+ /* enable domain access */
+ ldr r5, =0x0000ffff
+ mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
+
+ /* Set the TTB register */
+ ldr r0, _mmu_table_base
+ ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
+ ldr r2, =0xfff00000
+ bic r0, r0, r2
+ orr r1, r0, r1
+ mcr p15, 0, r1, c2, c0, 0
+
+ /* Enable the MMU */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #1 /* Set CR_M to enable MMU */
+
+ /* Prepare to enable the MMU */
+ adr r1, skip_hw_init
+ and r1, r1, #0x3fc
+ ldr r2, _TEXT_BASE
+ ldr r3, =0xfff00000
+ and r2, r2, r3
+ orr r2, r2, r1
+ b mmu_enable
+
+ .align 5
+ /* Run in a single cache-line */
+mmu_enable:
+
+ mcr p15, 0, r0, c1, c0, 0
+ nop
+ nop
+ mov pc, lr
+skip_hw_init:
+#endif
+#endif
+
+clear_bss:
+#ifndef CONFIG_PRELOADER
+ ldr r0, _bss_start_ofs
+ ldr r1, _bss_end_ofs
+ ldr r3, _TEXT_BASE /* Text base */
+ mov r4, r6 /* reloc addr */
+ add r0, r0, r4
+ add r1, r1, r4
+ mov r2, #0x00000000 /* clear */
+
+clbss_l:str r2, [r0] /* clear loop... */
+ add r0, r0, #4
+ cmp r0, r1
+ bne clbss_l
+
+#ifndef CONFIG_S5P6450
+ bl coloured_LED_init
+ bl red_LED_on
+#endif
+#endif
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+#ifdef CONFIG_NAND_SPL
+ ldr pc, _nand_boot
+
+_nand_boot: .word nand_boot
+#else
+ ldr r0, _board_init_r_ofs
+ adr r1, _start
+ add lr, r0, r1
+@ add lr, lr, r9
+ /* setup parameters for board_init_r */
+ mov r0, r5 /* gd_t */
+ mov r1, r6 /* dest_addr */
+ /* jump to it ... */
+ mov pc, lr
+ b .
+
+_board_init_r_ofs:
+ .word board_init_r - _start
+#endif
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
+
+#ifdef CONFIG_ENABLE_MMU
+_mmu_table_base:
+ .word mmu_table
+#endif
+
+/*
+ * exception handlers
+ */
+ .align 5
+undefined_instruction:
+
+ b reset
+
+ .align 5
+software_interrupt:
+
+ b reset
+
+ .align 5
+prefetch_abort:
+
+ b reset
+
+ .align 5
+data_abort:
+
+ b reset
+
+ .align 5
+not_used:
+
+ b reset
+
+ .align 5
+irq:
+
+ b reset
+
+ .align 5
+fiq:
+ b reset
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 49ac9c74ae..7f9b1712eb 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -23,7 +23,7 @@
PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
+PLATFORM_CPPFLAGS += -march=armv7-a
# =========================================================================
#
# Supply options according to compiler version
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index a01e0d605f..6b1a730b94 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -40,6 +40,9 @@
#endif
static void cache_flush(void);
+#if defined(CONFIG_S5PC210) || defined(CONFIG_ARCH_EXYNOS)
+void clear_hsmmc_clock_div(void);
+#endif
int cleanup_before_linux(void)
{
@@ -74,6 +77,9 @@ int cleanup_before_linux(void)
l2_cache_enable();
#endif
+#if defined(CONFIG_S5PC210) || defined(CONFIG_ARCH_EXYNOS)
+ clear_hsmmc_clock_div();
+#endif
return 0;
}
diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile
new file mode 100644
index 0000000000..5b5f952cf7
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/Makefile
@@ -0,0 +1,79 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2011 Samsung Electronics Co. Ltd
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+#SOBJS += reset.o
+COBJS += irom_copy.o
+COBJS += nand.o
+COBJS += nand_cp.o
+ifdef CONFIG_CMD_NAND
+COBJS += nand_write_bl.o
+endif
+COBJS += onenand_cp.o
+
+ifdef CONFIG_HKDK4212
+COBJS += pmic_hkdk4212.o
+else
+ifndef CONFIG_CPU_EXYNOS4X12
+ifndef CONFIG_CPU_EXYNOS5250
+COBJS += pmic.o
+endif
+endif
+endif
+
+ifdef CONFIG_SECURE_BOOT
+COBJS += UBOOT_SB20_S5PC210S.o
+COBJS += security_check.o
+COBJS += ace_sha1.o
+endif
+COBJS += reset.o
+COBJS += gpio.o
+COBJS += movi_partition.o
+COBJS += sys_info.o
+COBJS += clock.o
+COBJS += setup_hsmmc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.c b/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.c
new file mode 100644
index 0000000000..03830e30bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "UBOOT_SB20_S5PC210S.h"
+
+#include <asm/arch/ace_sha1.h>
+#define CONFIG_SHA1 (1)
+//#define SW_SHA1 (1)
+
+#define SHA1_BLOCK_LEN 64 /* Input Message Block Length */
+#define SHA1_DIGEST_LEN 20 /* Hash Code Length */
+
+/* SHA1 Context */
+typedef struct
+{
+ unsigned int auChain[SHA1_DIGEST_LEN/4]; /* Chaining Variable */
+ unsigned int auCount[2]; /* the number of input message bit */
+ unsigned char abBuffer[SHA1_BLOCK_LEN]; /* Buffer for unfilled block */
+} SHA1_ALG_INFO;
+
+/* int sscl_memcmp(BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memcmp(BASE_FUNC_PTR,a,b,c) \
+ (((int(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 0))))\
+ ((a),(b),(c)))
+
+/* void sscl_memcpy(BYTE *pbDst, BYTE *pbSrc, DWORD uByteLen); */
+#define macro_sscl_memcpy(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 4))))\
+ ((a),(b),(c)))
+
+//void sscl_memset(BYTE *pbDst, BYTE bValue, DWORD uByteLen); */
+#define macro_sscl_memset(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 8))))\
+ ((a),(b),(c)))
+
+/* void sscl_memxor(BYTE *pbDst, BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memxor(BASE_FUNC_PTR,a,b,c,d) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 12))))\
+ ((a),(b),(c),(d)))
+
+/* unsigned int SEC_SHA1_Init(SHA1_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 16))))\
+ ((a)))
+
+/* unsigned SEC_SHA1_Update(SHA1_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 20))))\
+ ((a),(b),(c)))
+
+/* unsigned SEC_SHA1_Final( SHA1_ALG_INFO *psAlgInfo, BYTE *pbDigest); */
+#define macro_SEC_SHA1_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 24))))\
+ ((a),(b)))
+
+/* RET_VAL SEC_SHA1_HMAC_SetInfo( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbUserKey, DWORD uUKeyLen ); */
+#define macro_SEC_SHA1_HMAC_SetInfo(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 28))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Init(SHA1_HMAC_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_HMAC_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 32))))\
+ ((a)))
+
+/* RET_VAL SEC_SHA1_HMAC_Update(SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_HMAC_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 36))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Final( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbHmacVal); */
+#define macro_SEC_SHA1_HMAC_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 40))))\
+ ((a),(b)))
+
+/* int Verify_PSS_RSASignature (
+ * IN unsigned char *rawRSAPublicKey,
+ * IN int rawRSAPublicKeyLen,
+ * IN unsigned char *hashCode,
+ * IN int hashCodeLen,
+ * IN unsigned char *signature,
+ * IN int signatureLen);
+ */
+#define macro_Verify_PSS_RSASignature(BASE_FUNC_PTR,a,b,c,d,e,f) \
+ (((int(*)(unsigned char *, int, unsigned char *, int, unsigned char*, int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 44))))\
+ ((a),(b),(c),(d),(e),(f)))
+#define macro_Verify_PSS_RSASignature2(BASE_FUNC_PTR,a,b,c,d,e,f) (((int(*)(unsigned char *, int, unsigned char *, int, unsigned char*, int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 48))))\
+ ((a),(b),(c),(d),(e),(f)))
+
+
+////////////////////////////////////////////////////////////////////////
+// Verify integrity of BL2(or OS) Image.
+int Check_Signature (
+ SB20_CONTEXT *sbContext,
+ unsigned char *data,
+ int dataLen,
+ unsigned char *signedData,
+ int signedDataLen )
+{
+ unsigned int rv;
+ unsigned int SBoot_BaseFunc_ptr;
+
+ SBoot_BaseFunc_ptr = (unsigned int)sbContext->func_ptr_BaseAddr;
+#if defined (CONFIG_SHA1)
+ unsigned char hashCode[SHA1_DIGEST_LEN];
+ int hashCodeLen = SHA1_DIGEST_LEN;
+ SHA1_ALG_INFO algInfo;
+ SB20_RSAPubKey tempPubKey;
+ SBoot_BaseFunc_ptr = (unsigned int)sbContext->func_ptr_BaseAddr;
+
+#if 0
+ /* 0. if stage2 pubkey is 0x00, do NOT check integrity. */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *)&tempPubKey,
+ 0x00,
+ sizeof(SB20_RSAPubKey));
+
+ rv = macro_sscl_memcmp(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ (unsigned char *)&tempPubKey,
+ sizeof(SB20_RSAPubKey));
+
+ if (rv == 0)
+ return SB_OFF;
+#endif
+ /* 1. Make HashCode */
+ /* 1-1. SHA1 Init */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *) &algInfo,
+ 0x00,
+ sizeof(SHA1_ALG_INFO));
+
+#if defined(SW_SHA1)
+ macro_SEC_SHA1_Init(SBoot_BaseFunc_ptr, &algInfo );
+
+ /* 1-3. SHA1 Update. */
+ macro_SEC_SHA1_Update(SBoot_BaseFunc_ptr, &algInfo, data, dataLen );
+
+ /* 1-4. SHA1 Final. */
+ macro_SEC_SHA1_Final(SBoot_BaseFunc_ptr, &algInfo, hashCode );
+#else
+ ace_hash_sha1_digest(hashCode, data, dataLen);
+#endif
+ rv = macro_Verify_PSS_RSASignature(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ sizeof(SB20_RSAPubKey),
+ hashCode, hashCodeLen,
+ signedData, signedDataLen );
+#else
+ rv = macro_Verify_PSS_RSASignature2(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ sizeof(SB20_RSAPubKey),
+ data, dataLen,
+ signedData, signedDataLen );
+#endif
+ if ( rv != SB_OK )
+ return rv;
+
+ return SB_OK;
+}
diff --git a/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.h b/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.h
new file mode 100644
index 0000000000..f96b9add96
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/UBOOT_SB20_S5PC210S.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _UBOOT_SB20_S5PC210S_H
+#define _UBOOT_SB20_S5PC210S_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+////////////////////////////////////////////////////////////////////////
+// SecureBoot return value define
+#define SB_OK 0x00000000
+#define SB_OFF 0x80000000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_VALIDATE_PUBLIC_KEY_INFO 0xFFF10000
+#define SB_ERROR_VERIFY_PSS_RSA_SIGNATURE 0xFFF20000
+#define SB_ERROR_CHECK_INTEGRITY_CODE 0xFFF30000
+
+//------------------------------------------------------------------------
+// added for Secure Boot 2.0
+#define SB_ERROR_GENERATE_PSS_RSA_SIGNATURE 0xFFF40000
+#define SB_ERROR_GENERATE_PUBLIC_KEY_INFO 0xFFF50000
+#define SB_ERROR_GENERATE_SB_CONTEXT 0xFFF60000
+#define SB_ERROR_ENCRYPTION 0xFFF70000
+
+#define SB_ERROR_AES_PARM 0x0000A000
+#define SB_ERROR_AES_SET_ALGO 0x0000B000
+#define SB_ERROR_AES_ENCRYPT 0x0000C000
+#define SB_ERROR_AES_DECRYPT 0x0000D000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_HMAC_SHA1_SET_INFO 0x00000010
+#define SB_ERROR_HMAC_SHA1_INIT 0x00000020
+#define SB_ERROR_HMAC_SHA1_UPDATE 0x00000030
+#define SB_ERROR_HMAC_SHA1_FINAL 0x00000040
+#define SB_ERROR_MEM_CMP 0x00000050
+#define SB_ERROR_SHA1_INIT 0x00000060
+#define SB_ERROR_SHA1_UPDATE 0x00000070
+#define SB_ERROR_SHA1_FINAL 0x00000080
+#define SB_ERROR_VERIFY_RSA_PSS 0x00000090
+
+////////////////////////////////////////////////////////////////////////
+//-------------------------------------------
+#define SB20_MAX_EFUSE_DATA_LEN 20
+
+#define SB20_MAX_RSA_KEY (2048/8)
+#define SB20_MAX_SIGN_LEN SB20_MAX_RSA_KEY
+
+#define SB20_HMAC_SHA1_LEN 20
+
+//-------------------------------------------
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_e_Len;
+ unsigned char rsa_e[4];
+} SB20_RSAPubKey;
+
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_d_Len;
+ unsigned char rsa_d[SB20_MAX_RSA_KEY];
+} SB20_RSAPrivKey;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey rsaPubKey;
+ unsigned char signedData[SB20_HMAC_SHA1_LEN];
+} SB20_PubKeyInfo;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey stage2PubKey;
+ int code_SignedDataLen;
+ unsigned char code_SignedData[SB20_MAX_SIGN_LEN];
+ SB20_PubKeyInfo pubKeyInfo;
+ unsigned char func_ptr_BaseAddr[64];
+ unsigned char reservedData[144];
+} SB20_CONTEXT;
+
+
+////////////////////////////////////////////////////////////////////////
+// Verify integrity of BL2(or OS) Image.
+int Check_Signature (
+ SB20_CONTEXT *sb20_Context,
+ unsigned char *codeImage,
+ int codeImageLen,
+ unsigned char *signedData,
+ int signedDataLen );
+
+///////////////////////////////////////////////////////////////////////////////////
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UBOOT_SB20_S5PC210S_H */
diff --git a/arch/arm/cpu/armv7/exynos/ace_sha1.c b/arch/arm/cpu/armv7/exynos/ace_sha1.c
new file mode 100644
index 0000000000..14906fb884
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/ace_sha1.c
@@ -0,0 +1,129 @@
+/*
+ * Advanced Crypto Engine - SHA1 Firmware
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/ace_sfr.h>
+
+
+#if (defined(CONFIG_S5PV210) || defined(CONFIG_S5PC110) || defined(CONFIG_S5PV310) || defined(CONFIG_S5PC210)) || defined(CONFIG_ARCH_EXYNOS)
+
+/*****************************************************************
+ Definitions
+*****************************************************************/
+#define ACE_read_sfr(_sfr_) \
+ (*(volatile unsigned int*)(ACE_SFR_BASE + _sfr_))
+#define ACE_write_sfr(_sfr_, _val_) \
+ do {*(volatile unsigned int*)(ACE_SFR_BASE + _sfr_) \
+ = (unsigned int)(_val_);} while(0)
+
+/* SHA1 value for the message of zero length */
+const unsigned char sha1_digest_emptymsg[20] = {
+ 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
+ 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
+ 0xAF, 0xD8, 0x07, 0x09};
+
+
+/*****************************************************************
+ Functions
+*****************************************************************/
+/**
+ * @brief This function computes hash value of input (pBuf[0]..pBuf[buflen-1]).
+ *
+ * @param pOut A pointer to the output buffer. When operation is completed
+ * 20 bytes are copied to pOut[0]...pOut[19]. Thus, a user
+ * should allocate at least 20 bytes at pOut in advance.
+ * @param pBuf A pointer to the input buffer
+ * @param bufLen Byte length of input buffer
+ *
+ * @return 0 Success
+ *
+ * @remark This function assumes that pBuf is a physical address of input buffer.
+ *
+ * @version V1.00
+ * @b Revision History
+ * - V01.00 2009.11.13/djpark Initial Version
+ * - V01.10 2010.10.19/djpark Modification to support C210/V310
+ */
+int ace_hash_sha1_digest (
+ unsigned char* pOut,
+ unsigned char* pBuf,
+ unsigned int bufLen
+)
+{
+ unsigned int reg;
+ unsigned int* pDigest;
+
+ if (bufLen == 0) {
+ /* ACE H/W cannot compute hash value for empty string */
+ memcpy(pOut, sha1_digest_emptymsg, 20);
+ return 0;
+ }
+
+ /* Flush HRDMA */
+ ACE_write_sfr(ACE_FC_HRDMAC, ACE_FC_HRDMACFLUSH_ON);
+ ACE_write_sfr(ACE_FC_HRDMAC, ACE_FC_HRDMACFLUSH_OFF);
+
+ /* Set byte swap of data in */
+ ACE_write_sfr(ACE_HASH_BYTESWAP,
+ ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON);
+
+ /* Select Hash input mux as external source */
+ reg = ACE_read_sfr(ACE_FC_FIFOCTRL);
+ reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
+ ACE_write_sfr(ACE_FC_FIFOCTRL, reg);
+
+ /* Set Hash as SHA1 and start Hash engine */
+ reg = ACE_HASH_ENGSEL_SHA1HASH | ACE_HASH_STARTBIT_ON;
+ ACE_write_sfr(ACE_HASH_CONTROL, reg);
+
+ /* Enable FIFO mode */
+ ACE_write_sfr(ACE_HASH_FIFO_MODE, ACE_HASH_FIFO_ON);
+
+ /* Set message length */
+ ACE_write_sfr(ACE_HASH_MSGSIZE_LOW, bufLen);
+ ACE_write_sfr(ACE_HASH_MSGSIZE_HIGH, 0);
+
+ /* Set HRDMA */
+ ACE_write_sfr(ACE_FC_HRDMAS, (unsigned int)virt_to_phys(pBuf));
+ ACE_write_sfr(ACE_FC_HRDMAL, bufLen);
+
+ while ((ACE_read_sfr(ACE_HASH_STATUS) & ACE_HASH_MSGDONE_MASK)
+ == ACE_HASH_MSGDONE_OFF);
+
+ /* Clear MSG_DONE bit */
+ ACE_write_sfr(ACE_HASH_STATUS, ACE_HASH_MSGDONE_ON);
+
+ /* Read hash result */
+ pDigest = (unsigned int*)pOut;
+ pDigest[0] = ACE_read_sfr(ACE_HASH_RESULT1);
+ pDigest[1] = ACE_read_sfr(ACE_HASH_RESULT2);
+ pDigest[2] = ACE_read_sfr(ACE_HASH_RESULT3);
+ pDigest[3] = ACE_read_sfr(ACE_HASH_RESULT4);
+ pDigest[4] = ACE_read_sfr(ACE_HASH_RESULT5);
+
+ /* Clear HRDMA pending bit */
+ ACE_write_sfr(ACE_FC_INTPEND, ACE_FC_HRDMA);
+
+ return 0;
+}
+
+#endif
+
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
new file mode 100644
index 0000000000..209d40d238
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+unsigned long (*get_uart_clk)(int dev_index);
+unsigned long (*get_pwm_clk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+void s5p_clock_init(void)
+{
+}
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define VPLL 3
+
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+ ulong r, m, p, s;
+
+ if (pllreg == APLL) {
+ r = APLL_CON0_REG;
+ m = (r>>16) & 0x3ff;
+ } else if (pllreg == MPLL) {
+ r = MPLL_CON0_REG;
+ m = (r>>16) & 0x3ff;
+ } else
+ hang();
+
+ p = (r>>8) & 0x3f;
+ s = r & 0x7;
+#if !(defined(CONFIG_SMDKC220) || defined(CONFIG_ARCH_EXYNOS5))
+ if ((pllreg == APLL) || (pllreg == MPLL))
+ s= s-1;
+#endif
+
+ return (m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s))));
+}
+
+ulong get_APLL_CLK(void)
+{
+ return (get_PLLCLK(APLL));
+}
+
+ulong get_MPLL_CLK(void)
+{
+#if defined(CONFIG_CPU_EXYNOS5250_EVT1)
+ u32 clk_mux_stat_cdrex, mpll_fout_sel;
+
+ clk_mux_stat_cdrex = __raw_readl(ELFIN_CLOCK_BASE +
+ CLK_MUX_STAT_CDREX_OFFSET);
+
+ mpll_fout_sel = ( clk_mux_stat_cdrex >> 16 ) && 0x1;
+
+ if(mpll_fout_sel) {
+ return (get_PLLCLK(MPLL) / 2);
+ }
+#else
+ return (get_PLLCLK(MPLL));
+#endif
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/gpio.c b/arch/arm/cpu/armv7/exynos/gpio.c
new file mode 100644
index 0000000000..553ec039b8
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/gpio.c
@@ -0,0 +1,5377 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * File Name : gpio.c
+ *
+ * File Description : This file declares prototypes of GPIO API funcions.
+ *
+ * Author : chansik.Jeon
+ * Dept. : AP Development Team
+ * Created Date : 2010/04/16
+ * Version : 0.1
+ *
+ * History
+ * - Created(chigwan.Oh 2010/04/16)
+ *
+ */
+
+
+#include <asm/arch/gpio.h>
+
+#define GPIO_REG ( ( volatile oGPIO_REGS * ) (GPIO_pBase) )
+
+//=============================================
+// Left Bottom Block = ( GPA0 Group ~ GPF3 Group, ETC0, ETC1 )
+// Right Top Block = ( GPJ0 Group ~ MP0 Group, ETC6, ECT8 )
+//=============================================
+typedef struct tag_GPIO_REGS
+{
+
+ // Start Right Top Register===================================
+ int rGPIOJ0CON; //0x11000000
+ int rGPIOJ0DAT;
+ int rGPIOJ0PUD;
+ int rGPIOJ0DRV_SR;
+ int rGPIOJ0CONPDN;
+ int rGPIOJ0PUDPDN;
+ int reservedJ0[2]; // 0x11000018 ~ 0x1100001C
+
+ int rGPIOJ1CON; //0x11000020
+ int rGPIOJ1DAT;
+ int rGPIOJ1PUD;
+ int rGPIOJ1DRV_SR;
+ int rGPIOJ1CONPDN;
+ int rGPIOJ1PUDPDN;
+ int reservedJ1[2];
+
+ int rGPIOK0CON; //0x11000040
+ int rGPIOK0DAT;
+ int rGPIOK0PUD;
+ int rGPIOK0DRV_SR;
+ int rGPIOK0CONPDN;
+ int rGPIOK0PUDPDN;
+ int reservedK0[2];
+
+ int rGPIOK1CON; //0x11000060
+ int rGPIOK1DAT;
+ int rGPIOK1PUD;
+ int rGPIOK1DRV_SR;
+ int rGPIOK1CONPDN;
+ int rGPIOK1PUDPDN;
+ int reservedK1[2];
+
+ int rGPIOK2CON; //0x11000080
+ int rGPIOK2DAT;
+ int rGPIOK2PUD;
+ int rGPIOK2DRV_SR;
+ int rGPIOK2CONPDN;
+ int rGPIOK2PUDPDN;
+ int reservedK2[2];
+
+ int rGPIOK3CON; //0x110000A0
+ int rGPIOK3DAT;
+ int rGPIOK3PUD;
+ int rGPIOK3DRV_SR;
+ int rGPIOK3CONPDN;
+ int rGPIOK3PUDPDN;
+ int reservedK3[2];
+
+ int rGPIOL0CON; //0x110000C0
+ int rGPIOL0DAT;
+ int rGPIOL0PUD;
+ int rGPIOL0DRV_SR;
+ int rGPIOL0CONPDN;
+ int rGPIOL0PUDPDN;
+ int reservedL0[2];
+
+ int rGPIOL1CON; //0x110000E0
+ int rGPIOL1DAT;
+ int rGPIOL1PUD;
+ int rGPIOL1DRV_SR;
+ int rGPIOL1CONPDN;
+ int rGPIOL1PUDPDN;
+ int reservedL1[2];
+
+ int rGPIOL2CON; //0x11000100
+ int rGPIOL2DAT;
+ int rGPIOL2PUD;
+ int rGPIOL2DRV_SR;
+ int rGPIOL2CONPDN;
+ int rGPIOL2PUDPDN;
+ int reservedL2[2];
+
+ int rGPIOMP0CON; //0x11000120
+ int rGPIOMP0DAT;
+ int rGPIOMP0PUD;
+ int rGPIOMP0DRV_SR;
+ int rGPIOMP0CONPDN;
+ int rGPIOMP0PUDPDN;
+ int reservedMP0[2];
+
+ int rGPIOMP1CON; //0x11000140
+ int rGPIOMP1DAT;
+ int rGPIOMP1PUD;
+ int rGPIOMP1DRV_SR;
+ int rGPIOMP1CONPDN;
+ int rGPIOMP1PUDPDN;
+ int reservedMP1[2];
+
+ int rGPIOMP2CON; //0x11000160
+ int rGPIOMP2DAT;
+ int rGPIOMP2PUD;
+ int rGPIOMP2DRV_SR;
+ int rGPIOMP2CONPDN;
+ int rGPIOMP2PUDPDN;
+ int reservedMP2[2];
+
+ int rGPIOMP3CON; //0x11000180
+ int rGPIOMP3DAT;
+ int rGPIOMP3PUD;
+ int rGPIOMP3DRVSR;
+ int rGPIOMP3CONPDN;
+ int rGPIOMP3PUDPDN;
+ int reservedMP3[2];
+
+ int rGPIOMP4CON; //0x110001A0
+ int rGPIOMP4DAT;
+ int rGPIOMP4PUD;
+ int rGPIOMP4DRV_SR;
+ int rGPIOMP4CONPDN;
+ int rGPIOMP4PUDPDN;
+ int reservedMP4[2];
+
+ int rGPIOMP5CON; //0x110001C0
+ int rGPIOMP5DAT;
+ int rGPIOMP5PUD;
+ int rGPIOMP5DRV_SR;
+ int rGPIOMP5CONPDN;
+ int rGPIOMP5PUDPDN;
+ int reservedMP5[2];
+
+ int rGPIOMP6CON; //0x110001E0
+ int rGPIOMP6DAT;
+ int rGPIOMP6PUD;
+ int rGPIOMP6DRV_SR;
+ int rGPIOMP6CONPDN;
+ int rGPIOMP6PUDPDN;
+ int reservedMP6[2];
+
+
+ int reservedETC6_1[2];
+ int rGPIOETC6PUD; //0x11000208
+ int rGPIOETC6DRV_SR;
+ int reservedETC6_2[4];
+
+ int reservedETC8_1[2];
+ int rGPIOETC8PUD; //0x11000228
+ int rGPIOETC8DRV_SR;
+ int reservedETC8_2[4];
+
+ int reserved1[304]; // 0x1100_0240 ~ 0x1100_06FC
+
+ int rEINT21CON; // 0x1100_0700
+ int rEINT22CON;
+ int rEINT23CON;
+ int rEINT24CON;
+ int rEINT25CON;
+ int rEINT26CON;
+ int rEINT27CON;
+ int rEINT28CON;
+ int rEINT29CON;
+
+ int reservedEINTCON_1[55];
+
+ int rEINT21FLTCON0; //0x1100_0800
+ int rEINT21FLTCON1;
+ int rEINT22FLTCON0;
+ int rEINT22FLTCON1;
+ int rEINT23FLTCON0;
+ int rEINT23FLTCON1;
+ int rEINT24FLTCON0;
+ int rEINT24FLTCON1;
+ int rEINT25FLTCON0;
+ int rEINT25FLTCON1;
+ int rEINT26FLTCON0;
+ int rEINT26FLTCON1;
+ int rEINT27FLTCON0;
+ int rEINT27FLTCON1;
+ int rEINT28FLTCON0;
+ int rEINT28FLTCON1;
+ int rEINT29FLTCON0;
+ int rEINT29FLTCON1;
+
+ int reserveEINTFLTCON[46];
+
+ int rEINT21MASK; //0x1100_0900
+ int rEINT22MASK;
+ int rEINT23MASK;
+ int rEINT24MASK;
+ int rEINT25MASK;
+ int rEINT26MASK;
+ int rEINT27MASK;
+ int rEINT28MASK;
+ int rEINT29MASK;
+
+ int reservedEINTMASK_1[55];
+
+ int rEINT21PEND; //0x1100_0A00
+ int rEINT22PEND;
+ int rEINT23PEND;
+ int rEINT24PEND;
+ int rEINT25PEND;
+ int rEINT26PEND;
+ int rEINT27PEND;
+ int rEINT28PEND;
+ int rEINT29PEND;
+ int reservedEINTPEND[55];
+
+ int rEINTGRPPRIXB; //0x1100_0B00
+ int rEINTPRIORITYXB;
+ int rEINTSERVICEXB;
+ int rEINTSERVICEPENDXB;
+ int rEINTGRPFIXPRIXB;
+
+ int rEINT21FIXPRI;
+ int rEINT22FIXPRI;
+ int rEINT23FIXPRI;
+ int rEINT24FIXPRI;
+ int rEINT25FIXPRI;
+ int rEINT26FIXPRI;
+ int rEINT27FIXPRI;
+ int rEINT28FIXPRI;
+ int rEINT29FIXPRI;
+
+ int reservedEINTFIXPRI[50];
+
+ int rGPIOX0CON; //0x1100_0C00
+ int rGPIOX0DAT;
+ int rGPIOX0PUD;
+ int rGPIOX0DRV_SR;
+ int reservedGPIOX0[4];
+
+ int rGPIOX1CON; //0x1100_0C20
+ int rGPIOX1DAT;
+ int rGPIOX1PUD;
+ int rGPIOX1DRV_SR;
+ int reservedGPIOX1[4];
+
+ int rGPIOX2CON; //0x1100_0C40
+ int rGPIOX2DAT;
+ int rGPIOX2PUD;
+ int rGPIOX2DRV_SR;
+ int reservedGPIOX2[4];
+
+ int rGPIOX3CON; //0x1100_0C60
+ int rGPIOX3DAT;
+ int rGPIOX3PUD;
+ int rGPIOX3DRV_SR;
+ int reservedGPIOX3_1[4];
+
+ int reservedGPIOX3_2[96];
+
+ int rEINT40CON; //0x1100_0E00
+ int rEINT41CON;
+ int rEINT42CON;
+ int rEINT43CON;
+
+ int reservedEINTCON_2[28];
+
+ int rEINT40FLTCON0; //0x1100_0E80
+ int rEINT40FLTCON1;
+ int rEINT41FLTCON0;
+ int rEINT41FLTCON1;
+ int rEINT42FLTCON0;
+ int rEINT42FLTCON1;
+ int rEINT43FLTCON0;
+ int rEINT43FLTCON1;
+
+ int reservedEINTFLTCON[24];
+
+ int rEINT40MASK; //0x1100_0F00
+ int rEINT41MASK;
+ int rEINT42MASK;
+ int rEINT43MASK;
+
+ int reservedEINTMASK_2[12];
+
+ int rEINT40PEND; //0x1100_0F40
+ int rEINT41PEND;
+ int rEINT42PEND;
+ int rEINT43PEND;
+
+ int reservedRT[1047596]; // 0x1100_F50 ~ 0x113F_FFFC
+
+
+ // Start Left Bottom Register===========================================
+ int rGPIOA0CON; //0x11400000
+ int rGPIOA0DAT;
+ int rGPIOA0PUD;
+ int rGPIOA0DRV_SR;
+ int rGPIOA0CONPDN;
+ int rGPIOA0PUDPDN;
+ int reservedA0[2]; // 0x11400018 ~ 0x1140001C
+
+ int rGPIOA1CON; //0x11400020
+ int rGPIOA1DAT;
+ int rGPIOA1PUD;
+ int rGPIOA1DRV_SR;
+ int rGPIOA1CONPDN;
+ int rGPIOA1PUDPDN;
+ int reservedA1[2];
+
+ int rGPIOBCON; //0x11400040
+ int rGPIOBDAT;
+ int rGPIOBPUD;
+ int rGPIOBDRV_SR;
+ int rGPIOBCONPDN;
+ int rGPIOBPUDPDN;
+ int reservedB[2];
+
+ int rGPIOC0CON; //0x11400060
+ int rGPIOC0DAT;
+ int rGPIOC0PUD;
+ int rGPIOC0DRV_SR;
+ int rGPIOC0CONPDN;
+ int rGPIOC0PUDPDN;
+ int reservedC0[2];
+
+ int rGPIOC1CON; //0x11400080
+ int rGPIOC1DAT;
+ int rGPIOC1PUD;
+ int rGPIOC1DRV_SR;
+ int rGPIOC1CONPDN;
+ int rGPIOC1PUDPDN;
+ int reservedC1[2];
+
+ int rGPIOD0CON; //0x114000A0
+ int rGPIOD0DAT;
+ int rGPIOD0PUD;
+ int rGPIOD0DRV_SR;
+ int rGPIOD0CONPDN;
+ int rGPIOD0PUDPDN;
+ int reservedD0[2];
+
+ int rGPIOD1CON; //0x114000C0
+ int rGPIOD1DAT;
+ int rGPIOD1PUD;
+ int rGPIOD1DRV_SR;
+ int rGPIOD1CONPDN;
+ int rGPIOD1PUDPDN;
+ int reservedD1[2];
+
+ int rGPIOE0CON; //0x114000E0
+ int rGPIOE0DAT;
+ int rGPIOE0PUD;
+ int rGPIOE0DRV_SR;
+ int rGPIOE0CONPDN;
+ int rGPIOE0PUDPDN;
+ int reservedE0[2];
+
+ int rGPIOE1CON; //0x11400100
+ int rGPIOE1DAT;
+ int rGPIOE1PUD;
+ int rGPIOE1DRV_SR;
+ int rGPIOE1CONPDN;
+ int rGPIOE1PUDPDN;
+ int reservedE1[2];
+
+ int rGPIOE2CON; //0x11400120
+ int rGPIOE2DAT;
+ int rGPIOE2PUD;
+ int rGPIOE2DRV_SR;
+ int rGPIOE2CONPDN;
+ int rGPIOE2PUDPDN;
+ int reservedE2[2];
+
+ int rGPIOE3CON; //0x11400140
+ int rGPIOE3DAT;
+ int rGPIOE3PUD;
+ int rGPIOE3DRV_SR;
+ int rGPIOE3CONPDN;
+ int rGPIOE3PUDPDN;
+ int reservedE3[2];
+
+ int rGPIOE4CON; //0x11400160
+ int rGPIOE4DAT;
+ int rGPIOE4PUD;
+ int rGPIOE4DRV_SR;
+ int rGPIOE4CONPDN;
+ int rGPIOE4PUDPDN;
+ int reservedE4[2];
+
+ int rGPIOF0CON; //0x11400180
+ int rGPIOF0DAT;
+ int rGPIOF0PUD;
+ int rGPIOF0DRV_SR;
+ int rGPIOF0CONPDN;
+ int rGPIOF0PUDPDN;
+ int reservedF0[2];
+
+ int rGPIOF1CON; //0x114001A0
+ int rGPIOF1DAT;
+ int rGPIOF1PUD;
+ int rGPIOF1DRV_SR;
+ int rGPIOF1CONPDN;
+ int rGPIOF1PUDPDN;
+ int reservedF1[2];
+
+ int rGPIOF2CON; //0x114001C0
+ int rGPIOF2DAT;
+ int rGPIOF2PUD;
+ int rGPIOF2DRV_SR;
+ int rGPIOF2CONPDN;
+ int rGPIOF2PUDPDN;
+ int reservedF2[2];
+
+ int rGPIOF3CON; //0x114001E0
+ int rGPIOF3DAT;
+ int rGPIOF3PUD;
+ int rGPIOF3DRV_SR;
+ int rGPIOF3CONPDN;
+ int rGPIOF3PUDPDN;
+ int reservedF3[2];
+
+ int reservedETC0_1[2];
+ int rGPIOETC0PUD; //0x11400208
+ int rGPIOETC0DRV_SR;
+ int reservedETC0_2[4];
+
+ int reservedETC1_1[2];
+ int rGPIOETC1PUD; //0x11400228
+ int rGPIOETC1DRV_SR;
+ int reservedETC1_2[4];
+
+ int reservedETC[304]; //0x11400240 ~ 0x114006FC
+
+ int rEINT1CON; //0x11400700
+ int rEINT2CON;
+ int rEINT3CON;
+ int rEINT4CON;
+ int rEINT5CON;
+ int rEINT6CON;
+ int rEINT7CON;
+ int rEINT8CON;
+ int rEINT9CON;
+ int rEINT10CON;
+ int rEINT11CON;
+ int rEINT12CON;
+ int rEINT13CON;
+ int rEINT14CON;
+ int rEINT15CON;
+ int rEINT16CON;
+
+
+ int reservedEINTCON_3[48];//0x11400740 ~ 0x114007FC
+
+ int rEINT1FLTCON0; //0x11400800
+ int rEINT1FLTCON1;
+ int rEINT2FLTCON0;
+ int rEINT2FLTCON1;
+ int rEINT3FLTCON0;
+ int rEINT3FLTCON1;
+ int rEINT4FLTCON0;
+ int rEINT4FLTCON1;
+ int rEINT5FLTCON0;
+ int rEINT5FLTCON1;
+ int rEINT6FLTCON0;
+ int rEINT6FLTCON1;
+ int rEINT7FLTCON0;
+ int rEINT7FLTCON1;
+ int rEINT8FLTCON0;
+ int rEINT8FLTCON1;
+ int rEINT9FLTCON0;
+ int rEINT9FLTCON1;
+ int rEINT10FLTCON0;
+ int rEINT10FLTCON1;
+ int rEINT11FLTCON0;
+ int rEINT11FLTCON1;
+ int rEINT12FLTCON0;
+ int rEINT12FLTCON1;
+ int rEINT13FLTCON0;
+ int rEINT13FLTCON1;
+ int rEINT14FLTCON0;
+ int rEINT14FLTCON1;
+ int rEINT15FLTCON0;
+ int rEINT15FLTCON1;
+ int rEINT16FLTCON0;
+ int rEINT16FLTCON1;
+
+
+ int reservedFLTCON[32]; //0x11400880 ~ 0x114008FC
+
+ int rEINT1MASK; //0x11400900
+ int rEINT2MASK;
+ int rEINT3MASK;
+ int rEINT4MASK;
+ int rEINT5MASK;
+ int rEINT6MASK;
+ int rEINT7MASK;
+ int rEINT8MASK;
+ int rEINT9MASK;
+ int rEINT10MASK;
+ int rEINT11MASK;
+ int rEINT12MASK;
+ int rEINT13MASK;
+ int rEINT14MASK;
+ int rEINT15MASK;
+ int rEINT16MASK;
+
+ int reservedMASK[48]; //0x11400940 ~ 0x114009FC
+
+ int rEINT1PEND; //0x11400A00
+ int rEINT2PEND;
+ int rEINT3PEND;
+ int rEINT4PEND;
+ int rEINT5PEND;
+ int rEINT6PEND;
+ int rEINT7PEND;
+ int rEINT8PEND;
+ int rEINT9PEND;
+ int rEINT10PEND;
+ int rEINT11PEND;
+ int rEINT12PEND;
+ int rEINT13PEND;
+ int rEINT14PEND;
+ int rEINT15PEND;
+ int rEINT16PEND;
+
+ int reservedPEND[48]; //0x11400A40 ~ 0x11400AFC
+
+ int rEINTGRPPRIXA; // 0x11000B00
+ int rEINTPRIORITYXA;
+ int rEINTSERVICEXA;
+ int rEINTSERVICEPENDXA;
+ int rEINTGRPFIXPRIXA;
+
+ int rEINT1FIXPRI; // 0x11000B14
+ int rEINT2FIXPRI;
+ int rEINT3FIXPRI;
+ int rEINT4FIXPRI;
+ int rEINT5FIXPRI;
+ int rEINT6FIXPRI;
+ int rEINT7FIXPRI;
+ int rEINT8FIXPRI;
+ int rEINT9FIXPRI;
+ int rEINT10FIXPRI;
+ int rEINT11FIXPRI;
+ int rEINT12FIXPRI;
+ int rEINT13FIXPRI;
+ int rEINT14FIXPRI;
+ int rEINT15FIXPRI;
+ int rEINT16FIXPRI;
+
+
+ int reservedFIXPRI[267];//0x11400B54 ~ 0x11400F7C
+
+
+}
+oGPIO_REGS;
+
+
+static volatile void * GPIO_pBase;
+
+volatile int g_IntCnt;
+
+
+//////////
+// Function Name : GPIO_Init
+// Function Desctiption : This function initializes gpio sfr base address
+// Input : NONE
+// Output : NONE
+// Version :
+//
+// Version : v0.1
+void GPIO_Init(void)
+{
+ GPIO_pBase = (void *)GPIO_BASE;
+}
+
+
+//////////
+// Function Name : GPIO_SetFunctionEach
+// Function Desctiption : This function set each GPIO function
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uFunction : Select the function
+// Output : NONE
+//
+// Version : v0.0
+
+void GPIO_SetFunctionEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uFunction)
+{
+ volatile int *pGPIOx_Reg0;
+ volatile int *pGPIO_Base_Addr;
+ int uMuxBit, uOffset;
+ int uConValue;
+
+ uMuxBit = 4; // 4bit
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_Reg0 = pGPIO_Base_Addr + uOffset/4;
+ uConValue = *pGPIOx_Reg0;
+ uConValue = (uConValue & ~(0xF<<(uMuxBit*eBitPos))) | (uFunction<<(uMuxBit*eBitPos));
+ *pGPIOx_Reg0 = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetFunctionAll
+// Function Desctiption : This function set all GPIO function selection
+// Input : Id : GPIO port
+// uValue0 : Write value(control register 0)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetFunctionAll(GPIO_eId Id, int uValue0)
+{
+ volatile int *pGPIOx_Reg0;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_Reg0 = pGPIO_Base_Addr + uOffset/4;
+ *pGPIOx_Reg0 = uValue0;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDataEach
+// Function Desctiption : This function set each GPIO data bit
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDataEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset, uConRegNum;
+ int uDataValue;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4) +uConRegNum;
+ uDataValue = *pGPIOx_DataReg;
+ uDataValue = (uDataValue & ~(0x1<<eBitPos)) | (uValue<<eBitPos);
+ *pGPIOx_DataReg = uDataValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDataAll
+// Function Desctiption : This function set all GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDataAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset, uConRegNum;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4) +uConRegNum;
+ *pGPIOx_DataReg = uValue;
+}
+
+//////////
+// Function Name : GPIO_GetDataEach
+// Function Desctiption : This function get each GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : Data register value
+//
+// Version : v0.0
+int GPIO_GetDataEach(GPIO_eId Id, GPIO_eBitPos eBitPos)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+ uOffset = Id & 0xFFFFFF;
+ uConRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset / 4) + uConRegNum;
+ return ((*pGPIOx_DataReg) & (1 << eBitPos)) ? 1 : 0;
+}
+
+//////////
+// Function Name : GPIO_GetDataAll
+// Function Desctiption : This function get all GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : Data register value
+//
+// Version : v0.0
+int GPIO_GetDataAll(GPIO_eId Id)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4)+ uConRegNum;
+ return (*pGPIOx_DataReg);
+}
+
+
+//////////
+// Function Name : GPIO_SetPullUpDownEach
+// Function Desctiption : This function set each GPIO Pull-up/Down bits
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetPullUpDownEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uOffset;
+ int uPullValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum;
+ uPullValue = *pGPIOx_PullUDReg;
+ uPullValue = (uPullValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pGPIOx_PullUDReg = uPullValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetPullUpDownAll
+// Function Desctiption : This function set all GPIO Pull-up/Down bits
+// Input : Id : GPIO port
+// uValue : value(32bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetPullUpDownAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum;
+ *pGPIOx_PullUDReg = uValue;
+}
+
+
+//////////
+// Function Name : ETC_SetPullUpDownEach
+// Function Desctiption : This function set each ETC Pull-up/Down bits
+// Input : Id : ETC port
+// eBitPos : ETC bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void ETC_SetPullUpDownEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pETCx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset;
+ int uPullValue;
+
+
+ uOffset = Id&0xFFFFFF;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pETCx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) ;
+ uPullValue = *pETCx_PullUDReg;
+ uPullValue = (uPullValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pETCx_PullUDReg = uPullValue;
+}
+
+
+//////////
+// Function Name : ETC_SetPullUpDownAll
+// Function Desctiption : This function set all ETC Pull-up/Down bits
+// Input : Id : ETC port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void ETC_SetPullUpDownAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pETCx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset;
+
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pETCx_PullUDReg = pGPIO_Base_Addr + (uOffset/4);
+ *pETCx_PullUDReg = uValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDSEach
+// Function Desctiption : This function set each GPIO Driving Strength bits
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDSEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_DSReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uOffset;
+ int uDSValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DSReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum+uPullUDRegNum;
+ uDSValue = *pGPIOx_DSReg;
+ uDSValue = (uDSValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pGPIOx_DSReg = uDSValue;
+}
+
+
+//////////
+// Function Name : GPIO_SetDSAll
+// Function Desctiption : This function set All GPIO Driving Strength bits
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDSAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_DSReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uOffset;
+ int uDSValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DSReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum+uPullUDRegNum;
+ uDSValue = *pGPIOx_DSReg;
+ uDSValue = (uDSValue & ~(0xffff)) | uValue;
+ *pGPIOx_DSReg = uDSValue;
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetConRegPDNAll
+// Function Desctiption : This function set all GPIO function when system enter to Power Down mode
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetConRegPDNAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_ConPDNReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uConDSRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+ uConDSRegNum =1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_ConPDNReg = pGPIO_Base_Addr + (uOffset/4) + (uConRegNum + uDataRegNum + uPullUDRegNum+uConDSRegNum);
+ *pGPIOx_ConPDNReg = uValue;
+}
+
+
+//////////
+// Function Name : GPIO_SetPullUDPDNAll
+// Function Desctiption : This function set all GPIO Pull-up/down when system enter to Power Down mode
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.1
+void GPIO_SetPullUDPDNAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_PullUDPDNReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uConDSRegNum, uConPDNRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+ uConDSRegNum =1;
+ uConPDNRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDPDNReg = pGPIO_Base_Addr + (uOffset/4) + (uConRegNum+uDataRegNum+uPullUDRegNum+uConDSRegNum+uConPDNRegNum);
+ *pGPIOx_PullUDPDNReg = uValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint1
+// Function Desctiption : This function setup Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint1(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+// GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT1CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_A0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT1FLTCON0) ; // EINT1FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT1FLTCON1); // EINT1FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT1ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT1PEND;
+ int uConValue;
+
+ pEINT1PEND = &(GPIO_REG->rEINT1PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT1PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT1UnMask
+// Function Desctiption : UnMask the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT1MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT1Mask
+// Function Desctiption : Mask the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT1MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+//////////
+// Function Name : GPIO_SetEint2
+// Function Desctiption : This function setup Eint2[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint2(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT2CON);
+
+
+ if (uEINT_No >5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_A1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT2FLTCON0) ; // EINT2FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT2FLTCON1); // EINT2FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT2ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT2PEND;
+ int uConValue;
+
+ pEINT2PEND = &(GPIO_REG->rEINT2PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT2PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT2UnMask
+// Function Desctiption : UnMask the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT2MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT2Mask
+// Function Desctiption : Mask the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT2MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint3
+// Function Desctiption : This function setup Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint3(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT3CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_B, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT3FLTCON0) ; // EINT3FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT3FLTCON1); // EINT3FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT3ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT3PEND;
+ int uConValue;
+
+ pEINT3PEND = &(GPIO_REG->rEINT3PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT3PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT3UnMask
+// Function Desctiption : UnMask the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT3MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT3Mask
+// Function Desctiption : Mask the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT3MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint4
+// Function Desctiption : This function setup Eint4[4:0]=> GPC0[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint4(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT4CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_C0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT4FLTCON0) ; // EINT4FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT4FLTCON1); // EINT4FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT4ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT4PEND;
+ int uConValue;
+
+ pEINT4PEND = &(GPIO_REG->rEINT4PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT4PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT4UnMask
+// Function Desctiption : UnMask the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT4MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT4Mask
+// Function Desctiption : Mask the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT4MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint5
+// Function Desctiption : This function setup Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint5(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT5CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_C1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT5FLTCON0) ; // EINT5FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT5FLTCON1); // EINT5FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT5ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT5PEND;
+ int uConValue;
+
+ pEINT5PEND = &(GPIO_REG->rEINT5PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT5PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT5UnMask
+// Function Desctiption : UnMask the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT5MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT5Mask
+// Function Desctiption : Mask the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT5MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint6
+// Function Desctiption : This function setup Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint6(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT6CON);
+
+ if (uEINT_No > 3)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 3)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_D0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT6FLTCON0) ; // EINT6FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT6ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT6PEND;
+ int uConValue;
+
+ pEINT6PEND = &(GPIO_REG->rEINT6PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT6PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT6UnMask
+// Function Desctiption : UnMask the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT6MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT6Mask
+// Function Desctiption : Mask the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT6MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint7
+// Function Desctiption : This function setup Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint7(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT7CON);
+
+ if (uEINT_No > 3)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 3)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_D1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT7FLTCON0) ; // EINT7FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT7ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT7PEND;
+ int uConValue;
+
+ pEINT7PEND = &(GPIO_REG->rEINT7PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT7PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT7UnMask
+// Function Desctiption : UnMask the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT7MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT7Mask
+// Function Desctiption : Mask the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT7MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint8
+// Function Desctiption : This function setup Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint8(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT8CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT8FLTCON0) ; // EINT8FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT8FLTCON1); // EINT8FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT8ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT8PEND;
+ int uConValue;
+
+ pEINT8PEND = &(GPIO_REG->rEINT8PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT8PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT8UnMask
+// Function Desctiption : UnMask the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT8MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT8Mask
+// Function Desctiption : Mask the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT8MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+//////////
+// Function Name : GPIO_SetEint9
+// Function Desctiption : This function setup Eint9[7:0]=> GPE1[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint9(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT9CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT9FLTCON0) ; // EINT9FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT9FLTCON1); // EINT9FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT9ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint9[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT9PEND;
+ int uConValue;
+
+ pEINT9PEND = &(GPIO_REG->rEINT9PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT9PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT9UnMask
+// Function Desctiption : UnMask the Eint9[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT9MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT9Mask
+// Function Desctiption : Mask the Eint9[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT9MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint10
+// Function Desctiption : This function setup Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint10(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT10CON);
+
+ if (uEINT_No > 5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT10FLTCON0) ; // EINT10FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <=5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT10FLTCON1); // EINT10FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT10ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT10PEND;
+ int uConValue;
+
+ pEINT10PEND = &(GPIO_REG->rEINT10PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT10PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT10UnMask
+// Function Desctiption : UnMask the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT10MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT10Mask
+// Function Desctiption : Mask the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT10MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint11
+// Function Desctiption : This function setup Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint11(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT11CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT11FLTCON0) ; // EINT11FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT11FLTCON1); // EINT11FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT11ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT11PEND;
+ int uConValue;
+
+ pEINT11PEND = &(GPIO_REG->rEINT11PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT11PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT11UnMask
+// Function Desctiption : UnMask the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT11MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT11Mask
+// Function Desctiption : Mask the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT11MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint12
+// Function Desctiption : This function setup Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint12(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT12CON);
+
+
+ if (uEINT_No >7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E4, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT12FLTCON0) ; // EINT12FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT12FLTCON1); // EINT12FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT12ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT12PEND;
+ int uConValue;
+
+ pEINT12PEND = &(GPIO_REG->rEINT12PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT12PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT12UnMask
+// Function Desctiption : UnMask the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT12MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT12Mask
+// Function Desctiption : Mask the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT12MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint13
+// Function Desctiption : This function setup Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint13(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT13CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT13FLTCON0) ; // EINT13FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT13FLTCON1); // EINT13FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT13ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT13PEND;
+ int uConValue;
+
+ pEINT13PEND = &(GPIO_REG->rEINT13PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT13PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT13UnMask
+// Function Desctiption : UnMask the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT13MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT13Mask
+// Function Desctiption : Mask the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT13MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint14
+// Function Desctiption : This function setup Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint14(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT14CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT14FLTCON0) ; // EINT14FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT14FLTCON1); // EINT14FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT14ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT14PEND;
+ int uConValue;
+
+ pEINT14PEND = &(GPIO_REG->rEINT14PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT14PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT14UnMask
+// Function Desctiption : UnMask the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT14MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT14Mask
+// Function Desctiption : Mask the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT14MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint15
+// Function Desctiption : This function setup Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint15(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT15CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT15FLTCON0) ; // EINT15FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT15FLTCON1); // EINT15FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT15ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT15PEND;
+ int uConValue;
+
+ pEINT15PEND = &(GPIO_REG->rEINT15PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT15PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT15UnMask
+// Function Desctiption : UnMask the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT15MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT15Mask
+// Function Desctiption : Mask the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT15MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint16
+// Function Desctiption : This function setup Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint16(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT16CON);
+
+ if (uEINT_No > 5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT16FLTCON0) ; // EINT16FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT16FLTCON1); // EINT16FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT16ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT16PEND;
+ int uConValue;
+
+ pEINT16PEND = &(GPIO_REG->rEINT16PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT16PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT16UnMask
+// Function Desctiption : UnMask the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT16MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT16Mask
+// Function Desctiption : Mask the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT16MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+//=========================================================
+// C200
+// Don't use eint17~eint20
+//=========================================================
+
+//////////
+// Function Name : GPIO_SetEint21
+// Function Desctiption : This function setup Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint21(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT21CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_J0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT21FLTCON0) ; // EINT21FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT21FLTCON1); // EINT21FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT21ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT21PEND;
+ int uConValue;
+
+ pEINT21PEND = &(GPIO_REG->rEINT21PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT21PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT21UnMask
+// Function Desctiption : UnMask the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT21MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT21Mask
+// Function Desctiption : Mask the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT21MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint22
+// Function Desctiption : This function setup Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint22(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT22CON);
+
+
+ if (uEINT_No >4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_J1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT22FLTCON0) ; // EINT22FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT22FLTCON1); // EINT22FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT22ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT22PEND;
+ int uConValue;
+
+ pEINT22PEND = &(GPIO_REG->rEINT22PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT22PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT22UnMask
+// Function Desctiption : UnMask the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT22MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT22Mask
+// Function Desctiption : Mask the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT22MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint23
+// Function Desctiption : This function setup Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint23(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT23CON);
+
+ if (uEINT_No > 6)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 6)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 6)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_K0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT23FLTCON0) ; // EINT23FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 6)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT23FLTCON1); // EINT23FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT23ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT23ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT23PEND;
+ int uConValue;
+
+ pEINT23PEND = &(GPIO_REG->rEINT23PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT23PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT23UnMask
+// Function Desctiption : UnMask the Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT23UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT23MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT23Mask
+// Function Desctiption : Mask the Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT23Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT23MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint24
+// Function Desctiption : This function setup Eint24[6:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint24(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT24CON);
+
+ if (uEINT_No > 6)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 6)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 6)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_K1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT24FLTCON0) ; // EINT24FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 6)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT24FLTCON1); // EINT24FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT24ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT24ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT24PEND;
+ int uConValue;
+
+ pEINT24PEND = &(GPIO_REG->rEINT24PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT24PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT24UnMask
+// Function Desctiption : UnMask the Eint24[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT24UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT24MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT24Mask
+// Function Desctiption : Mask the Eint24[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT24Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT24MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint25
+// Function Desctiption : This function setup Eint25[6:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint25(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT25CON);
+
+ if (uEINT_No > 6)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 6)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 6)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_K2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT25FLTCON0) ; // EINT25FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 6)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT25FLTCON1); // EINT25FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT25ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint25[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT25ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT25PEND;
+ int uConValue;
+
+ pEINT25PEND = &(GPIO_REG->rEINT25PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT25PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT25UnMask
+// Function Desctiption : UnMask the Eint25[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT25UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT25MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT25Mask
+// Function Desctiption : Mask the Eint25[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT25Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT25MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint26
+// Function Desctiption : This function setup Eint26[6:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint26(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT26CON);
+
+ if (uEINT_No > 6)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 6)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 6)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_K3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT26FLTCON0) ; // EINT26FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 6)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT26FLTCON1); // EINT26FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT26ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint26[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT26ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT26PEND;
+ int uConValue;
+
+ pEINT26PEND = &(GPIO_REG->rEINT26PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT26PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT26UnMask
+// Function Desctiption : UnMask the Eint26[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT26UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT26MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT26Mask
+// Function Desctiption : Mask the Eint26[6:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT26Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT26MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint27
+// Function Desctiption : This function setup Eint27[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint27(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT27CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_L0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT27FLTCON0) ; // EINT27FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT27FLTCON1); // EINT27FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT27ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint27[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT27ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT27PEND;
+ int uConValue;
+
+ pEINT27PEND = &(GPIO_REG->rEINT27PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT27PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT27UnMask
+// Function Desctiption : UnMask the Eint27[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT27UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT27MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT27Mask
+// Function Desctiption : Mask the Eint27[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT27Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT27MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint28
+// Function Desctiption : This function setup Eint28[2:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint28(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT28CON);
+
+ if (uEINT_No > 2)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 2)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 2)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_L1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 2)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT28FLTCON0) ; // EINT28FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT28ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint28[2:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT28ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT28PEND;
+ int uConValue;
+
+ pEINT28PEND = &(GPIO_REG->rEINT28PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT28PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT28UnMask
+// Function Desctiption : UnMask the Eint28[2:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT28UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT28MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT28Mask
+// Function Desctiption : Mask the Eint28[2:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT28Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT28MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint29
+// Function Desctiption : This function setup Eint29[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint29(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT29CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_L2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT29FLTCON0) ; // EINT29FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 6)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT29FLTCON1); // EINT29FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT29ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint29[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT29ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT29PEND;
+ int uConValue;
+
+ pEINT29PEND = &(GPIO_REG->rEINT29PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT29PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT29UnMask
+// Function Desctiption : UnMask the Eint29[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT29UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT29MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT29Mask
+// Function Desctiption : Mask the Eint29[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT29Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT29MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint40
+// Function Desctiption : This function setup Eint40[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 0x1 ~ 0x3F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint40(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT40CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x3f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_X0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT40FLTCON0) ; // EINT40FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <=7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT40FLTCON1); // EINT40FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT40ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint40[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT40ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT40PEND;
+ int uConValue;
+
+ pEINT40PEND = &(GPIO_REG->rEINT40PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT40PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT40UnMask
+// Function Desctiption : UnMask the Eint40[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT40UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT40MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT40Mask
+// Function Desctiption : Mask the Eint40[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT40Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT40MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint41
+// Function Desctiption : This function setup Eint41[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 0x1~0x3F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint41(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT41CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x3f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_X1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT41FLTCON0) ; // EINT41FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT41FLTCON1); // EINT41FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT41ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint41[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT41ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT41PEND;
+ int uConValue;
+
+ pEINT41PEND = &(GPIO_REG->rEINT41PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT41PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT41UnMask
+// Function Desctiption : UnMask the Eint41[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT41UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT41MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT41Mask
+// Function Desctiption : Mask the Eint41[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT41Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT41MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint42
+// Function Desctiption : This function setup Eint42[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 0x1~0x3F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint42(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT42CON);
+
+
+ if (uEINT_No >7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x3f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_X2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT42FLTCON0) ; // EINT42FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT42FLTCON1); // EINT42FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT42ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint42[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT42ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT42PEND;
+ int uConValue;
+
+ pEINT42PEND = &(GPIO_REG->rEINT42PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT42PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT42UnMask
+// Function Desctiption : UnMask the Eint42[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT42UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT42MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT42Mask
+// Function Desctiption : Mask the Eint42[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT42Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT42MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint43
+// Function Desctiption : This function setup Eint43[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 0x1~0x3F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint43(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT43CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x3f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_X3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT43FLTCON0) ; // EINT43FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT43FLTCON1); // EINT43FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT43ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint43[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT43ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT43PEND;
+ int uConValue;
+
+ pEINT43PEND = &(GPIO_REG->rEINT43PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT43PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT43UnMask
+// Function Desctiption : UnMask the Eint43[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT43UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT43MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+
+//////////
+// Function Name : GPIO_EINT43Mask
+// Function Desctiption : Mask the Eint43[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT43Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT43MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////====================================================
+// Function Name : EINT_GRPPRI_XA
+// Function Desctiption : EINT Group priority rotate enable/diable (Fixed)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_GRPPRI_XA(PRI_eTYPE uPriType )
+{
+
+ volatile int *pEINT_GrpPri;
+ int uConValue;
+
+ pEINT_GrpPri = &(GPIO_REG->rEINTGRPPRIXA);
+
+ uConValue = *pEINT_GrpPri;
+ uConValue = (uConValue & ~(0x1))|(uPriType);
+ *pEINT_GrpPri = uConValue;
+
+}
+
+
+//////////
+// Function Name : EINT_GRPPRI_XB
+// Function Desctiption : EINT Group priority rotate enable/diable (Fixed)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_GRPPRI_XB(PRI_eTYPE uPriType )
+{
+
+ volatile int *pEINT_GrpPri;
+ int uConValue;
+
+ pEINT_GrpPri = &(GPIO_REG->rEINTGRPPRIXB);
+
+ uConValue = *pEINT_GrpPri;
+ uConValue = (uConValue & ~(0x1))|(uPriType);
+ *pEINT_GrpPri = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : EINT_PRIORITY_XA
+// Function Desctiption : Every EINT group priority rotate enable/diable (Fixed)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_PRIORITY_XA(int uEINT_No )
+{
+
+ volatile int *pEINT_Priority;
+ int uConValue;
+
+ pEINT_Priority = &(GPIO_REG->rEINTPRIORITYXA);
+
+ uConValue = *pEINT_Priority;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No-1)))|(1<<uEINT_No-1);
+ *pEINT_Priority = uConValue;
+
+}
+
+
+//////////
+// Function Name : EINT_PRIORITY_XB
+// Function Desctiption : Every EINT group priority rotate enable/diable (Fixed)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_PRIORITY_XB(int uEINT_No )
+{
+
+ volatile int *pEINT_Priority;
+ int uConValue;
+
+ pEINT_Priority = &(GPIO_REG->rEINTPRIORITYXB);
+
+ uConValue = *pEINT_Priority;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No-1)))|(1<<uEINT_No-1);
+ *pEINT_Priority = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : Get_EINTSVC_XA
+// Function Desctiption : This function get EINT service group and interrupt number
+// Input : None
+// Output : Data register value
+//
+// Version : v0.0
+
+int Get_EINTSVC_XA(void)
+{
+ volatile int *pEINT_Service;
+ volatile int *pGPIO_Base_Addr;
+
+ pEINT_Service = &(GPIO_REG->rEINTSERVICEXA);
+
+ return (*pEINT_Service);
+}
+
+
+//////////
+// Function Name : Get_EINTSVC_XB
+// Function Desctiption : This function get EINT service group and interrupt number
+// Input : None
+// Output : Data register value
+//
+// Version : v0.0
+
+int Get_EINTSVC_XB(void)
+{
+ volatile int *pEINT_Service;
+ volatile int *pGPIO_Base_Addr;
+
+ pEINT_Service = &(GPIO_REG->rEINTSERVICEXB);
+
+ return (*pEINT_Service);
+}
+
+
+
+//////////
+// Function Name : Get_EINTSVCPND_XA
+// Function Desctiption : This function get pending EINT service group and interrupt number
+// Input : None
+// Output : Data register value
+//
+// Version : v0.0
+
+int Get_EINTSVCPEND_XA(void)
+{
+ volatile int *pEINT_ServicePnd;
+ volatile int *pGPIO_Base_Addr;
+
+ pEINT_ServicePnd = &(GPIO_REG->rEINTSERVICEPENDXA);
+ return (*pEINT_ServicePnd);
+}
+
+
+//////////
+// Function Name : Get_EINTSVCPND_XB
+// Function Desctiption : This function get pending EINT service group and interrupt number
+// Input : None
+// Output : Data register value
+//
+// Version : v0.0
+
+int Get_EINTSVCPEND_XB(void)
+{
+ volatile int *pEINT_ServicePnd;
+ volatile int *pGPIO_Base_Addr;
+
+ pEINT_ServicePnd = &(GPIO_REG->rEINTSERVICEPENDXB);
+ return (*pEINT_ServicePnd);
+}
+
+
+
+//////////
+// Function Name : EINT_GRPFIXPRI_XA
+// Function Desctiption : Group number of the highest priority when fixed group priority mode (EINT1 ~ 16)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_GRPFIXPRI_XA(int uEINT_No )
+{
+
+ volatile int *pEINT_GrpFixPri;
+ int uConValue;
+
+ pEINT_GrpFixPri = &(GPIO_REG->rEINTGRPFIXPRIXA);
+
+ uConValue = *pEINT_GrpFixPri;
+ uConValue = (uConValue & ~(0x1))|(uEINT_No);
+ *pEINT_GrpFixPri = uConValue;
+
+}
+
+
+//////////
+// Function Name : EINT_GRPFIXPRI_XB
+// Function Desctiption : Group number of the highest priority when fixed group priority mode (EINT21 ~ 29)
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_GRPFIXPRI_XB(int uEINT_No )
+{
+
+ volatile int *pEINT_GrpFixPri;
+ int uConValue;
+
+ pEINT_GrpFixPri = &(GPIO_REG->rEINTGRPFIXPRIXB);
+
+ uConValue = *pEINT_GrpFixPri;
+ uConValue = (uConValue & ~(0x1))|(uEINT_No);
+ *pEINT_GrpFixPri = uConValue;
+
+}
+
+
+//////////
+// Function Name : EINT_FIXPRI_XA
+// Function Desctiption : interrupt number of the highest priority when fixed group priority mode (0 ~ 7)
+// Input : uEINT_Grp_No
+// uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_FIXPRI_XA(int uEINT_Grp_No, int uEINT_No )
+{
+
+ volatile int *pEINT_Grpx_FixPri, *pEINT_Grp1_FixPri;
+ int uConValue;
+
+ if(uEINT_Grp_No>0 && uEINT_Grp_No<17) // EINT1 ~ EINT16
+ {
+ pEINT_Grp1_FixPri = &(GPIO_REG->rEINT1FIXPRI);
+ pEINT_Grpx_FixPri = pEINT_Grp1_FixPri + (uEINT_Grp_No-1);
+
+ uConValue = *pEINT_Grpx_FixPri;
+ uConValue = (uConValue & ~(0x7))|(uEINT_No);
+ *pEINT_Grpx_FixPri = uConValue;
+ }
+ else
+ {
+ printf(" select Fail. \n");
+ }
+}
+
+
+//////////
+// Function Name : EINT_FIXPRI_XB
+// Function Desctiption : interrupt number of the highest priority when fixed group priority mode (0 ~ 7)
+// Input : uEINT_Grp_No
+// uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void EINT_FIXPRI_XB(int uEINT_Grp_No, int uEINT_No )
+{
+
+ volatile int *pEINT_Grpx_FixPri, *pEINT_Grp21_FixPri;
+ int uConValue;
+
+ if(uEINT_Grp_No>20 && uEINT_Grp_No<30) // EINT21 ~ EINT29
+ {
+ pEINT_Grp21_FixPri = &(GPIO_REG->rEINT21FIXPRI);
+ pEINT_Grpx_FixPri = pEINT_Grp21_FixPri + (uEINT_Grp_No-1);
+
+ uConValue = *pEINT_Grpx_FixPri;
+ uConValue = (uConValue & ~(0x7))|(uEINT_No);
+ *pEINT_Grpx_FixPri = uConValue;
+ }
+ else
+ {
+ printf(" select Fail. \n");
+ }
+
+}
diff --git a/arch/arm/cpu/armv7/exynos/i2c.c b/arch/arm/cpu/armv7/exynos/i2c.c
new file mode 100644
index 0000000000..4905f0049b
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/i2c.c
@@ -0,0 +1,1096 @@
+/**************************************************************************************
+*
+* Project Name : S5PC210 Validation
+*
+* Copyright 2006 by Samsung Electronics, Inc.
+* All rights reserved.
+*
+* Project Description :
+* This software is only for validating functions of the S5PC210.
+* Anybody can use this software without our permission.
+*
+*--------------------------------------------------------------------------------------
+*
+* File Name : i2c.c
+*
+* File Description : This file implements the API functon for UART.
+*
+* Author : Jang TaeSu
+* Dept. : AP Development Team
+* Created Date : 2010/04/11
+* Version : 0.1
+*
+* History
+* - Create
+* - Modified by Jang TaeSu for S5PC210 (2010/04/11)
+*
+**************************************************************************************/
+#include <s5pc210.h>
+
+#include "gpio.h"
+#include "i2c.h"
+#include "cmu.h"
+
+/*
+ Macro
+*/
+#define HW_REG32(base, offset) (*(volatile unsigned int *)(base + (offset)))
+#define HW_REG16(base, offset) (*(volatile u16 *)(base + (offset)))
+#define HW_REG8(base, offset) (*(volatile u8 *)(base + (offset)))
+
+#define TRUE 1
+#define FALSE 0
+/*
+ Debug Message
+*/
+#define I2C_INIT 0
+#define I2C_ERR 1
+
+/*
+ Global Variable
+*/
+static I2C_CONTEXT g_aI2c[] =
+{
+ { I2C0_BASE, 0, 0, 0, 0, 0 },
+ { I2C1_BASE, 0, 0, 0, 0, 0 },
+ { I2C2_BASE, 0, 0, 0, 0, 0 },
+ { I2C3_BASE, 0, 0, 0, 0, 0 },
+ { I2C4_BASE, 0, 0, 0, 0, 0 },
+ { I2C5_BASE, 0, 0, 0, 0, 0 },
+ { I2C6_BASE, 0, 0, 0, 0, 0 },
+ { I2C7_BASE, 0, 0, 0, 0, 0 },
+ { I2C8_BASE, 0, 0, 0, 0, 0 },
+};
+
+/*
+ Public Function
+*/
+#define TAG_PUBLIC_FUNCTION
+
+bool I2C_InitIp(I2C_CHANNEL eCh, unsigned int nOpClock, unsigned int nTimeOut)
+{
+ I2C_PRESCALER ePrescaler;
+ unsigned int nPclk, nPrescaler;
+
+ nPclk = SYSC_GetClkFreq(SYSC_ACLK_GPL);
+
+ if (!I2C_CalculatePrescaler(nPclk, nOpClock, &ePrescaler, &nPrescaler))
+ {
+ g_aI2c[eCh].eError = I2C_INVALID_TX_CLOCK;
+ return FALSE;
+ }
+
+ g_aI2c[eCh].nOpClock = nPclk/ePrescaler/(nPrescaler+1);
+ g_aI2c[eCh].ePrescaler = ePrescaler;
+ g_aI2c[eCh].nPrescaler = nPrescaler;
+ g_aI2c[eCh].nTimeOut = nTimeOut;
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+ return TRUE;
+}
+
+static bool I2C_SendForGeneral(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aAddr[], unsigned int nNumOfAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = TRUE;
+ unsigned int i;
+
+ if (g_aI2c[eCh].eError == I2C_INVALID_TX_CLOCK)
+ {
+ bResult = FALSE;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_START;
+ goto I2C_Stop;
+ }
+
+ I2C_InitMaster(eCh, g_aI2c[eCh].ePrescaler, g_aI2c[eCh].nPrescaler); // Init I2C
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_TX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+
+ udelay(10);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Write Address
+ //
+ for (i = 0; i < nNumOfAddr; i++)
+ {
+ I2C_WriteData(eCh, aAddr[i]);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_WRITE_ADDRESS;
+ goto I2C_Stop;
+ }
+ }
+
+ //
+ // I2C Phase - Write Data
+ //
+ for (i = 0; i < nNumOfData; i++)
+ {
+ I2C_WriteData(eCh, aData[i]);
+ I2C_ClearIntStatus(eCh);
+
+ udelay(10);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+ }
+
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+I2C_Stop:
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ I2C_SetMode(eCh, DISABLE_I2C); // Deactivate I2C
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ bResult = FALSE;
+ }
+
+ I2C_PrintErrorCase(g_aI2c[eCh].eError);
+
+ return bResult;
+}
+
+static bool I2C_RecvForGeneral(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aAddr[], unsigned int nNumOfAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = TRUE;
+ unsigned int i;
+
+ if (g_aI2c[eCh].eError == I2C_INVALID_TX_CLOCK)
+ {
+ bResult = FALSE;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_START;
+ goto I2C_Stop;
+ }
+
+ I2C_InitMaster(eCh, g_aI2c[eCh].ePrescaler, g_aI2c[eCh].nPrescaler); // Init I2C
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_TX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Write Address
+ //
+ for (i = 0; i < nNumOfAddr; i++)
+ {
+ I2C_WriteData(eCh, aAddr[i]);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_WRITE_ADDRESS;
+ goto I2C_Stop;
+ }
+ }
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ return FALSE;
+ }
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_RX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Read Data
+ //
+ for (i = 0; i < nNumOfData; i++)
+ {
+ if (i < nNumOfData-1)
+ {
+ I2C_SetAckGeneration(eCh, TRUE);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ aData[i] = I2C_ReadData(eCh);
+ }
+ else
+ {
+ I2C_SetAckGeneration(eCh, FALSE);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ aData[i] = I2C_ReadData(eCh);
+ }
+ }
+
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+I2C_Stop:
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ I2C_SetMode(eCh, DISABLE_I2C); // Deactivate I2C
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ bResult = FALSE;
+ }
+
+ I2C_PrintErrorCase(g_aI2c[eCh].eError);
+
+ return bResult;
+}
+
+static bool I2C_SendForHdmiPhy(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = TRUE;
+ unsigned int i;
+
+ if (g_aI2c[eCh].eError == I2C_INVALID_TX_CLOCK)
+ {
+ bResult = FALSE;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_START;
+ goto I2C_Stop;
+ }
+
+ I2C_InitMaster(eCh, g_aI2c[eCh].ePrescaler, g_aI2c[eCh].nPrescaler); // Init I2C
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_TX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Write Data
+ //
+ for (i = 0; i < nNumOfData; i++)
+ {
+ I2C_WriteData(eCh, aData[i]);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+ }
+
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+I2C_Stop:
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ I2C_SetMode(eCh, DISABLE_I2C); // Deactivate I2C
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ bResult = FALSE;
+ }
+
+ I2C_PrintErrorCase(g_aI2c[eCh].eError);
+
+ return bResult;
+}
+
+static bool I2C_RecvForHdmiPhy(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = TRUE;
+ unsigned int i;
+
+ if (g_aI2c[eCh].eError == I2C_INVALID_TX_CLOCK)
+ {
+ bResult = FALSE;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_START;
+ return FALSE;
+ }
+
+ I2C_InitMaster(eCh, g_aI2c[eCh].ePrescaler, g_aI2c[eCh].nPrescaler); // Init I2C
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_RX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+ if (!I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut)) // Workaround for HDMI PHY
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Read Data
+ //
+ for (i = 0; i < nNumOfData; i++)
+ {
+ if (i < nNumOfData-1)
+ {
+ I2C_SetAckGeneration(eCh, TRUE);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE) // Workaround for HDMI PHY
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ aData[i] = I2C_ReadData(eCh);
+ }
+ else
+ {
+ I2C_SetAckGeneration(eCh, FALSE);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ aData[i] = I2C_ReadData(eCh);
+ }
+ }
+
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+I2C_Stop:
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ I2C_SetMode(eCh, DISABLE_I2C); // Deactivate I2C
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ return FALSE;
+ }
+
+ I2C_PrintErrorCase(g_aI2c[eCh].eError);
+
+ return bResult;
+}
+
+static bool I2C_SendForHdmiDdc(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = TRUE;
+ unsigned int i;
+
+ if (g_aI2c[eCh].eError == I2C_INVALID_TX_CLOCK)
+ {
+ bResult = FALSE;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_START;
+ goto I2C_Stop;
+ }
+
+ I2C_InitMaster(eCh, g_aI2c[eCh].ePrescaler, g_aI2c[eCh].nPrescaler); // Init I2C
+
+ //
+ // I2C Phase - START
+ //
+ I2C_SetMode(eCh, MASTER_TX_MODE); // Set Mode
+ I2C_WriteAddress(eCh, ucSlvAddr); // Write Slave Address
+ I2C_GenerateSignal(eCh, START_CONDITION); // Send START Signal
+ if (I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+
+ //
+ // I2C Phase - Write Data
+ //
+ for (i = 0; i < nNumOfData; i++)
+ {
+ I2C_WriteData(eCh, aData[i]);
+ I2C_ClearIntStatus(eCh);
+ if (I2C_WaitForXferNoAck(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_SLAVE_ADDRESS;
+ goto I2C_Stop;
+ }
+ }
+
+ g_aI2c[eCh].eError = I2C_SUCCESS;
+
+I2C_Stop:
+
+ //
+ // I2C Phase - STOP
+ //
+ I2C_GenerateSignal(eCh, STOP_CONDITION); // Send STOP Signal
+ I2C_ClearIntStatus(eCh);
+
+ I2C_SetMode(eCh, DISABLE_I2C); // Deactivate I2C
+
+ //
+ // I2C Phase - Check BUS Status
+ //
+ if (I2C_WaitForBusReady(eCh, g_aI2c[eCh].nTimeOut) == FALSE)
+ {
+ g_aI2c[eCh].eError = I2C_TIMEOUT_BUS_READY_STOP;
+ bResult = FALSE;
+ }
+
+ I2C_PrintErrorCase(g_aI2c[eCh].eError);
+
+ return bResult;
+}
+
+bool I2C_Send(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = FALSE;
+
+ switch (eCh)
+ {
+ case I2C8:
+ bResult = I2C_SendForHdmiPhy(eCh, ucSlvAddr, aData, nNumOfData);
+ break;
+ default:
+ bResult = I2C_SendForGeneral(eCh, ucSlvAddr, NULL, 0, aData, nNumOfData);
+ break;
+ }
+
+ return bResult;
+}
+
+bool I2C_Recv(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = FALSE;
+
+ switch (eCh)
+ {
+ case I2C8:
+ bResult = I2C_RecvForHdmiPhy(eCh, ucSlvAddr, aData, nNumOfData);
+ break;
+ default:
+ bResult = I2C_RecvForGeneral(eCh, ucSlvAddr, NULL, 0, aData, nNumOfData);
+ break;
+ }
+
+ return bResult;
+}
+
+bool I2C_SendEx(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aAddr[], unsigned int nNumOfAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = FALSE;
+
+ switch (eCh)
+ {
+ default:
+ bResult = I2C_SendForGeneral(eCh, ucSlvAddr, aAddr, nNumOfAddr, aData, nNumOfData);
+ break;
+ }
+
+ return bResult;
+}
+
+bool I2C_RecvEx(I2C_CHANNEL eCh, u8 ucSlvAddr, u8 aAddr[], unsigned int nNumOfAddr, u8 aData[], unsigned int nNumOfData)
+{
+ bool bResult = FALSE;
+
+ switch (eCh)
+ {
+ default:
+ bResult = I2C_RecvForGeneral(eCh, ucSlvAddr, aAddr, nNumOfAddr, aData, nNumOfData);
+ break;
+ }
+
+ return bResult;
+}
+
+I2C_ERROR I2C_GetLastError(I2C_CHANNEL eCh)
+{
+ return g_aI2c[eCh].eError;
+}
+
+void I2C_PrintErrorCase(I2C_ERROR eError)
+{
+ switch (eError)
+ {
+ case I2C_INVALID_TX_CLOCK:
+ printf("\n[I2C->ERR] Invalid TX Clock\n");
+ break;
+
+ case I2C_TIMEOUT_BUS_READY_START:
+ printf("\n[I2C->ERR] Timeout BUS Start Status\n");
+ break;
+
+ case I2C_TIMEOUT_SLAVE_ADDRESS:
+ printf("\n[I2C->ERR] Timeout Slave Address\n");
+ break;
+
+ case I2C_TIMEOUT_WRITE_ADDRESS:
+ printf("\n[I2C->ERR] Timeout Write Address\n");
+ break;
+
+ case I2C_TIMEOUT_WRITE_DATA:
+ printf("\n[I2C->ERR] Timeout Write Data\n");
+ break;
+
+ case I2C_TIMEOUT_READ_DATA:
+ printf("\n[I2C->ERR] Timeout Read Data\n");
+ break;
+
+ case I2C_TIMEOUT_BUS_READY_STOP:
+ printf("\n[I2C->ERR] BUS Stop Status\n");
+ break;
+ }
+}
+
+/*
+ Private Function
+*/
+#define TAG_PRIVATE_FUNCTION
+
+bool I2C_InitMaster(I2C_CHANNEL eCh, I2C_PRESCALER ePrescaler, unsigned int nPrescaler)
+{
+ I2C_SetGPIO(eCh, TRUE);
+
+ I2C_SetClock(eCh, ePrescaler, nPrescaler);
+ I2C_SetFilter(eCh, TRUE);
+// I2C_SetOutputDelay(eCh, 0x0);
+ I2C_SetAckGeneration(eCh, FALSE);
+
+ return TRUE;
+}
+
+bool I2C_InitSlave(I2C_CHANNEL eCh, unsigned int uSlaveAddr, I2C_PRESCALER ePrescaler, unsigned int nPrescaler)
+{
+ I2C_SetGPIO(eCh, TRUE);
+
+ I2C_SetClock(eCh, ePrescaler, nPrescaler);
+ I2C_SetSlaveAddress(eCh, uSlaveAddr);
+ I2C_SetFilter(eCh, TRUE);
+// I2C_SetOutputDelay(eCh, 0x0);
+ I2C_SetAckGeneration(eCh, TRUE);
+
+ return TRUE;
+}
+
+bool I2C_CalculatePrescaler(unsigned int uPClk, unsigned int uOpClk, I2C_PRESCALER *pePrescaler, unsigned int *pnPrescaler)
+{
+ unsigned int aTable[32];
+ unsigned int uCalcValue;
+ unsigned int i;
+
+ for (i = 0; i < 32; i++)
+ {
+ if (i < 16)
+ aTable[i] = uPClk / PRESCALER_16 / (i + 1);
+ else
+ aTable[i] = uPClk / PRESCALER_512 / (i - 16 + 1);
+ }
+
+ for (i = 0; i < 31; i++)
+ {
+ uCalcValue = aTable[i];
+
+ if (uCalcValue > 400000)
+ continue;
+
+ if (uCalcValue <= uOpClk)
+ {
+ if (i < 16)
+ {
+ *pePrescaler = PRESCALER_16;
+ *pnPrescaler = i;
+ }
+ else
+ {
+ *pePrescaler = PRESCALER_512;
+ *pnPrescaler = i - 16;
+ }
+
+ return TRUE;
+ }
+ }
+
+ printf("\n[I2C->ERR] Invalid TX Clock\n");
+ *pePrescaler = 0;
+ *pnPrescaler = 0;
+
+ return FALSE;
+}
+
+bool I2C_WaitForBusReady(I2C_CHANNEL eCh, unsigned int nTimeOut)
+{
+ while (--nTimeOut)
+ {
+ if (nTimeOut == I2C_TIMEOUT_INFINITY)
+ ++nTimeOut;
+
+ if (I2C_IsBusReady(eCh))
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+bool I2C_WaitForMatchAddress(I2C_CHANNEL eCh, unsigned int nTimeOut)
+{
+ while (--nTimeOut)
+ {
+ if (nTimeOut == I2C_TIMEOUT_INFINITY)
+ ++nTimeOut;
+
+ if (I2C_GetIntStatus(eCh))
+ {
+ if (I2C_IsMatchAddress(eCh))
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+bool I2C_WaitForXferAck(I2C_CHANNEL eCh, unsigned int nTimeOut)
+{
+ nTimeOut = 1000;
+ while (--nTimeOut)
+ {
+ if (nTimeOut == I2C_TIMEOUT_INFINITY)
+ ++nTimeOut;
+
+ if (I2C_GetIntStatus(eCh))
+ {
+ if (I2C_IsXferAck(eCh))
+ return TRUE;
+ }
+ }
+
+ return FALSE;
+}
+
+bool I2C_WaitForXferNoAck(I2C_CHANNEL eCh, unsigned int nTimeOut)
+{
+ while (--nTimeOut)
+ {
+ if (nTimeOut == I2C_TIMEOUT_INFINITY)
+ ++nTimeOut;
+
+ if (I2C_GetIntStatus(eCh))
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void I2C_SetGPIO(I2C_CHANNEL eCh, bool bEnable)
+{
+ switch (eCh)
+ {
+ case I2C0:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_0, 2); // GPIO set I2C0_SDA
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_1, 2); // GPIO set I2C0_SCL
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_0, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_1, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_0, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_1, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_0, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_1, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C1:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_2, 2); // GPIO set I2C1_SDA
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_3, 2); // GPIO set I2C1_SCL
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_2, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_3, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_2, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_D1, eGPIO_3, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_2, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D1, eGPIO_3, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C2:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_A0, eGPIO_6, 3); // GPIO set I2C2_SDA
+ GPIO_SetFunctionEach(eGPIO_A0, eGPIO_7, 3); // GPIO set I2C2_SCL
+ GPIO_SetPullUpDownEach(eGPIO_A0, eGPIO_6, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_A0, eGPIO_7, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_A0, eGPIO_6, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_A0, eGPIO_7, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_A0, eGPIO_6, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_A0, eGPIO_7, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C3:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_A1, eGPIO_2, 3); // GPIO set I2C3_SDA
+ GPIO_SetFunctionEach(eGPIO_A1, eGPIO_3, 3); // GPIO set I2C3_SCL
+ GPIO_SetPullUpDownEach(eGPIO_A1, eGPIO_2, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_A1, eGPIO_3, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_A1, eGPIO_2, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_A1, eGPIO_3, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_A1, eGPIO_2, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_A1, eGPIO_3, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C4:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_2, 3); // GPIO set I2C4_SDA
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_3, 3); // GPIO set I2C4_SCL
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_2, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_3, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_2, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_3, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_2, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_3, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C5:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_6, 3); // GPIO set I2C5_SDA
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_7, 3); // GPIO set I2C5_SCL
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_6, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_7, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_6, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_B, eGPIO_7, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_6, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_B, eGPIO_7, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C6:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_C1, eGPIO_3, 4); // GPIO set I2C6_SDA
+ GPIO_SetFunctionEach(eGPIO_C1, eGPIO_4, 4); // GPIO set I2C6_SCL
+ GPIO_SetPullUpDownEach(eGPIO_C1, eGPIO_3, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_C1, eGPIO_4, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_C1, eGPIO_3, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_C1, eGPIO_4, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_C1, eGPIO_3, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_C1, eGPIO_4, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C7:
+ if (bEnable)
+ {
+ GPIO_SetFunctionEach(eGPIO_D0, eGPIO_2, 3); // GPIO set I2C7_SDA
+ GPIO_SetFunctionEach(eGPIO_D0, eGPIO_3, 3); // GPIO set I2C7_SCL
+ GPIO_SetPullUpDownEach(eGPIO_D0, eGPIO_2, 0); // GPIO set Pull-up/down Disable
+ GPIO_SetPullUpDownEach(eGPIO_D0, eGPIO_3, 0); // GPIO set Pull-up/down Disable
+ }
+ else
+ {
+ GPIO_SetFunctionEach(eGPIO_D0, eGPIO_2, 0); // GPIO set reset value
+ GPIO_SetFunctionEach(eGPIO_D0, eGPIO_3, 0); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D0, eGPIO_2, 1); // GPIO set reset value
+ GPIO_SetPullUpDownEach(eGPIO_D0, eGPIO_3, 1); // GPIO set reset value
+ }
+ break;
+
+ case I2C8:
+ break;
+ }
+}
+
+void I2C_SetClock(I2C_CHANNEL eCh, I2C_PRESCALER eSource, unsigned int nPrescaler)
+{
+ if (eSource == PRESCALER_512)
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) |= (0x1 << 6);
+ else // PRESCALER_16
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) &= ~(0x1 << 6);
+
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) &= ~(0xF);
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) |= (nPrescaler & 0xF);
+}
+
+void I2C_SetAckGeneration(I2C_CHANNEL eCh, bool bEnable)
+{
+ if (bEnable)
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) |= (0x1 << 7);
+ else
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) &= ~(0x1 << 7);
+}
+
+void I2C_SetSlaveAddress(I2C_CHANNEL eCh, u8 nSlaveAddress)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_ADD) &= ~(0xFF);
+ HW_REG32(g_aI2c[eCh].uBase, I2C_ADD) |= nSlaveAddress;
+}
+
+void I2C_SetFilter(I2C_CHANNEL eCh, bool bEnable)
+{
+ if (bEnable)
+ HW_REG32(g_aI2c[eCh].uBase, I2C_LC ) |= (0x1 << 2);
+ else
+ HW_REG32(g_aI2c[eCh].uBase, I2C_LC ) &= ~(0x1 << 2);
+}
+
+void I2C_SetOutputDelay(I2C_CHANNEL eCh, I2C_OUTPUT_DELAY eOutputDelay)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_LC ) &= ~(0x3);
+ HW_REG32(g_aI2c[eCh].uBase, I2C_LC ) |= (eOutputDelay & 0x3);
+}
+
+void I2C_SetMode(I2C_CHANNEL eCh, I2C_MODE eMode)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) &= ~(0x1 << 4); // Disable I2C
+
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) &= ~(0x3 << 6); // Clear Mode
+
+ I2C_ClearIntStatus(eCh);
+ I2C_DisableInt(eCh); // Disable Interrupt
+
+ switch (eMode)
+ {
+ case MASTER_TX_MODE:
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x3 << 6); // Set Mode
+ break;
+
+ case MASTER_RX_MODE:
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x2 << 6); // Set Mode
+ break;
+
+ case SLAVE_TX_MODE:
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x1 << 6); // Set Mode
+ break;
+
+ case SLAVE_RX_MODE:
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x0 << 6); // Set Mode
+ break;
+
+ default:
+ return;
+ }
+
+ I2C_EnableInt(eCh);
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x1 << 4); // Enable I2C
+}
+
+void I2C_EnableInt(I2C_CHANNEL eCh)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) |= (0x1 << 5);
+}
+
+void I2C_DisableInt(I2C_CHANNEL eCh)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) &= ~(0x1 << 5);
+}
+
+bool I2C_GetIntStatus(I2C_CHANNEL eCh)
+{
+ if (HW_REG32(g_aI2c[eCh].uBase, I2C_CON) & (0x1 << 4))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+void I2C_ClearIntStatus(I2C_CHANNEL eCh)
+{
+ HW_REG32(g_aI2c[eCh].uBase, I2C_CON) &= ~(0x1 << 4);
+}
+
+void I2C_GenerateSignal(I2C_CHANNEL eCh, I2C_CONDITION eCondition)
+{
+ if (eCondition == START_CONDITION)
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) |= (0x1 << 5);
+ else
+ HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) &= ~(0x1 << 5);
+}
+
+bool I2C_GetBusStatus(I2C_CHANNEL eCh)
+{
+ return (HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) >> 5) & 0x1;
+}
+
+bool I2C_IsBusReady(I2C_CHANNEL eCh)
+{
+ if (HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) & (0x1 << 5))
+ return FALSE;
+ else
+ return TRUE;
+}
+
+bool I2C_IsBusBusy(I2C_CHANNEL eCh)
+{
+ if (HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) & (0x1 << 5))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+bool I2C_IsMatchAddress(I2C_CHANNEL eCh)
+{
+ if (HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) & (0x1 << 2))
+ return TRUE;
+ else
+ return FALSE;
+}
+
+bool I2C_IsXferAck(I2C_CHANNEL eCh)
+{
+ if (HW_REG32(g_aI2c[eCh].uBase, I2C_STAT) & (0x1 << 0))
+ return FALSE;
+ else
+ return TRUE;
+}
+
+void I2C_WriteAddress(I2C_CHANNEL eCh, u8 nAddress)
+{
+ HW_REG8(g_aI2c[eCh].uBase, I2C_DS) = nAddress & 0xFE;
+}
+
+void I2C_WriteData(I2C_CHANNEL eCh, u8 nData)
+{
+ HW_REG8(g_aI2c[eCh].uBase, I2C_DS) = nData;
+}
+
+u8 I2C_ReadData(I2C_CHANNEL eCh)
+{
+ return HW_REG8(g_aI2c[eCh].uBase, I2C_DS);
+}
+
+
diff --git a/arch/arm/cpu/armv7/exynos/irom_copy.c b/arch/arm/cpu/armv7/exynos/irom_copy.c
new file mode 100644
index 0000000000..b1fa6634c5
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/irom_copy.c
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#include "UBOOT_SB20_S5PC210S.h"
+#endif
+
+extern ulong movi_read(int dev, ulong start, lbaint_t blkcnt, void *dst);
+extern ulong movi_write(int dev, ulong start, lbaint_t blkcnt, void *src);
+
+typedef u32 (*copy_sd_mmc_to_mem) \
+ (u32 start_block, u32 block_count, u32* dest_addr);
+
+#define ISRAM_ADDRESS 0x02020000
+#define SECURE_CONTEXT_BASE 0x02023000
+#define EXTERNAL_FUNC_ADDRESS (ISRAM_ADDRESS + 0x0030)
+#define EXT_eMMC43_BL2_ByCPU_ADDRESS (EXTERNAL_FUNC_ADDRESS + 0x4)
+#define MSH_ReadFromFIFO_eMMC_ADDRESS (EXTERNAL_FUNC_ADDRESS + 0x14)
+#define MSH_EndBootOp_eMMC_ADDRESS (EXTERNAL_FUNC_ADDRESS + 0x18)
+#define LoadImageFromUsb_ADDRESS (EXTERNAL_FUNC_ADDRESS + 0x40)
+
+#define SDMMC_ReadBlocks_eMMC_ByCPU(uNumOfBlks, uDstAddr) \
+ (((void(*)(u32, u32*))(*((u32 *)EXT_eMMC43_BL2_ByCPU_ADDRESS)))(uNumOfBlks, uDstAddr))
+
+#define SDMMC_ReadBlocks(uStartBlk, uNumOfBlks, uDstAddr) \
+ (((void(*)(u32, u32, u32*))(*((u32 *)EXTERNAL_FUNC_ADDRESS)))(uStartBlk, uNumOfBlks, uDstAddr))
+
+#define LoadImageFromUsb() \
+ (((void(*)())(*((u32 *)LoadImageFromUsb_ADDRESS)))())
+
+#if defined (CONFIG_EXYNOS4212) || defined (CONFIG_ARCH_EXYNOS5)
+typedef u32(*MSH_ReadFromFIFO_eMMC)
+(u32 uNumOfBlks, u32 *uDstAddr);
+#else
+typedef u32(*MSH_ReadFromFIFO_eMMC)
+(u32 RxWaterMark,u32 uNumOfBlks, u32 *uDstAddr);
+#endif
+typedef u32(*MSH_EndBootOp_eMMC)
+(void);
+
+#ifdef CONFIG_CORTEXA5_ENABLE
+void * uboot_memcpy(void * dest,const void *src,size_t count)
+{
+ char *tmp = (char *) dest, *s = (char *) src;
+
+ while (count--)
+ *tmp++ = *s++;
+
+ return dest;
+}
+#endif
+
+void movi_uboot_copy(void)
+{
+#ifdef CONFIG_CORTEXA5_ENABLE
+ SDMMC_ReadBlocks(MOVI_UBOOT_POS, MOVI_UBOOT_BLKCNT, 0x40000000);
+#endif
+ SDMMC_ReadBlocks(MOVI_UBOOT_POS, MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+
+#ifdef CONFIG_SECURE_BOOT
+ if(Check_Signature( (SB20_CONTEXT *)SECURE_CONTEXT_BASE, (unsigned char*)CONFIG_PHY_UBOOT_BASE,
+ PART_SIZE_UBOOT-256, (unsigned char*)(CONFIG_PHY_UBOOT_BASE+PART_SIZE_UBOOT-256), 256 ) != 0) {
+ while(1);
+ }
+#endif
+}
+
+void usb_device_copy(void)
+{
+ LoadImageFromUsb();
+}
+
+void emmc_uboot_copy(void)
+{
+ SDMMC_ReadBlocks_eMMC_ByCPU(MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+}
+
+void emmc_4_4_uboot_copy(void)
+{
+ MSH_ReadFromFIFO_eMMC bl2_copy =
+ (MSH_ReadFromFIFO_eMMC) (*(u32 *) (MSH_ReadFromFIFO_eMMC_ADDRESS));
+
+#if defined (CONFIG_EXYNOS4212) || defined (CONFIG_ARCH_EXYNOS5)
+ bl2_copy(MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+#ifdef CONFIG_CORTEXA5_ENABLE
+ uboot_memcpy(0x40000000, CONFIG_PHY_UBOOT_BASE, PART_SIZE_UBOOT);
+#endif
+#else
+ bl2_copy(0x10, MOVI_UBOOT_BLKCNT, CONFIG_PHY_UBOOT_BASE);
+
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+ if(Check_Signature( (SB20_CONTEXT *)SECURE_CONTEXT_BASE, (unsigned char*)CONFIG_PHY_UBOOT_BASE,
+ PART_SIZE_UBOOT-256, (unsigned char*)(CONFIG_PHY_UBOOT_BASE+PART_SIZE_UBOOT-256), 256 ) != 0) {
+ while(1);
+ }
+#endif
+
+}
+
+void emmc_4_4_endbootOp_eMMC(void)
+{
+ MSH_EndBootOp_eMMC bl2_copy =
+ (MSH_EndBootOp_eMMC) (*(u32 *) (MSH_EndBootOp_eMMC_ADDRESS));
+
+ bl2_copy();
+}
+
+void movi_write_env(ulong addr)
+{
+ movi_write(0, raw_area_control.image[4].start_blk,
+ raw_area_control.image[4].used_blk, addr);
+}
+
+void movi_write_env_card(ulong addr, int card)
+{
+ movi_write(card, raw_area_control.image[4].start_blk, raw_area_control.image[4].used_blk, addr);
+}
+
+void movi_read_env(ulong addr)
+{
+ movi_read(0, raw_area_control.image[4].start_blk,
+ raw_area_control.image[4].used_blk, addr);
+}
+
+void movi_write_bl1(ulong addr, int dev_num)
+{
+ int i;
+ ulong checksum;
+ ulong src;
+ ulong tmp;
+
+ src = addr;
+
+ for(i = 0, checksum = 0;i < (14 * 1024) - 4;i++)
+ {
+ checksum += *(u8*)addr++;
+ }
+
+ tmp = *(ulong*)addr;
+ *(ulong*)addr = checksum;
+
+ movi_write(dev_num, raw_area_control.image[1].start_blk,
+ raw_area_control.image[1].used_blk, src);
+
+ *(ulong*)addr = tmp;
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/movi_partition.c b/arch/arm/cpu/armv7/exynos/movi_partition.c
new file mode 100644
index 0000000000..1cbf81ec7c
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/movi_partition.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+#include <asm/arch/cpu.h>
+
+#ifdef DEBUG_MOVI_PARTITION
+#define dbg(x...) printf(x)
+#else
+#define dbg(x...) do { } while (0)
+#endif
+
+raw_area_t raw_area_control;
+
+int init_raw_area_table(block_dev_desc_t * dev_desc, int location)
+{
+ int i;
+ member_t *image;
+
+ /* init raw_area will be 16MB */
+ raw_area_control.start_blk = 16*1024*1024/MOVI_BLKSIZE;
+ raw_area_control.next_raw_area = 0;
+ strcpy(raw_area_control.description, "initial raw table");
+
+ image = raw_area_control.image;
+
+ /* For eMMC partition BLOCK Change*/
+
+ /* image 0 should be fwbl1 */
+ image[0].start_blk = location;
+
+ image[0].used_blk = MOVI_FWBL1_BLKCNT;
+ image[0].size = PART_SIZE_FWBL1;
+ image[0].attribute = 0x0;
+ strcpy(image[0].description, "fwbl1");
+ dbg("fwbl1: %d\n", image[0].start_blk);
+
+ /* image 1 should be bl1 */
+ image[1].start_blk = image[0].start_blk + MOVI_FWBL1_BLKCNT;
+ image[1].used_blk = MOVI_BL1_BLKCNT;
+ image[1].size = PART_SIZE_BL1;
+ image[1].attribute = 0x1;
+ strcpy(image[1].description, "u-boot parted");
+ dbg("iram block: %d\n", image[1].start_blk);
+
+ /* image 2 should be u-boot */
+ image[2].start_blk = image[1].start_blk + MOVI_BL1_BLKCNT;
+ image[2].used_blk = MOVI_UBOOT_BLKCNT;
+ image[2].size = PART_SIZE_UBOOT;
+ image[2].attribute = 0x2;
+ strcpy(image[2].description, "u-boot");
+ dbg("u-boot: %d\n", image[2].start_blk);
+
+ /* image 3 should be TrustZone S/W */
+ image[3].start_blk = image[2].start_blk + MOVI_UBOOT_BLKCNT;
+ image[3].used_blk = MOVI_TZSW_BLKCNT;
+ image[3].size = PART_SIZE_TZSW;
+ image[3].attribute = 0x9;
+ strcpy(image[3].description, "TrustZone S/W");
+ dbg("TrustZone S/W: %d\n", image[3].start_blk);
+
+ /* image 4 should be environment */
+ image[4].start_blk = image[3].start_blk + MOVI_TZSW_BLKCNT;
+ image[4].used_blk = MOVI_ENV_BLKCNT;
+ image[4].size = CONFIG_ENV_SIZE;
+ image[4].attribute = 0x10;
+ strcpy(image[4].description, "environment");
+ dbg("env: %d\n", image[4].start_blk);
+
+
+ /* For eMMC partition BLOCK Change*/
+ if (location == 0)
+ image[4].start_blk = image[4].start_blk + 1;
+
+ /* image 5 should be kernel */
+ image[5].start_blk = image[4].start_blk + MOVI_ENV_BLKCNT;
+ image[5].used_blk = MOVI_ZIMAGE_BLKCNT;
+ image[5].size = PART_SIZE_KERNEL;
+ image[5].attribute = 0x4;
+ strcpy(image[5].description, "kernel");
+ dbg("knl: %d\n", image[5].start_blk);
+
+ /* image 6 should be RFS */
+ image[6].start_blk = image[5].start_blk + MOVI_ZIMAGE_BLKCNT;
+ image[6].used_blk = MOVI_ROOTFS_BLKCNT;
+ image[6].size = PART_SIZE_ROOTFS;
+ image[6].attribute = 0x8;
+ strcpy(image[6].description, "rfs");
+ dbg("rfs: %d\n", image[6].start_blk);
+
+ /* image 7 should be bl2 */
+ image[7].start_blk = image[0].start_blk + MOVI_FWBL1_BLKCNT;
+ image[7].used_blk = MOVI_BL1_BLKCNT;
+ image[7].size = PART_SIZE_BL1;
+ image[7].attribute = 0x3;
+ strcpy(image[7].description, "bl2");
+ dbg("bl2: %d\n", image[7].start_blk);
+
+ for (i=8; i<15; i++) {
+ raw_area_control.image[i].start_blk = 0;
+ raw_area_control.image[i].used_blk = 0;
+ }
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/nand.c b/arch/arm/cpu/armv7/exynos/nand.c
new file mode 100644
index 0000000000..ee4e4f5d70
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/nand.c
@@ -0,0 +1,1064 @@
+/*
+ * (C) Copyright 2006 DENX Software Engineering
+ * (C) Copyright 2006 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CONFIG_CMD_NAND)
+#include <nand.h>
+#include <asm/arch/s5p_nand.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+
+/* Nand flash definition values by jsgood */
+#define S3C_NAND_TYPE_UNKNOWN 0x0
+#define S3C_NAND_TYPE_SLC 0x1
+#define S3C_NAND_TYPE_MLC 0x2
+#undef S3C_NAND_DEBUG
+
+/* Nand flash global values by jsgood */
+int cur_ecc_mode = 0;
+int nand_type = S3C_NAND_TYPE_UNKNOWN;
+
+/* Nand flash oob definition for SLC 512b page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_16 = {
+// .useecc = MTD_NANDECC_AUTOPLACE, /* Only for U-Boot */
+ .eccbytes = 4,
+ .eccpos = {1, 2, 3, 4},
+ .oobfree = {
+ {.offset = 6,
+ . length = 10}}
+};
+
+/* Nand flash oob definition for SLC 2k page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_64 = {
+// .useecc = MTD_NANDECC_AUTOPLACE, /* Only for U-Boot */
+ .eccbytes = 16,
+ .eccpos = {40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55},
+ .oobfree = {
+ {.offset = 2,
+ .length = 38}}
+};
+
+/* Nand flash oob definition for MLC 2k page size by jsgood */
+static struct nand_ecclayout s3c_nand_oob_mlc_64 = {
+// .useecc = MTD_NANDECC_AUTOPLACE, /* Only for U-Boot */
+ .eccbytes = 32,
+ .eccpos = {
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63},
+ .oobfree = {
+ {.offset = 2,
+ .length = 28}}
+};
+
+/* Nand flash oob definition for 4Kb page size with 8_bit ECC */
+static struct nand_ecclayout s3c_nand_oob_128 = {
+// .useecc = MTD_NANDECC_AUTOPLACE,
+ .eccbytes = 104,
+ .eccpos = {
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39,
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63,
+ 64, 65, 66, 67, 68, 69, 70, 71,
+ 72, 73, 74, 75, 76, 77, 78, 79,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127},
+ .oobfree = {
+ {.offset = 2,
+ .length = 22}}
+};
+#if defined(S3C_NAND_DEBUG)
+/*
+ * Function to print out oob buffer for debugging
+ * Written by jsgood
+ */
+static void print_oob(const char *header, struct mtd_info *mtd)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+
+ printk("%s:\t", header);
+
+ for(i = 0; i < 64; i++)
+ printk("%02x ", chip->oob_poi[i]);
+
+ printk("\n");
+}
+#endif
+
+/*
+ * Hardware specific access to control-lines function
+ * Written by jsgood
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int dat, unsigned int ctrl)
+{
+ unsigned int cur;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ if (ctrl & NAND_NCE) {
+ if (dat != NAND_CMD_NONE) {
+ cur = readl(NFCONT);
+ /* Forced Enable CS */
+ cur &= ~NFCONT_CS;
+
+ writel(cur, NFCONT);
+ }
+ } else {
+ cur = readl(NFCONT);
+ /* Forced Enable CS */
+ cur &= ~NFCONT_CS;
+
+ writel(cur, NFCONT);
+ }
+ }
+
+ if (dat != NAND_CMD_NONE) {
+ if (ctrl & NAND_CLE)
+ writeb(dat, NFCMMD);
+ else if (ctrl & NAND_ALE)
+ writeb(dat, NFADDR);
+ }
+}
+
+/*
+ * Function for checking device ready pin
+ * Written by jsgood
+ */
+static int s3c_nand_device_ready(struct mtd_info *mtdinfo)
+{
+ while (!(readl(NFSTAT) & NFSTAT_RnB)) {}
+ return 1;
+}
+
+/*
+ * We don't use bad block table
+ */
+static int s3c_nand_scan_bbt(struct mtd_info *mtdinfo)
+{
+ return nand_default_bbt(mtdinfo);
+}
+
+#if defined(CFG_NAND_HWECC)
+
+/*
+ * Function for checking ECCEncDone in NFSTAT
+ * Written by jsgood
+ */
+static void s3c_nand_wait_enc(void)
+{
+ while (!(readl(NFECCSTAT) & NFSTAT_ECCENCDONE)) {}
+}
+
+/*
+ * Function for checking ECCDecDone in NFSTAT
+ * Written by jsgood
+ */
+static void s3c_nand_wait_dec(void)
+{
+ while (!(readl(NFECCSTAT) & NFSTAT_ECCDECDONE)) {}
+}
+
+/*
+ * Function for checking ECC Busy
+ * Written by jsgood
+ */
+static void s3c_nand_wait_ecc_busy(void)
+{
+ while (readl(NFECCSTAT) & NFESTAT0_ECCBUSY) {}
+}
+
+/*
+ * This function is called before encoding ecc codes to ready ecc engine.
+ * Written by jsgood
+ */
+static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode)
+{
+ u_long nfcont, nfconf;
+
+ cur_ecc_mode = mode;
+
+ nfconf = readl(NFCONF);
+
+ if (nand_type == S3C_NAND_TYPE_SLC)
+ nfconf &= ~NFCONF_ECC_MLC; /* SLC */
+ else
+ nfconf |= NFCONF_ECC_MLC; /* MLC */
+
+ writel(nfconf, NFCONF);
+
+ /* Initialize & unlock */
+ nfcont = readl(NFCONT);
+ nfcont |= NFCONT_INITMECC;
+ nfcont &= ~NFCONT_MECCLOCK;
+
+ if (nand_type == S3C_NAND_TYPE_MLC) {
+ if (mode == NAND_ECC_WRITE)
+ nfcont |= NFCONT_ECC_ENC;
+ else if (mode == NAND_ECC_READ)
+ nfcont &= ~NFCONT_ECC_ENC;
+ }
+
+ writel(nfcont, NFCONT);
+}
+
+/*
+ * This function is called immediately after encoding ecc codes.
+ * This function returns encoded ecc codes.
+ * Written by jsgood
+ */
+static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+{
+ u_long nfcont, nfmecc0, nfmecc1;
+
+ /* Lock */
+ nfcont = readl(NFCONT);
+ nfcont |= NFCONT_MECCLOCK;
+ writel(nfcont, NFCONT);
+
+ if (nand_type == S3C_NAND_TYPE_SLC) {
+ nfmecc0 = readl(NFMECC0);
+
+ ecc_code[0] = nfmecc0 & 0xff;
+ ecc_code[1] = (nfmecc0 >> 8) & 0xff;
+ ecc_code[2] = (nfmecc0 >> 16) & 0xff;
+ ecc_code[3] = (nfmecc0 >> 24) & 0xff;
+ } else {
+ if (cur_ecc_mode == NAND_ECC_READ)
+ s3c_nand_wait_dec();
+ else {
+ s3c_nand_wait_enc();
+
+ nfmecc0 = readl(NFMECC0);
+ nfmecc1 = readl(NFMECC1);
+
+ ecc_code[0] = nfmecc0 & 0xff;
+ ecc_code[1] = (nfmecc0 >> 8) & 0xff;
+ ecc_code[2] = (nfmecc0 >> 16) & 0xff;
+ ecc_code[3] = (nfmecc0 >> 24) & 0xff;
+ ecc_code[4] = nfmecc1 & 0xff;
+ ecc_code[5] = (nfmecc1 >> 8) & 0xff;
+ ecc_code[6] = (nfmecc1 >> 16) & 0xff;
+ ecc_code[7] = (nfmecc1 >> 24) & 0xff;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This function determines whether read data is good or not.
+ * If SLC, must write ecc codes to controller before reading status bit.
+ * If MLC, status bit is already set, so only reading is needed.
+ * If status bit is good, return 0.
+ * If correctable errors occured, do that.
+ * If uncorrectable errors occured, return -1.
+ * Written by jsgood
+ */
+static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
+{
+ int ret = -1;
+ u_long nfestat0, nfestat1, nfmeccdata0, nfmeccdata1, nfmlcbitpt;
+ u_char err_type;
+
+ if (nand_type == S3C_NAND_TYPE_SLC) {
+ /* SLC: Write ecc to compare */
+ nfmeccdata0 = (read_ecc[1] << 16) | read_ecc[0];
+ nfmeccdata1 = (read_ecc[3] << 16) | read_ecc[2];
+ writel(nfmeccdata0, NFMECCDATA0);
+ writel(nfmeccdata1, NFMECCDATA1);
+
+ /* Read ecc status */
+ nfestat0 = readl(NFESTAT0);
+ err_type = nfestat0 & 0x3;
+
+ switch (err_type) {
+ case 0: /* No error */
+ ret = 0;
+ break;
+
+ case 1: /* 1 bit error (Correctable)
+ (nfestat0 >> 7) & 0x7ff :error byte number
+ (nfestat0 >> 4) & 0x7 :error bit number */
+ printk("s3c-nand: 1 bit error detected at byte %ld, correcting from "
+ "0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]);
+ dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7));
+ printk("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]);
+ ret = 1;
+ break;
+
+ case 2: /* Multiple error */
+ case 3: /* ECC area error */
+ printk("s3c-nand: ECC uncorrectable error detected\n");
+ ret = -1;
+ break;
+ }
+ } else {
+ /* MLC: */
+ s3c_nand_wait_ecc_busy();
+
+ nfestat0 = readl(NFESTAT0);
+ nfestat1 = readl(NFESTAT1);
+ nfmlcbitpt = readl(NFMLCBITPT);
+
+ err_type = (nfestat0 >> 26) & 0x7;
+
+ /* No error, If free page (all 0xff) */
+ if ((nfestat0 >> 29) & 0x1) {
+ err_type = 0;
+ } else {
+ /* No error, If all 0xff from 17th byte in oob (in case of JFFS2 format) */
+ if (dat) {
+ if (dat[17] == 0xff && dat[26] == 0xff && dat[35] == 0xff && dat[44] == 0xff && dat[54] == 0xff)
+ err_type = 0;
+ }
+ }
+
+ switch (err_type) {
+ case 5: /* Uncorrectable */
+ printk("s3c-nand: ECC uncorrectable error detected\n");
+ ret = -1;
+ break;
+
+ case 4: /* 4 bit error (Correctable) */
+ dat[(nfestat1 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 24) & 0xff);
+
+ case 3: /* 3 bit error (Correctable) */
+ dat[nfestat1 & 0x3ff] ^= ((nfmlcbitpt >> 16) & 0xff);
+
+ case 2: /* 2 bit error (Correctable) */
+ dat[(nfestat0 >> 16) & 0x3ff] ^= ((nfmlcbitpt >> 8) & 0xff);
+
+ case 1: /* 1 bit error (Correctable) */
+ printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);
+ dat[nfestat0 & 0x3ff] ^= (nfmlcbitpt & 0xff);
+ ret = err_type;
+ break;
+
+ case 0: /* No error */
+ ret = 0;
+ break;
+ }
+ }
+
+ return ret;
+}
+
+#if defined(CONFIG_NAND_BL1_8BIT_ECC) && defined(CONFIG_S5PC110)
+/***************************************************************
+ * jsgood: Temporary 8 Bit H/W ECC supports for BL1 (6410/6430 only)
+ ***************************************************************/
+static void s3c_nand_wait_ecc_busy_8bit(void)
+{
+ while (readl(NFECCSTAT) & NFESTAT0_ECCBUSY) {
+ }
+}
+
+void s3c_nand_enable_hwecc_8bit(struct mtd_info *mtd, int mode)
+{
+ u_long nfreg;
+
+ cur_ecc_mode = mode;
+
+ if(cur_ecc_mode == NAND_ECC_WRITE){
+
+ /* 8 bit selection */
+ nfreg = readl(NFCONF);
+ nfreg &= ~(0x3 << 23);
+ nfreg |= (0x3<< 23);
+ writel(nfreg, NFCONF);
+
+ /* Set ECC type */
+ nfreg = readl(NFECCCONF);
+ nfreg &= 0xf;
+ nfreg |= 0x3;
+ writel(nfreg, NFECCCONF);
+
+ /* set 8/12/16bit Ecc direction to Encoding */
+ nfreg = readl(NFECCCONT);
+ nfreg &= ~(0x1 << 16);
+ nfreg |= (0x1 << 16);
+ writel(nfreg, NFECCCONT);
+
+ /* set 8/12/16bit ECC message length to msg */
+ nfreg = readl(NFECCCONF);
+ nfreg &= ~((0x3ff<<16));
+ nfreg |= (0x1ff << 16);
+ writel(nfreg, NFECCCONF);
+
+ /* write '1' to clear this bit. */
+ /* clear illegal access status bit */
+ nfreg = readl(NFSTAT);
+ nfreg |= (0x1 << 4);
+ nfreg |= (0x1 << 5);
+ writel(nfreg, NFSTAT);
+
+ /* clear 8/12/16bit ecc encode done */
+ nfreg = readl(NFECCSTAT);
+ nfreg |= (0x1 << 25);
+ writel(nfreg, NFECCSTAT);
+
+ nfreg = readl(NFCONT);
+ nfreg &= ~(0x1 << 1);
+ writel(nfreg, NFCONT);
+
+ /* Initialize & unlock */
+ nfreg = readl(NFCONT);
+ nfreg &= ~NFCONT_MECCLOCK;
+ nfreg |= NFCONT_INITECC;
+ writel(nfreg, NFCONT);
+
+ /* Reset ECC value. */
+ nfreg = readl(NFECCCONT);
+ nfreg |= (0x1 << 2);
+ writel(nfreg, NFECCCONT);
+
+ }else{
+
+ /* set 8/12/16bit ECC message length to msg */
+ nfreg = readl(NFECCCONF);
+ nfreg &= ~((0x3ff<<16));
+ nfreg |= (0x1ff << 16);
+ writel(nfreg, NFECCCONF);
+
+ /* set 8/12/16bit Ecc direction to Decoding */
+ nfreg = readl(NFECCCONT);
+ nfreg &= ~(0x1 << 16);
+ writel(nfreg, NFECCCONT);
+
+ /* write '1' to clear this bit. */
+ /* clear illegal access status bit */
+ nfreg = readl(NFSTAT);
+ nfreg |= (0x1 << 4);
+ nfreg |= (0x1 << 5);
+ writel(nfreg, NFSTAT);
+
+ /* Lock */
+ nfreg = readl(NFCONT);
+ nfreg |= NFCONT_MECCLOCK;
+ writel(nfreg, NFCONT);
+
+ nfreg = readl(NFCONT);
+ nfreg &= ~(0x1 << 1);
+ writel(nfreg, NFCONT);
+
+ /* clear 8/12/16bit ecc decode done */
+ nfreg = readl(NFECCSTAT);
+ nfreg |= (0x1 << 24);
+ writel(nfreg, NFECCSTAT);
+
+ /* Initialize & lock */
+ nfreg = readl(NFCONT);
+ nfreg &= ~NFCONT_MECCLOCK;
+ nfreg |= NFCONT_MECCLOCK;
+ writel(nfreg, NFCONT);
+
+ /* write '1' to clear this bit. */
+ nfreg = readl(NFSTAT);
+ nfreg &= ~(1<<4);
+ nfreg |= (1<<4);
+ writel(nfreg, NFSTAT);
+
+ while(!(nfreg &(1<<4))){
+ nfreg = readl(NFSTAT);
+ }
+
+ /* write '1' to clear this bit. */
+ nfreg = readl(NFSTAT);
+ nfreg &= ~(1<<4);
+ nfreg |= (1<<4);
+ writel(nfreg, NFSTAT);
+
+ /* Initialize & unlock */
+ nfreg = readl(NFCONT);
+ nfreg &= ~NFCONT_MECCLOCK;
+ nfreg |= NFCONT_INITECC;
+ writel(nfreg, NFCONT);
+
+ /* Reset ECC value. */
+ nfreg = readl(NFECCCONT);
+ nfreg |= (0x1 << 2);
+ writel(nfreg, NFECCCONT);
+ }
+
+}
+
+int s3c_nand_calculate_ecc_8bit(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
+{
+ u_long nfcont, nfeccprgecc0, nfeccprgecc1, nfeccprgecc2, nfeccprgecc3;
+
+ if (cur_ecc_mode == NAND_ECC_READ) {
+ /* Lock */
+ nfcont = readl(NFCONT);
+ nfcont |= NFCONT_MECCLOCK;
+ writel(nfcont, NFCONT);
+
+ s3c_nand_wait_dec();
+
+ /* clear 8/12/16bit ecc decode done */
+ nfcont = readl(NFECCSTAT);
+ nfcont |= (1<<24);
+ writel(nfcont, NFECCSTAT);
+
+ s3c_nand_wait_ecc_busy_8bit();
+
+ if(readl(NFSTAT)&(1<<5))
+ {
+ /* clear illegal access status bit */
+ nfcont = readl(NFSTAT);
+ nfcont |= (1<<5);
+ writel(nfcont, NFSTAT);
+
+ printf("\n Accessed locked area!! \n");
+
+ nfcont = readl(NFCONT);
+ nfcont |= (1<<1);
+ writel(nfcont, NFCONT);
+
+ return -1;
+ }
+
+ nfcont = readl(NFCONT);
+ nfcont |= (1<<1);
+ writel(nfcont, NFCONT);
+
+
+ } else {
+ /* Lock */
+ nfcont = readl(NFCONT);
+ nfcont |= NFCONT_MECCLOCK;
+ writel(nfcont, NFCONT);
+
+ s3c_nand_wait_enc();
+
+ /* clear 8/12/16bit ecc encode done */
+ nfcont = readl(NFECCSTAT);
+ nfcont |= (1<<25);
+ writel(nfcont, NFECCSTAT);
+
+ nfeccprgecc0 = readl(NFECCPRGECC0);
+ nfeccprgecc1 = readl(NFECCPRGECC1);
+ nfeccprgecc2 = readl(NFECCPRGECC2);
+ nfeccprgecc3 = readl(NFECCPRGECC3);
+
+ ecc_code[0] = nfeccprgecc0 & 0xff;
+ ecc_code[1] = (nfeccprgecc0 >> 8) & 0xff;
+ ecc_code[2] = (nfeccprgecc0 >> 16) & 0xff;
+ ecc_code[3] = (nfeccprgecc0 >> 24) & 0xff;
+ ecc_code[4] = nfeccprgecc1 & 0xff;
+ ecc_code[5] = (nfeccprgecc1 >> 8) & 0xff;
+ ecc_code[6] = (nfeccprgecc1 >> 16) & 0xff;
+ ecc_code[7] = (nfeccprgecc1 >> 24) & 0xff;
+ ecc_code[8] = nfeccprgecc2 & 0xff;
+ ecc_code[9] = (nfeccprgecc2 >> 8) & 0xff;
+ ecc_code[10] = (nfeccprgecc2 >> 16) & 0xff;
+ ecc_code[11] = (nfeccprgecc2 >> 24) & 0xff;
+ ecc_code[12] = nfeccprgecc3 & 0xff;
+
+
+
+ }
+
+ return 0;
+}
+
+int s3c_nand_correct_data_8bit(struct mtd_info *mtd, u_char *dat)
+{
+ int ret = -1;
+ u_long nf8eccerr0, nf8eccerr1, nf8eccerr2, nf8eccerr3, nf8eccerr4, nfmlc8bitpt0, nfmlc8bitpt1;
+ u_char err_type;
+
+ s3c_nand_wait_ecc_busy_8bit();
+
+ nf8eccerr0 = readl(NFECCSECSTAT);
+ nf8eccerr1 = readl(NFECCERL0);
+ nf8eccerr2 = readl(NFECCERL1);
+ nf8eccerr3 = readl(NFECCERL2);
+ nf8eccerr4 = readl(NFECCERL3);
+ nfmlc8bitpt0 = readl(NFECCERP0);
+ nfmlc8bitpt1 = readl(NFECCERP1);
+
+ err_type = (nf8eccerr0) & 0xf;
+
+ /* No error, If free page (all 0xff) */
+ if ((nf8eccerr0 >> 29) & 0x1)
+ err_type = 0;
+
+ switch (err_type) {
+ case 9: /* Uncorrectable */
+ printk("s3c-nand: ECC uncorrectable error detected\n");
+ ret = -1;
+ break;
+
+ case 8: /* 8 bit error (Correctable) */
+ dat[(nf8eccerr4 >> 16) & 0x3ff] ^= ((nfmlc8bitpt1 >> 24) & 0xff);
+
+ case 7: /* 7 bit error (Correctable) */
+ dat[(nf8eccerr4) & 0x3ff] ^= ((nfmlc8bitpt1 >> 16) & 0xff);
+
+ case 6: /* 6 bit error (Correctable) */
+ dat[(nf8eccerr3 >> 16) & 0x3ff] ^= ((nfmlc8bitpt1 >> 8) & 0xff);
+
+ case 5: /* 5 bit error (Correctable) */
+ dat[(nf8eccerr3) & 0x3ff] ^= ((nfmlc8bitpt1) & 0xff);
+
+ case 4: /* 8 bit error (Correctable) */
+ dat[(nf8eccerr2 >> 16) & 0x3ff] ^= ((nfmlc8bitpt0 >> 24) & 0xff);
+
+ case 3: /* 7 bit error (Correctable) */
+ dat[(nf8eccerr2) & 0x3ff] ^= ((nfmlc8bitpt0>> 16) & 0xff);
+
+ case 2: /* 6 bit error (Correctable) */
+ dat[(nf8eccerr1 >> 16) & 0x3ff] ^= ((nfmlc8bitpt0>> 8) & 0xff);
+
+ case 1: /* 1 bit error (Correctable) */
+ printk("s3c-nand: %d bit(s) error detected, corrected successfully\n", err_type);
+ dat[(nf8eccerr1) & 0x3ff] ^= ((nfmlc8bitpt0) & 0xff);
+ ret = err_type;
+ break;
+
+ case 0: /* No error */
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+
+void s3c_nand_write_page_8bit(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ u_long nfreg;
+ int i, eccsize = 512;
+ int eccbytes = 13;
+ int eccsteps = mtd->writesize / eccsize;
+ int badoffs = mtd->writesize == 512 ? NAND_SMALL_BADBLOCK_POS : NAND_LARGE_BADBLOCK_POS;
+
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint8_t *p = buf;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+ s3c_nand_calculate_ecc_8bit(mtd, p, &ecc_calc[i]);
+ }
+
+ chip->oob_poi[badoffs] = 0xff;
+ for (i = 0; i <= eccbytes * (mtd->writesize / eccsize); i++) {
+#if defined(CONFIG_EVT1)
+ chip->oob_poi[i+12] = ecc_calc[i];
+#else
+ chip->oob_poi[i] = ecc_calc[i];
+#endif
+ }
+
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+int s3c_nand_read_page_8bit(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf)
+{
+ u_long nfreg;
+ int i, stat, eccsize = 512;
+ int eccbytes = 13;
+ int eccsteps = mtd->writesize / eccsize;
+ int col = 0;
+ uint8_t *p = buf;
+
+ /* Step1: read whole oob */
+ col = mtd->writesize;
+#if defined(CONFIG_EVT1)
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col+12, -1);
+#else
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+#endif
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ col = 0;
+
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ s3c_nand_enable_hwecc_8bit(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->write_buf(mtd, chip->oob_poi + (((mtd->writesize / eccsize) - eccsteps) * eccbytes), eccbytes);
+ s3c_nand_calculate_ecc_8bit(mtd, 0, 0);
+ stat = s3c_nand_correct_data_8bit(mtd, p);
+
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+
+ col = eccsize * ((mtd->writesize / eccsize) + 1 - eccsteps);
+ }
+
+ return 0;
+}
+
+int s3c_nand_read_oob_8bit(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd)
+{
+ int eccbytes = chip->ecc.bytes;
+ int secc_start = mtd->oobsize - eccbytes;
+
+ if (sndcmd) {
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+ sndcmd = 0;
+ }
+
+ chip->read_buf(mtd, chip->oob_poi, 0); //secc_start);
+ return sndcmd;
+}
+
+int s3c_nand_write_oob_8bit(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+ int status = 0;
+ int eccbytes = chip->ecc.bytes;
+ int secc_start = mtd->oobsize - eccbytes;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ /* spare area */
+ chip->write_buf(mtd, chip->oob_poi, 0); //secc_start);
+
+ /* Send command to program the OOB data */
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+ status = chip->waitfunc(mtd, chip);
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+/********************************************************/
+#endif
+
+static int s3c_nand_write_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+ int page)
+{
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ int status = 0;
+ int eccbytes = chip->ecc.bytes;
+ int secc_start = mtd->oobsize - eccbytes;
+ int i;
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+
+ /* spare area */
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, chip->oob_poi, secc_start);
+ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
+
+ for (i = 0; i < eccbytes; i++)
+ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
+
+ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+ /* Send command to program the OOB data */
+ chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+ status = chip->waitfunc(mtd, chip);
+
+ return status & NAND_STATUS_FAIL ? -EIO : 0;
+}
+
+static int s3c_nand_read_oob_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+ int page, int sndcmd)
+{
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ int eccbytes = chip->ecc.bytes;
+ int secc_start = mtd->oobsize - eccbytes;
+
+ if (sndcmd) {
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+ sndcmd = 0;
+ }
+
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, chip->oob_poi, secc_start);
+ chip->ecc.calculate(mtd, 0, &ecc_calc[chip->ecc.total]);
+ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+ /* jffs2 special case */
+ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
+ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
+
+ return sndcmd;
+}
+
+static void s3c_nand_write_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int secc_start = mtd->oobsize - eccbytes;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ const uint8_t *p = buf;
+
+ uint32_t *eccpos = chip->ecc.layout->eccpos;
+
+ /* main area */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+ }
+
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[eccpos[i]] = ecc_calc[i];
+
+ /* spare area */
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, chip->oob_poi, secc_start);
+ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
+
+ for (i = 0; i < eccbytes; i++)
+ chip->oob_poi[secc_start + i] = ecc_calc[chip->ecc.total + i];
+
+ chip->write_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+}
+
+static int s3c_nand_read_page_1bit(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf)
+{
+ int i, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int secc_start = mtd->oobsize - eccbytes;
+ int col = 0;
+ uint8_t *p = buf;
+ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+
+ col = mtd->writesize;
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+
+ /* spare area */
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, chip->oob_poi, secc_start);
+ chip->ecc.calculate(mtd, p, &ecc_calc[chip->ecc.total]);
+ chip->read_buf(mtd, chip->oob_poi + secc_start, eccbytes);
+
+ /* jffs2 special case */
+ if (!(chip->oob_poi[2] == 0x85 && chip->oob_poi[3] == 0x19))
+ chip->ecc.correct(mtd, chip->oob_poi, chip->oob_poi + secc_start, 0);
+
+ col = 0;
+
+ /* main area */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+
+ stat = chip->ecc.correct(mtd, p, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), 0);
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+
+ col = eccsize * (chip->ecc.steps + 1 - eccsteps);
+ }
+
+ return 0;
+}
+
+/*
+ * Hardware specific page read function for MLC.
+ * Written by jsgood
+ */
+static int s3c_nand_read_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf)
+{
+ int i, stat, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ int col = 0;
+ uint8_t *p = buf;
+ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+
+ /* Step1: read whole oob */
+ col = mtd->writesize;
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ col = 0;
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ chip->ecc.hwctl(mtd, NAND_ECC_READ);
+ chip->read_buf(mtd, p, eccsize);
+ chip->write_buf(mtd, chip->oob_poi + mecc_pos[0] + ((chip->ecc.steps - eccsteps) * eccbytes), eccbytes);
+ chip->ecc.calculate(mtd, 0, 0);
+ stat = chip->ecc.correct(mtd, p, 0, 0);
+
+ if (stat == -1)
+ mtd->ecc_stats.failed++;
+
+ col = eccsize * (chip->ecc.steps + 1 - eccsteps);
+ }
+
+ return 0;
+}
+
+/*
+ * Hardware specific page write function for MLC.
+ * Written by jsgood
+ */
+static void s3c_nand_write_page_4bit(struct mtd_info *mtd, struct nand_chip *chip,
+ const uint8_t *buf)
+{
+ int i, eccsize = chip->ecc.size;
+ int eccbytes = chip->ecc.bytes;
+ int eccsteps = chip->ecc.steps;
+ const uint8_t *p = buf;
+ uint8_t *ecc_calc = chip->buffers->ecccalc;
+ uint32_t *mecc_pos = chip->ecc.layout->eccpos;
+
+ /* Step1: write main data and encode mecc */
+ for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
+ chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
+ chip->write_buf(mtd, p, eccsize);
+ chip->ecc.calculate(mtd, p, &ecc_calc[i]);
+ }
+
+ /* Step2: save encoded mecc */
+ for (i = 0; i < chip->ecc.total; i++)
+ chip->oob_poi[mecc_pos[i]] = ecc_calc[i];
+
+ chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+#endif
+
+/*
+ * Board-specific NAND initialization. The following members of the
+ * argument are board-specific (per include/linux/mtd/nand.h):
+ * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
+ * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
+ * - hwcontrol: hardwarespecific function for accesing control-lines
+ * - dev_ready: hardwarespecific function for accesing device ready/busy line
+ * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
+ * only be provided if a hardware ECC is available
+ * - eccmode: mode of ecc, see defines
+ * - chip_delay: chip dependent delay for transfering data from array to
+ * read regs (tR)
+ * - options: various chip options. They can partly be set to inform
+ * nand_scan about special functionality. See the defines for further
+ * explanation
+ * Members with a "?" were not set in the merged testing-NAND branch,
+ * so they are not set here either.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+#if defined(CFG_NAND_HWECC)
+ int i;
+ u_char tmp;
+ struct nand_flash_dev *type = NULL;
+#endif
+
+ NFCONT_REG &= ~NFCONT_WP;
+ nand->IO_ADDR_R = (void __iomem *)(NFDATA);
+ nand->IO_ADDR_W = (void __iomem *)(NFDATA);
+ nand->cmd_ctrl = s3c_nand_hwcontrol;
+ nand->dev_ready = s3c_nand_device_ready;
+ nand->scan_bbt = s3c_nand_scan_bbt;
+ nand->options = 0;
+
+#if defined(CFG_NAND_FLASH_BBT)
+ nand->options |= NAND_USE_FLASH_BBT;
+#else
+ nand->options |= NAND_SKIP_BBTSCAN;
+#endif
+
+#if defined(CFG_NAND_HWECC)
+ nand->ecc.mode = NAND_ECC_HW;
+ nand->ecc.hwctl = s3c_nand_enable_hwecc;
+ nand->ecc.calculate = s3c_nand_calculate_ecc;
+ nand->ecc.correct = s3c_nand_correct_data;
+
+ s3c_nand_hwcontrol(0, NAND_CMD_READID, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ s3c_nand_hwcontrol(0, 0x00, NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
+ s3c_nand_hwcontrol(0, 0x00, NAND_NCE | NAND_ALE);
+ s3c_nand_hwcontrol(0, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ s3c_nand_device_ready(0);
+
+ tmp = readb(nand->IO_ADDR_R); /* Maf. ID */
+ tmp = readb(nand->IO_ADDR_R); /* Device ID */
+
+ for (i = 0; nand_flash_ids[i].name != NULL; i++) {
+ if (tmp == nand_flash_ids[i].id) {
+ type = &nand_flash_ids[i];
+ break;
+ }
+ }
+
+ if (type == NULL)
+ return -1;
+
+ nand->cellinfo = readb(nand->IO_ADDR_R); /* 3rd byte */
+ tmp = readb(nand->IO_ADDR_R); /* 4th byte */
+
+ if (!type->pagesize) {
+ if (((nand->cellinfo >> 2) & 0x3) == 0) {
+ nand_type = S3C_NAND_TYPE_SLC;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 4;
+
+ if ((1024 << (tmp & 0x3)) > 512) {
+ nand->ecc.read_page = s3c_nand_read_page_1bit;
+ nand->ecc.write_page = s3c_nand_write_page_1bit;
+ nand->ecc.read_oob = s3c_nand_read_oob_1bit;
+ nand->ecc.write_oob = s3c_nand_write_oob_1bit;
+ nand->ecc.layout = &s3c_nand_oob_64;
+ nand->ecc.hwctl = s3c_nand_enable_hwecc;
+ nand->ecc.calculate = s3c_nand_calculate_ecc;
+ nand->ecc.correct = s3c_nand_correct_data;
+ nand->options |= NAND_NO_SUBPAGE_WRITE;
+ } else {
+ nand->ecc.layout = &s3c_nand_oob_16;
+ }
+ } else {
+ nand_type = S3C_NAND_TYPE_MLC;
+ nand->options |= NAND_NO_SUBPAGE_WRITE; /* NOP = 1 if MLC */
+ nand->ecc.read_page = s3c_nand_read_page_4bit;
+ nand->ecc.write_page = s3c_nand_write_page_4bit;
+ nand->ecc.size = 512;
+ nand->ecc.bytes = 8; /* really 7 bytes */
+ nand->ecc.layout = &s3c_nand_oob_mlc_64;
+ }
+ } else {
+ nand_type = S3C_NAND_TYPE_SLC;
+ nand->ecc.size = 512;
+ nand->cellinfo = 0;
+ nand->ecc.bytes = 4;
+ nand->ecc.layout = &s3c_nand_oob_16;
+ }
+#else
+ nand->ecc.mode = NAND_ECC_SOFT;
+#endif
+ return 0;
+}
+#endif /* (CONFIG_CMD_NAND) */
diff --git a/arch/arm/cpu/armv7/exynos/nand_cp.c b/arch/arm/cpu/armv7/exynos/nand_cp.c
new file mode 100644
index 0000000000..d925e8b243
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/nand_cp.c
@@ -0,0 +1,145 @@
+/*
+ * $Id: nand_cp.c,v 1.1 2008/11/20 01:08:36 boyko Exp $
+ *
+ * (C) Copyright 2006 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * You must make sure that all functions in this file are designed
+ * to load only U-Boot image.
+ *
+ * So, DO NOT USE in common read.
+ *
+ * By scsuh.
+ */
+
+
+#include <common.h>
+
+#ifdef CONFIG_S5PC210
+#include <asm/io.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/s5p_nand.h>
+
+
+#define NAND_CONTROL_ENABLE() (NFCONT_REG |= (1 << 0))
+
+/*
+ * address format
+ * 17 16 9 8 0
+ * --------------------------------------------
+ * | block(12bit) | page(5bit) | offset(9bit) |
+ * --------------------------------------------
+ */
+
+static int nandll_read_page (uchar *buf, ulong addr, int large_block)
+{
+ int i;
+ int page_size = 512;
+
+ if (large_block)
+ page_size = 2048;
+
+ NAND_ENABLE_CE();
+
+ NFCMD_REG = NAND_CMD_READ0;
+
+ /* Write Address */
+ NFADDR_REG = 0;
+
+ if (large_block)
+ NFADDR_REG = 0;
+
+ NFADDR_REG = (addr) & 0xff;
+ NFADDR_REG = (addr >> 8) & 0xff;
+ NFADDR_REG = (addr >> 16) & 0xff;
+
+ if (large_block)
+ NFCMD_REG = NAND_CMD_READSTART;
+
+ NF_TRANSRnB();
+
+ /* for compatibility(2460). u32 cannot be used. by scsuh */
+ for(i=0; i < page_size; i++) {
+ *buf++ = NFDATA8_REG;
+ }
+
+ NAND_DISABLE_CE();
+ return 0;
+}
+
+/*
+ * Read data from NAND.
+ */
+static int nandll_read_blocks (ulong dst_addr, ulong size, int large_block)
+{
+ uchar *buf = (uchar *)dst_addr;
+ int i;
+ uint page_shift = 9;
+
+ if (large_block)
+ page_shift = 11;
+
+ /* skip first 64 blocks (BL1 32 + BL2 32) for secure boot */
+ size -= (1<<(page_shift+6));
+//printk("size:0x%x\n",size);
+ /* Read the rest pages */
+ //for (i = 64; i < (size>>page_shift); i++, buf+=(1<<page_shift)) {
+ for (i = 64; i < (size>>page_shift)+64; i++, buf+=(1<<page_shift)) {
+ nandll_read_page(buf, i, large_block);
+ }
+
+ return 0;
+}
+
+int copy_uboot_to_ram (void)
+{
+ int large_block = 8;
+ int i;
+
+ vu_char id;
+
+ NAND_CONTROL_ENABLE();
+ NAND_ENABLE_CE();
+ NFCMD_REG = NAND_CMD_READID;
+ NFADDR_REG = 0x00;
+
+ /* wait for a while */
+ for (i=0; i<200; i++);
+ id = NFDATA8_REG;
+ id = NFDATA8_REG;
+
+ if (id > 0x80)
+ large_block = 1;
+
+ /* read NAND Block.
+ * 128KB ->240KB because of U-Boot size increase. by scsuh
+ * So, read 0x3c000 bytes not 0x20000(128KB).
+ */
+ //return nandll_read_blocks(CFG_PHY_UBOOT_BASE, COPY_BL2_SIZE, large_block);
+ i = nandll_read_blocks(CFG_PHY_UBOOT_BASE, COPY_BL2_SIZE, large_block);
+ //i = nandll_read_blocks(CFG_PHY_KERNEL_BASE, COPY_BL2_SIZE, large_block);
+//while(1);
+ return i;
+}
+
+#endif
+
diff --git a/arch/arm/cpu/armv7/exynos/nand_write_bl.c b/arch/arm/cpu/armv7/exynos/nand_write_bl.c
new file mode 100644
index 0000000000..360bcf8996
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/nand_write_bl.c
@@ -0,0 +1,286 @@
+/*
+ * $Id: nand_wite_bl.c,v 1.1 2008/11/20 01:08:36 boyko Exp $
+ *
+ * (C) Copyright 2006 Samsung Electronics
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * You must make sure that all functions in this file are designed
+ * to write only U-Boot BL1/2 image.
+ *
+ * So, DO NOT USE in common write.
+ *
+ * By scsuh.
+ */
+
+
+#include <common.h>
+
+#ifdef CONFIG_S5PC210
+#include <asm/io.h>
+#include <linux/mtd/nand.h>
+#include <asm/arch/s5p_nand.h>
+
+
+#define MAX_ECC_LEN 96
+#define NAND_RANDOMIZER_SEED (0x59A9)
+#define NFRANDSEED (ELFIN_NAND_BASE+0x20050)
+
+#define NAND_CONTROL_ENABLE() (writel(readl(NFCONT)|(1<<0),NFCONT))
+#define NAND_SEL_ECC16() (writel((readl(NFECCCONF)&~(0xf<<0))|(0x5<<0),NFECCCONF))
+#define NAND_ECC_SETDIR_ENC() (writel(readl(NFECCCONT)|(1<<16),NFECCCONT))
+#define NAND_ECC_SET_MSGLEN(msg) (writel((readl(NFECCCONF)&~(0x7ff<<16))|(((msg)-1)<<16),NFECCCONF))
+#define NAND_CLEAR_RB() (writel(readl(NFSTAT)|(1<<4),NFSTAT))
+#define NAND_ILL_ACC_CLEAR() (writel(readl(NFSTAT)|(1<<5),NFSTAT))
+#define NAND_ECC_ENC_DONE_CLEAR() (writel(readl(NFECCSTAT)|(1<<25),NFECCSTAT))
+#define NAND_nFCE_L(n) (writel(readl(NFCONT)&~(1<<((n>1)?(20+n):(n+1))),NFCONT))
+#define NAND_nFCE_H(n) (writel(readl(NFCONT)|(1<<((n>1)?(20+n):(n+1))),NFCONT))
+#define NAND_CMD(cmd) (writel((cmd),NFCMMD))
+#define NAND_ADDR(addr) (writel((addr),NFADDR))
+#define NAND_MECC_UnLock() (writel(readl(NFCONT)&~(1<<7),NFCONT))
+#define NAND_MECC_Lock() (writel(readl(NFCONT)|(1<<7),NFCONT))
+#define NAND_RSTECC() {(writel(readl(NFCONT)|((1<<5)|(1<<4)),NFCONT));\
+ (writel(readl(NFECCCONT)|(1<<2),NFECCCONT));}
+#define NAND_ECC_LOOP_UNTIL_ENC_DONE() {while(!(readl(NFECCSTAT)&(1<<25)));}
+#define NAND_IS_LOCKED() (readl(NFSTAT)&(1<<5))
+#define NAND_DETECT_RB() {while(!(readl(NFSTAT)&(1<<4)));}
+
+#define NAND_SET_RND_SEED(seed) (writel((seed),NFRANDSEED))
+#define NAND_RESET_RND() (writel(readl(NFECCCONT)|(1<<23),NFECCCONT))
+#define NAND_ENABLE_RND() (writel(readl(NFECCCONT)|(1<<22),NFECCCONT))
+#define NAND_DISABLE_RND() (writel(readl(NFECCCONT)&~(1<<22),NFECCCONT))
+
+
+
+static void nandll_calculate_ecc(uchar *ecc_code)
+{
+ int i;
+ u_long uRead0, uRead1, uRead2, uRead3, uRead4, uRead5, uRead6;
+
+ uRead0 = readl(NFECCPRGECC0);
+ uRead1 = readl(NFECCPRGECC1);
+ uRead2 = readl(NFECCPRGECC2);
+ uRead3 = readl(NFECCPRGECC3);
+ uRead4 = readl(NFECCPRGECC4);
+ uRead5 = readl(NFECCPRGECC5);
+ uRead6 = readl(NFECCPRGECC6);
+
+ for(i=0;i<4; i++) *ecc_code++ = (uRead0>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead1>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead2>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead3>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead4>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead5>>(8*i))&0xff;
+ for(i=0;i<4; i++) *ecc_code++ = (uRead6>>(8*i))&0xff;
+
+ return;
+}
+
+
+
+/*
+ * address format
+ * 17 16 9 8 0
+ * --------------------------------------------
+ * | block(12bit) | page(5bit) | offset(9bit) |
+ * --------------------------------------------
+ */
+static int nandll_write_page (uchar *buf, ulong addr, int large_block)
+{
+ int i;
+ int page_size = 512, ECCLen=26;
+ u16 uRandomSeed=NAND_RANDOMIZER_SEED;
+ uchar ECCData[MAX_ECC_LEN];
+
+ NAND_CLEAR_RB();
+ NAND_ILL_ACC_CLEAR();
+ NAND_ECC_ENC_DONE_CLEAR();
+
+ NAND_nFCE_L(0); /* Force nRCS[0] to low (Enable chip select) */
+
+ NAND_CMD(NAND_CMD_SEQIN); /* Write command, 0x80 */
+
+ /* Write Address */
+ NAND_ADDR(0);
+ if (large_block) NAND_ADDR(0);
+ NAND_ADDR((addr) & 0xff);
+ NAND_ADDR((addr>>8) & 0xff);
+ NAND_ADDR((addr>>16) & 0xff);
+
+ NAND_MECC_UnLock();
+ NAND_RSTECC();
+
+ NAND_SET_RND_SEED(uRandomSeed);
+ NAND_RESET_RND();
+ NAND_ENABLE_RND();
+
+ for(i=0; i < page_size; i++)
+ {
+ NFDATA8_REG = *buf++;
+ }
+
+ NAND_MECC_Lock();
+
+ NAND_ECC_LOOP_UNTIL_ENC_DONE();
+ NAND_ECC_ENC_DONE_CLEAR();
+
+ nandll_calculate_ecc(ECCData);
+
+ for(i=0; i<ECCLen; i++)
+ {
+ NFDATA8_REG = ECCData[i];
+ }
+
+ NAND_DISABLE_RND();
+
+ NAND_CLEAR_RB();
+ NAND_CMD(NAND_CMD_PAGEPROG);
+
+ if(NAND_IS_LOCKED())
+ {
+ NAND_ILL_ACC_CLEAR();
+ NAND_nFCE_H(0);
+ return 1;
+ }
+
+#if 0
+ if( NAND_DETECT_RB() == false )
+ {
+ NAND_nFCE_H(0);
+ return 1;
+ }
+#else
+ NAND_DETECT_RB();
+#endif
+
+ NAND_CMD(NAND_CMD_STATUS); // Read status command
+
+ for(i=0; i<1000; i++)
+ {
+
+ if ( NFDATA8_REG&0x40 ) break;
+ }
+
+ if( NFDATA8_REG & 1)
+ {
+ NAND_nFCE_H(0);
+ return 1;
+ }
+
+ NAND_nFCE_H(0);
+
+ return 0;
+}
+
+/*
+ * Read data from NAND.
+ */
+static int nandll_write_blocks (ulong src_addr, int dest_page, ulong size, int large_block)
+{
+ uchar *buf = (uchar *)src_addr;
+ uchar local_buf[512];
+ int i, j;
+ ulong checksum;
+ int ret;
+
+ NAND_ENABLE_CE();
+
+ /*
+ * from AP team's iROM code
+ */
+ NAND_ECC_SETDIR_ENC();
+ NAND_SEL_ECC16();
+ NAND_ECC_SET_MSGLEN(512);
+
+ checksum=0;
+ for (i = dest_page; i < dest_page+size; i++, buf+=512)
+ {
+#ifdef CONFIG_EVT1
+ if (i==43||i==75)
+#else
+ if (i==27||i==59)
+#endif
+ {
+ for (j=0;j<508;j++)
+ {
+ checksum+=buf[j];
+ local_buf[j]=buf[j];
+ }
+ *((volatile ulong *)(local_buf + 508)) = checksum;
+ nandll_write_page(local_buf, i, large_block);
+ checksum=0;
+ }
+ else
+ {
+#ifdef CONFIG_EVT1
+ if (i >= 16)
+#endif
+ for (j=0;j<512;j++)
+ {
+ checksum+=buf[j];
+ }
+ ret = nandll_write_page(buf, i, large_block);
+ if(ret)
+ {
+ printf("nandll_write_page %d fail\n", i);
+ }
+ }
+ }
+
+ NAND_DISABLE_CE();
+ return 0;
+}
+
+int write_bl1_to_nand (ulong src_addr, int dest_page, int size)
+{
+ int large_block = 8;
+ int i;
+ vu_char id;
+ /*
+ * dest_page : 0 (BL1) or 32 (BL2)
+ * size : 32 pages (16k bytes)
+ */
+ if (dest_page+size>64) return 1;
+ if (dest_page && dest_page!=32) return 1;
+ if (size!=32 && size!=64) return 1;
+
+ NAND_CONTROL_ENABLE();
+ NAND_ENABLE_CE();
+ NFCMD_REG = NAND_CMD_READID;
+ NFADDR_REG = 0x00;
+
+ /* wait for a while */
+ for (i=0; i<200; i++);
+ id = NFDATA8_REG;
+ id = NFDATA8_REG;
+
+ if (id > 0x80)
+ large_block = 1;
+
+ /* write BL1 or BL2 image to NAND.
+ * BL1 : 0 ~ 31 pages.
+ * BL2 : 32 ~ 63 pages.
+ */
+ return nandll_write_blocks(src_addr, dest_page, size, large_block);
+}
+
+#endif
+
diff --git a/arch/arm/cpu/armv7/exynos/onenand_cp.c b/arch/arm/cpu/armv7/exynos/onenand_cp.c
new file mode 100644
index 0000000000..79b8d80e64
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/onenand_cp.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Copy U-Boot code from OneNAND into DRAM (UBOOT_PHY_BASE).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/onenand_regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#include "UBOOT_SB20_S5PC210S.h"
+#endif
+
+#ifdef CONFIG_BOOT_ONENAND_IROM
+
+#define ONENAND_BASE (CFG_ONENAND_BASE)
+#define CONFIG_EVT1
+//#define CONFIG_SECURE_BOOT
+#define CONFIG_SECURE_BL1_ONLY
+
+#if defined(CONFIG_MCP_AC) || defined(CONFIG_MCP_B) || defined(CONFIG_MCP_D)
+#define ONENAND_PAGE_SIZE 4096
+#elif defined(CONFIG_MCP_H)
+#define ONENAND_PAGE_SIZE 2048
+#else // default page size (for V210 daughter board)
+#define ONENAND_PAGE_SIZE 2048
+#endif
+
+#if defined(CONFIG_FUSED)
+#define FWBL1_SIZE (4096)
+#define UBOOT_START_BLOCK (FWBL1_SIZE / ONENAND_PAGE_SIZE)
+#else
+#define UBOOT_START_BLOCK (0)
+#endif
+
+#define READ_INTERRUPT() \
+ onenand_readw(ONENAND_BASE + ONENAND_REG_INTERRUPT)
+
+#define onenand_block_address(block) (block)
+#define onenand_sector_address(page) (page << ONENAND_FPA_SHIFT)
+#define onenand_buffer_address() ((1 << 3) << 8)
+//#define onenand_buffer_address() ((0 << 3) << 8)
+#define onenand_bufferram_address(block) (0)
+
+
+#ifdef CONFIG_EVT1
+#define SECURE_CONTEXT_BASE 0x02023000
+#else
+#define SECURE_CONTEXT_BASE 0x02023800
+#endif
+
+inline unsigned short onenand_readw (unsigned int addr)
+{
+ return *(unsigned short*)addr;
+}
+
+inline void onenand_writew (unsigned short value, unsigned int addr)
+{
+ *(unsigned short*)addr = value;
+}
+
+void onenand_loadpage (unsigned int block, unsigned int page)
+{
+ // Block Number
+ onenand_writew(onenand_block_address(block),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS1);
+
+ // BufferRAM
+ onenand_writew(onenand_bufferram_address(block),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS2);
+
+ // Page (Sector) Number Set: FPA, FSA
+ onenand_writew(onenand_sector_address(page),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS8);
+
+ // BSA, BSC
+ onenand_writew(onenand_buffer_address(),
+ ONENAND_BASE + ONENAND_REG_START_BUFFER);
+
+ // Interrupt clear
+ onenand_writew(ONENAND_INT_CLEAR, ONENAND_BASE + ONENAND_REG_INTERRUPT);
+
+ onenand_writew(ONENAND_CMD_READ, ONENAND_BASE + ONENAND_REG_COMMAND);
+
+#if 1
+ while (!(READ_INTERRUPT() & ONENAND_INT_READ))
+ continue;
+#else
+ while (!(READ_INTERRUPT() & ONENAND_INT_MASTER))
+ continue;
+#endif
+}
+
+int onenand_isbad (unsigned int block)
+{
+ unsigned short* src;
+
+ onenand_loadpage(block, 0);
+
+ src = (unsigned short *)(ONENAND_BASE + ONENAND_SPARERAM);
+ if (src[0] == (unsigned short)0xFFFF)
+ return 0;
+ else
+ return 1;
+}
+
+void onenand_readpage (void* base, unsigned int block, unsigned int page)
+{
+ int len;
+ unsigned short* dest;
+ unsigned short* src;
+
+ onenand_loadpage(block, page);
+
+ len = ONENAND_PAGE_SIZE >> 1;
+ dest = (unsigned short *)(base);
+ src = (unsigned short *)(ONENAND_BASE + ONENAND_DATARAM);
+ while (len-- > 0)
+ {
+ *dest++ = *src++;
+ }
+}
+
+/*
+ * Copy U-Boot from OneNAND to DRAM (512KB)
+ */
+void onenand_bl2_copy(void)
+{
+ unsigned int base = CFG_PHY_UBOOT_BASE;
+ int download_size = 512 * 1024; /* U-boot image size */
+ //int block = 0; /* Start block */
+ //int page = UBOOT_START_BLOCK; /* Start page */
+ int block = 0; /* Start block */
+
+ int page = 16; /* Start page */
+#ifndef CONFIG_SECURE_BOOT
+#ifndef CONFIG_SECURE_BL1_ONLY
+#ifndef CONFIG_EVT1
+ page = 8; /* Start page */
+#endif
+#endif
+#endif
+ do {
+ onenand_readpage((void *)base, block, page);
+
+ base += ONENAND_PAGE_SIZE;
+ download_size -= ONENAND_PAGE_SIZE;
+
+ if (++page == 64) {
+ page = 0;
+ do {
+ block++;
+ } while (onenand_isbad(block));
+ }
+ } while (download_size > 0);
+
+#ifdef CONFIG_SECURE_BOOT
+ if(Check_Signature( (SB20_CONTEXT *)SECURE_CONTEXT_BASE, (unsigned char*)CFG_PHY_UBOOT_BASE,
+ 1024*512-256, (unsigned char*)(CFG_PHY_UBOOT_BASE+1024*512-256), 256 ) != 0) {
+ while(1);
+ }
+#endif
+
+
+}
+
+#endif /* CONFIG_BOOT_ONENAND_IROM */
+
diff --git a/arch/arm/cpu/armv7/exynos/pmic.c b/arch/arm/cpu/armv7/exynos/pmic.c
new file mode 100644
index 0000000000..036ed50987
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/pmic.c
@@ -0,0 +1,705 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/pmic.h>
+
+void Delay(void)
+{
+ unsigned long i;
+ for(i=0;i<DELAY;i++);
+}
+
+void IIC0_SCLH_SDAH(void)
+{
+ IIC0_ESCL_Hi;
+ IIC0_ESDA_Hi;
+ Delay();
+}
+
+void IIC0_SCLH_SDAL(void)
+{
+ IIC0_ESCL_Hi;
+ IIC0_ESDA_Lo;
+ Delay();
+}
+
+void IIC0_SCLL_SDAH(void)
+{
+ IIC0_ESCL_Lo;
+ IIC0_ESDA_Hi;
+ Delay();
+}
+
+void IIC0_SCLL_SDAL(void)
+{
+ IIC0_ESCL_Lo;
+ IIC0_ESDA_Lo;
+ Delay();
+}
+
+void IIC1_SCLH_SDAH(void)
+{
+ IIC1_ESCL_Hi;
+ IIC1_ESDA_Hi;
+ Delay();
+}
+
+void IIC1_SCLH_SDAL(void)
+{
+ IIC1_ESCL_Hi;
+ IIC1_ESDA_Lo;
+ Delay();
+}
+
+void IIC1_SCLL_SDAH(void)
+{
+ IIC1_ESCL_Lo;
+ IIC1_ESDA_Hi;
+ Delay();
+}
+
+void IIC1_SCLL_SDAL(void)
+{
+ IIC1_ESCL_Lo;
+ IIC1_ESDA_Lo;
+ Delay();
+}
+
+#ifdef CONFIG_SMDKC220
+void IIC3_SCLH_SDAH(void)
+{
+ IIC3_ESCL_Hi;
+ IIC3_ESDA_Hi;
+ Delay();
+}
+
+void IIC3_SCLH_SDAL(void)
+{
+ IIC3_ESCL_Hi;
+ IIC3_ESDA_Lo;
+ Delay();
+}
+
+void IIC3_SCLL_SDAH(void)
+{
+ IIC3_ESCL_Lo;
+ IIC3_ESDA_Hi;
+ Delay();
+}
+
+void IIC3_SCLL_SDAL(void)
+{
+ IIC3_ESCL_Lo;
+ IIC3_ESDA_Lo;
+ Delay();
+}
+#endif
+
+void IIC0_ELow(void)
+{
+ IIC0_SCLL_SDAL();
+ IIC0_SCLH_SDAL();
+ IIC0_SCLH_SDAL();
+ IIC0_SCLL_SDAL();
+}
+
+void IIC0_EHigh(void)
+{
+ IIC0_SCLL_SDAH();
+ IIC0_SCLH_SDAH();
+ IIC0_SCLH_SDAH();
+ IIC0_SCLL_SDAH();
+}
+
+void IIC1_ELow(void)
+{
+ IIC1_SCLL_SDAL();
+ IIC1_SCLH_SDAL();
+ IIC1_SCLH_SDAL();
+ IIC1_SCLL_SDAL();
+}
+
+void IIC1_EHigh(void)
+{
+ IIC1_SCLL_SDAH();
+ IIC1_SCLH_SDAH();
+ IIC1_SCLH_SDAH();
+ IIC1_SCLL_SDAH();
+}
+
+#ifdef CONFIG_SMDKC220
+void IIC3_ELow(void)
+{
+ IIC3_SCLL_SDAL();
+ IIC3_SCLH_SDAL();
+ IIC3_SCLH_SDAL();
+ IIC3_SCLL_SDAL();
+}
+
+void IIC3_EHigh(void)
+{
+ IIC3_SCLL_SDAH();
+ IIC3_SCLH_SDAH();
+ IIC3_SCLH_SDAH();
+ IIC3_SCLL_SDAH();
+}
+#endif
+
+
+void IIC0_EStart(void)
+{
+ IIC0_SCLH_SDAH();
+ IIC0_SCLH_SDAL();
+ Delay();
+ IIC0_SCLL_SDAL();
+}
+
+void IIC0_EEnd(void)
+{
+ IIC0_SCLL_SDAL();
+ IIC0_SCLH_SDAL();
+ Delay();
+ IIC0_SCLH_SDAH();
+}
+
+void IIC0_EAck_write(void)
+{
+ unsigned long ack;
+
+ IIC0_ESDA_INP; // Function <- Input
+
+ IIC0_ESCL_Lo;
+ Delay();
+ IIC0_ESCL_Hi;
+ Delay();
+ ack = GPD1DAT;
+ IIC0_ESCL_Hi;
+ Delay();
+ IIC0_ESCL_Hi;
+ Delay();
+
+ IIC0_ESDA_OUTP; // Function <- Output (SDA)
+
+#ifdef CONFIG_INVERSE_PMIC_I2C
+ ack = (ack>>1)&0x1;
+#else
+ ack = (ack>>0)&0x1;
+#endif
+// while(ack!=0);
+
+ IIC0_SCLL_SDAL();
+}
+
+void IIC0_EAck_read(void)
+{
+ IIC0_ESDA_OUTP; // Function <- Output
+
+ IIC0_ESCL_Lo;
+ IIC0_ESCL_Lo;
+ IIC0_ESDA_Lo;
+ IIC0_ESCL_Hi;
+ IIC0_ESCL_Hi;
+
+ IIC0_ESDA_INP; // Function <- Input (SDA)
+
+ IIC0_SCLL_SDAL();
+}
+
+void IIC1_EStart(void)
+{
+ IIC1_SCLH_SDAH();
+ IIC1_SCLH_SDAL();
+ Delay();
+ IIC1_SCLL_SDAL();
+}
+
+void IIC1_EEnd(void)
+{
+ IIC1_SCLL_SDAL();
+ IIC1_SCLH_SDAL();
+ Delay();
+ IIC1_SCLH_SDAH();
+}
+
+void IIC1_EAck(void)
+{
+ unsigned long ack;
+
+ IIC1_ESDA_INP; // Function <- Input
+
+ IIC1_ESCL_Lo;
+ Delay();
+ IIC1_ESCL_Hi;
+ Delay();
+ ack = GPD1DAT;
+ IIC1_ESCL_Hi;
+ Delay();
+ IIC1_ESCL_Hi;
+ Delay();
+
+ IIC1_ESDA_OUTP; // Function <- Output (SDA)
+
+ ack = (ack>>2)&0x1;
+// while(ack!=0);
+
+ IIC1_SCLL_SDAL();
+}
+
+#ifdef CONFIG_SMDKC220
+void IIC3_EStart(void)
+{
+ IIC3_SCLH_SDAH();
+ IIC3_SCLH_SDAL();
+ Delay();
+ IIC3_SCLL_SDAL();
+}
+
+void IIC3_EEnd(void)
+{
+ IIC3_SCLL_SDAL();
+ IIC3_SCLH_SDAL();
+ Delay();
+ IIC3_SCLH_SDAH();
+}
+
+void IIC3_EAck(void)
+{
+ unsigned long ack;
+
+ IIC3_ESDA_INP; // Function <- Input
+
+ IIC3_ESCL_Lo;
+ Delay();
+ IIC3_ESCL_Hi;
+ Delay();
+ ack = GPA1DAT;
+ IIC3_ESCL_Hi;
+ Delay();
+ IIC3_ESCL_Hi;
+ Delay();
+
+ IIC3_ESDA_OUTP; // Function <- Output (SDA)
+
+ ack = (ack>>2)&0x1;
+// while(ack!=0);
+
+ IIC3_SCLL_SDAL();
+}
+#endif
+
+
+void IIC0_ESetport(void)
+{
+ GPD1PUD &= ~(0xf<<0); // Pull Up/Down Disable SCL, SDA
+
+ IIC0_ESCL_Hi;
+ IIC0_ESDA_Hi;
+
+ IIC0_ESCL_OUTP; // Function <- Output (SCL)
+ IIC0_ESDA_OUTP; // Function <- Output (SDA)
+
+ Delay();
+}
+
+void IIC1_ESetport(void)
+{
+ GPD1PUD &= ~(0xf<<4); // Pull Up/Down Disable SCL, SDA
+
+ IIC1_ESCL_Hi;
+ IIC1_ESDA_Hi;
+
+ IIC1_ESCL_OUTP; // Function <- Output (SCL)
+ IIC1_ESDA_OUTP; // Function <- Output (SDA)
+
+ Delay();
+}
+
+#ifdef CONFIG_SMDKC220
+void IIC3_ESetport(void)
+{
+ GPA1PUD &= ~(0xf<<4); // Pull Up/Down Disable SCL, SDA
+
+ IIC3_ESCL_Hi;
+ IIC3_ESDA_Hi;
+
+ IIC3_ESCL_OUTP; // Function <- Output (SCL)
+ IIC3_ESDA_OUTP; // Function <- Output (SDA)
+
+ Delay();
+}
+#endif
+
+void IIC0_EWrite (unsigned char ChipId, unsigned char IicAddr, unsigned char IicData)
+{
+ unsigned long i;
+
+ IIC0_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> i) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_ELow(); // write
+
+ IIC0_EAck_write(); // ACK
+
+////////////////// write reg. addr. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicAddr >> (i-1)) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_EAck_write(); // ACK
+
+////////////////// write reg. data. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicData >> (i-1)) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_EAck_write(); // ACK
+
+ IIC0_EEnd();
+}
+
+void IIC0_ERead (unsigned char ChipId, unsigned char IicAddr, unsigned char *IicData)
+{
+ unsigned long i, reg;
+ unsigned char data = 0;
+
+ IIC0_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> i) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_ELow(); // write
+
+ IIC0_EAck_write(); // ACK
+
+////////////////// write reg. addr. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicAddr >> (i-1)) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_EAck_write(); // ACK
+
+ IIC0_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> i) & 0x0001)
+ IIC0_EHigh();
+ else
+ IIC0_ELow();
+ }
+
+ IIC0_EHigh(); // read
+
+ IIC0_EAck_write(); // ACK
+
+////////////////// read reg. data. //////////////////
+ IIC0_ESDA_INP;
+
+ for(i = 8; i>0; i--)
+ {
+ IIC0_ESCL_Lo;
+ Delay();
+ IIC0_ESCL_Hi;
+ Delay();
+ reg = GPD1DAT;
+ IIC0_ESCL_Hi;
+ Delay();
+ IIC0_ESCL_Hi;
+ Delay();
+
+#ifdef CONFIG_INVERSE_PMIC_I2C
+ reg = (reg >> 1) & 0x1;
+#else
+ reg = (reg >> 0) & 0x1;
+#endif
+ data |= reg << (i-1);
+ }
+
+ IIC0_EAck_read(); // ACK
+ IIC0_ESDA_OUTP;
+
+ IIC0_EEnd();
+
+ *IicData = data;
+}
+
+
+void IIC1_EWrite (unsigned char ChipId, unsigned char IicAddr, unsigned char IicData)
+{
+ unsigned long i;
+
+ IIC1_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> i) & 0x0001)
+ IIC1_EHigh();
+ else
+ IIC1_ELow();
+ }
+
+ IIC1_ELow(); // write 'W'
+
+ IIC1_EAck(); // ACK
+
+////////////////// write reg. addr. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicAddr >> (i-1)) & 0x0001)
+ IIC1_EHigh();
+ else
+ IIC1_ELow();
+ }
+
+ IIC1_EAck(); // ACK
+
+////////////////// write reg. data. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicData >> (i-1)) & 0x0001)
+ IIC1_EHigh();
+ else
+ IIC1_ELow();
+ }
+
+ IIC1_EAck(); // ACK
+
+ IIC1_EEnd();
+}
+
+#ifdef CONFIG_SMDKC220
+void IIC3_EWrite (unsigned char ChipId, unsigned char IicAddr, unsigned char IicData)
+{
+ unsigned long i;
+
+ IIC3_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> i) & 0x0001)
+ IIC3_EHigh();
+ else
+ IIC3_ELow();
+ }
+
+ IIC3_ELow(); // write 'W'
+
+ IIC3_EAck(); // ACK
+
+////////////////// write reg. addr. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicAddr >> (i-1)) & 0x0001)
+ IIC3_EHigh();
+ else
+ IIC3_ELow();
+ }
+
+ IIC3_EAck(); // ACK
+
+////////////////// write reg. data. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicData >> (i-1)) & 0x0001)
+ IIC3_EHigh();
+ else
+ IIC3_ELow();
+ }
+
+ IIC3_EAck(); // ACK
+
+ IIC3_EEnd();
+}
+#endif
+
+
+void I2C_MAX8997_VolSetting(PMIC_RegNum eRegNum, u8 ucVolLevel, u8 ucEnable)
+{
+ u8 reg_addr, reg_bitpos, reg_bitmask, vol_level;
+ u8 read_data;
+
+ reg_bitpos = 0;
+ reg_bitmask = 0x3F;
+ if(eRegNum == 0)
+ {
+ reg_addr = 0x19;
+ }
+ else if(eRegNum == 1)
+ {
+ reg_addr = 0x22;
+ }
+ else if(eRegNum == 2)
+ {
+ reg_addr = 0x2B;
+ }
+ else if(eRegNum == 3)
+ {
+ reg_addr = 0x2D;
+ }
+ else if(eRegNum == 4)
+ {
+ reg_addr = 0x48;
+ }
+ else if(eRegNum == 5)
+ {
+ reg_addr = 0x44;
+ }
+ else
+ while(1);
+
+ vol_level = ucVolLevel&reg_bitmask;
+
+ IIC0_ERead(MAX8997_ADDR, reg_addr, &read_data);
+
+ read_data = (read_data & (~(reg_bitmask<<reg_bitpos))) | (vol_level<<reg_bitpos);
+
+ IIC0_EWrite(MAX8997_ADDR, reg_addr, read_data);
+
+ I2C_MAX8997_EnableReg(eRegNum, ucEnable);
+}
+
+void I2C_MAX8997_EnableReg(PMIC_RegNum eRegNum, u8 ucEnable)
+{
+ u8 reg_addr, reg_bitpos;
+ u8 read_data;
+
+ reg_bitpos = 0;
+ if(eRegNum == 0)
+ {
+ reg_addr = 0x18;
+ }
+ else if(eRegNum == 1)
+ {
+ reg_addr = 0x21;
+ }
+ else if(eRegNum == 2)
+ {
+ reg_addr = 0x2A;
+ }
+ else if(eRegNum == 3)
+ {
+ reg_addr = 0x2C;
+ }
+ else if(eRegNum == 4)
+ {
+ reg_addr = 0x48;
+ reg_bitpos = 0x6;
+ }
+ else if(eRegNum == 5)
+ {
+ reg_addr = 0x44;
+ reg_bitpos = 0x6;
+ }
+
+ else
+ while(1);
+
+ IIC0_ERead(MAX8997_ADDR, reg_addr, &read_data);
+
+ read_data = (read_data & (~(1<<reg_bitpos))) | (ucEnable<<reg_bitpos);
+
+ IIC0_EWrite(MAX8997_ADDR, reg_addr, read_data);
+}
+
+void pmic_init(void)
+{
+ float vdd_arm, vdd_int, vdd_g3d;
+
+#if defined(CONFIG_SMDKC220) || defined(CONFIG_ARCH_EXYNOS5)
+ float vdd_mif;
+ float vdd_ldo14;
+#if defined(CONFIG_PM_VDD_LDO10)
+ float vdd_ldo10;
+#endif
+#endif
+
+ u8 read_data;
+
+ vdd_arm = CONFIG_PM_VDD_ARM;
+ vdd_int = CONFIG_PM_VDD_INT;
+ vdd_g3d = CONFIG_PM_VDD_G3D;
+#if defined(CONFIG_SMDKC220) || defined(CONFIG_ARCH_EXYNOS5)
+ vdd_mif = CONFIG_PM_VDD_MIF;
+#if defined(CONFIG_PM_VDD_LDO10)
+ vdd_ldo10 = CONFIG_PM_VDD_LDO10;
+#endif
+ vdd_ldo14 = CONFIG_PM_VDD_LDO14;
+#endif
+ IIC0_ESetport();
+ IIC1_ESetport();
+#ifdef CONFIG_SMDKC220
+ IIC3_ESetport();
+#endif
+ /* read ID */
+ IIC0_ERead(MAX8997_ADDR, 0, &read_data);
+ if (read_data == 0x77) {
+ I2C_MAX8997_VolSetting(PMIC_BUCK1, CALC_MAXIM_BUCK1245_VOLT(vdd_arm * 1000), 1);
+ I2C_MAX8997_VolSetting(PMIC_BUCK2, CALC_MAXIM_BUCK1245_VOLT(vdd_int * 1000), 1);
+ I2C_MAX8997_VolSetting(PMIC_BUCK3, CALC_MAXIM_BUCK37_VOLT(vdd_g3d * 1000), 1);
+#if defined(CONFIG_ARCH_EXYNOS5)
+ I2C_MAX8997_VolSetting(PMIC_BUCK4, CALC_MAXIM_BUCK1245_VOLT(vdd_mif * 1000), 1);
+#if defined(CONFIG_PM_VDD_LDO10)
+ I2C_MAX8997_VolSetting(PMIC_LDO10, CALC_MAXIM_ALL_LDO(vdd_ldo10 * 1000), 3);
+#endif
+#endif
+
+#if defined(CONFIG_SMDKC220) || defined(CONFIG_CPU_EXYNOS5210)
+ /* LDO14 config */
+ I2C_MAX8997_VolSetting(PMIC_LDO14, CALC_MAXIM_ALL_LDO(vdd_ldo14 * 1000), 3);
+#endif
+ } else {
+#if !defined(CONFIG_ARCH_EXYNOS5)
+ /* VDD_ARM, mode 3 register */
+ IIC0_EWrite(MAX8952_ADDR, 0x03, 0x80 | (((unsigned char)(vdd_arm * 100))-77));
+ /* VDD_INT, mode 2 register */
+ IIC1_EWrite(MAX8649_ADDR, 0x02, 0x80 | (((unsigned char)(vdd_int * 100))-75));
+ /* VDD_G3D, mode 2 register */
+ IIC0_EWrite(MAX8649A_ADDR, 0x02, 0x80 | (((unsigned char)(vdd_g3d * 100))-75));
+#endif
+ }
+
+#ifdef CONFIG_SMDKC220
+ /* VDD_MIF, mode 1 register */
+ IIC3_EWrite(MAX8952_ADDR, 0x01, 0x80 | (((unsigned char)(vdd_mif * 100))-77));
+ GPA1PUD |= (0x5<<4); // restore reset value: Pull Up/Down Enable SCL, SDA
+#endif
+}
diff --git a/arch/arm/cpu/armv7/exynos/pmic_hkdk4212.c b/arch/arm/cpu/armv7/exynos/pmic_hkdk4212.c
new file mode 100644
index 0000000000..da2b3e9e42
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/pmic_hkdk4212.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+//[*]----------------------------------------------------------------------------------------------[*]
+#include <common.h>
+#include <asm/arch/pmic_hkdk4212.h>
+
+//[*]----------------------------------------------------------------------------------------------[*]
+// static function prototype
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_sda_port_control (unsigned char inout);
+static void gpio_i2c_clk_port_control (unsigned char inout);
+
+static unsigned char gpio_i2c_get_sda (void);
+static void gpio_i2c_set_sda (unsigned char hi_lo);
+static void gpio_i2c_set_clk (unsigned char hi_lo);
+
+static void gpio_i2c_start (void);
+static void gpio_i2c_stop (void);
+
+static void gpio_i2c_send_ack (void);
+static void gpio_i2c_send_noack (void);
+static unsigned char gpio_i2c_chk_ack (void);
+
+static void gpio_i2c_byte_write (unsigned char wdata);
+static void gpio_i2c_byte_read (unsigned char *rdata);
+
+//[*]----------------------------------------------------------------------------------------------[*]
+void delay_func(unsigned int us)
+{
+ unsigned long i;
+
+ for(i = 0; i < us; i++) { i++; i--; }
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_sda_port_control (unsigned char inout)
+{
+ GPIO_I2C_SDA_CON_PORT &= (unsigned long)(~(GPIO_CON_PORT_MASK << (GPIO_SDA_PIN * GPIO_CON_PORT_OFFSET)));
+ GPIO_I2C_SDA_CON_PORT |= (unsigned long)( (inout << (GPIO_SDA_PIN * GPIO_CON_PORT_OFFSET)));
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_clk_port_control (unsigned char inout)
+{
+ GPIO_I2C_CLK_CON_PORT &= (unsigned long)(~(GPIO_CON_PORT_MASK << (GPIO_CLK_PIN * GPIO_CON_PORT_OFFSET)));
+ GPIO_I2C_CLK_CON_PORT |= (unsigned long)( (inout << (GPIO_CLK_PIN * GPIO_CON_PORT_OFFSET)));
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static unsigned char gpio_i2c_get_sda (void)
+{
+ return GPIO_I2C_SDA_DAT_PORT & (HIGH << GPIO_SDA_PIN) ? 1 : 0;
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_set_sda (unsigned char hi_lo)
+{
+ if(hi_lo) {
+ gpio_i2c_sda_port_control(GPIO_CON_INPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+ }
+ else {
+ GPIO_I2C_SDA_DAT_PORT &= ~(HIGH << GPIO_SDA_PIN);
+ gpio_i2c_sda_port_control(GPIO_CON_OUTPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+ }
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_set_clk (unsigned char hi_lo)
+{
+ if(hi_lo) {
+ gpio_i2c_clk_port_control(GPIO_CON_INPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+ }
+ else {
+ GPIO_I2C_CLK_DAT_PORT &= ~(HIGH << GPIO_CLK_PIN);
+ gpio_i2c_clk_port_control(GPIO_CON_OUTPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+ }
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_start (void)
+{
+ // Setup SDA, CLK output High
+ gpio_i2c_set_sda(HIGH);
+ gpio_i2c_set_clk(HIGH);
+
+ delay_func(DELAY_TIME);
+
+ // SDA low before CLK low
+ gpio_i2c_set_sda(LOW); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_stop (void)
+{
+ // Setup SDA, CLK output low
+ gpio_i2c_set_sda(LOW);
+ gpio_i2c_set_clk(LOW);
+
+ delay_func(DELAY_TIME);
+
+ // SDA high after CLK high
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+ gpio_i2c_set_sda(HIGH); delay_func(DELAY_TIME);
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_send_ack (void)
+{
+ // SDA Low
+ gpio_i2c_set_sda(LOW); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_send_noack (void)
+{
+ // SDA High
+ gpio_i2c_set_sda(HIGH); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static unsigned char gpio_i2c_chk_ack (void)
+{
+ unsigned char count = 0, ret = 0;
+
+ gpio_i2c_set_sda(LOW); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+
+ gpio_i2c_sda_port_control(GPIO_CON_INPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+
+ while(gpio_i2c_get_sda()) {
+ if(count++ > 100) { ret = 1; break; }
+ else delay_func(DELAY_TIME);
+ }
+
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+
+ #if defined(DEBUG_GPIO_I2C)
+ if(ret) DEBUG_MSG(("%s (%d): no ack!!\n",__FUNCTION__, ret));
+ else DEBUG_MSG(("%s (%d): ack !! \n" ,__FUNCTION__, ret));
+ #endif
+
+ return ret;
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_byte_write (unsigned char wdata)
+{
+ unsigned char cnt, mask;
+
+ for(cnt = 0, mask = 0x80; cnt < 8; cnt++, mask >>= 1) {
+ if(wdata & mask) gpio_i2c_set_sda(HIGH);
+ else gpio_i2c_set_sda(LOW);
+
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+ }
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+static void gpio_i2c_byte_read (unsigned char *rdata)
+{
+ unsigned char cnt, mask;
+
+ gpio_i2c_sda_port_control(GPIO_CON_INPUT);
+ delay_func(PORT_CHANGE_DELAY_TIME);
+
+ for(cnt = 0, mask = 0x80, *rdata = 0; cnt < 8; cnt++, mask >>= 1) {
+ gpio_i2c_set_clk(HIGH); delay_func(DELAY_TIME);
+
+ if(gpio_i2c_get_sda()) *rdata |= mask;
+
+ gpio_i2c_set_clk(LOW); delay_func(DELAY_TIME);
+
+ }
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+int pmic_write (unsigned char reg, unsigned char *wdata, unsigned char wsize)
+{
+ unsigned char cnt, ack;
+
+ // start
+ gpio_i2c_start();
+
+ gpio_i2c_byte_write(MAX77687_ADDR + I2C_WRITE); // i2c address
+
+ if((ack = gpio_i2c_chk_ack())) goto write_stop;
+
+ gpio_i2c_byte_write(reg); // register
+
+ if((ack = gpio_i2c_chk_ack())) goto write_stop;
+
+ if(wsize) {
+ for(cnt = 0; cnt < wsize; cnt++) {
+ gpio_i2c_byte_write(wdata[cnt]);
+
+ if((ack = gpio_i2c_chk_ack())) goto write_stop;
+ }
+ }
+
+write_stop:
+
+ if(wsize) gpio_i2c_stop();
+
+ return ack;
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+int pmic_read (unsigned char reg, unsigned char *rdata, unsigned char rsize)
+{
+ unsigned char ack, cnt;
+
+ // register pointer write
+ if(pmic_write(reg, NULL, 0)) goto read_stop;
+
+ // restart
+ gpio_i2c_start();
+
+ gpio_i2c_byte_write(MAX77687_ADDR + I2C_READ); // i2c address
+
+ if((ack = gpio_i2c_chk_ack())) goto read_stop;
+
+ for(cnt=0; cnt < rsize; cnt++) {
+
+ gpio_i2c_byte_read(&rdata[cnt]);
+
+ if(cnt == rsize -1) gpio_i2c_send_noack();
+ else gpio_i2c_send_ack();
+ }
+
+read_stop:
+ gpio_i2c_stop();
+
+ return ack;
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+//[*]----------------------------------------------------------------------------------------------[*]
+void pmic_init(void)
+{
+ unsigned char rwdata;
+ gpio_i2c_set_sda(HIGH); gpio_i2c_set_clk(HIGH);
+
+ rwdata = 0x08; // reset delay changed : 7sec to 3sec
+ pmic_write(0x0A, &rwdata, 1);
+
+ rwdata = 0x14; // 1.8V Enable
+ pmic_write(0x53, &rwdata, 1); // EMMC
+}
+
+//[*]----------------------------------------------------------------------------------------------[*]
+//[*]----------------------------------------------------------------------------------------------[*]
+void emmc_pwr_reset(void)
+{
+ unsigned char rwdata;
+ gpio_i2c_set_sda(HIGH); gpio_i2c_set_clk(HIGH);
+
+ rwdata = 0x14; // 1.8V Enable
+ pmic_write(0x53, &rwdata, 1); // EMMC
+
+ rwdata = 0x00; // 1.8V Enable
+// pmic_write(0x34, &rwdata, 1); // BUCK7 3.0V
+ pmic_write(0x36, &rwdata, 1); // BUCK8 3.0V
+}
+//[*]----------------------------------------------------------------------------------------------[*]
+//[*]----------------------------------------------------------------------------------------------[*]
diff --git a/arch/arm/cpu/armv7/exynos/reset.c b/arch/arm/cpu/armv7/exynos/reset.c
new file mode 100644
index 0000000000..1de9d3aba8
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/reset.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+#if defined(CONFIG_HKDK4412)
+#include <asm/arch/gpio.h>
+#endif
+/* * reset the cpu by setting up the watchdog timer and let him time out */
+void reset_cpu(ulong ignored)
+{
+
+#if defined(CONFIG_HKDK4412)
+ emmc_pwr_reset();
+
+ GPIO_Init();
+
+ GPIO_SetFunctionEach(eGPIO_K1, eGPIO_2, eGPO);
+// GPIO_SetPullUpDownEach(eGPIO_K1, eGPIO_2, 0);
+ GPIO_SetDataEach(eGPIO_K1, eGPIO_2, 0);
+ udelay (50000); /* wait 50 ms */
+ GPIO_SetDataEach(eGPIO_K1, eGPIO_2, 1);
+
+#endif
+
+ printf("reset... \n\n\n");
+ SW_RST_REG = 0x1;
+
+ /* loop forever and wait for reset to happen */
+ while (1)
+ {
+ if (serial_tstc())
+ {
+ serial_getc();
+ break;
+ }
+ }
+ /*NOTREACHED*/
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/security_check.c b/arch/arm/cpu/armv7/exynos/security_check.c
new file mode 100644
index 0000000000..04b29a9698
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/security_check.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/ace_sha1.h>
+#include <asm/arch/movi_partition.h>
+
+#include "uboot_sb21.h"
+
+void security_check(void)
+{
+ unsigned char hash_code[20];
+ unsigned int bl1_size = PART_SIZE_FWBL1;
+ unsigned int secure_context_base;
+
+ if(bl1_size == (15 * 1024)) {
+ secure_context_base = 0x40003800;
+ } else
+ secure_context_base = 0x40001c00;
+
+ ace_hash_sha1_digest(hash_code, (unsigned char *)CONFIG_SECURE_KERNEL_BASE, CONFIG_SECURE_KERNEL_SIZE-256);
+
+ if(check_signature( (SB20_CONTEXT *)secure_context_base,
+ hash_code, 20,
+ (unsigned char*)(CONFIG_SECURE_KERNEL_BASE+CONFIG_SECURE_KERNEL_SIZE-256),
+ 256 ) != 0) {
+ printf("Kernel Integrity check fail\nSystem Halt....");
+ while(1);
+ }
+ printf("Kernel Integirty check success.\n");
+
+#ifdef CONFIG_SECURE_ROOTFS
+ ace_hash_sha1_digest(hash_code, (unsigned char *)CONFIG_SECURE_ROOTFS_BASE, CONFIG_SECURE_ROOTFS_SIZE-256);
+
+ if(check_signature( (SB20_CONTEXT *)secure_context_base,
+ hash_code, 20,
+ (unsigned char*)(CONFIG_SECURE_ROOTFS_BASE+CONFIG_SECURE_ROOTFS_SIZE-256),
+ 256 ) != 0) {
+ printf("rootfs Integrity check fail\nSystem Halt....");
+ while(1);
+ }
+ printf("rootfs Integirty check success.\n");
+#endif
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/setup_hsmmc.c b/arch/arm/cpu/armv7/exynos/setup_hsmmc.c
new file mode 100644
index 0000000000..f6ef3c6ef4
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/setup_hsmmc.c
@@ -0,0 +1,247 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/s3c_hsmmc.h>
+
+void clear_hsmmc_clock_div(void)
+{
+#if defined(CONFIG_EXYNOS4212) || defined(CONFIG_ARCH_EXYNOS5)
+ CLK_DIV_FSYS1 = 0x000f000f;
+ CLK_DIV_FSYS2 = 0x000f000f;
+ CLK_DIV_FSYS3 = 0x00000300;
+#else
+ CLK_DIV_FSYS1 = 0x00070007;
+ CLK_DIV_FSYS2 = 0x00070007;
+ CLK_DIV_FSYS3 = 0x00000400;
+#endif
+}
+
+void set_hsmmc_pre_ratio (struct sdhci_host *host, uint clock)
+{
+ u32 div;
+ u32 tmp;
+ u32 clk;
+ u32 i;
+
+#ifdef USE_MMC0
+ /* MMC2 clock div */
+ div = CLK_DIV_FSYS1 & ~(0xff000000);
+ tmp = CLK_DIV_FSYS1 & (0x000f0000);
+
+ clk = get_MPLL_CLK();
+ clk = clk / (tmp + 1);
+ for(i=0 ; i<=0xff; i++)
+ {
+ if((clk /(i+1)) <= clock) {
+ CLK_DIV_FSYS1 = tmp | i<<24;
+ break;
+ }
+ }
+#endif
+#ifdef USE_MMC2
+ /* MMC2 clock div */
+ div = CLK_DIV_FSYS2 & ~(0x0000ff00);
+ tmp = CLK_DIV_FSYS2 & (0x0000000f);
+
+ clk = get_MPLL_CLK();
+#if 1
+ clk = clk / (tmp + 1);
+
+ for(i=0 ; i<=0xff; i++)
+ {
+ if((clk /(i+1)) <= clock) {
+ CLK_DIV_FSYS2 = tmp | i<<8;
+ break;
+ }
+ }
+#else
+ CLK_DIV_FSYS2 = 0x000f000f;
+#endif
+#endif
+}
+
+void setup_hsmmc_clock(void)
+{
+ u32 tmp;
+ u32 clock;
+ u32 i;
+
+#ifdef USE_MMC0
+ /* MMC0 clock src = SCLKMPLL */
+ tmp = CLK_SRC_FSYS & ~(0x0000000f);
+ CLK_SRC_FSYS = tmp | 0x00000006;
+
+ /* MMC0 clock div */
+ tmp = CLK_DIV_FSYS1 & ~(0x0000000f);
+ clock = get_MPLL_CLK()/1000000;
+ for(i=0; i<= 0xf; i++)
+ {
+ // if((clock / (i+1)) <= 90) {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV_FSYS1 = tmp | i<<0;
+ break;
+ }
+ }
+#endif
+
+#ifdef USE_MMC1
+#endif
+
+#ifdef USE_MMC2
+ /* MMC2 clock src = SCLKMPLL */
+ tmp = CLK_SRC_FSYS & ~(0x00000f00);
+ CLK_SRC_FSYS = tmp | 0x00000600;
+
+ /* MMC2 clock div */
+ tmp = CLK_DIV_FSYS2 & ~(0x0000000f);
+ clock = get_MPLL_CLK()/1000000;
+ for(i=0; i<= 0xf; i++)
+ {
+ if((clock / (i+1)) <= 90) {
+ //if((clock / (i+1)) <= 50) {
+ //if((clock / (i+1)) <= 40) {
+ CLK_DIV_FSYS2 = tmp | i<<0;
+ break;
+ }
+ }
+#endif
+
+#ifdef USE_MMC3
+#endif
+
+#ifdef USE_MMC4
+ /* MMC4 clock src = SCLKMPLL */
+ tmp = CLK_SRC_FSYS & ~(0x000f0000);
+ CLK_SRC_FSYS = tmp | 0x00060000;
+
+ /* MMC4 clock div */
+ tmp = CLK_DIV_FSYS3 & ~(0x0000ff0f);
+ clock = get_MPLL_CLK()/1000000;
+ for(i=0 ; i<=0xf; i++)
+ {
+#if defined(CONFIG_EXYNOS4212) || defined(CONFIG_EXYNOS5)
+ if((clock /(i+1)) <= 170) {
+#else
+ if((clock /(i+1)) <= 160) {
+#endif
+ CLK_DIV_FSYS3 = tmp | i<<8;
+ break;
+ }
+ }
+#endif
+}
+
+/*
+ * this will set the GPIO for hsmmc ch0
+ * GPG0[0:6] = CLK, CMD, CDn, DAT[0:3]
+ */
+void setup_hsmmc_cfg_gpio(void)
+{
+#ifdef USE_MMC0
+ writel(0x02222222, GPIO_CON_MMC0_1);
+ writel(0x00003FF0, GPIO_CON_MMC0_1 + GPIO_PUD_OFFSET);
+ writel(0x00003FFF, GPIO_CON_MMC0_1 + GPIO_DRV_OFFSET);
+
+ writel(0x03333000, GPIO_CON_MMC0_2);
+ writel(0x00003FF0, GPIO_CON_MMC0_2 + GPIO_PUD_OFFSET);
+ writel(0x00003FFF, GPIO_CON_MMC0_2 + GPIO_DRV_OFFSET);
+#endif
+
+#ifdef USE_MMC1
+#endif
+
+#ifdef USE_MMC2
+ writel(0x02222222, GPIO_CON_MMC2_1);
+ writel(0x00003FF0, GPIO_CON_MMC2_1 + GPIO_PUD_OFFSET);
+ writel(0x00003FFF, GPIO_CON_MMC2_1 + GPIO_DRV_OFFSET);
+ /* 8 bit supprot */
+ writel(0x03333000, GPIO_CON_MMC2_2);
+ writel(0x00003FF0, GPIO_CON_MMC2_2 + GPIO_PUD_OFFSET);
+ writel(0x00003FFF, GPIO_CON_MMC2_2 + GPIO_DRV_OFFSET);
+#endif
+
+#ifdef USE_MMC3
+#endif
+
+#ifdef USE_MMC4
+ writel(0x03333333, GPIO_CON_MMC4_1);
+ writel(0x00003FF0, GPIO_CON_MMC4_1 + GPIO_PUD_OFFSET);
+ writel(0x00002AAA, GPIO_CON_MMC4_1 + GPIO_DRV_OFFSET);
+
+#if defined(CONFIG_HKDK4212)
+ writel(0x04444100, GPIO_CON_MMC4_2);
+ writel(0x00003FF0, GPIO_CON_MMC4_2 + GPIO_PUD_OFFSET);
+ writel(0x00002AA0, GPIO_CON_MMC4_2 + GPIO_DRV_OFFSET);
+#else
+ writel(0x04444000, GPIO_CON_MMC4_2);
+ writel(0x00003FC0, GPIO_CON_MMC4_2 + GPIO_PUD_OFFSET);
+ writel(0x00002A80, GPIO_CON_MMC4_2 + GPIO_DRV_OFFSET);
+#endif
+
+#ifndef CONFIG_ARCH_EXYNOS5
+ /* Drive Strength */
+ writel(0x00010001, 0x1255009C);
+#endif
+
+#endif
+}
+
+
+void setup_sdhci0_cfg_card(struct sdhci_host *host)
+{
+ u32 ctrl2;
+ u32 ctrl3;
+
+ /* don't need to alter anything acording to card-type */
+ writel(S3C_SDHCI_CONTROL4_DRIVE_9mA, host->ioaddr + S3C_SDHCI_CONTROL4);
+
+ ctrl2 = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+ ctrl3 = readl(host->ioaddr + S3C_SDHCI_CONTROL3);
+
+ ctrl2 |= (S3C_SDHCI_CTRL2_ENSTAASYNCCLR |
+ S3C_SDHCI_CTRL2_ENCMDCNFMSK |
+ S3C_SDHCI_CTRL2_DFCNT_NONE |
+ S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+ if (0 <= host->clock && host->clock < 25000000) {
+ /* Feedback Delay Disable */
+ ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX |
+ S3C_SDHCI_CTRL2_ENFBCLKRX);
+ ctrl3 &= ~(1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+
+ } else if (25000000 <= host->clock && host->clock <= 52000000) {
+#ifdef CONFIG_HKDK4412
+ /* Feedback Delay Enable */
+ ctrl2 |= (S3C_SDHCI_CTRL2_ENFBCLKTX | S3C_SDHCI_CTRL2_ENFBCLKRX);
+
+ ctrl3 |= (1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+#else
+ /* Feedback Delay Disable */
+ ctrl2 &= ~(S3C_SDHCI_CTRL2_ENFBCLKTX |
+ S3C_SDHCI_CTRL2_ENFBCLKRX);
+ /* Feedback Delay Rx Enable */
+ ctrl2 |= (S3C_SDHCI_CTRL2_ENFBCLKRX);
+ ctrl3 &= ~(1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+ ctrl3 |= (1 << 15 | 1 << 7);
+#endif
+
+ } else
+ printf("This CLOCK is Not Support: %d\n", host->clock);
+
+ writel(ctrl2, host->ioaddr + S3C_SDHCI_CONTROL2);
+ writel(ctrl3, host->ioaddr + S3C_SDHCI_CONTROL3);
+}
+
diff --git a/arch/arm/cpu/armv7/exynos/sys_info.c b/arch/arm/cpu/armv7/exynos/sys_info.c
new file mode 100644
index 0000000000..93ad7d0550
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/sys_info.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/cpu.h>
+
+/* Default is s5pc100 */
+unsigned int s5p_cpu_id = 0xC100;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ s5p_set_cpu_id();
+
+ s5p_clock_init();
+
+ return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+ return s5p_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ char buf[32];
+ unsigned int cpuid;
+
+#ifdef CONFIG_ARCH_EXYNOS5
+
+ __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
+
+ printf("\nCPU: S5PC%x Rev%x.%x [Samsung SOC on SMP Platform Base on ARM CortexA%d]\n" \
+ , ((PRO_ID >> 12) & 0xfff), PRO_MAINREV, PRO_SUBREV, ((cpuid >> 4) & 0xf));
+
+#elif CONFIG_SMDKC220
+ printf("\nCPU: S5PC220 [Samsung SOC on SMP Platform Base on ARM CortexA9]\n");
+#else
+ if(((PRO_ID & 0x300) >> 8) == 2){
+ printf("\nCPU: S5PC210 [Samsung SOC on SMP Platform Base on ARM CortexA9]\n");
+ }
+ else{
+ printf("\nCPU: S5PV310 [Samsung SOC on SMP Platform Base on ARM CortexA9]\n");
+ }
+#endif
+
+ printf("APLL = %ldMHz, MPLL = %ldMHz\n", get_APLL_CLK()/1000000, get_MPLL_CLK()/1000000);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/exynos/uboot_sb21.h b/arch/arm/cpu/armv7/exynos/uboot_sb21.h
new file mode 100644
index 0000000000..8e85461e16
--- /dev/null
+++ b/arch/arm/cpu/armv7/exynos/uboot_sb21.h
@@ -0,0 +1,102 @@
+#ifndef _UBOOT_SB21_H
+#define _UBOOT_SB21_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+////////////////////////////////////////////////////////////////////////
+// SecureBoot return value define
+#define SB_OK 0x00000000
+#define SB_OFF 0x80000000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_VALIDATE_PUBLIC_KEY_INFO 0xFFF10000
+#define SB_ERROR_VERIFY_PSS_RSA_SIGNATURE 0xFFF20000
+#define SB_ERROR_CHECK_INTEGRITY_CODE 0xFFF30000
+
+//------------------------------------------------------------------------
+// added for Secure Boot 2.0
+#define SB_ERROR_GENERATE_PSS_RSA_SIGNATURE 0xFFF40000
+#define SB_ERROR_GENERATE_PUBLIC_KEY_INFO 0xFFF50000
+#define SB_ERROR_GENERATE_SB_CONTEXT 0xFFF60000
+#define SB_ERROR_ENCRYPTION 0xFFF70000
+
+#define SB_ERROR_AES_PARM 0x0000A000
+#define SB_ERROR_AES_SET_ALGO 0x0000B000
+#define SB_ERROR_AES_ENCRYPT 0x0000C000
+#define SB_ERROR_AES_DECRYPT 0x0000D000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_HMAC_SHA1_SET_INFO 0x00000010
+#define SB_ERROR_HMAC_SHA1_INIT 0x00000020
+#define SB_ERROR_HMAC_SHA1_UPDATE 0x00000030
+#define SB_ERROR_HMAC_SHA1_FINAL 0x00000040
+#define SB_ERROR_MEM_CMP 0x00000050
+#define SB_ERROR_SHA1_INIT 0x00000060
+#define SB_ERROR_SHA1_UPDATE 0x00000070
+#define SB_ERROR_SHA1_FINAL 0x00000080
+#define SB_ERROR_VERIFY_RSA_PSS 0x00000090
+
+////////////////////////////////////////////////////////////////////////
+//-------------------------------------------
+#define SB20_MAX_EFUSE_DATA_LEN 20
+
+#define SB20_MAX_RSA_KEY (2048/8)
+#define SB20_MAX_SIGN_LEN SB20_MAX_RSA_KEY
+
+#define SB20_HMAC_SHA1_LEN 20
+
+//-------------------------------------------
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_e_Len;
+ unsigned char rsa_e[4];
+} SB20_RSAPubKey;
+
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_d_Len;
+ unsigned char rsa_d[SB20_MAX_RSA_KEY];
+} SB20_RSAPrivKey;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey rsaPubKey;
+ unsigned char signedData[SB20_HMAC_SHA1_LEN];
+} SB20_PubKeyInfo;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey stage2PubKey;
+ int code_SignedDataLen;
+ unsigned char code_SignedData[SB20_MAX_SIGN_LEN];
+ SB20_PubKeyInfo pubKeyInfo;
+ unsigned char func_ptr_BaseAddr[128];
+ unsigned char reservedData[80];
+} SB20_CONTEXT;
+
+
+////////////////////////////////////////////////////////////////////////
+// Verify integrity of Kernel Image.
+int check_signature ( SB20_CONTEXT *sb20_Context, unsigned char *hash_code, int hash_code_len,
+ unsigned char *signed_data, int signed_data_len );
+
+int check_signature2 ( SB20_CONTEXT *sb20_Context, unsigned char *code_image, int code_image_len,
+ unsigned char *signed_data, int signed_data_len );
+
+///////////////////////////////////////////////////////////////////////////////////
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UBOOT_SB21_H */
diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile
index 922cd95448..5629a7c773 100644
--- a/arch/arm/cpu/armv7/s5p-common/Makefile
+++ b/arch/arm/cpu/armv7/s5p-common/Makefile
@@ -25,7 +25,6 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libs5p-common.o
-COBJS-y += cpu_info.o
COBJS-y += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c
index 651fd5ddff..2be12bb789 100644
--- a/arch/arm/cpu/armv7/s5p-common/timer.c
+++ b/arch/arm/cpu/armv7/s5p-common/timer.c
@@ -25,6 +25,7 @@
#include <common.h>
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/pwm.h>
#include <asm/arch/clk.h>
@@ -44,9 +45,17 @@ static unsigned long long timestamp; /* Monotonic incrementing timer */
static unsigned long lastdec; /* Last decremneter snapshot */
/* macro to read the 16 bit timer */
+
static inline struct s5p_timer *s5p_get_base_timer(void)
{
+ //return (struct s5p_timer *)samsung_get_base_timer();
+#if defined(CONFIG_ARCH_EXYNOS)
return (struct s5p_timer *)samsung_get_base_timer();
+#elif defined(CONFIG_S5PC210)
+ return (struct s5p_timer *)0x139D0000;
+#elif defined(CONFIG_S5PC110)
+ return (struct s5p_timer *)0xE2500000;
+#endif
}
int timer_init(void)
@@ -64,10 +73,10 @@ int timer_init(void)
/* set divider : 2 */
writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
-
/* count_value = 2085937.5(HZ) (per 1 sec)*/
- count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
- (MUX_DIV_2 + 1));
+ //count_value = get_pwm_clk() / ((PRESCALER_1 + 1) *
+ // (MUX_DIV_2 + 1));
+ count_value = 2500000;
/* count_value / 100 = 20859.375(HZ) (per 10 msec) */
count_value = count_value / 100;
diff --git a/arch/arm/cpu/armv7/s5pv210/Makefile b/arch/arm/cpu/armv7/s5pv210/Makefile
new file mode 100644
index 0000000000..00f658605b
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/Makefile
@@ -0,0 +1,72 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2011 Samsung Electronics Co. Ltd
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+#SOBJS += reset.o
+
+COBJS += irom_copy.o
+COBJS += onenand_cp.o
+#COBJS += nand.o
+#COBJS += nand_cp.o
+#ifdef CONFIG_CMD_NAND
+#COBJS += nand_write_bl.o
+#endif
+COBJS += pmic.o
+ifdef CONFIG_SECURE_BOOT
+COBJS += secure_boot.o
+COBJS += ace_sha1.o
+COBJS += security_check.o
+endif
+COBJS += reset.o
+COBJS += clock.o
+COBJS += setup_hsmmc.o
+COBJS += movi_partition.o
+#COBJS += sys_info.o
+#COBJS += usb_ohci.o
+#COBJS += usbd-otg-hs.o
+#COBJS += fastboot.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/s5pv210/ace_sha1.c b/arch/arm/cpu/armv7/s5pv210/ace_sha1.c
new file mode 100644
index 0000000000..ef69d2e735
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/ace_sha1.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * SHA1 Code using ACE (Advanced Crypto Engine)
+ *
+ * Based on SHA1 F/W Code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <ace_sha1.h>
+
+
+/*****************************************************************
+ Definitions
+*****************************************************************/
+#define read_u32(_addr_) \
+ (*(volatile unsigned int*)(_addr_))
+#define write_u32(_addr_, _val_) \
+ do {*(volatile unsigned int*)(_addr_) = (unsigned int)(_val_);} while(0)
+
+
+/*****************************************************************
+ Functions
+*****************************************************************/
+/**
+ * @brief This function computes hash value of input (pBuf[0]..pBuf[buflen-1]).
+ *
+ * @param pOut A pointer to the output buffer. When operation is completed
+ * 20 bytes are copied to pOut[0]...pOut[19]. Thus, a user
+ * should allocate at least 20 bytes at pOut in advance.
+ * @param pBuf A pointer to the input buffer
+ * @param bufLen Byte length of input buffer
+ *
+ * @return 0 Success
+ *
+ * @remark This function assumes that pBuf is a physical address of input buffer.
+ *
+ * @version V1.00
+ * @b Revision History
+ * - V01.00 2009.11.13/djpark Initial Version
+ */
+int SHA1_digest (
+ unsigned char* pOut,
+ unsigned char* pBuf,
+ unsigned int bufLen
+)
+{
+ unsigned int reg;
+ unsigned int* pDigest;
+
+ /* Flush HRDMA */
+ write_u32(ACE_FC_HRDMAC, FC_HRDMACFLUSH_ON);
+ write_u32(ACE_FC_HRDMAC, FC_HRDMACFLUSH_OFF);
+
+ /* Set byte swap of data in */
+ write_u32(ACE_HASH_BYTESWAP, HASH_SWAPDI_ON | HASH_SWAPDO_ON);
+
+ /* Select Hash input mux as external source */
+ reg = read_u32(ACE_FC_FIFOCTRL);
+ reg = (reg & ~FC_SELHASH_MASK) | FC_SELHASH_EXOUT;
+ write_u32(ACE_FC_FIFOCTRL, reg);
+
+ /* Set Hash as SHA1 and start Hash engine */
+ reg = HASH_ENGSEL_SHA1HASH | HASH_STARTBIT_ON;
+ write_u32(ACE_HASH_CONTROL, reg);
+
+ /* Enable FIFO mode */
+ write_u32(ACE_HASH_FIFO_MODE, HASH_FIFO_ON);
+
+ /* Set message length */
+ write_u32(ACE_HASH_MSGSIZE_LOW, bufLen);
+ write_u32(ACE_HASH_MSGSIZE_HIGH, 0);
+
+ /* Set HRDMA */
+ write_u32(ACE_FC_HRDMAS, (unsigned int)pBuf);
+ write_u32(ACE_FC_HRDMAL, bufLen);
+
+ do
+ {
+ reg = read_u32(ACE_HASH_STATUS) & HASH_MSGDONE_MASK;
+ } while (reg == HASH_MSGDONE_OFF);
+
+ /* Clear MSG_DONE bit */
+ write_u32(ACE_HASH_STATUS, reg);
+
+ /* Read hash result */
+ pDigest = (unsigned int*)pOut;
+ pDigest[0] = read_u32(ACE_HASH_OUT1);
+ pDigest[1] = read_u32(ACE_HASH_OUT2);
+ pDigest[2] = read_u32(ACE_HASH_OUT3);
+ pDigest[3] = read_u32(ACE_HASH_OUT4);
+ pDigest[4] = read_u32(ACE_HASH_OUT5);
+
+ /* Clear HRDMA pending bit */
+ write_u32(ACE_FC_INTPEND, FC_HRDMA);
+
+ return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/clock.c b/arch/arm/cpu/armv7/s5pv210/clock.c
new file mode 100644
index 0000000000..03d4554ba1
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/clock.c
@@ -0,0 +1,217 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+unsigned long (*get_uart_clk)(int dev_index);
+unsigned long (*get_pwm_clk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+void s5p_clock_init(void)
+{
+}
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+ ulong r, m, p, s;
+
+ if (pllreg == APLL) {
+ r = APLL_CON0_REG;
+ m = (r>>16) & 0x3ff;
+ } else if (pllreg == MPLL) {
+ r = MPLL_CON_REG;
+ m = (r>>16) & 0x3ff;
+ } else if (pllreg == EPLL) {
+ r = EPLL_CON_REG;
+ m = (r>>16) & 0x1ff;
+ } else
+ hang();
+
+ p = (r>>8) & 0x3f;
+ s = r & 0x7;
+
+ if (pllreg == APLL)
+ s= s-1;
+
+ return (m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s))));
+}
+
+/* return ARMCORE frequency */
+ulong get_ARMCLK(void)
+{
+ ulong div,apll_ratio;
+
+ div = CLK_DIV0_REG;
+ apll_ratio = ((div>>0) & 0x7);
+
+ return ((get_PLLCLK(APLL)) / (apll_ratio + 1));
+
+}
+
+/* return FCLK frequency */
+ulong get_FCLK(void)
+{
+ return (get_PLLCLK(APLL));
+}
+
+/* return FCLK frequency */
+ulong get_MPLL_CLK(void)
+{
+ return (get_PLLCLK(MPLL));
+}
+
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+ ulong fclk;
+ uint mux_stat = CLK_MUX_STAT0_REG;
+ uint div,hclk_msys_ratio,apll_ratio;
+
+ div = CLK_DIV0_REG;
+
+ apll_ratio = ((div>>0) & 0x7);
+ hclk_msys_ratio = ((div>>8)&0x7);
+
+ switch ((mux_stat>>16) & 0x7) {
+ case 2: //SCLKMPLL source
+ fclk = get_MPLL_CLK();
+ break;
+ case 1: //SCLKAPLL source
+ default:
+ fclk = get_FCLK();
+ break;
+ }
+
+ return fclk/((apll_ratio+1)*(hclk_msys_ratio+1));
+}
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+ ulong hclk;
+ uint div = CLK_DIV0_REG;
+ uint pclk_msys_ratio = ((div>>12) & 0x7);
+
+ hclk = get_HCLK();
+
+ return hclk/(pclk_msys_ratio+1);
+}
+
+/* return HCLKDSYS frequency */
+ulong get_HCLKD(void)
+{
+ ulong fclk;
+ uint mux_stat = CLK_MUX_STAT0_REG;
+
+ uint div,a2m_ratio,hclk_dsys_ratio;
+
+ div = CLK_DIV0_REG;
+
+ a2m_ratio = ((div >>4) & 0x7);
+ hclk_dsys_ratio = ((div >>16) & 0xf);
+
+ switch ((mux_stat>>20) & 0x7) {
+ case 2: //SCLKA2M source
+ fclk = get_FCLK()/(a2m_ratio+1);
+ break;
+ case 1: //SCLKMPLL source
+ default:
+ fclk = get_MPLL_CLK();
+ break;
+ }
+
+ return fclk/(hclk_dsys_ratio+1);
+}
+
+/* return PCLKDSYS frequency */
+ulong get_PCLKD(void)
+{
+ ulong fclk;
+ uint div = CLK_DIV0_REG;
+ uint pclk_dsys_ratio = ((div>>20) & 0x7);
+
+ fclk = get_HCLKD();
+
+ return fclk/(pclk_dsys_ratio+1);
+}
+
+/* return HCLKPSYS frequency */
+ulong get_HCLKP(void)
+{
+ ulong fclk;
+ uint mux_stat = CLK_MUX_STAT0_REG;
+ uint div,hclk_psys_ratio,a2m_ratio;
+
+ div = CLK_DIV0_REG;
+ a2m_ratio = ((div >>4) & 0x7);
+ hclk_psys_ratio = ((div>>24)&0xf);
+
+ switch ((mux_stat>>20) & 0x7) {
+ case 2: //SCLKA2M source
+ fclk = get_FCLK()/(a2m_ratio+1);
+ break;
+ case 1: //SCLKMPLL source
+ default:
+ fclk = get_MPLL_CLK();
+ break;
+ }
+
+
+ return fclk/(hclk_psys_ratio+1);
+}
+
+/* return PCLKPSYS frequency */
+ulong get_PCLKP(void)
+{
+ ulong fclk;
+ uint div = CLK_DIV0_REG;
+ uint pclk_psys_ratio = ((div>>28) & 0x7);
+
+ fclk = get_HCLKP();
+
+ return fclk/(pclk_psys_ratio+1);
+}
+
+/* return SCLKA2M frequency */
+ulong get_SCLKA2M(void)
+{
+ ulong fclk;
+ uint div = CLK_DIV0_REG;
+ uint a2m_ratio = ((div>>4) & 0x7);
+
+ fclk = get_FCLK();
+
+ return fclk/(a2m_ratio+1);
+}/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+ return (get_PLLCLK(EPLL));
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/irom_copy.c b/arch/arm/cpu/armv7/s5pv210/irom_copy.c
new file mode 100644
index 0000000000..cf0e9103b6
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/irom_copy.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+
+#if defined(CONFIG_SECURE_BOOT)
+#include <secure_boot.h>
+#endif
+
+extern raw_area_t raw_area_control;
+
+typedef u32(*copy_sd_mmc_to_mem)
+(u32 channel, u32 start_block, u16 block_size, u32 *trg, u32 init);
+
+
+typedef u32(*copy_emmc_to_mem)
+(u8 whthACK, u32 block_size, u32 *buffer, int buswidth);
+
+
+//#define CopyMMC4_3toMem(a,b,c,d) (((bool(*)(bool, unsigned int, unsigned int*, int))(*((unsigned int *)0xD0037F9C)))(a,b,c,d))
+
+void movi_bl2_copy(void)
+{
+ ulong ch;
+#if defined(CONFIG_EVT1)
+ ch = *(volatile u32 *)(0xD0037488);
+ copy_sd_mmc_to_mem copy_bl2 =
+ (copy_sd_mmc_to_mem) (*(u32 *) (0xD0037F98));
+
+ #if defined(CONFIG_SECURE_BOOT)
+ ulong rv;
+ #endif
+#else
+ ch = *(volatile u32 *)(0xD003A508);
+ copy_sd_mmc_to_mem copy_bl2 =
+ (copy_sd_mmc_to_mem) (*(u32 *) (0xD003E008));
+#endif
+ u32 ret;
+ if (ch == 0xEB000000) {
+ ret = copy_bl2(0, MOVI_BL2_POS, MOVI_BL2_BLKCNT,
+ CONFIG_PHY_UBOOT_BASE, 0);
+
+#if defined(CONFIG_SECURE_BOOT)
+ /* do security check */
+ rv = Check_Signature( (SecureBoot_CTX *)SECURE_BOOT_CONTEXT_ADDR,
+ (unsigned char *)CONFIG_PHY_UBOOT_BASE, (1024*512-128),
+ (unsigned char *)(CONFIG_PHY_UBOOT_BASE+(1024*512-128)), 128 );
+ if (rv != 0){
+ while(1);
+ }
+#endif
+ }
+ else if (ch == 0xEB200000) {
+ ret = copy_bl2(2, MOVI_BL2_POS, MOVI_BL2_BLKCNT,
+ CONFIG_PHY_UBOOT_BASE, 0);
+
+#if defined(CONFIG_SECURE_BOOT)
+ /* do security check */
+ rv = Check_Signature( (SecureBoot_CTX *)SECURE_BOOT_CONTEXT_ADDR,
+ (unsigned char *)CONFIG_PHY_UBOOT_BASE, (1024*512-128),
+ (unsigned char *)(CONFIG_PHY_UBOOT_BASE+(1024*512-128)), 128 );
+ if (rv != 0) {
+ while(1);
+ }
+#endif
+ }
+ else
+ return;
+
+ if (ret == 0)
+ while (1)
+ ;
+ else
+ return;
+}
+
+void emmc_bl2_copy(void)
+{
+ copy_emmc_to_mem copy_bl2 =
+ (copy_emmc_to_mem) (*(u32 *) (0xD0037F9C));
+
+#if 0//defined(CONFIG_SECURE_BOOT)
+ volatile u32 * pub_key;
+ int secure_booting;
+ int i;
+ ulong rv;
+#endif
+
+ //u32 ret;
+ copy_bl2(0, MOVI_BL2_BLKCNT, CONFIG_PHY_UBOOT_BASE, 4);
+
+#if 0//defined(CONFIG_SECURE_BOOT)
+ pub_key = (volatile u32 *)SECURE_KEY_ADDRESS;
+ secure_booting = 0;
+
+ for(i=0;i<33;i++){
+ if( *(pub_key+i) != 0x0) secure_booting = 1;
+ }
+
+ if (secure_booting == 1) {
+ /* do security check */
+ rv = Check_IntegrityOfImage( (SecureBoot_CTX *)SECURE_KEY_ADDRESS, (unsigned char*)CFG_PHY_UBOOT_BASE,
+ (1024*512-128), (unsigned char*)(CONFIG_PHY_UBOOT_BASE+(1024*512-128)), 128 );
+
+ if (rv != 0){
+ while(1);
+ }
+ }
+#endif
+ return;
+}
+
+
+/*
+ * Copy zImage from SD/MMC to mem
+ */
+#ifdef CONFIG_MCP_SINGLE
+#if 0
+void movi_zImage_copy(void)
+{
+ copy_sd_mmc_to_mem copy_zImage =
+ (copy_sd_mmc_to_mem) (*(u32 *) COPY_SDMMC_TO_MEM);
+ u32 ret;
+
+ /*
+ * 0x3C6FCE is total size of 2GB SD/MMC card
+ * TODO : eMMC will be used as boot device on HP proto2 board
+ * So, total size of eMMC will be re-defined next board.
+ */
+ ret =
+ copy_zImage(0, 0x3C6FCE, MOVI_ZIMAGE_BLKCNT, CFG_PHY_KERNEL_BASE,
+ 1);
+
+ if (ret == 0)
+ while (1)
+ ;
+ else
+ return;
+}
+#endif
+#endif
+
+void print_movi_bl2_info(void)
+{
+ printf("%d, %d, %d\n", MOVI_BL2_POS, MOVI_BL2_BLKCNT, MOVI_ENV_BLKCNT);
+}
+
+void movi_write_env(ulong addr)
+{
+ movi_write(raw_area_control.image[2].start_blk,
+ raw_area_control.image[2].used_blk, addr);
+}
+
+void movi_read_env(ulong addr)
+{
+ movi_read(raw_area_control.image[2].start_blk,
+ raw_area_control.image[2].used_blk, addr);
+}
+
+void movi_write_bl1(ulong addr, u32 dev_num)
+{
+ int i;
+ ulong checksum;
+ ulong src;
+ ulong tmp;
+
+ src = addr;
+#if defined(CONFIG_EVT1)
+ addr += 16;
+ for (i = 16, checksum = 0; i < SS_SIZE; i++) {
+ checksum += *(u8 *) addr++;
+ }
+ printf("checksum : 0x%x\n", checksum);
+ *(volatile u32 *)(src + 0x8) = checksum;
+ movi_write(dev_num, raw_area_control.image[1].start_blk,
+ raw_area_control.image[1].used_blk, src);
+#else
+ for (i = 0, checksum = 0; i < SS_SIZE - 4; i++) {
+ checksum += *(u8 *) addr++;
+ }
+
+ tmp = *(ulong *) addr;
+ *(ulong *) addr = checksum;
+
+ movi_write(dev_num, raw_area_control.image[0].start_blk,
+ raw_area_control.image[0].used_blk, src);
+
+ *(ulong *) addr = tmp;
+#endif
+}
+
+#if defined(CONFIG_VOGUES)
+int movi_boot_src()
+{
+ ulong reg;
+ ulong src;
+
+ reg = (*(volatile u32 *)(INF_REG_BASE + INF_REG3_OFFSET));
+
+ if (reg == BOOT_MMCSD)
+ /* boot device is SDMMC */
+ src = 0;
+ else if (reg == BOOT_NOR)
+ /* boot device is NOR */
+ src = 1;
+
+ return src;
+}
+#endif
diff --git a/arch/arm/cpu/armv7/s5pv210/movi_partition.c b/arch/arm/cpu/armv7/s5pv210/movi_partition.c
new file mode 100644
index 0000000000..09abcf4bc1
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/movi_partition.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/movi_partition.h>
+
+#ifdef DEBUG_MOVI_PARTITION
+#define dbg(x...) printf(x)
+#else
+#define dbg(x...) do { } while (0)
+#endif
+
+raw_area_t raw_area_control;
+
+int init_raw_area_table(block_dev_desc_t * dev_desc, int location)
+{
+ int i;
+ member_t *image;
+ u32 capacity;
+
+ /* init raw_area will be 16MB */
+ raw_area_control.start_blk = 16*1024*1024/MOVI_BLKSIZE;
+ raw_area_control.next_raw_area = 0;
+ strcpy(raw_area_control.description, "initial raw table");
+
+ image = raw_area_control.image;
+
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ #if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_BL1_ONLY)
+ /* image 0 should be fwbl1 */
+ image[0].start_blk = location;
+ image[0].used_blk = MOVI_FWBL1_BLKCNT;
+ image[0].size = FWBL1_SIZE;
+ image[0].attribute = 0x0;
+ strcpy(image[0].description, "fwbl1");
+ dbg("fwbl1: %d\n", image[0].start_blk);
+ #endif
+#endif
+
+ /* image 1 should be bl2 */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ #if defined(CONFIG_SECURE_BOOT) || defined(CONFIG_SECURE_BL1_ONLY)
+ image[1].start_blk = image[0].start_blk + MOVI_FWBL1_BLKCNT;
+ #else
+ image[1].start_blk = location;
+ #endif
+#else
+ image[1].start_blk = capacity - (eFUSE_SIZE/MOVI_BLKSIZE) - MOVI_BL1_BLKCNT;
+#endif
+ image[1].used_blk = MOVI_BL1_BLKCNT;
+ image[1].size = SS_SIZE;
+ #if defined(CONFIG_SECURE_BOOT)
+ image[1].attribute = 0x3;
+ #else
+ image[1].attribute = 0x1;
+ #endif
+ strcpy(image[1].description, "u-boot parted");
+ dbg("bl1: %d\n", image[1].start_blk);
+
+ /* image 2 should be environment */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ image[2].start_blk = image[1].start_blk + MOVI_BL1_BLKCNT;
+#else
+ image[2].start_blk = image[1].start_blk - MOVI_ENV_BLKCNT;
+#endif
+ image[2].used_blk = MOVI_ENV_BLKCNT;
+ image[2].size = CONFIG_ENV_SIZE;
+ image[2].attribute = 0x10;
+ strcpy(image[2].description, "environment");
+ dbg("env: %d\n", image[2].start_blk);
+
+ /* image 3 should be u-boot */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ #if defined(CONFIG_EMMC)
+ image[3].start_blk = image[2].start_blk;
+ #else
+ image[3].start_blk = image[2].start_blk + MOVI_ENV_BLKCNT;
+ #endif
+#else
+ image[3].start_blk = image[2].start_blk - MOVI_BL2_BLKCNT;
+#endif
+ image[3].used_blk = MOVI_BL2_BLKCNT;
+ image[3].size = PART_SIZE_BL;
+ image[3].attribute = 0x2;
+ strcpy(image[3].description, "u-boot");
+ dbg("bl2: %d\n", image[3].start_blk);
+
+ /* image 4 should be kernel */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ image[4].start_blk = image[3].start_blk + MOVI_BL2_BLKCNT;
+#else
+ image[4].start_blk = image[3].start_blk - MOVI_ZIMAGE_BLKCNT;
+#endif
+ image[4].used_blk = MOVI_ZIMAGE_BLKCNT;
+ image[4].size = PART_SIZE_KERNEL;
+ image[4].attribute = 0x4;
+ strcpy(image[4].description, "kernel");
+ dbg("knl: %d\n", image[4].start_blk);
+
+ /* image 5 should be RFS */
+#if defined(CONFIG_EVT1) && defined(CONFIG_S5PC110)
+ image[5].start_blk = image[4].start_blk + MOVI_ZIMAGE_BLKCNT;
+#else
+ image[5].start_blk = image[4].start_blk - MOVI_ROOTFS_BLKCNT;
+#endif
+ image[5].used_blk = MOVI_ROOTFS_BLKCNT;
+ image[5].size = PART_SIZE_ROOTFS;
+ image[5].attribute = 0x8;
+ strcpy(image[5].description, "rfs");
+ dbg("rfs: %d\n", image[5].start_blk);
+
+ for (i=6; i<15; i++) {
+ raw_area_control.image[i].start_blk = 0;
+ raw_area_control.image[i].used_blk = 0;
+ }
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/onenand_cp.c b/arch/arm/cpu/armv7/s5pv210/onenand_cp.c
new file mode 100644
index 0000000000..14d1eb522a
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/onenand_cp.c
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Copy U-Boot code from OneNAND into DRAM (UBOOT_PHY_BASE).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/mtd/onenand_regs.h>
+
+#if defined(CONFIG_SECURE_BOOT)
+#include <secure_boot.h>
+#endif
+
+#ifdef CONFIG_BOOT_ONENAND_IROM
+
+#define ONENAND_BASE (CFG_ONENAND_BASE)
+
+#if defined(CONFIG_MCP_AC) || defined(CONFIG_MCP_B) || defined(CONFIG_MCP_D) || defined(CONFIG_MCP_N)
+#define ONENAND_PAGE_SIZE 4096
+#elif defined(CONFIG_MCP_H)
+#define ONENAND_PAGE_SIZE 2048
+#else // default page size (for V210 daughter board)
+#define ONENAND_PAGE_SIZE 2048
+#endif
+
+#if defined(CONFIG_EVT1)
+#if defined(CONFIG_FUSED)
+#define FWBL1_SIZE (4096)
+
+#if defined(CONFIG_SECURE_BOOT)
+#define BL2_SIZE (8192)
+#define UBOOT_START_BLOCK ((FWBL1_SIZE / ONENAND_PAGE_SIZE) + (BL2_SIZE / ONENAND_PAGE_SIZE))
+#else
+#define UBOOT_START_BLOCK (FWBL1_SIZE / ONENAND_PAGE_SIZE)
+#endif
+
+#else
+#define UBOOT_START_BLOCK (0)
+#endif
+
+#else
+#error "Unsupported H/W version!"
+#error "To support EVT0, a seperated BL1 is required!"
+#endif
+
+
+#define READ_INTERRUPT() \
+ onenand_readw(ONENAND_BASE + ONENAND_REG_INTERRUPT)
+
+#define onenand_block_address(block) (block)
+#define onenand_sector_address(page) (page << ONENAND_FPA_SHIFT)
+#define onenand_buffer_address() ((1 << 3) << 8)
+//#define onenand_buffer_address() ((0 << 3) << 8)
+#define onenand_bufferram_address(block) (0)
+
+inline unsigned short onenand_readw (unsigned int addr)
+{
+ return *(unsigned short*)addr;
+}
+
+inline void onenand_writew (unsigned short value, unsigned int addr)
+{
+ *(unsigned short*)addr = value;
+}
+
+void onenand_loadpage (unsigned int block, unsigned int page)
+{
+ // Block Number
+ onenand_writew(onenand_block_address(block),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS1);
+
+ // BufferRAM
+ onenand_writew(onenand_bufferram_address(block),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS2);
+
+ // Page (Sector) Number Set: FPA, FSA
+ onenand_writew(onenand_sector_address(page),
+ ONENAND_BASE + ONENAND_REG_START_ADDRESS8);
+
+ // BSA, BSC
+ onenand_writew(onenand_buffer_address(),
+ ONENAND_BASE + ONENAND_REG_START_BUFFER);
+
+ // Interrupt clear
+ onenand_writew(ONENAND_INT_CLEAR, ONENAND_BASE + ONENAND_REG_INTERRUPT);
+
+ onenand_writew(ONENAND_CMD_READ, ONENAND_BASE + ONENAND_REG_COMMAND);
+
+#if 1
+ while (!(READ_INTERRUPT() & ONENAND_INT_READ))
+ continue;
+#else
+ while (!(READ_INTERRUPT() & ONENAND_INT_MASTER))
+ continue;
+#endif
+}
+
+int onenand_isbad (unsigned int block)
+{
+ unsigned short* src;
+
+ onenand_loadpage(block, 0);
+
+ src = (unsigned short *)(ONENAND_BASE + ONENAND_SPARERAM);
+ if (src[0] == (unsigned short)0xFFFF)
+ return 0;
+ else
+ return 1;
+}
+
+void onenand_readpage (void* base, unsigned int block, unsigned int page)
+{
+ int len;
+ unsigned short* dest;
+ unsigned short* src;
+
+ onenand_loadpage(block, page);
+
+ len = ONENAND_PAGE_SIZE >> 1;
+ dest = (unsigned short *)(base);
+ src = (unsigned short *)(ONENAND_BASE + ONENAND_DATARAM);
+ while (len-- > 0)
+ {
+ *dest++ = *src++;
+ }
+}
+
+/*
+ * Copy U-Boot from OneNAND to DRAM (512KB)
+ */
+void onenand_bl2_copy(void)
+{
+ int rv;
+
+ unsigned int base = CONFIG_PHY_UBOOT_BASE;
+ int download_size = 512 * 1024; /* U-boot image size */
+ int block = 0; /* Start block */
+
+ int page = UBOOT_START_BLOCK; /* Start page */
+
+ do {
+ onenand_readpage((void *)base, block, page);
+
+ base += ONENAND_PAGE_SIZE;
+ download_size -= ONENAND_PAGE_SIZE;
+
+ if (++page == 64) {
+ page = 0;
+ do {
+ block++;
+ } while (onenand_isbad(block));
+ }
+ } while (download_size > 0);
+
+#if defined(CONFIG_SECURE_BOOT)
+ rv = Check_Signature((SecureBoot_CTX *)SECURE_BOOT_CONTEXT_ADDR,
+ (unsigned char *)CONFIG_PHY_UBOOT_BASE,
+ (1024*512 - 128),
+ (unsigned char *)(CONFIG_PHY_UBOOT_BASE + (1024*512-128)),
+ 128);
+ if (rv != SB_OK)
+ while(1);
+#endif
+
+}
+
+#endif /* CONFIG_BOOT_ONENAND_IROM */
+
diff --git a/arch/arm/cpu/armv7/s5pv210/pmic.c b/arch/arm/cpu/armv7/s5pv210/pmic.c
new file mode 100644
index 0000000000..3e3b272114
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/pmic.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/pmic.h>
+
+void Delay(void)
+{
+ unsigned long i,j;
+ for(i=0;i<DELAY;i++);
+}
+
+void SCLH_SDAH()
+{
+ IIC_ESCL_Hi;
+ IIC_ESDA_Hi;
+ Delay();
+}
+
+void SCLH_SDAL()
+{
+ IIC_ESCL_Hi;
+ IIC_ESDA_Lo;
+ Delay();
+}
+
+void SCLL_SDAH()
+{
+ IIC_ESCL_Lo;
+ IIC_ESDA_Hi;
+ Delay();
+}
+
+void SCLL_SDAL()
+{
+ IIC_ESCL_Lo;
+ IIC_ESDA_Lo;
+ Delay();
+}
+
+void IIC_ELow()
+{
+ SCLL_SDAL();
+ SCLH_SDAL();
+ SCLH_SDAL();
+ SCLL_SDAL();
+}
+
+void IIC_EHigh()
+{
+ SCLL_SDAH();
+ SCLH_SDAH();
+ SCLH_SDAH();
+ SCLL_SDAH();
+}
+
+void IIC_EStart()
+{
+ SCLH_SDAH();
+ SCLH_SDAL();
+ Delay();
+ SCLL_SDAL();
+}
+
+void IIC_EEnd()
+{
+ SCLL_SDAL();
+ SCLH_SDAL();
+ Delay();
+ SCLH_SDAH();
+}
+
+void IIC_EAck()
+{
+ unsigned long ack;
+
+ IIC_ESDA_INP; // Function <- Input
+
+ IIC_ESCL_Lo;
+ Delay();
+ IIC_ESCL_Hi;
+ Delay();
+ ack = GPD1DAT;
+ IIC_ESCL_Hi;
+ Delay();
+ IIC_ESCL_Hi;
+ Delay();
+
+ IIC_ESDA_OUTP; // Function <- Output (SDA)
+
+ ack = (ack>>4)&0x1;
+ while(ack!=0);
+
+ SCLL_SDAL();
+}
+
+void IIC_ESetport(void)
+{
+ GPD1PUD &= ~(0xf<<8); // Pull Up/Down Disable SCL, SDA
+
+ IIC_ESCL_Hi;
+ IIC_ESDA_Hi;
+
+ IIC_ESCL_OUTP; // Function <- Output (SCL)
+ IIC_ESDA_OUTP; // Function <- Output (SDA)
+
+ Delay();
+}
+
+void IIC_EWrite (unsigned char ChipId, unsigned char IicAddr, unsigned char IicData)
+{
+ unsigned long i;
+
+ IIC_EStart();
+
+////////////////// write chip id //////////////////
+ for(i = 7; i>0; i--)
+ {
+ if((ChipId >> (i-1)) & 0x0001)
+ IIC_EHigh();
+ else
+ IIC_ELow();
+ }
+
+ IIC_ELow(); // write 'W'
+
+ IIC_EAck(); // ACK
+
+////////////////// write reg. addr. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicAddr >> (i-1)) & 0x0001)
+ IIC_EHigh();
+ else
+ IIC_ELow();
+ }
+
+ IIC_EAck(); // ACK
+
+////////////////// write reg. data. //////////////////
+ for(i = 8; i>0; i--)
+ {
+ if((IicData >> (i-1)) & 0x0001)
+ IIC_EHigh();
+ else
+ IIC_ELow();
+ }
+
+ IIC_EAck(); // ACK
+
+ IIC_EEnd();
+}
+
+void pmic_init(void)
+{
+ IIC_ESetport();
+
+#if !(defined(CONFIG_SMDKC110_REV03) || defined(CONFIG_SMDKV210_REV02))
+ IIC_EWrite(MAX8698_ADDR, 0x00, 0x3E);
+ IIC_EWrite(MAX8698_ADDR, 0x01, 0xF0);
+
+ // VDD_ARM
+#if defined(CONFIG_CLK_1200_200_166_133)
+ IIC_EWrite(MAX8698_ADDR, 0x04, 0xBB); // default:0x99=>1.2v, 0xBB=>1.30v
+ IIC_EWrite(MAX8698_ADDR, 0x05, 0xBB); // default:0x99=>1.2v, 0xBB=>1.30v
+#elif defined (CONFIG_CLK_1000_200_166_133)
+ IIC_EWrite(MAX8698_ADDR, 0x04, 0xAA); // default:0x99=>1.2v, 0xAA=>1.25v
+ IIC_EWrite(MAX8698_ADDR, 0x05, 0xAA); // default:0x99=>1.2v, 0xAA=>1.25v
+#else
+ IIC_EWrite(MAX8698_ADDR, 0x04, 0x99); // default:0x99=>1.2v, 0x99=>1.2v
+ IIC_EWrite(MAX8698_ADDR, 0x05, 0x99); // default:0x99=>1.2v, 0x99=>1.2v
+#endif
+
+ // VDD_INT
+#if defined(CONFIG_CLK_1200_200_166_133)
+ IIC_EWrite(MAX8698_ADDR, 0x06, 0x88); // default:0x99=>1.2v, 0x88=>1.15v
+#else
+ IIC_EWrite(MAX8698_ADDR, 0x06, 0x77); // default:0x99=>1.2v, 0x77=>1.1v
+#endif
+ IIC_EWrite(MAX8698_ADDR, 0x07, 0x02);
+
+ IIC_EWrite(MAX8698_ADDR, 0x08, 0x66);
+ IIC_EWrite(MAX8698_ADDR, 0x09, 0x02);
+ IIC_EWrite(MAX8698_ADDR, 0x0A, 0x0C);
+ IIC_EWrite(MAX8698_ADDR, 0x0B, 0x0A);
+ IIC_EWrite(MAX8698_ADDR, 0x0C, 0x0E);
+ IIC_EWrite(MAX8698_ADDR, 0x0D, 0x33);
+ IIC_EWrite(MAX8698_ADDR, 0x0E, 0x0E);
+#else /* CONFIG_SMDKC110_REV03, CONFIG_SMDKV210_REV02 */
+ IIC_EWrite(MAX8998_ADDR, 0x11, 0x2F); // VDD_ARM, VDD_INT disable
+ IIC_EWrite(MAX8998_ADDR, 0x12, 0xFB);
+ IIC_EWrite(MAX8998_ADDR, 0x13, 0x00);
+
+ // VDD_ARM
+#if defined(CONFIG_CLK_1200_200_166_133)
+ IIC_EWrite(MAX8998_ADDR, 0x15, 0x16); // default:0x12=>1.2v, 0x16=>1.30v
+ IIC_EWrite(MAX8998_ADDR, 0x16, 0x16); // default:0x12=>1.2v, 0x16=>1.30v
+ IIC_EWrite(MAX8998_ADDR, 0x17, 0x16); // default:0x12=>1.2v, 0x16=>1.30v
+ IIC_EWrite(MAX8998_ADDR, 0x18, 0x16); // default:0x12=>1.2v, 0x16=>1.30v
+#elif defined (CONFIG_CLK_1000_200_166_133)
+ IIC_EWrite(MAX8998_ADDR, 0x15, 0x14); // default:0x12=>1.2v, 0x14=>1.25v
+ IIC_EWrite(MAX8998_ADDR, 0x16, 0x14); // default:0x12=>1.2v, 0x14=>1.25v
+ IIC_EWrite(MAX8998_ADDR, 0x17, 0x14); // default:0x12=>1.2v, 0x14=>1.25v
+ IIC_EWrite(MAX8998_ADDR, 0x18, 0x14); // default:0x12=>1.2v, 0x14=>1.25v
+#else
+ IIC_EWrite(MAX8998_ADDR, 0x15, 0x12); // default:0x12=>1.2v, 0x12=>1.2v
+ IIC_EWrite(MAX8998_ADDR, 0x16, 0x12); // default:0x12=>1.2v, 0x12=>1.2v
+ IIC_EWrite(MAX8998_ADDR, 0x17, 0x12); // default:0x12=>1.2v, 0x12=>1.2v
+ IIC_EWrite(MAX8998_ADDR, 0x18, 0x12); // default:0x12=>1.2v, 0x12=>1.2v
+#endif
+
+ // VDD_INT
+#if defined(CONFIG_CLK_1200_200_166_133)
+ IIC_EWrite(MAX8998_ADDR, 0x19, 0x10); // default:0x12=>1.2v, 0x10=>1.15v
+ IIC_EWrite(MAX8998_ADDR, 0x1A, 0x10); // default:0x12=>1.2v, 0x10=>1.15v
+#else
+ IIC_EWrite(MAX8998_ADDR, 0x19, 0x0E); // default:0x12=>1.2v, 0x0E=>1.1v
+ IIC_EWrite(MAX8998_ADDR, 0x1A, 0x0E); // default:0x12=>1.2v, 0x0E=>1.1v
+#endif
+ // VDD_MEM
+ IIC_EWrite(MAX8998_ADDR, 0x1B, 0x02); // default:0x02=>1.8v, 0x02=>1.8v
+
+ IIC_EWrite(MAX8998_ADDR, 0x1D, 0x66); // LDO2 = 1.1v, LDO3 = 1.1v
+ IIC_EWrite(MAX8998_ADDR, 0x1E, 0x02); // LDO4 = 1.8v
+ IIC_EWrite(MAX8998_ADDR, 0x1F, 0x0C); // LDO5 = 2.8v
+ IIC_EWrite(MAX8998_ADDR, 0x20, 0x0A); // LDO6 = 2.6v
+ IIC_EWrite(MAX8998_ADDR, 0x21, 0x0E); // LDO7 = 3.0v
+ IIC_EWrite(MAX8998_ADDR, 0x22, 0x32); // LDO8 = 3.3v, LDO9 = 3.0v
+
+ IIC_EWrite(MAX8998_ADDR, 0x23, 0x60); // LDO10 = 1.1v, LDO11 = not used
+ IIC_EWrite(MAX8998_ADDR, 0x24, 0x03); // LDO12 = 1.1v
+ IIC_EWrite(MAX8998_ADDR, 0x25, 0x14); // LDO13 = 2.8v
+#endif
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/reset.c b/arch/arm/cpu/armv7/s5pv210/reset.c
new file mode 100644
index 0000000000..c1f796617a
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/reset.c
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+/* * reset the cpu by setting up the watchdog timer and let him time out */
+void reset_cpu(ulong ignored)
+{
+ printf("reset... \n\n\n");
+
+ SW_RST_REG = 0x1;
+
+ /* loop forever and wait for reset to happen */
+ while (1)
+ {
+ if (serial_tstc())
+ {
+ serial_getc();
+ break;
+ }
+ }
+ /*NOTREACHED*/
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/secure.h b/arch/arm/cpu/armv7/s5pv210/secure.h
new file mode 100644
index 0000000000..98e5cf1caf
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/secure.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _SECURE_H_
+#define _SECURE_H_
+
+#define IN
+#define OUT
+
+/* Return Value Definition */
+#define SB_OK 0x00000000
+#define SB_OFF 0x80000000
+
+#define SB_ERROR_VALIDATE_PUBLIC_KEY_INFO 0xFFF10000
+#define SB_ERROR_VERIFY_PSS_RSA_SIGNATURE 0xFFF20000
+#define SB_ERROR_CHECK_INTEGRITY_CODE 0xFFF30000
+
+#define SB_ERROR_HMAC_SHA1_SET_INFO 0x00000010
+#define SB_ERROR_HMAC_SHA1_INIT 0x00000020
+#define SB_ERROR_HMAC_SHA1_UPDATE 0x00000030
+#define SB_ERROR_HMAC_SHA1_FINAL 0x00000040
+#define SB_ERROR_MEM_CMP 0x00000050
+#define SB_ERROR_SHA1_INIT 0x00000060
+#define SB_ERROR_SHA1_UPDATE 0x00000070
+#define SB_ERROR_SHA1_FINAL 0x00000080
+#define SB_ERROR_VERIFY_RSA_PSS 0x00000090
+
+#define MAX_EFUSE_DATA_LEN 16
+
+typedef struct
+{
+ unsigned char rsa_n[128]; /* RSA Modulus N */
+ unsigned char rsa_e[4]; /* RSA Public Exponent E */
+} RawRSAPublicKey;
+
+typedef struct
+{
+ RawRSAPublicKey rsaPubKey; /* RSA PublicKey */
+ unsigned char signedData[20]; /* HMAC Value of RSA PublicKey */
+} PubKeyInfo;
+
+/* Secure Boot Context */
+typedef struct
+{
+ RawRSAPublicKey stage2PubKey; /* Stage2 RSA Public Key */
+ unsigned char code_SignedData[128]; /* RSA Signature Value */
+ PubKeyInfo pubKeyInfo; /* Stage1 RSA PublicKey and it's HMAC value */
+ unsigned char func_ptr_BaseAddr[48]; /* Function pointer of iROM's secure boot function */
+ unsigned char test_eFuse[MAX_EFUSE_DATA_LEN];
+ unsigned char reservedData[36];
+} SecureBoot_CTX;
+
+/* Verify integrity of Image. */
+int Check_IntegrityOfImage (
+ IN SecureBoot_CTX *sbContext,
+ IN unsigned char *BL2,
+ IN int BL2Len,
+ IN unsigned char *BL2_SignedData,
+ IN int BL2_SignedDataLen );
+
+#endif /* _BL1_SB_C110_H_ */
diff --git a/arch/arm/cpu/armv7/s5pv210/secure_boot.c b/arch/arm/cpu/armv7/s5pv210/secure_boot.c
new file mode 100644
index 0000000000..fea7820904
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/secure_boot.c
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <secure_boot.h>
+#include <ace_sha1.h>
+
+//#define SW_SHA1 (1)
+
+#define SHA1_BLOCK_LEN 64 /* Input Message Block Length */
+#define SHA1_DIGEST_LEN 20 /* Hash Code Length */
+
+/* SHA1 Context */
+typedef struct
+{
+ unsigned int auChain[SHA1_DIGEST_LEN/4]; /* Chaining Variable */
+ unsigned int auCount[2]; /* the number of input message bit */
+ unsigned char abBuffer[SHA1_BLOCK_LEN]; /* Buffer for unfilled block */
+} SHA1_ALG_INFO;
+
+/* int sscl_memcmp(BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memcmp(BASE_FUNC_PTR,a,b,c) \
+ (((int(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 0))))\
+ ((a),(b),(c)))
+
+/* void sscl_memcpy(BYTE *pbDst, BYTE *pbSrc, DWORD uByteLen); */
+#define macro_sscl_memcpy(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 4))))\
+ ((a),(b),(c)))
+
+//void sscl_memset(BYTE *pbDst, BYTE bValue, DWORD uByteLen); */
+#define macro_sscl_memset(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 8))))\
+ ((a),(b),(c)))
+
+/* void sscl_memxor(BYTE *pbDst, BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memxor(BASE_FUNC_PTR,a,b,c,d) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 12))))\
+ ((a),(b),(c),(d)))
+
+/* unsigned int SEC_SHA1_Init(SHA1_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 16))))\
+ ((a)))
+
+/* unsigned SEC_SHA1_Update(SHA1_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 20))))\
+ ((a),(b),(c)))
+
+/* unsigned SEC_SHA1_Final( SHA1_ALG_INFO *psAlgInfo, BYTE *pbDigest); */
+#define macro_SEC_SHA1_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 24))))\
+ ((a),(b)))
+
+/* RET_VAL SEC_SHA1_HMAC_SetInfo( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbUserKey, DWORD uUKeyLen ); */
+#define macro_SEC_SHA1_HMAC_SetInfo(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 28))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Init(SHA1_HMAC_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_HMAC_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 32))))\
+ ((a)))
+
+/* RET_VAL SEC_SHA1_HMAC_Update(SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_HMAC_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 36))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Final( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbHmacVal); */
+#define macro_SEC_SHA1_HMAC_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 40))))\
+ ((a),(b)))
+
+/* int Verify_PSS_RSASignature (
+ * IN unsigned char *rawRSAPublicKey,
+ * IN int rawRSAPublicKeyLen,
+ * IN unsigned char *hashCode,
+ * IN int hashCodeLen,
+ * IN unsigned char *signature,
+ * IN int signatureLen);
+ */
+#define macro_Verify_PSS_RSASignature(BASE_FUNC_PTR,a,b,c,d,e,f) \
+ (((int(*)(unsigned char *, int, unsigned char *, int, unsigned char*, int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 44))))\
+ ((a),(b),(c),(d),(e),(f)))
+
+
+/* Verify integrity of BL2(or OS) Image. */
+int Check_Signature (
+ IN SecureBoot_CTX *sbContext,
+ IN unsigned char *data,
+ IN int dataLen,
+ IN unsigned char *signedData,
+ IN int signedDataLen )
+{
+ unsigned int rv;
+ unsigned char hashCode[SHA1_DIGEST_LEN];
+ int hashCodeLen = SHA1_DIGEST_LEN;
+ unsigned int SBoot_BaseFunc_ptr;
+ SHA1_ALG_INFO algInfo;
+ RawRSAPublicKey tempPubKey;
+ SBoot_BaseFunc_ptr = (unsigned int)sbContext->func_ptr_BaseAddr;
+
+ /* 0. if stage2 pubkey is 0x00, do NOT check integrity. */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *)&tempPubKey,
+ 0x00,
+ sizeof(RawRSAPublicKey));
+
+ rv = macro_sscl_memcmp(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ (unsigned char *)&tempPubKey,
+ sizeof(RawRSAPublicKey));
+
+ if (rv == 0)
+ return SB_OFF;
+
+ /* 1. Make HashCode */
+ /* 1-1. SHA1 Init */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *) &algInfo,
+ 0x00,
+ sizeof(SHA1_ALG_INFO));
+
+#if defined(SW_SHA1)
+ macro_SEC_SHA1_Init(SBoot_BaseFunc_ptr, &algInfo );
+
+ /* 1-3. SHA1 Update. */
+ macro_SEC_SHA1_Update(SBoot_BaseFunc_ptr, &algInfo, data, dataLen );
+
+ /* 1-4. SHA1 Final. */
+ macro_SEC_SHA1_Final(SBoot_BaseFunc_ptr, &algInfo, hashCode );
+#else
+ SHA1_digest(hashCode, data, dataLen);
+#endif
+ /* 2. BL2's signature verification */
+ rv = macro_Verify_PSS_RSASignature(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ sizeof(RawRSAPublicKey),
+ hashCode, hashCodeLen,
+ signedData, signedDataLen );
+ if ( rv != SB_OK )
+ return rv;
+
+ return SB_OK;
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/security_check.c b/arch/arm/cpu/armv7/s5pv210/security_check.c
new file mode 100644
index 0000000000..3a650ad183
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/security_check.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <secure_boot.h>
+
+void security_check(void)
+{
+ /* do security check */
+ if(Check_Signature( (SecureBoot_CTX *)SECURE_BOOT_CONTEXT_ADDR,
+ (unsigned char*)CONFIG_SECURE_KERNEL_BASE,
+ CONFIG_SECURE_KERNEL_SIZE-128,
+ (unsigned char*)(CONFIG_SECURE_KERNEL_BASE+CONFIG_SECURE_KERNEL_SIZE-128),
+ 128 ) != 0) {
+ printf("Kernel Integrity check fail\nSystem Halt....");
+ while(1);
+ }
+ printf("Kernel Integirty check success.\n");
+
+#ifdef CONFIG_SECURE_ROOTFS
+ if(Check_Signature( (SecureBoot_CTX *)SECURE_BOOT_CONTEXT_ADDR,
+ (unsigned char*)CONFIG_SECURE_ROOTFS_BASE,
+ CONFIG_SECURE_ROOTFS_SIZE-128,
+ (unsigned char*)(CONFIG_SECURE_ROOTFS_BASE+CONFIG_SECURE_ROOTFS_SIZE-128),
+ 128 ) != 0) {
+ printf("rootfs Integrity check fail\nSystem Halt....");
+ while(1);
+ }
+ printf("rootfs Integirty check success.\n");
+#endif
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv210/setup_hsmmc.c b/arch/arm/cpu/armv7/s5pv210/setup_hsmmc.c
new file mode 100644
index 0000000000..4bfb7ca7cf
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv210/setup_hsmmc.c
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/s3c_hsmmc.h>
+
+extern ulong get_MPLL_CLK(void);
+
+void set_hsmmc_pre_ratio (struct sdhci_host *host, uint clock)
+{
+ u32 div, clk;
+
+ clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
+
+ /* XXX: we assume that clock is between 40MHz and 50MHz */
+ if (clock <= 400000)
+ div = 0x40;
+ else if (clock <= 20000000)
+ div = 2;
+ else if (clock <= 26000000)
+ div = 1;
+ else
+ div = 0;
+ clk = div << SDHCI_DIVIDER_SHIFT;
+
+ writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
+}
+void setup_hsmmc_clock(void)
+{
+ u32 tmp;
+ u32 clock;
+ u32 i;
+
+ /* MMC0 clock src = SCLKMPLL */
+ tmp = CLK_SRC4_REG & ~(0x0000000f);
+ CLK_SRC4_REG = tmp | 0x00000006;
+
+ /* MMC0 clock div */
+ tmp = CLK_DIV4_REG & ~(0x0000000f);
+ clock = get_MPLL_CLK()/1000000;
+ for(i=0; i<0xf; i++)
+ {
+ if((clock / (i+1)) <= 50) {
+ CLK_DIV4_REG = tmp | i<<0;
+ break;
+ }
+ }
+
+#ifdef USE_MMC1
+ /* MMC1 clock src = SCLKMPLL */
+ tmp = CLK_SRC4_REG & ~(0x000000f0);
+ CLK_SRC4_REG = tmp | 0x00000060;
+
+ /* MMC1 clock div */
+ tmp = CLK_DIV4_REG & ~(0x000000f0);
+ CLK_DIV4_REG = tmp | i<<4;
+#endif
+
+#ifdef USE_MMC2
+ /* MMC2 clock src = SCLKMPLL */
+ tmp = CLK_SRC4_REG & ~(0x00000f00);
+ CLK_SRC4_REG = tmp | 0x00000600;
+
+ /* MMC2 clock div */
+ tmp = CLK_DIV4_REG & ~(0x00000f00);
+ CLK_DIV4_REG = tmp | i<<8;
+#endif
+
+#ifdef USE_MMC3
+ /* MMC3 clock src = SCLKMPLL */
+ tmp = CLK_SRC4_REG & ~(0x00000f00);
+ CLK_SRC4_REG = tmp | 0x00000600;
+
+ /* MMC3 clock div */
+ tmp = CLK_DIV4_REG & ~(0x00000f00);
+ CLK_DIV4_REG = tmp | i<<12;
+#endif
+}
+
+/*
+ * this will set the GPIO for hsmmc ch0
+ * GPG0[0:6] = CLK, CMD, CDn, DAT[0:3]
+ */
+void setup_hsmmc_cfg_gpio(void)
+{
+ ulong reg;
+
+ /* MMC channel 0 */
+ /* 7 pins will be assigned - GPG0[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPG0CON) & 0xf0000000;
+ writel(reg | 0x02222222, GPG0CON);
+ reg = readl(GPG0PUD) & 0xffffc000;
+ writel(reg | 0x00002aaa, GPG0PUD);
+ writel(0x00003fff, GPG0DRV);
+
+ /* MMC channel 0 8 BIT */
+ /* 7 pins will be assigned - GPG1[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPG1CON) & 0xf0000000;
+ writel(reg | 0x03333000, GPG1CON);
+ reg = readl(GPG1PUD) & 0xffffc000;
+ writel(reg | 0x00002a80, GPG1PUD);
+ writel(0x00003fff, GPG1DRV);
+
+#ifdef USE_MMC1
+ /* MMC channel 1 */
+ /* 7 pins will be assigned - GPG1[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPG1CON) & 0xf0000000;
+ writel(reg | 0x02222222, GPG1CON);
+ reg = readl(GPG1PUD) & 0xffffc000;
+ writel(reg | 0x00002aaa, GPG1PUD);
+ writel(0x00003fff, GPG1DRV);
+#endif
+
+#ifdef USE_MMC2
+ /* MMC channel 2 */
+ /* 7 pins will be assigned - GPG2[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPG2CON) & 0xf0000000;
+ writel(reg | 0x02222222, GPG2CON);
+ reg = readl(GPG2PUD) & 0xffffc000;
+ writel(reg | 0x00002aaa, GPG2PUD);
+ writel(0x00003fff, GPG2DRV);
+#endif
+
+#ifdef USE_MMC3
+ /* MMC channel 3 */
+ /* 7 pins will be assigned - GPG0[0:6] = CLK, CMD, CDn, DAT[0:3] */
+ reg = readl(GPG3CON) & 0xf0000000;
+ writel(reg | 0x02222222, GPG3CON);
+ reg = readl(GPG3PUD) & 0xffffc000;
+ writel(reg | 0x00002aaa, GPG3PUD);
+ writel(0x00003fff, GPG3DRV);
+#endif
+}
+
+
+void setup_sdhci0_cfg_card(struct sdhci_host *host)
+{
+ u32 ctrl2;
+ u32 ctrl3 = 0;
+
+ /* don't need to alter anything acording to card-type */
+ writel(S3C_SDHCI_CONTROL4_DRIVE_9mA, host->ioaddr + S3C_SDHCI_CONTROL4);
+
+ ctrl2 = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
+ ctrl3 = readl(host->ioaddr + S3C_SDHCI_CONTROL3);
+
+ ctrl2 |= (S3C_SDHCI_CTRL2_ENSTAASYNCCLR |
+ S3C_SDHCI_CTRL2_ENCMDCNFMSK |
+ S3C_SDHCI_CTRL2_ENFBCLKRX |
+ S3C_SDHCI_CTRL2_ENFBCLKTX |
+ S3C_SDHCI_CTRL2_DFCNT_NONE |
+ S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+ if (0 <= host->clock && host->clock < 20000000) {
+ ctrl3 &= ~(1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+ ctrl3 |= (1 << 31 | 1 << 23 | 0 << 15 | 0 << 7);
+ } else if (20000000 <= host->clock && host->clock < 37000000) {
+ ctrl3 &= ~(1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+ ctrl3 |= (1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+ } else if (37000000 <= host->clock && host->clock <= 52000000) {
+ ctrl3 &= ~(1 << 31 | 1 << 23 | 1 << 15 | 1 << 7);
+ ctrl3 |= (1 << 31 | 1 << 23 | 0 << 15 | 0 << 7);
+ } else {
+ printf("This CLOCK is Not Support: %d\n", host->clock);
+ }
+
+#if defined(CONFIG_EMMC_4_4)
+ ctrl3 = 1<<31 | 1<< 23 | 1<<15 | 1<<7;
+#endif
+
+ writel(ctrl2, host->ioaddr + S3C_SDHCI_CONTROL2);
+ writel(ctrl3, host->ioaddr + S3C_SDHCI_CONTROL3);
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv310/Makefile b/arch/arm/cpu/armv7/s5pv310/Makefile
new file mode 100644
index 0000000000..337e2b62bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/Makefile
@@ -0,0 +1,69 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# (C) Copyright 2011 Samsung Electronics Co. Ltd
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+#SOBJS += reset.o
+COBJS += irom_copy.o
+COBJS += nand.o
+COBJS += nand_cp.o
+ifdef CONFIG_CMD_NAND
+COBJS += nand_write_bl.o
+endif
+COBJS += onenand_cp.o
+COBJS += pmic.o
+ifdef CONFIG_SECURE_BOOT
+COBJS += UBOOT_SB20_S5PC210S.o
+COBJS += security_check.o
+COBJS += ace_sha1.o
+endif
+COBJS += reset.o
+COBJS += gpio.o
+COBJS += movi_partition.o
+COBJS += sys_info.o
+COBJS += clock.o
+COBJS += setup_hsmmc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.c b/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.c
new file mode 100644
index 0000000000..03830e30bf
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.c
@@ -0,0 +1,182 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include "UBOOT_SB20_S5PC210S.h"
+
+#include <asm/arch/ace_sha1.h>
+#define CONFIG_SHA1 (1)
+//#define SW_SHA1 (1)
+
+#define SHA1_BLOCK_LEN 64 /* Input Message Block Length */
+#define SHA1_DIGEST_LEN 20 /* Hash Code Length */
+
+/* SHA1 Context */
+typedef struct
+{
+ unsigned int auChain[SHA1_DIGEST_LEN/4]; /* Chaining Variable */
+ unsigned int auCount[2]; /* the number of input message bit */
+ unsigned char abBuffer[SHA1_BLOCK_LEN]; /* Buffer for unfilled block */
+} SHA1_ALG_INFO;
+
+/* int sscl_memcmp(BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memcmp(BASE_FUNC_PTR,a,b,c) \
+ (((int(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 0))))\
+ ((a),(b),(c)))
+
+/* void sscl_memcpy(BYTE *pbDst, BYTE *pbSrc, DWORD uByteLen); */
+#define macro_sscl_memcpy(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 4))))\
+ ((a),(b),(c)))
+
+//void sscl_memset(BYTE *pbDst, BYTE bValue, DWORD uByteLen); */
+#define macro_sscl_memset(BASE_FUNC_PTR,a,b,c) \
+ (((void(*)(unsigned char *, unsigned char, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 8))))\
+ ((a),(b),(c)))
+
+/* void sscl_memxor(BYTE *pbDst, BYTE *pbSrc1, BYTE *pbSrc2, DWORD uByteLen); */
+#define macro_sscl_memxor(BASE_FUNC_PTR,a,b,c,d) \
+ (((void(*)(unsigned char *, unsigned char *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 12))))\
+ ((a),(b),(c),(d)))
+
+/* unsigned int SEC_SHA1_Init(SHA1_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 16))))\
+ ((a)))
+
+/* unsigned SEC_SHA1_Update(SHA1_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 20))))\
+ ((a),(b),(c)))
+
+/* unsigned SEC_SHA1_Final( SHA1_ALG_INFO *psAlgInfo, BYTE *pbDigest); */
+#define macro_SEC_SHA1_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 24))))\
+ ((a),(b)))
+
+/* RET_VAL SEC_SHA1_HMAC_SetInfo( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbUserKey, DWORD uUKeyLen ); */
+#define macro_SEC_SHA1_HMAC_SetInfo(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 28))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Init(SHA1_HMAC_ALG_INFO *psAlgInfo); */
+#define macro_SEC_SHA1_HMAC_Init(BASE_FUNC_PTR,a) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 32))))\
+ ((a)))
+
+/* RET_VAL SEC_SHA1_HMAC_Update(SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbMessage, DWORD uMsgLen); */
+#define macro_SEC_SHA1_HMAC_Update(BASE_FUNC_PTR,a,b,c) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *, unsigned int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 36))))\
+ ((a),(b),(c)))
+
+/* RET_VAL SEC_SHA1_HMAC_Final( SHA1_HMAC_ALG_INFO *psAlgInfo, BYTE *pbHmacVal); */
+#define macro_SEC_SHA1_HMAC_Final(BASE_FUNC_PTR,a,b) \
+ (((unsigned int(*)(SHA1_HMAC_ALG_INFO *, unsigned char *))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 40))))\
+ ((a),(b)))
+
+/* int Verify_PSS_RSASignature (
+ * IN unsigned char *rawRSAPublicKey,
+ * IN int rawRSAPublicKeyLen,
+ * IN unsigned char *hashCode,
+ * IN int hashCodeLen,
+ * IN unsigned char *signature,
+ * IN int signatureLen);
+ */
+#define macro_Verify_PSS_RSASignature(BASE_FUNC_PTR,a,b,c,d,e,f) \
+ (((int(*)(unsigned char *, int, unsigned char *, int, unsigned char*, int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 44))))\
+ ((a),(b),(c),(d),(e),(f)))
+#define macro_Verify_PSS_RSASignature2(BASE_FUNC_PTR,a,b,c,d,e,f) (((int(*)(unsigned char *, int, unsigned char *, int, unsigned char*, int))\
+ (*((unsigned int *)(BASE_FUNC_PTR + 48))))\
+ ((a),(b),(c),(d),(e),(f)))
+
+
+////////////////////////////////////////////////////////////////////////
+// Verify integrity of BL2(or OS) Image.
+int Check_Signature (
+ SB20_CONTEXT *sbContext,
+ unsigned char *data,
+ int dataLen,
+ unsigned char *signedData,
+ int signedDataLen )
+{
+ unsigned int rv;
+ unsigned int SBoot_BaseFunc_ptr;
+
+ SBoot_BaseFunc_ptr = (unsigned int)sbContext->func_ptr_BaseAddr;
+#if defined (CONFIG_SHA1)
+ unsigned char hashCode[SHA1_DIGEST_LEN];
+ int hashCodeLen = SHA1_DIGEST_LEN;
+ SHA1_ALG_INFO algInfo;
+ SB20_RSAPubKey tempPubKey;
+ SBoot_BaseFunc_ptr = (unsigned int)sbContext->func_ptr_BaseAddr;
+
+#if 0
+ /* 0. if stage2 pubkey is 0x00, do NOT check integrity. */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *)&tempPubKey,
+ 0x00,
+ sizeof(SB20_RSAPubKey));
+
+ rv = macro_sscl_memcmp(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ (unsigned char *)&tempPubKey,
+ sizeof(SB20_RSAPubKey));
+
+ if (rv == 0)
+ return SB_OFF;
+#endif
+ /* 1. Make HashCode */
+ /* 1-1. SHA1 Init */
+ macro_sscl_memset(SBoot_BaseFunc_ptr,
+ (unsigned char *) &algInfo,
+ 0x00,
+ sizeof(SHA1_ALG_INFO));
+
+#if defined(SW_SHA1)
+ macro_SEC_SHA1_Init(SBoot_BaseFunc_ptr, &algInfo );
+
+ /* 1-3. SHA1 Update. */
+ macro_SEC_SHA1_Update(SBoot_BaseFunc_ptr, &algInfo, data, dataLen );
+
+ /* 1-4. SHA1 Final. */
+ macro_SEC_SHA1_Final(SBoot_BaseFunc_ptr, &algInfo, hashCode );
+#else
+ ace_hash_sha1_digest(hashCode, data, dataLen);
+#endif
+ rv = macro_Verify_PSS_RSASignature(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ sizeof(SB20_RSAPubKey),
+ hashCode, hashCodeLen,
+ signedData, signedDataLen );
+#else
+ rv = macro_Verify_PSS_RSASignature2(SBoot_BaseFunc_ptr,
+ (unsigned char *)&(sbContext->stage2PubKey),
+ sizeof(SB20_RSAPubKey),
+ data, dataLen,
+ signedData, signedDataLen );
+#endif
+ if ( rv != SB_OK )
+ return rv;
+
+ return SB_OK;
+}
diff --git a/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.h b/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.h
new file mode 100644
index 0000000000..f96b9add96
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/UBOOT_SB20_S5PC210S.h
@@ -0,0 +1,113 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _UBOOT_SB20_S5PC210S_H
+#define _UBOOT_SB20_S5PC210S_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+////////////////////////////////////////////////////////////////////////
+// SecureBoot return value define
+#define SB_OK 0x00000000
+#define SB_OFF 0x80000000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_VALIDATE_PUBLIC_KEY_INFO 0xFFF10000
+#define SB_ERROR_VERIFY_PSS_RSA_SIGNATURE 0xFFF20000
+#define SB_ERROR_CHECK_INTEGRITY_CODE 0xFFF30000
+
+//------------------------------------------------------------------------
+// added for Secure Boot 2.0
+#define SB_ERROR_GENERATE_PSS_RSA_SIGNATURE 0xFFF40000
+#define SB_ERROR_GENERATE_PUBLIC_KEY_INFO 0xFFF50000
+#define SB_ERROR_GENERATE_SB_CONTEXT 0xFFF60000
+#define SB_ERROR_ENCRYPTION 0xFFF70000
+
+#define SB_ERROR_AES_PARM 0x0000A000
+#define SB_ERROR_AES_SET_ALGO 0x0000B000
+#define SB_ERROR_AES_ENCRYPT 0x0000C000
+#define SB_ERROR_AES_DECRYPT 0x0000D000
+
+//------------------------------------------------------------------------
+#define SB_ERROR_HMAC_SHA1_SET_INFO 0x00000010
+#define SB_ERROR_HMAC_SHA1_INIT 0x00000020
+#define SB_ERROR_HMAC_SHA1_UPDATE 0x00000030
+#define SB_ERROR_HMAC_SHA1_FINAL 0x00000040
+#define SB_ERROR_MEM_CMP 0x00000050
+#define SB_ERROR_SHA1_INIT 0x00000060
+#define SB_ERROR_SHA1_UPDATE 0x00000070
+#define SB_ERROR_SHA1_FINAL 0x00000080
+#define SB_ERROR_VERIFY_RSA_PSS 0x00000090
+
+////////////////////////////////////////////////////////////////////////
+//-------------------------------------------
+#define SB20_MAX_EFUSE_DATA_LEN 20
+
+#define SB20_MAX_RSA_KEY (2048/8)
+#define SB20_MAX_SIGN_LEN SB20_MAX_RSA_KEY
+
+#define SB20_HMAC_SHA1_LEN 20
+
+//-------------------------------------------
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_e_Len;
+ unsigned char rsa_e[4];
+} SB20_RSAPubKey;
+
+typedef struct
+{
+ int rsa_n_Len;
+ unsigned char rsa_n[SB20_MAX_RSA_KEY];
+ int rsa_d_Len;
+ unsigned char rsa_d[SB20_MAX_RSA_KEY];
+} SB20_RSAPrivKey;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey rsaPubKey;
+ unsigned char signedData[SB20_HMAC_SHA1_LEN];
+} SB20_PubKeyInfo;
+
+//-------------------------------------------
+typedef struct
+{
+ SB20_RSAPubKey stage2PubKey;
+ int code_SignedDataLen;
+ unsigned char code_SignedData[SB20_MAX_SIGN_LEN];
+ SB20_PubKeyInfo pubKeyInfo;
+ unsigned char func_ptr_BaseAddr[64];
+ unsigned char reservedData[144];
+} SB20_CONTEXT;
+
+
+////////////////////////////////////////////////////////////////////////
+// Verify integrity of BL2(or OS) Image.
+int Check_Signature (
+ SB20_CONTEXT *sb20_Context,
+ unsigned char *codeImage,
+ int codeImageLen,
+ unsigned char *signedData,
+ int signedDataLen );
+
+///////////////////////////////////////////////////////////////////////////////////
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _UBOOT_SB20_S5PC210S_H */
diff --git a/arch/arm/cpu/armv7/s5pv310/ace_sha1.c b/arch/arm/cpu/armv7/s5pv310/ace_sha1.c
new file mode 100644
index 0000000000..f3bc5ee298
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/ace_sha1.c
@@ -0,0 +1,129 @@
+/*
+ * Advanced Crypto Engine - SHA1 Firmware
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/ace_sfr.h>
+
+
+#if (defined(CONFIG_S5PV210) || defined(CONFIG_S5PC110) || defined(CONFIG_S5PV310) || defined(CONFIG_S5PC210))
+
+/*****************************************************************
+ Definitions
+*****************************************************************/
+#define ACE_read_sfr(_sfr_) \
+ (*(volatile unsigned int*)(ACE_SFR_BASE + _sfr_))
+#define ACE_write_sfr(_sfr_, _val_) \
+ do {*(volatile unsigned int*)(ACE_SFR_BASE + _sfr_) \
+ = (unsigned int)(_val_);} while(0)
+
+/* SHA1 value for the message of zero length */
+const unsigned char sha1_digest_emptymsg[20] = {
+ 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
+ 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
+ 0xAF, 0xD8, 0x07, 0x09};
+
+
+/*****************************************************************
+ Functions
+*****************************************************************/
+/**
+ * @brief This function computes hash value of input (pBuf[0]..pBuf[buflen-1]).
+ *
+ * @param pOut A pointer to the output buffer. When operation is completed
+ * 20 bytes are copied to pOut[0]...pOut[19]. Thus, a user
+ * should allocate at least 20 bytes at pOut in advance.
+ * @param pBuf A pointer to the input buffer
+ * @param bufLen Byte length of input buffer
+ *
+ * @return 0 Success
+ *
+ * @remark This function assumes that pBuf is a physical address of input buffer.
+ *
+ * @version V1.00
+ * @b Revision History
+ * - V01.00 2009.11.13/djpark Initial Version
+ * - V01.10 2010.10.19/djpark Modification to support C210/V310
+ */
+int ace_hash_sha1_digest (
+ unsigned char* pOut,
+ unsigned char* pBuf,
+ unsigned int bufLen
+)
+{
+ unsigned int reg;
+ unsigned int* pDigest;
+
+ if (bufLen == 0) {
+ /* ACE H/W cannot compute hash value for empty string */
+ memcpy(pOut, sha1_digest_emptymsg, 20);
+ return 0;
+ }
+
+ /* Flush HRDMA */
+ ACE_write_sfr(ACE_FC_HRDMAC, ACE_FC_HRDMACFLUSH_ON);
+ ACE_write_sfr(ACE_FC_HRDMAC, ACE_FC_HRDMACFLUSH_OFF);
+
+ /* Set byte swap of data in */
+ ACE_write_sfr(ACE_HASH_BYTESWAP,
+ ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON);
+
+ /* Select Hash input mux as external source */
+ reg = ACE_read_sfr(ACE_FC_FIFOCTRL);
+ reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
+ ACE_write_sfr(ACE_FC_FIFOCTRL, reg);
+
+ /* Set Hash as SHA1 and start Hash engine */
+ reg = ACE_HASH_ENGSEL_SHA1HASH | ACE_HASH_STARTBIT_ON;
+ ACE_write_sfr(ACE_HASH_CONTROL, reg);
+
+ /* Enable FIFO mode */
+ ACE_write_sfr(ACE_HASH_FIFO_MODE, ACE_HASH_FIFO_ON);
+
+ /* Set message length */
+ ACE_write_sfr(ACE_HASH_MSGSIZE_LOW, bufLen);
+ ACE_write_sfr(ACE_HASH_MSGSIZE_HIGH, 0);
+
+ /* Set HRDMA */
+ ACE_write_sfr(ACE_FC_HRDMAS, (unsigned int)virt_to_phys(pBuf));
+ ACE_write_sfr(ACE_FC_HRDMAL, bufLen);
+
+ while ((ACE_read_sfr(ACE_HASH_STATUS) & ACE_HASH_MSGDONE_MASK)
+ == ACE_HASH_MSGDONE_OFF);
+
+ /* Clear MSG_DONE bit */
+ ACE_write_sfr(ACE_HASH_STATUS, ACE_HASH_MSGDONE_ON);
+
+ /* Read hash result */
+ pDigest = (unsigned int*)pOut;
+ pDigest[0] = ACE_read_sfr(ACE_HASH_RESULT1);
+ pDigest[1] = ACE_read_sfr(ACE_HASH_RESULT2);
+ pDigest[2] = ACE_read_sfr(ACE_HASH_RESULT3);
+ pDigest[3] = ACE_read_sfr(ACE_HASH_RESULT4);
+ pDigest[4] = ACE_read_sfr(ACE_HASH_RESULT5);
+
+ /* Clear HRDMA pending bit */
+ ACE_write_sfr(ACE_FC_INTPEND, ACE_FC_HRDMA);
+
+ return 0;
+}
+
+#endif
+
diff --git a/arch/arm/cpu/armv7/s5pv310/clock.c b/arch/arm/cpu/armv7/s5pv310/clock.c
new file mode 100644
index 0000000000..0f341b8a68
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/clock.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2011 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+
+unsigned long (*get_uart_clk)(int dev_index);
+unsigned long (*get_pwm_clk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+void s5p_clock_init(void)
+{
+}
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define VPLL 3
+
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static ulong get_PLLCLK(int pllreg)
+{
+ ulong r, m, p, s;
+
+ if (pllreg == APLL) {
+ r = APLL_CON0_REG;
+ m = (r>>16) & 0x3ff;
+ } else if (pllreg == MPLL) {
+ r = MPLL_CON0_REG;
+ m = (r>>16) & 0x3ff;
+ } else
+ hang();
+
+ p = (r>>8) & 0x3f;
+ s = r & 0x7;
+
+ if ((pllreg == APLL) || (pllreg == MPLL))
+ s= s-1;
+
+ return (m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s))));
+}
+
+ulong get_APLL_CLK(void)
+{
+ return (get_PLLCLK(APLL));
+}
+
+ulong get_MPLL_CLK(void)
+{
+ return (get_PLLCLK(MPLL));
+}
+
diff --git a/arch/arm/cpu/armv7/s5pv310/gpio.c b/arch/arm/cpu/armv7/s5pv310/gpio.c
new file mode 100644
index 0000000000..553ec039b8
--- /dev/null
+++ b/arch/arm/cpu/armv7/s5pv310/gpio.c
@@ -0,0 +1,5377 @@
+/*
+ * (C) Copyright 2009 Samsung Electronics Co. Ltd
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * File Name : gpio.c
+ *
+ * File Description : This file declares prototypes of GPIO API funcions.
+ *
+ * Author : chansik.Jeon
+ * Dept. : AP Development Team
+ * Created Date : 2010/04/16
+ * Version : 0.1
+ *
+ * History
+ * - Created(chigwan.Oh 2010/04/16)
+ *
+ */
+
+
+#include <asm/arch/gpio.h>
+
+#define GPIO_REG ( ( volatile oGPIO_REGS * ) (GPIO_pBase) )
+
+//=============================================
+// Left Bottom Block = ( GPA0 Group ~ GPF3 Group, ETC0, ETC1 )
+// Right Top Block = ( GPJ0 Group ~ MP0 Group, ETC6, ECT8 )
+//=============================================
+typedef struct tag_GPIO_REGS
+{
+
+ // Start Right Top Register===================================
+ int rGPIOJ0CON; //0x11000000
+ int rGPIOJ0DAT;
+ int rGPIOJ0PUD;
+ int rGPIOJ0DRV_SR;
+ int rGPIOJ0CONPDN;
+ int rGPIOJ0PUDPDN;
+ int reservedJ0[2]; // 0x11000018 ~ 0x1100001C
+
+ int rGPIOJ1CON; //0x11000020
+ int rGPIOJ1DAT;
+ int rGPIOJ1PUD;
+ int rGPIOJ1DRV_SR;
+ int rGPIOJ1CONPDN;
+ int rGPIOJ1PUDPDN;
+ int reservedJ1[2];
+
+ int rGPIOK0CON; //0x11000040
+ int rGPIOK0DAT;
+ int rGPIOK0PUD;
+ int rGPIOK0DRV_SR;
+ int rGPIOK0CONPDN;
+ int rGPIOK0PUDPDN;
+ int reservedK0[2];
+
+ int rGPIOK1CON; //0x11000060
+ int rGPIOK1DAT;
+ int rGPIOK1PUD;
+ int rGPIOK1DRV_SR;
+ int rGPIOK1CONPDN;
+ int rGPIOK1PUDPDN;
+ int reservedK1[2];
+
+ int rGPIOK2CON; //0x11000080
+ int rGPIOK2DAT;
+ int rGPIOK2PUD;
+ int rGPIOK2DRV_SR;
+ int rGPIOK2CONPDN;
+ int rGPIOK2PUDPDN;
+ int reservedK2[2];
+
+ int rGPIOK3CON; //0x110000A0
+ int rGPIOK3DAT;
+ int rGPIOK3PUD;
+ int rGPIOK3DRV_SR;
+ int rGPIOK3CONPDN;
+ int rGPIOK3PUDPDN;
+ int reservedK3[2];
+
+ int rGPIOL0CON; //0x110000C0
+ int rGPIOL0DAT;
+ int rGPIOL0PUD;
+ int rGPIOL0DRV_SR;
+ int rGPIOL0CONPDN;
+ int rGPIOL0PUDPDN;
+ int reservedL0[2];
+
+ int rGPIOL1CON; //0x110000E0
+ int rGPIOL1DAT;
+ int rGPIOL1PUD;
+ int rGPIOL1DRV_SR;
+ int rGPIOL1CONPDN;
+ int rGPIOL1PUDPDN;
+ int reservedL1[2];
+
+ int rGPIOL2CON; //0x11000100
+ int rGPIOL2DAT;
+ int rGPIOL2PUD;
+ int rGPIOL2DRV_SR;
+ int rGPIOL2CONPDN;
+ int rGPIOL2PUDPDN;
+ int reservedL2[2];
+
+ int rGPIOMP0CON; //0x11000120
+ int rGPIOMP0DAT;
+ int rGPIOMP0PUD;
+ int rGPIOMP0DRV_SR;
+ int rGPIOMP0CONPDN;
+ int rGPIOMP0PUDPDN;
+ int reservedMP0[2];
+
+ int rGPIOMP1CON; //0x11000140
+ int rGPIOMP1DAT;
+ int rGPIOMP1PUD;
+ int rGPIOMP1DRV_SR;
+ int rGPIOMP1CONPDN;
+ int rGPIOMP1PUDPDN;
+ int reservedMP1[2];
+
+ int rGPIOMP2CON; //0x11000160
+ int rGPIOMP2DAT;
+ int rGPIOMP2PUD;
+ int rGPIOMP2DRV_SR;
+ int rGPIOMP2CONPDN;
+ int rGPIOMP2PUDPDN;
+ int reservedMP2[2];
+
+ int rGPIOMP3CON; //0x11000180
+ int rGPIOMP3DAT;
+ int rGPIOMP3PUD;
+ int rGPIOMP3DRVSR;
+ int rGPIOMP3CONPDN;
+ int rGPIOMP3PUDPDN;
+ int reservedMP3[2];
+
+ int rGPIOMP4CON; //0x110001A0
+ int rGPIOMP4DAT;
+ int rGPIOMP4PUD;
+ int rGPIOMP4DRV_SR;
+ int rGPIOMP4CONPDN;
+ int rGPIOMP4PUDPDN;
+ int reservedMP4[2];
+
+ int rGPIOMP5CON; //0x110001C0
+ int rGPIOMP5DAT;
+ int rGPIOMP5PUD;
+ int rGPIOMP5DRV_SR;
+ int rGPIOMP5CONPDN;
+ int rGPIOMP5PUDPDN;
+ int reservedMP5[2];
+
+ int rGPIOMP6CON; //0x110001E0
+ int rGPIOMP6DAT;
+ int rGPIOMP6PUD;
+ int rGPIOMP6DRV_SR;
+ int rGPIOMP6CONPDN;
+ int rGPIOMP6PUDPDN;
+ int reservedMP6[2];
+
+
+ int reservedETC6_1[2];
+ int rGPIOETC6PUD; //0x11000208
+ int rGPIOETC6DRV_SR;
+ int reservedETC6_2[4];
+
+ int reservedETC8_1[2];
+ int rGPIOETC8PUD; //0x11000228
+ int rGPIOETC8DRV_SR;
+ int reservedETC8_2[4];
+
+ int reserved1[304]; // 0x1100_0240 ~ 0x1100_06FC
+
+ int rEINT21CON; // 0x1100_0700
+ int rEINT22CON;
+ int rEINT23CON;
+ int rEINT24CON;
+ int rEINT25CON;
+ int rEINT26CON;
+ int rEINT27CON;
+ int rEINT28CON;
+ int rEINT29CON;
+
+ int reservedEINTCON_1[55];
+
+ int rEINT21FLTCON0; //0x1100_0800
+ int rEINT21FLTCON1;
+ int rEINT22FLTCON0;
+ int rEINT22FLTCON1;
+ int rEINT23FLTCON0;
+ int rEINT23FLTCON1;
+ int rEINT24FLTCON0;
+ int rEINT24FLTCON1;
+ int rEINT25FLTCON0;
+ int rEINT25FLTCON1;
+ int rEINT26FLTCON0;
+ int rEINT26FLTCON1;
+ int rEINT27FLTCON0;
+ int rEINT27FLTCON1;
+ int rEINT28FLTCON0;
+ int rEINT28FLTCON1;
+ int rEINT29FLTCON0;
+ int rEINT29FLTCON1;
+
+ int reserveEINTFLTCON[46];
+
+ int rEINT21MASK; //0x1100_0900
+ int rEINT22MASK;
+ int rEINT23MASK;
+ int rEINT24MASK;
+ int rEINT25MASK;
+ int rEINT26MASK;
+ int rEINT27MASK;
+ int rEINT28MASK;
+ int rEINT29MASK;
+
+ int reservedEINTMASK_1[55];
+
+ int rEINT21PEND; //0x1100_0A00
+ int rEINT22PEND;
+ int rEINT23PEND;
+ int rEINT24PEND;
+ int rEINT25PEND;
+ int rEINT26PEND;
+ int rEINT27PEND;
+ int rEINT28PEND;
+ int rEINT29PEND;
+ int reservedEINTPEND[55];
+
+ int rEINTGRPPRIXB; //0x1100_0B00
+ int rEINTPRIORITYXB;
+ int rEINTSERVICEXB;
+ int rEINTSERVICEPENDXB;
+ int rEINTGRPFIXPRIXB;
+
+ int rEINT21FIXPRI;
+ int rEINT22FIXPRI;
+ int rEINT23FIXPRI;
+ int rEINT24FIXPRI;
+ int rEINT25FIXPRI;
+ int rEINT26FIXPRI;
+ int rEINT27FIXPRI;
+ int rEINT28FIXPRI;
+ int rEINT29FIXPRI;
+
+ int reservedEINTFIXPRI[50];
+
+ int rGPIOX0CON; //0x1100_0C00
+ int rGPIOX0DAT;
+ int rGPIOX0PUD;
+ int rGPIOX0DRV_SR;
+ int reservedGPIOX0[4];
+
+ int rGPIOX1CON; //0x1100_0C20
+ int rGPIOX1DAT;
+ int rGPIOX1PUD;
+ int rGPIOX1DRV_SR;
+ int reservedGPIOX1[4];
+
+ int rGPIOX2CON; //0x1100_0C40
+ int rGPIOX2DAT;
+ int rGPIOX2PUD;
+ int rGPIOX2DRV_SR;
+ int reservedGPIOX2[4];
+
+ int rGPIOX3CON; //0x1100_0C60
+ int rGPIOX3DAT;
+ int rGPIOX3PUD;
+ int rGPIOX3DRV_SR;
+ int reservedGPIOX3_1[4];
+
+ int reservedGPIOX3_2[96];
+
+ int rEINT40CON; //0x1100_0E00
+ int rEINT41CON;
+ int rEINT42CON;
+ int rEINT43CON;
+
+ int reservedEINTCON_2[28];
+
+ int rEINT40FLTCON0; //0x1100_0E80
+ int rEINT40FLTCON1;
+ int rEINT41FLTCON0;
+ int rEINT41FLTCON1;
+ int rEINT42FLTCON0;
+ int rEINT42FLTCON1;
+ int rEINT43FLTCON0;
+ int rEINT43FLTCON1;
+
+ int reservedEINTFLTCON[24];
+
+ int rEINT40MASK; //0x1100_0F00
+ int rEINT41MASK;
+ int rEINT42MASK;
+ int rEINT43MASK;
+
+ int reservedEINTMASK_2[12];
+
+ int rEINT40PEND; //0x1100_0F40
+ int rEINT41PEND;
+ int rEINT42PEND;
+ int rEINT43PEND;
+
+ int reservedRT[1047596]; // 0x1100_F50 ~ 0x113F_FFFC
+
+
+ // Start Left Bottom Register===========================================
+ int rGPIOA0CON; //0x11400000
+ int rGPIOA0DAT;
+ int rGPIOA0PUD;
+ int rGPIOA0DRV_SR;
+ int rGPIOA0CONPDN;
+ int rGPIOA0PUDPDN;
+ int reservedA0[2]; // 0x11400018 ~ 0x1140001C
+
+ int rGPIOA1CON; //0x11400020
+ int rGPIOA1DAT;
+ int rGPIOA1PUD;
+ int rGPIOA1DRV_SR;
+ int rGPIOA1CONPDN;
+ int rGPIOA1PUDPDN;
+ int reservedA1[2];
+
+ int rGPIOBCON; //0x11400040
+ int rGPIOBDAT;
+ int rGPIOBPUD;
+ int rGPIOBDRV_SR;
+ int rGPIOBCONPDN;
+ int rGPIOBPUDPDN;
+ int reservedB[2];
+
+ int rGPIOC0CON; //0x11400060
+ int rGPIOC0DAT;
+ int rGPIOC0PUD;
+ int rGPIOC0DRV_SR;
+ int rGPIOC0CONPDN;
+ int rGPIOC0PUDPDN;
+ int reservedC0[2];
+
+ int rGPIOC1CON; //0x11400080
+ int rGPIOC1DAT;
+ int rGPIOC1PUD;
+ int rGPIOC1DRV_SR;
+ int rGPIOC1CONPDN;
+ int rGPIOC1PUDPDN;
+ int reservedC1[2];
+
+ int rGPIOD0CON; //0x114000A0
+ int rGPIOD0DAT;
+ int rGPIOD0PUD;
+ int rGPIOD0DRV_SR;
+ int rGPIOD0CONPDN;
+ int rGPIOD0PUDPDN;
+ int reservedD0[2];
+
+ int rGPIOD1CON; //0x114000C0
+ int rGPIOD1DAT;
+ int rGPIOD1PUD;
+ int rGPIOD1DRV_SR;
+ int rGPIOD1CONPDN;
+ int rGPIOD1PUDPDN;
+ int reservedD1[2];
+
+ int rGPIOE0CON; //0x114000E0
+ int rGPIOE0DAT;
+ int rGPIOE0PUD;
+ int rGPIOE0DRV_SR;
+ int rGPIOE0CONPDN;
+ int rGPIOE0PUDPDN;
+ int reservedE0[2];
+
+ int rGPIOE1CON; //0x11400100
+ int rGPIOE1DAT;
+ int rGPIOE1PUD;
+ int rGPIOE1DRV_SR;
+ int rGPIOE1CONPDN;
+ int rGPIOE1PUDPDN;
+ int reservedE1[2];
+
+ int rGPIOE2CON; //0x11400120
+ int rGPIOE2DAT;
+ int rGPIOE2PUD;
+ int rGPIOE2DRV_SR;
+ int rGPIOE2CONPDN;
+ int rGPIOE2PUDPDN;
+ int reservedE2[2];
+
+ int rGPIOE3CON; //0x11400140
+ int rGPIOE3DAT;
+ int rGPIOE3PUD;
+ int rGPIOE3DRV_SR;
+ int rGPIOE3CONPDN;
+ int rGPIOE3PUDPDN;
+ int reservedE3[2];
+
+ int rGPIOE4CON; //0x11400160
+ int rGPIOE4DAT;
+ int rGPIOE4PUD;
+ int rGPIOE4DRV_SR;
+ int rGPIOE4CONPDN;
+ int rGPIOE4PUDPDN;
+ int reservedE4[2];
+
+ int rGPIOF0CON; //0x11400180
+ int rGPIOF0DAT;
+ int rGPIOF0PUD;
+ int rGPIOF0DRV_SR;
+ int rGPIOF0CONPDN;
+ int rGPIOF0PUDPDN;
+ int reservedF0[2];
+
+ int rGPIOF1CON; //0x114001A0
+ int rGPIOF1DAT;
+ int rGPIOF1PUD;
+ int rGPIOF1DRV_SR;
+ int rGPIOF1CONPDN;
+ int rGPIOF1PUDPDN;
+ int reservedF1[2];
+
+ int rGPIOF2CON; //0x114001C0
+ int rGPIOF2DAT;
+ int rGPIOF2PUD;
+ int rGPIOF2DRV_SR;
+ int rGPIOF2CONPDN;
+ int rGPIOF2PUDPDN;
+ int reservedF2[2];
+
+ int rGPIOF3CON; //0x114001E0
+ int rGPIOF3DAT;
+ int rGPIOF3PUD;
+ int rGPIOF3DRV_SR;
+ int rGPIOF3CONPDN;
+ int rGPIOF3PUDPDN;
+ int reservedF3[2];
+
+ int reservedETC0_1[2];
+ int rGPIOETC0PUD; //0x11400208
+ int rGPIOETC0DRV_SR;
+ int reservedETC0_2[4];
+
+ int reservedETC1_1[2];
+ int rGPIOETC1PUD; //0x11400228
+ int rGPIOETC1DRV_SR;
+ int reservedETC1_2[4];
+
+ int reservedETC[304]; //0x11400240 ~ 0x114006FC
+
+ int rEINT1CON; //0x11400700
+ int rEINT2CON;
+ int rEINT3CON;
+ int rEINT4CON;
+ int rEINT5CON;
+ int rEINT6CON;
+ int rEINT7CON;
+ int rEINT8CON;
+ int rEINT9CON;
+ int rEINT10CON;
+ int rEINT11CON;
+ int rEINT12CON;
+ int rEINT13CON;
+ int rEINT14CON;
+ int rEINT15CON;
+ int rEINT16CON;
+
+
+ int reservedEINTCON_3[48];//0x11400740 ~ 0x114007FC
+
+ int rEINT1FLTCON0; //0x11400800
+ int rEINT1FLTCON1;
+ int rEINT2FLTCON0;
+ int rEINT2FLTCON1;
+ int rEINT3FLTCON0;
+ int rEINT3FLTCON1;
+ int rEINT4FLTCON0;
+ int rEINT4FLTCON1;
+ int rEINT5FLTCON0;
+ int rEINT5FLTCON1;
+ int rEINT6FLTCON0;
+ int rEINT6FLTCON1;
+ int rEINT7FLTCON0;
+ int rEINT7FLTCON1;
+ int rEINT8FLTCON0;
+ int rEINT8FLTCON1;
+ int rEINT9FLTCON0;
+ int rEINT9FLTCON1;
+ int rEINT10FLTCON0;
+ int rEINT10FLTCON1;
+ int rEINT11FLTCON0;
+ int rEINT11FLTCON1;
+ int rEINT12FLTCON0;
+ int rEINT12FLTCON1;
+ int rEINT13FLTCON0;
+ int rEINT13FLTCON1;
+ int rEINT14FLTCON0;
+ int rEINT14FLTCON1;
+ int rEINT15FLTCON0;
+ int rEINT15FLTCON1;
+ int rEINT16FLTCON0;
+ int rEINT16FLTCON1;
+
+
+ int reservedFLTCON[32]; //0x11400880 ~ 0x114008FC
+
+ int rEINT1MASK; //0x11400900
+ int rEINT2MASK;
+ int rEINT3MASK;
+ int rEINT4MASK;
+ int rEINT5MASK;
+ int rEINT6MASK;
+ int rEINT7MASK;
+ int rEINT8MASK;
+ int rEINT9MASK;
+ int rEINT10MASK;
+ int rEINT11MASK;
+ int rEINT12MASK;
+ int rEINT13MASK;
+ int rEINT14MASK;
+ int rEINT15MASK;
+ int rEINT16MASK;
+
+ int reservedMASK[48]; //0x11400940 ~ 0x114009FC
+
+ int rEINT1PEND; //0x11400A00
+ int rEINT2PEND;
+ int rEINT3PEND;
+ int rEINT4PEND;
+ int rEINT5PEND;
+ int rEINT6PEND;
+ int rEINT7PEND;
+ int rEINT8PEND;
+ int rEINT9PEND;
+ int rEINT10PEND;
+ int rEINT11PEND;
+ int rEINT12PEND;
+ int rEINT13PEND;
+ int rEINT14PEND;
+ int rEINT15PEND;
+ int rEINT16PEND;
+
+ int reservedPEND[48]; //0x11400A40 ~ 0x11400AFC
+
+ int rEINTGRPPRIXA; // 0x11000B00
+ int rEINTPRIORITYXA;
+ int rEINTSERVICEXA;
+ int rEINTSERVICEPENDXA;
+ int rEINTGRPFIXPRIXA;
+
+ int rEINT1FIXPRI; // 0x11000B14
+ int rEINT2FIXPRI;
+ int rEINT3FIXPRI;
+ int rEINT4FIXPRI;
+ int rEINT5FIXPRI;
+ int rEINT6FIXPRI;
+ int rEINT7FIXPRI;
+ int rEINT8FIXPRI;
+ int rEINT9FIXPRI;
+ int rEINT10FIXPRI;
+ int rEINT11FIXPRI;
+ int rEINT12FIXPRI;
+ int rEINT13FIXPRI;
+ int rEINT14FIXPRI;
+ int rEINT15FIXPRI;
+ int rEINT16FIXPRI;
+
+
+ int reservedFIXPRI[267];//0x11400B54 ~ 0x11400F7C
+
+
+}
+oGPIO_REGS;
+
+
+static volatile void * GPIO_pBase;
+
+volatile int g_IntCnt;
+
+
+//////////
+// Function Name : GPIO_Init
+// Function Desctiption : This function initializes gpio sfr base address
+// Input : NONE
+// Output : NONE
+// Version :
+//
+// Version : v0.1
+void GPIO_Init(void)
+{
+ GPIO_pBase = (void *)GPIO_BASE;
+}
+
+
+//////////
+// Function Name : GPIO_SetFunctionEach
+// Function Desctiption : This function set each GPIO function
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uFunction : Select the function
+// Output : NONE
+//
+// Version : v0.0
+
+void GPIO_SetFunctionEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uFunction)
+{
+ volatile int *pGPIOx_Reg0;
+ volatile int *pGPIO_Base_Addr;
+ int uMuxBit, uOffset;
+ int uConValue;
+
+ uMuxBit = 4; // 4bit
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_Reg0 = pGPIO_Base_Addr + uOffset/4;
+ uConValue = *pGPIOx_Reg0;
+ uConValue = (uConValue & ~(0xF<<(uMuxBit*eBitPos))) | (uFunction<<(uMuxBit*eBitPos));
+ *pGPIOx_Reg0 = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetFunctionAll
+// Function Desctiption : This function set all GPIO function selection
+// Input : Id : GPIO port
+// uValue0 : Write value(control register 0)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetFunctionAll(GPIO_eId Id, int uValue0)
+{
+ volatile int *pGPIOx_Reg0;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_Reg0 = pGPIO_Base_Addr + uOffset/4;
+ *pGPIOx_Reg0 = uValue0;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDataEach
+// Function Desctiption : This function set each GPIO data bit
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDataEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset, uConRegNum;
+ int uDataValue;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4) +uConRegNum;
+ uDataValue = *pGPIOx_DataReg;
+ uDataValue = (uDataValue & ~(0x1<<eBitPos)) | (uValue<<eBitPos);
+ *pGPIOx_DataReg = uDataValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDataAll
+// Function Desctiption : This function set all GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDataAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset, uConRegNum;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4) +uConRegNum;
+ *pGPIOx_DataReg = uValue;
+}
+
+//////////
+// Function Name : GPIO_GetDataEach
+// Function Desctiption : This function get each GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : Data register value
+//
+// Version : v0.0
+int GPIO_GetDataEach(GPIO_eId Id, GPIO_eBitPos eBitPos)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+ uOffset = Id & 0xFFFFFF;
+ uConRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset / 4) + uConRegNum;
+ return ((*pGPIOx_DataReg) & (1 << eBitPos)) ? 1 : 0;
+}
+
+//////////
+// Function Name : GPIO_GetDataAll
+// Function Desctiption : This function get all GPIO data bit
+// Input : Id : GPIO port
+// uValue : value
+// Output : Data register value
+//
+// Version : v0.0
+int GPIO_GetDataAll(GPIO_eId Id)
+{
+ volatile int *pGPIOx_DataReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uOffset;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DataReg = pGPIO_Base_Addr + (uOffset/4)+ uConRegNum;
+ return (*pGPIOx_DataReg);
+}
+
+
+//////////
+// Function Name : GPIO_SetPullUpDownEach
+// Function Desctiption : This function set each GPIO Pull-up/Down bits
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetPullUpDownEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uOffset;
+ int uPullValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum;
+ uPullValue = *pGPIOx_PullUDReg;
+ uPullValue = (uPullValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pGPIOx_PullUDReg = uPullValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetPullUpDownAll
+// Function Desctiption : This function set all GPIO Pull-up/Down bits
+// Input : Id : GPIO port
+// uValue : value(32bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetPullUpDownAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum;
+ *pGPIOx_PullUDReg = uValue;
+}
+
+
+//////////
+// Function Name : ETC_SetPullUpDownEach
+// Function Desctiption : This function set each ETC Pull-up/Down bits
+// Input : Id : ETC port
+// eBitPos : ETC bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void ETC_SetPullUpDownEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pETCx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset;
+ int uPullValue;
+
+
+ uOffset = Id&0xFFFFFF;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pETCx_PullUDReg = pGPIO_Base_Addr + (uOffset/4) ;
+ uPullValue = *pETCx_PullUDReg;
+ uPullValue = (uPullValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pETCx_PullUDReg = uPullValue;
+}
+
+
+//////////
+// Function Name : ETC_SetPullUpDownAll
+// Function Desctiption : This function set all ETC Pull-up/Down bits
+// Input : Id : ETC port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void ETC_SetPullUpDownAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pETCx_PullUDReg;
+ volatile int *pGPIO_Base_Addr;
+ int uOffset;
+
+ uOffset = Id&0xFFFFFF;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pETCx_PullUDReg = pGPIO_Base_Addr + (uOffset/4);
+ *pETCx_PullUDReg = uValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetDSEach
+// Function Desctiption : This function set each GPIO Driving Strength bits
+// Input : Id : GPIO port
+// eBitPos : GPIO bit
+// uValue : value(2bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDSEach(GPIO_eId Id, GPIO_eBitPos eBitPos, int uValue)
+{
+ volatile int *pGPIOx_DSReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uOffset;
+ int uDSValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DSReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum+uPullUDRegNum;
+ uDSValue = *pGPIOx_DSReg;
+ uDSValue = (uDSValue & ~(0x3<<(0x02*eBitPos))) | (uValue<<(0x02*eBitPos));
+ *pGPIOx_DSReg = uDSValue;
+}
+
+
+//////////
+// Function Name : GPIO_SetDSAll
+// Function Desctiption : This function set All GPIO Driving Strength bits
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetDSAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_DSReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uOffset;
+ int uDSValue;
+
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_DSReg = pGPIO_Base_Addr + (uOffset/4) + uConRegNum+uDataRegNum+uPullUDRegNum;
+ uDSValue = *pGPIOx_DSReg;
+ uDSValue = (uDSValue & ~(0xffff)) | uValue;
+ *pGPIOx_DSReg = uDSValue;
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetConRegPDNAll
+// Function Desctiption : This function set all GPIO function when system enter to Power Down mode
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetConRegPDNAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_ConPDNReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uConDSRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+ uConDSRegNum =1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_ConPDNReg = pGPIO_Base_Addr + (uOffset/4) + (uConRegNum + uDataRegNum + uPullUDRegNum+uConDSRegNum);
+ *pGPIOx_ConPDNReg = uValue;
+}
+
+
+//////////
+// Function Name : GPIO_SetPullUDPDNAll
+// Function Desctiption : This function set all GPIO Pull-up/down when system enter to Power Down mode
+// Input : Id : GPIO port
+// uValue : value(16bit)
+// Output : NONE
+//
+// Version : v0.1
+void GPIO_SetPullUDPDNAll(GPIO_eId Id, int uValue)
+{
+ volatile int *pGPIOx_PullUDPDNReg;
+ volatile int *pGPIO_Base_Addr;
+ int uConRegNum, uDataRegNum, uPullUDRegNum, uConDSRegNum, uConPDNRegNum, uOffset;
+
+ uOffset = Id&0xFFFFFF;
+ uConRegNum = 1;
+ uDataRegNum = 1;
+ uPullUDRegNum = 1;
+ uConDSRegNum =1;
+ uConPDNRegNum = 1;
+
+ pGPIO_Base_Addr = &(GPIO_REG->rGPIOJ0CON);
+
+ pGPIOx_PullUDPDNReg = pGPIO_Base_Addr + (uOffset/4) + (uConRegNum+uDataRegNum+uPullUDRegNum+uConDSRegNum+uConPDNRegNum);
+ *pGPIOx_PullUDPDNReg = uValue;
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint1
+// Function Desctiption : This function setup Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint1(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+// GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT1CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_A0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT1FLTCON0) ; // EINT1FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT1FLTCON1); // EINT1FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT1ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT1PEND;
+ int uConValue;
+
+ pEINT1PEND = &(GPIO_REG->rEINT1PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT1PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT1UnMask
+// Function Desctiption : UnMask the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT1MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT1Mask
+// Function Desctiption : Mask the Eint1[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT1Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT1MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+//////////
+// Function Name : GPIO_SetEint2
+// Function Desctiption : This function setup Eint2[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint2(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT2CON);
+
+
+ if (uEINT_No >5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_A1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT2FLTCON0) ; // EINT2FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT2FLTCON1); // EINT2FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT2ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT2PEND;
+ int uConValue;
+
+ pEINT2PEND = &(GPIO_REG->rEINT2PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT2PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT2UnMask
+// Function Desctiption : UnMask the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT2MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT2Mask
+// Function Desctiption : Mask the Eint2[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT2Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT2MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint3
+// Function Desctiption : This function setup Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint3(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT3CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_B, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT3FLTCON0) ; // EINT3FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT3FLTCON1); // EINT3FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT3ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT3PEND;
+ int uConValue;
+
+ pEINT3PEND = &(GPIO_REG->rEINT3PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT3PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT3UnMask
+// Function Desctiption : UnMask the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT3MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT3Mask
+// Function Desctiption : Mask the Eint3[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT3Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT3MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint4
+// Function Desctiption : This function setup Eint4[4:0]=> GPC0[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint4(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT4CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_C0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT4FLTCON0) ; // EINT4FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT4FLTCON1); // EINT4FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT4ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT4PEND;
+ int uConValue;
+
+ pEINT4PEND = &(GPIO_REG->rEINT4PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT4PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT4UnMask
+// Function Desctiption : UnMask the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT4MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT4Mask
+// Function Desctiption : Mask the Eint4[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT4Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT4MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint5
+// Function Desctiption : This function setup Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint5(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT5CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_C1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT5FLTCON0) ; // EINT5FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT5FLTCON1); // EINT5FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT5ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT5PEND;
+ int uConValue;
+
+ pEINT5PEND = &(GPIO_REG->rEINT5PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT5PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT5UnMask
+// Function Desctiption : UnMask the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT5MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT5Mask
+// Function Desctiption : Mask the Eint5[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT5Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT5MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint6
+// Function Desctiption : This function setup Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint6(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT6CON);
+
+ if (uEINT_No > 3)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 3)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_D0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT6FLTCON0) ; // EINT6FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+6)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT6ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT6PEND;
+ int uConValue;
+
+ pEINT6PEND = &(GPIO_REG->rEINT6PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT6PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT6UnMask
+// Function Desctiption : UnMask the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT6MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT6Mask
+// Function Desctiption : Mask the Eint6[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT6Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT6MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint7
+// Function Desctiption : This function setup Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint7(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT7CON);
+
+ if (uEINT_No > 3)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 3)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_D1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT7FLTCON0) ; // EINT7FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT7ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT7PEND;
+ int uConValue;
+
+ pEINT7PEND = &(GPIO_REG->rEINT7PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT7PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT7UnMask
+// Function Desctiption : UnMask the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT7MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT7Mask
+// Function Desctiption : Mask the Eint7[3:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT7Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT7MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint8
+// Function Desctiption : This function setup Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint8(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT8CON);
+
+ if (uEINT_No > 4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT8FLTCON0) ; // EINT8FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT8FLTCON1); // EINT8FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT8ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT8PEND;
+ int uConValue;
+
+ pEINT8PEND = &(GPIO_REG->rEINT8PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT8PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT8UnMask
+// Function Desctiption : UnMask the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT8MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT8Mask
+// Function Desctiption : Mask the Eint8[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT8Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT8MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+//////////
+// Function Name : GPIO_SetEint9
+// Function Desctiption : This function setup Eint9[7:0]=> GPE1[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint9(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT9CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT9FLTCON0) ; // EINT9FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT9FLTCON1); // EINT9FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT9ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint9[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT9PEND;
+ int uConValue;
+
+ pEINT9PEND = &(GPIO_REG->rEINT9PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT9PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT9UnMask
+// Function Desctiption : UnMask the Eint9[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT9MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT9Mask
+// Function Desctiption : Mask the Eint9[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT9Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT9MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint10
+// Function Desctiption : This function setup Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint10(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT10CON);
+
+ if (uEINT_No > 5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT10FLTCON0) ; // EINT10FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <=5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT10FLTCON1); // EINT10FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT10ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT10PEND;
+ int uConValue;
+
+ pEINT10PEND = &(GPIO_REG->rEINT10PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT10PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT10UnMask
+// Function Desctiption : UnMask the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT10MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT10Mask
+// Function Desctiption : Mask the Eint10[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT10Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT10MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint11
+// Function Desctiption : This function setup Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint11(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT11CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT11FLTCON0) ; // EINT11FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT11FLTCON1); // EINT11FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT11ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT11PEND;
+ int uConValue;
+
+ pEINT11PEND = &(GPIO_REG->rEINT11PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT11PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT11UnMask
+// Function Desctiption : UnMask the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT11MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT11Mask
+// Function Desctiption : Mask the Eint11[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT11Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT11MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint12
+// Function Desctiption : This function setup Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint12(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT12CON);
+
+
+ if (uEINT_No >7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_E4, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT12FLTCON0) ; // EINT12FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT12FLTCON1); // EINT12FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT12ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT12PEND;
+ int uConValue;
+
+ pEINT12PEND = &(GPIO_REG->rEINT12PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT12PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT12UnMask
+// Function Desctiption : UnMask the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT12MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT12Mask
+// Function Desctiption : Mask the Eint12[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT12Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT12MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint13
+// Function Desctiption : This function setup Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint13(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT13CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT13FLTCON0) ; // EINT13FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT13FLTCON1); // EINT13FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT13ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT13PEND;
+ int uConValue;
+
+ pEINT13PEND = &(GPIO_REG->rEINT13PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT13PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT13UnMask
+// Function Desctiption : UnMask the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT13MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT13Mask
+// Function Desctiption : Mask the Eint13[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT13Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT13MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint14
+// Function Desctiption : This function setup Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint14(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT14CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT14FLTCON0) ; // EINT14FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT14FLTCON1); // EINT14FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT14ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT14PEND;
+ int uConValue;
+
+ pEINT14PEND = &(GPIO_REG->rEINT14PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT14PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT14UnMask
+// Function Desctiption : UnMask the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT14MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT14Mask
+// Function Desctiption : Mask the Eint14[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT14Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT14MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint15
+// Function Desctiption : This function setup Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint15(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT15CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F2, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT15FLTCON0) ; // EINT15FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT15FLTCON1); // EINT15FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT15ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT15PEND;
+ int uConValue;
+
+ pEINT15PEND = &(GPIO_REG->rEINT15PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT15PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT15UnMask
+// Function Desctiption : UnMask the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT15MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT15Mask
+// Function Desctiption : Mask the Eint15[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT15Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT15MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint16
+// Function Desctiption : This function setup Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint16(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT16CON);
+
+ if (uEINT_No > 5)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth > 0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 5)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 5)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_F3, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT16FLTCON0) ; // EINT16FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No >3 && uEINT_No <= 5)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT16FLTCON1); // EINT16FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT16ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT16PEND;
+ int uConValue;
+
+ pEINT16PEND = &(GPIO_REG->rEINT16PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT16PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT16UnMask
+// Function Desctiption : UnMask the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT16MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT16Mask
+// Function Desctiption : Mask the Eint16[5:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT16Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT16MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+//=========================================================
+// C200
+// Don't use eint17~eint20
+//=========================================================
+
+//////////
+// Function Name : GPIO_SetEint21
+// Function Desctiption : This function setup Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint21(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT21CON);
+
+ if (uEINT_No > 7)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 7)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 7)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_J0, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT21FLTCON0) ; // EINT21FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No > 3 && uEINT_No <= 7)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT21FLTCON1); // EINT21FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT21ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT21PEND;
+ int uConValue;
+
+ pEINT21PEND = &(GPIO_REG->rEINT21PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT21PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT21UnMask
+// Function Desctiption : UnMask the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT21MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT21Mask
+// Function Desctiption : Mask the Eint21[7:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT21Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT21MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+
+//////////
+// Function Name : GPIO_SetEint22
+// Function Desctiption : This function setup Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint22(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT22CON);
+
+
+ if (uEINT_No >4)
+ {
+ printf("Error Eint No. \n");
+ }
+
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+
+ // Interrupt Type
+ if( uEINT_No <= 4)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 4)
+ {
+ uGpioPort = uEINT_No;
+ uFunc = 0xf; // EINT Function
+ GPIO_SetFunctionEach(eGPIO_J1, (GPIO_eBitPos)uGpioPort, uFunc); // ??
+ // GPIO_SetPullUpDownEach(eGPIO_N,(GPIO_eBitPos) uGpioPort, 0x0); // disable Pull-up/dn
+ }
+
+ // Fliter Type & Filter Width
+ if( uEINT_No <= 3)
+ {
+ uType =uEINT_No;
+ pFLTx_Reg = &(GPIO_REG->rEINT22FLTCON0) ; // EINT22FLTCON0
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+ else if(uEINT_No == 4)
+ {
+ uType =uEINT_No-4;
+ pFLTx_Reg =&(GPIO_REG->rEINT22FLTCON1); // EINT22FLTCON1
+ uConValue = *pFLTx_Reg;
+ uConValue = (uConValue & ~(0xFF<<(uType*8))) |((uFltWidth<<(uType*8))|(eFltType<<(uType*8+7)));
+ *pFLTx_Reg = uConValue;
+ }
+
+
+}
+
+
+
+//////////
+// Function Name : GPIO_EINT22ClrPend
+// Function Desctiption : Clear Eint pending bit of the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22ClrPend(int uEINT_No )
+{
+
+ volatile int *pEINT22PEND;
+ int uConValue;
+
+ pEINT22PEND = &(GPIO_REG->rEINT22PEND);
+
+ uConValue = (1<<uEINT_No);
+ *pEINT22PEND = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT22UnMask
+// Function Desctiption : UnMask the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22UnMask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT22MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)));
+ *pMASK_Reg = uConValue;
+
+}
+
+//////////
+// Function Name : GPIO_EINT22Mask
+// Function Desctiption : Mask the Eint22[4:0]
+// Input : uEINT_No: EINT No.
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_EINT22Mask(int uEINT_No )
+{
+
+ volatile int *pMASK_Reg;
+ int uConValue;
+
+ pMASK_Reg = &(GPIO_REG->rEINT22MASK);
+
+ uConValue = *pMASK_Reg;
+ uConValue = (uConValue & ~(0x1<<(uEINT_No)))|(1<<uEINT_No);
+ *pMASK_Reg = uConValue;
+
+}
+
+
+
+//////////
+// Function Name : GPIO_SetEint23
+// Function Desctiption : This function setup Eint23[6:0]
+// Input : uEINT_No: EINT No.
+// uINTType: Select EINT Type.
+// Low, High, Falling, Rising, Both
+// uFltType : Select Filter Type
+// DisFLT(Disable Filter), DLYFLT(Delay Filter), DIGFLT(Digital Filter)
+// uFltWidth : Digital Filter Width ( 1~0x7F)
+// Output : NONE
+//
+// Version : v0.0
+void GPIO_SetEint23(int uEINT_No , int uIntType, FLT_eTYPE eFltType, int uFltWidth)
+{
+
+ volatile int *pEINTx_Reg, *pFLTx_Reg;
+ volatile int *pGPIO_EINT_Addr;
+ int uGpioPort, uFunc, uType ;
+ int uConValue;
+
+ GPIO_pBase = (void *)GPIO_BASE;
+
+ pGPIO_EINT_Addr = &(GPIO_REG->rEINT23CON);
+
+ if (uEINT_No > 6)
+ {
+ printf("Error Eint No. \n");
+ }
+
+ // Check Filter Width
+ if(uFltWidth >0x7f)
+ {
+ printf("Error Filter Width. \n");
+ }
+
+ // Interrupt Type
+ if( uEINT_No <= 6)
+ {
+ uType =uEINT_No;
+ pEINTx_Reg = pGPIO_EINT_Addr ;
+ uConValue = *pEINTx_Reg;
+ uConValue = (uConValue & ~(0xF<<(uType*4))) | (uIntType<<(uType*4));
+ *pEINTx_Reg = uConValue;
+ }
+
+
+ // EINT Port
+ if( uEINT_No <= 6)
+ {
+ uGpioPort = uEINT_No;