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2018-02-07Fix a typo errorodroidn1-v2017.07joy1-1/+1
Change-Id: I300e06a2ed3aed60300a2322a041a13fbe249473
2017-12-28sd_fuse: adjust sdfuse.sh to use flexible card nodeJoy Cho1-3/+19
Change-Id: I6fa0c6d365683bb4f9fe633049993e53922aaed3
2017-12-28Add boot device detection logic to operate flexible mmc ordersJoy Cho6-6/+143
In case of rk3399 platform, there is no way to detect boot storage from chip side, so mmc orders are fixed based on aliases setting. - mmc0 : sdhci (eMMC) / mmc1 : dwmmc (SD) To be available to use both of eMMC and SD with a single image, this storage scanning logic is introduced. Change-Id: Iecb3778b43c096a0b0eeba1741763b7bc10013e8
2017-12-28configs: odroid-n1: set CONFIG_EXTRA_ENV_SETTINGSJoy Cho1-0/+8
Change-Id: I6b6767c54ae0751f76f290e138e396fa53961c8e
2017-12-28cmd: Introduce cfgload command to load boot.iniJoy Cho4-0/+153
Change-Id: I3c41b9678493135c45d69fa681ddf6a4ac8a59ef
2017-12-28board: odroidn1: Activate regulator, vdd-logJoy Cho1-0/+14
Change-Id: I002c2c4e99dfd4a08628f9ea850d52a79e41092a
2017-12-27ODROID-N1: Introduce ODROID-N1 with all rockchip binaries and a sample build ↵Mauro (mdrjr) Ribeiro30-0/+1905
script Required Toolchain: https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu.tar.xz export ARCH=arm64 export CROSS_COMPILE=.... Change-Id: I00673c8b006e53e876c52bb09ddea92812a824fb
2017-07-25rockchip: use UUID for root partitionsKever Yang1-1/+7
We use to use /dev/mmcbl0p7 as root partition, and pass it to kernel by cmdline, but the mmc number in kernel in not fixed, we need to change the bootargs to adapt it from time to time. We can use the UUID to fix it, the ID is from: https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/ ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3 ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae Change-Id: I5918251ff128ded2a91b82faa378e71ab3ee95cb Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21TESTONLY: rk322x local patchKever Yang2-0/+2
1. fifo mode is need when not using miniloader 2. rockchip is needed when not using SPL Change-Id: I926cea6f6e1bfd81f4fe207ec43ddd4d490ddd25 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: dts: rk3229: remove dram channel infoKever Yang1-1/+0
The dram channel info will be auto detect by the driver, we do not need it. Cover-letter: rockchip: rk3229: add sdram and sd support Add sdram driver for rk3229 and other fix like pinctrl and sd node. END Change-Id: I4cb96150fe3cf68278b9c1cb6585e1bf3d4df4b1 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: rk322x: pinctrl: using compatible name same with dtsKever Yang1-4/+4
The dts from kernel is using rk3228-pinctrl as compatible name, need to sync with it to make the driver work. Fix the IOMUX setting for SDcard CMD pin at the same time. Change-Id: Idbde27833c4db30fd6938e46af2fbd276833a905 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: dts: rk322x: add sdmmc device nodeKever Yang2-0/+74
add node for sdmmc in dts and rk3229-evb. Change-Id: I33d328967c904fc56f6195f89cc601eb159b4451 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: rk322x: add sdram driverKever Yang3-0/+1437
Add driver for rk322x to support sdram initialize in SPL. Change-Id: I44f5fed275d65e7758efd38f1a5124a8d9698a7d Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: rk322x: update dram bank sizeKever Yang1-4/+6
The DRAM start address is not 0, so need to update the last bank size as: DRAM start addr + DRAM_SIZE - last bank start addr Change-Id: I674a7564b6223c49447d1aa40780196d2f7d3cfa Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: dts: rk3229: add dwc2 node for fastbootMeng Dongyang2-0/+14
Add dwc2 node for fastboot to init dwc2 controller. Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
2017-07-21rockchip: rk3399: correct the env settingKever Yang1-5/+6
The mmc0(emmc) is the default boot device, so let's use mmc device 0 as default env device. The SPL size in rk3399 is lager than other Rockchip SoC, we need to using a new offset and not to conflict with SPL memory space. Change-Id: I2b2738afda4f6e9340691fef7abb197550ce6fba Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: pwm: add mask for config settingKever Yang2-0/+3
Use mask to clear old setting before direct set the new config, or else there it will mess up the config when it's not the same with default value. Fixs: 3851059 rockchip: Setup default PWM flags Change-Id: Id991f5af0917a70cf25e9ff7434b7b4e9592d0a0 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21power: pwm_regulator: remove redundance codeKever Yang1-7/+1
The regulator_enable() should be called from upper layer like regulators_enable_boot_on(), remove it from pwm regulator driver. Change-Id: Ibb4e631d42fa8099cc25abf3d0b61c031c7804fa Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21power: pwm_regulator: fix the pwm_set_config parameter orderKever Yang1-1/+1
The rkpwm reg order has fixed by below patch: e3ef41d rockchip: pwm: fix the register layout for the PWM controller We need to correct the parameter order for pwm_set_config() to make the pwm regulator works correctly. Change-Id: I89d548972ce95454dee99522c0db83e5b90c8a76 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: dts: correct vdd_log setting for firefly-rk3399Kever Yang1-1/+2
Add regulator-init-microvolt for driver to init the regulator, and the min output value is not 800000mV for the PWM2 io domain has changed to VCC3V0 instead of VCC1V8 in rockchip evb, we need to correct it with the value measured when PWM2 output HIGH. Change-Id: I3689496c7cae4b6551205eb2f9ec5393234cf953 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: dts: firefly using ddr3 1600Kever Yang1-1/+1
According to my test, some of firefly-rk3399 hang after dram init when using ddr3-1333 config, while using ddr3-1600 config works for all the board I have test. Change-Id: Ia16319ab028a9c5cd7ab331a8dd25f28ffbac225 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: rk3399: dtsi: enable mmc_phy in SPLKever Yang1-0/+1
Change-Id: I741fb1416f176a64a792e6c35c1103bcdc9a5b27 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21mmc: rpmb: update size format for write_counterKever Yang1-1/+1
According to MMC spec, the write_counter is 4-byte length, use 'int' instead of 'long' type for the 'long' is not 4-byte in 64 bit CPU. Change-Id: Id7581a5248b29bd98c7207afa2993990ff0f4660 Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21mmc: use new hwpart API when CONFIG_BLK enabledKever Yang1-0/+4
When CONFIG_BLK is enabled, the hwpart id is different with legacy interface, update it to kame driver work with CONFIG_BLK. Change-Id: I581c2da9573e4a61dffc2031131e668127b97b9a Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-21rockchip: config: add ATF support for rk3399Kever Yang2-0/+8
Change-Id: Iebd2ae738cd952e16fd24d6869dfafe36ef77140 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2017-07-18dts: rk3399: change the maximum eMMC clock frequency to 150MHzZiyuan Xu1-1/+1
The rockchip mmc controllers don't support _the _odd__ divider, otherwise probably cause unpredictable error. The driver originally select gpll(594M) as the clock source, and we set div to 3 at 200MHz. We have to change the maximum eMMC clock frequency to 150MHz in U-Boot stage, so that the div will be 4. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: add support for HS400 mode of eMMC5.0Ziyuan Xu1-2/+46
This patch adds HS400 mode support for eMMC5.0 device. HS400 mode is high speed DDR interface timing from HS200. Clock frequency is up to 200MHz and only 8-bit bus width is supported. In addition, tuning process of HS200 is required to synchronize the command response on the CMD line because CMD input timing for HS400 mode is the same as HS200 mode. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: add the support for tuningZiyuan Xu1-1/+115
MMC framework has already implemented hs200 mode for eMMC devices, moreover the standard SDHC3.0 controller support tuning. We can set the corresponding flag in host->host_cpas. Host driver issue tuning command repeatedly until the host controller resets Execute Tuning to 0. Host controller resets Execute Tuning to 0 when tuning is completed or tuning is not completed within 40 times. Host driver can abort this loop by 40 times CMD19/CMD21 issue or 150ms time-out. If tuning is completed successfully, driver set Sampling Clock Select to 1 and this means the host contorller start to use tuned sampling clcok. If tuning is failed, host controller keeps Sampling Clock Select to 0. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: rockchip: add phy supportZiyuan Xu1-0/+147
This patch gets phy phandle from dt-binding, and power cycle/re-configure phy whilst changing card clock. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: export sdhci_set_clock()Ziyuan Xu2-10/+11
For arasan-rk3399-sdhci controller, we should make sure the phy is in poweroff status before we configure the clock stuff. So that we need to export it for phy configuration. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: rename set_clock callbackZiyuan Xu2-4/+4
In fact, the original name is unsuitable for its behavior. It's better to rename to set_clock_ext. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: add support for UHS timingZiyuan Xu3-0/+58
To support UHS speed mode, controller should enable 1.8V signaling and select one of UHS modes. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: update host->clock after clock settingZiyuan Xu1-0/+3
Overwrite host->clock after clock setting to avoid repetitive reset clock. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: rockchip: fix bus width settingZiyuan Xu1-0/+14
Rockchip sdhci controller capable of 8-bit transfer. The original can only run at 4 bit mode. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: dw_mmc: fix bus width settingZiyuan Xu1-2/+1
Hosts capable of 8-bit transfers can also do 4 bits. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: dw_mmc: rockchip: fix data crc error on ddr52 8bit modeZiyuan Xu2-1/+8
The clk_divider must be set to 1 on ddr52 8bit mode for rockchip platform. Otherwise we will get a data crc error during data transmission. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: add DDR52 support for eMMC cardZiyuan Xu1-1/+25
4.41+ eMMC card devices can run at 52MHz on DDR 8-bit mode, it can improve write/read performance. Host driver can set MMC_MODE_DDR_52Mhz to enable this feature. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: dw_mmc: reset controller after data errorZiyuan Xu1-1/+18
Per dw_mmc databook, it's recommend that reset the host contoller if some data-related error occurre during tuning progress. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: dw_mmc: rockchip: implement tuning with clock phase frameworkZiyuan Xu1-0/+121
This algorithm will try 1 degree increment, since there's no way to tell what resolution the underlying phase code uses. As an added bonus, doing many tunings yields better results since some tests are run more than once (ex: if the underlying driver use 45 degree increments, the tuning code will try the same angle more than once). It will then construct a list of good phase ranges (even range that cross 270/0), will pick the biggest range then it will set the sample_clk to the middle of that range. Please notice that it tuning only 0-270 degree in U-Boot, but kernel tuning range is 0-360 degree. Below are two reasons about this: 1. Expect data-related interrupt may miss during 270-360 degree on rockchip platform, dw_mmc driver will poll for data interrupt until 240 seconds timeout afterwards. And the host controller will be left in an unpredictable state. 2. The phase of a clock signal is shift by some delay elements on rockchip platform. And the delay element affected by logic voltage and temperature in runtime. These factors wouldn't have changed a lot in U-Boot stage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: dw_mmc: add the support for the tuning schemeZiyuan Xu2-0/+19
For the HS200/HS400/SDR104, tuning is needed to determine the optimal sampling point. Actual tuning procedure is provided by specific host controller driver. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18rockchip: clk: rk3399: fix emmc clock settingZiyuan Xu1-2/+2
Before this: gpll = 594MHz, set_clock = 200MHz div = 594/200 = 2 real clock is 297MHz After this: gpll = 594MHz, clock = 148.5MHz div = 594+200-1/200 = 3 real clock is 198Mhz Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18rockchip: clk: rk3288: add support for the clock phaseZiyuan Xu1-0/+124
This patch adds phase adjustment for mmc clock(ciu_sample), which is used to select the optimal sampling point of a data input. The phase shift is achieved through 255 delay elements(40-80 picoseconds), and calculate the number of delay element via clock frequency. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18rockchip: clk: rk3288: fix mmc clock settingZiyuan Xu1-3/+3
Mmc clock automatically divide 2 in internal. Before this: gpll = 594MHz, clock = 148.5MHz div = 594/148.5-1 = 3 output clock is 99MHz After this: gpll = 594MHz, clock = 148.5MHz div = 297+148.5-1/148.5 = 2 output clock is 148.5Mhz Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18clk: introduce clk_phase get/set function & callbackZiyuan Xu3-0/+57
A common operation for a clock signal generator is to shift the phase of that signal. This patch introduces a new function to the clk.h API to dynamically adjust the phase of a clock signal. Additionally this patch introduces support for the new function in the clock framework via the .set_phase & .get_phase callback in struct clk_ops. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18cmd: mmc: show the current speed modeZiyuan Xu1-0/+5
So far mmc framework had support speed mode switch, it good to show the current speed mode from 'mmc info'. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: remove tran_speed from struct mmcZiyuan Xu4-8/+7
The clock element is updated by mmc_set_clock every time, it denotes the current transfer speed. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: rework ddr mode judgement with timingZiyuan Xu7-12/+10
Since the card device is set the proper timing after speed mode switch is completed, host driver can get ddr_mode from timing parameter. So drop the antiquated ddr_mode. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: add support for HS200 mode of eMMC4.5Ziyuan Xu2-133/+289
Add the support of the HS200 mode for eMMC 4.5 devices. The eMMC 4.5 device has support up to 200MHz bus speed, it can speed up the boot speed. We can enable this feature via MMC_MODE_HS200 if the host controller has the ability to support HS200 timing. Also the tuning feature required when the HS200 mode is selected. By the way, mmc card can only switch to high speed mode in SPL stage. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: rework mmc_switch for non-send_status scenarioZiyuan Xu1-10/+45
Per JEDEC spec, it is not recommended to use cmd13 to get card status after speed mode switch. CMD13 can't be guaranteed due to the asynchronous operation. Besieds, if the host controller supports busy detection in HW, we use it instead of cmd13. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-07-18mmc: sdhci: implement card_busy detectionZiyuan Xu2-0/+20
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>