diff options
| author | Matt Redfearn <matt.redfearn@imgtec.com> | 2015-08-12 12:25:54 +0300 |
|---|---|---|
| committer | Matt Redfearn <matt.redfearn@imgtec.com> | 2015-08-17 17:02:23 +0300 |
| commit | 02c37a5bf395e55b65e9985315b8fcf22fc14a76 (patch) | |
| tree | 81871007daabb0229bb7659017f7bdec1fcdbce4 | |
| parent | 040103141210f8e84049d203d0043f2f6b362f6b (diff) | |
| download | CI20_u-boot-02c37a5bf395e55b65e9985315b8fcf22fc14a76.tar.xz | |
jz4780: apply DQS changes to ddr config
The ddr phy used in the soc has a silicon bug which affects DQS
gating. This patch enables DQS gate early and DQS gate extension and
sets the DQSRES pull-up and pull-down resistors values to 500R to
get round the issue.
Signed-off-by: Ian Pozella <ian.pozella@imgtec.com>
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
| -rw-r--r-- | arch/mips/cpu/xburst/jz4780/sdram.c | 15 | ||||
| -rwxr-xr-x | arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h | 2 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/mips/cpu/xburst/jz4780/sdram.c b/arch/mips/cpu/xburst/jz4780/sdram.c index 953a50dc0..3dc46cc8f 100644 --- a/arch/mips/cpu/xburst/jz4780/sdram.c +++ b/arch/mips/cpu/xburst/jz4780/sdram.c @@ -187,6 +187,19 @@ static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg) hang(); } + // DQS extension and early set to 1 + tmp = readl(DDRP_DSGCR); + tmp &= ~(0x7E << 4); + tmp |= 0x12 << 4; + writel(tmp, DDRP_DSGCR); + + // 500 pull up and 500 pull down + tmp = readl(DDRP_DXCCR); + tmp &= ~(0xFF << 4); + tmp |= 0xC4 << 4; + writel(tmp, DDRP_DXCCR); + + // Initialise phy writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST, DDRP_PIR); count = 0; @@ -207,6 +220,7 @@ static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg) } } + // Override impedence tmp = readl(DDRP_ZQXCR0(0)); tmp &= ~0x3ff; tmp |= (CONFIG_SYS_DDR3PHY_PULLUP_IMPEDANCE & 0x1f) << @@ -215,6 +229,7 @@ static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg) DDRP_ZQXCR_PULLDOWN_IMPE_BIT; tmp |= DDRP_ZQXCR_ZDEN; writel(tmp, DDRP_ZQXCR0(0)); + } #define BIT(bit) ((bit % 4) * 8) diff --git a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h index c9a0a6d78..c3e8a9b65 100755 --- a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h +++ b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h @@ -70,7 +70,7 @@ #define DDR_tWL (DDR_tAL + DDR_tCWL) /* DDR3: Write Latency = tAL + tCWL */ #define DDR_tRDLAT (DDR_tRL - 2) #define DDR_tWDLAT (DDR_tWL - 1) -#define DDR_tRTW (DDR_tRL + DDR_tCCD + 2 - DDR_tWL) /* Read to Write delay */ +#define DDR_tRTW (DDR_tRL + DDR_tCCD + 2 - DDR_tWL + 1) /* Read to Write delay */ #define DDR_tCKSRE DDR_MAX(5, 10000) /* Valid Clock Requirement after Self Refresh Entry or Power-Down Entry */ #define DDR_tDLLLOCK 512 /* DDR3 only: DLL LOCK, tck */ |