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authorMatt Redfearn <matt.redfearn@imgtec.com>2015-08-17 17:09:47 +0300
committerMatt Redfearn <matt.redfearn@imgtec.com>2015-08-17 17:09:47 +0300
commit4b23cbb425f92a5045abd8aef6c032b9188b8125 (patch)
treecc96e6d63a1ef2066acfa41b96b337595a1d83d3
parent383e0f20df1908af739d716dece58a27ad58e4b5 (diff)
downloadCI20_u-boot-4b23cbb425f92a5045abd8aef6c032b9188b8125.tar.xz
jz4780: Set up RAM device settings
Set up a structure of device settings for each of the in use RAM devices Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
-rwxr-xr-xarch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h64
-rw-r--r--arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h64
2 files changed, 122 insertions, 6 deletions
diff --git a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
index c3e8a9b65..6fc6541d3 100755
--- a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
+++ b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
@@ -1,5 +1,7 @@
-#ifndef __DDR3_CONFIG_H
-#define __DDR3_CONFIG_H
+#ifndef __DDR3_H5TQ2G83CFR_CONFIG_H
+#define __DDR3_H5TQ2G83CFR_CONFIG_H
+
+#if 0
#define SDRAM_PART_NAME "H5TQ2G83CFR"
#define SDRAM_TYPE_DDR3
@@ -87,5 +89,61 @@
#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh
* cnt_clk = memclk/(16*(2^DDR_CLK_DIV))
*/
+#endif
+
+#include "ddr_parameters.h"
+
+static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
+ .name = "H5TQ2G83CFR",
+
+ .timing1 = ( (4 << DDRC_TIMING1_TRTP_BIT) |
+ (13 << DDRC_TIMING1_TWTR_BIT) |
+ (6 << DDRC_TIMING1_TWR_BIT) |
+ (5 << DDRC_TIMING1_TWL_BIT)),
+
+ .timing2 = ( (4 << DDRC_TIMING2_TCCD_BIT) |
+ (16 << DDRC_TIMING2_TRAS_BIT) |
+ (6 << DDRC_TIMING2_TRCD_BIT) |
+ (6 << DDRC_TIMING2_TRL_BIT)),
+
+ .timing3 = ( (4 << DDRC_TIMING3_ONUM) |
+ (7 << DDRC_TIMING3_TCKSRE_BIT) |
+ (6 << DDRC_TIMING3_TRP_BIT) |
+ (4 << DDRC_TIMING3_TRRD_BIT) |
+ (22 << DDRC_TIMING3_TRC_BIT)),
+
+ .timing4 = ( (42 << DDRC_TIMING4_TRFC_BIT) |
+ (1 << DDRC_TIMING4_TRWCOV_BIT) |
+ (4 << DDRC_TIMING4_TCKE_BIT) |
+ (7 << DDRC_TIMING4_TMINSR_BIT) |
+ (3 << DDRC_TIMING4_TXP_BIT) |
+ (3 << DDRC_TIMING4_TMRD_BIT)),
+
+ .timing5 = ( (8 << DDRC_TIMING5_TRTW_BIT) |
+ (4 << DDRC_TIMING5_TRDLAT_BIT) |
+ (4 << DDRC_TIMING5_TWDLAT_BIT)),
+
+ .timing6 = ( (25 << DDRC_TIMING6_TXSRD_BIT) |
+ (20 << DDRC_TIMING6_TFAW_BIT) |
+ (2 << DDRC_TIMING6_TCFGW_BIT) |
+ (2 << DDRC_TIMING6_TCFGR_BIT)),
+ /* PHY */
+
+ /* Mode Register 0 */
+ .mr0 = (0x00000420),
+#ifdef SDRAM_DISABLE_DLL
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+ .ptr0 = 0x002000d4,
+ .ptr1 = 0x02d30d40,
+ .ptr2 = 0x04013880,
+
+ .dtpr0 = 0x2c906690,
+ .dtpr1 = 0x005608a0,
+ .dtpr2 = 0x10042a00,
+};
-#endif /* __DDR3_CONFIG_H */
+#endif /* __DDR3_H5TQ2G83CFR_CONFIG_H */
diff --git a/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h b/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h
index e33452b1d..ab4df221e 100644
--- a/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h
+++ b/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h
@@ -1,5 +1,7 @@
-#ifndef __DDR3_CONFIG_H
-#define __DDR3_CONFIG_H
+#ifndef __DDR3_K4B2G0846Q_CONFIG_H
+#define __DDR3_K4B2G0846Q_CONFIG_H
+
+#if 0
#define SDRAM_PART_NAME "K4B2G0846Q"
#define SDRAM_TYPE_DDR3
@@ -87,5 +89,61 @@
#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh
* cnt_clk = memclk/(16*(2^DDR_CLK_DIV))
*/
+#endif
+
+#include "ddr_parameters.h"
+
+
+static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
+ .name = "K4B2G0846Q",
+
+ .timing1 = ( (4 << DDRC_TIMING1_TRTP_BIT) |
+ (13 << DDRC_TIMING1_TWTR_BIT) |
+ (6 << DDRC_TIMING1_TWR_BIT) |
+ (5 << DDRC_TIMING1_TWL_BIT)),
+
+ .timing2 = ( (4 << DDRC_TIMING2_TCCD_BIT) |
+ (15 << DDRC_TIMING2_TRAS_BIT) |
+ (6 << DDRC_TIMING2_TRCD_BIT) |
+ (6 << DDRC_TIMING2_TRL_BIT)),
+
+ .timing3 = ( (4 << DDRC_TIMING3_ONUM) |
+ (7 << DDRC_TIMING3_TCKSRE_BIT) |
+ (6 << DDRC_TIMING3_TRP_BIT) |
+ (4 << DDRC_TIMING3_TRRD_BIT) |
+ (21 << DDRC_TIMING3_TRC_BIT)),
+
+ .timing4 = ( (31 << DDRC_TIMING4_TRFC_BIT) |
+ (1 << DDRC_TIMING4_TRWCOV_BIT) |
+ (4 << DDRC_TIMING4_TCKE_BIT) |
+ (9 << DDRC_TIMING4_TMINSR_BIT) |
+ (8 << DDRC_TIMING4_TXP_BIT) |
+ (3 << DDRC_TIMING4_TMRD_BIT)),
+
+ .timing5 = ( (8 << DDRC_TIMING5_TRTW_BIT) |
+ (4 << DDRC_TIMING5_TRDLAT_BIT) |
+ (4 << DDRC_TIMING5_TWDLAT_BIT)),
+
+ .timing6 = ( (25 << DDRC_TIMING6_TXSRD_BIT) |
+ (12 << DDRC_TIMING6_TFAW_BIT) |
+ (2 << DDRC_TIMING6_TCFGW_BIT) |
+ (2 << DDRC_TIMING6_TCFGR_BIT)),
+ /* PHY */
+
+ /* Mode Register 0 */
+ .mr0 = (0x00000420),
+#ifdef SDRAM_DISABLE_DLL
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+ .ptr0 = 0x002000d4,
+ .ptr1 = 0x02230d40,
+ .ptr2 = 0x04013880,
-#endif /* __DDR3_CONFIG_H */
+ .dtpr0 = 0x2a8f6690,
+ .dtpr1 = 0x00400860,
+ .dtpr2 = 0x10042a00,
+};
+#endif /* __DDR3_K4B2G0846Q_CONFIG_H */