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authorMatt Redfearn <matt.redfearn@imgtec.com>2015-07-15 17:06:46 +0300
committerMatt Redfearn <matt.redfearn@imgtec.com>2015-07-15 17:53:41 +0300
commit5da5eb5eb58d28d00caeddaffcb04d9e772f1d6e (patch)
treed87d03e3426210218d0332134203ae037d6acb2d
parent367f34c092e7ba9dd7e4c41993a00dc13a857bdf (diff)
downloadCI20_u-boot-5da5eb5eb58d28d00caeddaffcb04d9e772f1d6e.tar.xz
jz4780: Placeholder for refering to ci20 revision
If u-boot is configured for the Ci20 board, access the ci20_revision Ideally I guess, SDRAM initialisation would be board specific, not SoC Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
-rw-r--r--arch/mips/cpu/xburst/jz4780/sdram.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/cpu/xburst/jz4780/sdram.c b/arch/mips/cpu/xburst/jz4780/sdram.c
index 8d54412b4..953a50dc0 100644
--- a/arch/mips/cpu/xburst/jz4780/sdram.c
+++ b/arch/mips/cpu/xburst/jz4780/sdram.c
@@ -27,6 +27,11 @@
#include <asm/io.h>
#include <asm/arch/jz4780.h>
+#ifdef __CONFIG_CI20_H__
+/* Configured for Ci20 - we can get the board revision from here */
+extern int ci20_revision;
+#endif /* ci20 */
+
#ifdef CONFIG_SYS_DDR3_H5TQ2G83CFR
#include "sdram/H5TQ2G83CFR.h"
#endif