summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorChris Larsen <chris.larsen@imgtec.com>2014-10-03 21:38:22 +0400
committerJames Cowgill <james410@cowgill.org.uk>2015-05-21 15:44:48 +0300
commit6a9d3738225351efe9a2134a1ce512e7f82728a7 (patch)
treed6a984226652dbe60b43378505ab999845afe760
parent132f9a8398a21e600612855fae94859b72a513de (diff)
downloadCI20_u-boot-6a9d3738225351efe9a2134a1ce512e7f82728a7.tar.xz
Fix U-Boot shell command "reset" to actually reset the CI20 board.ci20-chromiumos
-rw-r--r--arch/mips/cpu/xburst/jz4780/Makefile1
-rw-r--r--arch/mips/cpu/xburst/jz4780/cpu.c76
-rw-r--r--arch/mips/cpu/xburst/jz4780/timer.c3
-rw-r--r--arch/mips/include/asm/arch-jz4780/jz4780.h211
4 files changed, 289 insertions, 2 deletions
diff --git a/arch/mips/cpu/xburst/jz4780/Makefile b/arch/mips/cpu/xburst/jz4780/Makefile
index 126b989ab..8720c38c3 100644
--- a/arch/mips/cpu/xburst/jz4780/Makefile
+++ b/arch/mips/cpu/xburst/jz4780/Makefile
@@ -29,6 +29,7 @@ COBJS-y = $(SOC).o
COBJS-y += pll.o
COBJS-y += sdram.o
COBJS-y += timer.o
+COBJS-y += cpu.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/mips/cpu/xburst/jz4780/cpu.c b/arch/mips/cpu/xburst/jz4780/cpu.c
new file mode 100644
index 000000000..28d7cae76
--- /dev/null
+++ b/arch/mips/cpu/xburst/jz4780/cpu.c
@@ -0,0 +1,76 @@
+/*
+ * JZ4780 CPU
+ *
+ * Copyright (c) 2014 Imagination Technologies
+ * Author: Chris Larsen <chris.larsen@imgtec.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/jz4780.h>
+
+extern void tcu_writel(uint32_t, uint32_t);
+
+static void wdt_writew(uint16_t val, uint32_t off)
+{
+ writew(val, (void __iomem *)WDT_BASE + off);
+}
+
+static void wdt_writeb(uint8_t val, uint32_t off)
+{
+ writeb(val, (void __iomem *)WDT_BASE + off);
+}
+
+void _machine_restart(void)
+{
+ debug("%s, line %d: %s() entered\n", __FILE__, __LINE__, __func__);
+
+ mdelay(100);
+
+ /* Select the EXTAL as the timer clock input, and make each
+ * WDT clock tick equal 4 ticks of the system clock.
+ */
+ wdt_writew(WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN, WDT_TCSR);
+
+ /* Reset the WDT counter to zero. */
+ wdt_writew(0, WDT_TCNT);
+
+ /* reset after 4ms
+ *
+ * 1 sec CONFIG_SYS_EXTAL ticks
+ * 4ms * ------- * ---------------------- = Number of WDT clock ticks
+ * 1000 ms 1 sec
+ *
+ * As noted above the number of system clock ticks have been
+ * effectively multiplied by 4. All that's left here for the
+ * computation of WDT clock ticks is to divide by 1000
+ * (one thousand).
+ */
+ wdt_writew(CONFIG_SYS_EXTAL / 1000, WDT_TDR);
+
+ /* enable wdt clock */
+ tcu_writel(TCU_TSSR_WDTSC, TCU_TSCR);
+
+ /* wdt start */
+ wdt_writeb(WDT_TCER_TCEN, WDT_TCER);
+
+ while (1) ;
+}
diff --git a/arch/mips/cpu/xburst/jz4780/timer.c b/arch/mips/cpu/xburst/jz4780/timer.c
index ad78e1d36..2d64192c8 100644
--- a/arch/mips/cpu/xburst/jz4780/timer.c
+++ b/arch/mips/cpu/xburst/jz4780/timer.c
@@ -49,7 +49,8 @@ static void tcu_writew(uint16_t val, uint32_t off)
writew(val, (void __iomem *)TCU_BASE + off);
}
-static void tcu_writel(uint32_t val, uint32_t off)
+// This is needed by the WDT code
+void tcu_writel(uint32_t val, uint32_t off)
{
writel(val, (void __iomem *)TCU_BASE + off);
}
diff --git a/arch/mips/include/asm/arch-jz4780/jz4780.h b/arch/mips/include/asm/arch-jz4780/jz4780.h
index 1855726b5..8fe1dc2c9 100644
--- a/arch/mips/include/asm/arch-jz4780/jz4780.h
+++ b/arch/mips/include/asm/arch-jz4780/jz4780.h
@@ -32,7 +32,8 @@
/* APB BUS Devices */
#define CPM_BASE 0xb0000000
-#define TCU_BASE 0xb0002000
+#define TCU_BASE 0xb0002000
+#define WDT_BASE 0xb0002000
#define GPIO_BASE 0xb0010000
#define UART0_BASE 0xb0030000
#define UART1_BASE 0xb0031000
@@ -380,6 +381,214 @@
#define REBOOT_SIGNATURE (0x3535) /* means reboot*/
+/*************************************************************************
+ * TCU (Timer Counter Unit)
+ *************************************************************************/
+#define TCU_TSR 0x1C /* Timer Stop Register */
+#define TCU_TSSR 0x2C /* Timer Stop Set Register */
+#define TCU_TSCR 0x3C /* Timer Stop Clear Register */
+#define TCU_TER 0x10 /* Timer Counter Enable Register */
+#define TCU_TESR 0x14 /* Timer Counter Enable Set Register */
+#define TCU_TECR 0x18 /* Timer Counter Enable Clear Register */
+#define TCU_TFR 0x20 /* Timer Flag Register */
+#define TCU_TFSR 0x24 /* Timer Flag Set Register */
+#define TCU_TFCR 0x28 /* Timer Flag Clear Register */
+#define TCU_TMR 0x30 /* Timer Mask Register */
+#define TCU_TMSR 0x34 /* Timer Mask Set Register */
+#define TCU_TMCR 0x38 /* Timer Mask Clear Register */
+#define TCU_TDFR0 0x40 /* Timer Data Full Register */
+#define TCU_TDHR0 0x44 /* Timer Data Half Register */
+#define TCU_TCNT0 0x48 /* Timer Counter Register */
+#define TCU_TCSR0 0x4C /* Timer Control Register */
+#define TCU_TDFR1 0x50
+#define TCU_TDHR1 0x54
+#define TCU_TCNT1 0x58
+#define TCU_TCSR1 0x5C
+#define TCU_TDFR2 0x60
+#define TCU_TDHR2 0x64
+#define TCU_TCNT2 0x68
+#define TCU_TCSR2 0x6C
+#define TCU_TDFR3 0x70
+#define TCU_TDHR3 0x74
+#define TCU_TCNT3 0x78
+#define TCU_TCSR3 0x7C
+#define TCU_TDFR4 0x80
+#define TCU_TDHR4 0x84
+#define TCU_TCNT4 0x88
+#define TCU_TCSR4 0x8C
+#define TCU_TDFR5 0x90
+#define TCU_TDHR5 0x94
+#define TCU_TCNT5 0x98
+#define TCU_TCSR5 0x9C
+
+// n = 0,1,2,3,4,5
+#define TCU_TDFR(n) (0x40 + (n)*0x10) /* Timer Data Full Reg */
+#define TCU_TDHR(n) (0x44 + (n)*0x10) /* Timer Data Half Reg */
+#define TCU_TCNT(n) (0x48 + (n)*0x10) /* Timer Counter Reg */
+#define TCU_TCSR(n) (0x4C + (n)*0x10) /* Timer Control Reg */
+
+// Register definitions
+#define TCU_TCSR_PWM_SD (1 << 9)
+#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
+#define TCU_TCSR_PWM_EN (1 << 7)
+#define TCU_TCSR_PRESCALE_BIT 3
+#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT)
+ #define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT)
+#define TCU_TCSR_EXT_EN (1 << 2)
+#define TCU_TCSR_RTC_EN (1 << 1)
+#define TCU_TCSR_PCK_EN (1 << 0)
+
+#define TCU_TER_TCEN5 (1 << 5)
+#define TCU_TER_TCEN4 (1 << 4)
+#define TCU_TER_TCEN3 (1 << 3)
+#define TCU_TER_TCEN2 (1 << 2)
+#define TCU_TER_TCEN1 (1 << 1)
+#define TCU_TER_TCEN0 (1 << 0)
+
+#define TCU_TESR_TCST5 (1 << 5)
+#define TCU_TESR_TCST4 (1 << 4)
+#define TCU_TESR_TCST3 (1 << 3)
+#define TCU_TESR_TCST2 (1 << 2)
+#define TCU_TESR_TCST1 (1 << 1)
+#define TCU_TESR_TCST0 (1 << 0)
+
+#define TCU_TECR_TCCL5 (1 << 5)
+#define TCU_TECR_TCCL4 (1 << 4)
+#define TCU_TECR_TCCL3 (1 << 3)
+#define TCU_TECR_TCCL2 (1 << 2)
+#define TCU_TECR_TCCL1 (1 << 1)
+#define TCU_TECR_TCCL0 (1 << 0)
+
+#define TCU_TFR_HFLAG5 (1 << 21)
+#define TCU_TFR_HFLAG4 (1 << 20)
+#define TCU_TFR_HFLAG3 (1 << 19)
+#define TCU_TFR_HFLAG2 (1 << 18)
+#define TCU_TFR_HFLAG1 (1 << 17)
+#define TCU_TFR_HFLAG0 (1 << 16)
+#define TCU_TFR_FFLAG5 (1 << 5)
+#define TCU_TFR_FFLAG4 (1 << 4)
+#define TCU_TFR_FFLAG3 (1 << 3)
+#define TCU_TFR_FFLAG2 (1 << 2)
+#define TCU_TFR_FFLAG1 (1 << 1)
+#define TCU_TFR_FFLAG0 (1 << 0)
+
+#define TCU_TFSR_HFLAG5 (1 << 21)
+#define TCU_TFSR_HFLAG4 (1 << 20)
+#define TCU_TFSR_HFLAG3 (1 << 19)
+#define TCU_TFSR_HFLAG2 (1 << 18)
+#define TCU_TFSR_HFLAG1 (1 << 17)
+#define TCU_TFSR_HFLAG0 (1 << 16)
+#define TCU_TFSR_FFLAG5 (1 << 5)
+#define TCU_TFSR_FFLAG4 (1 << 4)
+#define TCU_TFSR_FFLAG3 (1 << 3)
+#define TCU_TFSR_FFLAG2 (1 << 2)
+#define TCU_TFSR_FFLAG1 (1 << 1)
+#define TCU_TFSR_FFLAG0 (1 << 0)
+
+#define TCU_TFCR_HFLAG5 (1 << 21)
+#define TCU_TFCR_HFLAG4 (1 << 20)
+#define TCU_TFCR_HFLAG3 (1 << 19)
+#define TCU_TFCR_HFLAG2 (1 << 18)
+#define TCU_TFCR_HFLAG1 (1 << 17)
+#define TCU_TFCR_HFLAG0 (1 << 16)
+#define TCU_TFCR_FFLAG5 (1 << 5)
+#define TCU_TFCR_FFLAG4 (1 << 4)
+#define TCU_TFCR_FFLAG3 (1 << 3)
+#define TCU_TFCR_FFLAG2 (1 << 2)
+#define TCU_TFCR_FFLAG1 (1 << 1)
+#define TCU_TFCR_FFLAG0 (1 << 0)
+
+#define TCU_TMR_HMASK5 (1 << 21)
+#define TCU_TMR_HMASK4 (1 << 20)
+#define TCU_TMR_HMASK3 (1 << 19)
+#define TCU_TMR_HMASK2 (1 << 18)
+#define TCU_TMR_HMASK1 (1 << 17)
+#define TCU_TMR_HMASK0 (1 << 16)
+#define TCU_TMR_FMASK5 (1 << 5)
+#define TCU_TMR_FMASK4 (1 << 4)
+#define TCU_TMR_FMASK3 (1 << 3)
+#define TCU_TMR_FMASK2 (1 << 2)
+#define TCU_TMR_FMASK1 (1 << 1)
+#define TCU_TMR_FMASK0 (1 << 0)
+
+#define TCU_TMSR_HMST5 (1 << 21)
+#define TCU_TMSR_HMST4 (1 << 20)
+#define TCU_TMSR_HMST3 (1 << 19)
+#define TCU_TMSR_HMST2 (1 << 18)
+#define TCU_TMSR_HMST1 (1 << 17)
+#define TCU_TMSR_HMST0 (1 << 16)
+#define TCU_TMSR_FMST5 (1 << 5)
+#define TCU_TMSR_FMST4 (1 << 4)
+#define TCU_TMSR_FMST3 (1 << 3)
+#define TCU_TMSR_FMST2 (1 << 2)
+#define TCU_TMSR_FMST1 (1 << 1)
+#define TCU_TMSR_FMST0 (1 << 0)
+
+#define TCU_TMCR_HMCL5 (1 << 21)
+#define TCU_TMCR_HMCL4 (1 << 20)
+#define TCU_TMCR_HMCL3 (1 << 19)
+#define TCU_TMCR_HMCL2 (1 << 18)
+#define TCU_TMCR_HMCL1 (1 << 17)
+#define TCU_TMCR_HMCL0 (1 << 16)
+#define TCU_TMCR_FMCL5 (1 << 5)
+#define TCU_TMCR_FMCL4 (1 << 4)
+#define TCU_TMCR_FMCL3 (1 << 3)
+#define TCU_TMCR_FMCL2 (1 << 2)
+#define TCU_TMCR_FMCL1 (1 << 1)
+#define TCU_TMCR_FMCL0 (1 << 0)
+
+#define TCU_TSR_WDTS (1 << 16)
+#define TCU_TSR_STOP5 (1 << 5)
+#define TCU_TSR_STOP4 (1 << 4)
+#define TCU_TSR_STOP3 (1 << 3)
+#define TCU_TSR_STOP2 (1 << 2)
+#define TCU_TSR_STOP1 (1 << 1)
+#define TCU_TSR_STOP0 (1 << 0)
+
+#define TCU_TSSR_WDTSS (1 << 16)
+#define TCU_TSSR_STPS5 (1 << 5)
+#define TCU_TSSR_STPS4 (1 << 4)
+#define TCU_TSSR_STPS3 (1 << 3)
+#define TCU_TSSR_STPS2 (1 << 2)
+#define TCU_TSSR_STPS1 (1 << 1)
+#define TCU_TSSR_STPS0 (1 << 0)
+
+#define TCU_TSSR_WDTSC (1 << 16)
+#define TCU_TSSR_STPC5 (1 << 5)
+#define TCU_TSSR_STPC4 (1 << 4)
+#define TCU_TSSR_STPC3 (1 << 3)
+#define TCU_TSSR_STPC2 (1 << 2)
+#define TCU_TSSR_STPC1 (1 << 1)
+#define TCU_TSSR_STPC0 (1 << 0)
+
+/*************************************************************************
+ * WDT (WatchDog Timer)
+ *************************************************************************/
+#define WDT_TDR 0x00
+#define WDT_TCER 0x04
+#define WDT_TCNT 0x08
+#define WDT_TCSR 0x0C
+
+// Register definition
+#define WDT_TCSR_PRESCALE_BIT 3
+#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT)
+ #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT)
+#define WDT_TCSR_EXT_EN (1 << 2)
+#define WDT_TCSR_RTC_EN (1 << 1)
+#define WDT_TCSR_PCK_EN (1 << 0)
+
+#define WDT_TCER_TCEN (1 << 0)
+
//n = 0,1,2,3,4,5
#define GPIO_PXPIN(n) (GPIO_BASE + (0x00 + (n)*0x100)) /* PIN Level Register */
#define GPIO_PXINT(n) (GPIO_BASE + (0x10 + (n)*0x100)) /* Port Interrupt Register */