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authorPaul Burton <paul.burton@imgtec.com>2013-06-25 13:31:39 +0400
committerAlex Smith <alex.smith@imgtec.com>2014-07-08 19:10:36 +0400
commit7a0ce7b84b5523d912852c9a512c8bd8b67fbbfa (patch)
tree7a47a4dab60c7f88cfaa7263802f5a73dfb53494
parentebf0c0a0fbdd15eb7429ec1892a292d982b82048 (diff)
downloadCI20_u-boot-7a0ce7b84b5523d912852c9a512c8bd8b67fbbfa.tar.xz
ci20: add support for the Imagination CI20
This is a developer board based around the Ingenic XBurst JZ4780 SoC.
-rw-r--r--board/imgtec/ci20/Makefile42
-rw-r--r--board/imgtec/ci20/README10
-rw-r--r--board/imgtec/ci20/ci20.c187
-rw-r--r--board/imgtec/ci20/config.mk29
-rw-r--r--boards.cfg2
-rw-r--r--include/configs/ci20.h317
6 files changed, 587 insertions, 0 deletions
diff --git a/board/imgtec/ci20/Makefile b/board/imgtec/ci20/Makefile
new file mode 100644
index 000000000..117c680d3
--- /dev/null
+++ b/board/imgtec/ci20/Makefile
@@ -0,0 +1,42 @@
+#
+# CI20 makefile
+#
+# Copyright (c) 2013 Imagination Technologies
+# Author: Paul Burton <paul.burton@imgtec.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/imgtec/ci20/README b/board/imgtec/ci20/README
new file mode 100644
index 000000000..c757d41c7
--- /dev/null
+++ b/board/imgtec/ci20/README
@@ -0,0 +1,10 @@
+CI20 U-Boot
+
+Installation to an SD card:
+ Repartition your card with an MBR such that the first partition starts at an
+ offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
+ to the card like so:
+
+ dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
+ dd if=u-boot.img of=/dev/sdX obs=1K seek=14
+ sync
diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c
new file mode 100644
index 000000000..cf5d5131c
--- /dev/null
+++ b/board/imgtec/ci20/ci20.c
@@ -0,0 +1,187 @@
+/*
+ * CI20 setup code
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/arch/efuse.h>
+#include <asm/arch/jz4780.h>
+#include <asm/arch/nand.h>
+#include <asm/jz_mmc.h>
+
+struct ci20_otp {
+ uint32_t serial_number;
+ uint32_t date;
+ char manufacturer[2];
+ uint8_t mac[6];
+} __packed;
+
+int board_early_init_f(void)
+{
+ /* SYS_POWER_IND high (LED blue, VBUS on) */
+ gpio_direction_output(32 * 5 + 15, 1);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ uint32_t cpccr, ahb2_div;
+ struct ci20_otp otp;
+ char manufacturer[3];
+
+ /* read the board OTP data */
+ cpccr = readl(CPM_CPCCR);
+ ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT) + 1;
+ jz4780_efuse_init(CONFIG_SYS_MEM_SPEED / ahb2_div);
+ jz4780_efuse_read(0x18, 16, (uint8_t *)&otp);
+
+ /* set MAC address */
+ if (!is_valid_ether_addr(otp.mac)) {
+ /* no MAC assigned, generate one from the unique chip ID */
+ jz4780_efuse_read(0x8, 4, &otp.mac[0]);
+ jz4780_efuse_read(0x12, 2, &otp.mac[4]);
+ otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
+ }
+ eth_setenv_enetaddr("ethaddr", otp.mac);
+
+ /* put other board information into the environment */
+ setenv_ulong("serial#", otp.serial_number);
+ setenv_ulong("board_date", otp.date);
+ memcpy(manufacturer, otp.manufacturer, 2);
+ manufacturer[2] = 0;
+ setenv("board_mfr", otp.manufacturer);
+
+ return 0;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+ /* setup pins */
+ writel(0x002c00ff, GPIO_PXINTC(0));
+ writel(0x002c00ff, GPIO_PXMASKC(0));
+ writel(0x002c00ff, GPIO_PXPAT1C(0));
+ writel(0x002c00ff, GPIO_PXPAT0C(0));
+ writel(0x002c00ff, GPIO_PXPENS(0));
+ writel(0x00000003, GPIO_PXINTC(1));
+ writel(0x00000003, GPIO_PXMASKC(1));
+ writel(0x00000003, GPIO_PXPAT1C(1));
+ writel(0x00000003, GPIO_PXPAT0C(1));
+ writel(0x00000003, GPIO_PXPENS(1));
+
+ /* FRB0_N */
+ gpio_direction_input(32 * 0 + 20);
+
+ /* disable write protect */
+ gpio_direction_output(32 * 5 + 22, 1);
+
+ return jz4780_nand_init(nand);
+}
+
+#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MMC_SUPPORT)
+
+int board_mmc_init(bd_t *bd)
+{
+ uint32_t msc_cdr;
+
+ /* setup MSC1 clock */
+ msc_cdr = CONFIG_SYS_MEM_SPEED / 24000000 / 2 - 1;
+ writel(msc_cdr | CPM_MSCCDR_CE, CPM_MSCCDR1);
+ while (readl(CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY);
+
+ /* setup MSC1 pins */
+ writel(0x30f00000, GPIO_PXINTC(4));
+ writel(0x30f00000, GPIO_PXMASKC(4));
+ writel(0x30f00000, GPIO_PXPAT1C(4));
+ writel(0x30f00000, GPIO_PXPAT0S(4));
+
+ jz_mmc_init((msc_cdr + 1) * 2);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_DRIVER_DM9000
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_NAND
+ /* setup pins (some already setup for NAND) */
+ writel(0x04030000, GPIO_PXINTC(0));
+ writel(0x04030000, GPIO_PXMASKC(0));
+ writel(0x04030000, GPIO_PXPAT1C(0));
+ writel(0x04030000, GPIO_PXPAT0C(0));
+ writel(0x04030000, GPIO_PXPENS(0));
+#else
+ /* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
+ writel(0x0dff00ff, GPIO_PXINTC(0));
+ writel(0x0dff00ff, GPIO_PXMASKC(0));
+ writel(0x0dff00ff, GPIO_PXPAT1C(0));
+ writel(0x0dff00ff, GPIO_PXPAT0C(0));
+ writel(0x0d5ff00ff, GPIO_PXPENS(0));
+ writel(0x00000003, GPIO_PXINTC(1));
+ writel(0x00000003, GPIO_PXMASKC(1));
+ writel(0x00000003, GPIO_PXPAT1C(1));
+ writel(0x00000003, GPIO_PXPAT0C(1));
+ writel(0x00000003, GPIO_PXPENS(1));
+#endif
+
+ /* enable clocks */
+ writel(readl(CPM_CLKGR0) & ~CPM_CLKGR0_MAC, CPM_CLKGR0);
+ writel(readl(CPM_CLKGR0) & ~CPM_CLKGR0_NEMC, CPM_CLKGR0);
+
+ /* enable power (PB25) */
+ gpio_direction_output(32 * 1 + 25, 1);
+
+ /* reset (PF12) */
+ gpio_direction_output(32 * 5 + 12, 0);
+ udelay(10000);
+ gpio_set(32 * 5 + 12, 1);
+ udelay(10000);
+
+ return dm9000_initialize(bis);
+}
+
+#endif /* CONFIG_DRIVER_DM9000 */
+
+/* U-Boot common routines */
+int checkboard(void)
+{
+ puts("Board: ci20 (Ingenic XBurst JZ4780 SoC)\n");
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+void spl_board_init(void)
+{
+#if 0
+ /* set I2C pins low */
+ gpio_direction_output(32 * 3 + 30, 0); /* I2C0 SDA */
+ gpio_direction_output(32 * 4 + 31, 0); /* I2C1 SCL */
+ gpio_direction_output(32 * 5 + 17, 0); /* I2C2 SCL */
+ gpio_direction_output(32 * 4 + 13, 0); /* I2C4 SCL */
+#endif
+}
+
+#endif /* CONFIG_SPL_BUILD */
diff --git a/board/imgtec/ci20/config.mk b/board/imgtec/ci20/config.mk
new file mode 100644
index 000000000..50ad5c77f
--- /dev/null
+++ b/board/imgtec/ci20/config.mk
@@ -0,0 +1,29 @@
+#
+# CI20 configuration
+#
+# Copyright (c) 2013 Imagination Technologies
+# Author: Paul Burton <paul.burton@imgtec.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
diff --git a/boards.cfg b/boards.cfg
index 9fc77fb4d..18d631460 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -504,6 +504,8 @@ Active mips mips32 incaip - incaip
Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
+Active mips xburst jz4780 imgtec ci20 ci20 - Paul Burton <paul.burton@imgtec.com>
+Active mips xburst jz4780 imgtec ci20 ci20_mmc ci20:SPL_MMC_SUPPORT,ENV_IS_IN_MMC Paul Burton <paul.burton@imgtec.com>
Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
new file mode 100644
index 000000000..f283e5db7
--- /dev/null
+++ b/include/configs/ci20.h
@@ -0,0 +1,317 @@
+/*
+ * CI20 configuration
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_CI20_H__
+#define __CONFIG_CI20_H__
+
+/* Ingenic JZ4780 based, mips32r2el ISA */
+#define CONFIG_MIPS32
+#define CONFIG_SYS_LITTLE_ENDIAN
+#define CONFIG_JZSOC
+#define CONFIG_JZ4780
+
+#define CONFIG_SYS_CPU_SPEED 1200000000 /* CPU clock: 1.2 GHz */
+#define CONFIG_SYS_EXTAL 48000000 /* EXTAL freq: 48 MHz */
+#define CONFIG_SYS_HZ (CONFIG_SYS_EXTAL / 16) /* incrementer freq */
+#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
+
+#define CONFIG_SYS_DDR3_H5TQ2G83CFR
+#define CONFIG_SYS_MEM_SPEED CONFIG_SYS_CPU_SPEED
+#define CONFIG_SYS_MEM_DIV 3
+#define CONFIG_SYS_DDR3PHY_PULLUP_IMPEDANCE 0xe
+#define CONFIG_SYS_DDR3PHY_PULLDOWN_IMPEDANCE 0xe
+
+#define CONFIG_SYS_AUDIO_SPEED (768 * 1000000)
+
+/* define this if you require JTAG support */
+#undef CONFIG_JTAG
+
+/* NS16550-ish UARTs, uart[013] are accessible */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_EXTAL
+#define CONFIG_SYS_NS16550_COM1 0xb0030000 /* uart0 */
+#define CONFIG_SYS_NS16550_COM2 0xb0031000 /* uart1 */
+#define CONFIG_SYS_NS16550_COM4 0xb0033000 /* uart3 */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200, 230400 }
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE 0 /* init flash_base as 0 */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_MISC_INIT_R 1
+
+#define CONFIG_JZ4780_EFUSE 1
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAUL)
+
+#define CONFIG_BOOTDELAY 2
+#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+#define BOOTARGS_COMMON "console=ttyS0,115200 console=tty0 mem=256M@0x0 mem=768M@0x30000000"
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+
+/* SD/MMC card defaults */
+
+#define CONFIG_BOOTARGS \
+ BOOTARGS_COMMON " root=/dev/mmcblk0p1"
+#define CONFIG_BOOTCOMMAND \
+ "ext4load mmc 0:1 0x88000000 /boot/vmlinux.img; bootm 0x88000000"
+
+#else /* !CONFIG_SPL_MMC_SUPPORT */
+
+/* NAND defaults */
+
+#define CONFIG_BOOTARGS \
+ BOOTARGS_COMMON " ubi.mtd=1 root=ubi0:root rootfstype=ubifs rw"
+#define CONFIG_BOOTCOMMAND \
+ "mtdparts default; ubi part system; ubifsmount ubi:boot; " \
+ "ubifsload 0x88000000 vmlinux.img; bootm 0x88000000"
+
+#endif /* !CONFIG_SPL_MMC_SUPPORT */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "stdin=eserial0,eserial3\0" \
+ "stdout=eserial0,eserial3\0" \
+ "stderr=eserial0,eserial3\0"
+
+#define CONFIG_SYS_HUSH_PARSER
+
+/* NAND */
+#define CONFIG_NAND 1
+#define CONFIG_NAND_JZ4780 1
+#define CONFIG_SYS_NAND_BASE 0xbb000000
+#define CONFIG_SYS_NAND_ONFI_DETECTION 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_PAGE_SIZE 8192
+#define CONFIG_SYS_NAND_BLOCK_SIZE (2048 << 10)
+#define CONFIG_SYS_NAND_OOBSIZE 448
+#define CONFIG_SYS_NAND_ECCSIZE 1024
+#define CONFIG_SYS_NAND_ECCSTRENGTH 24
+#define CONFIG_SYS_NAND_ECCBYTES ((CONFIG_SYS_NAND_ECCSTRENGTH * 14) / 8)
+#define CONFIG_SYS_NAND_ECC_POS 112
+#define CONFIG_SYS_NAND_ECCPOS { \
+ 112, 113, 114, 115, 116, 117, 118, 119, \
+ 120, 121, 122, 123, 124, 125, 126, 127, \
+ 128, 129, 130, 131, 132, 133, 134, 135, \
+ 136, 137, 138, 139, 140, 141, 142, 143, \
+ 144, 145, 146, 147, 148, 149, 150, 151, \
+ 152, 153, 154, 155, 156, 157, 158, 159, \
+ 160, 161, 162, 163, 164, 165, 166, 167, \
+ 168, 169, 170, 171, 172, 173, 174, 175, \
+ 176, 177, 178, 179, 180, 181, 182, 183, \
+ 184, 185, 186, 187, 188, 189, 190, 191, \
+ 192, 193, 194, 195, 196, 197, 198, 199, \
+ 200, 201, 202, 203, 204, 205, 206, 207, \
+ 208, 209, 210, 211, 212, 213, 214, 215, \
+ 216, 217, 218, 219, 220, 221, 222, 223, \
+ 224, 225, 226, 227, 228, 229, 230, 231, \
+ 232, 233, 234, 235, 236, 237, 238, 239, \
+ 240, 241, 242, 243, 244, 245, 246, 247, \
+ 248, 249, 250, 251, 252, 253, 254, 255, \
+ 256, 257, 258, 259, 260, 261, 262, 263, \
+ 264, 265, 266, 267, 268, 269, 270, 271, \
+ 272, 273, 274, 275, 276, 277, 278, 279, \
+ 280, 281, 282, 283, 284, 285, 286, 287, \
+ 288, 289, 290, 291, 292, 293, 294, 295, \
+ 296, 297, 298, 299, 300, 301, 302, 303, \
+ 304, 305, 306, 307, 308, 309, 310, 311, \
+ 312, 313, 314, 315, 316, 317, 318, 319, \
+ 320, 321, 322, 323, 324, 325, 326, 327, \
+ 328, 329, 330, 331, 332, 333, 334, 335, \
+ 336, 337, 338, 339, 340, 341, 342, 343, \
+ 344, 345, 346, 347, 348, 349, 350, 351, \
+ 352, 353, 354, 355, 356, 357, 358, 359, \
+ 360, 361, 362, 363, 364, 365, 366, 367, \
+ 368, 369, 370, 371, 372, 373, 374, 375, \
+ 376, 377, 378, 379, 380, 381, 382, 383, \
+ 384, 385, 386, 387, 388, 389, 390, 391, \
+ 392, 393, 394, 395, 396, 397, 398, 399, \
+ 400, 401, 402, 403, 404, 405, 406, 407, \
+ 408, 409, 410, 411, 412, 413, 414, 415, \
+ 416, 417, 418, 419, 420, 421, 422, 423, \
+ 424, 425, 426, 427, 428, 429, 430, 431, \
+ 432, 433, 434, 435, 436, 437, 438, 439, \
+ 440, 441, 442, 443, 444, 445, 446, 447 }
+#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST 1
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE 1
+#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=nand"
+#define MTDPARTS_DEFAULT "mtdparts=nand:8m(uboot-spl),2m(uboot),2m(uboot-env),-(system)"
+
+/*
+ * MMC
+ */
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_JZ_MMC 1
+#define CONFIG_JZ_MMC_MSC1 1
+#define CONFIG_JZ_MMC_SPLMSC 1
+
+/* Ethernet: davicom DM9000 */
+#define CONFIG_DRIVER_DM9000 1
+#define CONFIG_DM9000_BASE 0xb6000000
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_DHCP /* DHCP support */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_EXT4 /* ext4 support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#define CONFIG_CMD_MMC /* MMC/SD support */
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_LOCK_UNLOCK
+#define CONFIG_CMD_NET /* networking support */
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SAVEENV /* saveenv */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_SOURCE /* "source" command support */
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+
+/*
+ * Serial download configuration
+ */
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "ci20# "
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
+#define CONFIG_SYS_SDRAM_MAX_TOP 0x90000000 /* don't run into IO space */
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+#define CONFIG_SYS_LOAD_ADDR 0x88000000
+#define CONFIG_SYS_MEMTEST_START 0x80000000
+#define CONFIG_SYS_MEMTEST_END 0x88000000
+
+#define CONFIG_SYS_TEXT_BASE 0x80000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+/*
+ * Environment
+ */
+#ifdef CONFIG_ENV_IS_IN_MMC
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE (32 << 10)
+#define CONFIG_ENV_OFFSET ((14 + 512) << 10)
+
+#else
+
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE (32 << 10)
+#define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_BLOCK_SIZE * 5)
+
+#endif
+
+/*
+ * SDRAM Info.
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 32768
+#define CONFIG_SYS_ICACHE_SIZE 32768
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_STACK 0xf4004000 /* only max. 2KB spare! */
+
+#define CONFIG_SPL_BSS_START_ADDR 0x8f000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512KB, arbitrary */
+
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/jz4780/u-boot-spl.lds"
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14KB offset */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 /* 512 KB */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (CONFIG_SYS_NAND_BLOCK_SIZE * 4)
+#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+
+#ifdef CONFIG_SPL_MMC_SUPPORT
+
+#define CONFIG_SPL_TEXT_BASE 0xf4000a00
+#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
+
+#else /* !CONFIG_SPL_MMC_SUPPORT */
+
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+
+#define CONFIG_SPL_TEXT_BASE 0xf4000800
+#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0x800)
+
+/* the NAND SPL is small enough to enable serial */
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+#endif /* !CONFIG_SPL_MMC_SUPPORT */
+
+#endif /* __CONFIG_CI20_H__ */