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authorZubairLK <ZubairLK@users.noreply.github.com>2015-08-19 12:20:43 +0300
committerZubairLK <ZubairLK@users.noreply.github.com>2015-08-19 12:20:43 +0300
commitb07a6684eae9c680f205e216943dfc2d8e57a3f1 (patch)
tree5499279fb814e0b7a6854443d2f54f1b93e01a2a
parent040103141210f8e84049d203d0043f2f6b362f6b (diff)
parentbed765e054fe8a3b42562453e3f99939d872e21e (diff)
downloadCI20_u-boot-b07a6684eae9c680f205e216943dfc2d8e57a3f1.tar.xz
Merge pull request #7 from mpredfearn/ci20-v2013.10-revision-detect
Ci20 v2013.10 revision detect
-rw-r--r--arch/mips/cpu/xburst/jz4780/sdram.c294
-rwxr-xr-xarch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h66
-rw-r--r--arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h149
-rw-r--r--arch/mips/cpu/xburst/jz4780/sdram/ddr_parameters.h73
-rw-r--r--board/imgtec/ci20/ci20.c14
-rw-r--r--include/configs/ci20.h5
6 files changed, 367 insertions, 234 deletions
diff --git a/arch/mips/cpu/xburst/jz4780/sdram.c b/arch/mips/cpu/xburst/jz4780/sdram.c
index 953a50dc0..b5cedf63b 100644
--- a/arch/mips/cpu/xburst/jz4780/sdram.c
+++ b/arch/mips/cpu/xburst/jz4780/sdram.c
@@ -29,14 +29,17 @@
#ifdef __CONFIG_CI20_H__
/* Configured for Ci20 - we can get the board revision from here */
-extern int ci20_revision;
+extern int ci20_revision(void);
#endif /* ci20 */
#ifdef CONFIG_SYS_DDR3_H5TQ2G83CFR
#include "sdram/H5TQ2G83CFR.h"
#endif
+#ifdef CONFIG_SYS_DDR3_K4B2G0846Q
+#include "sdram/K4B2G0846Q.h"
+#endif
-static uint32_t get_mem_clk(void)
+static const uint32_t get_mem_clk(void)
{
uint32_t mpll_out;
mpll_out = (uint64_t)CONFIG_SYS_EXTAL * JZ4780_MPLL_M / (JZ4780_MPLL_N * JZ4780_MPLL_OD);
@@ -85,90 +88,32 @@ static void ddr_cfg_init(void)
writel(ddrc_cfg, DDRC_CFG);
}
-#define DDRP_PTR0_tDLLSRST 50 // 50ns
-#define DDRP_tDLLLOCK 5120 // 5.12us
-#define DDRP_PTR0_ITMSRST_8 8 // 8tck
-#define DDRP_PTR1_DINIT0_DDR3 500 * 1000 // 500us
-#define DDRP_PTR2_DINIT2_DDR3 200 * 1000 // 200us
-#define DDRP_PTR2_DINIT3_DDR3 512 // 512 tck
+#define DDRP_PTR0_tDLLSRST 50 /* 50ns */
+#define DDRP_tDLLLOCK 5120 /* 5.12us */
+#define DDRP_PTR0_ITMSRST_8 8 /* 8tck */
+#define DDRP_PTR1_DINIT0_DDR3 500 * 1000 /* 500us */
+#define DDRP_PTR2_DINIT2_DDR3 200 * 1000 /* 200us */
+#define DDRP_PTR2_DINIT3_DDR3 512 /* 512 tck */
-static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg)
+static void ddr_phy_init(const struct jz4780_ddr_config *ddr_config)
{
register unsigned int tmp;
- unsigned int ptr0_reg = 0, ptr1_reg = 0, ptr2_reg = 0, dtpr1_reg = 0, dtpr2_reg = 0;
- unsigned int count = 0, dinit1 = 0, i;
+ unsigned int count = 0, i;
writel(DDRP_DCR_TYPE_DDR3 | (DDR_BANK8 << 3), DDRP_DCR);
- tmp = DIV_ROUND_UP(DDR_tWR * 1000, ps);
- if (tmp < 5)
- tmp = 5;
- if (tmp > 12)
- tmp = 12;
- if (tmp <= 8)
- tmp -= 4;
- else
- tmp = (tmp + 1) / 2;
-
- /* BL 8 = 0, 0x410 */
- writel(tmp << DDR3_MR0_WR_BIT | (DDR_CL - 4) << 4 | ((8 - DDR_BL) / 2), DDRP_MR0);
-#ifdef SDRAM_DISABLE_DLL
- writel(DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE, DDRP_MR1);
-#else
- writel(DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS, DDRP_MR1);
-#endif
+ writel(ddr_config->mr0, DDRP_MR0);
+ writel(ddr_config->mr1, DDRP_MR1);
writel(0, DDRP_ODTCR);
- writel((DDR_tCWL - 5) << DDR3_MR2_CWL_BIT, DDRP_MR2);
-
- /* DLL Soft Rest time */
- ptr0_reg |= min(DIV_ROUND_UP(DDRP_PTR0_tDLLSRST * 1000, ps), 63);
- /* DLL Lock time */
- ptr0_reg |= min(DIV_ROUND_UP(DDRP_tDLLLOCK, ps), 0xfff) << 6;
- ptr0_reg |= DDRP_PTR0_ITMSRST_8 << 18;
- writel(ptr0_reg, DDRP_PTR0);
-
- ptr1_reg |= min(DIV_ROUND_UP(DDRP_PTR1_DINIT0_DDR3 * 1000, ps), 0x7ffff);
- if (((DDR_tRFC + 10) * 1000) > (5 * ps)) //ddr3 only
- dinit1 = (DDR_tRFC + 10) * 1000;
- else
- dinit1 = 5 * ps;
- ptr1_reg |= min(DIV_ROUND_UP(dinit1, ps), 0xff) << 19;
- writel(ptr1_reg, DDRP_PTR1);
-
- ptr2_reg |= min(DIV_ROUND_UP(DDRP_PTR2_DINIT2_DDR3 * 1000, ps), 0x1ffff);
- ptr2_reg |= min(DDRP_PTR2_DINIT3_DDR3, 0x3ff) << 17;
- writel(ptr2_reg, DDRP_PTR2);
-
- dtpr0_reg |= (DDR_tMRD - 4); // valid values: 4 - 7
- if (DDR_tCCD > 4)
- dtpr0_reg |= 1 << 31;
- writel(dtpr0_reg, DDRP_DTPR0);
-
- dtpr1_reg |= min(max(DIV_ROUND_UP(DDR_tFAW * 1000, ps), 2), 31) << 3;
- dtpr1_reg |= min(max(DIV_ROUND_UP(DDR_tRFC * 1000, ps), 1), 255) << 16;
- dtpr1_reg |= min(DIV_ROUND_UP(DDR_tMOD * 1000, ps) - 12, 3) << 9;
- dtpr1_reg |= (1 << 11); /* ODT may not be turned on until one clock after the read post-amble */
- writel(dtpr1_reg, DDRP_DTPR1);
-
- tmp = (DDR_tXS > DDR_tXSDLL) ? DDR_tXS : DDR_tXSDLL; //only ddr3
- tmp = DIV_ROUND_UP(tmp * 1000, ps);
- if (tmp < 2) tmp = 2;
- if (tmp > 1023) tmp = 1023;
- dtpr2_reg |= tmp;
- tmp = (DDR_tXP > DDR_tXPDLL) ? DDR_tXP : DDR_tXPDLL;
- tmp = DIV_ROUND_UP(tmp * 1000, ps);
- if (tmp < 2) tmp = 2;
- if (tmp > 31) tmp = 31;
- dtpr2_reg |= tmp << 10;
- tmp = DDR_tCKE;
- if (tmp < 2) tmp = 2;
- if (tmp > 15) tmp = 15;
- dtpr2_reg |= tmp << 15;
- tmp = DDR_tDLLLOCK;
- if (tmp < 2) tmp = 2;
- if (tmp > 1023) tmp = 1023;
- dtpr2_reg |= tmp << 19;
- writel(dtpr2_reg, DDRP_DTPR2);
+ writel(0, DDRP_MR2);
+
+ writel(ddr_config->ptr0, DDRP_PTR0);
+ writel(ddr_config->ptr1, DDRP_PTR1);
+ writel(ddr_config->ptr2, DDRP_PTR2);
+
+ writel(ddr_config->dtpr0, DDRP_DTPR0);
+ writel(ddr_config->dtpr1, DDRP_DTPR1);
+ writel(ddr_config->dtpr2, DDRP_DTPR2);
writel(DDRP_PGCR_DQSCFG |
7 << DDRP_PGCR_CKEN_BIT |
@@ -187,6 +132,19 @@ static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg)
hang();
}
+ /* DQS extension and early set to 1 */
+ tmp = readl(DDRP_DSGCR);
+ tmp &= ~(0x7E << 4);
+ tmp |= 0x12 << 4;
+ writel(tmp, DDRP_DSGCR);
+
+ /* 500 pull up and 500 pull down */
+ tmp = readl(DDRP_DXCCR);
+ tmp &= ~(0xFF << 4);
+ tmp |= 0xC4 << 4;
+ writel(tmp, DDRP_DXCCR);
+
+ /* Initialise phy */
writel(DDRP_PIR_INIT | DDRP_PIR_DRAMINT | DDRP_PIR_DRAMRST, DDRP_PIR);
count = 0;
@@ -207,6 +165,7 @@ static void ddr_phy_init(unsigned long ps, unsigned int dtpr0_reg)
}
}
+ /* Override impedence */
tmp = readl(DDRP_ZQXCR0(0));
tmp &= ~0x3ff;
tmp |= (CONFIG_SYS_DDR3PHY_PULLUP_IMPEDANCE & 0x1f) <<
@@ -259,20 +218,46 @@ static void mem_remap(void)
void sdram_init(void)
{
+ int board_revision;
uint32_t mem_clk, ps, tmp;
uint32_t ddrc_timing1 = 0, ddrc_timing2 = 0, ddrc_timing3 = 0;
uint32_t ddrc_timing4 = 0, ddrc_timing5 = 0, ddrc_timing6 = 0;
uint32_t ddrc_refcnt = 0;
- uint32_t ddrp_dtpr0 = 0;
uint32_t mem_base0, mem_base1;
uint32_t mem_mask0, mem_mask1;
uint32_t mem_size0, mem_size1;
+ const struct jz4780_ddr_config *ddr_config;
+
+ board_revision = ci20_revision();
+
+ if (board_revision == 2)
+#ifdef CONFIG_SYS_DDR3_K4B2G0846Q
+#if CONFIG_SYS_CPU_SPEED == 1200000000 && CONFIG_SYS_EXTAL == 48000000
+ ddr_config = &K4B2G0846Q_48_config;
+#else
+#error No DDR configuration for CPU speed
+#endif
+#else
+#error K4B2G0846Q support disabled
+#endif
+ else /* Fall back to H5TQ2G83CFR RAM */
+#ifdef CONFIG_SYS_DDR3_H5TQ2G83CFR
+#if CONFIG_SYS_CPU_SPEED == 1200000000 && CONFIG_SYS_EXTAL == 48000000
+ ddr_config = &H5TQ2G83CFR_48_config;
+#else
+#error No DDR configuration for CPU speed
+#endif
+#else
+#error H5TQ2G83CFR support disabled
+#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
- puts("SDRAM " SDRAM_PART_NAME " initialization...");
+ puts("SDRAM ");
+ puts(ddr_config->name);
+ puts(" initialization...\n");
#endif
- /* ??? */
+ /* Reset DLL in DDR PHY */
writel(0x3, 0xb00000d0);
udelay(400000);
writel(0x1, 0xb00000d0);
@@ -284,143 +269,12 @@ void sdram_init(void)
mem_clk = get_mem_clk();
ps = 1000000000 / (mem_clk / 1000); /* ns per tck ns <= real value , ns * 1000*/
- /* READ to PRECHARGE command period. */
- tmp = DIV_ROUND_UP(DDR_tRTP * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 6) tmp = 6;
- ddrc_timing1 |= (tmp << DDRC_TIMING1_TRTP_BIT);
- if (tmp < 2) tmp = 2;
- ddrp_dtpr0 |= tmp << 2;
-
- tmp = DIV_ROUND_UP(DDR_tWTR * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 6) tmp = 6;
- ddrc_timing1 |= ((DDR_tWL + DDR_BL / 2 + tmp) << DDRC_TIMING1_TWTR_BIT);
- ddrp_dtpr0 |= tmp << 5;
-
- /* WRITE Recovery Time defined by register MR of DDR3 memory */
- tmp = DIV_ROUND_UP(DDR_tWR * 1000, ps);
- if (tmp < 5) tmp = 5;
- if (tmp > 12) tmp = 12;
- ddrc_timing1 |= (tmp << DDRC_TIMING1_TWR_BIT);
- /* Write latency: dif ddr dif tWL, unit - tCK*/
- tmp = DDR_tWL;
- if (tmp < 1) tmp = 1;
- if (tmp > 63) tmp = 63;
- ddrc_timing1 |= (tmp << DDRC_TIMING1_TWL_BIT);
-
- /* CAS to CAS command delay , unit - tCK*/
- tmp = DDR_tCCD;
- if (tmp < 1) tmp = 1;
- if (tmp > 63) tmp = 63;
- ddrc_timing2 |= (tmp << DDRC_TIMING2_TCCD_BIT);
-
- /* ACTIVE to PRECHARGE command period */
- tmp = DIV_ROUND_UP(DDR_tRAS * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 31) tmp = 31;
- ddrc_timing2 |= (tmp << DDRC_TIMING2_TRAS_BIT);
- if (tmp < 2) tmp = 2;
- ddrp_dtpr0 |= tmp << 16;
-
- /* ACTIVE to READ or WRITE command period. */
- tmp = DIV_ROUND_UP(DDR_tRCD * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 11) tmp = 11;
- ddrc_timing2 |= (tmp << DDRC_TIMING2_TRCD_BIT);
- if (tmp < 2) tmp = 2;
- ddrp_dtpr0 |= tmp << 12;
-
- /* Read latency , unit tCK*/
- tmp = DDR_tRL;
- if (tmp < 1) tmp = 1;
- if (tmp > 63) tmp = 63;
- ddrc_timing2 |= (tmp << DDRC_TIMING2_TRL_BIT);
-
- ddrc_timing3 |= (4 << DDRC_TIMING3_ONUM);
-
- tmp = DIV_ROUND_UP(DDR_tCKSRE * 1000, ps) / 8;
- if (tmp < 1) tmp = 1;
- if (tmp > 7) tmp = 7;
- /*
- * Set DDR_tCKSRE to max to ensafe suspend & resume
- */
- tmp = 7;
- ddrc_timing3 |= (tmp << DDRC_TIMING3_TCKSRE_BIT);
-
- /* PRECHARGE command period. */
- tmp = DIV_ROUND_UP(DDR_tRP * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 11) tmp = 11;
- ddrc_timing3 |= (tmp << DDRC_TIMING3_TRP_BIT);
- if (tmp < 2) tmp = 2;
- ddrp_dtpr0 |= tmp << 8;
-
- /* ACTIVE bank A to ACTIVE bank B command period. */
- tmp = DIV_ROUND_UP(DDR_tRRD * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 8) tmp = 8;
- ddrc_timing3 |= (tmp << DDRC_TIMING3_TRRD_BIT);
- ddrp_dtpr0 |= tmp << 21;
-
- /* ACTIVE to ACTIVE command period. */
- tmp = DIV_ROUND_UP(DDR_tRC * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 42) tmp = 42;
- ddrc_timing3 |= (tmp << DDRC_TIMING3_TRC_BIT);
- if (tmp < 2) tmp = 2;
- ddrp_dtpr0 |= tmp << 25;
-
- /* AUTO-REFRESH command period. */
- tmp = DIV_ROUND_UP(DDR_tRFC * 1000, ps) - 1;
- tmp = tmp / 2;
- if (tmp < 1) tmp = 1;
- if (tmp > 63) tmp = 63;
- ddrc_timing4 |= (tmp << DDRC_TIMING4_TRFC_BIT);
-
- /* RWCOV: */
- tmp = 1;
- ddrc_timing4 |= (tmp << DDRC_TIMING4_TRWCOV_BIT);
-
- tmp = DIV_ROUND_UP(DDR_tCKE * 1000, ps);
- ddrc_timing4 |= (tmp << DDRC_TIMING4_TCKE_BIT);
-
- /* Minimum Self-Refresh / Deep-Power-Down time */
- tmp = DDR_tMINSR;
- if (tmp < 9) tmp = 9; //unit: tCK
- if (tmp > 129) tmp = 129;
- tmp = ((tmp - 1) % 8) ? ((tmp - 1) / 8) : ((tmp - 1) / 8 - 1);
- ddrc_timing4 |= (tmp << DDRC_TIMING4_TMINSR_BIT);
- ddrc_timing4 |= (DDR_tXP << DDRC_TIMING4_TXP_BIT) | (DDR_tMRD - 1);
-
- /* RTW: read to write*/
- tmp = DDR_tRTW;
- if (tmp < 1) tmp = 1;
- if (tmp > 63) tmp = 63;
- ddrc_timing5 |= (tmp << DDRC_TIMING5_TRTW_BIT);
-
- /* trdlat: */
- tmp = DDR_tRDLAT;
- if (tmp > 63) tmp = 63;
- ddrc_timing5 |= (tmp << DDRC_TIMING5_TRDLAT_BIT);
-
- /* twdlat: */
- tmp = DDR_tWDLAT;
- if (tmp > 63) tmp = 63;
- ddrc_timing5 |= (tmp << DDRC_TIMING5_TWDLAT_BIT);
-
- tmp = DDR_tXSRD / 4;
- if (tmp < 1) tmp = 1;
- if (tmp > 255) tmp = 255;
- ddrc_timing6 |= (tmp << DDRC_TIMING6_TXSRD_BIT);
-
- /* FAW: Four bank activate period - tCK */
- tmp = DIV_ROUND_UP(DDR_tFAW * 1000, ps);
- if (tmp < 1) tmp = 1;
- if (tmp > 31) tmp = 31;
- ddrc_timing6 |= (tmp << DDRC_TIMING6_TFAW_BIT);
- ddrc_timing6 |= (2 << DDRC_TIMING6_TCFGW_BIT);
- ddrc_timing6 |= (2 << DDRC_TIMING6_TCFGR_BIT);
+ ddrc_timing1 = ddr_config->timing1;
+ ddrc_timing2 = ddr_config->timing2;
+ ddrc_timing3 = ddr_config->timing3;
+ ddrc_timing4 = ddr_config->timing4;
+ ddrc_timing5 = ddr_config->timing5;
+ ddrc_timing6 = ddr_config->timing6;
ddrc_refcnt = DDR_CLK_DIV << 1 | DDRC_REFCNT_REF_EN;
tmp = (1000000000 % mem_clk == 0) ? (1000000000 / mem_clk) : (1000000000 / mem_clk + 1);
@@ -436,7 +290,7 @@ void sdram_init(void)
writel(0x0, DDRC_CTRL);
writel(0x150000, DDRP_DTAR);
- ddr_phy_init(ps, ddrp_dtpr0);
+ ddr_phy_init(ddr_config);
writel(DDRC_CTRL_CKE | DDRC_CTRL_ALH, DDRC_CTRL);
writel(0x0, DDRC_CTRL);
diff --git a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
index c9a0a6d78..6fc6541d3 100755
--- a/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
+++ b/arch/mips/cpu/xburst/jz4780/sdram/H5TQ2G83CFR.h
@@ -1,5 +1,7 @@
-#ifndef __DDR3_CONFIG_H
-#define __DDR3_CONFIG_H
+#ifndef __DDR3_H5TQ2G83CFR_CONFIG_H
+#define __DDR3_H5TQ2G83CFR_CONFIG_H
+
+#if 0
#define SDRAM_PART_NAME "H5TQ2G83CFR"
#define SDRAM_TYPE_DDR3
@@ -70,7 +72,7 @@
#define DDR_tWL (DDR_tAL + DDR_tCWL) /* DDR3: Write Latency = tAL + tCWL */
#define DDR_tRDLAT (DDR_tRL - 2)
#define DDR_tWDLAT (DDR_tWL - 1)
-#define DDR_tRTW (DDR_tRL + DDR_tCCD + 2 - DDR_tWL) /* Read to Write delay */
+#define DDR_tRTW (DDR_tRL + DDR_tCCD + 2 - DDR_tWL + 1) /* Read to Write delay */
#define DDR_tCKSRE DDR_MAX(5, 10000) /* Valid Clock Requirement after Self Refresh Entry or Power-Down Entry */
#define DDR_tDLLLOCK 512 /* DDR3 only: DLL LOCK, tck */
@@ -87,5 +89,61 @@
#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh
* cnt_clk = memclk/(16*(2^DDR_CLK_DIV))
*/
+#endif
+
+#include "ddr_parameters.h"
+
+static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
+ .name = "H5TQ2G83CFR",
+
+ .timing1 = ( (4 << DDRC_TIMING1_TRTP_BIT) |
+ (13 << DDRC_TIMING1_TWTR_BIT) |
+ (6 << DDRC_TIMING1_TWR_BIT) |
+ (5 << DDRC_TIMING1_TWL_BIT)),
+
+ .timing2 = ( (4 << DDRC_TIMING2_TCCD_BIT) |
+ (16 << DDRC_TIMING2_TRAS_BIT) |
+ (6 << DDRC_TIMING2_TRCD_BIT) |
+ (6 << DDRC_TIMING2_TRL_BIT)),
+
+ .timing3 = ( (4 << DDRC_TIMING3_ONUM) |
+ (7 << DDRC_TIMING3_TCKSRE_BIT) |
+ (6 << DDRC_TIMING3_TRP_BIT) |
+ (4 << DDRC_TIMING3_TRRD_BIT) |
+ (22 << DDRC_TIMING3_TRC_BIT)),
+
+ .timing4 = ( (42 << DDRC_TIMING4_TRFC_BIT) |
+ (1 << DDRC_TIMING4_TRWCOV_BIT) |
+ (4 << DDRC_TIMING4_TCKE_BIT) |
+ (7 << DDRC_TIMING4_TMINSR_BIT) |
+ (3 << DDRC_TIMING4_TXP_BIT) |
+ (3 << DDRC_TIMING4_TMRD_BIT)),
+
+ .timing5 = ( (8 << DDRC_TIMING5_TRTW_BIT) |
+ (4 << DDRC_TIMING5_TRDLAT_BIT) |
+ (4 << DDRC_TIMING5_TWDLAT_BIT)),
+
+ .timing6 = ( (25 << DDRC_TIMING6_TXSRD_BIT) |
+ (20 << DDRC_TIMING6_TFAW_BIT) |
+ (2 << DDRC_TIMING6_TCFGW_BIT) |
+ (2 << DDRC_TIMING6_TCFGR_BIT)),
+ /* PHY */
+
+ /* Mode Register 0 */
+ .mr0 = (0x00000420),
+#ifdef SDRAM_DISABLE_DLL
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+ .ptr0 = 0x002000d4,
+ .ptr1 = 0x02d30d40,
+ .ptr2 = 0x04013880,
+
+ .dtpr0 = 0x2c906690,
+ .dtpr1 = 0x005608a0,
+ .dtpr2 = 0x10042a00,
+};
-#endif /* __DDR3_CONFIG_H */
+#endif /* __DDR3_H5TQ2G83CFR_CONFIG_H */
diff --git a/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h b/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h
new file mode 100644
index 000000000..ab4df221e
--- /dev/null
+++ b/arch/mips/cpu/xburst/jz4780/sdram/K4B2G0846Q.h
@@ -0,0 +1,149 @@
+#ifndef __DDR3_K4B2G0846Q_CONFIG_H
+#define __DDR3_K4B2G0846Q_CONFIG_H
+
+#if 0
+
+#define SDRAM_PART_NAME "K4B2G0846Q"
+#define SDRAM_TYPE_DDR3
+
+#define DDR_MAX(tck, time) \
+({ \
+ unsigned long value; \
+ value = (tck * ps > time) ? (tck * ps) : time; \
+ value = (value % 1000 == 0) ? (value / 1000) : (value / 1000 + 1); \
+ value; \
+})
+
+/*
+ * This file contains the memory configuration parameters for the cygnus board.
+ */
+/*--------------------------------------------------------------------------------
+ * DDR3-1066 info
+ */
+/* Chip Select */
+#define DDR_CS1EN 0 /* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
+#define DDR_CS0EN 1
+#define DDR_DW32 1 /* 0 - 16-bit data width, 1 - 32-bit data width */
+//#define SDRAM_DISABLE_DLL
+
+/* DDR3 paramters */
+//2 chip
+//#define DDR_ROW 14 /* ROW : 12 to 18 row address ,1G only 512MB*/
+//4chip
+#define DDR_ROW 15 /* ROW : 12 to 18 row address ,1G only 512MB*/
+#define DDR_COL 10 /* COL : 8 to 14 column address */
+#define DDR_BANK8 1 /* Banks each chip: 0-4bank, 1-8bank */
+
+#ifdef SDRAM_DISABLE_DLL
+#define DDR_CL 6 /* dll off */
+#define DDR_tCWL 6 /* DDR3 dll off*/
+#else
+#define DDR_CL 6 /* CAS latency: 5 to 14 ,tCK*/
+#define DDR_tCWL (DDR_CL - 1) /* DDR3 only: CAS Write Latency, 5 to 8 */
+#endif
+
+/*
+ * DDR3 controller timing1 register
+ */
+#define DDR_tRAS 37 /* tRAS: ACTIVE to PRECHARGE command period to the same bank. ns*/
+#define DDR_tRP 15 /* tRP: PRECHARGE command period to the same bank. ns*/
+#define DDR_tRCD 15 /* ACTIVE to READ or WRITE command period to the same bank. ns*/
+#define DDR_tRC 52 /* ACTIVE to ACTIVE command period to the same bank. ns*/
+#define DDR_tWR 15 /* WRITE Recovery Time defined by register MR of DDR2 memory, ns*/
+#define DDR_tRRD DDR_MAX(4, 6000) /* ACTIVE bank A to ACTIVE bank B command period. DDR3 - tCK*/
+#define DDR_tRTP DDR_MAX(4, 7500) /* READ to PRECHARGE command period. DDR3 spec no. 7.5ns*/
+#define DDR_tWTR DDR_MAX(4, 7500) /* WRITE to READ command delay. DDR3 spec no. 7.5 ns*/
+
+/*
+ * DDR3 controller timing2 register
+ */
+#define DDR_tRFC 160 /* AUTO-REFRESH command period. DDR3 - ns*/
+#define DDR_tMINSR 80 /* Minimum Self-Refresh / Deep-Power-Down . DDR3 no*/
+#define DDR_tXP DDR_MAX(3, 6000) /* DDR3 only: Exit active power down to any valid command, ns*/
+#define DDR_tMRD 4 /* unit: tCK. Load-Mode-Register to next valid command period: DDR3 rang 4 to 7 tCK. DDR3 spec no */
+
+/* new add */
+#define DDR_BL 8 /* DDR3 Burst length: 0 - 8 burst, 2 - 4 burst , 1 - 4 or 8(on the fly)*/
+#define DDR_tAL 0 /* Additive Latency, tCK*/
+#define DDR_tCCD 4 /* CAS# to CAS# command delay , tCK. 4 or 5 */
+#define DDR_tFAW 30 /* Four bank activate period, DDR3 - tCK */
+#define DDR_tCKE DDR_MAX(3, 5000) /* CKE minimum pulse width, DDR3 spec no, tCK */
+#define DDR_tRL (DDR_tAL + DDR_CL) /* DDR3: Read Latency = tAL + tCL */
+#define DDR_tWL (DDR_tAL + DDR_tCWL) /* DDR3: Write Latency = tAL + tCWL */
+#define DDR_tRDLAT (DDR_tRL - 2)
+#define DDR_tWDLAT (DDR_tWL - 1)
+#define DDR_tRTW (DDR_tRL + DDR_tCCD + 2 - DDR_tWL + 1) /* Read to Write delay */
+#define DDR_tCKSRE DDR_MAX(5, 10000) /* Valid Clock Requirement after Self Refresh Entry or Power-Down Entry */
+
+#define DDR_tDLLLOCK 512 /* DDR3 only: DLL LOCK, tck */
+#define DDR_tXSDLL DDR_MAX(DDR_tDLLLOCK, 0) /* DDR3 only: EXit self-refresh to command requiring a locked DLL, tck*/
+#define DDR_tMOD DDR_MAX(12, 15 * 1000) /* DDR3 only: Mode Register Set Command update delay*/
+#define DDR_tXPDLL DDR_MAX(10, 24 * 1000) /* DDR3 only: Exit active power down to command requirint a locked DLL, ns*/
+#define DDR_tXS DDR_MAX(5, (DDR_tRFC + 10) * 1000) /* DDR3 only: EXit self-refresh to command not requiring a locked DLL, ns*/
+#define DDR_tXSRD 100 /* DDR2 only: Exit self refresh to a read command, tck */
+
+/*
+ * DDR3 controller refcnt register
+ */
+#define DDR_tREFI 7800 /* Refresh period: 64ms / 32768 = 1.95 us , 2 ^ 15 = 32768 */
+#define DDR_CLK_DIV 1 /* Clock Divider. auto refresh
+ * cnt_clk = memclk/(16*(2^DDR_CLK_DIV))
+ */
+#endif
+
+#include "ddr_parameters.h"
+
+
+static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
+ .name = "K4B2G0846Q",
+
+ .timing1 = ( (4 << DDRC_TIMING1_TRTP_BIT) |
+ (13 << DDRC_TIMING1_TWTR_BIT) |
+ (6 << DDRC_TIMING1_TWR_BIT) |
+ (5 << DDRC_TIMING1_TWL_BIT)),
+
+ .timing2 = ( (4 << DDRC_TIMING2_TCCD_BIT) |
+ (15 << DDRC_TIMING2_TRAS_BIT) |
+ (6 << DDRC_TIMING2_TRCD_BIT) |
+ (6 << DDRC_TIMING2_TRL_BIT)),
+
+ .timing3 = ( (4 << DDRC_TIMING3_ONUM) |
+ (7 << DDRC_TIMING3_TCKSRE_BIT) |
+ (6 << DDRC_TIMING3_TRP_BIT) |
+ (4 << DDRC_TIMING3_TRRD_BIT) |
+ (21 << DDRC_TIMING3_TRC_BIT)),
+
+ .timing4 = ( (31 << DDRC_TIMING4_TRFC_BIT) |
+ (1 << DDRC_TIMING4_TRWCOV_BIT) |
+ (4 << DDRC_TIMING4_TCKE_BIT) |
+ (9 << DDRC_TIMING4_TMINSR_BIT) |
+ (8 << DDRC_TIMING4_TXP_BIT) |
+ (3 << DDRC_TIMING4_TMRD_BIT)),
+
+ .timing5 = ( (8 << DDRC_TIMING5_TRTW_BIT) |
+ (4 << DDRC_TIMING5_TRDLAT_BIT) |
+ (4 << DDRC_TIMING5_TWDLAT_BIT)),
+
+ .timing6 = ( (25 << DDRC_TIMING6_TXSRD_BIT) |
+ (12 << DDRC_TIMING6_TFAW_BIT) |
+ (2 << DDRC_TIMING6_TCFGW_BIT) |
+ (2 << DDRC_TIMING6_TCFGR_BIT)),
+ /* PHY */
+
+ /* Mode Register 0 */
+ .mr0 = (0x00000420),
+#ifdef SDRAM_DISABLE_DLL
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
+#else
+ .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
+#endif
+
+ .ptr0 = 0x002000d4,
+ .ptr1 = 0x02230d40,
+ .ptr2 = 0x04013880,
+
+ .dtpr0 = 0x2a8f6690,
+ .dtpr1 = 0x00400860,
+ .dtpr2 = 0x10042a00,
+};
+#endif /* __DDR3_K4B2G0846Q_CONFIG_H */
diff --git a/arch/mips/cpu/xburst/jz4780/sdram/ddr_parameters.h b/arch/mips/cpu/xburst/jz4780/sdram/ddr_parameters.h
new file mode 100644
index 000000000..68936b9ec
--- /dev/null
+++ b/arch/mips/cpu/xburst/jz4780/sdram/ddr_parameters.h
@@ -0,0 +1,73 @@
+/*
+ * JZ4780 DDR initialization - parameters definitions
+ *
+ * Copyright (c) 2015 Imagination Technologies
+ * Author: Matt Redfearn <matt.redfearn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __DDR_PARAMETERS_H
+#define __DDR_PARAMETERS_H
+
+
+/* Paramters common to all RAM devices used */
+
+/* Chip Select */
+#define DDR_CS0EN 1 /* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
+#define DDR_CS1EN 0 /* CSEN : whether a ddr chip exists 0 - un-used, 1 - used */
+
+#define DDR_ROW 15 /* ROW : 12 to 18 row address ,1G only 512MB*/
+#define DDR_COL 10 /* COL : 8 to 14 column address */
+#define DDR_BANK8 1 /* Banks each chip: 0-4bank, 1-8bank */
+#define DDR_DW32 1 /* 0 - 16-bit data width, 1 - 32-bit data width */
+
+#define DDR_tREFI 7800 /* Refresh period: 64ms / 32768 = 1.95 us , 2 ^ 15 = 32768 */
+#define DDR_CLK_DIV 1 /* Clock Divider */
+
+#define DDR_BL 8 /* DDR3 Burst length: 0 - 8 burst, 2 - 4 burst , 1 - 4 or 8(on the fly)*/
+
+#define DDR_CL 6 /* CAS latency: 5 to 14 ,tCK*/
+#define DDR_tCWL (DDR_CL - 1) /* DDR3 only: CAS Write Latency, 5 to 8 */
+
+/* Structure representing per-RAM type configuration */
+
+struct jz4780_ddr_config {
+ const char *name; /* Part name */
+
+ u32 timing1; /* Timing1 register value */
+ u32 timing2; /* Timing2 register value */
+ u32 timing3; /* Timing3 register value */
+ u32 timing4; /* Timing4 register value */
+ u32 timing5; /* Timing5 register value */
+ u32 timing6; /* Timing6 register value */
+
+ /* DDR PHY control */
+
+ u32 mr0; /* Mode Register 0 */
+ u32 mr1; /* Mode Register 1 */
+
+ u32 ptr0; /* PHY Timing Register 0 */
+ u32 ptr1; /* PHY Timing Register 1 */
+ u32 ptr2; /* PHY Timing Register 1 */
+
+ u32 dtpr0; /* DRAM Timing Parameters Register 0 */
+ u32 dtpr1; /* DRAM Timing Parameters Register 1 */
+ u32 dtpr2; /* DRAM Timing Parameters Register 2 */
+};
+
+
+#endif /* __DDR_PARAMETERS_H */
diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c
index 3d8dfe838..538b371fc 100644
--- a/board/imgtec/ci20/ci20.c
+++ b/board/imgtec/ci20/ci20.c
@@ -34,8 +34,6 @@
#define CI20_GPIO_REV_BITS (3) /* 2 bits */
#define CI20_GPIO_REV_MASK (CI20_GPIO_REV_BITS << CI20_GPIO_REV_SHIFT)
-int ci20_revision = 0;
-
struct ci20_otp {
uint32_t serial_number;
uint32_t date;
@@ -171,8 +169,7 @@ int board_eth_init(bd_t *bis)
#endif /* CONFIG_DRIVER_DM9000 */
-/* U-Boot common routines */
-int checkboard(void)
+int ci20_revision(void)
{
int val;
@@ -188,13 +185,18 @@ int checkboard(void)
/* pulldowns invert the revision number */
switch (val) {
-#define CI20_REV(a, b) case(b): ci20_revision = a; break
+#define CI20_REV(a, b) case(b): return a
CI20_REV(1, 3); /* Rev 1 boards had no pulldowns - giving 3 */
CI20_REV(2, 1); /* Rev 2 boards pulldown port C bit 18 giving 1 */
#undef CI20_REV
}
+ return 0;
+}
- printf("Board: ci20 (r%d) (Ingenic XBurst JZ4780 SoC)\n", ci20_revision);
+/* U-Boot common routines */
+int checkboard(void)
+{
+ printf("Board: ci20 (r%d) (Ingenic XBurst JZ4780 SoC)\n", ci20_revision());
return 0;
}
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index ee808ce1b..21d68c5ea 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -35,6 +35,7 @@
#define CONFIG_SYS_MIPS_TIMER_FREQ CONFIG_SYS_CPU_SPEED
#define CONFIG_SYS_DDR3_H5TQ2G83CFR
+#define CONFIG_SYS_DDR3_K4B2G0846Q
#define CONFIG_SYS_MEM_SPEED CONFIG_SYS_CPU_SPEED
#define CONFIG_SYS_MEM_DIV 3
#define CONFIG_SYS_DDR3PHY_PULLUP_IMPEDANCE 0xe
@@ -311,10 +312,6 @@
#define CONFIG_SPL_TEXT_BASE 0xf4000800
#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0x800)
-/* the NAND SPL is small enough to enable serial */
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
#endif /* !CONFIG_SPL_MMC_SUPPORT */
#endif /* __CONFIG_CI20_H__ */