summaryrefslogtreecommitdiff
path: root/board/imgtec/ci20/ci20.c
blob: 3d8dfe8383baed1545ad7a9d7c115557ab3c3626 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
/*
 * CI20 setup code
 *
 * Copyright (c) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/efuse.h>
#include <asm/arch/jz4780.h>
#include <asm/arch/nand.h>
#include <asm/jz_mmc.h>

#define CI20_GPIO_REV_PORT	(2)	/* Port C */
#define CI20_GPIO_REV_SHIFT	(18)	/* Bit 18 */
#define CI20_GPIO_REV_BITS	(3)	/* 2 bits */
#define CI20_GPIO_REV_MASK	(CI20_GPIO_REV_BITS << CI20_GPIO_REV_SHIFT)

int ci20_revision = 0;

struct ci20_otp {
	uint32_t serial_number;
	uint32_t date;
	char manufacturer[2];
	uint8_t mac[6];
} __packed;

int board_early_init_f(void)
{
	/* SYS_POWER_IND high (LED blue, VBUS on) */
	gpio_direction_output(32 * 5 + 15, 1);

	return 0;
}

int misc_init_r(void)
{
	uint32_t cpccr, ahb2_div;
	struct ci20_otp otp;
	char manufacturer[3];

	/* read the board OTP data */
	cpccr = readl(CPM_CPCCR);
	ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >> CPM_CPCCR_H2DIV_BIT) + 1;
	jz4780_efuse_init(CONFIG_SYS_MEM_SPEED / ahb2_div);
	jz4780_efuse_read(0x18, 16, (uint8_t *)&otp);

	/* set MAC address */
	if (!is_valid_ether_addr(otp.mac)) {
		/* no MAC assigned, generate one from the unique chip ID */
		jz4780_efuse_read(0x8, 4, &otp.mac[0]);
		jz4780_efuse_read(0x12, 2, &otp.mac[4]);
		otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
	}
	eth_setenv_enetaddr("ethaddr", otp.mac);

	/* put other board information into the environment */
	setenv_ulong("serial#", otp.serial_number);
	setenv_ulong("board_date", otp.date);
	memcpy(manufacturer, otp.manufacturer, 2);
	manufacturer[2] = 0;
	setenv("board_mfr", manufacturer);

	return 0;
}

int board_nand_init(struct nand_chip *nand)
{
	/* setup pins */
	writel(0x002c00ff, GPIO_PXINTC(0));
	writel(0x002c00ff, GPIO_PXMASKC(0));
	writel(0x002c00ff, GPIO_PXPAT1C(0));
	writel(0x002c00ff, GPIO_PXPAT0C(0));
	writel(0x002c00ff, GPIO_PXPENS(0));
	writel(0x00000003, GPIO_PXINTC(1));
	writel(0x00000003, GPIO_PXMASKC(1));
	writel(0x00000003, GPIO_PXPAT1C(1));
	writel(0x00000003, GPIO_PXPAT0C(1));
	writel(0x00000003, GPIO_PXPENS(1));

	/* FRB0_N */
	gpio_direction_input(32 * 0 + 20);

	/* disable write protect */
	gpio_direction_output(32 * 5 + 22, 1);

	return jz4780_nand_init(nand);
}

#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MMC_SUPPORT)

int board_mmc_init(bd_t *bd)
{
	uint32_t msc_cdr;

	/* setup MSC1 clock */
	msc_cdr = CONFIG_SYS_MEM_SPEED / 24000000 / 2 - 1;
	writel(msc_cdr | CPM_MSCCDR_CE, CPM_MSCCDR1);
	while (readl(CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY);

	/* setup MSC1 pins */
	writel(0x30f00000, GPIO_PXINTC(4));
	writel(0x30f00000, GPIO_PXMASKC(4));
	writel(0x30f00000, GPIO_PXPAT1C(4));
	writel(0x30f00000, GPIO_PXPAT0S(4));

	jz_mmc_init((msc_cdr + 1) * 2);
	return 0;
}

#endif

#ifdef CONFIG_DRIVER_DM9000

int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_NAND
	/* setup pins (some already setup for NAND) */
	writel(0x04030000, GPIO_PXINTC(0));
	writel(0x04030000, GPIO_PXMASKC(0));
	writel(0x04030000, GPIO_PXPAT1C(0));
	writel(0x04030000, GPIO_PXPAT0C(0));
	writel(0x04030000, GPIO_PXPENS(0));
#else
	/* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
	writel(0x0dff00ff, GPIO_PXINTC(0));
	writel(0x0dff00ff, GPIO_PXMASKC(0));
	writel(0x0dff00ff, GPIO_PXPAT1C(0));
	writel(0x0dff00ff, GPIO_PXPAT0C(0));
	writel(0x0dff00ff, GPIO_PXPENS(0));
	writel(0x00000003, GPIO_PXINTC(1));
	writel(0x00000003, GPIO_PXMASKC(1));
	writel(0x00000003, GPIO_PXPAT1C(1));
	writel(0x00000003, GPIO_PXPAT0C(1));
	writel(0x00000003, GPIO_PXPENS(1));
#endif

	/* enable clocks */
	writel(readl(CPM_CLKGR0) & ~CPM_CLKGR0_MAC, CPM_CLKGR0);
	writel(readl(CPM_CLKGR0) & ~CPM_CLKGR0_NEMC, CPM_CLKGR0);

	/* enable power (PB25) */
	gpio_direction_output(32 * 1 + 25, 1);

	/* reset (PF12) */
	gpio_direction_output(32 * 5 + 12, 0);
	udelay(10000);
	gpio_set(32 * 5 + 12, 1);
	udelay(10000);

	return dm9000_initialize(bis);
}

#endif /* CONFIG_DRIVER_DM9000 */

/* U-Boot common routines */
int checkboard(void)
{
	int val;

	gpio_port_direction_input(CI20_GPIO_REV_PORT, CI20_GPIO_REV_SHIFT);
	gpio_port_direction_input(CI20_GPIO_REV_PORT, CI20_GPIO_REV_SHIFT+1);

	/* Re-enable pullups (gpio_port_direction_input turns them off) */
	writel(CI20_GPIO_REV_MASK, GPIO_PXPENC(CI20_GPIO_REV_PORT));

	/* Read PC18/19 for version */
	val = readl(GPIO_PXPIN(CI20_GPIO_REV_PORT));
	val = (val & CI20_GPIO_REV_MASK) >> CI20_GPIO_REV_SHIFT;

	/* pulldowns invert the revision number */
	switch (val) {
#define CI20_REV(a, b) case(b): ci20_revision = a; break
	CI20_REV(1, 3); /* Rev 1 boards had no pulldowns - giving 3 */
	CI20_REV(2, 1); /* Rev 2 boards pulldown port C bit 18 giving 1 */
#undef CI20_REV
	}

	printf("Board: ci20 (r%d) (Ingenic XBurst JZ4780 SoC)\n", ci20_revision);
	return 0;
}

#ifdef CONFIG_SPL_BUILD

void spl_board_init(void)
{
}

#endif /* CONFIG_SPL_BUILD */