#ifndef _DM644X_H_
#define _DM644X_H_

/* Return type defines */ 
#define E_PASS    0x00000000u
#define E_FAIL    0x00000001u
#define E_TIMEOUT 0x00000002u 

/***************************************************************
  BIT mask defines
 ***************************************************************/
/*  BIT masks */
#define BIT0    0x00000001
#define BIT1    0x00000002
#define BIT2    0x00000004
#define BIT3    0x00000008
#define BIT4    0x00000010
#define BIT5    0x00000020
#define BIT6    0x00000040
#define BIT7    0x00000080
#define BIT8    0x00000100
#define BIT9    0x00000200
#define BIT10   0x00000400
#define BIT11   0x00000800
#define BIT12   0x00001000
#define BIT13   0x00002000
#define BIT14   0x00004000
#define BIT15   0x00008000
#define BIT16   0x00010000
#define BIT17   0x00020000
#define BIT18   0x00040000
#define BIT19   0x00080000
#define BIT20   0x00100000
#define BIT21   0x00200000
#define BIT22   0x00400000
#define BIT23   0x00800000
#define BIT24   0x01000000
#define BIT25   0x02000000
#define BIT26   0x04000000
#define BIT27   0x08000000
#define BIT28   0x10000000
#define BIT29   0x20000000
#define BIT30   0x40000000
#define BIT31   0x80000000

/***************************************************************
  System Control Module register structure - See sprue14.pdf,
  Chapter 10 for more details.
 ***************************************************************/
typedef struct _sys_module_regs_
{
  vuint32_t  PINMUX[2];         /* 0x00 */
  vuint32_t  DSPBOOTADDR;       /* 0x08 */
  vuint32_t  SUSPSRC;           /* 0x0C */
  vuint32_t  INTGEN;            /* 0x10 */
  vuint32_t  BOOTCFG;           /* 0x14 */
  vuint8_t   RSVD0[16];         /* 0x18 */
  vuint32_t  DEVICE_ID;         /* 0x28 */
  vuint8_t   RSVD1[8];          /* 0x2C */
  vuint32_t  USBPHY_CTL;        /* 0x34 */
  vuint32_t  CHP_SHRTSW;        /* 0x38 */
  vuint32_t  MSTPRI[2];         /* 0x3C */
  vuint32_t  VPSS_CLKCTL;       /* 0x44 */
  vuint32_t  VDD3P3V_PWDN;      /* 0x48 */
  vuint32_t  DDRVTPER;          /* 0x4C */
  vuint8_t   RSVD2[32];         /* 0x50 */ 
} sysModuleRegs;

#define SYSTEM ((sysModuleRegs*) 0x01C40000)

/***************************************************************
  ARM Interrupt Controller register structure - See sprue26.pdf
  for more details.
 ***************************************************************/
typedef struct _aintc_regs_
{
  vuint32_t  FIQ0;
  vuint32_t  FIQ1;
  vuint32_t  IRQ0;
  vuint32_t  IRQ1;
  vuint32_t  FIQENTRY;
  vuint32_t  IRQENTRY;
  vuint32_t  EINT0;
  vuint32_t  EINT1;
  vuint32_t  INTCTL;
  vuint32_t  EABASE;
  vuint8_t   RSVD0[8];
  vuint32_t  INTPRI0;
  vuint32_t  INTPRI1;
  vuint32_t  INTPRI2;
  vuint32_t  INTPRI3;
  vuint32_t  INTPRI4;
  vuint32_t  INTPRI5;
  vuint32_t  INTPRI6;
  vuint32_t  INTPRI7;
} aintcRegs;

#define AINTC ((aintcRegs*) 0x01C48000)

/***************************************************************
  PLL Register structure - See sprue14.pdf, Chapter 6
  for more details.
 ***************************************************************/
typedef struct _PLL_regs_
{
  vuint32_t  PID;
  vuint8_t   RSVD0[224];
  vuint32_t  RSTYPE;
  vuint8_t   RSVD1[24];
  vuint32_t  PLLCTL;
  vuint8_t   RSVD2[12];
  vuint32_t  PLLM;
  vuint8_t   RSVD3[4];
  vuint32_t  PLLDIV1;
  vuint32_t  PLLDIV2;
  vuint32_t  PLLDIV3;
  vuint8_t   RSVD4[4];
  vuint32_t  POSTDIV;
  vuint32_t  BPDIV;
  vuint8_t   RSVD5[8];
  vuint32_t  PLLCMD;
  vuint32_t  PLLSTAT;
  vuint32_t  ALNCTL;
  vuint32_t  DCHANGE;
  vuint32_t  CKEN;
  vuint32_t  CKSTAT;
  vuint32_t  SYSTAT;
  vuint8_t   RSVD6[12];
  vuint32_t  PLLDIV4;
  vuint32_t  PLLDIV5;
} PLLRegs;

#define PLL1 ((PLLRegs*) 0x01C40800)
#define PLL2 ((PLLRegs*) 0x01C40C00)

/***************************************************************
  Power/Sleep Ctrl Register structure - See sprue14.pdf,
  Chapter 7 for more details.
 ***************************************************************/
typedef struct _PSC_regs_
{
  vuint32_t  PID;
  vuint8_t   RSVD0[12];
  vuint32_t  GBLCTL;
  vuint8_t   RSVD1[4];
  vuint32_t  INTEVAL;
  vuint8_t   RSVD2[36];	
  vuint32_t  MERRPR0;
  vuint32_t  MERRPR1;
  vuint8_t   RSVD3[8];
  vuint32_t  MERRCR0;
  vuint32_t  MERRCR1;
  vuint8_t   RSVD4[8];
  vuint32_t  PERRPR;
  vuint8_t   RSVD5[4];
  vuint32_t  PERRCR;
  vuint8_t   RSVD6[4];
  vuint32_t  EPCPR;
  vuint8_t   RSVD7[4];
  vuint32_t  EPCCR;
  vuint8_t   RSVD8[132];
  vuint32_t  RAILSTAT;
  vuint32_t  RAILCTL;
  vuint32_t  RAILSEL;
  vuint8_t   RSVD9[20];
  vuint32_t  PTCMD;
  vuint8_t   RSVD10[4];
  vuint32_t  PTSTAT;
  vuint8_t   RSVD11[212];
  vuint32_t  PDSTAT0;
  vuint32_t  PDSTAT1;
  vuint8_t   RSVD12[248];
  vuint32_t  PDCTL0;
  vuint32_t  PDCTL1;
  vuint8_t   RSVD13[536];
  vuint32_t  MCKOUT0;
  vuint32_t  MCKOUT1;
  vuint8_t   RSVD14[728];
  vuint32_t  MDSTAT[41];
  vuint8_t   RSVD15[348];
  vuint32_t  MDCTL[41];
} PSCRegs;

#define PSC ((PSCRegs*) 0x01C41000)

/* PSC constants */
#define LPSC_VPSS_MAST      0
#define LPSC_VPSS_SLV       1
#define LPSC_TPCC           2
#define LPSC_TPTC0          3
#define LPSC_TPTC1          4
#define LPSC_EMAC0          5
#define LPSC_EMAC1          6
#define LPSC_MDIO           7
#define LPSC_1394           8
#define LPSC_USB            9
#define LPSC_ATA            10
#define LPSC_VLYNQ          11
#define LPSC_HPI            12
#define LPSC_DDR2           13
#define LPSC_AEMIF          14
#define LPSC_MMCSD          15
#define LPSC_MEMSTK         16
#define LPSC_ASP            17
#define LPSC_I2C            18

#define LPSC_GPIO           26

#define LPSC_UART0          19
#define LPSC_TIMER0         27

#define LPSC_UART2          21
#define LPSC_TIMER1         28

#define LPSC_ARM            31
#define LPSC_DSP            39
#define LPSC_IMCOP          40

#define EMURSTIE_MASK       0x00000200

#define PSC_ENABLE          0x3
#define PSC_DISABLE         0x2
#define PSC_SYNCRESET       0x1
#define PSC_SWRSTDISABLE    0x0


/***************************************************************
  DDR2 Memory Ctrl Register structure - See sprue22b.pdf
  for more details.
 ***************************************************************/
typedef struct _DDR2_MEM_CTL_REGS_
{
  vuint8_t   RSVD0[4];     /* 0x00 */
  vuint32_t  SDRSTAT;      /* 0x04 */
  vuint32_t  SDBCR;        /* 0x08 */
  vuint32_t  SDRCR;        /* 0x0C */
  vuint32_t  SDTIMR;       /* 0x10 */
  vuint32_t  SDTIMR2;      /* 0x14 */
  vuint8_t   RSVD1[8];     /* 0x18 */ 
  vuint32_t  PBBPR;        /* 0x20 */
  vuint8_t   RSVD2[156];   /* 0x24 */ 
  vuint32_t  IRR;          /* 0xC0 */
  vuint32_t  IMR;          /* 0xC4 */
  vuint32_t  IMSR;         /* 0xC8 */
  vuint32_t  IMCR;         /* 0xCC */
  vuint8_t   RSVD3[20];    /* 0xD0 */
  vuint32_t  DDRPHYCR;     /* 0xE4 */
  vuint8_t   RSVD4[8];     /* 0xE8 */
  vuint32_t  VTPIOCR;      /* 0xF0 */
} DDR2Regs;

#define DDRVTPR (*((vuint32_t*) 0x01C42030))
#define DDR ((DDR2Regs*) 0x20000000)
#define DDR_TEST_PATTERN 0xA55AA55Au
#define DDR_RAM_SIZE 0x10000000u


/***************************************************************
  AEMIF Register structure - See sprue20a.pdf
  for more details.
 ***************************************************************/
typedef struct _emif_regs_
{
  vuint32_t  ERCSR;        /* 0x00 */
  vuint32_t  AWCCR;        /* 0x04 */
  vuint32_t  SDBCR;        /* 0x08 */
  vuint32_t  SDRCR;        /* 0x0C */
  vuint32_t  AB1CR;        /* 0x10 */
  vuint32_t  AB2CR;        /* 0x14 */
  vuint32_t  AB3CR;
  vuint32_t  AB4CR;
  vuint32_t  SDTIMR;       /* 0x20 */
  vuint32_t  DDRSR;
  vuint32_t  DDRPHYCR;
  vuint32_t  DDRPHYSR;
  vuint32_t  TOTAR;        /* 0x30 */
  vuint32_t  TOTACTR;
  vuint32_t  DDRPHYID_REV;
  vuint32_t  SDSRETR;
  vuint32_t  EIRR;         /* 0x40 */
  vuint32_t  EIMR;
  vuint32_t  EIMSR;
  vuint32_t  EIMCR;
  vuint32_t  IOCTRLR;      /* 0x50 */
  vuint32_t  IOSTATR;
  vuint8_t   RSVD0[8];
  vuint32_t  NANDFCR;      /* 0x60 */
  vuint32_t  NANDFSR;
  vuint8_t   RSVD1[8];
  vuint32_t  NANDF1ECC;    /* 0x70 */
  vuint32_t  NANDF2ECC;
  vuint32_t  NANDF3ECC;
  vuint32_t  NANDF4ECC;
  vuint8_t   RSVD2[4];      /* 0x80 */
  vuint32_t  IODFTECR;
  vuint32_t  IODFTGCR;
  vuint8_t   RSVD3[4];
  vuint32_t  IODFTMRLR;    /* 0x90 */
  vuint32_t  IODFTMRMR;
  vuint32_t  IODFTMRMSBR;
  vuint8_t   RSVD4[20];
  vuint32_t  MODRNR;       /* 0xB0 */
} emifRegs;

#define AEMIF ((emifRegs*) 0x01E00000)

/***************************************************************
  UART Register structure - See sprue33.pdf
  for more details.
 ***************************************************************/
typedef struct _uart_regs_
{
  vuint32_t  RBR;
  vuint32_t  IER;
  vuint32_t  IIR;
  vuint32_t  LCR;
  vuint32_t  MCR;
  vuint32_t  LSR;
  vuint32_t  MSR;
  vuint32_t  SCR;
  vuint8_t   DLL;
  vuint8_t   RSVDO[3];
  vuint8_t   DLH;
  vuint8_t   RSVD1[3];	
  vuint32_t  PID1;
  vuint32_t  PID2;
  vuint32_t  PWREMU_MGNT;
} uartRegs;

#define THR RBR
#define FCR IIR

#define UART0 ((uartRegs*) 0x01C20000)
#define UART2 ((uartRegs*) 0x01C20800)

/***************************************************************
  Timer Register structure - See sprue26.pdf
  for more details.
 ***************************************************************/
typedef struct _timer_regs_
{
  vuint32_t  PID12;
  vuint32_t  EMUMGT_CLKSPD;
  vuint32_t  GPINT_GPEN;
  vuint32_t  GPTDAT_GPDIR;
  vuint32_t  TIM12;
  vuint32_t  TIM34;
  vuint32_t  PRD12;
  vuint32_t  PRD34;
  vuint32_t  TCR;
  vuint32_t  TGCR;
  vuint32_t  WDTCR;
} timerRegs;

#define TIMER0 ((timerRegs*) 0x01C21400)

/* Timer inline functions */
static inline void TIMER0Start( void )
{
  AINTC->IRQ1  |= 0x00000001;
  TIMER0->TGCR &= 0xfffffffe; /* reset TIM12RS */
  TIMER0->TIM12 = 0x0;
  TIMER0->TCR  |= 0x00000040; /* ENAMODE12 = 01 */
  TIMER0->TGCR |= 0x00000001; /*   set TIM12RS */
}

static inline int TIMER0Status( void )
{
  return( (AINTC->IRQ1) & 1 );
}

static inline void TIMER1Start( void )
{
  AINTC->IRQ1  |= 0x00000002;
  TIMER0->TGCR &= 0xfffffffd; /* reset TIM34RS */
  TIMER0->TIM34 = 0x0;
  TIMER0->TCR  |= 0x00400000; /* ENAMODE34 = 01 */
  TIMER0->TGCR |= 0x00000002; /*   set TIM34RS */
}

static inline int TIMER1Status( void )
{
  return( (AINTC->IRQ1) & 2 );
}

/* Function Prototypes */

/* Execute LPSC state transition */
extern void LPSCTransition( uint8_t module, uint8_t state ); /* dm644x.c */

/* Initialization prototypes */
extern void DM644xInit( void );                              /* dm644x.c */
extern void PSCInit( void );                                 /* dm644x.c */
extern void TIMER0Init( void );                              /* dm644x.c */
extern void UART0Init( void );                               /* dm644x.c */
extern void UART2Init( void );                               /* dm644x.c */
extern void PLL1Init( void );                                /* dm644x.c */
extern void PLL2Init( void );                                /* dm644x.c */
extern void DDR2Init( void );                                /* dm644x.c */
extern void AEMIFInit( void );                               /* dm644x.c */
extern void IVTInit( void );                                 /* dm644x.c */

/* NOP wait loop */
extern void waitloop( uint32_t loopcnt );                    /* dm644x.c */

#endif /* End _DM644X_H_ */