diff options
author | kx <kx@radix.pro> | 2023-09-20 20:39:46 +0300 |
---|---|---|
committer | kx <kx@radix.pro> | 2023-09-20 20:39:46 +0300 |
commit | 5fe56a16f7f63d8c3a4b0091cd4902d1d558d602 (patch) | |
tree | 29269ff4449662695bb32d5e6afb00edc7f57b01 | |
parent | f3c042d7a10d0531e19475a86f7863911d631810 (diff) | |
download | linux-5fe56a16f7f63d8c3a4b0091cd4902d1d558d602.tar.xz |
dts: rk3588
35 files changed, 17795 insertions, 287 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 8c15593c0ca4..4be76f0a7257 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -72,3 +72,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-mixtile-blade3.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-radxa-cm5-io.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts new file mode 100644 index 000000000000..b51543892078 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-edgeble-neu6a.dtsi" + +/ { + model = "Edgeble Neu6A IO Board"; + compatible = "edgeble,neural-compute-module-6a-io", + "edgeble,neural-compute-module-6a", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi new file mode 100644 index 000000000000..38e1a1e25f33 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts new file mode 100644 index 000000000000..e9d5a8bab581 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rk3588j.dtsi" +#include "rk3588-edgeble-neu6b.dtsi" + +/ { + model = "Edgeble Neu6B IO Board"; + compatible = "edgeble,neural-compute-module-6b-io", + "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi new file mode 100644 index 000000000000..1c5bcf1280b4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts new file mode 100644 index 000000000000..c730c9be848b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -0,0 +1,1135 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 V10 Board"; + compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-vol-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + button-vol-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + button-menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + button-escape { + label = "Escape"; + linux,code = <KEY_ESC>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc12v_dcin>; + pwms = <&pwm2 0 25000 0>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30_en>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-rxid"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + pinctrl-names = "default"; + rx_delay = <0x00>; + tx_delay = <0x43>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + usbc0_role_sw: endpoint { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg = <2>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_1_rst>, <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie2 { + pcie2_1_rst: pcie2-1-rst { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie30_en: vcc3v3-pcie30-en { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_gpu_mem_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vdd_npu_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + pmic@1 { + compatible = "rockchip,rk806"; + reg = <0x01>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, + <&rk806_slave_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_slave_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_cpu_big1_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "otg"; + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts new file mode 100644 index 000000000000..9d236a535342 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-mixtile-blade3.dts @@ -0,0 +1,729 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588.dtsi" + +/ { + model = "Mixtile Blade 3"; + compatible = "mixtile,blade3", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + }; + + vbus5v0_typec0: vbus5v0-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren0>; + }; + + vbus5v0_typec1: vbus5v0-typec1 { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren1>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + rockchip,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m0_xfer>; + status = "okay"; +}; + +&i2c5 { + pinctrl-0 = <&i2c5m3_xfer>; + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + usbc1_int: usbc1-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren0: typec5v-pwren0 { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec5v_pwren1: typec5v-pwren1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m2_pins>; + status = "okay"; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m3_pins>; + status = "disabled"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4m2_cs0 &spi4m2_pins>; + num-cs = <1>; + status = "okay"; +}; + +&i2s2_2ch { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_mclk + &i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts new file mode 100644 index 000000000000..f76377a7818c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts @@ -0,0 +1,918 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "FriendlyElec NanoPC-T6"; + compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphones"; + + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "system-led"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + linux,default-trigger = "heartbeat"; + }; + + usr_led: led-1 { + gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "user-led"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pin>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vcc5v0_sys powers peripherals */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* vcc4v0_sys powers the RK806, RK860's */ + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-1v1-nldo-s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc4v0_sys>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "HEADER_10", "HEADER_08", "HEADER_32", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27", "HEADER_28", "", "", + "", "", "", "HEADER_15", + /* GPIO1 B0-B7 */ + "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", + "HEADER_24", "HEADER_22", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_05", "HEADER_03"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI1_11", "CSI1_12", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", + "HEADER_37", "", "DSI0_12", "", + /* GPIO3 B0-B7 */ + "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", + "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", + /* GPIO3 C0-C7 */ + "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "DSI1_10", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "DSI1_08", "DSI1_14", "", "DSI1_12", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "CSI0_11", "CSI0_12", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + rockchip,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <1000000>; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + + port { + rt5616_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&rt5616_p0_0>; + }; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usr_led_pin: usr-led-pin { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts new file mode 100644 index 000000000000..657838969554 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts @@ -0,0 +1,1226 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Orange Pi 5 Plus"; + compatible = "xunlong,orangepi-5-plus", "rockchip,rk3588"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_rgb>; + status = "okay"; + + blue_led@1 { + gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + label = "blue_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + + green_led@2 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + label = "green_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + + status = "okay"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = <KEY_BACK>; + press-threshold-microvolt = <1235000>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "ES8388 Audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,frame-master = <&masterdai>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Microphone", "Onboard Mic", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Speaker Amplifier INL", "LOUT2", + "Speaker Amplifier INR", "ROUT2", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR", + "Headphone Amplifier INL", "LOUT1", + "Headphone Amplifier INR", "ROUT1", + "Headphones", "Headphone Amplifier OUTL", + "Headphones", "Headphone Amplifier OUTR", + "LINPUT1", "Onboard Mic", + "LINPUT2", "Onboard Mic", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + simple-audio-card,spk-con-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + simple-audio-card,hp-con-gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + + simple-audio-card,io-channels = <&saradc 3>; + simple-audio-card,io-channel-names = "adc-detect"; + simple-audio-card,keyup-threshold-microvolt = <1800000>; + simple-audio-card,poll-interval = <100>; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + }; + + play-pause-key { + label = "playpause"; + linux,code = <KEY_PLAYPAUSE>; + press-threshold-microvolt = <2000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wifi_disable: wifi-diable-gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "wifi_disable"; + enable-active-high; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + enable-active-low; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + pcie20_avdd0v85: pcie20-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_pcie_eth: vcc3v3-pcie-eth-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_eth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + enable-active-low; + gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + startup-delay-us = <50000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PC6 IRQ_TYPE_LEVEL_LOW>; + }; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + #sound-dai-cells = <0>; + }; +}; + +&i2s0_8ch { + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc_pwr { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-func { + leds_rgb: leds-rgb { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m2_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi0 { + assigned-clocks = <&cru CLK_SPI0>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "disabled"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fudr_moden0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&spi4 { + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "disabled"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart9 { + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&sfc { + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim1_pins>; + status = "okay"; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + //rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + //svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + dr_mode = "otg"; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi new file mode 100644 index 000000000000..244c66faa161 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk32k { + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko_25m */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + }; + + fspi { + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins = + /* fspi_clk_m1 */ + <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m1 */ + <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m1 */ + <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m1 */ + <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m1 */ + <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim1_cs1: fspim1-cs1 { + rockchip,pins = + /* fspi_cs1n_m1 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <4 RK_PC4 1 &pcfg_pull_none>, + /* gmac0_mdio */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* gmac0_rxdv_crs */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins = + /* gmac0_ppsclk */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppstring: gmac0-ppstring { + rockchip,pins = + /* gmac0_ppstring */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins = + /* gmac0_ptp_refclk */ + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_txer: gmac0-txer { + rockchip,pins = + /* gmac0_txer */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_tx1_cec: hdmim0-tx1-cec { + rockchip,pins = + /* hdmim0_tx1_cec */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_scl: hdmim0-tx1-scl { + rockchip,pins = + /* hdmim0_tx1_scl */ + <2 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_sda: hdmim0-tx1-sda { + rockchip,pins = + /* hdmim0_tx1_sda */ + <2 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PC0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins = + /* i2c3_scl_m3 */ + <2 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m3 */ + <2 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <2 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <2 RK_PB4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins = + /* i2c5_scl_m4 */ + <2 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m4 */ + <2 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins = + /* i2c6_scl_m2 */ + <2 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m2 */ + <2 RK_PC2 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins = + /* i2c7_scl_m1 */ + <4 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m1 */ + <4 RK_PC4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins = + /* i2c8_scl_m1 */ + <2 RK_PB0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m1 */ + <2 RK_PB1 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m2_pins: pwm2m2-pins { + rockchip,pins = + /* pwm2_m2 */ + <4 RK_PC2 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <4 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m2_pins: pwm5m2-pins { + rockchip,pins = + /* pwm5_m2 */ + <4 RK_PC4 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <4 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m3_pins: pwm7m3-pins { + rockchip,pins = + /* pwm7_ir_m3 */ + <4 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom0_pins: sdiom0-pins { + rockchip,pins = + /* sdio_clk_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* sdio_cmd_m0 */ + <2 RK_PB2 2 &pcfg_pull_none>, + /* sdio_d0_m0 */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* sdio_d1_m0 */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* sdio_d2_m0 */ + <2 RK_PB0 2 &pcfg_pull_none>, + /* sdio_d3_m0 */ + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m0 */ + <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m0 */ + <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0_m0 */ + <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1_m0 */ + <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clk_m0 */ + <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m0 */ + <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m0 */ + <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0_m0 */ + <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1_m0 */ + <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <2 RK_PB6 10 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <2 RK_PB7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PC1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PC0 10 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <2 RK_PA6 10 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <2 RK_PA7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PB1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB0 10 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <2 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <2 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <4 RK_PC6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <4 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PC4 10 &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts new file mode 100644 index 000000000000..7dbe298cadf9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -0,0 +1,924 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "Radxa ROCK 5 Model B"; + compatible = "radxa,rock-5b", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_b>; + + led_rgb_b { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_BLUE>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_vcc3v3_en>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_vcc3v3_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "okay"; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc12v_dcin>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>, + <PDO_VAR(5000, 20000, 5000)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_rgb_b: led-rgb-b { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_vcc3v3_en: pcie2-0-vcc-en { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_rst: pcie3-rst { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie3_vcc3v3_en: pcie3-vcc3v3-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim2_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_rst>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi new file mode 100644 index 000000000000..01778f609f98 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3588s.dtsi" +#include "rk3588-pinctrl.dtsi" + +/ { + usb_host1_xhci: usb@fc400000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588j.dtsi b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi new file mode 100644 index 000000000000..38b9dbf38a21 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts new file mode 100644 index 000000000000..1a60a275ddf9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -0,0 +1,763 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588s.dtsi" + +/ { + model = "Indiedroid Nova"; + compatible = "indiedroid,nova", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clock-names = "ext_clock"; + clocks = <&rtc_hym8563>; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,es8388-codec"; + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + routing = "LINPUT2", "Mic Jack", + "Headphones", "LOUT1", + "Headphones", "ROUT1"; + dais = <&i2s0_8ch_p0>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&typec5v_pwren>; + pinctrl-names = "default"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc5v0_sys>; + }; + + /* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */ + vcc_3v3_s0: vcc-3v3-s0-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc5v0_usbdcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vcc5v0_usbdcin"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +/* + * Add labels for each GPIO pin exposed on the 40 pin header. Note that + * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by + * label). + */ +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 D0-D7 */ + "HEADER_12_1v8", "", "", "HEADER_24_1v8", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27_3v3", "HEADER_28_3v3", "", "", + "HEADER_29_1v8", "", "HEADER_7_1v8", "", + /* GPIO1 B0-B7 */ + "", "HEADER_31_1v8", "HEADER_33_1v8", "", + "HEADER_11_1v8", "HEADER_13_1v8", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_5_3v3", "HEADER_3_3v3"; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO3 B0-B7 */ + "HEADER_16_1v8", "HEADER_18_1v8", "", "", + "", "", "", "HEADER_19_1v8", + /* GPIO3 C0-C7 */ + "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8", + "HEADER_15_1v8", "HEADER_22_1v8", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "", "", "HEADER_37_3v3", "HEADER_32_3v3", + "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3", + /* GPIO4 B0-B7 */ + "", "", "", "HEADER_40_3v3", + "HEADER_8_3v3", "HEADER_10_3v3", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-0 = <&i2c0m2_xfer>; + pinctrl-names = "default"; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <1000000>; + }; + }; + + rtc_hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&hym8563_int>; + pinctrl-names = "default"; + wakeup-source; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m0_xfer>; + status = "okay"; + + es8388: audio-codec@11 { + compatible = "everest,es8388"; + reg = <0x11>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply = <&vcc_3v3_s3>; + clock-names = "mclk"; + clocks = <&cru I2S0_8CH_MCLKOUT>; + DVDD-supply = <&vcc_1v8_s3>; + HPVDD-supply = <&vcc_3v3_s3>; + PVDD-supply = <&vcc_1v8_s3>; + #sound-dai-cells = <0>; + + port { + es8388_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8388_p0_0>; + }; + }; +}; + +&pinctrl { + bluetooth-pins { + bt_reset: bt-reset { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_dev: bt-wake-dev { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hym8563 { + + hym8563_int: hym8563-int { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = + <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* HS400 modes seemed to cause io errors. */ +&sdhci { + bus-width = <8>; + no-mmc-hs400; + no-sd; + no-sdio; + non-removable; + max-frequency = <200000000>; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>; + pinctrl-names = "default"; + #size-cells = <0>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-names = "default"; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <675000>; + regulator-name = "vdd_logic_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <950000>; + regulator-min-microvolt = <550000>; + regulator-name = "vdd_vdenc_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2000000>; + regulator-min-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <600000>; + regulator-min-microvolt = <600000>; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3_pldo6: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3_pldo6"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <750000>; + regulator-min-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Schematics show not in use */ + nldo-reg5 { + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +/* DMA seems to interfere with bluetooth device normal operation. */ +&uart9 { + pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>; + pinctrl-names = "default"; + /delete-property/ dma-names; + /delete-property/ dmas; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "realtek,rtl8821cs-bt", + "realtek,rtl8723bs-bt"; + device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>; + pinctrl-names = "default"; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts new file mode 100644 index 000000000000..93b4a0c4ed0f --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "Khadas Edge2"; + compatible = "khadas,edge2", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts new file mode 100644 index 000000000000..8fc4ba584d89 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588s-nanopi-r6s.dts" + +/ { + model = "FriendlyElec NanoPi R6C"; + compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s"; + + aliases { + ethernet0 = &r8125_u25; + }; +}; + +&lan2_led { + label = "user_led"; +}; + +&pcie2x1l2 { + /delete-node/ pcie@40; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts new file mode 100644 index 000000000000..63e215694160 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts @@ -0,0 +1,791 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include "rk3588s.dtsi" + +/ { + model = "FriendlyElec NanoPi R6S"; + compatible = "friendlyarm,nanopi-r6s", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key1_pin>; + + button@1 { + debounce-interval = <50>; + gpios = <&gpio1 RK_PC0 GPIO_ACTIVE_LOW>; + label = "K1"; + linux,code = <BTN_1>; + wakeup-source; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + label = "sys_led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + wan_led: led-1 { + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "wan_led"; + pinctrl-names = "default"; + pinctrl-0 = <&wan_led_pin>; + }; + + lan1_led: led-2 { + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "lan1_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan1_led_pin>; + }; + + lan2_led: led-3 { + gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + label = "lan2_led"; + pinctrl-names = "default"; + pinctrl-0 = <&lan2_led_pin>; + }; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host_20: vcc5v0-host-20-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host20_en>; + regulator-name = "vcc5v0_host_20"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,no-vlhash; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-key { + key1_pin: key1-pin { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan1_led_pin: lan1-led-pin { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lan2_led_pin: lan2-led-pin { + rockchip,pins = + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host20_en: vcc5v0-host20-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +/* HS400 modes seemed to cause io errors. */ +&sdhci { + bus-width = <8>; + no-mmc-hs400; + no-sd; + no-sdio; + non-removable; + max-frequency = <200000000>; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vcc_1v8_s3>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,init-delay-ms = <100>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; + + pcie@0,0 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u25: pcie@30 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + status = "okay"; + + pcie@0,0 { + reg = <0x00400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + r8125_u40: pcie@40 { + reg = <0x000000 0 0 0 0>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vbus5v0_typec>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_20>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts new file mode 100644 index 000000000000..8fbccab8e7c7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts @@ -0,0 +1,1284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588s.dtsi" + +/ { + model = "Orange Pi 5"; + compatible = "xunlong,orangepi-5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdmmc; + mmc1 = &sdhci; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + status = "okay"; + + led@1 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + linux,default-trigger-delay-ms = <0>; + }; + }; + + analog-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_detect>; + simple-audio-card,name = "ES8388 Audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&masterdai>; + simple-audio-card,frame-master = <&masterdai>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Microphone", "Onboard Mic", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Speaker Amplifier INL", "LOUT2", + "Speaker Amplifier INR", "ROUT2", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR", + "Headphone Amplifier INL", "LOUT1", + "Headphone Amplifier INR", "ROUT1", + "Headphones", "Headphone Amplifier OUTL", + "Headphones", "Headphone Amplifier OUTR", + "LINPUT1", "Onboard Mic", + "LINPUT2", "Onboard Mic", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + masterdai: simple-audio-card,codec { + sound-dai = <&es8388>; + }; + + play-pause-key { + label = "playpause"; + linux,code = <KEY_PLAYPAUSE>; + press-threshold-microvolt = <2000>; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = <KEY_BACK>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight_1: backlight_1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + combophy_avdd0v85: combophy-avdd0v85-regulator { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + rx_delay = <0x3f>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + status = "disabled"; +}; + +/* + pin3: GPIO1_B7 + pin5: GPIO1_B6 +*/ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m3_xfer>; + status = "disabled"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; + + es8388: audio-codec@10 { + compatible = "everest,es8388"; + reg = <0x10>; + assigned-clock-rates = <12288000>; + assigned-clocks = <&cru I2S1_8CH_MCLKOUT>; + clock-names = "mclk"; + clocks = <&cru I2S1_8CH_MCLKOUT>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + + AVDD-supply = <&vcc_3v3_s3>; + DVDD-supply = <&vcc_1v8_s3>; + HPVDD-supply = <&vcc_3v3_s3>; + PVDD-supply = <&vcc_3v3_s3>; + + }; + + usbc0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; + source-pdos = + <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; +}; + +&i2s1_8ch { +// rockchip,i2s-tx-route = <3 2 1 0>; +// rockchip,i2s-rx-route = <1 3 2 0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclk + &i2s1m0_lrck + &i2s1m0_sdi1 + &i2s1m0_sdo3>; + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sound { + hp_detect: hp-detect { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-func { + leds_gpio: leds-gpio { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata_reset:sata-reset{ + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m1_pins>; + status = "disabled"; +}; + +/* + pin26: GPIO1_A3 +*/ +&pwm1 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m1_pins>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m2_pins>; + status = "disabled"; +}; + +&pwm6 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m2_pins>; + status = "disabled"; +}; + +/* + pin11: GPIO4_B2 + pin13: GPIO4_B3 +*/ +&pwm14 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m1_pins>; + status = "disabled"; +}; + +/* + pin7: GPIO1_C6 +*/ +&pwm15 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m2_pins>; + status = "disabled"; +}; + +&backlight_1 { + pwms = <&pwm6 0 25000 0>; + status = "okay"; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&av1d { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "disabled"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +/* + pin19: GPIO1_C1 + pin21: GPIO1_C0 + pin23: GPIO1_C2 + pin24: GPIO1_C4 +*/ +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + assigned-clocks = <&cru CLK_SPI4>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + status = "disabled"; + + spi_dev@1 { + compatible = "rockchip,spidev"; + reg = <1>; + spi-max-frequency = <50000000>; + }; +}; + +/* + pin8: GPIO4_A3 + pin10: GPIO4_A4 +*/ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; + status = "disabled"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + status = "disabled"; +}; + +/* + pin16: GPIO1_D3 + pin18: GPIO1_D2 +*/ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + status = "disabled"; +}; + +&uart9 { + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&sata0 { + pinctrl-names = "default"; + pinctrl-0 = <&sata_reset>; + status = "disabled"; +}; + +&sfc { + status = "okay"; + max-freq = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + + spi_flash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + loader@0 { + label = "loader"; + reg = <0x0 0x1000000>; + }; + }; + }; +}; + + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + mode-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + usb-role-switch; + dr_mode = "otg"; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts new file mode 100644 index 000000000000..e0dc34cbe6c8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5b.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3588s-orangepi-5.dts" + +/ { + model = "Orange Pi 5B"; + compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588"; +}; + +&sdhci { + status = "okay"; +}; + +&sfc { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "okay"; +}; + +&wireless_wlan { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi new file mode 100644 index 000000000000..48181671eacb --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi @@ -0,0 +1,3403 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + auddsm { + /omit-if-no-ref/ + auddsm_pins: auddsm-pins { + rockchip,pins = + /* auddsm_ln */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PA2 4 &pcfg_pull_none>, + /* auddsm_rn */ + <3 RK_PA3 4 &pcfg_pull_none>, + /* auddsm_rp */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <4 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <0 RK_PC0 11 &pcfg_pull_none>, + /* can0_tx_m0 */ + <0 RK_PB7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <4 RK_PD5 9 &pcfg_pull_none>, + /* can0_tx_m1 */ + <4 RK_PD4 9 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <3 RK_PB5 9 &pcfg_pull_none>, + /* can1_tx_m0 */ + <3 RK_PB6 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <4 RK_PB2 12 &pcfg_pull_none>, + /* can1_tx_m1 */ + <4 RK_PB3 12 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rx_m0 */ + <3 RK_PC4 9 &pcfg_pull_none>, + /* can2_tx_m0 */ + <3 RK_PC5 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rx_m1 */ + <0 RK_PD4 10 &pcfg_pull_none>, + /* can2_tx_m1 */ + <0 RK_PD5 10 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_d10 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d11 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d12 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d13 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d14 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d15 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d1 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d2 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d3 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d4 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d5 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_d6 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* cif_d7 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_big0_avs */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* cpu_big1_avs */ + <0 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + /omit-if-no-ref/ + ddrphych0_pins: ddrphych0-pins { + rockchip,pins = + /* ddrphych0_dtb0 */ + <4 RK_PA0 7 &pcfg_pull_none>, + /* ddrphych0_dtb1 */ + <4 RK_PA1 7 &pcfg_pull_none>, + /* ddrphych0_dtb2 */ + <4 RK_PA2 7 &pcfg_pull_none>, + /* ddrphych0_dtb3 */ + <4 RK_PA3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + /omit-if-no-ref/ + ddrphych1_pins: ddrphych1-pins { + rockchip,pins = + /* ddrphych1_dtb0 */ + <4 RK_PA4 7 &pcfg_pull_none>, + /* ddrphych1_dtb1 */ + <4 RK_PA5 7 &pcfg_pull_none>, + /* ddrphych1_dtb2 */ + <4 RK_PA6 7 &pcfg_pull_none>, + /* ddrphych1_dtb3 */ + <4 RK_PA7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + /omit-if-no-ref/ + ddrphych2_pins: ddrphych2-pins { + rockchip,pins = + /* ddrphych2_dtb0 */ + <4 RK_PB0 7 &pcfg_pull_none>, + /* ddrphych2_dtb1 */ + <4 RK_PB1 7 &pcfg_pull_none>, + /* ddrphych2_dtb2 */ + <4 RK_PB2 7 &pcfg_pull_none>, + /* ddrphych2_dtb3 */ + <4 RK_PB3 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + /omit-if-no-ref/ + ddrphych3_pins: ddrphych3-pins { + rockchip,pins = + /* ddrphych3_dtb0 */ + <4 RK_PB4 7 &pcfg_pull_none>, + /* ddrphych3_dtb1 */ + <4 RK_PB5 7 &pcfg_pull_none>, + /* ddrphych3_dtb2 */ + <4 RK_PB6 7 &pcfg_pull_none>, + /* ddrphych3_dtb3 */ + <4 RK_PB7 7 &pcfg_pull_none>; + }; + }; + + dp0 { + /omit-if-no-ref/ + dp0m0_pins: dp0m0-pins { + rockchip,pins = + /* dp0_hpdin_m0 */ + <4 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m1_pins: dp0m1-pins { + rockchip,pins = + /* dp0_hpdin_m1 */ + <0 RK_PC4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m2_pins: dp0m2-pins { + rockchip,pins = + /* dp0_hpdin_m2 */ + <1 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + /omit-if-no-ref/ + dp1m0_pins: dp1m0-pins { + rockchip,pins = + /* dp1_hpdin_m0 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m1_pins: dp1m1-pins { + rockchip,pins = + /* dp1_hpdin_m1 */ + <0 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m2_pins: dp1m2-pins { + rockchip,pins = + /* dp1_hpdin_m2 */ + <1 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = + /* emmc_data_strobe */ + <2 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1_pins: eth1-pins { + rockchip,pins = + /* eth1_refclko_25m */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspim0_pins: fspim0-pins { + rockchip,pins = + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim0_cs1: fspim0-cs1 { + rockchip,pins = + /* fspi_cs1n_m0 */ + <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_pins: fspim2-pins { + rockchip,pins = + /* fspi_clk_m2 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m2 */ + <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m2 */ + <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m2 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m2 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m2 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_cs1: fspim2-cs1 { + rockchip,pins = + /* fspi_cs1n_m2 */ + <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1_miim: gmac1-miim { + rockchip,pins = + /* gmac1_mdc */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* gmac1_mdio */ + <3 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_clkinout: gmac1-clkinout { + rockchip,pins = + /* gmac1_mclkinout */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* gmac1_rxd1 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* gmac1_rxdv_crs */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclk */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* gmac1_txclk */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins = + /* gmac1_ppsclk */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins = + /* gmac1_ppstrig */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins = + /* gmac1_ptp_ref_clk */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_txer: gmac1-txer { + rockchip,pins = + /* gmac1_txer */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_rx_cec: hdmim0-rx-cec { + rockchip,pins = + /* hdmim0_rx_cec */ + <4 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_hpdin: hdmim0-rx-hpdin { + rockchip,pins = + /* hdmim0_rx_hpdin */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_scl: hdmim0-rx-scl { + rockchip,pins = + /* hdmim0_rx_scl */ + <0 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_sda: hdmim0-rx-sda { + rockchip,pins = + /* hdmim0_rx_sda */ + <0 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = + /* hdmim0_tx0_cec */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = + /* hdmim0_tx0_hpd */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = + /* hdmim0_tx0_scl */ + <4 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = + /* hdmim0_tx0_sda */ + <4 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_hpd: hdmim0-tx1-hpd { + rockchip,pins = + /* hdmim0_tx1_hpd */ + <1 RK_PA6 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins = + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins = + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins = + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_cec: hdmim1-tx0-cec { + rockchip,pins = + /* hdmim1_tx0_cec */ + <0 RK_PD1 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_hpd: hdmim1-tx0-hpd { + rockchip,pins = + /* hdmim1_tx0_hpd */ + <3 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_scl: hdmim1-tx0-scl { + rockchip,pins = + /* hdmim1_tx0_scl */ + <0 RK_PD5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_sda: hdmim1-tx0-sda { + rockchip,pins = + /* hdmim1_tx0_sda */ + <0 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_cec: hdmim1-tx1-cec { + rockchip,pins = + /* hdmim1_tx1_cec */ + <0 RK_PD2 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_hpd: hdmim1-tx1-hpd { + rockchip,pins = + /* hdmim1_tx1_hpd */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_scl: hdmim1-tx1-scl { + rockchip,pins = + /* hdmim1_tx1_scl */ + <3 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_sda: hdmim1-tx1-sda { + rockchip,pins = + /* hdmim1_tx1_sda */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + hdmim2_rx_cec: hdmim2-rx-cec { + rockchip,pins = + /* hdmim2_rx_cec */ + <1 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_hpdin: hdmim2-rx-hpdin { + rockchip,pins = + /* hdmim2_rx_hpdin */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_scl: hdmim2-rx-scl { + rockchip,pins = + /* hdmim2_rx_scl */ + <1 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_sda: hdmim2-rx-sda { + rockchip,pins = + /* hdmim2_rx_sda */ + <1 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_scl: hdmim2-tx0-scl { + rockchip,pins = + /* hdmim2_tx0_scl */ + <3 RK_PC7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_sda: hdmim2-tx0-sda { + rockchip,pins = + /* hdmim2_tx0_sda */ + <3 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_cec: hdmim2-tx1-cec { + rockchip,pins = + /* hdmim2_tx1_cec */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_scl: hdmim2-tx1-scl { + rockchip,pins = + /* hdmim2_tx1_scl */ + <1 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_sda: hdmim2-tx1-sda { + rockchip,pins = + /* hdmim2_tx1_sda */ + <1 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug0: hdmi-debug0 { + rockchip,pins = + /* hdmi_debug0 */ + <1 RK_PA7 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug1: hdmi-debug1 { + rockchip,pins = + /* hdmi_debug1 */ + <1 RK_PB0 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug2: hdmi-debug2 { + rockchip,pins = + /* hdmi_debug2 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug3: hdmi-debug3 { + rockchip,pins = + /* hdmi_debug3 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug4: hdmi-debug4 { + rockchip,pins = + /* hdmi_debug4 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug5: hdmi-debug5 { + rockchip,pins = + /* hdmi_debug5 */ + <1 RK_PB4 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug6: hdmi-debug6 { + rockchip,pins = + /* hdmi_debug6 */ + <1 RK_PA0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PB3 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <0 RK_PD1 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <0 RK_PD2 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <0 RK_PB0 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <0 RK_PB1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins = + /* i2c1_scl_m2 */ + <0 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m2 */ + <0 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins = + /* i2c1_scl_m3 */ + <2 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m3 */ + <2 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins = + /* i2c1_scl_m4 */ + <1 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m4 */ + <1 RK_PD3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins = + /* i2c2_scl_m2 */ + <2 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m2 */ + <2 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins = + /* i2c2_scl_m4 */ + <1 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m4 */ + <1 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + /* i2c3_scl_m2 */ + <4 RK_PA4 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <4 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins = + /* i2c3_scl_m4 */ + <4 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m4 */ + <4 RK_PD1 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins = + /* i2c4_scl_m2 */ + <0 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m2 */ + <0 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins = + /* i2c4_scl_m3 */ + <1 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m3 */ + <1 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins = + /* i2c4_scl_m4 */ + <1 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m4 */ + <1 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PD0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + /* i2c5_scl_m2 */ + <4 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <4 RK_PA7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins = + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PC2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins = + /* i2c6_scl_m3 */ + <4 RK_PB1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m3 */ + <4 RK_PB0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins = + /* i2c6_scl_m4 */ + <3 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m4 */ + <3 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins = + /* i2c7_scl_m2 */ + <3 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m2 */ + <3 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins = + /* i2c7_scl_m3 */ + <4 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m3 */ + <4 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins = + /* i2c8_scl_m0 */ + <4 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m0 */ + <4 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins = + /* i2c8_scl_m2 */ + <1 RK_PD6 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m2 */ + <1 RK_PD7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins = + /* i2c8_scl_m3 */ + <4 RK_PC0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m3 */ + <4 RK_PC1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0_lrck: i2s0-lrck { + rockchip,pins = + /* i2s0_lrck */ + <1 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_mclk: i2s0-mclk { + rockchip,pins = + /* i2s0_mclk */ + <1 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sclk: i2s0-sclk { + rockchip,pins = + /* i2s0_sclk */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins = + /* i2s0_sdi0 */ + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins = + /* i2s0_sdi1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins = + /* i2s0_sdi2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins = + /* i2s0_sdi3 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins = + /* i2s0_sdo0 */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins = + /* i2s0_sdo1 */ + <1 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins = + /* i2s0_sdo2 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins = + /* i2s0_sdo3 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1m0_lrck */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1m0_sclk */ + <4 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <4 RK_PA5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1m1_lrck */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1m1_sclk */ + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <0 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <0 RK_PD2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <0 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2m1_sclk */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3_lrck: i2s3-lrck { + rockchip,pins = + /* i2s3_lrck */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_mclk: i2s3-mclk { + rockchip,pins = + /* i2s3_mclk */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sclk: i2s3-sclk { + rockchip,pins = + /* i2s3_sclk */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdi: i2s3-sdi { + rockchip,pins = + /* i2s3_sdi */ + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdo: i2s3-sdo { + rockchip,pins = + /* i2s3_sdo */ + <3 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <4 RK_PD2 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <4 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <4 RK_PD0 5 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <4 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2_pins: jtagm2-pins { + rockchip,pins = + /* jtag_tck_m2 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + litcpu { + /omit-if-no-ref/ + litcpu_pins: litcpu-pins { + rockchip,pins = + /* litcpu_avs */ + <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcum0_pins: mcum0-pins { + rockchip,pins = + /* mcu_jtag_tck_m0 */ + <4 RK_PD4 5 &pcfg_pull_none>, + /* mcu_jtag_tms_m0 */ + <4 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mcum1_pins: mcum1-pins { + rockchip,pins = + /* mcu_jtag_tck_m1 */ + <3 RK_PD4 6 &pcfg_pull_none>, + /* mcu_jtag_tms_m1 */ + <3 RK_PD5 6 &pcfg_pull_none>; + }; + }; + + mipi { + /omit-if-no-ref/ + mipim0_camera0_clk: mipim0-camera0-clk { + rockchip,pins = + /* mipim0_camera0_clk */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera1_clk: mipim0-camera1-clk { + rockchip,pins = + /* mipim0_camera1_clk */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera2_clk: mipim0-camera2-clk { + rockchip,pins = + /* mipim0_camera2_clk */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera3_clk: mipim0-camera3-clk { + rockchip,pins = + /* mipim0_camera3_clk */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera4_clk: mipim0-camera4-clk { + rockchip,pins = + /* mipim0_camera4_clk */ + <1 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera0_clk: mipim1-camera0-clk { + rockchip,pins = + /* mipim1_camera0_clk */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera1_clk: mipim1-camera1-clk { + rockchip,pins = + /* mipim1_camera1_clk */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera2_clk: mipim1-camera2-clk { + rockchip,pins = + /* mipim1_camera2_clk */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera3_clk: mipim1-camera3-clk { + rockchip,pins = + /* mipim1_camera3_clk */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera4_clk: mipim1-camera4-clk { + rockchip,pins = + /* mipim1_camera4_clk */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te0: mipi-te0 { + rockchip,pins = + /* mipi_te0 */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te1: mipi-te1 { + rockchip,pins = + /* mipi_te1 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + /omit-if-no-ref/ + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m0 */ + <3 RK_PC7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m0 */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m1 */ + <4 RK_PC1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins = + /* pcie20x1_2_button_rstn */ + <4 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + /omit-if-no-ref/ + pcie30phy_pins: pcie30phy-pins { + rockchip,pins = + /* pcie30phy_dtb0 */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* pcie30phy_dtb1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m0 */ + <0 RK_PC0 12 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m0 */ + <0 RK_PC5 12 &pcfg_pull_none>, + /* pcie30x1_0_waken_m0 */ + <0 RK_PC4 12 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m0 */ + <0 RK_PB5 12 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m0 */ + <0 RK_PB7 12 &pcfg_pull_none>, + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m1 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m1 */ + <4 RK_PA4 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m1 */ + <4 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m1 */ + <4 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m2 */ + <1 RK_PB5 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m2 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m2 */ + <1 RK_PB3 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m2 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m2 */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins = + /* pcie30x1_0_button_rstn */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins = + /* pcie30x1_1_button_rstn */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m0 */ + <0 RK_PD1 12 &pcfg_pull_none>, + /* pcie30x2_perstn_m0 */ + <0 RK_PD4 12 &pcfg_pull_none>, + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m2 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m2 */ + <3 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m3 */ + <1 RK_PD7 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m3 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins = + /* pcie30x2_button_rstn */ + <3 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + /omit-if-no-ref/ + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m0 */ + <0 RK_PC6 12 &pcfg_pull_none>, + /* pcie30x4_perstn_m0 */ + <0 RK_PD0 12 &pcfg_pull_none>, + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m1 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m2 */ + <3 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m2 */ + <3 RK_PC6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m3 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m3 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins = + /* pcie30x4_button_rstn */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + /omit-if-no-ref/ + pdm0m0_clk: pdm0m0-clk { + rockchip,pins = + /* pdm0_clk0_m0 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins = + /* pdm0m0_clk1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins = + /* pdm0m0_sdi0 */ + <1 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins = + /* pdm0m0_sdi1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins = + /* pdm0m0_sdi2 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins = + /* pdm0m0_sdi3 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm0m1_clk: pdm0m1-clk { + rockchip,pins = + /* pdm0_clk0_m1 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins = + /* pdm0m1_clk1 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins = + /* pdm0m1_sdi0 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins = + /* pdm0m1_sdi1 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins = + /* pdm0m1_sdi2 */ + <0 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins = + /* pdm0m1_sdi3 */ + <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + /omit-if-no-ref/ + pdm1m0_clk: pdm1m0-clk { + rockchip,pins = + /* pdm1_clk0_m0 */ + <4 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins = + /* pdm1m0_clk1 */ + <4 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins = + /* pdm1m0_sdi0 */ + <4 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins = + /* pdm1m0_sdi1 */ + <4 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins = + /* pdm1m0_sdi2 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins = + /* pdm1m0_sdi3 */ + <4 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm1m1_clk: pdm1m1-clk { + rockchip,pins = + /* pdm1_clk0_m1 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins = + /* pdm1m1_clk1 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins = + /* pdm1m1_sdi0 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins = + /* pdm1m1_sdi1 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins = + /* pdm1m1_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins = + /* pdm1m1_sdi3 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_int_l */ + <0 RK_PA7 0 &pcfg_pull_up>, + /* pmic_sleep1 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pmic_sleep2 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pmic_sleep3 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* pmic_sleep4 */ + <0 RK_PC2 1 &pcfg_pull_none>, + /* pmic_sleep5 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pmic_sleep6 */ + <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m2_pins: pwm0m2-pins { + rockchip,pins = + /* pwm0_m2 */ + <1 RK_PA2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m2_pins: pwm1m2-pins { + rockchip,pins = + /* pwm1_m2 */ + <1 RK_PA3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <3 RK_PB1 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_ir_m0 */ + <0 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_ir_m1 */ + <3 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m2_pins: pwm3m2-pins { + rockchip,pins = + /* pwm3_ir_m2 */ + <1 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m3_pins: pwm3m3-pins { + rockchip,pins = + /* pwm3_ir_m3 */ + <1 RK_PA7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <0 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <4 RK_PC1 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_ir_m0 */ + <0 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_ir_m1 */ + <4 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m2_pins: pwm7m2-pins { + rockchip,pins = + /* pwm7_ir_m2 */ + <1 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <4 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m2_pins: pwm8m2-pins { + rockchip,pins = + /* pwm8_m2 */ + <3 RK_PD0 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <4 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m2_pins: pwm9m2-pins { + rockchip,pins = + /* pwm9_m2 */ + <3 RK_PD1 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PA0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <4 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m2_pins: pwm10m2-pins { + rockchip,pins = + /* pwm10_m2 */ + <3 RK_PD3 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_ir_m0 */ + <3 RK_PA1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_ir_m1 */ + <4 RK_PB4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m2_pins: pwm11m2-pins { + rockchip,pins = + /* pwm11_ir_m2 */ + <1 RK_PC4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m3_pins: pwm11m3-pins { + rockchip,pins = + /* pwm11_ir_m3 */ + <3 RK_PD5 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PB5 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m2_pins: pwm13m2-pins { + rockchip,pins = + /* pwm13_m2 */ + <1 RK_PB7 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m2_pins: pwm14m2-pins { + rockchip,pins = + /* pwm14_m2 */ + <1 RK_PD6 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_ir_m0 */ + <3 RK_PC3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_ir_m1 */ + <4 RK_PB3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m2_pins: pwm15m2-pins { + rockchip,pins = + /* pwm15_ir_m2 */ + <1 RK_PC6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m3_pins: pwm15m3-pins { + rockchip,pins = + /* pwm15_ir_m3 */ + <1 RK_PD7 11 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cp_pod */ + <0 RK_PC6 13 &pcfg_pull_none>, + /* sata_cpdet */ + <0 RK_PD4 13 &pcfg_pull_none>, + /* sata_mp_switch */ + <0 RK_PD5 13 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0m0_pins: sata0m0-pins { + rockchip,pins = + /* sata0_act_led_m0 */ + <4 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata0m1_pins: sata0m1-pins { + rockchip,pins = + /* sata0_act_led_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1m0_pins: sata1m0-pins { + rockchip,pins = + /* sata1_act_led_m0 */ + <4 RK_PB5 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata1m1_pins: sata1m1-pins { + rockchip,pins = + /* sata1_act_led_m1 */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2m0_pins: sata2m0-pins { + rockchip,pins = + /* sata2_act_led_m0 */ + <4 RK_PB1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata2m1_pins: sata2m1-pins { + rockchip,pins = + /* sata2_act_led_m1 */ + <1 RK_PB7 6 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom1_pins: sdiom1-pins { + rockchip,pins = + /* sdio_clk_m1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* sdio_cmd_m1 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* sdio_d0_m1 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* sdio_d1_m1 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* sdio_d2_m1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* sdio_d3_m1 */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + /omit-if-no-ref/ + spdif0m0_tx: spdif0m0-tx { + rockchip,pins = + /* spdif0m0_tx */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif0m1_tx: spdif0m1-tx { + rockchip,pins = + /* spdif0m1_tx */ + <4 RK_PB4 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + /omit-if-no-ref/ + spdif1m0_tx: spdif1m0-tx { + rockchip,pins = + /* spdif1m0_tx */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m1_tx: spdif1m1-tx { + rockchip,pins = + /* spdif1m1_tx */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m2_tx: spdif1m2-tx { + rockchip,pins = + /* spdif1m2_tx */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0_m0 */ + <0 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1_m0 */ + <0 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0_m1 */ + <4 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1_m1 */ + <4 RK_PB1 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m2_pins: spi0m2-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + /* spi0_cs0_m2 */ + <1 RK_PB4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins = + /* spi0_cs1_m2 */ + <1 RK_PB5 8 &pcfg_pull_up_drv_level_1>; + }; + /omit-if-no-ref/ + spi0m3_pins: spi0m3-pins { + rockchip,pins = + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_up_drv_level_1>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins = + /* spi0_cs0_m3 */ + <3 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins = + /* spi0_cs1_m3 */ + <3 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0_m1 */ + <3 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins = + /* spi1_cs1_m1 */ + <3 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_pins: spi1m2-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins = + /* spi1_cs0_m2 */ + <1 RK_PD3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins = + /* spi1_cs1_m2 */ + <1 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0_m0 */ + <1 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1_m0 */ + <1 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0_m1 */ + <4 RK_PA7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1_m1 */ + <4 RK_PB0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_pins: spi2m2-pins { + rockchip,pins = + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins = + /* spi2_cs0_m2 */ + <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins = + /* spi2_cs1_m2 */ + <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0_m1 */ + <4 RK_PC0 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1_m1 */ + <4 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_pins: spi3m2-pins { + rockchip,pins = + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins = + /* spi3_cs0_m2 */ + <0 RK_PD4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins = + /* spi3_cs1_m2 */ + <0 RK_PD5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_pins: spi3m3-pins { + rockchip,pins = + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins = + /* spi3_cs0_m3 */ + <3 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins = + /* spi3_cs1_m3 */ + <3 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi4 { + /omit-if-no-ref/ + spi4m0_pins: spi4m0-pins { + rockchip,pins = + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins = + /* spi4_cs0_m0 */ + <1 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins = + /* spi4_cs1_m0 */ + <1 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_pins: spi4m1-pins { + rockchip,pins = + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins = + /* spi4_cs0_m1 */ + <3 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins = + /* spi4_cs1_m1 */ + <3 RK_PA4 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_pins: spi4m2-pins { + rockchip,pins = + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_up_drv_level_1>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_up_drv_level_1>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins = + /* spi4_cs0_m2 */ + <1 RK_PA3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut: tsadc-shut { + rockchip,pins = + /* tsadc_shut */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB0 4 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <4 RK_PA4 10 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <4 RK_PA3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PB7 10 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB6 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PD7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PD6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <0 RK_PD2 10 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <0 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <0 RK_PD0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <0 RK_PC7 10 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB6 10 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <4 RK_PD1 10 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <4 RK_PD0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <3 RK_PB2 10 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <3 RK_PB1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2_ctsn: uart2-ctsn { + rockchip,pins = + /* uart2_ctsn */ + <3 RK_PB4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2_rtsn: uart2-rtsn { + rockchip,pins = + /* uart2_rtsn */ + <3 RK_PB3 10 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <1 RK_PC0 10 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <1 RK_PC1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PB6 10 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <4 RK_PA6 10 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <4 RK_PA5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <1 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <1 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <1 RK_PD3 10 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <1 RK_PD2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <3 RK_PD0 10 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <3 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PB2 10 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PB3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <1 RK_PC7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <1 RK_PC5 10 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <4 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <4 RK_PD2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <4 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PC5 10 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PC4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <2 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <2 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PD5 10 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <1 RK_PA0 10 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <1 RK_PA1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <1 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <1 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m2_xfer: uart6m2-xfer { + rockchip,pins = + /* uart6_rx_m2 */ + <1 RK_PD1 10 &pcfg_pull_up>, + /* uart6_tx_m2 */ + <1 RK_PD0 10 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <3 RK_PC1 10 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <3 RK_PC0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <3 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <3 RK_PC2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rx_m2 */ + <1 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m2 */ + <1 RK_PB5 10 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <4 RK_PB1 10 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <4 RK_PB0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <4 RK_PB3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <4 RK_PB2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PA3 10 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PA2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PA5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <3 RK_PA4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8_xfer: uart8-xfer { + rockchip,pins = + /* uart8_rx_ */ + <4 RK_PB1 10 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <4 RK_PB5 10 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <4 RK_PB4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins = + /* uart9m1_ctsn */ + <4 RK_PA1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins = + /* uart9m1_rtsn */ + <4 RK_PA0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rx_m2 */ + <3 RK_PD4 10 &pcfg_pull_up>, + /* uart9_tx_m2 */ + <3 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins = + /* uart9m2_ctsn */ + <3 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins = + /* uart9m2_rtsn */ + <3 RK_PD2 10 &pcfg_pull_none>; + }; + }; + + vop { + /omit-if-no-ref/ + vop_pins: vop-pins { + rockchip,pins = + /* vop_post_empty */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + bt656 { + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts new file mode 100644 index 000000000000..4b39df415a90 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5-io.dts @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include "rk3588s-radxa-cm5.dtsi" + +/ { + model = "Radxa CM5 IO"; + compatible = "radxa,cm5-io", "radxa,cm5", "rockchip,rk3588s"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + user-led1 { + gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vbus5v0_typec_en>; + enable-active-high; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie2x1l0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302 { + vbus5v0_typec_en: vbus5v0-typec-en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm4m0_pins>; + status = "okay"; +}; + +&pwm11 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +&sdhci { + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie2x1l0>; + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,sel-pipe-phystatus; + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi new file mode 100644 index 000000000000..2bb75225443e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-radxa-cm5.dtsi @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/input/input.h> +#include "rk3588s.dtsi" + +/ { + compatible = "radxa,cm5", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + serial2 = &uart2; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x41>; + rx_delay = <0x3a>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + max-frequency = <150000000>; + mmc-hs200-1_8v; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts new file mode 100644 index 000000000000..6d73f2016eb8 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -0,0 +1,773 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include "rk3588s.dtsi" + +/ { + model = "Radxa ROCK 5 Model A"; + compatible = "radxa,rock-5a", "rockchip,rk3588s"; + + aliases { + mmc0 = &sdhci; + serial2 = &uart2; + }; + + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&io_led>; + + io-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&gmac1 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + pinctrl-names = "default"; + tx_delay = <0x3a>; + rx_delay = <0x3e>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + leds { + io_led: io-led { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifibt { + wl_reset: wl-reset { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wl_dis: wl-dis { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_dis: bt-dis { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host2_xhci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi new file mode 100644 index 000000000000..ac7a8329e5f9 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -0,0 +1,3188 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include <dt-bindings/clock/rockchip,rk3588-cru.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/power/rk3588-power.h> +#include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &sfc; + pwm0 = &pwm0; + pwm1 = &pwm1; + pwm2 = &pwm2; + pwm3 = &pwm3; + pwm4 = &pwm4; + pwm5 = &pwm5; + pwm6 = &pwm6; + pwm7 = &pwm7; + pwm8 = &pwm8; + pwm9 = &pwm9; + pwm10 = &pwm10; + pwm11 = &pwm11; + pwm12 = &pwm12; + pwm13 = &pwm13; + pwm14 = &pwm14; + pwm15 = &pwm15; + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; +// hdmi0 = &hdmi0; +// dp0 = &dp0; +// edp0 = &edp0; +// hdptx0 = &hdptxphy0; +// hdptxhdmi0 = &hdptxphy_hdmi0; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + +/* + spll: spll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <702000000>; + clock-output-names = "spll"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; +*/ + + hclk_vo1: hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_vo0: hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_usb: hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_nvm: hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c087c 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_NVM_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_usb: aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_isp1_pre: hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VI_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_isp1_pre: aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VI_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_RKVENC0>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_RKVENC0>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VOP_LOW_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_av1_pre: pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_av1_pre: aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_sdio_pre: hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c092c 0 0x10>; + clock-names = "link"; + clocks = <&hclk_nvm>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_vo0_grf: pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x4>; + clocks = <&hclk_vo0>; + clock-names = "link"; + #clock-cells = <0>; + }; + + pclk_vo1_grf: pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x4>; + clocks = <&hclk_vo1>; + clock-names = "link"; + #clock-cells = <0>; + }; + }; + + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <775000 775000 950000>, + <775000 775000 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <825000 825000 950000>, + <825000 825000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,grf = <&bigcore0_grf>; + rockchip,volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + + rockchip,reboot-freq = <1800000000>; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <625000 625000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <650000 650000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <775000 775000 1000000>, + <775000 775000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,grf = <&bigcore1_grf>; + rockchip,volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + + rockchip,reboot-freq = <1800000000>; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <600000 600000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <625000 625000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <650000 650000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <775000 775000 1000000>, + <775000 775000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; + assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + dynamic-power-coefficient = <228>; + #cooling-cells = <2>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; + assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + dynamic-power-coefficient = <416>; + #cooling-cells = <2>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-level = <3>; + cache-unified; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + spll: clock-0 { + compatible = "fixed-clock"; + clock-frequency = <702000000>; + clock-output-names = "spll"; + #clock-cells = <0>; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <2100>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&soc_target>; + cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 1>; + + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + b0_target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&b0_target>; + cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + bigcore1_thermal: bigcore1-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 2>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + b1_target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&b1_target>; + cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + little_core_thermal: littlecore-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 3>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + l0_target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&l0_target>; + cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + center_thermal: center-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 4>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 5>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 6>; + trips { + trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + trip-point-2 { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; + + xin24m: clock-1 { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: clock-2 { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + pmu_sram: sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + ranges = <0 0x0 0x0010f000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + usb_host0_xhci: usb@fc000000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + status = "disabled"; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + }; + + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + }; + + bigcore1_grf: syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&cru PCLK_VO0GRF>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + system_sram1: sram@fd600000 { + compatible = "mmio-sram"; + reg = <0x0 0xfd600000 0x0 0x100000>; + ranges = <0x0 0x0 0xfd600000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <800000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, <500000000>, + <375000000>, <150000000>, + <200000000>; + rockchip,grf = <&php_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-0 = <&i2c0m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart0m1_xfer>; + pinctrl-names = "default"; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm0m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm1m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm2m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm3m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #address-cells = <1>; + #power-domain-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = <RK3588_PD_NPU>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = <RK3588_PD_NPUTOP>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPU1 { + reg = <RK3588_PD_NPU1>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_NPU2 { + reg = <RK3588_PD_NPU2>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu2>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = <RK3588_PD_GPU>; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + #power-domain-cells = <0>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = <RK3588_PD_VCODEC>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VENC0 { + reg = <RK3588_PD_VENC0>; + clocks = <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VENC1 { + reg = <RK3588_PD_VENC1>; + clocks = <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + #power-domain-cells = <0>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = <RK3588_PD_VDPU>; + clocks = <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + + power-domain@RK3588_PD_AV1 { + reg = <RK3588_PD_AV1>; + clocks = <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos = <&qos_av1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg = <RK3588_PD_RKVDEC0>; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos = <&qos_rkvdec0>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = <RK3588_PD_RKVDEC1>; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos = <&qos_rkvdec1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_RGA30 { + reg = <RK3588_PD_RGA30>; + clocks = <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos = <&qos_rga3_0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = <RK3588_PD_VOP>; + clocks = <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_VO0 { + reg = <RK3588_PD_VO0>; + clocks = <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos = <&qos_hdcp0>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg = <RK3588_PD_VO1>; + clocks = <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_VI { + reg = <RK3588_PD_VI>; + clocks = <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <0>; + + power-domain@RK3588_PD_ISP1 { + reg = <RK3588_PD_ISP1>; + clocks = <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_FEC { + reg = <RK3588_PD_FEC>; + clocks = <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + #power-domain-cells = <0>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = <RK3588_PD_RGA31>; + clocks = <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos = <&qos_rga3_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_USB { + reg = <RK3588_PD_USB>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB_ROOT>, + <&cru HCLK_USB_ROOT>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_GMAC { + reg = <RK3588_PD_GMAC>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_PCIE { + reg = <RK3588_PD_PCIE>; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDIO { + reg = <RK3588_PD_SDIO>; + clocks = <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_AUDIO { + reg = <RK3588_PD_AUDIO>; + clocks = <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + #power-domain-cells = <0>; + }; + power-domain@RK3588_PD_SDMMC { + reg = <RK3588_PD_SDMMC>; + pm_qos = <&qos_sdmmc>; + #power-domain-cells = <0>; + }; + }; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "rockchip,rk3588-qos", "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq", "eth_wake_irq"; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + power-domains = <&power RK3588_PD_GMAC>; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + rockchip,grf = <&sys_grf>; + rockchip,php-grf = <&php_grf>; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mixed-burst; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + snps,tso; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x00 0xfe2d0000 0x00 0x4000>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, + <&emmc_cmd>, <&emmc_data_strobe>; + pinctrl-names = "default"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,trcm-sync-tx-only; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3_lrck + &i2s3_sclk + &i2s3_sdi + &i2s3_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-controller; + mbi-alias = <0x0 0xfe610000>; + mbi-ranges = <424 56>; + msi-controller; + ranges; + #address-cells = <2>; + #interrupt-cells = <4>; + #size-cells = <2>; + + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe640000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfe660000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + + ppi-partitions { + ppi_partition0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_partition1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>; + }; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c1m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c2m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c3m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c4m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c5m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + timer0: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "rockchip,rk3588-wdt", "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart1m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart2m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac0 12>, <&dmac0 13>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart3m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 9>, <&dmac1 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart4m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 11>, <&dmac1 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart5m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac1 13>, <&dmac1 14>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart6m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 7>, <&dmac2 8>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart7m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 9>, <&dmac2 10>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart8m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac2 11>, <&dmac2 12>; + dma-names = "tx", "rx"; + pinctrl-0 = <&uart9m1_xfer>; + pinctrl-names = "default"; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm4m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm5m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm6m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm7m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm8m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm9m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm10m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm11m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm12m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm13m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm14m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + pinctrl-0 = <&pwm15m0_pins>; + pinctrl-names = "default"; + #pwm-cells = <3>; + status = "disabled"; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; + reset-names = "tsadc-apb", "tsadc"; + rockchip,grf = <&sys_grf>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + pinctrl-names = "gpio", "otpout"; + #thermal-sensor-cells = <1>; + }; + + saradc: adc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c6m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c7m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&i2c8m0_xfer>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + num-cs = <2>; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: efuse@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>; + clock-names = "otp", "apb_pclk", "phy", "arb"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otp", "apb", "arb"; + #address-cells = <1>; + #size-cells = <1>; + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + + otp_id: id@7 { + reg = <0x07 0x10>; + }; + + cpub0_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + + cpub1_leakage: cpu-leakage@18 { + reg = <0x18 0x1>; + }; + + cpul_leakage: cpu-leakage@19 { + reg = <0x19 0x1>; + }; + + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: usb3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + + system_sram2: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + ranges = <0x0 0x0 0xff001000 0xef000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + ranges; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + }; + + av1d: av1d@fdc70000 { + compatible = "rockchip,rk3588-av1-vpu"; + reg = <0x0 0xfdc70000 0x0 0x800>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "vdpu"; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "hclk"; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>; + power-domains = <&power RK3588_PD_AV1>; + status = "disabled"; + }; +}; + +#include "rk3588s-pinctrl.dtsi" diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c index b87ea7148b58..4b011f7eddec 100644 --- a/drivers/iio/adc/rockchip_saradc.c +++ b/drivers/iio/adc/rockchip_saradc.c @@ -4,7 +4,9 @@ * Copyright (C) 2014 ROCKCHIP, Inc. */ +#include <linux/bitfield.h> #include <linux/module.h> +#include <linux/mutex.h> #include <linux/platform_device.h> #include <linux/interrupt.h> #include <linux/io.h> @@ -37,10 +39,31 @@ #define SARADC_TIMEOUT msecs_to_jiffies(100) #define SARADC_MAX_CHANNELS 8 +/* v2 registers */ +#define SARADC2_CONV_CON 0x000 +#define SARADC_T_PD_SOC 0x004 +#define SARADC_T_DAS_SOC 0x00c +#define SARADC2_END_INT_EN 0x104 +#define SARADC2_ST_CON 0x108 +#define SARADC2_STATUS 0x10c +#define SARADC2_END_INT_ST 0x110 +#define SARADC2_DATA_BASE 0x120 + +#define SARADC2_EN_END_INT BIT(0) +#define SARADC2_START BIT(4) +#define SARADC2_SINGLE_MODE BIT(5) + +#define SARADC2_CONV_CHANNELS GENMASK(15, 0) + +struct rockchip_saradc; + struct rockchip_saradc_data { const struct iio_chan_spec *channels; int num_channels; unsigned long clk_rate; + void (*start)(struct rockchip_saradc *info, int chn); + int (*read)(struct rockchip_saradc *info); + void (*power_down)(struct rockchip_saradc *info); }; struct rockchip_saradc { @@ -49,6 +72,8 @@ struct rockchip_saradc { struct clk *clk; struct completion completion; struct regulator *vref; + /* lock to protect against multiple access to the device */ + struct mutex lock; int uv_vref; struct reset_control *reset; const struct rockchip_saradc_data *data; @@ -57,27 +82,81 @@ struct rockchip_saradc { struct notifier_block nb; }; -static void rockchip_saradc_power_down(struct rockchip_saradc *info) +static void rockchip_saradc_reset_controller(struct reset_control *reset); + +static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn) +{ + /* 8 clock periods as delay between power up and start cmd */ + writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); + /* Select the channel to be used and trigger conversion */ + writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) | + SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL); +} + +static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn) +{ + int val; + + if (info->reset) + rockchip_saradc_reset_controller(info->reset); + + writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC); + writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC); + val = FIELD_PREP(SARADC2_EN_END_INT, 1); + val |= val << 16; + writel_relaxed(val, info->regs + SARADC2_END_INT_EN); + val = FIELD_PREP(SARADC2_START, 1) | + FIELD_PREP(SARADC2_SINGLE_MODE, 1) | + FIELD_PREP(SARADC2_CONV_CHANNELS, chn); + val |= val << 16; + writel(val, info->regs + SARADC2_CONV_CON); +} + +static void rockchip_saradc_start(struct rockchip_saradc *info, int chn) +{ + info->data->start(info, chn); +} + +static int rockchip_saradc_read_v1(struct rockchip_saradc *info) +{ + return readl_relaxed(info->regs + SARADC_DATA); +} + +static int rockchip_saradc_read_v2(struct rockchip_saradc *info) +{ + int offset; + + /* Clear irq */ + writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST); + + offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4; + + return readl_relaxed(info->regs + offset); +} + +static int rockchip_saradc_read(struct rockchip_saradc *info) +{ + return info->data->read(info); +} + +static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info) { - /* Clear irq & power down adc */ writel_relaxed(0, info->regs + SARADC_CTRL); } +static void rockchip_saradc_power_down(struct rockchip_saradc *info) +{ + if (info->data->power_down) + info->data->power_down(info); +} + static int rockchip_saradc_conversion(struct rockchip_saradc *info, - struct iio_chan_spec const *chan) + struct iio_chan_spec const *chan) { reinit_completion(&info->completion); - /* 8 clock periods as delay between power up and start cmd */ - writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC); - info->last_chan = chan; - - /* Select the channel to be used and trigger conversion */ - writel(SARADC_CTRL_POWER_CTRL - | (chan->channel & SARADC_CTRL_CHN_MASK) - | SARADC_CTRL_IRQ_ENABLE, - info->regs + SARADC_CTRL); + rockchip_saradc_start(info, chan->channel); if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT)) return -ETIMEDOUT; @@ -94,17 +173,17 @@ static int rockchip_saradc_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_RAW: - mutex_lock(&indio_dev->mlock); + mutex_lock(&info->lock); ret = rockchip_saradc_conversion(info, chan); if (ret) { rockchip_saradc_power_down(info); - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&info->lock); return ret; } *val = info->last_val; - mutex_unlock(&indio_dev->mlock); + mutex_unlock(&info->lock); return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: *val = info->uv_vref / 1000; @@ -120,7 +199,7 @@ static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id) struct rockchip_saradc *info = dev_id; /* Read value */ - info->last_val = readl_relaxed(info->regs + SARADC_DATA); + info->last_val = rockchip_saradc_read(info); info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0); rockchip_saradc_power_down(info); @@ -160,6 +239,9 @@ static const struct rockchip_saradc_data saradc_data = { .channels = rockchip_saradc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels), .clk_rate = 1000000, + .start = rockchip_saradc_start_v1, + .read = rockchip_saradc_read_v1, + .power_down = rockchip_saradc_power_down_v1, }; static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = { @@ -171,6 +253,9 @@ static const struct rockchip_saradc_data rk3066_tsadc_data = { .channels = rockchip_rk3066_tsadc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels), .clk_rate = 50000, + .start = rockchip_saradc_start_v1, + .read = rockchip_saradc_read_v1, + .power_down = rockchip_saradc_power_down_v1, }; static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = { @@ -186,6 +271,9 @@ static const struct rockchip_saradc_data rk3399_saradc_data = { .channels = rockchip_rk3399_saradc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels), .clk_rate = 1000000, + .start = rockchip_saradc_start_v1, + .read = rockchip_saradc_read_v1, + .power_down = rockchip_saradc_power_down_v1, }; static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = { @@ -203,6 +291,28 @@ static const struct rockchip_saradc_data rk3568_saradc_data = { .channels = rockchip_rk3568_saradc_iio_channels, .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels), .clk_rate = 1000000, + .start = rockchip_saradc_start_v1, + .read = rockchip_saradc_read_v1, + .power_down = rockchip_saradc_power_down_v1, +}; + +static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = { + SARADC_CHANNEL(0, "adc0", 12), + SARADC_CHANNEL(1, "adc1", 12), + SARADC_CHANNEL(2, "adc2", 12), + SARADC_CHANNEL(3, "adc3", 12), + SARADC_CHANNEL(4, "adc4", 12), + SARADC_CHANNEL(5, "adc5", 12), + SARADC_CHANNEL(6, "adc6", 12), + SARADC_CHANNEL(7, "adc7", 12), +}; + +static const struct rockchip_saradc_data rk3588_saradc_data = { + .channels = rockchip_rk3588_saradc_iio_channels, + .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels), + .clk_rate = 1000000, + .start = rockchip_saradc_start_v2, + .read = rockchip_saradc_read_v2, }; static const struct of_device_id rockchip_saradc_match[] = { @@ -218,6 +328,9 @@ static const struct of_device_id rockchip_saradc_match[] = { }, { .compatible = "rockchip,rk3568-saradc", .data = &rk3568_saradc_data, + }, { + .compatible = "rockchip,rk3588-saradc", + .data = &rk3588_saradc_data, }, {}, }; @@ -233,20 +346,6 @@ static void rockchip_saradc_reset_controller(struct reset_control *reset) reset_control_deassert(reset); } -static void rockchip_saradc_clk_disable(void *data) -{ - struct rockchip_saradc *info = data; - - clk_disable_unprepare(info->clk); -} - -static void rockchip_saradc_pclk_disable(void *data) -{ - struct rockchip_saradc *info = data; - - clk_disable_unprepare(info->pclk); -} - static void rockchip_saradc_regulator_disable(void *data) { struct rockchip_saradc *info = data; @@ -270,7 +369,7 @@ static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) int ret; int i, j = 0; - mutex_lock(&i_dev->mlock); + mutex_lock(&info->lock); for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) { const struct iio_chan_spec *chan = &i_dev->channels[i]; @@ -287,7 +386,7 @@ static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p) iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev)); out: - mutex_unlock(&i_dev->mlock); + mutex_unlock(&info->lock); iio_trigger_notify_done(i_dev->trig); @@ -295,8 +394,7 @@ out: } static int rockchip_saradc_volt_notify(struct notifier_block *nb, - unsigned long event, - void *data) + unsigned long event, void *data) { struct rockchip_saradc *info = container_of(nb, struct rockchip_saradc, nb); @@ -316,10 +414,10 @@ static void rockchip_saradc_regulator_unreg_notifier(void *data) static int rockchip_saradc_probe(struct platform_device *pdev) { + const struct rockchip_saradc_data *match_data; struct rockchip_saradc *info = NULL; struct device_node *np = pdev->dev.of_node; struct iio_dev *indio_dev = NULL; - const struct of_device_id *match; int ret; int irq; @@ -327,25 +425,23 @@ static int rockchip_saradc_probe(struct platform_device *pdev) return -ENODEV; indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); - if (!indio_dev) { - dev_err(&pdev->dev, "failed allocating iio device\n"); - return -ENOMEM; - } + if (!indio_dev) + return dev_err_probe(&pdev->dev, -ENOMEM, + "failed allocating iio device\n"); + info = iio_priv(indio_dev); - match = of_match_device(rockchip_saradc_match, &pdev->dev); - if (!match) { - dev_err(&pdev->dev, "failed to match device\n"); - return -ENODEV; - } + match_data = of_device_get_match_data(&pdev->dev); + if (!match_data) + return dev_err_probe(&pdev->dev, -ENODEV, + "failed to match device\n"); - info->data = match->data; + info->data = match_data; /* Sanity check for possible later IP variants with more channels */ - if (info->data->num_channels > SARADC_MAX_CHANNELS) { - dev_err(&pdev->dev, "max channels exceeded"); - return -EINVAL; - } + if (info->data->num_channels > SARADC_MAX_CHANNELS) + return dev_err_probe(&pdev->dev, -EINVAL, + "max channels exceeded"); info->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(info->regs)) @@ -380,16 +476,6 @@ static int rockchip_saradc_probe(struct platform_device *pdev) return ret; } - info->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); - if (IS_ERR(info->pclk)) - return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), - "failed to get pclk\n"); - - info->clk = devm_clk_get(&pdev->dev, "saradc"); - if (IS_ERR(info->clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), - "failed to get adc clock\n"); - info->vref = devm_regulator_get(&pdev->dev, "vref"); if (IS_ERR(info->vref)) return dev_err_probe(&pdev->dev, PTR_ERR(info->vref), @@ -403,23 +489,20 @@ static int rockchip_saradc_probe(struct platform_device *pdev) * This may become user-configurable in the future. */ ret = clk_set_rate(info->clk, info->data->clk_rate); - if (ret < 0) { - dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed to set adc clk rate\n"); ret = regulator_enable(info->vref); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable vref regulator\n"); - return ret; - } + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed to enable vref regulator\n"); + ret = devm_add_action_or_reset(&pdev->dev, rockchip_saradc_regulator_disable, info); - if (ret) { - dev_err(&pdev->dev, "failed to register devm action, %d\n", - ret); - return ret; - } + if (ret) + return dev_err_probe(&pdev->dev, ret, + "failed to register devm action\n"); ret = regulator_get_voltage(info->vref); if (ret < 0) @@ -427,31 +510,15 @@ static int rockchip_saradc_probe(struct platform_device *pdev) info->uv_vref = ret; - ret = clk_prepare_enable(info->pclk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable pclk\n"); - return ret; - } - ret = devm_add_action_or_reset(&pdev->dev, - rockchip_saradc_pclk_disable, info); - if (ret) { - dev_err(&pdev->dev, "failed to register devm action, %d\n", - ret); - return ret; - } + info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); + if (IS_ERR(info->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk), + "failed to get pclk\n"); - ret = clk_prepare_enable(info->clk); - if (ret < 0) { - dev_err(&pdev->dev, "failed to enable converter clock\n"); - return ret; - } - ret = devm_add_action_or_reset(&pdev->dev, - rockchip_saradc_clk_disable, info); - if (ret) { - dev_err(&pdev->dev, "failed to register devm action, %d\n", - ret); - return ret; - } + info->clk = devm_clk_get_enabled(&pdev->dev, "saradc"); + if (IS_ERR(info->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(info->clk), + "failed to get adc clock\n"); platform_set_drvdata(pdev, indio_dev); @@ -478,6 +545,8 @@ static int rockchip_saradc_probe(struct platform_device *pdev) if (ret) return ret; + mutex_init(&info->lock); + return devm_iio_device_register(&pdev->dev, indio_dev); } diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index f268f9c04a1c..3d5fb0b78cda 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2204,7 +2204,9 @@ static struct page *its_allocate_prop_table(gfp_t gfp_flags) { struct page *prop_page; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) gfp_flags |= GFP_DMA32; prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ)); @@ -2343,7 +2345,9 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser, } gfp_flags = GFP_KERNEL | __GFP_ZERO; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) gfp_flags |= GFP_DMA32; page = alloc_pages_node(its->numa_node, gfp_flags, order); @@ -2984,7 +2988,9 @@ static struct page *its_allocate_pending_table(gfp_t gfp_flags) { struct page *pend_page; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) gfp_flags |= GFP_DMA32; pend_page = alloc_pages(gfp_flags | __GFP_ZERO, get_order(LPI_PENDBASE_SZ)); @@ -3142,8 +3148,8 @@ static void its_cpu_init_lpis(void) tmp = gicr_read_propbaser(rbase + GICR_PROPBASER); if (of_machine_is_compatible("rockchip,rk3568") || - of_machine_is_compatible("rockchip,rk3566") || - of_machine_is_compatible("rockchip,rk3588")) + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK; if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) { @@ -3171,8 +3177,8 @@ static void its_cpu_init_lpis(void) tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER); if (of_machine_is_compatible("rockchip,rk3568") || - of_machine_is_compatible("rockchip,rk3566") || - of_machine_is_compatible("rockchip,rk3588")) + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK; if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) { @@ -3340,7 +3346,9 @@ static bool its_alloc_table_entry(struct its_node *its, if (!table[idx]) { gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) gfp_flags |= GFP_DMA32; page = alloc_pages_node(its->numa_node, gfp_flags, get_order(baser->psz)); @@ -3449,7 +3457,9 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; gfp_flags = GFP_KERNEL; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) { + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) { gfp_flags |= GFP_DMA32; itt = (void *)__get_free_pages(gfp_flags, get_order(sz)); } else { @@ -3471,7 +3481,8 @@ static struct its_device *its_create_device(struct its_node *its, u32 dev_id, kfree(dev); if (of_machine_is_compatible("rockchip,rk3568") || - of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) free_pages((unsigned long)itt, get_order(sz)); else kfree(itt); @@ -3515,7 +3526,8 @@ static void its_free_device(struct its_device *its_dev) kfree(its_dev->event_map.col_map); if (of_machine_is_compatible("rockchip,rk3568") || - of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz)); else kfree(its_dev->itt); @@ -5139,7 +5151,9 @@ static int __init its_probe_one(struct resource *res, its->numa_node = numa_node; gfp_flags = GFP_KERNEL | __GFP_ZERO; - if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) + if (of_machine_is_compatible("rockchip,rk3568") || + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) gfp_flags |= GFP_DMA32; page = alloc_pages_node(its->numa_node, gfp_flags, get_order(ITS_CMD_QUEUE_SZ)); @@ -5173,8 +5187,8 @@ static int __init its_probe_one(struct resource *res, tmp = gits_read_cbaser(its->base + GITS_CBASER); if (of_machine_is_compatible("rockchip,rk3568") || - of_machine_is_compatible("rockchip,rk3566") || - of_machine_is_compatible("rockchip,rk3588")) + of_machine_is_compatible("rockchip,rk3566") || + of_machine_is_compatible("rockchip,rk3588")) tmp &= ~GITS_CBASER_SHAREABILITY_MASK; if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 9f53bcce2f87..cb9aa5428350 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -54,21 +54,32 @@ #define OTPC_TIMEOUT 10000 +/* RK3588 Register */ +#define RK3588_OTPC_AUTO_CTRL 0x04 +#define RK3588_OTPC_AUTO_EN 0x08 +#define RK3588_OTPC_INT_ST 0x84 +#define RK3588_OTPC_DOUT0 0x20 +#define RK3588_NO_SECURE_OFFSET 0x300 +#define RK3588_NBYTES 4 +#define RK3588_BURST_NUM 1 +#define RK3588_BURST_SHIFT 8 +#define RK3588_ADDR_SHIFT 16 +#define RK3588_AUTO_EN BIT(0) +#define RK3588_RD_DONE BIT(1) + +struct rockchip_data { + int size; + const char * const *clks; + int num_clks; + nvmem_reg_read_t reg_read; +}; + struct rockchip_otp { struct device *dev; void __iomem *base; - struct clk_bulk_data *clks; - int num_clks; + struct clk_bulk_data *clks; struct reset_control *rst; -}; - -/* list of required clocks */ -static const char * const rockchip_otp_clocks[] = { - "otp", "apb_pclk", "phy", -}; - -struct rockchip_data { - int size; + const struct rockchip_data *data; }; static int rockchip_otp_reset(struct rockchip_otp *otp) @@ -92,18 +103,19 @@ static int rockchip_otp_reset(struct rockchip_otp *otp) return 0; } -static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag) +static int rockchip_otp_wait_status(struct rockchip_otp *otp, + unsigned int reg, u32 flag) { u32 status = 0; int ret; - ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status, + ret = readl_poll_timeout_atomic(otp->base + reg, status, (status & flag), 1, OTPC_TIMEOUT); if (ret) return ret; /* clean int status */ - writel(flag, otp->base + OTPC_INT_STATUS); + writel(flag, otp->base + reg); return 0; } @@ -125,36 +137,30 @@ static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable) writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL); - ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE); if (ret < 0) dev_err(otp->dev, "timeout during ecc_enable\n"); return ret; } -static int rockchip_otp_read(void *context, unsigned int offset, - void *val, size_t bytes) +static int px30_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) { struct rockchip_otp *otp = context; u8 *buf = val; - int ret = 0; - - ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks); - if (ret < 0) { - dev_err(otp->dev, "failed to prepare/enable clks\n"); - return ret; - } + int ret; ret = rockchip_otp_reset(otp); if (ret) { dev_err(otp->dev, "failed to reset otp phy\n"); - goto disable_clks; + return ret; } ret = rockchip_otp_ecc_enable(otp, false); if (ret < 0) { dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); - goto disable_clks; + return ret; } writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); @@ -164,7 +170,7 @@ static int rockchip_otp_read(void *context, unsigned int offset, otp->base + OTPC_USER_ADDR); writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, otp->base + OTPC_USER_ENABLE); - ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); if (ret < 0) { dev_err(otp->dev, "timeout during read setup\n"); goto read_end; @@ -174,8 +180,74 @@ static int rockchip_otp_read(void *context, unsigned int offset, read_end: writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); -disable_clks: - clk_bulk_disable_unprepare(otp->num_clks, otp->clks); + + return ret; +} + +static int rk3588_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct rockchip_otp *otp = context; + unsigned int addr_start, addr_end, addr_len; + int ret, i = 0; + u32 data; + u8 *buf; + + addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES; + addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES; + addr_len = addr_end - addr_start; + addr_start += RK3588_NO_SECURE_OFFSET; + + buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL); + if (!buf) + return -ENOMEM; + + while (addr_len--) { + writel((addr_start << RK3588_ADDR_SHIFT) | + (RK3588_BURST_NUM << RK3588_BURST_SHIFT), + otp->base + RK3588_OTPC_AUTO_CTRL); + writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN); + + ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST, + RK3588_RD_DONE); + if (ret < 0) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; + } + + data = readl(otp->base + RK3588_OTPC_DOUT0); + memcpy(&buf[i], &data, RK3588_NBYTES); + + i += RK3588_NBYTES; + addr_start++; + } + + memcpy(val, buf + offset % RK3588_NBYTES, bytes); + +read_end: + kfree(buf); + + return ret; +} + +static int rockchip_otp_read(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct rockchip_otp *otp = context; + int ret; + + if (!otp->data || !otp->data->reg_read) + return -EINVAL; + + ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks); + if (ret < 0) { + dev_err(otp->dev, "failed to prepare/enable clks\n"); + return ret; + } + + ret = otp->data->reg_read(context, offset, val, bytes); + + clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks); return ret; } @@ -189,18 +261,40 @@ static struct nvmem_config otp_config = { .reg_read = rockchip_otp_read, }; +static const char * const px30_otp_clocks[] = { + "otp", "apb_pclk", "phy", +}; + static const struct rockchip_data px30_data = { .size = 0x40, + .clks = px30_otp_clocks, + .num_clks = ARRAY_SIZE(px30_otp_clocks), + .reg_read = px30_otp_read, +}; + +static const char * const rk3588_otp_clocks[] = { + "otp", "apb_pclk", "phy", "arb", +}; + +static const struct rockchip_data rk3588_data = { + .size = 0x400, + .clks = rk3588_otp_clocks, + .num_clks = ARRAY_SIZE(rk3588_otp_clocks), + .reg_read = rk3588_otp_read, }; static const struct of_device_id rockchip_otp_match[] = { { .compatible = "rockchip,px30-otp", - .data = (void *)&px30_data, + .data = &px30_data, }, { .compatible = "rockchip,rk3308-otp", - .data = (void *)&px30_data, + .data = &px30_data, + }, + { + .compatible = "rockchip,rk3588-otp", + .data = &rk3588_data, }, { /* sentinel */ }, }; @@ -215,44 +309,47 @@ static int rockchip_otp_probe(struct platform_device *pdev) int ret, i; data = of_device_get_match_data(dev); - if (!data) { - dev_err(dev, "failed to get match data\n"); - return -EINVAL; - } + if (!data) + return dev_err_probe(dev, -EINVAL, "failed to get match data\n"); otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp), GFP_KERNEL); if (!otp) return -ENOMEM; + otp->data = data; otp->dev = dev; otp->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(otp->base)) - return PTR_ERR(otp->base); + return dev_err_probe(dev, PTR_ERR(otp->base), + "failed to ioremap resource\n"); - otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks); - otp->clks = devm_kcalloc(dev, otp->num_clks, - sizeof(*otp->clks), GFP_KERNEL); + otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks), + GFP_KERNEL); if (!otp->clks) return -ENOMEM; - for (i = 0; i < otp->num_clks; ++i) - otp->clks[i].id = rockchip_otp_clocks[i]; + for (i = 0; i < data->num_clks; ++i) + otp->clks[i].id = data->clks[i]; - ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks); + ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks); if (ret) - return ret; + return dev_err_probe(dev, ret, "failed to get clocks\n"); - otp->rst = devm_reset_control_get(dev, "phy"); + otp->rst = devm_reset_control_array_get_exclusive(dev); if (IS_ERR(otp->rst)) - return PTR_ERR(otp->rst); + return dev_err_probe(dev, PTR_ERR(otp->rst), + "failed to get resets\n"); otp_config.size = data->size; otp_config.priv = otp; otp_config.dev = dev; - nvmem = devm_nvmem_register(dev, &otp_config); - return PTR_ERR_OR_ZERO(nvmem); + nvmem = devm_nvmem_register(dev, &otp_config); + if (IS_ERR(nvmem)) + return dev_err_probe(dev, PTR_ERR(nvmem), + "failed to register nvmem device\n"); + return 0; } static struct platform_driver rockchip_otp_driver = { diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c index 7b213825fb5d..7b8b001e4f9e 100644 --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c @@ -63,6 +63,9 @@ #define PHYREG18 0x44 #define PHYREG18_PLL_LOOP 0x32 +#define PHYREG27 0x6C +#define PHYREG27_RX_TRIM_RK3588 0x4C + #define PHYREG32 0x7C #define PHYREG32_SSC_MASK GENMASK(7, 4) #define PHYREG32_SSC_DIR_SHIFT 4 @@ -114,7 +117,10 @@ struct rockchip_combphy_grfcfg { struct combphy_reg con2_for_sata; struct combphy_reg con3_for_sata; struct combphy_reg pipe_con0_for_sata; + struct combphy_reg pipe_con1_for_sata; struct combphy_reg pipe_xpcs_phy_ready; + struct combphy_reg pipe_pcie1l0_sel; + struct combphy_reg pipe_pcie1l1_sel; }; struct rockchip_combphy_cfg { @@ -559,11 +565,189 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { .combphy_cfg = rk3568_combphy_cfg, }; +static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv) +{ + const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; + unsigned long rate; + u32 val; + + switch (priv->type) { + case PHY_TYPE_PCIE: + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true); + break; + case PHY_TYPE_USB3: + /* Set SSC downward spread spectrum */ + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, + PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, + PHYREG32); + + /* Enable adaptive CTLE for USB3.0 Rx. */ + val = readl(priv->mmio + PHYREG15); + val |= PHYREG15_CTLE_EN; + writel(val, priv->mmio + PHYREG15); + + /* Set PLL KVCO fine tuning signals. */ + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, + PHYREG33); + + /* Enable controlling random jitter. */ + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + + /* Set PLL input clock divider 1/2. */ + rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, + PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, + PHYREG6); + + writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); + rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); + break; + case PHY_TYPE_SATA: + /* Enable adaptive CTLE for SATA Rx. */ + val = readl(priv->mmio + PHYREG15); + val |= PHYREG15_CTLE_EN; + writel(val, priv->mmio + PHYREG15); + /* + * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. + * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) + */ + val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; + val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; + writel(val, priv->mmio + PHYREG7); + + rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); + rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); + rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true); + break; + case PHY_TYPE_SGMII: + case PHY_TYPE_QSGMII: + default: + dev_err(priv->dev, "incompatible PHY type\n"); + return -EINVAL; + } + + rate = clk_get_rate(priv->refclk); + + switch (rate) { + case REF_CLOCK_24MHz: + if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { + /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ + val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; + rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, + val, PHYREG15); + + writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); + } + break; + + case REF_CLOCK_25MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); + break; + case REF_CLOCK_100MHz: + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); + if (priv->type == PHY_TYPE_PCIE) { + /* PLL KVCO fine tuning. */ + val = 4 << PHYREG33_PLL_KVCO_SHIFT; + rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, + val, PHYREG33); + + /* Enable controlling random jitter. */ + writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); + + /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */ + writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27); + + /* Set up su_trim: */ + writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); + } else if (priv->type == PHY_TYPE_SATA) { + /* downward spread spectrum +500ppm */ + val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; + val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; + rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); + } + break; + default: + dev_err(priv->dev, "Unsupported rate: %lu\n", rate); + return -EINVAL; + } + + if (priv->ext_refclk) { + rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { + val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; + val |= PHYREG13_CKRCV_AMP0; + rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); + + val = readl(priv->mmio + PHYREG14); + val |= PHYREG14_CKRCV_AMP1; + writel(val, priv->mmio + PHYREG14); + } + } + + if (priv->enable_ssc) { + val = readl(priv->mmio + PHYREG8); + val |= PHYREG8_SSC_EN; + writel(val, priv->mmio + PHYREG8); + } + + return 0; +} + +static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = { + /* pipe-phy-grf */ + .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, + .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, + .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, + .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, + .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, + .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, + .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, + .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, + .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, + .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, + .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, + .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, + .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, + .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, + .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, + .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 }, + .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 }, + .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 }, + .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 }, + /* pipe-grf */ + .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 }, + .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 }, + .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 }, + .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 }, +}; + +static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = { + .grfcfg = &rk3588_combphy_grfcfgs, + .combphy_cfg = rk3588_combphy_cfg, +}; + static const struct of_device_id rockchip_combphy_of_match[] = { { .compatible = "rockchip,rk3568-naneng-combphy", .data = &rk3568_combphy_cfgs, }, + { + .compatible = "rockchip,rk3588-naneng-combphy", + .data = &rk3588_combphy_cfgs, + }, { }, }; MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 819e059cde71..bd6aad05552f 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -40,15 +40,6 @@ enum tshut_polarity { }; /* - * The system has two Temperature Sensors. - * sensor0 is for CPU, and sensor1 is for GPU. - */ -enum sensor_id { - SENSOR_CPU = 0, - SENSOR_GPU, -}; - -/* * The conversion table has the adc value and temperature. * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) @@ -61,12 +52,6 @@ enum adc_sort_mode { #include "thermal_hwmon.h" /** - * The max sensors is two in rockchip SoCs. - * Two sensors: CPU and GPU sensor. - */ -#define SOC_MAX_SENSORS 2 - -/** * struct chip_tsadc_table - hold information about chip-specific differences * @id: conversion table * @length: size of conversion table @@ -82,7 +67,7 @@ struct chip_tsadc_table { /** * struct rockchip_tsadc_chip - hold the private data of tsadc chip - * @chn_id: array of sensor ids of chip corresponding to the channel + * @chn_offset: the channel offset of the first channel * @chn_num: the channel number of tsadc chip * @tshut_temp: the hardware-controlled shutdown temperature value * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) @@ -98,7 +83,7 @@ struct chip_tsadc_table { */ struct rockchip_tsadc_chip { /* The sensor id of chip correspond to the ADC channel */ - int chn_id[SOC_MAX_SENSORS]; + int chn_offset; int chn_num; /* The hardware-controlled tshut property */ @@ -156,7 +141,7 @@ struct rockchip_thermal_data { struct platform_device *pdev; struct reset_control *reset; - struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; + struct rockchip_thermal_sensor *sensors; struct clk *clk; struct clk *pclk; @@ -169,7 +154,7 @@ struct rockchip_thermal_data { enum tshut_polarity tshut_polarity; }; -/** +/* * TSADC Sensor Register description: * * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. @@ -180,29 +165,49 @@ struct rockchip_thermal_data { #define TSADCV2_AUTO_CON 0x04 #define TSADCV2_INT_EN 0x08 #define TSADCV2_INT_PD 0x0c +#define TSADCV3_AUTO_SRC_CON 0x0c +#define TSADCV3_HT_INT_EN 0x14 +#define TSADCV3_HSHUT_GPIO_INT_EN 0x18 +#define TSADCV3_HSHUT_CRU_INT_EN 0x1c +#define TSADCV3_INT_PD 0x24 +#define TSADCV3_HSHUT_PD 0x28 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) +#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04) +#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04) +#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04) #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 +#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c +#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150 #define TSADCV2_AUTO_PERIOD 0x68 #define TSADCV2_AUTO_PERIOD_HT 0x6c +#define TSADCV3_AUTO_PERIOD 0x154 +#define TSADCV3_AUTO_PERIOD_HT 0x158 #define TSADCV2_AUTO_EN BIT(0) +#define TSADCV2_AUTO_EN_MASK BIT(16) #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) +#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn) +#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn) #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) +#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24) #define TSADCV3_AUTO_Q_SEL_EN BIT(1) #define TSADCV2_INT_SRC_EN(chn) BIT(chn) +#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn)) #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) +#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff #define TSADCV2_DATA_MASK 0xfff #define TSADCV3_DATA_MASK 0x3ff +#define TSADCV4_DATA_MASK 0x1ff #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 @@ -213,6 +218,8 @@ struct rockchip_thermal_data { #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */ +#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */ #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ @@ -229,6 +236,12 @@ struct rockchip_thermal_data { #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) +#define RK3588_GRF0_TSADC_CON 0x0100 + +#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0) +#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10) +#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12) + #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) #define GRF_TSADC_VCM_EN_L (0x10001 << 7) @@ -523,6 +536,15 @@ static const struct tsadc_table rk3568_code_table[] = { {TSADCV2_DATA_MASK, 125000}, }; +static const struct tsadc_table rk3588_code_table[] = { + {0, -40000}, + {215, -40000}, + {285, 25000}, + {350, 85000}, + {395, 125000}, + {TSADCV4_DATA_MASK, 125000}, +}; + static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, int temp) { @@ -793,6 +815,25 @@ static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, } } +static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs, + enum tshut_polarity tshut_polarity) +{ + writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD); + writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME, + regs + TSADCV3_AUTO_PERIOD_HT); + writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_INT_DEBOUNCE); + writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, + regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE); + if (tshut_polarity == TSHUT_HIGH_ACTIVE) + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH | + TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); + else + writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK, + regs + TSADCV2_AUTO_CON); +} + static void rk_tsadcv2_irq_ack(void __iomem *regs) { u32 val; @@ -809,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __iomem *regs) writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); } +static void rk_tsadcv4_irq_ack(void __iomem *regs) +{ + u32 val; + + val = readl_relaxed(regs + TSADCV3_INT_PD); + writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD); + val = readl_relaxed(regs + TSADCV3_HSHUT_PD); + writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, + regs + TSADCV3_HSHUT_PD); +} + static void rk_tsadcv2_control(void __iomem *regs, bool enable) { u32 val; @@ -844,6 +896,18 @@ static void rk_tsadcv3_control(void __iomem *regs, bool enable) writel_relaxed(val, regs + TSADCV2_AUTO_CON); } +static void rk_tsadcv4_control(void __iomem *regs, bool enable) +{ + u32 val; + + if (enable) + val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK; + else + val = TSADCV2_AUTO_EN_MASK; + + writel_relaxed(val, regs + TSADCV2_AUTO_CON); +} + static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int *temp) { @@ -854,6 +918,16 @@ static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, return rk_tsadcv2_code_to_temp(table, val, temp); } +static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int *temp) +{ + u32 val; + + val = readl_relaxed(regs + TSADCV3_DATA(chn)); + + return rk_tsadcv2_code_to_temp(table, val, temp); +} + static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -888,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, return 0; } +static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 alarm_value; + + /* + * In some cases, some sensors didn't need the trip points, the + * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm + * in the end, ignore this case and disable the high temperature + * interrupt. + */ + if (temp == INT_MAX) { + writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; + } + /* Make sure the value is valid */ + alarm_value = rk_tsadcv2_temp_to_code(table, temp); + if (alarm_value == table->data_mask) + return -ERANGE; + writel_relaxed(alarm_value & table->data_mask, + regs + TSADCV3_COMP_INT(chn)); + writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn), + regs + TSADCV3_HT_INT_EN); + return 0; +} + static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, int chn, void __iomem *regs, int temp) { @@ -907,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, return 0; } +static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table, + int chn, void __iomem *regs, int temp) +{ + u32 tshut_value; + + /* Make sure the value is valid */ + tshut_value = rk_tsadcv2_temp_to_code(table, temp); + if (tshut_value == table->data_mask) + return -ERANGE; + + writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn)); + + /* TSHUT will be valid */ + writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn), + regs + TSADCV3_AUTO_SRC_CON); + + return 0; +} + static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, enum tshut_mode mode) { @@ -924,9 +1044,25 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, writel_relaxed(val, regs + TSADCV2_INT_EN); } +static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, + enum tshut_mode mode) +{ + u32 val_gpio, val_cru; + + if (mode == TSHUT_MODE_GPIO) { + val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_cru = TSADCV2_INT_SRC_EN_MASK(chn); + } else { + val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn); + val_gpio = TSADCV2_INT_SRC_EN_MASK(chn); + } + writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); + writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); +} + static const struct rockchip_tsadc_chip px30_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* 2 channels for tsadc */ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -949,7 +1085,8 @@ static const struct rockchip_tsadc_chip px30_tsadc_data = { }; static const struct rockchip_tsadc_chip rv1108_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channel for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -973,7 +1110,8 @@ static const struct rockchip_tsadc_chip rv1108_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3228_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channel for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -997,8 +1135,8 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3288_tsadc_data = { - .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ - .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ + /* cpu, gpu */ + .chn_offset = 1, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1022,7 +1160,8 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3328_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + /* cpu */ + .chn_offset = 0, .chn_num = 1, /* one channels for tsadc */ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ @@ -1045,8 +1184,8 @@ static const struct rockchip_tsadc_chip rk3328_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3366_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1070,8 +1209,8 @@ static const struct rockchip_tsadc_chip rk3366_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3368_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1095,8 +1234,8 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3399_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1120,8 +1259,8 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_data = { }; static const struct rockchip_tsadc_chip rk3568_tsadc_data = { - .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ - .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + /* cpu, gpu */ + .chn_offset = 0, .chn_num = 2, /* two channels for tsadc */ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ @@ -1144,6 +1283,28 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3588_tsadc_data = { + /* top, big_core0, big_core1, little_core, center, gpu, npu */ + .chn_offset = 0, + .chn_num = 7, /* seven channels for tsadc */ + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + .initialize = rk_tsadcv8_initialize, + .irq_ack = rk_tsadcv4_irq_ack, + .control = rk_tsadcv4_control, + .get_temp = rk_tsadcv4_get_temp, + .set_alarm_temp = rk_tsadcv3_alarm_temp, + .set_tshut_temp = rk_tsadcv3_tshut_temp, + .set_tshut_mode = rk_tsadcv3_tshut_mode, + .table = { + .id = rk3588_code_table, + .length = ARRAY_SIZE(rk3588_code_table), + .data_mask = TSADCV4_DATA_MASK, + .mode = ADC_INCREMENT, + }, +}; + static const struct of_device_id of_rockchip_thermal_match[] = { { .compatible = "rockchip,px30-tsadc", .data = (void *)&px30_tsadc_data, @@ -1180,6 +1341,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3568-tsadc", .data = (void *)&rk3568_tsadc_data, }, + { + .compatible = "rockchip,rk3588-tsadc", + .data = (void *)&rk3588_tsadc_data, + }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); @@ -1233,9 +1398,6 @@ static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_te retval = tsadc->get_temp(&tsadc->table, sensor->id, thermal->regs, out_temp); - dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", - sensor->id, *out_temp, retval); - return retval; } @@ -1339,7 +1501,7 @@ rockchip_thermal_register_sensor(struct platform_device *pdev, } /** - * Reset TSADC Controller, reset all tsadc registers. + * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers. * @reset: the reset controller of tsadc */ static void rockchip_thermal_reset_controller(struct reset_control *reset) @@ -1353,16 +1515,10 @@ static int rockchip_thermal_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct rockchip_thermal_data *thermal; - const struct of_device_id *match; - struct resource *res; int irq; int i; int error; - match = of_match_node(of_rockchip_thermal_match, np); - if (!match) - return -ENXIO; - irq = platform_get_irq(pdev, 0); if (irq < 0) return -EINVAL; @@ -1374,58 +1530,40 @@ static int rockchip_thermal_probe(struct platform_device *pdev) thermal->pdev = pdev; - thermal->chip = (const struct rockchip_tsadc_chip *)match->data; + thermal->chip = device_get_match_data(&pdev->dev); if (!thermal->chip) return -EINVAL; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - thermal->regs = devm_ioremap_resource(&pdev->dev, res); + thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num, + sizeof(*thermal->sensors), GFP_KERNEL); + if (!thermal->sensors) + return -ENOMEM; + + thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(thermal->regs)) return PTR_ERR(thermal->regs); - thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); - if (IS_ERR(thermal->reset)) { - error = PTR_ERR(thermal->reset); - dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); - return error; - } - - thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); - if (IS_ERR(thermal->clk)) { - error = PTR_ERR(thermal->clk); - dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); - return error; - } - - thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); - if (IS_ERR(thermal->pclk)) { - error = PTR_ERR(thermal->pclk); - dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", - error); - return error; - } + thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev); + if (IS_ERR(thermal->reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), + "failed to get tsadc reset.\n"); - error = clk_prepare_enable(thermal->clk); - if (error) { - dev_err(&pdev->dev, "failed to enable converter clock: %d\n", - error); - return error; - } + thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); + if (IS_ERR(thermal->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk), + "failed to get tsadc clock.\n"); - error = clk_prepare_enable(thermal->pclk); - if (error) { - dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); - goto err_disable_clk; - } + thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); + if (IS_ERR(thermal->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk), + "failed to get apb_pclk clock.\n"); rockchip_thermal_reset_controller(thermal->reset); error = rockchip_configure_from_dt(&pdev->dev, np, thermal); - if (error) { - dev_err(&pdev->dev, "failed to parse device tree data: %d\n", - error); - goto err_disable_pclk; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to parse device tree data\n"); thermal->chip->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); @@ -1433,30 +1571,24 @@ static int rockchip_thermal_probe(struct platform_device *pdev) for (i = 0; i < thermal->chip->chn_num; i++) { error = rockchip_thermal_register_sensor(pdev, thermal, &thermal->sensors[i], - thermal->chip->chn_id[i]); - if (error) { - dev_err(&pdev->dev, - "failed to register sensor[%d] : error = %d\n", - i, error); - goto err_disable_pclk; - } + thermal->chip->chn_offset + i); + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to register sensor[%d].\n", i); } error = devm_request_threaded_irq(&pdev->dev, irq, NULL, &rockchip_thermal_alarm_irq_thread, IRQF_ONESHOT, "rockchip_thermal", thermal); - if (error) { - dev_err(&pdev->dev, - "failed to request tsadc irq: %d\n", error); - goto err_disable_pclk; - } + if (error) + return dev_err_probe(&pdev->dev, error, + "failed to request tsadc irq.\n"); thermal->chip->control(thermal->regs, true); for (i = 0; i < thermal->chip->chn_num; i++) { rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); - thermal->sensors[i].tzd->tzp->no_hwmon = false; error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd); if (error) dev_warn(&pdev->dev, @@ -1467,13 +1599,6 @@ static int rockchip_thermal_probe(struct platform_device *pdev) platform_set_drvdata(pdev, thermal); return 0; - -err_disable_pclk: - clk_disable_unprepare(thermal->pclk); -err_disable_clk: - clk_disable_unprepare(thermal->clk); - - return error; } static int rockchip_thermal_remove(struct platform_device *pdev) @@ -1490,9 +1615,6 @@ static int rockchip_thermal_remove(struct platform_device *pdev) thermal->chip->control(thermal->regs, false); - clk_disable_unprepare(thermal->pclk); - clk_disable_unprepare(thermal->clk); - return 0; } diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig index 42f76bc0fb02..f98a2fa85edd 100644 --- a/sound/soc/rockchip/Kconfig +++ b/sound/soc/rockchip/Kconfig @@ -13,7 +13,7 @@ config SND_SOC_ROCKCHIP_I2S select SND_SOC_GENERIC_DMAENGINE_PCM help Say Y or M if you want to add support for I2S driver for - Rockchip I2S device. The device supports upto maximum of + Rockchip I2S device. The device supports up to maximum of 8 channels each for play and record. config SND_SOC_ROCKCHIP_I2S_TDM diff --git a/sound/soc/rockchip/rk3399_gru_sound.c b/sound/soc/rockchip/rk3399_gru_sound.c index 2540b9ba37c8..5e52e9d60d44 100644 --- a/sound/soc/rockchip/rk3399_gru_sound.c +++ b/sound/soc/rockchip/rk3399_gru_sound.c @@ -21,7 +21,6 @@ #include <sound/soc.h> #include "rockchip_i2s.h" #include "../codecs/da7219.h" -#include "../codecs/da7219-aad.h" #include "../codecs/rt5514.h" #define DRV_NAME "rk3399-gru-sound" @@ -226,7 +225,7 @@ static int rockchip_sound_da7219_init(struct snd_soc_pcm_runtime *rtd) snd_jack_set_key( rockchip_sound_jack.jack, SND_JACK_BTN_3, KEY_VOICECOMMAND); - da7219_aad_jack_det(component, &rockchip_sound_jack); + snd_soc_component_set_jack(component, &rockchip_sound_jack, NULL); return 0; } diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c index a8758ad68442..575a0b9b01e9 100644 --- a/sound/soc/rockchip/rockchip_i2s.c +++ b/sound/soc/rockchip/rockchip_i2s.c @@ -659,6 +659,7 @@ static const struct of_device_id rockchip_i2s_match[] __maybe_unused = { { .compatible = "rockchip,rk3366-i2s", }, { .compatible = "rockchip,rk3368-i2s", }, { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, + { .compatible = "rockchip,rk3588-i2s", }, { .compatible = "rockchip,rv1126-i2s", }, {}, }; @@ -850,7 +851,7 @@ err_clk: return ret; } -static int rockchip_i2s_remove(struct platform_device *pdev) +static void rockchip_i2s_remove(struct platform_device *pdev) { struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); @@ -859,8 +860,6 @@ static int rockchip_i2s_remove(struct platform_device *pdev) i2s_runtime_suspend(&pdev->dev); clk_disable_unprepare(i2s->hclk); - - return 0; } static const struct dev_pm_ops rockchip_i2s_pm_ops = { @@ -870,7 +869,7 @@ static const struct dev_pm_ops rockchip_i2s_pm_ops = { static struct platform_driver rockchip_i2s_driver = { .probe = rockchip_i2s_probe, - .remove = rockchip_i2s_remove, + .remove_new = rockchip_i2s_remove, .driver = { .name = DRV_NAME, .of_match_table = of_match_ptr(rockchip_i2s_match), diff --git a/sound/soc/rockchip/rockchip_i2s_tdm.c b/sound/soc/rockchip/rockchip_i2s_tdm.c index 2550bd2a5e78..166257c6ae14 100644 --- a/sound/soc/rockchip/rockchip_i2s_tdm.c +++ b/sound/soc/rockchip/rockchip_i2s_tdm.c @@ -756,6 +756,12 @@ static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream, if (!i2s_tdm->io_multiplex) return 0; + if (IS_ERR_OR_NULL(i2s_tdm->grf)) { + dev_err(i2s_tdm->dev, + "io multiplex not supported for this device\n"); + return -EINVAL; + } + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { struct snd_pcm_str *playback_str = &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; @@ -1064,9 +1070,9 @@ static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai) struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); if (i2s_tdm->has_capture) - dai->capture_dma_data = &i2s_tdm->capture_dma_data; + snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data); if (i2s_tdm->has_playback) - dai->playback_dma_data = &i2s_tdm->playback_dma_data; + snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data); if (i2s_tdm->mclk_calibrate) snd_soc_add_dai_controls(dai, &rockchip_i2s_tdm_compensation_control, 1); @@ -1222,6 +1228,12 @@ static int common_soc_init(struct device *dev, u32 addr) if (trcm == TRCM_TXRX) return 0; + if (IS_ERR_OR_NULL(i2s_tdm->grf)) { + dev_err(i2s_tdm->dev, + "no grf present but non-txrx TRCM specified\n"); + return -EINVAL; + } + for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { if (addr != configs[i].addr) continue; @@ -1306,6 +1318,7 @@ static const struct of_device_id rockchip_i2s_tdm_match[] = { { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, + { .compatible = "rockchip,rk3588-i2s-tdm" }, { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, {}, }; @@ -1544,7 +1557,7 @@ static int rockchip_i2s_tdm_probe(struct platform_device *pdev) i2s_tdm->dev = &pdev->dev; of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev); - if (!of_id || !of_id->data) + if (!of_id) return -EINVAL; spin_lock_init(&i2s_tdm->lock); @@ -1568,10 +1581,6 @@ static int rockchip_i2s_tdm_probe(struct platform_device *pdev) return ret; i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); - if (IS_ERR(i2s_tdm->grf)) - return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf), - "Error in rockchip,grf\n"); - i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "tx-m"); if (IS_ERR(i2s_tdm->tx_reset)) { diff --git a/sound/soc/rockchip/rockchip_pdm.c b/sound/soc/rockchip/rockchip_pdm.c index 5b1e47bdc376..52f9aae60be8 100644 --- a/sound/soc/rockchip/rockchip_pdm.c +++ b/sound/soc/rockchip/rockchip_pdm.c @@ -373,7 +373,7 @@ static int rockchip_pdm_dai_probe(struct snd_soc_dai *dai) { struct rk_pdm_dev *pdm = to_info(dai); - dai->capture_dma_data = &pdm->capture_dma_data; + snd_soc_dai_dma_data_set_capture(dai, &pdm->capture_dma_data); return 0; } @@ -661,7 +661,7 @@ err_pm_disable: return ret; } -static int rockchip_pdm_remove(struct platform_device *pdev) +static void rockchip_pdm_remove(struct platform_device *pdev) { struct rk_pdm_dev *pdm = dev_get_drvdata(&pdev->dev); @@ -671,8 +671,6 @@ static int rockchip_pdm_remove(struct platform_device *pdev) clk_disable_unprepare(pdm->clk); clk_disable_unprepare(pdm->hclk); - - return 0; } #ifdef CONFIG_PM_SLEEP @@ -710,7 +708,7 @@ static const struct dev_pm_ops rockchip_pdm_pm_ops = { static struct platform_driver rockchip_pdm_driver = { .probe = rockchip_pdm_probe, - .remove = rockchip_pdm_remove, + .remove_new = rockchip_pdm_remove, .driver = { .name = "rockchip-pdm", .of_match_table = of_match_ptr(rockchip_pdm_match), diff --git a/sound/soc/rockchip/rockchip_rt5645.c b/sound/soc/rockchip/rockchip_rt5645.c index d07cc5c813f2..e73a342b7953 100644 --- a/sound/soc/rockchip/rockchip_rt5645.c +++ b/sound/soc/rockchip/rockchip_rt5645.c @@ -206,14 +206,12 @@ put_codec_of_node: return ret; } -static int snd_rk_mc_remove(struct platform_device *pdev) +static void snd_rk_mc_remove(struct platform_device *pdev) { of_node_put(rk_dailink.cpus->of_node); rk_dailink.cpus->of_node = NULL; of_node_put(rk_dailink.codecs->of_node); rk_dailink.codecs->of_node = NULL; - - return 0; } static const struct of_device_id rockchip_rt5645_of_match[] = { @@ -225,7 +223,7 @@ MODULE_DEVICE_TABLE(of, rockchip_rt5645_of_match); static struct platform_driver snd_rk_mc_driver = { .probe = snd_rk_mc_probe, - .remove = snd_rk_mc_remove, + .remove_new = snd_rk_mc_remove, .driver = { .name = DRV_NAME, .pm = &snd_soc_pm_ops, |