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authorLinus Torvalds <torvalds@linux-foundation.org>2022-04-02 05:19:56 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2022-04-02 05:19:56 +0300
commit1fdff407028c6064be96343f4bac31a0e679cbd0 (patch)
tree787561f0bea44fbfba7fb640a33a77390641535b
parent8467b0ed6ce37f7e3f87aa3826627dc9cc55ecb2 (diff)
parent2524257bce43610f5ec14feccbacf7a103cae94a (diff)
downloadlinux-1fdff407028c6064be96343f4bac31a0e679cbd0.tar.xz
Merge tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fix from Palmer Dabbelt: - Fix the RISC-V section of the generic CPU idle bindings to comply with the recently tightened DT schema. * tag 'riscv-for-linus-5.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: dt-bindings: Fix phandle-array issues in the idle-states bindings
-rw-r--r--Documentation/devicetree/bindings/cpu/idle-states.yaml16
-rw-r--r--Documentation/devicetree/bindings/riscv/cpus.yaml2
2 files changed, 10 insertions, 8 deletions
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml
index 5daa219ceb7b..fa4d4142ac93 100644
--- a/Documentation/devicetree/bindings/cpu/idle-states.yaml
+++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml
@@ -719,8 +719,8 @@ examples:
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
@@ -735,8 +735,8 @@ examples:
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
@@ -751,8 +751,8 @@ examples:
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
@@ -767,8 +767,8 @@ examples:
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f62f646bc695..d632ac76532e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -101,6 +101,8 @@ properties:
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).