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authorStafford Horne <shorne@gmail.com>2022-06-15 02:54:26 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-07-21 21:42:47 +0300
commit08fb5e4f79fca0cd99b673b6c3cf1ec8cb324f1b (patch)
tree73557036998d4827fad985d95de56a07b5bd31fd
parent37f99b368e5cc7551a8655dddae95852a39d961a (diff)
downloadlinux-08fb5e4f79fca0cd99b673b6c3cf1ec8cb324f1b.tar.xz
irqchip: or1k-pic: Undefine mask_ack for level triggered hardware
[ Upstream commit 8520501346ed8d1c4a6dfa751cb57328a9c843f1 ] The mask_ack operation clears the interrupt by writing to the PICSR register. This we don't want for level triggered interrupt because it does not actually clear the interrupt on the source hardware. This was causing issues in qemu with multi core setups where interrupts would continue to fire even though they had been cleared in PICSR. Just remove the mask_ack operation. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
-rw-r--r--drivers/irqchip/irq-or1k-pic.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c
index dd9d5d12fea2..05931fdedbb9 100644
--- a/drivers/irqchip/irq-or1k-pic.c
+++ b/drivers/irqchip/irq-or1k-pic.c
@@ -70,7 +70,6 @@ static struct or1k_pic_dev or1k_pic_level = {
.name = "or1k-PIC-level",
.irq_unmask = or1k_pic_unmask,
.irq_mask = or1k_pic_mask,
- .irq_mask_ack = or1k_pic_mask_ack,
},
.handle = handle_level_irq,
.flags = IRQ_LEVEL | IRQ_NOPROBE,