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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2020-09-14 19:05:00 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-09-23 13:11:00 +0300 |
| commit | 4cf1b96a36d5b26dadca1e2ab0f85180259bab75 (patch) | |
| tree | adcab96669c402e36ca94400fa8fa07b2cf83f66 | |
| parent | c5dbe21652cd7a0ab49274d79077a8655255611a (diff) | |
| download | linux-4cf1b96a36d5b26dadca1e2ab0f85180259bab75.tar.xz | |
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a830a9701e50..cc8c8d22afaf 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -852,6 +852,7 @@ config SNI_RM select I8253 select I8259 select ISA + select MIPS_L1_CACHE_SHIFT_6 select SWAP_IO_SPACE if CPU_BIG_ENDIAN select SYS_HAS_CPU_R4X00 select SYS_HAS_CPU_R5000 |