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authorAlexandre Belloni <alexandre.belloni@bootlin.com>2021-02-03 12:03:20 +0300
committerArnd Bergmann <arnd@arndb.de>2021-02-03 13:15:08 +0300
commit5638159f6d93b99ec9743ac7f65563fca3cf413d (patch)
treeb41be46d34ca8efc0e5d4ff058b0a83aa6232c27
parent62c31574cdb770c78f67e7aa6e0b0244ad122901 (diff)
downloadlinux-5638159f6d93b99ec9743ac7f65563fca3cf413d.tar.xz
ARM: dts: lpc32xx: Revert set default clock rate of HCLK PLL
This reverts commit c17e9377aa81664d94b4f2102559fcf2a01ec8e7. The lpc32xx clock driver is not able to actually change the PLL rate as this would require reparenting ARM_CLK, DDRAM_CLK, PERIPH_CLK to SYSCLK, then stop the PLL, update the register, restart the PLL and wait for the PLL to lock and finally reparent ARM_CLK, DDRAM_CLK, PERIPH_CLK to HCLK PLL. Currently, the HCLK driver simply updates the registers but this has no real effect and all the clock rate calculation end up being wrong. This is especially annoying for the peripheral (e.g. UARTs, I2C, SPI). Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Tested-by: Gregory CLEMENT <gregory.clement@bootlin.com> Link: https://lore.kernel.org/r/20210203090320.GA3760268@piout.net' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3a5cfb0ddb20..c87066d6c995 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -326,9 +326,6 @@
clocks = <&xtal_32k>, <&xtal>;
clock-names = "xtal_32k", "xtal";
-
- assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
- assigned-clock-rates = <208000000>;
};
};